diff options
Diffstat (limited to 'meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch')
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch | 752 |
1 files changed, 752 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch b/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch new file mode 100644 index 0000000000..5ca12a6848 --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-4.7/ppc_with_cpu.patch | |||
@@ -0,0 +1,752 @@ | |||
1 | Upstream-Status: Backport | ||
2 | Signed-off-by: Khem Raj <raj.khem@gmail.com> | ||
3 | |||
4 | From 7630308303ea21c318bd57c35590fc4f249a30d8 Mon Sep 17 00:00:00 2001 | ||
5 | From: hainque <hainque@138bc75d-0d04-0410-961f-82ee72b054a4> | ||
6 | Date: Wed, 16 May 2012 08:43:41 +0000 | ||
7 | Subject: [PATCH] * config/rs6000/rs6000-opts.h (enum processor_type): | ||
8 | Add PROCESSOR_PPC8548. * | ||
9 | config/rs6000/rs6000-cpus.def: Reference it for cpu="8548". | ||
10 | * config/rs6000/rs6000.md (cpu attribute | ||
11 | definition): Add ppc8548. * config/rs6000/8540.md: | ||
12 | indicate that the units/patterns apply to ppc8548 | ||
13 | as well. | ||
14 | |||
15 | * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename | ||
16 | default_cpu into implicit_cpu, conveying what --with-cpu was passed at | ||
17 | configure time. Treat implicit_cpu as have_CPU. Pick defaults for SPE | ||
18 | related flags, check that what is queried is supported by the selected | ||
19 | configuration. Rework the single/double_float and MASK_STRING resets to | ||
20 | hit for all the E500 cores (854x + E500MC variants). Select the ppc8540 | ||
21 | costs for PROCESSOR_PPC8548 as well. | ||
22 | (rs6000_issue_rate): case CPU_PPC8548 together with CPU_PPC8540. | ||
23 | (rs6000_use_sched_lookahead): Likewise, rewriting function as a case | ||
24 | statement instead of a sequence of ifs. | ||
25 | |||
26 | * config/rs6000/rs6000.h (TARGET_E500): Remove. | ||
27 | (TARGET_NO_LWSYNC): Adjust accordingly. | ||
28 | * config/rs6000/e500.h (TARGET_E500): Remove. | ||
29 | (CHECK_E500_OPTIONS): Adjust accordingly. | ||
30 | * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Remove. | ||
31 | (TARGET_DEFAULT): Reformat definition to match the one in linuxspe.h. | ||
32 | * config/rs6000/linuxspe.h: Likewise. | ||
33 | * config/rs6000/vxworks.h: Remove bogus TARGET_E500 overrides and | ||
34 | superfluous comments. | ||
35 | * config/rs6000/e500-double.h: Remove. | ||
36 | |||
37 | * config.gcc (pick a default with_cpu): For powerpc*-*-*spe*, | ||
38 | default to with_cpu=8548 if --enable-e500-double, and to 8540 | ||
39 | otherwise. | ||
40 | (set misc flags section): For powerpc*|rs6000*, remove inclusion | ||
41 | of e500-double.h for --enable-e500-double. | ||
42 | |||
43 | |||
44 | |||
45 | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@187581 138bc75d-0d04-0410-961f-82ee72b054a4 | ||
46 | --- | ||
47 | gcc/ChangeLog | 37 +++++++++ | ||
48 | gcc/config.gcc | 12 +-- | ||
49 | gcc/config/rs6000/8540.md | 50 ++++++------ | ||
50 | gcc/config/rs6000/e500-double.h | 24 ------ | ||
51 | gcc/config/rs6000/e500.h | 10 +-- | ||
52 | gcc/config/rs6000/eabispe.h | 17 +--- | ||
53 | gcc/config/rs6000/linuxspe.h | 16 +--- | ||
54 | gcc/config/rs6000/rs6000-cpus.def | 3 +- | ||
55 | gcc/config/rs6000/rs6000-opts.h | 1 + | ||
56 | gcc/config/rs6000/rs6000.c | 155 +++++++++++++++++++++++-------------- | ||
57 | gcc/config/rs6000/rs6000.h | 7 +- | ||
58 | gcc/config/rs6000/rs6000.md | 2 +- | ||
59 | gcc/config/rs6000/rtems.h | 14 ---- | ||
60 | gcc/config/rs6000/vxworks.h | 11 --- | ||
61 | 14 files changed, 178 insertions(+), 181 deletions(-) | ||
62 | |||
63 | Index: gcc-4_7-branch/gcc/config.gcc | ||
64 | =================================================================== | ||
65 | --- gcc-4_7-branch.orig/gcc/config.gcc 2012-07-06 19:43:53.000000000 -0700 | ||
66 | +++ gcc-4_7-branch/gcc/config.gcc 2012-07-06 19:44:38.000000000 -0700 | ||
67 | @@ -2876,6 +2876,13 @@ | ||
68 | mips*-*-vxworks) | ||
69 | with_arch=mips2 | ||
70 | ;; | ||
71 | + powerpc*-*-*spe*) | ||
72 | + if test x$enable_e500_double = xyes; then | ||
73 | + with_cpu=8548 | ||
74 | + else | ||
75 | + with_cpu=8540 | ||
76 | + fi | ||
77 | + ;; | ||
78 | sparc-leon*-*) | ||
79 | with_cpu=v8; | ||
80 | ;; | ||
81 | @@ -3564,11 +3571,6 @@ | ||
82 | c_target_objs="${c_target_objs} rs6000-c.o" | ||
83 | cxx_target_objs="${cxx_target_objs} rs6000-c.o" | ||
84 | tmake_file="rs6000/t-rs6000 ${tmake_file}" | ||
85 | - | ||
86 | - if test x$enable_e500_double = xyes | ||
87 | - then | ||
88 | - tm_file="$tm_file rs6000/e500-double.h" | ||
89 | - fi | ||
90 | ;; | ||
91 | |||
92 | sh[123456ble]*-*-* | sh-*-*) | ||
93 | Index: gcc-4_7-branch/gcc/config/rs6000/8540.md | ||
94 | =================================================================== | ||
95 | --- gcc-4_7-branch.orig/gcc/config/rs6000/8540.md 2012-07-05 23:49:07.000000000 -0700 | ||
96 | +++ gcc-4_7-branch/gcc/config/rs6000/8540.md 2012-07-06 19:44:38.466780001 -0700 | ||
97 | @@ -87,18 +87,18 @@ | ||
98 | (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ | ||
99 | delayed_compare,var_delayed_compare,fast_compare,\ | ||
100 | shift,trap,var_shift_rotate,cntlz,exts,isel") | ||
101 | - (eq_attr "cpu" "ppc8540")) | ||
102 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
103 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
104 | |||
105 | (define_insn_reservation "ppc8540_two" 1 | ||
106 | (and (eq_attr "type" "two") | ||
107 | - (eq_attr "cpu" "ppc8540")) | ||
108 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
109 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | ||
110 | ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
111 | |||
112 | (define_insn_reservation "ppc8540_three" 1 | ||
113 | (and (eq_attr "type" "three") | ||
114 | - (eq_attr "cpu" "ppc8540")) | ||
115 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
116 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | ||
117 | ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | ||
118 | ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
119 | @@ -106,13 +106,13 @@ | ||
120 | ;; Branch. Actually this latency time is not used by the scheduler. | ||
121 | (define_insn_reservation "ppc8540_branch" 1 | ||
122 | (and (eq_attr "type" "jmpreg,branch,isync") | ||
123 | - (eq_attr "cpu" "ppc8540")) | ||
124 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
125 | "ppc8540_decode,ppc8540_bu,ppc8540_retire") | ||
126 | |||
127 | ;; Multiply | ||
128 | (define_insn_reservation "ppc8540_multiply" 4 | ||
129 | (and (eq_attr "type" "imul,imul2,imul3,imul_compare") | ||
130 | - (eq_attr "cpu" "ppc8540")) | ||
131 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
132 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | ||
133 | ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | ||
134 | |||
135 | @@ -122,57 +122,57 @@ | ||
136 | ;; time. | ||
137 | (define_insn_reservation "ppc8540_divide" 14 | ||
138 | (and (eq_attr "type" "idiv") | ||
139 | - (eq_attr "cpu" "ppc8540")) | ||
140 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
141 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | ||
142 | ppc8540_mu_div*13") | ||
143 | |||
144 | ;; CR logical | ||
145 | (define_insn_reservation "ppc8540_cr_logical" 1 | ||
146 | (and (eq_attr "type" "cr_logical,delayed_cr") | ||
147 | - (eq_attr "cpu" "ppc8540")) | ||
148 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
149 | "ppc8540_decode,ppc8540_bu,ppc8540_retire") | ||
150 | |||
151 | ;; Mfcr | ||
152 | (define_insn_reservation "ppc8540_mfcr" 1 | ||
153 | (and (eq_attr "type" "mfcr") | ||
154 | - (eq_attr "cpu" "ppc8540")) | ||
155 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
156 | "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | ||
157 | |||
158 | ;; Mtcrf | ||
159 | (define_insn_reservation "ppc8540_mtcrf" 1 | ||
160 | (and (eq_attr "type" "mtcr") | ||
161 | - (eq_attr "cpu" "ppc8540")) | ||
162 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
163 | "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | ||
164 | |||
165 | ;; Mtjmpr | ||
166 | (define_insn_reservation "ppc8540_mtjmpr" 1 | ||
167 | (and (eq_attr "type" "mtjmpr,mfjmpr") | ||
168 | - (eq_attr "cpu" "ppc8540")) | ||
169 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
170 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
171 | |||
172 | ;; Loads | ||
173 | (define_insn_reservation "ppc8540_load" 3 | ||
174 | (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | ||
175 | load_l,sync") | ||
176 | - (eq_attr "cpu" "ppc8540")) | ||
177 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
178 | "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | ||
179 | |||
180 | ;; Stores. | ||
181 | (define_insn_reservation "ppc8540_store" 3 | ||
182 | (and (eq_attr "type" "store,store_ux,store_u,store_c") | ||
183 | - (eq_attr "cpu" "ppc8540")) | ||
184 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
185 | "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | ||
186 | |||
187 | ;; Simple FP | ||
188 | (define_insn_reservation "ppc8540_simple_float" 1 | ||
189 | (and (eq_attr "type" "fpsimple") | ||
190 | - (eq_attr "cpu" "ppc8540")) | ||
191 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
192 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
193 | |||
194 | ;; FP | ||
195 | (define_insn_reservation "ppc8540_float" 4 | ||
196 | (and (eq_attr "type" "fp") | ||
197 | - (eq_attr "cpu" "ppc8540")) | ||
198 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
199 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | ||
200 | ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | ||
201 | |||
202 | @@ -180,44 +180,44 @@ | ||
203 | ;; because of the result automata will be huge. | ||
204 | (define_insn_reservation "ppc8540_float_vector_divide" 29 | ||
205 | (and (eq_attr "type" "vecfdiv") | ||
206 | - (eq_attr "cpu" "ppc8540")) | ||
207 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
208 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | ||
209 | ppc8540_mu_div*28") | ||
210 | |||
211 | ;; Brinc | ||
212 | (define_insn_reservation "ppc8540_brinc" 1 | ||
213 | (and (eq_attr "type" "brinc") | ||
214 | - (eq_attr "cpu" "ppc8540")) | ||
215 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
216 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
217 | |||
218 | ;; Simple vector | ||
219 | (define_insn_reservation "ppc8540_simple_vector" 1 | ||
220 | (and (eq_attr "type" "vecsimple") | ||
221 | - (eq_attr "cpu" "ppc8540")) | ||
222 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
223 | "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | ||
224 | |||
225 | ;; Simple vector compare | ||
226 | (define_insn_reservation "ppc8540_simple_vector_compare" 1 | ||
227 | (and (eq_attr "type" "veccmpsimple") | ||
228 | - (eq_attr "cpu" "ppc8540")) | ||
229 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
230 | "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | ||
231 | |||
232 | ;; Vector compare | ||
233 | (define_insn_reservation "ppc8540_vector_compare" 1 | ||
234 | (and (eq_attr "type" "veccmp") | ||
235 | - (eq_attr "cpu" "ppc8540")) | ||
236 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
237 | "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | ||
238 | |||
239 | ;; evsplatfi evsplati | ||
240 | (define_insn_reservation "ppc8540_vector_perm" 1 | ||
241 | (and (eq_attr "type" "vecperm") | ||
242 | - (eq_attr "cpu" "ppc8540")) | ||
243 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
244 | "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | ||
245 | |||
246 | ;; Vector float | ||
247 | (define_insn_reservation "ppc8540_float_vector" 4 | ||
248 | (and (eq_attr "type" "vecfloat") | ||
249 | - (eq_attr "cpu" "ppc8540")) | ||
250 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
251 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | ||
252 | ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | ||
253 | |||
254 | @@ -226,25 +226,25 @@ | ||
255 | ;; of miu_stage3 here because we use the average latency time. | ||
256 | (define_insn_reservation "ppc8540_vector_divide" 14 | ||
257 | (and (eq_attr "type" "vecdiv") | ||
258 | - (eq_attr "cpu" "ppc8540")) | ||
259 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
260 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | ||
261 | ppc8540_mu_div*13") | ||
262 | |||
263 | ;; Complex vector. | ||
264 | (define_insn_reservation "ppc8540_complex_vector" 4 | ||
265 | (and (eq_attr "type" "veccomplex") | ||
266 | - (eq_attr "cpu" "ppc8540")) | ||
267 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
268 | "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | ||
269 | ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | ||
270 | |||
271 | ;; Vector load | ||
272 | (define_insn_reservation "ppc8540_vector_load" 3 | ||
273 | (and (eq_attr "type" "vecload") | ||
274 | - (eq_attr "cpu" "ppc8540")) | ||
275 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
276 | "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | ||
277 | |||
278 | ;; Vector store | ||
279 | (define_insn_reservation "ppc8540_vector_store" 3 | ||
280 | (and (eq_attr "type" "vecstore") | ||
281 | - (eq_attr "cpu" "ppc8540")) | ||
282 | + (eq_attr "cpu" "ppc8540,ppc8548")) | ||
283 | "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | ||
284 | Index: gcc-4_7-branch/gcc/config/rs6000/e500-double.h | ||
285 | =================================================================== | ||
286 | --- gcc-4_7-branch.orig/gcc/config/rs6000/e500-double.h 2012-07-05 23:49:07.000000000 -0700 | ||
287 | +++ /dev/null 1970-01-01 00:00:00.000000000 +0000 | ||
288 | @@ -1,24 +0,0 @@ | ||
289 | -/* Target definitions for E500 with double precision FP. | ||
290 | - Copyright (C) 2004, 2006, 2007, 2011 Free Software Foundation, Inc. | ||
291 | - Contributed by Aldy Hernandez (aldyh@redhat.com). | ||
292 | - | ||
293 | - This file is part of GCC. | ||
294 | - | ||
295 | - GCC is free software; you can redistribute it and/or modify it | ||
296 | - under the terms of the GNU General Public License as published | ||
297 | - by the Free Software Foundation; either version 3, or (at your | ||
298 | - option) any later version. | ||
299 | - | ||
300 | - GCC is distributed in the hope that it will be useful, but WITHOUT | ||
301 | - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | ||
302 | - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | ||
303 | - License for more details. | ||
304 | - | ||
305 | - You should have received a copy of the GNU General Public License | ||
306 | - along with GCC; see the file COPYING3. If not see | ||
307 | - <http://www.gnu.org/licenses/>. */ | ||
308 | - | ||
309 | -#undef SUB3TARGET_OVERRIDE_OPTIONS | ||
310 | -#define SUB3TARGET_OVERRIDE_OPTIONS \ | ||
311 | - if (!global_options_set.x_rs6000_float_gprs) \ | ||
312 | - rs6000_float_gprs = 2; | ||
313 | Index: gcc-4_7-branch/gcc/config/rs6000/e500.h | ||
314 | =================================================================== | ||
315 | --- gcc-4_7-branch.orig/gcc/config/rs6000/e500.h 2012-07-05 23:49:07.000000000 -0700 | ||
316 | +++ gcc-4_7-branch/gcc/config/rs6000/e500.h 2012-07-06 19:44:38.466780001 -0700 | ||
317 | @@ -19,7 +19,6 @@ | ||
318 | |||
319 | #undef TARGET_SPE_ABI | ||
320 | #undef TARGET_SPE | ||
321 | -#undef TARGET_E500 | ||
322 | #undef TARGET_FPRS | ||
323 | #undef TARGET_E500_SINGLE | ||
324 | #undef TARGET_E500_DOUBLE | ||
325 | @@ -27,21 +26,20 @@ | ||
326 | |||
327 | #define TARGET_SPE_ABI rs6000_spe_abi | ||
328 | #define TARGET_SPE rs6000_spe | ||
329 | -#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540) | ||
330 | #define TARGET_FPRS (rs6000_float_gprs == 0) | ||
331 | #define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1) | ||
332 | #define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2) | ||
333 | #define CHECK_E500_OPTIONS \ | ||
334 | do { \ | ||
335 | - if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \ | ||
336 | + if (TARGET_SPE || TARGET_SPE_ABI \ | ||
337 | || TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \ | ||
338 | { \ | ||
339 | if (TARGET_ALTIVEC) \ | ||
340 | - error ("AltiVec and E500 instructions cannot coexist"); \ | ||
341 | + error ("AltiVec and SPE instructions cannot coexist"); \ | ||
342 | if (TARGET_VSX) \ | ||
343 | - error ("VSX and E500 instructions cannot coexist"); \ | ||
344 | + error ("VSX and SPE instructions cannot coexist"); \ | ||
345 | if (TARGET_64BIT) \ | ||
346 | - error ("64-bit E500 not supported"); \ | ||
347 | + error ("64-bit SPE not supported"); \ | ||
348 | if (TARGET_HARD_FLOAT && TARGET_FPRS) \ | ||
349 | error ("E500 and FPRs not supported"); \ | ||
350 | } \ | ||
351 | Index: gcc-4_7-branch/gcc/config/rs6000/eabispe.h | ||
352 | =================================================================== | ||
353 | --- gcc-4_7-branch.orig/gcc/config/rs6000/eabispe.h 2012-07-05 23:49:07.000000000 -0700 | ||
354 | +++ gcc-4_7-branch/gcc/config/rs6000/eabispe.h 2012-07-06 19:44:38.466780001 -0700 | ||
355 | @@ -21,21 +21,8 @@ | ||
356 | <http://www.gnu.org/licenses/>. */ | ||
357 | |||
358 | #undef TARGET_DEFAULT | ||
359 | -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI \ | ||
360 | - | MASK_STRICT_ALIGN) | ||
361 | - | ||
362 | -#undef SUBSUBTARGET_OVERRIDE_OPTIONS | ||
363 | -#define SUBSUBTARGET_OVERRIDE_OPTIONS \ | ||
364 | - if (!global_options_set.x_rs6000_cpu_index) \ | ||
365 | - rs6000_cpu = PROCESSOR_PPC8540; \ | ||
366 | - if (!global_options_set.x_rs6000_spe_abi) \ | ||
367 | - rs6000_spe_abi = 1; \ | ||
368 | - if (!global_options_set.x_rs6000_float_gprs) \ | ||
369 | - rs6000_float_gprs = 1; \ | ||
370 | - if (!global_options_set.x_rs6000_spe) \ | ||
371 | - rs6000_spe = 1; \ | ||
372 | - if (target_flags & MASK_64BIT) \ | ||
373 | - error ("-m64 not supported in this configuration") | ||
374 | +#define TARGET_DEFAULT \ | ||
375 | + (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI) | ||
376 | |||
377 | #undef ASM_DEFAULT_SPEC | ||
378 | #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" | ||
379 | Index: gcc-4_7-branch/gcc/config/rs6000/linuxspe.h | ||
380 | =================================================================== | ||
381 | --- gcc-4_7-branch.orig/gcc/config/rs6000/linuxspe.h 2012-07-05 23:52:14.000000000 -0700 | ||
382 | +++ gcc-4_7-branch/gcc/config/rs6000/linuxspe.h 2012-07-06 19:44:38.466780001 -0700 | ||
383 | @@ -22,20 +22,8 @@ | ||
384 | |||
385 | /* Override rs6000.h and sysv4.h definition. */ | ||
386 | #undef TARGET_DEFAULT | ||
387 | -#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN) | ||
388 | - | ||
389 | -#undef SUBSUBTARGET_OVERRIDE_OPTIONS | ||
390 | -#define SUBSUBTARGET_OVERRIDE_OPTIONS \ | ||
391 | - if (!global_options_set.x_rs6000_cpu_index) \ | ||
392 | - rs6000_cpu = PROCESSOR_PPC8540; \ | ||
393 | - if (!global_options_set.x_rs6000_spe_abi) \ | ||
394 | - rs6000_spe_abi = 1; \ | ||
395 | - if (!global_options_set.x_rs6000_float_gprs) \ | ||
396 | - rs6000_float_gprs = 1; \ | ||
397 | - if (!global_options_set.x_rs6000_spe) \ | ||
398 | - rs6000_spe = 1; \ | ||
399 | - if (target_flags & MASK_64BIT) \ | ||
400 | - error ("-m64 not supported in this configuration") | ||
401 | +#define TARGET_DEFAULT \ | ||
402 | + (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN) | ||
403 | |||
404 | #undef ASM_DEFAULT_SPEC | ||
405 | #define ASM_DEFAULT_SPEC "-mppc -mspe -me500" | ||
406 | Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def | ||
407 | =================================================================== | ||
408 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:43:53.000000000 -0700 | ||
409 | +++ gcc-4_7-branch/gcc/config/rs6000/rs6000-cpus.def 2012-07-06 19:44:38.000000000 -0700 | ||
410 | @@ -76,8 +76,7 @@ | ||
411 | RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT) | ||
412 | RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN | ||
413 | | MASK_ISEL) | ||
414 | -/* 8548 has a dummy entry for now. */ | ||
415 | -RS6000_CPU ("8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN | ||
416 | +RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN | ||
417 | | MASK_ISEL) | ||
418 | RS6000_CPU ("a2", PROCESSOR_PPCA2, | ||
419 | POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | ||
420 | Index: gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h | ||
421 | =================================================================== | ||
422 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:43:53.000000000 -0700 | ||
423 | +++ gcc-4_7-branch/gcc/config/rs6000/rs6000-opts.h 2012-07-06 19:44:38.000000000 -0700 | ||
424 | @@ -49,6 +49,7 @@ | ||
425 | PROCESSOR_PPC7400, | ||
426 | PROCESSOR_PPC7450, | ||
427 | PROCESSOR_PPC8540, | ||
428 | + PROCESSOR_PPC8548, | ||
429 | PROCESSOR_PPCE300C2, | ||
430 | PROCESSOR_PPCE300C3, | ||
431 | PROCESSOR_PPCE500MC, | ||
432 | Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.c | ||
433 | =================================================================== | ||
434 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.c 2012-07-06 19:43:53.194780001 -0700 | ||
435 | +++ gcc-4_7-branch/gcc/config/rs6000/rs6000.c 2012-07-06 19:44:38.000000000 -0700 | ||
436 | @@ -2597,7 +2597,10 @@ | ||
437 | { | ||
438 | bool ret = true; | ||
439 | bool have_cpu = false; | ||
440 | - const char *default_cpu = OPTION_TARGET_CPU_DEFAULT; | ||
441 | + | ||
442 | + /* The default cpu requested at configure time, if any. */ | ||
443 | + const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT; | ||
444 | + | ||
445 | int set_masks; | ||
446 | int cpu_index; | ||
447 | int tune_index; | ||
448 | @@ -2616,11 +2619,6 @@ | ||
449 | warning (0, "-malign-power is not supported for 64-bit Darwin;" | ||
450 | " it is incompatible with the installed C and C++ libraries"); | ||
451 | |||
452 | - if (global_options_set.x_rs6000_spe_abi | ||
453 | - && rs6000_spe_abi | ||
454 | - && !TARGET_SPE_ABI) | ||
455 | - error ("not configured for SPE ABI"); | ||
456 | - | ||
457 | /* Numerous experiment shows that IRA based loop pressure | ||
458 | calculation works better for RTL loop invariant motion on targets | ||
459 | with enough (>= 32) registers. It is an expensive optimization. | ||
460 | @@ -2656,7 +2654,8 @@ | ||
461 | /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed | ||
462 | the cpu in a target attribute or pragma, but did not specify a tuning | ||
463 | option, use the cpu for the tuning option rather than the option specified | ||
464 | - with -mtune on the command line. */ | ||
465 | + with -mtune on the command line. Process a '--with-cpu' configuration | ||
466 | + request as an implicit --cpu. */ | ||
467 | if (rs6000_cpu_index >= 0) | ||
468 | { | ||
469 | cpu_index = rs6000_cpu_index; | ||
470 | @@ -2669,10 +2668,12 @@ | ||
471 | } | ||
472 | else | ||
473 | { | ||
474 | - if (!default_cpu) | ||
475 | - default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc"); | ||
476 | + const char *default_cpu = | ||
477 | + (implicit_cpu ? implicit_cpu | ||
478 | + : (TARGET_POWERPC64 ? "powerpc64" : "powerpc")); | ||
479 | |||
480 | rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu); | ||
481 | + have_cpu = implicit_cpu != 0; | ||
482 | } | ||
483 | |||
484 | gcc_assert (cpu_index >= 0); | ||
485 | @@ -2703,6 +2704,42 @@ | ||
486 | gcc_assert (tune_index >= 0); | ||
487 | rs6000_cpu = processor_target_table[tune_index].processor; | ||
488 | |||
489 | + /* Pick defaults for SPE related control flags. Do this early to make sure | ||
490 | + that the TARGET_ macros are representative ASAP. */ | ||
491 | + { | ||
492 | + int spe_capable_cpu = | ||
493 | + (rs6000_cpu == PROCESSOR_PPC8540 | ||
494 | + || rs6000_cpu == PROCESSOR_PPC8548); | ||
495 | + | ||
496 | + if (!global_options_set.x_rs6000_spe_abi) | ||
497 | + rs6000_spe_abi = spe_capable_cpu; | ||
498 | + | ||
499 | + if (!global_options_set.x_rs6000_spe) | ||
500 | + rs6000_spe = spe_capable_cpu; | ||
501 | + | ||
502 | + if (!global_options_set.x_rs6000_float_gprs) | ||
503 | + rs6000_float_gprs = | ||
504 | + (rs6000_cpu == PROCESSOR_PPC8540 ? 1 | ||
505 | + : rs6000_cpu == PROCESSOR_PPC8548 ? 2 | ||
506 | + : 0); | ||
507 | + } | ||
508 | + | ||
509 | + if (global_options_set.x_rs6000_spe_abi | ||
510 | + && rs6000_spe_abi | ||
511 | + && !TARGET_SPE_ABI) | ||
512 | + error ("not configured for SPE ABI"); | ||
513 | + | ||
514 | + if (global_options_set.x_rs6000_spe | ||
515 | + && rs6000_spe | ||
516 | + && !TARGET_SPE) | ||
517 | + error ("not configured for SPE instruction set"); | ||
518 | + | ||
519 | + if (main_target_opt != NULL | ||
520 | + && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) | ||
521 | + || (main_target_opt->x_rs6000_spe != rs6000_spe) | ||
522 | + || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs))) | ||
523 | + error ("target attribute or pragma changes SPE ABI"); | ||
524 | + | ||
525 | if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3 | ||
526 | || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
527 | { | ||
528 | @@ -2938,35 +2975,44 @@ | ||
529 | SUB3TARGET_OVERRIDE_OPTIONS; | ||
530 | #endif | ||
531 | |||
532 | - if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC | ||
533 | - || rs6000_cpu == PROCESSOR_PPCE500MC64) | ||
534 | + /* For the E500 family of cores, reset the single/double FP flags to let us | ||
535 | + check that they remain constant across attributes or pragmas. Also, | ||
536 | + clear a possible request for string instructions, not supported and which | ||
537 | + we might have silently queried above for -Os. | ||
538 | + | ||
539 | + For other families, clear ISEL in case it was set implicitly. | ||
540 | + */ | ||
541 | + | ||
542 | + switch (rs6000_cpu) | ||
543 | { | ||
544 | - /* The e500 and e500mc do not have string instructions, and we set | ||
545 | - MASK_STRING above when optimizing for size. */ | ||
546 | - if ((target_flags & MASK_STRING) != 0) | ||
547 | - target_flags = target_flags & ~MASK_STRING; | ||
548 | - } | ||
549 | - else if (global_options_set.x_rs6000_cpu_index) | ||
550 | - { | ||
551 | - /* For the powerpc-eabispe configuration, we set all these by | ||
552 | - default, so let's unset them if we manually set another | ||
553 | - CPU that is not the E500. */ | ||
554 | - if (main_target_opt != NULL | ||
555 | - && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi) | ||
556 | - || (main_target_opt->x_rs6000_spe != rs6000_spe) | ||
557 | - || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs))) | ||
558 | - error ("target attribute or pragma changes SPE ABI"); | ||
559 | - else | ||
560 | - { | ||
561 | - if (!global_options_set.x_rs6000_spe_abi) | ||
562 | - rs6000_spe_abi = 0; | ||
563 | - if (!global_options_set.x_rs6000_spe) | ||
564 | - rs6000_spe = 0; | ||
565 | - if (!global_options_set.x_rs6000_float_gprs) | ||
566 | - rs6000_float_gprs = 0; | ||
567 | - } | ||
568 | - if (!(target_flags_explicit & MASK_ISEL)) | ||
569 | + case PROCESSOR_PPC8540: | ||
570 | + case PROCESSOR_PPC8548: | ||
571 | + case PROCESSOR_PPCE500MC: | ||
572 | + case PROCESSOR_PPCE500MC64: | ||
573 | + | ||
574 | + rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE; | ||
575 | + rs6000_double_float = TARGET_E500_DOUBLE; | ||
576 | + | ||
577 | + target_flags &= ~MASK_STRING; | ||
578 | + | ||
579 | + break; | ||
580 | + | ||
581 | + default: | ||
582 | + | ||
583 | + if (have_cpu && !(target_flags_explicit & MASK_ISEL)) | ||
584 | target_flags &= ~MASK_ISEL; | ||
585 | + | ||
586 | + break; | ||
587 | + } | ||
588 | + | ||
589 | + if (main_target_opt) | ||
590 | + { | ||
591 | + if (main_target_opt->x_rs6000_single_float != rs6000_single_float) | ||
592 | + error ("target attribute or pragma changes single precision floating " | ||
593 | + "point"); | ||
594 | + if (main_target_opt->x_rs6000_double_float != rs6000_double_float) | ||
595 | + error ("target attribute or pragma changes double precision floating " | ||
596 | + "point"); | ||
597 | } | ||
598 | |||
599 | /* Detect invalid option combinations with E500. */ | ||
600 | @@ -3193,6 +3239,7 @@ | ||
601 | break; | ||
602 | |||
603 | case PROCESSOR_PPC8540: | ||
604 | + case PROCESSOR_PPC8548: | ||
605 | rs6000_cost = &ppc8540_cost; | ||
606 | break; | ||
607 | |||
608 | @@ -3265,26 +3312,6 @@ | ||
609 | && rs6000_single_float == 0 && rs6000_double_float == 0) | ||
610 | rs6000_single_float = rs6000_double_float = 1; | ||
611 | |||
612 | - /* Reset single and double FP flags if target is E500. */ | ||
613 | - if (TARGET_E500) | ||
614 | - { | ||
615 | - rs6000_single_float = rs6000_double_float = 0; | ||
616 | - if (TARGET_E500_SINGLE) | ||
617 | - rs6000_single_float = 1; | ||
618 | - if (TARGET_E500_DOUBLE) | ||
619 | - rs6000_single_float = rs6000_double_float = 1; | ||
620 | - } | ||
621 | - | ||
622 | - if (main_target_opt) | ||
623 | - { | ||
624 | - if (main_target_opt->x_rs6000_single_float != rs6000_single_float) | ||
625 | - error ("target attribute or pragma changes single precision floating " | ||
626 | - "point"); | ||
627 | - if (main_target_opt->x_rs6000_double_float != rs6000_double_float) | ||
628 | - error ("target attribute or pragma changes double precision floating " | ||
629 | - "point"); | ||
630 | - } | ||
631 | - | ||
632 | /* If not explicitly specified via option, decide whether to generate indexed | ||
633 | load/store instructions. */ | ||
634 | if (TARGET_AVOID_XFORM == -1) | ||
635 | @@ -22816,6 +22843,7 @@ | ||
636 | case CPU_PPC750: | ||
637 | case CPU_PPC7400: | ||
638 | case CPU_PPC8540: | ||
639 | + case CPU_PPC8548: | ||
640 | case CPU_CELL: | ||
641 | case CPU_PPCE300C2: | ||
642 | case CPU_PPCE300C3: | ||
643 | @@ -22846,11 +22874,18 @@ | ||
644 | static int | ||
645 | rs6000_use_sched_lookahead (void) | ||
646 | { | ||
647 | - if (rs6000_cpu_attr == CPU_PPC8540) | ||
648 | - return 4; | ||
649 | - if (rs6000_cpu_attr == CPU_CELL) | ||
650 | - return (reload_completed ? 8 : 0); | ||
651 | - return 0; | ||
652 | + switch (rs6000_cpu_attr) | ||
653 | + { | ||
654 | + case CPU_PPC8540: | ||
655 | + case CPU_PPC8548: | ||
656 | + return 4; | ||
657 | + | ||
658 | + case CPU_CELL: | ||
659 | + return (reload_completed ? 8 : 0); | ||
660 | + | ||
661 | + default: | ||
662 | + return 0; | ||
663 | + } | ||
664 | } | ||
665 | |||
666 | /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */ | ||
667 | Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.h | ||
668 | =================================================================== | ||
669 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.h 2012-07-06 19:43:53.000000000 -0700 | ||
670 | +++ gcc-4_7-branch/gcc/config/rs6000/rs6000.h 2012-07-06 19:44:38.000000000 -0700 | ||
671 | @@ -457,7 +457,6 @@ | ||
672 | |||
673 | #define TARGET_SPE_ABI 0 | ||
674 | #define TARGET_SPE 0 | ||
675 | -#define TARGET_E500 0 | ||
676 | #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) | ||
677 | #define TARGET_FPRS 1 | ||
678 | #define TARGET_E500_SINGLE 0 | ||
679 | @@ -500,11 +499,11 @@ | ||
680 | || TARGET_ALTIVEC \ | ||
681 | || TARGET_VSX))) | ||
682 | |||
683 | +/* E500 cores only support plain "sync", not lwsync. */ | ||
684 | +#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | ||
685 | + || rs6000_cpu == PROCESSOR_PPC8548) | ||
686 | |||
687 | |||
688 | -/* E500 processors only support plain "sync", not lwsync. */ | ||
689 | -#define TARGET_NO_LWSYNC TARGET_E500 | ||
690 | - | ||
691 | /* Which machine supports the various reciprocal estimate instructions. */ | ||
692 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ | ||
693 | && TARGET_FPRS && TARGET_SINGLE_FLOAT) | ||
694 | Index: gcc-4_7-branch/gcc/config/rs6000/rs6000.md | ||
695 | =================================================================== | ||
696 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rs6000.md 2012-07-06 19:43:53.000000000 -0700 | ||
697 | +++ gcc-4_7-branch/gcc/config/rs6000/rs6000.md 2012-07-06 19:44:38.000000000 -0700 | ||
698 | @@ -166,7 +166,7 @@ | ||
699 | ;; Processor type -- this attribute must exactly match the processor_type | ||
700 | ;; enumeration in rs6000.h. | ||
701 | |||
702 | -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" | ||
703 | +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan" | ||
704 | (const (symbol_ref "rs6000_cpu_attr"))) | ||
705 | |||
706 | |||
707 | Index: gcc-4_7-branch/gcc/config/rs6000/rtems.h | ||
708 | =================================================================== | ||
709 | --- gcc-4_7-branch.orig/gcc/config/rs6000/rtems.h 2012-07-05 23:49:07.000000000 -0700 | ||
710 | +++ gcc-4_7-branch/gcc/config/rs6000/rtems.h 2012-07-06 19:44:38.470780001 -0700 | ||
711 | @@ -55,17 +55,3 @@ | ||
712 | #undef SUBSUBTARGET_EXTRA_SPECS | ||
713 | #define SUBSUBTARGET_EXTRA_SPECS \ | ||
714 | { "cpp_os_rtems", CPP_OS_RTEMS_SPEC } | ||
715 | - | ||
716 | -#undef SUBSUBTARGET_OVERRIDE_OPTIONS | ||
717 | -#define SUBSUBTARGET_OVERRIDE_OPTIONS \ | ||
718 | - do { \ | ||
719 | - if (TARGET_E500) \ | ||
720 | - { \ | ||
721 | - if (TARGET_HARD_FLOAT && !global_options_set.x_rs6000_float_gprs) \ | ||
722 | - rs6000_float_gprs = 1; \ | ||
723 | - if (rs6000_float_gprs != 0 && !global_options_set.x_rs6000_spe) \ | ||
724 | - rs6000_spe = 1; \ | ||
725 | - if (rs6000_spe && !global_options_set.x_rs6000_spe_abi) \ | ||
726 | - rs6000_spe_abi = 1; \ | ||
727 | - } \ | ||
728 | - } while(0) | ||
729 | Index: gcc-4_7-branch/gcc/config/rs6000/vxworks.h | ||
730 | =================================================================== | ||
731 | --- gcc-4_7-branch.orig/gcc/config/rs6000/vxworks.h 2012-07-05 23:49:07.000000000 -0700 | ||
732 | +++ gcc-4_7-branch/gcc/config/rs6000/vxworks.h 2012-07-06 19:44:38.470780001 -0700 | ||
733 | @@ -122,19 +122,8 @@ | ||
734 | |||
735 | #undef ABI_STACK_BOUNDARY | ||
736 | |||
737 | -/* Make -mcpu=8540 imply SPE. ISEL is automatically enabled, the | ||
738 | - others must be done by hand. Handle -mrtp. Disable -fPIC | ||
739 | - for -mrtp - the VxWorks PIC model is not compatible with it. */ | ||
740 | #undef SUBSUBTARGET_OVERRIDE_OPTIONS | ||
741 | #define SUBSUBTARGET_OVERRIDE_OPTIONS \ | ||
742 | - do { \ | ||
743 | - if (TARGET_E500) \ | ||
744 | - { \ | ||
745 | - rs6000_spe = 1; \ | ||
746 | - rs6000_spe_abi = 1; \ | ||
747 | - rs6000_float_gprs = 1; \ | ||
748 | - } \ | ||
749 | - \ | ||
750 | if (!global_options_set.x_g_switch_value) \ | ||
751 | g_switch_value = SDATA_DEFAULT_SIZE; \ | ||
752 | VXWORKS_OVERRIDE_OPTIONS; \ | ||