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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch465
1 files changed, 0 insertions, 465 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch b/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch
deleted file mode 100644
index 1f478f3ea7..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.6/powerpc-e5500.patch
+++ /dev/null
@@ -1,465 +0,0 @@
1Upstream-Status: Pending
2
3Implements basic e5500 enablement in gcc, with a scheduler, -mcpu
4flag, etc...
5
6Also splits the masks for popcntb, popcntd, and cmpb. Originally those
7masks would also control other instructions that e5500 does not
8support (so, we either get none or all).
9
10For the lack of means to do tests, those instructions were never
11enabled until now. The new instructions enabled with this patch are:
12popcntb, popcntw, popcntd, bpermd, prtyw, prtyd, cmpb, ldbrx, and
13stdbrx.
14
15Signed-off-by: Edmar Wienskoski <edmar@freescale.com>
16Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
17
18Index: gcc-4_6-branch/gcc/config.gcc
19===================================================================
20--- gcc-4_6-branch.orig/gcc/config.gcc
21+++ gcc-4_6-branch/gcc/config.gcc
22@@ -395,7 +395,7 @@ powerpc*-*-*)
23 extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h spu2vmx.h vec_types.h si2vmx.h"
24 need_64bit_hwint=yes
25 case x$with_cpu in
26- xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64)
27+ xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[34567]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500)
28 cpu_is_64bit=yes
29 ;;
30 esac
31@@ -3493,7 +3493,7 @@ case "${target}" in
32 | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
33 | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \
34 | 604 | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
35- | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | titan\
36+ | a2 | e300c[23] | 854[08] | e500mc | e500mc64 | e5500 | titan\
37 | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
38 # OK
39 ;;
40Index: gcc-4_6-branch/gcc/config/rs6000/e5500.md
41===================================================================
42--- /dev/null
43+++ gcc-4_6-branch/gcc/config/rs6000/e5500.md
44@@ -0,0 +1,176 @@
45+;; Pipeline description for Freescale PowerPC e5500 core.
46+;; Copyright (C) 2011 Free Software Foundation, Inc.
47+;; Contributed by Edmar Wienskoski (edmar@freescale.com)
48+;;
49+;; This file is part of GCC.
50+;;
51+;; GCC is free software; you can redistribute it and/or modify it
52+;; under the terms of the GNU General Public License as published
53+;; by the Free Software Foundation; either version 3, or (at your
54+;; option) any later version.
55+;;
56+;; GCC is distributed in the hope that it will be useful, but WITHOUT
57+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
58+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
59+;; License for more details.
60+;;
61+;; You should have received a copy of the GNU General Public License
62+;; along with GCC; see the file COPYING3. If not see
63+;; <http://www.gnu.org/licenses/>.
64+;;
65+;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
66+;; Max issue 3 insns/clock cycle (includes 1 branch)
67+
68+(define_automaton "e5500_most,e5500_long")
69+(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
70+
71+;; SFX.
72+(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
73+
74+;; CFX.
75+(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
76+
77+;; Non-pipelined division.
78+(define_cpu_unit "e5500_cfx_div" "e5500_long")
79+
80+;; LSU.
81+(define_cpu_unit "e5500_lsu" "e5500_most")
82+
83+;; FPU.
84+(define_cpu_unit "e5500_fpu" "e5500_long")
85+
86+;; BU.
87+(define_cpu_unit "e5500_bu" "e5500_most")
88+
89+;; The following units are used to make the automata deterministic.
90+(define_cpu_unit "present_e5500_decode_0" "e5500_most")
91+(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
92+(presence_set "present_e5500_decode_0" "e5500_decode_0")
93+(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
94+
95+;; Some useful abbreviations.
96+(define_reservation "e5500_decode"
97+ "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
98+(define_reservation "e5500_sfx"
99+ "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
100+
101+;; SFX.
102+(define_insn_reservation "e5500_sfx" 1
103+ (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
104+ shift,cntlz,exts")
105+ (eq_attr "cpu" "ppce5500"))
106+ "e5500_decode,e5500_sfx")
107+
108+(define_insn_reservation "e5500_sfx2" 2
109+ (and (eq_attr "type" "cmp,compare,fast_compare,trap")
110+ (eq_attr "cpu" "ppce5500"))
111+ "e5500_decode,e5500_sfx")
112+
113+(define_insn_reservation "e5500_delayed" 2
114+ (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt")
115+ (eq_attr "cpu" "ppce5500"))
116+ "e5500_decode,e5500_sfx*2")
117+
118+(define_insn_reservation "e5500_two" 2
119+ (and (eq_attr "type" "two")
120+ (eq_attr "cpu" "ppce5500"))
121+ "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
122+
123+(define_insn_reservation "e5500_three" 3
124+ (and (eq_attr "type" "three")
125+ (eq_attr "cpu" "ppce5500"))
126+ "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
127+
128+;; SFX - Mfcr.
129+(define_insn_reservation "e5500_mfcr" 4
130+ (and (eq_attr "type" "mfcr")
131+ (eq_attr "cpu" "ppce5500"))
132+ "e5500_decode,e5500_sfx_0*4")
133+
134+;; SFX - Mtcrf.
135+(define_insn_reservation "e5500_mtcrf" 1
136+ (and (eq_attr "type" "mtcr")
137+ (eq_attr "cpu" "ppce5500"))
138+ "e5500_decode,e5500_sfx_0")
139+
140+;; SFX - Mtjmpr.
141+(define_insn_reservation "e5500_mtjmpr" 1
142+ (and (eq_attr "type" "mtjmpr,mfjmpr")
143+ (eq_attr "cpu" "ppce5500"))
144+ "e5500_decode,e5500_sfx")
145+
146+;; CFX - Multiply.
147+(define_insn_reservation "e5500_multiply" 4
148+ (and (eq_attr "type" "imul")
149+ (eq_attr "cpu" "ppce5500"))
150+ "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
151+
152+(define_insn_reservation "e5500_multiply_i" 5
153+ (and (eq_attr "type" "imul2,imul3,imul_compare")
154+ (eq_attr "cpu" "ppce5500"))
155+ "e5500_decode,e5500_cfx_stage0,\
156+ e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
157+
158+;; CFX - Divide.
159+(define_insn_reservation "e5500_divide" 16
160+ (and (eq_attr "type" "idiv")
161+ (eq_attr "cpu" "ppce5500"))
162+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
163+ e5500_cfx_div*15")
164+
165+(define_insn_reservation "e5500_divide_d" 26
166+ (and (eq_attr "type" "ldiv")
167+ (eq_attr "cpu" "ppce5500"))
168+ "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
169+ e5500_cfx_div*25")
170+
171+;; LSU - Loads.
172+(define_insn_reservation "e5500_load" 3
173+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
174+ load_l,sync")
175+ (eq_attr "cpu" "ppce5500"))
176+ "e5500_decode,e5500_lsu")
177+
178+(define_insn_reservation "e5500_fpload" 4
179+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
180+ (eq_attr "cpu" "ppce5500"))
181+ "e5500_decode,e5500_lsu")
182+
183+;; LSU - Stores.
184+(define_insn_reservation "e5500_store" 3
185+ (and (eq_attr "type" "store,store_ux,store_u,store_c")
186+ (eq_attr "cpu" "ppce5500"))
187+ "e5500_decode,e5500_lsu")
188+
189+(define_insn_reservation "e5500_fpstore" 3
190+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
191+ (eq_attr "cpu" "ppce5500"))
192+ "e5500_decode,e5500_lsu")
193+
194+;; FP.
195+(define_insn_reservation "e5500_float" 7
196+ (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
197+ (eq_attr "cpu" "ppce5500"))
198+ "e5500_decode,e5500_fpu")
199+
200+(define_insn_reservation "e5500_sdiv" 20
201+ (and (eq_attr "type" "sdiv")
202+ (eq_attr "cpu" "ppce5500"))
203+ "e5500_decode,e5500_fpu*20")
204+
205+(define_insn_reservation "e5500_ddiv" 35
206+ (and (eq_attr "type" "ddiv")
207+ (eq_attr "cpu" "ppce5500"))
208+ "e5500_decode,e5500_fpu*35")
209+
210+;; BU.
211+(define_insn_reservation "e5500_branch" 1
212+ (and (eq_attr "type" "jmpreg,branch,isync")
213+ (eq_attr "cpu" "ppce5500"))
214+ "e5500_decode,e5500_bu")
215+
216+;; BU - CR logical.
217+(define_insn_reservation "e5500_cr_logical" 1
218+ (and (eq_attr "type" "cr_logical,delayed_cr")
219+ (eq_attr "cpu" "ppce5500"))
220+ "e5500_decode,e5500_bu")
221Index: gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h
222===================================================================
223--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000-opts.h
224+++ gcc-4_6-branch/gcc/config/rs6000/rs6000-opts.h
225@@ -53,6 +53,7 @@ enum processor_type
226 PROCESSOR_PPCE300C3,
227 PROCESSOR_PPCE500MC,
228 PROCESSOR_PPCE500MC64,
229+ PROCESSOR_PPCE5500,
230 PROCESSOR_POWER4,
231 PROCESSOR_POWER5,
232 PROCESSOR_POWER6,
233Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.c
234===================================================================
235--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.c
236+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.c
237@@ -779,6 +779,25 @@ struct processor_costs ppce500mc64_cost
238 1, /* prefetch streams /*/
239 };
240
241+/* Instruction costs on PPCE5500 processors. */
242+static const
243+struct processor_costs ppce5500_cost = {
244+ COSTS_N_INSNS (5), /* mulsi */
245+ COSTS_N_INSNS (5), /* mulsi_const */
246+ COSTS_N_INSNS (5), /* mulsi_const9 */
247+ COSTS_N_INSNS (5), /* muldi */
248+ COSTS_N_INSNS (14), /* divsi */
249+ COSTS_N_INSNS (14), /* divdi */
250+ COSTS_N_INSNS (7), /* fp */
251+ COSTS_N_INSNS (10), /* dmul */
252+ COSTS_N_INSNS (36), /* sdiv */
253+ COSTS_N_INSNS (66), /* ddiv */
254+ 64, /* cache line size */
255+ 32, /* l1 cache */
256+ 128, /* l2 cache */
257+ 1, /* prefetch streams /*/
258+};
259+
260 /* Instruction costs on AppliedMicro Titan processors. */
261 static const
262 struct processor_costs titan_cost = {
263@@ -1784,6 +1803,9 @@ static struct rs6000_ptt const processor
264 | MASK_ISEL},
265 {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64
266 | MASK_PPC_GFXOPT | MASK_ISEL},
267+ {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
268+ | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB
269+ | MASK_POPCNTD},
270 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
271 {"970", PROCESSOR_POWER4,
272 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
273@@ -2741,7 +2763,8 @@ rs6000_option_override_internal (bool gl
274 : PROCESSOR_DEFAULT));
275
276 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
277- || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
278+ || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
279+ || rs6000_cpu == PROCESSOR_PPCE5500)
280 {
281 if (TARGET_ALTIVEC)
282 error ("AltiVec not supported in this target");
283@@ -2842,9 +2865,14 @@ rs6000_option_override_internal (bool gl
284 user's opinion, though. */
285 if (rs6000_block_move_inline_limit == 0
286 && (rs6000_cpu == PROCESSOR_PPCE500MC
287- || rs6000_cpu == PROCESSOR_PPCE500MC64))
288+ || rs6000_cpu == PROCESSOR_PPCE500MC64
289+ || rs6000_cpu == PROCESSOR_PPCE5500))
290 rs6000_block_move_inline_limit = 128;
291
292+ /* Those machines does not have fsqrt instruction */
293+ if (rs6000_cpu == PROCESSOR_PPCE5500)
294+ target_flags &= ~MASK_PPC_GPOPT;
295+
296 /* store_one_arg depends on expand_block_move to handle at least the
297 size of reg_parm_stack_space. */
298 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
299@@ -2976,7 +3004,8 @@ rs6000_option_override_internal (bool gl
300 #endif
301
302 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
303- || rs6000_cpu == PROCESSOR_PPCE500MC64)
304+ || rs6000_cpu == PROCESSOR_PPCE500MC64
305+ || rs6000_cpu == PROCESSOR_PPCE5500)
306 {
307 /* The e500 and e500mc do not have string instructions, and we set
308 MASK_STRING above when optimizing for size. */
309@@ -3023,7 +3052,8 @@ rs6000_option_override_internal (bool gl
310 || rs6000_cpu == PROCESSOR_POWER6
311 || rs6000_cpu == PROCESSOR_POWER7
312 || rs6000_cpu == PROCESSOR_PPCE500MC
313- || rs6000_cpu == PROCESSOR_PPCE500MC64);
314+ || rs6000_cpu == PROCESSOR_PPCE500MC64
315+ || rs6000_cpu == PROCESSOR_PPCE5500);
316
317 /* Allow debug switches to override the above settings. These are set to -1
318 in rs6000.opt to indicate the user hasn't directly set the switch. */
319@@ -3245,6 +3275,10 @@ rs6000_option_override_internal (bool gl
320 rs6000_cost = &ppce500mc64_cost;
321 break;
322
323+ case PROCESSOR_PPCE5500:
324+ rs6000_cost = &ppce5500_cost;
325+ break;
326+
327 case PROCESSOR_TITAN:
328 rs6000_cost = &titan_cost;
329 break;
330@@ -23227,6 +23261,7 @@ rs6000_adjust_cost (rtx insn, rtx link,
331 || rs6000_cpu_attr == CPU_PPC750
332 || rs6000_cpu_attr == CPU_PPC7400
333 || rs6000_cpu_attr == CPU_PPC7450
334+ || rs6000_cpu_attr == CPU_PPCE5500
335 || rs6000_cpu_attr == CPU_POWER4
336 || rs6000_cpu_attr == CPU_POWER5
337 || rs6000_cpu_attr == CPU_POWER7
338@@ -23771,6 +23806,7 @@ rs6000_issue_rate (void)
339 case CPU_PPCE300C3:
340 case CPU_PPCE500MC:
341 case CPU_PPCE500MC64:
342+ case CPU_PPCE5500:
343 case CPU_TITAN:
344 return 2;
345 case CPU_RIOS2:
346Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.h
347===================================================================
348--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.h
349+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.h
350@@ -168,6 +168,7 @@
351 %{mcpu=e300c3: -me300} \
352 %{mcpu=e500mc: -me500mc} \
353 %{mcpu=e500mc64: -me500mc64} \
354+%{mcpu=e5500: -me5500} \
355 %{maltivec: -maltivec} \
356 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
357 -many"
358@@ -477,13 +478,13 @@ extern int rs6000_vector_align[];
359
360 #define TARGET_FCTIDZ TARGET_FCFID
361 #define TARGET_STFIWX TARGET_PPC_GFXOPT
362-#define TARGET_LFIWAX TARGET_CMPB
363-#define TARGET_LFIWZX TARGET_POPCNTD
364-#define TARGET_FCFIDS TARGET_POPCNTD
365-#define TARGET_FCFIDU TARGET_POPCNTD
366-#define TARGET_FCFIDUS TARGET_POPCNTD
367-#define TARGET_FCTIDUZ TARGET_POPCNTD
368-#define TARGET_FCTIWUZ TARGET_POPCNTD
369+#define TARGET_LFIWAX (TARGET_CMPB && rs6000_cpu != PROCESSOR_PPCE5500)
370+#define TARGET_LFIWZX (TARGET_POPCNTD && rs6000_cpu != PROCESSOR_PPCE5500)
371+#define TARGET_FCFIDS TARGET_LFIWZX
372+#define TARGET_FCFIDU TARGET_LFIWZX
373+#define TARGET_FCFIDUS TARGET_LFIWZX
374+#define TARGET_FCTIDUZ TARGET_LFIWZX
375+#define TARGET_FCTIWUZ TARGET_LFIWZX
376
377 /* E500 processors only support plain "sync", not lwsync. */
378 #define TARGET_NO_LWSYNC TARGET_E500
379@@ -494,10 +495,12 @@ extern int rs6000_vector_align[];
380
381 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
382 && TARGET_DOUBLE_FLOAT \
383- && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
384+ && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) \
385+ && rs6000_cpu != PROCESSOR_PPCE5500)
386
387 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
388- && TARGET_FPRS && TARGET_SINGLE_FLOAT)
389+ && TARGET_FPRS && TARGET_SINGLE_FLOAT \
390+ && rs6000_cpu != PROCESSOR_PPCE5500)
391
392 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
393 && TARGET_DOUBLE_FLOAT \
394Index: gcc-4_6-branch/gcc/config/rs6000/rs6000.md
395===================================================================
396--- gcc-4_6-branch.orig/gcc/config/rs6000/rs6000.md
397+++ gcc-4_6-branch/gcc/config/rs6000/rs6000.md
398@@ -126,7 +126,7 @@
399
400 ;; Define an insn type attribute. This is used in function unit delay
401 ;; computations.
402-(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
403+(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
404 (const_string "integer"))
405
406 ;; Define floating point instruction sub-types for use with Xfpu.md
407@@ -148,7 +148,7 @@
408 ;; Processor type -- this attribute must exactly match the processor_type
409 ;; enumeration in rs6000.h.
410
411-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
412+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,power4,power5,power6,power7,cell,ppca2,titan"
413 (const (symbol_ref "rs6000_cpu_attr")))
414
415
416@@ -176,6 +176,7 @@
417 (include "e300c2c3.md")
418 (include "e500mc.md")
419 (include "e500mc64.md")
420+(include "e5500.md")
421 (include "power4.md")
422 (include "power5.md")
423 (include "power6.md")
424@@ -2302,13 +2303,17 @@
425 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
426 UNSPEC_POPCNTB))]
427 "TARGET_POPCNTB"
428- "popcntb %0,%1")
429+ "popcntb %0,%1"
430+ [(set_attr "length" "4")
431+ (set_attr "type" "popcnt")])
432
433 (define_insn "popcntd<mode>2"
434 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
435 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
436 "TARGET_POPCNTD"
437- "popcnt<wd> %0,%1")
438+ "popcnt<wd> %0,%1"
439+ [(set_attr "length" "4")
440+ (set_attr "type" "popcnt")])
441
442 (define_expand "popcount<mode>2"
443 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
444@@ -5957,10 +5962,10 @@
445 && ((TARGET_PPC_GFXOPT
446 && !HONOR_NANS (<MODE>mode)
447 && !HONOR_SIGNED_ZEROS (<MODE>mode))
448- || TARGET_CMPB
449+ || TARGET_LFIWAX
450 || VECTOR_UNIT_VSX_P (<MODE>mode))"
451 {
452- if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
453+ if (TARGET_LFIWAX || VECTOR_UNIT_VSX_P (<MODE>mode))
454 {
455 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
456 operands[2]));
457@@ -5979,7 +5984,7 @@
458 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
459 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
460 UNSPEC_COPYSIGN))]
461- "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
462+ "TARGET_LFIWAX && !VECTOR_UNIT_VSX_P (<MODE>mode)"
463 "fcpsgn %0,%2,%1"
464 [(set_attr "type" "fp")])
465
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-04-25 14:21:46 +0000