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Diffstat (limited to 'meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch')
-rw-r--r-- | meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch new file mode 100644 index 0000000000..4e133ff66f --- /dev/null +++ b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0270-config-rx-rx.md-Add-peephole-to-remove-redundant-ext.patch | |||
@@ -0,0 +1,126 @@ | |||
1 | From ad1e75ff0d2af88f3845d34f3f944a9211f7d9ec Mon Sep 17 00:00:00 2001 | ||
2 | From: nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4> | ||
3 | Date: Tue, 17 May 2011 08:46:51 +0000 | ||
4 | Subject: [PATCH] * config/rx/rx.md: Add peephole to remove redundant extensions | ||
5 | after loads. | ||
6 | (bitset_in_memory): Use rx_restricted_mem_operand. | ||
7 | (bitinvert_in_memory): Likewise. | ||
8 | (bitclr_in_memory): Likewise. | ||
9 | |||
10 | * config/rx/rx.md: Add peepholes to match a register move followed | ||
11 | by a comparison of the moved register. Replace these with an | ||
12 | addition of zero that does both actions in one instruction. | ||
13 | |||
14 | |||
15 | |||
16 | git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@173823 138bc75d-0d04-0410-961f-82ee72b054a4 | ||
17 | |||
18 | index 641f1d4..742c0f9 100644 | ||
19 | --- a/gcc/config/rx/rx.md | ||
20 | +++ b/gcc/config/rx/rx.md | ||
21 | @@ -904,6 +904,39 @@ | ||
22 | (set_attr "length" "3,4,5,6,7,6")] | ||
23 | ) | ||
24 | |||
25 | +;; Peepholes to match: | ||
26 | +;; (set (reg A) (reg B)) | ||
27 | +;; (set (CC) (compare:CC (reg A/reg B) (const_int 0))) | ||
28 | +;; and replace them with the addsi3_flags pattern, using an add | ||
29 | +;; of zero to copy the register and set the condition code bits. | ||
30 | +(define_peephole2 | ||
31 | + [(set (match_operand:SI 0 "register_operand") | ||
32 | + (match_operand:SI 1 "register_operand")) | ||
33 | + (set (reg:CC CC_REG) | ||
34 | + (compare:CC (match_dup 0) | ||
35 | + (const_int 0)))] | ||
36 | + "" | ||
37 | + [(parallel [(set (match_dup 0) | ||
38 | + (plus:SI (match_dup 1) (const_int 0))) | ||
39 | + (set (reg:CC_ZSC CC_REG) | ||
40 | + (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0)) | ||
41 | + (const_int 0)))])] | ||
42 | +) | ||
43 | + | ||
44 | +(define_peephole2 | ||
45 | + [(set (match_operand:SI 0 "register_operand") | ||
46 | + (match_operand:SI 1 "register_operand")) | ||
47 | + (set (reg:CC CC_REG) | ||
48 | + (compare:CC (match_dup 1) | ||
49 | + (const_int 0)))] | ||
50 | + "" | ||
51 | + [(parallel [(set (match_dup 0) | ||
52 | + (plus:SI (match_dup 1) (const_int 0))) | ||
53 | + (set (reg:CC_ZSC CC_REG) | ||
54 | + (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0)) | ||
55 | + (const_int 0)))])] | ||
56 | +) | ||
57 | + | ||
58 | (define_expand "adddi3" | ||
59 | [(set (match_operand:DI 0 "register_operand") | ||
60 | (plus:DI (match_operand:DI 1 "register_operand") | ||
61 | @@ -1668,6 +1701,35 @@ | ||
62 | (extend_types:SI (match_dup 1))))] | ||
63 | ) | ||
64 | |||
65 | +;; Convert: | ||
66 | +;; (set (reg1) (sign_extend (mem)) | ||
67 | +;; (set (reg2) (zero_extend (reg1)) | ||
68 | +;; into | ||
69 | +;; (set (reg2) (zero_extend (mem))) | ||
70 | +(define_peephole2 | ||
71 | + [(set (match_operand:SI 0 "register_operand") | ||
72 | + (sign_extend:SI (match_operand:small_int_modes 1 "memory_operand"))) | ||
73 | + (set (match_operand:SI 2 "register_operand") | ||
74 | + (zero_extend:SI (match_operand:small_int_modes 3 "register_operand")))] | ||
75 | + "REGNO (operands[0]) == REGNO (operands[3]) | ||
76 | + && (REGNO (operands[0]) == REGNO (operands[2]) | ||
77 | + || peep2_regno_dead_p (2, REGNO (operands[0])))" | ||
78 | + [(set (match_dup 2) | ||
79 | + (zero_extend:SI (match_dup 1)))] | ||
80 | +) | ||
81 | + | ||
82 | +;; Remove the redundant sign extension from: | ||
83 | +;; (set (reg) (extend (mem))) | ||
84 | +;; (set (reg) (extend (reg))) | ||
85 | +(define_peephole2 | ||
86 | + [(set (match_operand:SI 0 "register_operand") | ||
87 | + (extend_types:SI (match_operand:small_int_modes 1 "memory_operand"))) | ||
88 | + (set (match_dup 0) | ||
89 | + (extend_types:SI (match_operand:small_int_modes 2 "register_operand")))] | ||
90 | + "REGNO (operands[0]) == REGNO (operands[2])" | ||
91 | + [(set (match_dup 0) (extend_types:SI (match_dup 1)))] | ||
92 | +) | ||
93 | + | ||
94 | (define_insn "*comparesi3_<extend_types:code><small_int_modes:mode>" | ||
95 | [(set (reg:CC CC_REG) | ||
96 | (compare:CC (match_operand:SI 0 "register_operand" "=r") | ||
97 | @@ -1769,7 +1831,7 @@ | ||
98 | ) | ||
99 | |||
100 | (define_insn "*bitset_in_memory" | ||
101 | - [(set (match_operand:QI 0 "memory_operand" "+Q") | ||
102 | + [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") | ||
103 | (ior:QI (ashift:QI (const_int 1) | ||
104 | (match_operand:QI 1 "nonmemory_operand" "ri")) | ||
105 | (match_dup 0)))] | ||
106 | @@ -1790,7 +1852,7 @@ | ||
107 | ) | ||
108 | |||
109 | (define_insn "*bitinvert_in_memory" | ||
110 | - [(set (match_operand:QI 0 "memory_operand" "+Q") | ||
111 | + [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") | ||
112 | (xor:QI (ashift:QI (const_int 1) | ||
113 | (match_operand:QI 1 "nonmemory_operand" "ri")) | ||
114 | (match_dup 0)))] | ||
115 | @@ -1813,7 +1875,7 @@ | ||
116 | ) | ||
117 | |||
118 | (define_insn "*bitclr_in_memory" | ||
119 | - [(set (match_operand:QI 0 "memory_operand" "+Q") | ||
120 | + [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q") | ||
121 | (and:QI (not:QI | ||
122 | (ashift:QI | ||
123 | (const_int 1) | ||
124 | -- | ||
125 | 1.7.0.4 | ||
126 | |||