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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0219-Backport-from-mainline.patch145
1 files changed, 145 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0219-Backport-from-mainline.patch b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0219-Backport-from-mainline.patch
new file mode 100644
index 0000000000..89ac751c92
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0219-Backport-from-mainline.patch
@@ -0,0 +1,145 @@
1From c36ec52943b79e5245d18041217a1b9a76fde887 Mon Sep 17 00:00:00 2001
2From: irar <irar@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 5 May 2011 08:39:40 +0000
4Subject: [PATCH] Backport from mainline:
5 2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org>
6 Ira Rosen <ira.rosen@linaro.org>
7
8 PR target/48252
9 * config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments
10 to match neon_vzip/vuzp/vtrn_internal.
11 * config/arm/neon.md (neon_vtrn<mode>_internal): Make both
12 outputs explicitly dependent on both inputs.
13 (neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Likewise.
14
15
16
17git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@173418 138bc75d-0d04-0410-961f-82ee72b054a4
18
19index 8515002..9e6582a 100644
20--- a/gcc/config/arm/arm.c
21+++ b/gcc/config/arm/arm.c
22@@ -19564,7 +19564,7 @@ neon_emit_pair_result_insn (enum machine_mode mode,
23 rtx tmp1 = gen_reg_rtx (mode);
24 rtx tmp2 = gen_reg_rtx (mode);
25
26- emit_insn (intfn (tmp1, op1, tmp2, op2));
27+ emit_insn (intfn (tmp1, op1, op2, tmp2));
28
29 emit_move_insn (mem, tmp1);
30 mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
31diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
32index 440b982..bc13722 100644
33--- a/gcc/config/arm/neon.md
34+++ b/gcc/config/arm/neon.md
35@@ -4079,20 +4079,21 @@
36
37 (define_insn "neon_vtrn<mode>_internal"
38 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
39- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
40- UNSPEC_VTRN1))
41- (set (match_operand:VDQW 2 "s_register_operand" "=w")
42- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
43- UNSPEC_VTRN2))]
44- "TARGET_NEON"
45- "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
46+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
47+ (match_operand:VDQW 2 "s_register_operand" "w")]
48+ UNSPEC_VTRN1))
49+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
50+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
51+ UNSPEC_VTRN2))]
52+ "TARGET_NEON"
53+ "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
54 [(set (attr "neon_type")
55 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
56 (const_string "neon_bp_simple")
57 (const_string "neon_bp_3cycle")))]
58 )
59
60-(define_expand "neon_vtrn<mode>"
61+ "neon_vtrn<mode>"
62 [(match_operand:SI 0 "s_register_operand" "r")
63 (match_operand:VDQW 1 "s_register_operand" "w")
64 (match_operand:VDQW 2 "s_register_operand" "w")]
65@@ -4105,13 +4106,14 @@
66
67 (define_insn "neon_vzip<mode>_internal"
68 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
69- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
70- UNSPEC_VZIP1))
71- (set (match_operand:VDQW 2 "s_register_operand" "=w")
72- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
73- UNSPEC_VZIP2))]
74- "TARGET_NEON"
75- "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
76+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
77+ (match_operand:VDQW 2 "s_register_operand" "w")]
78+ UNSPEC_VZIP1))
79+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
80+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
81+ UNSPEC_VZIP2))]
82+ "TARGET_NEON"
83+ "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
84 [(set (attr "neon_type")
85 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
86 (const_string "neon_bp_simple")
87@@ -4131,13 +4133,14 @@
88
89 (define_insn "neon_vuzp<mode>_internal"
90 [(set (match_operand:VDQW 0 "s_register_operand" "=w")
91- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
92+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
93+ (match_operand:VDQW 2 "s_register_operand" "w")]
94 UNSPEC_VUZP1))
95- (set (match_operand:VDQW 2 "s_register_operand" "=w")
96- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
97- UNSPEC_VUZP2))]
98+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
99+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
100+ UNSPEC_VUZP2))]
101 "TARGET_NEON"
102- "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
103+ "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
104 [(set (attr "neon_type")
105 (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
106 (const_string "neon_bp_simple")
107new file mode 100644
108index 0000000..1a06c71
109--- /dev/null
110+++ b/gcc/testsuite/gcc.target/arm/pr48252.c
111@@ -0,0 +1,31 @@
112+/* { dg-do run } */
113+/* { dg-require-effective-target arm_neon_hw } */
114+/* { dg-options "-O2" } */
115+/* { dg-add-options arm_neon } */
116+
117+#include "arm_neon.h"
118+#include <stdlib.h>
119+
120+int main(void)
121+{
122+ uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1};
123+ uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2};
124+ uint8x8x2_t vd1, vd2;
125+ union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
126+ int i;
127+
128+ vd1 = vzip_u8(v1, vdup_n_u8(0));
129+ vd2 = vzip_u8(v2, vdup_n_u8(0));
130+
131+ vst1_u8(d1.buf, vd1.val[0]);
132+ vst1_u8(d2.buf, vd1.val[1]);
133+ vst1_u8(d3.buf, vd2.val[0]);
134+ vst1_u8(d4.buf, vd2.val[1]);
135+
136+ for (i = 0; i < 8; i++)
137+ if ((i % 2 == 0 && d4.buf[i] != 2)
138+ || (i % 2 == 1 && d4.buf[i] != 0))
139+ abort ();
140+
141+ return 0;
142+}
143--
1441.7.0.4
145
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