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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.5.1/pr30961.dpatch179
1 files changed, 0 insertions, 179 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.5.1/pr30961.dpatch b/meta/recipes-devtools/gcc/gcc-4.5.1/pr30961.dpatch
deleted file mode 100644
index b20fdf5bf5..0000000000
--- a/meta/recipes-devtools/gcc/gcc-4.5.1/pr30961.dpatch
+++ /dev/null
@@ -1,179 +0,0 @@
1#! /bin/sh -e
2
3# DP: <your description>
4
5dir=
6if [ $# -eq 3 -a "$2" = '-d' ]; then
7 pdir="-d $3"
8 dir="$3/"
9elif [ $# -ne 1 ]; then
10 echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
11 exit 1
12fi
13case "$1" in
14 -patch)
15 patch $pdir -f --no-backup-if-mismatch -p0 < $0
16 ;;
17 -unpatch)
18 patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
19 ;;
20 *)
21 echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
22 exit 1
23esac
24exit 0
25
26From: "H.J. Lu" <hjl@lucon.org>
27Sender: gcc-patches-owner@gcc.gnu.org
28To: gcc-patches@gcc.gnu.org
29Subject: PATCH: PR target/30961: [4.1/4.2/4.3 regression] redundant reg/mem stores/moves
30Date: Mon, 27 Aug 2007 11:34:12 -0700
31
32We start with
33
34(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
35
36(insn:HI 6 3 10 2 c.c:3 (set (reg:DF 58 [ <result> ])
37 (subreg:DF (reg/v:DI 59 [ in ]) 0)) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg/v:DI 59 [ in ])
38 (nil)))
39
40(insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ])
41 (reg:DF 58 [ <result> ])) 102 {*movdf_integer_rex64} (expr_list:REG_DEAD (reg:DF 58 [ <result> ])
42 (nil)))
43
44(insn:HI 16 10 0 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
45
46we are trying to allocate registers for insn 6 and we allocate
47xmm0 for the return value. Reload doesn't check if xmm0 can be used for
48DF 59, it allocates xmm1 for DF 59 and generates:
49
50Reloads for insn # 6
51Reload 0: reload_in (DF) = (reg:DF 5 di)
52 SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
53 reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0)
54 reload_reg_rtx: (reg:DF 22 xmm1)
55...
56
57(note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
58
59(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
60
61(insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp)
62 (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])
63 (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil))
64
65(insn 23 22 6 2 c.c:3 (set (reg:DF 22 xmm1)
66 (mem/c:DF (plus:DI (reg/f:DI 7 sp)
67 (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil))
68
69(insn:HI 6 23 16 2 c.c:3 (set (reg:DF 21 xmm0 [orig:58 <result> ] [58])
70 (reg:DF 22 xmm1)) 102 {*movdf_integer_rex64} (nil))
71
72(insn 16 6 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
73
74This patch tries to use the destination register when reloading for input. It
75generates
76
77Reloads for insn # 6
78Reload 0: reload_in (DF) = (reg:DF 5 di)
79 SSE_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
80 reload_in_reg: (subreg:DF (reg/v:DI 5 di [orig:59 in ] [59]) 0)
81 reload_reg_rtx: (reg:DF 21 xmm0)
82...
83(note:HI 4 1 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
84
85(note:HI 3 4 22 2 NOTE_INSN_FUNCTION_BEG)
86
87(insn 22 3 23 2 c.c:3 (set (mem/c:DF (plus:DI (reg/f:DI 7 sp)
88 (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])
89 (reg:DF 5 di)) 102 {*movdf_integer_rex64} (nil))
90
91(insn 23 22 6 2 c.c:3 (set (reg:DF 21 xmm0)
92 (mem/c:DF (plus:DI (reg/f:DI 7 sp)
93 (const_int -8 [0xfffffffffffffff8])) [0 S8 A8])) 102 {*movdf_integer_rex64} (nil))
94
95(insn:HI 6 23 10 2 c.c:3 (set (reg:DF 22 xmm1 [orig:58 <result> ] [58])
96 (reg:DF 21 xmm0)) 102 {*movdf_integer_rex64} (nil))
97
98(insn:HI 10 6 16 2 c.c:7 (set (reg/i:DF 21 xmm0 [ <result> ])
99 (reg:DF 22 xmm1 [orig:58 <result> ] [58])) 102 {*movdf_integer_rex64} (nil))
100
101(insn 16 10 21 2 c.c:7 (use (reg/i:DF 21 xmm0 [ <result> ])) -1 (nil))
102
103
104H.J.
105----
106gcc/
107
1082007-08-27 H.J. Lu <hongjiu.lu@intel.com>
109
110 PR target/30961
111 * reload1.c (find_reg): Favor the hard register in destination
112 if it is usable and a memory location is needed for reload
113 input.
114
115gcc/testsuite/
116
1172007-08-27 H.J. Lu <hongjiu.lu@intel.com>
118
119 PR target/30961
120 * gcc.target/i386/pr30961-1.c: New.
121
122--- gcc/reload1.c.second 2007-08-27 09:35:08.000000000 -0700
123+++ gcc/reload1.c 2007-08-27 09:36:33.000000000 -0700
124@@ -1781,6 +1781,20 @@ find_reg (struct insn_chain *chain, int
125 HARD_REG_SET not_usable;
126 HARD_REG_SET used_by_other_reload;
127 reg_set_iterator rsi;
128+#ifdef SECONDARY_MEMORY_NEEDED
129+ rtx body = PATTERN (chain->insn);
130+ unsigned int dest_reg = FIRST_PSEUDO_REGISTER;
131+
132+ if (GET_CODE (body) == SET)
133+ {
134+ rtx dest = SET_DEST (body);
135+
136+ if ((REG_P (dest)
137+ || (GET_CODE (dest) == SUBREG
138+ && REG_P (SUBREG_REG (dest)))))
139+ dest_reg = reg_or_subregno (dest);
140+ }
141+#endif
142
143 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
144 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
145@@ -1821,6 +1835,18 @@ find_reg (struct insn_chain *chain, int
146 this_cost--;
147 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
148 this_cost--;
149+#ifdef SECONDARY_MEMORY_NEEDED
150+ /* If a memory location is needed for rl->in and dest_reg
151+ is usable, we will favor it. */
152+ else if (dest_reg == regno
153+ && rl->in
154+ && REG_P (rl->in)
155+ && REGNO (rl->in) < FIRST_PSEUDO_REGISTER
156+ && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (rl->in)),
157+ rl->class,
158+ rl->mode))
159+ this_cost = 0;
160+#endif
161 if (this_cost < best_cost
162 /* Among registers with equal cost, prefer caller-saved ones, or
163 use REG_ALLOC_ORDER if it is defined. */
164--- gcc/testsuite/gcc.target/i386/pr30961-1.c.second 2007-08-27 11:01:59.000000000 -0700
165+++ gcc/testsuite/gcc.target/i386/pr30961-1.c 2007-08-27 11:02:51.000000000 -0700
166@@ -0,0 +1,13 @@
167+/* { dg-do compile } */
168+/* { dg-require-effective-target lp64 } */
169+/* { dg-options "-O2" } */
170+
171+double
172+convert (long long in)
173+{
174+ double f;
175+ __builtin_memcpy( &f, &in, sizeof( in ) );
176+ return f;
177+}
178+
179+/* { dg-final { scan-assembler-not "movapd" } } */
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