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-rw-r--r--meta/recipes-devtools/elfutils/elfutils-0.160/arm_backend.diff625
1 files changed, 625 insertions, 0 deletions
diff --git a/meta/recipes-devtools/elfutils/elfutils-0.160/arm_backend.diff b/meta/recipes-devtools/elfutils/elfutils-0.160/arm_backend.diff
new file mode 100644
index 0000000000..c97c4e470d
--- /dev/null
+++ b/meta/recipes-devtools/elfutils/elfutils-0.160/arm_backend.diff
@@ -0,0 +1,625 @@
1From 0db1687eee0b4d16ccbc40db5a06b574fca6614c Mon Sep 17 00:00:00 2001
2From: Hongxu Jia <hongxu.jia@windriver.com>
3Date: Fri, 14 Nov 2014 15:25:42 +0800
4Subject: [PATCH] Rebase arm_backend.diff from 0.159 to 0.160
5
6Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
7---
8 backends/arm_init.c | 18 ++++-
9 backends/arm_regs.c | 132 ++++++++++++++++++++++++++++++++++++
10 backends/arm_retval.c | 44 +++++++++++-
11 backends/libebl_arm.h | 9 +++
12 libelf/elf.h | 11 +++
13 tests/run-addrcfi.sh | 93 ++++++++++++++++++++++++-
14 tests/run-allregs.sh | 95 +++++++++++++++++++++++++-
15 tests/run-readelf-mixed-corenote.sh | 11 ++-
16 8 files changed, 401 insertions(+), 12 deletions(-)
17 create mode 100644 backends/libebl_arm.h
18
19diff --git a/backends/arm_init.c b/backends/arm_init.c
20index 3283c97..8b57d3f 100644
21--- a/backends/arm_init.c
22+++ b/backends/arm_init.c
23@@ -35,21 +35,32 @@
24 #define RELOC_PREFIX R_ARM_
25 #include "libebl_CPU.h"
26
27+#include "libebl_arm.h"
28+
29 /* This defines the common reloc hooks based on arm_reloc.def. */
30 #include "common-reloc.c"
31
32
33 const char *
34 arm_init (elf, machine, eh, ehlen)
35- Elf *elf __attribute__ ((unused));
36+ Elf *elf;
37 GElf_Half machine __attribute__ ((unused));
38 Ebl *eh;
39 size_t ehlen;
40 {
41+ int soft_float = 0;
42+
43 /* Check whether the Elf_BH object has a sufficent size. */
44 if (ehlen < sizeof (Ebl))
45 return NULL;
46
47+ if (elf) {
48+ GElf_Ehdr ehdr_mem;
49+ GElf_Ehdr *ehdr = gelf_getehdr (elf, &ehdr_mem);
50+ if (ehdr && (ehdr->e_flags & EF_ARM_SOFT_FLOAT))
51+ soft_float = 1;
52+ }
53+
54 /* We handle it. */
55 eh->name = "ARM";
56 arm_init_reloc (eh);
57@@ -61,7 +72,10 @@ arm_init (elf, machine, eh, ehlen)
58 HOOK (eh, core_note);
59 HOOK (eh, auxv_info);
60 HOOK (eh, check_object_attribute);
61- HOOK (eh, return_value_location);
62+ if (soft_float)
63+ eh->return_value_location = arm_return_value_location_soft;
64+ else
65+ eh->return_value_location = arm_return_value_location_hard;
66 HOOK (eh, abi_cfi);
67 HOOK (eh, check_reloc_target_type);
68
69diff --git a/backends/arm_regs.c b/backends/arm_regs.c
70index 21c5ad3..4ee1039 100644
71--- a/backends/arm_regs.c
72+++ b/backends/arm_regs.c
73@@ -31,6 +31,7 @@
74 #endif
75
76 #include <string.h>
77+#include <stdio.h>
78 #include <dwarf.h>
79
80 #define BACKEND arm_
81@@ -76,6 +77,9 @@ arm_register_info (Ebl *ebl __attribute__ ((unused)),
82 break;
83
84 case 16 + 0 ... 16 + 7:
85+ /* AADWARF says that there are no registers in that range,
86+ * but gcc maps FPA registers here
87+ */
88 regno += 96 - 16;
89 /* Fall through. */
90 case 96 + 0 ... 96 + 7:
91@@ -87,11 +91,139 @@ arm_register_info (Ebl *ebl __attribute__ ((unused)),
92 namelen = 2;
93 break;
94
95+ case 64 + 0 ... 64 + 9:
96+ *setname = "VFP";
97+ *bits = 32;
98+ *type = DW_ATE_float;
99+ name[0] = 's';
100+ name[1] = regno - 64 + '0';
101+ namelen = 2;
102+ break;
103+
104+ case 64 + 10 ... 64 + 31:
105+ *setname = "VFP";
106+ *bits = 32;
107+ *type = DW_ATE_float;
108+ name[0] = 's';
109+ name[1] = (regno - 64) / 10 + '0';
110+ name[2] = (regno - 64) % 10 + '0';
111+ namelen = 3;
112+ break;
113+
114+ case 104 + 0 ... 104 + 7:
115+ /* XXX TODO:
116+ * This can be either intel wireless MMX general purpose/control
117+ * registers or xscale accumulator, which have different usage.
118+ * We only have the intel wireless MMX here now.
119+ * The name needs to be changed for the xscale accumulator too. */
120+ *setname = "MMX";
121+ *type = DW_ATE_unsigned;
122+ *bits = 32;
123+ memcpy(name, "wcgr", 4);
124+ name[4] = regno - 104 + '0';
125+ namelen = 5;
126+ break;
127+
128+ case 112 + 0 ... 112 + 9:
129+ *setname = "MMX";
130+ *type = DW_ATE_unsigned;
131+ *bits = 64;
132+ name[0] = 'w';
133+ name[1] = 'r';
134+ name[2] = regno - 112 + '0';
135+ namelen = 3;
136+ break;
137+
138+ case 112 + 10 ... 112 + 15:
139+ *setname = "MMX";
140+ *type = DW_ATE_unsigned;
141+ *bits = 64;
142+ name[0] = 'w';
143+ name[1] = 'r';
144+ name[2] = '1';
145+ name[3] = regno - 112 - 10 + '0';
146+ namelen = 4;
147+ break;
148+
149 case 128:
150+ *setname = "state";
151 *type = DW_ATE_unsigned;
152 return stpcpy (name, "spsr") + 1 - name;
153
154+ case 129:
155+ *setname = "state";
156+ *type = DW_ATE_unsigned;
157+ return stpcpy(name, "spsr_fiq") + 1 - name;
158+
159+ case 130:
160+ *setname = "state";
161+ *type = DW_ATE_unsigned;
162+ return stpcpy(name, "spsr_irq") + 1 - name;
163+
164+ case 131:
165+ *setname = "state";
166+ *type = DW_ATE_unsigned;
167+ return stpcpy(name, "spsr_abt") + 1 - name;
168+
169+ case 132:
170+ *setname = "state";
171+ *type = DW_ATE_unsigned;
172+ return stpcpy(name, "spsr_und") + 1 - name;
173+
174+ case 133:
175+ *setname = "state";
176+ *type = DW_ATE_unsigned;
177+ return stpcpy(name, "spsr_svc") + 1 - name;
178+
179+ case 144 ... 150:
180+ *setname = "integer";
181+ *type = DW_ATE_signed;
182+ *bits = 32;
183+ return sprintf(name, "r%d_usr", regno - 144 + 8) + 1;
184+
185+ case 151 ... 157:
186+ *setname = "integer";
187+ *type = DW_ATE_signed;
188+ *bits = 32;
189+ return sprintf(name, "r%d_fiq", regno - 151 + 8) + 1;
190+
191+ case 158 ... 159:
192+ *setname = "integer";
193+ *type = DW_ATE_signed;
194+ *bits = 32;
195+ return sprintf(name, "r%d_irq", regno - 158 + 13) + 1;
196+
197+ case 160 ... 161:
198+ *setname = "integer";
199+ *type = DW_ATE_signed;
200+ *bits = 32;
201+ return sprintf(name, "r%d_abt", regno - 160 + 13) + 1;
202+
203+ case 162 ... 163:
204+ *setname = "integer";
205+ *type = DW_ATE_signed;
206+ *bits = 32;
207+ return sprintf(name, "r%d_und", regno - 162 + 13) + 1;
208+
209+ case 164 ... 165:
210+ *setname = "integer";
211+ *type = DW_ATE_signed;
212+ *bits = 32;
213+ return sprintf(name, "r%d_svc", regno - 164 + 13) + 1;
214+
215+ case 192 ... 199:
216+ *setname = "MMX";
217+ *bits = 32;
218+ *type = DW_ATE_unsigned;
219+ name[0] = 'w';
220+ name[1] = 'c';
221+ name[2] = regno - 192 + '0';
222+ namelen = 3;
223+ break;
224+
225 case 256 + 0 ... 256 + 9:
226+ /* XXX TODO: Neon also uses those registers and can contain
227+ * both float and integers */
228 *setname = "VFP";
229 *type = DW_ATE_float;
230 *bits = 64;
231diff --git a/backends/arm_retval.c b/backends/arm_retval.c
232index 7aced74..052132e 100644
233--- a/backends/arm_retval.c
234+++ b/backends/arm_retval.c
235@@ -48,6 +48,13 @@ static const Dwarf_Op loc_intreg[] =
236 #define nloc_intreg 1
237 #define nloc_intregs(n) (2 * (n))
238
239+/* f1 */ /* XXX TODO: f0 can also have number 96 if program was compiled with -mabi=aapcs */
240+static const Dwarf_Op loc_fpreg[] =
241+ {
242+ { .atom = DW_OP_reg16 },
243+ };
244+#define nloc_fpreg 1
245+
246 /* The return value is a structure and is actually stored in stack space
247 passed in a hidden argument by the caller. But, the compiler
248 helpfully returns the address of that space in r0. */
249@@ -58,8 +65,9 @@ static const Dwarf_Op loc_aggregate[] =
250 #define nloc_aggregate 1
251
252
253-int
254-arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
255+static int
256+arm_return_value_location_ (Dwarf_Die *functypedie, const Dwarf_Op **locp,
257+ int soft_float)
258 {
259 /* Start with the function's type, and get the DW_AT_type attribute,
260 which is the type of the return value. */
261@@ -98,14 +106,31 @@ arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
262 else
263 return -1;
264 }
265+ if (tag == DW_TAG_base_type)
266+ {
267+ Dwarf_Word encoding;
268+ if (dwarf_formudata (dwarf_attr_integrate (typedie, DW_AT_encoding,
269+ &attr_mem), &encoding) != 0)
270+ return -1;
271+
272+ if ((encoding == DW_ATE_float) && !soft_float)
273+ {
274+ *locp = loc_fpreg;
275+ if (size <= 8)
276+ return nloc_fpreg;
277+ goto aggregate;
278+ }
279+ }
280 if (size <= 16)
281 {
282 intreg:
283 *locp = loc_intreg;
284 return size <= 4 ? nloc_intreg : nloc_intregs ((size + 3) / 4);
285 }
286+ /* fall through. */
287
288 aggregate:
289+ /* XXX TODO sometimes aggregates are returned in r0 (-mabi=aapcs) */
290 *locp = loc_aggregate;
291 return nloc_aggregate;
292 }
293@@ -125,3 +150,18 @@ arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
294 DWARF and might be valid. */
295 return -2;
296 }
297+
298+/* return location for -mabi=apcs-gnu -msoft-float */
299+int
300+arm_return_value_location_soft (Dwarf_Die *functypedie, const Dwarf_Op **locp)
301+{
302+ return arm_return_value_location_ (functypedie, locp, 1);
303+}
304+
305+/* return location for -mabi=apcs-gnu -mhard-float (current default) */
306+int
307+arm_return_value_location_hard (Dwarf_Die *functypedie, const Dwarf_Op **locp)
308+{
309+ return arm_return_value_location_ (functypedie, locp, 0);
310+}
311+
312diff --git a/backends/libebl_arm.h b/backends/libebl_arm.h
313new file mode 100644
314index 0000000..c00770c
315--- /dev/null
316+++ b/backends/libebl_arm.h
317@@ -0,0 +1,9 @@
318+#ifndef _LIBEBL_ARM_H
319+#define _LIBEBL_ARM_H 1
320+
321+#include <libdw.h>
322+
323+extern int arm_return_value_location_soft(Dwarf_Die *, const Dwarf_Op **locp);
324+extern int arm_return_value_location_hard(Dwarf_Die *, const Dwarf_Op **locp);
325+
326+#endif
327diff --git a/libelf/elf.h b/libelf/elf.h
328index a3cce3e..0891674 100644
329--- a/libelf/elf.h
330+++ b/libelf/elf.h
331@@ -2346,6 +2346,9 @@ typedef Elf32_Addr Elf32_Conflict;
332 #define EF_ARM_EABI_VER4 0x04000000
333 #define EF_ARM_EABI_VER5 0x05000000
334
335+/* EI_OSABI values */
336+#define ELFOSABI_ARM_AEABI 64 /* Contains symbol versioning. */
337+
338 /* Additional symbol types for Thumb. */
339 #define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
340 #define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
341@@ -2363,12 +2366,19 @@ typedef Elf32_Addr Elf32_Conflict;
342
343 /* Processor specific values for the Phdr p_type field. */
344 #define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */
345+#define PT_ARM_UNWIND PT_ARM_EXIDX
346
347 /* Processor specific values for the Shdr sh_type field. */
348 #define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */
349 #define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */
350 #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */
351
352+/* Processor specific values for the Dyn d_tag field. */
353+#define DT_ARM_RESERVED1 (DT_LOPROC + 0)
354+#define DT_ARM_SYMTABSZ (DT_LOPROC + 1)
355+#define DT_ARM_PREEMTMAB (DT_LOPROC + 2)
356+#define DT_ARM_RESERVED2 (DT_LOPROC + 3)
357+#define DT_ARM_NUM 4
358
359 /* AArch64 relocs. */
360
361@@ -2647,6 +2657,7 @@ typedef Elf32_Addr Elf32_Conflict;
362 TLS block (LDR, STR). */
363 #define R_ARM_TLS_IE12GP 111 /* 12 bit GOT entry relative
364 to GOT origin (LDR). */
365+/* 112 - 127 private range */
366 #define R_ARM_ME_TOO 128 /* Obsolete. */
367 #define R_ARM_THM_TLS_DESCSEQ 129
368 #define R_ARM_THM_TLS_DESCSEQ16 129
369diff --git a/tests/run-addrcfi.sh b/tests/run-addrcfi.sh
370index 5d33246..78464a8 100755
371--- a/tests/run-addrcfi.sh
372+++ b/tests/run-addrcfi.sh
373@@ -2530,6 +2530,38 @@ dwarf_cfi_addrframe (.eh_frame): no matching address range
374 FPA reg21 (f5): undefined
375 FPA reg22 (f6): undefined
376 FPA reg23 (f7): undefined
377+ VFP reg64 (s0): undefined
378+ VFP reg65 (s1): undefined
379+ VFP reg66 (s2): undefined
380+ VFP reg67 (s3): undefined
381+ VFP reg68 (s4): undefined
382+ VFP reg69 (s5): undefined
383+ VFP reg70 (s6): undefined
384+ VFP reg71 (s7): undefined
385+ VFP reg72 (s8): undefined
386+ VFP reg73 (s9): undefined
387+ VFP reg74 (s10): undefined
388+ VFP reg75 (s11): undefined
389+ VFP reg76 (s12): undefined
390+ VFP reg77 (s13): undefined
391+ VFP reg78 (s14): undefined
392+ VFP reg79 (s15): undefined
393+ VFP reg80 (s16): undefined
394+ VFP reg81 (s17): undefined
395+ VFP reg82 (s18): undefined
396+ VFP reg83 (s19): undefined
397+ VFP reg84 (s20): undefined
398+ VFP reg85 (s21): undefined
399+ VFP reg86 (s22): undefined
400+ VFP reg87 (s23): undefined
401+ VFP reg88 (s24): undefined
402+ VFP reg89 (s25): undefined
403+ VFP reg90 (s26): undefined
404+ VFP reg91 (s27): undefined
405+ VFP reg92 (s28): undefined
406+ VFP reg93 (s29): undefined
407+ VFP reg94 (s30): undefined
408+ VFP reg95 (s31): undefined
409 FPA reg96 (f0): undefined
410 FPA reg97 (f1): undefined
411 FPA reg98 (f2): undefined
412@@ -2538,7 +2570,66 @@ dwarf_cfi_addrframe (.eh_frame): no matching address range
413 FPA reg101 (f5): undefined
414 FPA reg102 (f6): undefined
415 FPA reg103 (f7): undefined
416- integer reg128 (spsr): undefined
417+ MMX reg104 (wcgr0): undefined
418+ MMX reg105 (wcgr1): undefined
419+ MMX reg106 (wcgr2): undefined
420+ MMX reg107 (wcgr3): undefined
421+ MMX reg108 (wcgr4): undefined
422+ MMX reg109 (wcgr5): undefined
423+ MMX reg110 (wcgr6): undefined
424+ MMX reg111 (wcgr7): undefined
425+ MMX reg112 (wr0): undefined
426+ MMX reg113 (wr1): undefined
427+ MMX reg114 (wr2): undefined
428+ MMX reg115 (wr3): undefined
429+ MMX reg116 (wr4): undefined
430+ MMX reg117 (wr5): undefined
431+ MMX reg118 (wr6): undefined
432+ MMX reg119 (wr7): undefined
433+ MMX reg120 (wr8): undefined
434+ MMX reg121 (wr9): undefined
435+ MMX reg122 (wr10): undefined
436+ MMX reg123 (wr11): undefined
437+ MMX reg124 (wr12): undefined
438+ MMX reg125 (wr13): undefined
439+ MMX reg126 (wr14): undefined
440+ MMX reg127 (wr15): undefined
441+ state reg128 (spsr): undefined
442+ state reg129 (spsr_fiq): undefined
443+ state reg130 (spsr_irq): undefined
444+ state reg131 (spsr_abt): undefined
445+ state reg132 (spsr_und): undefined
446+ state reg133 (spsr_svc): undefined
447+ integer reg144 (r8_usr): undefined
448+ integer reg145 (r9_usr): undefined
449+ integer reg146 (r10_usr): undefined
450+ integer reg147 (r11_usr): undefined
451+ integer reg148 (r12_usr): undefined
452+ integer reg149 (r13_usr): undefined
453+ integer reg150 (r14_usr): undefined
454+ integer reg151 (r8_fiq): undefined
455+ integer reg152 (r9_fiq): undefined
456+ integer reg153 (r10_fiq): undefined
457+ integer reg154 (r11_fiq): undefined
458+ integer reg155 (r12_fiq): undefined
459+ integer reg156 (r13_fiq): undefined
460+ integer reg157 (r14_fiq): undefined
461+ integer reg158 (r13_irq): undefined
462+ integer reg159 (r14_irq): undefined
463+ integer reg160 (r13_abt): undefined
464+ integer reg161 (r14_abt): undefined
465+ integer reg162 (r13_und): undefined
466+ integer reg163 (r14_und): undefined
467+ integer reg164 (r13_svc): undefined
468+ integer reg165 (r14_svc): undefined
469+ MMX reg192 (wc0): undefined
470+ MMX reg193 (wc1): undefined
471+ MMX reg194 (wc2): undefined
472+ MMX reg195 (wc3): undefined
473+ MMX reg196 (wc4): undefined
474+ MMX reg197 (wc5): undefined
475+ MMX reg198 (wc6): undefined
476+ MMX reg199 (wc7): undefined
477 VFP reg256 (d0): undefined
478 VFP reg257 (d1): undefined
479 VFP reg258 (d2): undefined
480diff --git a/tests/run-allregs.sh b/tests/run-allregs.sh
481index 6f3862e..13557d5 100755
482--- a/tests/run-allregs.sh
483+++ b/tests/run-allregs.sh
484@@ -2671,7 +2671,28 @@ integer registers:
485 13: sp (sp), address 32 bits
486 14: lr (lr), address 32 bits
487 15: pc (pc), address 32 bits
488- 128: spsr (spsr), unsigned 32 bits
489+ 144: r8_usr (r8_usr), signed 32 bits
490+ 145: r9_usr (r9_usr), signed 32 bits
491+ 146: r10_usr (r10_usr), signed 32 bits
492+ 147: r11_usr (r11_usr), signed 32 bits
493+ 148: r12_usr (r12_usr), signed 32 bits
494+ 149: r13_usr (r13_usr), signed 32 bits
495+ 150: r14_usr (r14_usr), signed 32 bits
496+ 151: r8_fiq (r8_fiq), signed 32 bits
497+ 152: r9_fiq (r9_fiq), signed 32 bits
498+ 153: r10_fiq (r10_fiq), signed 32 bits
499+ 154: r11_fiq (r11_fiq), signed 32 bits
500+ 155: r12_fiq (r12_fiq), signed 32 bits
501+ 156: r13_fiq (r13_fiq), signed 32 bits
502+ 157: r14_fiq (r14_fiq), signed 32 bits
503+ 158: r13_irq (r13_irq), signed 32 bits
504+ 159: r14_irq (r14_irq), signed 32 bits
505+ 160: r13_abt (r13_abt), signed 32 bits
506+ 161: r14_abt (r14_abt), signed 32 bits
507+ 162: r13_und (r13_und), signed 32 bits
508+ 163: r14_und (r14_und), signed 32 bits
509+ 164: r13_svc (r13_svc), signed 32 bits
510+ 165: r14_svc (r14_svc), signed 32 bits
511 FPA registers:
512 16: f0 (f0), float 96 bits
513 17: f1 (f1), float 96 bits
514@@ -2689,7 +2710,72 @@ FPA registers:
515 101: f5 (f5), float 96 bits
516 102: f6 (f6), float 96 bits
517 103: f7 (f7), float 96 bits
518+MMX registers:
519+ 104: wcgr0 (wcgr0), unsigned 32 bits
520+ 105: wcgr1 (wcgr1), unsigned 32 bits
521+ 106: wcgr2 (wcgr2), unsigned 32 bits
522+ 107: wcgr3 (wcgr3), unsigned 32 bits
523+ 108: wcgr4 (wcgr4), unsigned 32 bits
524+ 109: wcgr5 (wcgr5), unsigned 32 bits
525+ 110: wcgr6 (wcgr6), unsigned 32 bits
526+ 111: wcgr7 (wcgr7), unsigned 32 bits
527+ 112: wr0 (wr0), unsigned 64 bits
528+ 113: wr1 (wr1), unsigned 64 bits
529+ 114: wr2 (wr2), unsigned 64 bits
530+ 115: wr3 (wr3), unsigned 64 bits
531+ 116: wr4 (wr4), unsigned 64 bits
532+ 117: wr5 (wr5), unsigned 64 bits
533+ 118: wr6 (wr6), unsigned 64 bits
534+ 119: wr7 (wr7), unsigned 64 bits
535+ 120: wr8 (wr8), unsigned 64 bits
536+ 121: wr9 (wr9), unsigned 64 bits
537+ 122: wr10 (wr10), unsigned 64 bits
538+ 123: wr11 (wr11), unsigned 64 bits
539+ 124: wr12 (wr12), unsigned 64 bits
540+ 125: wr13 (wr13), unsigned 64 bits
541+ 126: wr14 (wr14), unsigned 64 bits
542+ 127: wr15 (wr15), unsigned 64 bits
543+ 192: wc0 (wc0), unsigned 32 bits
544+ 193: wc1 (wc1), unsigned 32 bits
545+ 194: wc2 (wc2), unsigned 32 bits
546+ 195: wc3 (wc3), unsigned 32 bits
547+ 196: wc4 (wc4), unsigned 32 bits
548+ 197: wc5 (wc5), unsigned 32 bits
549+ 198: wc6 (wc6), unsigned 32 bits
550+ 199: wc7 (wc7), unsigned 32 bits
551 VFP registers:
552+ 64: s0 (s0), float 32 bits
553+ 65: s1 (s1), float 32 bits
554+ 66: s2 (s2), float 32 bits
555+ 67: s3 (s3), float 32 bits
556+ 68: s4 (s4), float 32 bits
557+ 69: s5 (s5), float 32 bits
558+ 70: s6 (s6), float 32 bits
559+ 71: s7 (s7), float 32 bits
560+ 72: s8 (s8), float 32 bits
561+ 73: s9 (s9), float 32 bits
562+ 74: s10 (s10), float 32 bits
563+ 75: s11 (s11), float 32 bits
564+ 76: s12 (s12), float 32 bits
565+ 77: s13 (s13), float 32 bits
566+ 78: s14 (s14), float 32 bits
567+ 79: s15 (s15), float 32 bits
568+ 80: s16 (s16), float 32 bits
569+ 81: s17 (s17), float 32 bits
570+ 82: s18 (s18), float 32 bits
571+ 83: s19 (s19), float 32 bits
572+ 84: s20 (s20), float 32 bits
573+ 85: s21 (s21), float 32 bits
574+ 86: s22 (s22), float 32 bits
575+ 87: s23 (s23), float 32 bits
576+ 88: s24 (s24), float 32 bits
577+ 89: s25 (s25), float 32 bits
578+ 90: s26 (s26), float 32 bits
579+ 91: s27 (s27), float 32 bits
580+ 92: s28 (s28), float 32 bits
581+ 93: s29 (s29), float 32 bits
582+ 94: s30 (s30), float 32 bits
583+ 95: s31 (s31), float 32 bits
584 256: d0 (d0), float 64 bits
585 257: d1 (d1), float 64 bits
586 258: d2 (d2), float 64 bits
587@@ -2722,6 +2808,13 @@ VFP registers:
588 285: d29 (d29), float 64 bits
589 286: d30 (d30), float 64 bits
590 287: d31 (d31), float 64 bits
591+state registers:
592+ 128: spsr (spsr), unsigned 32 bits
593+ 129: spsr_fiq (spsr_fiq), unsigned 32 bits
594+ 130: spsr_irq (spsr_irq), unsigned 32 bits
595+ 131: spsr_abt (spsr_abt), unsigned 32 bits
596+ 132: spsr_und (spsr_und), unsigned 32 bits
597+ 133: spsr_svc (spsr_svc), unsigned 32 bits
598 EOF
599
600 # See run-readelf-mixed-corenote.sh for instructions to regenerate
601diff --git a/tests/run-readelf-mixed-corenote.sh b/tests/run-readelf-mixed-corenote.sh
602index 01e4594..9a8a380 100755
603--- a/tests/run-readelf-mixed-corenote.sh
604+++ b/tests/run-readelf-mixed-corenote.sh
605@@ -30,12 +30,11 @@ Note segment of 892 bytes at offset 0x274:
606 pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
607 utime: 0.000000, stime: 0.010000, cutime: 0.000000, cstime: 0.000000
608 orig_r0: -1, fpvalid: 1
609- r0: 1 r1: -1091672508 r2: -1091672500
610- r3: 0 r4: 0 r5: 0
611- r6: 33728 r7: 0 r8: 0
612- r9: 0 r10: -1225703496 r11: -1091672844
613- r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48
614- pc: 0x00008500 spsr: 0x60000010
615+ r0: 1 r1: -1091672508 r2: -1091672500 r3: 0
616+ r4: 0 r5: 0 r6: 33728 r7: 0
617+ r8: 0 r9: 0 r10: -1225703496 r11: -1091672844
618+ r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48 pc: 0x00008500
619+ spsr: 0x60000010
620 CORE 124 PRPSINFO
621 state: 0, sname: R, zomb: 0, nice: 0, flag: 0x00400500
622 uid: 0, gid: 0, pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
623--
6241.9.1
625
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-25 06:47:23 +0000