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-rw-r--r--meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch296
1 files changed, 148 insertions, 148 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch b/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch
index a1999184be..b03bb28237 100644
--- a/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch
+++ b/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch
@@ -16,75 +16,73 @@ Netlogic. Also, update vendor name to NLM wherever applicable.
16 bfd/cpu-mips.c | 6 ++++-- 16 bfd/cpu-mips.c | 6 ++++--
17 bfd/elfxx-mips.c | 8 ++++++++ 17 bfd/elfxx-mips.c | 8 ++++++++
18 binutils/readelf.c | 1 + 18 binutils/readelf.c | 1 +
19 config.sub | 6 ++++++ 19 gas/config/tc-mips.c | 4 +++-
20 gas/config/tc-mips.c | 7 ++++++-
21 gas/configure | 3 +++ 20 gas/configure | 3 +++
22 gas/configure.tgt | 2 +- 21 gas/configure.tgt | 2 +-
23 gas/doc/c-mips.texi | 3 ++-
24 include/elf/mips.h | 1 + 22 include/elf/mips.h | 1 +
25 include/opcode/mips.h | 6 +++++- 23 include/opcode/mips.h | 10 ++++++++--
26 ld/configure.tgt | 2 ++ 24 ld/configure.tgt | 2 ++
27 opcodes/mips-dis.c | 6 ++++++ 25 opcodes/mips-dis.c | 12 +++++-------
28 opcodes/mips-opc.c | 31 ++++++++++++++++++++----------- 26 opcodes/mips-opc.c | 33 +++++++++++++++++++++------------
29 17 files changed, 73 insertions(+), 17 deletions(-) 27 15 files changed, 65 insertions(+), 25 deletions(-)
30 28
31Index: binutils-2.24/bfd/aoutx.h 29diff --git a/bfd/aoutx.h b/bfd/aoutx.h
32=================================================================== 30index 9385a98..a88df99 100644
33--- binutils-2.24.orig/bfd/aoutx.h 2013-12-15 13:07:57.180399300 -0800 31--- a/bfd/aoutx.h
34+++ binutils-2.24/bfd/aoutx.h 2013-12-15 13:08:03.397065919 -0800 32+++ b/bfd/aoutx.h
35@@ -798,6 +798,7 @@ 33@@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
36 case bfd_mach_mipsisa64r2: 34 case bfd_mach_mipsisa64r6:
37 case bfd_mach_mips_sb1: 35 case bfd_mach_mips_sb1:
38 case bfd_mach_mips_xlr: 36 case bfd_mach_mips_xlr:
39+ case bfd_mach_mips_xlp: 37+ case bfd_mach_mips_xlp:
40 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ 38 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
41 arch_flags = M_MIPS2; 39 arch_flags = M_MIPS2;
42 break; 40 break;
43Index: binutils-2.24/bfd/archures.c 41diff --git a/bfd/archures.c b/bfd/archures.c
44=================================================================== 42index c9fd6c8..547bd09 100644
45--- binutils-2.24.orig/bfd/archures.c 2013-12-15 13:07:57.180399300 -0800 43--- a/bfd/archures.c
46+++ binutils-2.24/bfd/archures.c 2013-12-15 13:08:03.397065919 -0800 44+++ b/bfd/archures.c
47@@ -178,6 +178,7 @@ 45@@ -180,6 +180,7 @@ DESCRIPTION
48 .#define bfd_mach_mips_octeonp 6601 46 .#define bfd_mach_mips_octeonp 6601
49 .#define bfd_mach_mips_octeon2 6502 47 .#define bfd_mach_mips_octeon2 6502
50 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} 48 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
51+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *} 49+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
52 .#define bfd_mach_mipsisa32 32 50 .#define bfd_mach_mipsisa32 32
53 .#define bfd_mach_mipsisa32r2 33 51 .#define bfd_mach_mipsisa32r2 33
54 .#define bfd_mach_mipsisa64 64 52 .#define bfd_mach_mipsisa32r3 34
55Index: binutils-2.24/bfd/bfd-in2.h 53diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
56=================================================================== 54index c7a2bb5..413b773 100644
57--- binutils-2.24.orig/bfd/bfd-in2.h 2013-12-15 13:07:57.180399300 -0800 55--- a/bfd/bfd-in2.h
58+++ binutils-2.24/bfd/bfd-in2.h 2013-12-15 13:08:03.400399254 -0800 56+++ b/bfd/bfd-in2.h
59@@ -1933,6 +1933,7 @@ 57@@ -1967,6 +1967,7 @@ enum bfd_architecture
60 #define bfd_mach_mips_octeonp 6601 58 #define bfd_mach_mips_octeonp 6601
61 #define bfd_mach_mips_octeon2 6502 59 #define bfd_mach_mips_octeon2 6502
62 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ 60 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
63+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */ 61+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
64 #define bfd_mach_mipsisa32 32 62 #define bfd_mach_mipsisa32 32
65 #define bfd_mach_mipsisa32r2 33 63 #define bfd_mach_mipsisa32r2 33
66 #define bfd_mach_mipsisa64 64 64 #define bfd_mach_mipsisa32r3 34
67Index: binutils-2.24/bfd/config.bfd 65diff --git a/bfd/config.bfd b/bfd/config.bfd
68=================================================================== 66index 03d2c6f..91cedb8 100644
69--- binutils-2.24.orig/bfd/config.bfd 2013-12-15 13:08:03.047065922 -0800 67--- a/bfd/config.bfd
70+++ binutils-2.24/bfd/config.bfd 2013-12-15 13:08:03.400399254 -0800 68+++ b/bfd/config.bfd
71@@ -1032,6 +1032,11 @@ 69@@ -1041,6 +1041,11 @@ case "${targ}" in
72 targ_defvec=bfd_elf32_littlemips_vec 70 targ_defvec=mips_elf32_le_vec
73 targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" 71 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
74 ;; 72 ;;
75+ mipsisa64*-*-elf*) 73+ mipsisa64*-*-elf*)
76+ targ_defvec=bfd_elf32_tradbigmips_vec 74+ targ_defvec=mips_elf32_trad_be_vec
77+ targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec" 75+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
78+ want64=true 76+ want64=true
79+ ;; 77+ ;;
80 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss) 78 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss)
81 targ_defvec=bfd_elf32_bigmips_vec 79 targ_defvec=mips_elf32_be_vec
82 targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" 80 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
83Index: binutils-2.24/bfd/cpu-mips.c 81diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
84=================================================================== 82index b617aaa..19a99d1 100644
85--- binutils-2.24.orig/bfd/cpu-mips.c 2013-12-15 13:07:57.180399300 -0800 83--- a/bfd/cpu-mips.c
86+++ binutils-2.24/bfd/cpu-mips.c 2013-12-15 13:08:03.400399254 -0800 84+++ b/bfd/cpu-mips.c
87@@ -99,7 +99,8 @@ 85@@ -103,7 +103,8 @@ enum
88 I_mipsocteonp, 86 I_mipsocteonp,
89 I_mipsocteon2, 87 I_mipsocteon2,
90 I_xlr, 88 I_xlr,
@@ -94,7 +92,7 @@ Index: binutils-2.24/bfd/cpu-mips.c
94 }; 92 };
95 93
96 #define NN(index) (&arch_info_struct[(index) + 1]) 94 #define NN(index) (&arch_info_struct[(index) + 1])
97@@ -143,7 +144,8 @@ 95@@ -153,7 +154,8 @@ static const bfd_arch_info_type arch_info_struct[] =
98 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)), 96 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
99 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)), 97 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
100 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), 98 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
@@ -104,11 +102,11 @@ Index: binutils-2.24/bfd/cpu-mips.c
104 }; 102 };
105 103
106 /* The default architecture is mips:3000, but with a machine number of 104 /* The default architecture is mips:3000, but with a machine number of
107Index: binutils-2.24/bfd/elfxx-mips.c 105diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
108=================================================================== 106index a0cc26e..672d5b3 100644
109--- binutils-2.24.orig/bfd/elfxx-mips.c 2013-12-15 13:07:57.180399300 -0800 107--- a/bfd/elfxx-mips.c
110+++ binutils-2.24/bfd/elfxx-mips.c 2013-12-15 13:08:03.400399254 -0800 108+++ b/bfd/elfxx-mips.c
111@@ -6404,6 +6404,9 @@ 109@@ -6608,6 +6608,9 @@ _bfd_elf_mips_mach (flagword flags)
112 case E_MIPS_MACH_XLR: 110 case E_MIPS_MACH_XLR:
113 return bfd_mach_mips_xlr; 111 return bfd_mach_mips_xlr;
114 112
@@ -118,7 +116,7 @@ Index: binutils-2.24/bfd/elfxx-mips.c
118 default: 116 default:
119 switch (flags & EF_MIPS_ARCH) 117 switch (flags & EF_MIPS_ARCH)
120 { 118 {
121@@ -11622,6 +11625,10 @@ 119@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
122 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; 120 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
123 break; 121 break;
124 122
@@ -129,31 +127,31 @@ Index: binutils-2.24/bfd/elfxx-mips.c
129 case bfd_mach_mipsisa32: 127 case bfd_mach_mipsisa32:
130 val = E_MIPS_ARCH_32; 128 val = E_MIPS_ARCH_32;
131 break; 129 break;
132@@ -14202,6 +14209,7 @@ 130@@ -14753,6 +14760,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
133 { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
134 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, 131 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
135 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, 132 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
133 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
136+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, 134+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
137 135
138 /* MIPS64 extensions. */ 136 /* MIPS64 extensions. */
139 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, 137 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
140Index: binutils-2.24/binutils/readelf.c 138diff --git a/binutils/readelf.c b/binutils/readelf.c
141=================================================================== 139index 0c00b2f..6e9d5e4 100644
142--- binutils-2.24.orig/binutils/readelf.c 2013-12-15 13:07:57.180399300 -0800 140--- a/binutils/readelf.c
143+++ binutils-2.24/binutils/readelf.c 2013-12-15 13:08:03.403732587 -0800 141+++ b/binutils/readelf.c
144@@ -2602,6 +2602,7 @@ 142@@ -2898,6 +2898,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
145 case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
146 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; 143 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
144 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
147 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; 145 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
148+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break; 146+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
149 case 0: 147 case 0:
150 /* We simply ignore the field in this case to avoid confusion: 148 /* We simply ignore the field in this case to avoid confusion:
151 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU 149 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
152Index: binutils-2.24/gas/config/tc-mips.c 150diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
153=================================================================== 151index c3e3e2a..8d64344 100644
154--- binutils-2.24.orig/gas/config/tc-mips.c 2013-12-15 13:07:57.180399300 -0800 152--- a/gas/config/tc-mips.c
155+++ binutils-2.24/gas/config/tc-mips.c 2013-12-15 13:17:19.943728439 -0800 153+++ b/gas/config/tc-mips.c
156@@ -486,6 +486,7 @@ 154@@ -551,6 +551,7 @@ static int mips_32bitmode = 0;
157 || mips_opts.arch == CPU_RM7000 \ 155 || mips_opts.arch == CPU_RM7000 \
158 || mips_opts.arch == CPU_VR5500 \ 156 || mips_opts.arch == CPU_VR5500 \
159 || mips_opts.micromips \ 157 || mips_opts.micromips \
@@ -161,7 +159,7 @@ Index: binutils-2.24/gas/config/tc-mips.c
161 ) 159 )
162 160
163 /* Whether the processor uses hardware interlocks to protect reads 161 /* Whether the processor uses hardware interlocks to protect reads
164@@ -515,6 +516,7 @@ 162@@ -580,6 +581,7 @@ static int mips_32bitmode = 0;
165 && mips_opts.isa != ISA_MIPS3) \ 163 && mips_opts.isa != ISA_MIPS3) \
166 || mips_opts.arch == CPU_R4300 \ 164 || mips_opts.arch == CPU_R4300 \
167 || mips_opts.micromips \ 165 || mips_opts.micromips \
@@ -169,7 +167,7 @@ Index: binutils-2.24/gas/config/tc-mips.c
169 ) 167 )
170 168
171 /* Whether the processor uses hardware interlocks to protect reads 169 /* Whether the processor uses hardware interlocks to protect reads
172@@ -17794,7 +17796,7 @@ 170@@ -18682,7 +18684,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
173 /* Broadcom XLP. 171 /* Broadcom XLP.
174 XLP is mostly like XLR, with the prominent exception that it is 172 XLP is mostly like XLR, with the prominent exception that it is
175 MIPS64R2 rather than MIPS64. */ 173 MIPS64R2 rather than MIPS64. */
@@ -178,13 +176,13 @@ Index: binutils-2.24/gas/config/tc-mips.c
178 176
179 /* End marker */ 177 /* End marker */
180 { NULL, 0, 0, 0, 0 } 178 { NULL, 0, 0, 0, 0 }
181Index: binutils-2.24/gas/configure 179diff --git a/gas/configure b/gas/configure
182=================================================================== 180index 9529f1a..63bba5b 100755
183--- binutils-2.24.orig/gas/configure 2013-12-15 13:08:01.127065936 -0800 181--- a/gas/configure
184+++ binutils-2.24/gas/configure 2013-12-15 13:08:03.407065920 -0800 182+++ b/gas/configure
185@@ -12697,6 +12697,9 @@ 183@@ -12808,6 +12808,9 @@ _ACEOF
186 mipsisa64r2 | mipsisa64r2el) 184 mipsisa64r6 | mipsisa64r6el)
187 mips_cpu=mips64r2 185 mips_cpu=mips64r6
188 ;; 186 ;;
189+ mipsisa64r2nlm | mipsisa64r2nlmel) 187+ mipsisa64r2nlm | mipsisa64r2nlmel)
190+ mips_cpu=xlp 188+ mips_cpu=xlp
@@ -192,36 +190,36 @@ Index: binutils-2.24/gas/configure
192 mipstx39 | mipstx39el) 190 mipstx39 | mipstx39el)
193 mips_cpu=r3900 191 mips_cpu=r3900
194 ;; 192 ;;
195Index: binutils-2.24/gas/configure.tgt 193diff --git a/gas/configure.tgt b/gas/configure.tgt
196=================================================================== 194index 05546ca..bb859d6 100644
197--- binutils-2.24.orig/gas/configure.tgt 2013-12-15 13:08:00.783732605 -0800 195--- a/gas/configure.tgt
198+++ binutils-2.24/gas/configure.tgt 2013-12-15 13:08:03.407065920 -0800 196+++ b/gas/configure.tgt
199@@ -325,7 +325,7 @@ 197@@ -332,7 +332,7 @@ case ${generic_target} in
200 fmt=elf em=freebsd ;;
201 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; 198 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;;
202 mips*-sde-elf* | mips*-mti-elf*) fmt=elf em=tmips ;; 199 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
200 fmt=elf em=tmips ;;
203- mips-*-elf* | mips-*-rtems*) fmt=elf ;; 201- mips-*-elf* | mips-*-rtems*) fmt=elf ;;
204+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;; 202+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;;
205 mips-*-netbsd*) fmt=elf em=tmips ;; 203 mips-*-netbsd*) fmt=elf em=tmips ;;
206 mips-*-openbsd*) fmt=elf em=tmips ;; 204 mips-*-openbsd*) fmt=elf em=tmips ;;
207 205
208Index: binutils-2.24/include/elf/mips.h 206diff --git a/include/elf/mips.h b/include/elf/mips.h
209=================================================================== 207index 2ed6acd..899b1e5 100644
210--- binutils-2.24.orig/include/elf/mips.h 2013-12-15 13:07:57.180399300 -0800 208--- a/include/elf/mips.h
211+++ binutils-2.24/include/elf/mips.h 2013-12-15 13:08:03.407065920 -0800 209+++ b/include/elf/mips.h
212@@ -274,6 +274,7 @@ 210@@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
213 #define E_MIPS_MACH_SB1 0x008a0000 211 #define E_MIPS_MACH_SB1 0x008a0000
214 #define E_MIPS_MACH_OCTEON 0x008b0000 212 #define E_MIPS_MACH_OCTEON 0x008b0000
215 #define E_MIPS_MACH_XLR 0x008c0000 213 #define E_MIPS_MACH_XLR 0x008c0000
216+#define E_MIPS_MACH_XLP 0x008e0000 214+#define E_MIPS_MACH_XLP 0x008f0000
217 #define E_MIPS_MACH_OCTEON2 0x008d0000 215 #define E_MIPS_MACH_OCTEON2 0x008d0000
216 #define E_MIPS_MACH_OCTEON3 0x008e0000
218 #define E_MIPS_MACH_5400 0x00910000 217 #define E_MIPS_MACH_5400 0x00910000
219 #define E_MIPS_MACH_5900 0x00920000 218diff --git a/include/opcode/mips.h b/include/opcode/mips.h
220Index: binutils-2.24/include/opcode/mips.h 219index ef26167..ef53ec6 100644
221=================================================================== 220--- a/include/opcode/mips.h
222--- binutils-2.24.orig/include/opcode/mips.h 2013-12-15 13:07:57.180399300 -0800 221+++ b/include/opcode/mips.h
223+++ binutils-2.24/include/opcode/mips.h 2013-12-15 13:40:11.130384844 -0800 222@@ -1227,8 +1227,10 @@ static const unsigned int mips_isa_table[] = {
224@@ -1092,8 +1092,10 @@
225 #define INSN_LOONGSON_2F 0x80000000 223 #define INSN_LOONGSON_2F 0x80000000
226 /* Loongson 3A. */ 224 /* Loongson 3A. */
227 #define INSN_LOONGSON_3A 0x00000400 225 #define INSN_LOONGSON_3A 0x00000400
@@ -234,7 +232,7 @@ Index: binutils-2.24/include/opcode/mips.h
234 232
235 /* DSP ASE */ 233 /* DSP ASE */
236 #define ASE_DSP 0x00000001 234 #define ASE_DSP 0x00000001
237@@ -1172,6 +1174,7 @@ 235@@ -1324,6 +1326,7 @@ static const unsigned int mips_isa_table[] = {
238 #define CPU_OCTEONP 6601 236 #define CPU_OCTEONP 6601
239 #define CPU_OCTEON2 6502 237 #define CPU_OCTEON2 6502
240 #define CPU_XLR 887682 /* decimal 'XLR' */ 238 #define CPU_XLR 887682 /* decimal 'XLR' */
@@ -242,9 +240,9 @@ Index: binutils-2.24/include/opcode/mips.h
242 240
243 /* Return true if the given CPU is included in INSN_* mask MASK. */ 241 /* Return true if the given CPU is included in INSN_* mask MASK. */
244 242
245@@ -1239,6 +1242,9 @@ 243@@ -1398,6 +1401,9 @@ cpu_is_member (int cpu, unsigned int mask)
246 case CPU_XLR: 244 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
247 return (mask & INSN_XLR) != 0; 245 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
248 246
249+ case CPU_XLP: 247+ case CPU_XLP:
250+ return (mask & INSN_XLP) != 0; 248+ return (mask & INSN_XLP) != 0;
@@ -252,12 +250,12 @@ Index: binutils-2.24/include/opcode/mips.h
252 default: 250 default:
253 return FALSE; 251 return FALSE;
254 } 252 }
255Index: binutils-2.24/ld/configure.tgt 253diff --git a/ld/configure.tgt b/ld/configure.tgt
256=================================================================== 254index 740b2ea..4df13a7 100644
257--- binutils-2.24.orig/ld/configure.tgt 2013-12-15 13:08:03.047065922 -0800 255--- a/ld/configure.tgt
258+++ binutils-2.24/ld/configure.tgt 2013-12-15 13:08:03.407065920 -0800 256+++ b/ld/configure.tgt
259@@ -457,6 +457,8 @@ 257@@ -462,6 +462,8 @@ mips*el-sde-elf*) targ_emul=elf32ltsmip
260 mips*-sde-elf* | mips*-mti-elf*) 258 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
261 targ_emul=elf32btsmip 259 targ_emul=elf32btsmip
262 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; 260 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
263+mipsisa64*-*-elf*) targ_emul=elf32btsmip 261+mipsisa64*-*-elf*) targ_emul=elf32btsmip
@@ -265,13 +263,13 @@ Index: binutils-2.24/ld/configure.tgt
265 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 263 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
266 targ_extra_emuls="elf32lr5900" 264 targ_extra_emuls="elf32lr5900"
267 targ_extra_libpath=$targ_extra_emuls ;; 265 targ_extra_libpath=$targ_extra_emuls ;;
268Index: binutils-2.24/opcodes/mips-dis.c 266diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
269=================================================================== 267index 1eb1d45..d6881af 100644
270--- binutils-2.24.orig/opcodes/mips-dis.c 2013-12-15 13:07:57.180399300 -0800 268--- a/opcodes/mips-dis.c
271+++ binutils-2.24/opcodes/mips-dis.c 2013-12-15 13:39:50.243718329 -0800 269+++ b/opcodes/mips-dis.c
272@@ -554,13 +554,11 @@ 270@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] =
273 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 271 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
274 mips_hwr_names_numeric }, 272 mips_cp1_names_mips3264, mips_hwr_names_numeric },
275 273
276- /* XLP is mostly like XLR, with the prominent exception it is being 274- /* XLP is mostly like XLR, with the prominent exception it is being
277- MIPS64R2. */ 275- MIPS64R2. */
@@ -279,7 +277,7 @@ Index: binutils-2.24/opcodes/mips-dis.c
279- ISA_MIPS64R2 | INSN_XLR, 0, 277- ISA_MIPS64R2 | INSN_XLR, 0,
280- mips_cp0_names_xlr, 278- mips_cp0_names_xlr,
281- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 279- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
282- mips_hwr_names_numeric }, 280- mips_cp1_names_mips3264, mips_hwr_names_numeric },
283+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP, 281+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
284+ ISA_MIPS64R2 | INSN_XLP, 0, 282+ ISA_MIPS64R2 | INSN_XLP, 0,
285+ mips_cp0_names_mips3264r2, 283+ mips_cp0_names_mips3264r2,
@@ -288,11 +286,11 @@ Index: binutils-2.24/opcodes/mips-dis.c
288 286
289 /* This entry, mips16, is here only for ISA/processor selection; do 287 /* This entry, mips16, is here only for ISA/processor selection; do
290 not print its name. */ 288 not print its name. */
291Index: binutils-2.24/opcodes/mips-opc.c 289diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
292=================================================================== 290index 2c3bbad..86eb95b 100644
293--- binutils-2.24.orig/opcodes/mips-opc.c 2013-12-15 13:07:57.180399300 -0800 291--- a/opcodes/mips-opc.c
294+++ binutils-2.24/opcodes/mips-opc.c 2013-12-15 13:27:30.573724118 -0800 292+++ b/opcodes/mips-opc.c
295@@ -262,7 +262,8 @@ 293@@ -319,7 +319,8 @@ decode_mips_operand (const char *p)
296 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) 294 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
297 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2) 295 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
298 #define IOCT2 INSN_OCTEON2 296 #define IOCT2 INSN_OCTEON2
@@ -302,67 +300,69 @@ Index: binutils-2.24/opcodes/mips-opc.c
302 #define IVIRT ASE_VIRT 300 #define IVIRT ASE_VIRT
303 #define IVIRT64 ASE_VIRT64 301 #define IVIRT64 ASE_VIRT64
304 302
305@@ -881,6 +882,7 @@ 303@@ -956,6 +957,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
306 {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, 304 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
307 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, 305 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
308 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, 306 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
309+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, 307+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
310 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, 308 /* ctc0 is at the bottom of the table. */
311 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, 309 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
312 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, 310 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
313@@ -913,10 +915,11 @@ 311@@ -988,12 +990,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
314 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, 312 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
315 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, 313 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
316 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, 314 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
317-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, 315-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
318+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 }, 316+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
319 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, 317 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
320 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, 318 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
321 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, 319 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
320 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
321 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
322+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, 322+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
323 /* dctr and dctw are used on the r5000. */ 323 /* dctr and dctw are used on the r5000. */
324 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, 324 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
325 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, 325 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
326@@ -980,6 +983,7 @@ 326@@ -1065,6 +1068,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
327 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I64, 0, 0 }, 327 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
328 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, 328 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
329 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 }, 329 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
330+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 }, 330+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
331 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, 331 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
332 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, 332 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
333 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I3, 0, EE }, 333 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
334@@ -994,6 +998,8 @@ 334@@ -1079,6 +1083,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
335 /* dmtc2 is at the bottom of the table. */ 335 /* dmtc2 is at the bottom of the table. */
336 /* dmfc3 is at the bottom of the table. */ 336 /* dmfc3 is at the bottom of the table. */
337 /* dmtc3 is at the bottom of the table. */ 337 /* dmtc3 is at the bottom of the table. */
338 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
338+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 }, 339+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
339+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, 340+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
341 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
340 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, 342 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
341 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 }, 343@@ -1229,9 +1235,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
342 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 }, 344 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
343@@ -1134,9 +1140,9 @@
344 /* The macro has to be first to handle o32 correctly. */
345 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, 345 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
346 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, 346 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
347-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 347-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
348-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 348-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
349-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 349-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
350+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 350+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
351+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 351+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
352+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 352+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
353 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, 353 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
354 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, 354 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
355 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, 355 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
356@@ -1288,7 +1294,7 @@ 356@@ -1396,7 +1402,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
357 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, 357 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
358 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, 358 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
359 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, 359 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
360-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 }, 360-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
361+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 }, 361+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
362 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, 362 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
363 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, 363 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
364 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, 364 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
365@@ -1332,10 +1338,13 @@ 365@@ -1441,10 +1447,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
366 /* move is at the top of the table. */ 366 /* move is at the top of the table. */
367 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, 367 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
368 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, 368 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
@@ -375,28 +375,28 @@ Index: binutils-2.24/opcodes/mips-opc.c
375+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 }, 375+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
376+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 }, 376+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
377+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 }, 377+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
378 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, 378 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
379 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, 379 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
380 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, 380 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
381@@ -1381,7 +1390,7 @@ 381@@ -1494,7 +1503,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
382 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, 382 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
383 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, 383 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
384 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, 384 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
385-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 }, 385-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
386+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 }, 386+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
387 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, 387 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
388 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, 388 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
389 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, 389 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
390@@ -1802,9 +1811,9 @@ 390@@ -1924,9 +1933,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
391 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, 0}, 391 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
392 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, 392 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
393 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, 393 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
394-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 394-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
395-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 395-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
396-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, 396-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
397+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 397+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
398+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 398+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
399+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, 399+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
400 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, 400 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
401 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, 401 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
402 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, 402 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-22 10:13:00 +0000