diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch b/meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch index 6a3b78f227..f686763594 100644 --- a/meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch +++ b/meta/recipes-devtools/binutils/binutils/0012-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From e48767a0298e6ccf53d83fecc93bb6d26b595897 Mon Sep 17 00:00:00 2001 | 1 | From f34aac4314b821396fe745013dc8ec8683ea2598 Mon Sep 17 00:00:00 2001 |
2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> | 2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> |
3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 | 3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 |
4 | Subject: [PATCH 12/15] fix the incorrect assembling for ppc wait mnemonic | 4 | Subject: [PATCH] fix the incorrect assembling for ppc wait mnemonic |
5 | 5 | ||
6 | Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> | 6 | Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> |
7 | 7 | ||
@@ -11,10 +11,10 @@ Upstream-Status: Pending | |||
11 | 1 file changed, 1 insertion(+), 2 deletions(-) | 11 | 1 file changed, 1 insertion(+), 2 deletions(-) |
12 | 12 | ||
13 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c | 13 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c |
14 | index 3032631d4e..142f096ef4 100644 | 14 | index b56fe3e21a..696fe83a7b 100644 |
15 | --- a/opcodes/ppc-opc.c | 15 | --- a/opcodes/ppc-opc.c |
16 | +++ b/opcodes/ppc-opc.c | 16 | +++ b/opcodes/ppc-opc.c |
17 | @@ -5325,7 +5325,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 17 | @@ -5709,7 +5709,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
18 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | 18 | {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
19 | 19 | ||
20 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | 20 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, |
@@ -22,7 +22,7 @@ index 3032631d4e..142f096ef4 100644 | |||
22 | 22 | ||
23 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | 23 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
24 | 24 | ||
25 | @@ -5379,7 +5378,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 25 | @@ -5763,7 +5762,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
26 | 26 | ||
27 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | 27 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
28 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | 28 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
@@ -31,6 +31,3 @@ index 3032631d4e..142f096ef4 100644 | |||
31 | 31 | ||
32 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, | 32 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
33 | 33 | ||
34 | -- | ||
35 | 2.20.1 | ||
36 | |||