diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch | 88 |
1 files changed, 44 insertions, 44 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch index af7f12ff8b..8103347ba4 100644 --- a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch +++ b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 9f967c555b3fda64af4549ae252a0fba00120529 Mon Sep 17 00:00:00 2001 | 1 | From c2e138f4ccdf8af81c18c8511c901d3deee696b5 Mon Sep 17 00:00:00 2001 |
2 | From: Khem Raj <raj.khem@gmail.com> | 2 | From: Khem Raj <raj.khem@gmail.com> |
3 | Date: Sun, 14 Feb 2016 17:06:19 +0000 | 3 | Date: Sun, 14 Feb 2016 17:06:19 +0000 |
4 | Subject: [PATCH 12/14] Add support for Netlogic XLP | 4 | Subject: [PATCH 12/13] Add support for Netlogic XLP |
5 | 5 | ||
6 | Patch From: Nebu Philips <nphilips@netlogicmicro.com> | 6 | Patch From: Nebu Philips <nphilips@netlogicmicro.com> |
7 | 7 | ||
@@ -35,10 +35,10 @@ Upstream-Status: Pending | |||
35 | 15 files changed, 65 insertions(+), 25 deletions(-) | 35 | 15 files changed, 65 insertions(+), 25 deletions(-) |
36 | 36 | ||
37 | diff --git a/bfd/aoutx.h b/bfd/aoutx.h | 37 | diff --git a/bfd/aoutx.h b/bfd/aoutx.h |
38 | index f78b910..d0d8dd3 100644 | 38 | index be0126a..4ca7e24 100644 |
39 | --- a/bfd/aoutx.h | 39 | --- a/bfd/aoutx.h |
40 | +++ b/bfd/aoutx.h | 40 | +++ b/bfd/aoutx.h |
41 | @@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, | 41 | @@ -812,6 +812,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, |
42 | case bfd_mach_mipsisa64r6: | 42 | case bfd_mach_mipsisa64r6: |
43 | case bfd_mach_mips_sb1: | 43 | case bfd_mach_mips_sb1: |
44 | case bfd_mach_mips_xlr: | 44 | case bfd_mach_mips_xlr: |
@@ -47,10 +47,10 @@ index f78b910..d0d8dd3 100644 | |||
47 | arch_flags = M_MIPS2; | 47 | arch_flags = M_MIPS2; |
48 | break; | 48 | break; |
49 | diff --git a/bfd/archures.c b/bfd/archures.c | 49 | diff --git a/bfd/archures.c b/bfd/archures.c |
50 | index 51068b9..727741f 100644 | 50 | index 96c9109..5a30d02 100644 |
51 | --- a/bfd/archures.c | 51 | --- a/bfd/archures.c |
52 | +++ b/bfd/archures.c | 52 | +++ b/bfd/archures.c |
53 | @@ -181,6 +181,7 @@ DESCRIPTION | 53 | @@ -197,6 +197,7 @@ DESCRIPTION |
54 | .#define bfd_mach_mips_octeon2 6502 | 54 | .#define bfd_mach_mips_octeon2 6502 |
55 | .#define bfd_mach_mips_octeon3 6503 | 55 | .#define bfd_mach_mips_octeon3 6503 |
56 | .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} | 56 | .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} |
@@ -59,10 +59,10 @@ index 51068b9..727741f 100644 | |||
59 | .#define bfd_mach_mipsisa32r2 33 | 59 | .#define bfd_mach_mipsisa32r2 33 |
60 | .#define bfd_mach_mipsisa32r3 34 | 60 | .#define bfd_mach_mipsisa32r3 34 |
61 | diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h | 61 | diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h |
62 | index 779ffbf..bf5a565 100644 | 62 | index 30513c4..5e8ed4c 100644 |
63 | --- a/bfd/bfd-in2.h | 63 | --- a/bfd/bfd-in2.h |
64 | +++ b/bfd/bfd-in2.h | 64 | +++ b/bfd/bfd-in2.h |
65 | @@ -1993,6 +1993,7 @@ enum bfd_architecture | 65 | @@ -2008,6 +2008,7 @@ enum bfd_architecture |
66 | #define bfd_mach_mips_octeon2 6502 | 66 | #define bfd_mach_mips_octeon2 6502 |
67 | #define bfd_mach_mips_octeon3 6503 | 67 | #define bfd_mach_mips_octeon3 6503 |
68 | #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ | 68 | #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ |
@@ -71,10 +71,10 @@ index 779ffbf..bf5a565 100644 | |||
71 | #define bfd_mach_mipsisa32r2 33 | 71 | #define bfd_mach_mipsisa32r2 33 |
72 | #define bfd_mach_mipsisa32r3 34 | 72 | #define bfd_mach_mipsisa32r3 34 |
73 | diff --git a/bfd/config.bfd b/bfd/config.bfd | 73 | diff --git a/bfd/config.bfd b/bfd/config.bfd |
74 | index 5c27b49..d553039 100644 | 74 | index ab17e72..863be89 100644 |
75 | --- a/bfd/config.bfd | 75 | --- a/bfd/config.bfd |
76 | +++ b/bfd/config.bfd | 76 | +++ b/bfd/config.bfd |
77 | @@ -1066,6 +1066,11 @@ case "${targ}" in | 77 | @@ -1084,6 +1084,11 @@ case "${targ}" in |
78 | targ_defvec=mips_elf32_le_vec | 78 | targ_defvec=mips_elf32_le_vec |
79 | targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" | 79 | targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" |
80 | ;; | 80 | ;; |
@@ -83,11 +83,11 @@ index 5c27b49..d553039 100644 | |||
83 | + targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec" | 83 | + targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec" |
84 | + want64=true | 84 | + want64=true |
85 | + ;; | 85 | + ;; |
86 | mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss) | 86 | mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none) |
87 | targ_defvec=mips_elf32_be_vec | 87 | targ_defvec=mips_elf32_be_vec |
88 | targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec" | 88 | targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec" |
89 | diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c | 89 | diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c |
90 | index 8a9475d..de7e5a3 100644 | 90 | index d209fb6..b6a86ae 100644 |
91 | --- a/bfd/cpu-mips.c | 91 | --- a/bfd/cpu-mips.c |
92 | +++ b/bfd/cpu-mips.c | 92 | +++ b/bfd/cpu-mips.c |
93 | @@ -104,7 +104,8 @@ enum | 93 | @@ -104,7 +104,8 @@ enum |
@@ -111,10 +111,10 @@ index 8a9475d..de7e5a3 100644 | |||
111 | 111 | ||
112 | /* The default architecture is mips:3000, but with a machine number of | 112 | /* The default architecture is mips:3000, but with a machine number of |
113 | diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c | 113 | diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c |
114 | index 1f2f4a3..700afd3 100644 | 114 | index e47276b..71c30a0 100644 |
115 | --- a/bfd/elfxx-mips.c | 115 | --- a/bfd/elfxx-mips.c |
116 | +++ b/bfd/elfxx-mips.c | 116 | +++ b/bfd/elfxx-mips.c |
117 | @@ -6605,6 +6605,9 @@ _bfd_elf_mips_mach (flagword flags) | 117 | @@ -6646,6 +6646,9 @@ _bfd_elf_mips_mach (flagword flags) |
118 | case E_MIPS_MACH_XLR: | 118 | case E_MIPS_MACH_XLR: |
119 | return bfd_mach_mips_xlr; | 119 | return bfd_mach_mips_xlr; |
120 | 120 | ||
@@ -124,7 +124,7 @@ index 1f2f4a3..700afd3 100644 | |||
124 | default: | 124 | default: |
125 | switch (flags & EF_MIPS_ARCH) | 125 | switch (flags & EF_MIPS_ARCH) |
126 | { | 126 | { |
127 | @@ -11901,6 +11904,10 @@ mips_set_isa_flags (bfd *abfd) | 127 | @@ -11949,6 +11952,10 @@ mips_set_isa_flags (bfd *abfd) |
128 | val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; | 128 | val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; |
129 | break; | 129 | break; |
130 | 130 | ||
@@ -135,7 +135,7 @@ index 1f2f4a3..700afd3 100644 | |||
135 | case bfd_mach_mipsisa32: | 135 | case bfd_mach_mipsisa32: |
136 | val = E_MIPS_ARCH_32; | 136 | val = E_MIPS_ARCH_32; |
137 | break; | 137 | break; |
138 | @@ -13931,6 +13938,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = | 138 | @@ -13975,6 +13982,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = |
139 | { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, | 139 | { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, |
140 | { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, | 140 | { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, |
141 | { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, | 141 | { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, |
@@ -144,10 +144,10 @@ index 1f2f4a3..700afd3 100644 | |||
144 | /* MIPS64 extensions. */ | 144 | /* MIPS64 extensions. */ |
145 | { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, | 145 | { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, |
146 | diff --git a/binutils/readelf.c b/binutils/readelf.c | 146 | diff --git a/binutils/readelf.c b/binutils/readelf.c |
147 | index d5dd46f..66810cc 100644 | 147 | index 274ddd1..d31558c 100644 |
148 | --- a/binutils/readelf.c | 148 | --- a/binutils/readelf.c |
149 | +++ b/binutils/readelf.c | 149 | +++ b/binutils/readelf.c |
150 | @@ -3140,6 +3140,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) | 150 | @@ -3230,6 +3230,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) |
151 | case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; | 151 | case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; |
152 | case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; | 152 | case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; |
153 | case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; | 153 | case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; |
@@ -156,7 +156,7 @@ index d5dd46f..66810cc 100644 | |||
156 | /* We simply ignore the field in this case to avoid confusion: | 156 | /* We simply ignore the field in this case to avoid confusion: |
157 | MIPS ELF does not specify EF_MIPS_MACH, it is a GNU | 157 | MIPS ELF does not specify EF_MIPS_MACH, it is a GNU |
158 | diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c | 158 | diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c |
159 | index a2d45a4..75902c0 100644 | 159 | index eb8b26b..e59dce6 100644 |
160 | --- a/gas/config/tc-mips.c | 160 | --- a/gas/config/tc-mips.c |
161 | +++ b/gas/config/tc-mips.c | 161 | +++ b/gas/config/tc-mips.c |
162 | @@ -552,6 +552,7 @@ static int mips_32bitmode = 0; | 162 | @@ -552,6 +552,7 @@ static int mips_32bitmode = 0; |
@@ -175,20 +175,20 @@ index a2d45a4..75902c0 100644 | |||
175 | ) | 175 | ) |
176 | 176 | ||
177 | /* Whether the processor uses hardware interlocks to protect reads | 177 | /* Whether the processor uses hardware interlocks to protect reads |
178 | @@ -18702,7 +18704,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = | 178 | @@ -18858,7 +18860,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = |
179 | /* Broadcom XLP. | 179 | /* Broadcom XLP. |
180 | XLP is mostly like XLR, with the prominent exception that it is | 180 | XLP is mostly like XLR, with the prominent exception that it is |
181 | MIPS64R2 rather than MIPS64. */ | 181 | MIPS64R2 rather than MIPS64. */ |
182 | - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, | 182 | - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
183 | + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, | 183 | + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, |
184 | 184 | ||
185 | /* i6400. */ | 185 | /* MIPS 64 Release 6 */ |
186 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, | 186 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
187 | diff --git a/gas/configure b/gas/configure | 187 | diff --git a/gas/configure b/gas/configure |
188 | index 89f18b3..86b19ae 100755 | 188 | index 45da030..aba89f7 100755 |
189 | --- a/gas/configure | 189 | --- a/gas/configure |
190 | +++ b/gas/configure | 190 | +++ b/gas/configure |
191 | @@ -12851,6 +12851,9 @@ _ACEOF | 191 | @@ -12914,6 +12914,9 @@ _ACEOF |
192 | mipsisa64r6 | mipsisa64r6el) | 192 | mipsisa64r6 | mipsisa64r6el) |
193 | mips_cpu=mips64r6 | 193 | mips_cpu=mips64r6 |
194 | ;; | 194 | ;; |
@@ -199,7 +199,7 @@ index 89f18b3..86b19ae 100755 | |||
199 | mips_cpu=r3900 | 199 | mips_cpu=r3900 |
200 | ;; | 200 | ;; |
201 | diff --git a/gas/configure.tgt b/gas/configure.tgt | 201 | diff --git a/gas/configure.tgt b/gas/configure.tgt |
202 | index 086e0d2..2b71270 100644 | 202 | index 1b9fd99..a9f1977 100644 |
203 | --- a/gas/configure.tgt | 203 | --- a/gas/configure.tgt |
204 | +++ b/gas/configure.tgt | 204 | +++ b/gas/configure.tgt |
205 | @@ -339,7 +339,7 @@ case ${generic_target} in | 205 | @@ -339,7 +339,7 @@ case ${generic_target} in |
@@ -212,10 +212,10 @@ index 086e0d2..2b71270 100644 | |||
212 | mips-*-openbsd*) fmt=elf em=tmips ;; | 212 | mips-*-openbsd*) fmt=elf em=tmips ;; |
213 | 213 | ||
214 | diff --git a/include/elf/mips.h b/include/elf/mips.h | 214 | diff --git a/include/elf/mips.h b/include/elf/mips.h |
215 | index 57de3bc..9ba141d 100644 | 215 | index 7e813de..d7d72c1 100644 |
216 | --- a/include/elf/mips.h | 216 | --- a/include/elf/mips.h |
217 | +++ b/include/elf/mips.h | 217 | +++ b/include/elf/mips.h |
218 | @@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) | 218 | @@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) |
219 | #define E_MIPS_MACH_SB1 0x008a0000 | 219 | #define E_MIPS_MACH_SB1 0x008a0000 |
220 | #define E_MIPS_MACH_OCTEON 0x008b0000 | 220 | #define E_MIPS_MACH_OCTEON 0x008b0000 |
221 | #define E_MIPS_MACH_XLR 0x008c0000 | 221 | #define E_MIPS_MACH_XLR 0x008c0000 |
@@ -224,10 +224,10 @@ index 57de3bc..9ba141d 100644 | |||
224 | #define E_MIPS_MACH_OCTEON3 0x008e0000 | 224 | #define E_MIPS_MACH_OCTEON3 0x008e0000 |
225 | #define E_MIPS_MACH_5400 0x00910000 | 225 | #define E_MIPS_MACH_5400 0x00910000 |
226 | diff --git a/include/opcode/mips.h b/include/opcode/mips.h | 226 | diff --git a/include/opcode/mips.h b/include/opcode/mips.h |
227 | index 9318fcc..9be5645 100644 | 227 | index b1d4ef6..f2c8e88 100644 |
228 | --- a/include/opcode/mips.h | 228 | --- a/include/opcode/mips.h |
229 | +++ b/include/opcode/mips.h | 229 | +++ b/include/opcode/mips.h |
230 | @@ -1228,8 +1228,10 @@ static const unsigned int mips_isa_table[] = { | 230 | @@ -1232,8 +1232,10 @@ static const unsigned int mips_isa_table[] = { |
231 | #define INSN_LOONGSON_2F 0x80000000 | 231 | #define INSN_LOONGSON_2F 0x80000000 |
232 | /* Loongson 3A. */ | 232 | /* Loongson 3A. */ |
233 | #define INSN_LOONGSON_3A 0x00000400 | 233 | #define INSN_LOONGSON_3A 0x00000400 |
@@ -240,7 +240,7 @@ index 9318fcc..9be5645 100644 | |||
240 | 240 | ||
241 | /* DSP ASE */ | 241 | /* DSP ASE */ |
242 | #define ASE_DSP 0x00000001 | 242 | #define ASE_DSP 0x00000001 |
243 | @@ -1326,6 +1328,7 @@ static const unsigned int mips_isa_table[] = { | 243 | @@ -1331,6 +1333,7 @@ static const unsigned int mips_isa_table[] = { |
244 | #define CPU_OCTEON2 6502 | 244 | #define CPU_OCTEON2 6502 |
245 | #define CPU_OCTEON3 6503 | 245 | #define CPU_OCTEON3 6503 |
246 | #define CPU_XLR 887682 /* decimal 'XLR' */ | 246 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
@@ -248,7 +248,7 @@ index 9318fcc..9be5645 100644 | |||
248 | 248 | ||
249 | /* Return true if the given CPU is included in INSN_* mask MASK. */ | 249 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
250 | 250 | ||
251 | @@ -1403,6 +1406,9 @@ cpu_is_member (int cpu, unsigned int mask) | 251 | @@ -1408,6 +1411,9 @@ cpu_is_member (int cpu, unsigned int mask) |
252 | return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) | 252 | return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) |
253 | || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); | 253 | || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); |
254 | 254 | ||
@@ -259,10 +259,10 @@ index 9318fcc..9be5645 100644 | |||
259 | return FALSE; | 259 | return FALSE; |
260 | } | 260 | } |
261 | diff --git a/ld/configure.tgt b/ld/configure.tgt | 261 | diff --git a/ld/configure.tgt b/ld/configure.tgt |
262 | index b45b1e5..fb2f36a 100644 | 262 | index 212327c..212e09c 100644 |
263 | --- a/ld/configure.tgt | 263 | --- a/ld/configure.tgt |
264 | +++ b/ld/configure.tgt | 264 | +++ b/ld/configure.tgt |
265 | @@ -495,6 +495,8 @@ mips*el-sde-elf*) targ_emul=elf32ltsmip | 265 | @@ -499,6 +499,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) |
266 | mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) | 266 | mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) |
267 | targ_emul=elf32btsmip | 267 | targ_emul=elf32btsmip |
268 | targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; | 268 | targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; |
@@ -272,7 +272,7 @@ index b45b1e5..fb2f36a 100644 | |||
272 | targ_extra_emuls="elf32lr5900" | 272 | targ_extra_emuls="elf32lr5900" |
273 | targ_extra_libpath=$targ_extra_emuls ;; | 273 | targ_extra_libpath=$targ_extra_emuls ;; |
274 | diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c | 274 | diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c |
275 | index 8200920..40d9fe2 100644 | 275 | index 3f874e7..9813d0e 100644 |
276 | --- a/opcodes/mips-dis.c | 276 | --- a/opcodes/mips-dis.c |
277 | +++ b/opcodes/mips-dis.c | 277 | +++ b/opcodes/mips-dis.c |
278 | @@ -648,13 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] = | 278 | @@ -648,13 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] = |
@@ -295,7 +295,7 @@ index 8200920..40d9fe2 100644 | |||
295 | /* This entry, mips16, is here only for ISA/processor selection; do | 295 | /* This entry, mips16, is here only for ISA/processor selection; do |
296 | not print its name. */ | 296 | not print its name. */ |
297 | diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c | 297 | diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c |
298 | index 402f887..3764836 100644 | 298 | index a95eff1..99fb7bb 100644 |
299 | --- a/opcodes/mips-opc.c | 299 | --- a/opcodes/mips-opc.c |
300 | +++ b/opcodes/mips-opc.c | 300 | +++ b/opcodes/mips-opc.c |
301 | @@ -320,7 +320,8 @@ decode_mips_operand (const char *p) | 301 | @@ -320,7 +320,8 @@ decode_mips_operand (const char *p) |
@@ -308,7 +308,7 @@ index 402f887..3764836 100644 | |||
308 | #define IVIRT ASE_VIRT | 308 | #define IVIRT ASE_VIRT |
309 | #define IVIRT64 ASE_VIRT64 | 309 | #define IVIRT64 ASE_VIRT64 |
310 | 310 | ||
311 | @@ -957,6 +958,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | 311 | @@ -958,6 +959,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
312 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, | 312 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, |
313 | {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, | 313 | {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, |
314 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, | 314 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, |
@@ -316,7 +316,7 @@ index 402f887..3764836 100644 | |||
316 | /* ctc0 is at the bottom of the table. */ | 316 | /* ctc0 is at the bottom of the table. */ |
317 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, | 317 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, |
318 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, | 318 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, |
319 | @@ -989,12 +991,13 @@ const struct mips_opcode mips_builtin_opcodes[] = | 319 | @@ -990,12 +992,13 @@ const struct mips_opcode mips_builtin_opcodes[] = |
320 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, | 320 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, |
321 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | 321 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, |
322 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, | 322 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, |
@@ -331,7 +331,7 @@ index 402f887..3764836 100644 | |||
331 | /* dctr and dctw are used on the r5000. */ | 331 | /* dctr and dctw are used on the r5000. */ |
332 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, | 332 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, |
333 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, | 333 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, |
334 | @@ -1066,6 +1069,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | 334 | @@ -1067,6 +1070,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
335 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, | 335 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, |
336 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, | 336 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, |
337 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, | 337 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, |
@@ -339,7 +339,7 @@ index 402f887..3764836 100644 | |||
339 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | 339 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, |
340 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, | 340 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, |
341 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, | 341 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, |
342 | @@ -1081,6 +1085,8 @@ const struct mips_opcode mips_builtin_opcodes[] = | 342 | @@ -1082,6 +1086,8 @@ const struct mips_opcode mips_builtin_opcodes[] = |
343 | /* dmfc3 is at the bottom of the table. */ | 343 | /* dmfc3 is at the bottom of the table. */ |
344 | /* dmtc3 is at the bottom of the table. */ | 344 | /* dmtc3 is at the bottom of the table. */ |
345 | {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, | 345 | {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, |
@@ -348,7 +348,7 @@ index 402f887..3764836 100644 | |||
348 | {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, | 348 | {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, |
349 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, | 349 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, |
350 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, | 350 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, |
351 | @@ -1234,9 +1240,9 @@ const struct mips_opcode mips_builtin_opcodes[] = | 351 | @@ -1235,9 +1241,9 @@ const struct mips_opcode mips_builtin_opcodes[] = |
352 | {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, | 352 | {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, |
353 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, | 353 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, |
354 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, | 354 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, |
@@ -361,7 +361,7 @@ index 402f887..3764836 100644 | |||
361 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | 361 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, |
362 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | 362 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, |
363 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | 363 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, |
364 | @@ -1401,7 +1407,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | 364 | @@ -1402,7 +1408,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
365 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, | 365 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, |
366 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, | 366 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, |
367 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, | 367 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, |
@@ -370,7 +370,7 @@ index 402f887..3764836 100644 | |||
370 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, | 370 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, |
371 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | 371 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, |
372 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | 372 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, |
373 | @@ -1446,10 +1452,13 @@ const struct mips_opcode mips_builtin_opcodes[] = | 373 | @@ -1447,10 +1453,13 @@ const struct mips_opcode mips_builtin_opcodes[] = |
374 | /* move is at the top of the table. */ | 374 | /* move is at the top of the table. */ |
375 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | 375 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, |
376 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, | 376 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, |
@@ -386,7 +386,7 @@ index 402f887..3764836 100644 | |||
386 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, | 386 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, |
387 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | 387 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, |
388 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | 388 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, |
389 | @@ -1499,7 +1508,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | 389 | @@ -1500,7 +1509,7 @@ const struct mips_opcode mips_builtin_opcodes[] = |
390 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, | 390 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, |
391 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, | 391 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, |
392 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, | 392 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, |
@@ -395,7 +395,7 @@ index 402f887..3764836 100644 | |||
395 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | 395 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, |
396 | {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, | 396 | {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, |
397 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | 397 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, |
398 | @@ -1936,9 +1945,9 @@ const struct mips_opcode mips_builtin_opcodes[] = | 398 | @@ -1937,9 +1946,9 @@ const struct mips_opcode mips_builtin_opcodes[] = |
399 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, | 399 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, |
400 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, | 400 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, |
401 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, | 401 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, |
@@ -409,5 +409,5 @@ index 402f887..3764836 100644 | |||
409 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, | 409 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, |
410 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, | 410 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, |
411 | -- | 411 | -- |
412 | 2.7.1 | 412 | 2.9.0 |
413 | 413 | ||