1 files changed, 64 insertions, 82 deletions

diff --git a/meta/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch b/meta/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch
index ecc37ccc01..01492b566a 100644
--- a/meta/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch
+++ b/meta/recipes-devtools/binutils/binutils/0012-Add-XLP-instructions-support.patch
@@ -1,7 +1,7 @@
-From 448329ea097447aee73d050045295c5a0ae8519e Mon Sep 17 00:00:00 2001
+From 10e0f42d258164a6a8c0c733518c79e114f5d702 Mon Sep 17 00:00:00 2001
 From: Khem Raj <raj.khem@gmail.com>
-Date: Mon, 2 Mar 2015 01:51:05 +0000
-Subject: [PATCH 12/13] Add XLP instructions support
+Date: Fri, 15 Jan 2016 06:37:20 +0000
+Subject: [PATCH 12/12] Add XLP instructions support
 
 From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001
 From: Nebu Philips <nphilips@netlogicmicro.com>
@@ -10,34 +10,16 @@ Subject: [PATCH] Add support for Netlogic XLP
 
 Using the mipsisa64r2nlm target, add support for XLP from
 Netlogic. Also, update vendor name to NLM wherever applicable.
----
- bfd/aoutx.h           |    1 +
- bfd/archures.c        |    1 +
- bfd/bfd-in2.h         |    1 +
- bfd/config.bfd        |    5 +++++
- bfd/cpu-mips.c        |    6 ++++--
- bfd/elfxx-mips.c      |    8 ++++++++
- binutils/readelf.c    |    1 +
- gas/config/tc-mips.c  |    4 +++-
- gas/configure         |    3 +++
- gas/configure.tgt     |    2 +-
- include/elf/mips.h    |    1 +
- include/opcode/mips.h |   10 ++++++++--
- ld/configure.tgt      |    2 ++
- opcodes/mips-dis.c    |   12 +++++-------
- opcodes/mips-opc.c    |   33 +++++++++++++++++++++------------
- 15 files changed, 65 insertions(+), 25 deletions(-)
 
-Upstream-Status: Pending
+Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
+assigned to INSN_OCTEON3
 
 Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been assigned
-to INSN_OCTEON3
-
 Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
 Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
 ---
+Upstream-Status: Pending
+
  bfd/aoutx.h           |  1 +
  bfd/archures.c        |  1 +
  bfd/bfd-in2.h         |  1 +
@@ -56,7 +38,7 @@ Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
  15 files changed, 65 insertions(+), 25 deletions(-)
 
 diff --git a/bfd/aoutx.h b/bfd/aoutx.h
-index 9385a98..a88df99 100644
+index f78b910..d0d8dd3 100644
 --- a/bfd/aoutx.h
 +++ b/bfd/aoutx.h
 @@ -802,6 +802,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
@@ -68,34 +50,34 @@ index 9385a98..a88df99 100644
           arch_flags = M_MIPS2;
           break;
 diff --git a/bfd/archures.c b/bfd/archures.c
-index c9fd6c8..547bd09 100644
+index 51068b9..727741f 100644
 --- a/bfd/archures.c
 +++ b/bfd/archures.c
-@@ -180,6 +180,7 @@ DESCRIPTION
- .#define bfd_mach_mips_octeonp         6601
+@@ -181,6 +181,7 @@ DESCRIPTION
  .#define bfd_mach_mips_octeon2         6502
+ .#define bfd_mach_mips_octeon3          6503
  .#define bfd_mach_mips_xlr              887682   {* decimal 'XLR'  *}
 +.#define bfd_mach_mips_xlp              887680   {* decimal 'XLP'  *}
  .#define bfd_mach_mipsisa32             32
  .#define bfd_mach_mipsisa32r2           33
  .#define bfd_mach_mipsisa32r3           34
 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index c7a2bb5..413b773 100644
+index 779ffbf..bf5a565 100644
 --- a/bfd/bfd-in2.h
 +++ b/bfd/bfd-in2.h
-@@ -1967,6 +1967,7 @@ enum bfd_architecture
- #define bfd_mach_mips_octeonp          6601
+@@ -1993,6 +1993,7 @@ enum bfd_architecture
  #define bfd_mach_mips_octeon2          6502
+ #define bfd_mach_mips_octeon3          6503
  #define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
 +#define bfd_mach_mips_xlp              887680   /* decimal 'XLP'  */
  #define bfd_mach_mipsisa32             32
  #define bfd_mach_mipsisa32r2           33
  #define bfd_mach_mipsisa32r3           34
 diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 03d2c6f..27086db 100644
+index 5c27b49..d553039 100644
 --- a/bfd/config.bfd
 +++ b/bfd/config.bfd
-@@ -1041,6 +1041,11 @@ case "${targ}" in
+@@ -1066,6 +1066,11 @@ case "${targ}" in
      targ_defvec=mips_elf32_le_vec
      targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
      ;;
@@ -108,12 +90,12 @@ index 03d2c6f..27086db 100644
      targ_defvec=mips_elf32_be_vec
      targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
 diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
-index b617aaa..19a99d1 100644
+index 8a9475d..de7e5a3 100644
 --- a/bfd/cpu-mips.c
 +++ b/bfd/cpu-mips.c
-@@ -103,7 +103,8 @@ enum
-   I_mipsocteonp,
+@@ -104,7 +104,8 @@ enum
    I_mipsocteon2,
+   I_mipsocteon3,
    I_xlr,
 -  I_micromips
 +  I_micromips,
@@ -121,9 +103,9 @@ index b617aaa..19a99d1 100644
  };
  
  #define NN(index) (&arch_info_struct[(index) + 1])
-@@ -153,7 +154,8 @@ static const bfd_arch_info_type arch_info_struct[] =
-   N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+",  FALSE, NN(I_mipsocteonp)),
+@@ -155,7 +156,8 @@ static const bfd_arch_info_type arch_info_struct[] =
    N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2",  FALSE, NN(I_mipsocteon2)),
+   N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3",  FALSE, NN(I_mipsocteon3)),
    N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, NN(I_xlr)),
 -  N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
 +  N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
@@ -132,10 +114,10 @@ index b617aaa..19a99d1 100644
  
  /* The default architecture is mips:3000, but with a machine number of
 diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
-index 0df7abf..d268e86 100644
+index 1f2f4a3..700afd3 100644
 --- a/bfd/elfxx-mips.c
 +++ b/bfd/elfxx-mips.c
-@@ -6608,6 +6608,9 @@ _bfd_elf_mips_mach (flagword flags)
+@@ -6605,6 +6605,9 @@ _bfd_elf_mips_mach (flagword flags)
      case E_MIPS_MACH_XLR:
        return bfd_mach_mips_xlr;
  
@@ -145,7 +127,7 @@ index 0df7abf..d268e86 100644
      default:
        switch (flags & EF_MIPS_ARCH)
         {
-@@ -11878,6 +11881,10 @@ mips_set_isa_flags (bfd *abfd)
+@@ -11901,6 +11904,10 @@ mips_set_isa_flags (bfd *abfd)
        val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
        break;
  
@@ -156,7 +138,7 @@ index 0df7abf..d268e86 100644
      case bfd_mach_mipsisa32:
        val = E_MIPS_ARCH_32;
        break;
-@@ -14765,6 +14772,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
+@@ -13931,6 +13938,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
    { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
    { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
    { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
@@ -165,10 +147,10 @@ index 0df7abf..d268e86 100644
    /* MIPS64 extensions.  */
    { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
 diff --git a/binutils/readelf.c b/binutils/readelf.c
-index 0c00b2f..6e9d5e4 100644
+index d5dd46f..66810cc 100644
 --- a/binutils/readelf.c
 +++ b/binutils/readelf.c
-@@ -2898,6 +2898,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
+@@ -3140,6 +3140,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
             case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
             case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
             case E_MIPS_MACH_XLR:  strcat (buf, ", xlr"); break;
@@ -177,10 +159,10 @@ index 0c00b2f..6e9d5e4 100644
             /* We simply ignore the field in this case to avoid confusion:
                MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
 diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
-index c3e3e2a..8d64344 100644
+index a2d45a4..75902c0 100644
 --- a/gas/config/tc-mips.c
 +++ b/gas/config/tc-mips.c
-@@ -551,6 +551,7 @@ static int mips_32bitmode = 0;
+@@ -552,6 +552,7 @@ static int mips_32bitmode = 0;
     || mips_opts.arch == CPU_RM7000                    \
     || mips_opts.arch == CPU_VR5500                    \
     || mips_opts.micromips                             \
@@ -188,7 +170,7 @@ index c3e3e2a..8d64344 100644
     )
  
  /* Whether the processor uses hardware interlocks to protect reads
-@@ -580,6 +581,7 @@ static int mips_32bitmode = 0;
+@@ -581,6 +582,7 @@ static int mips_32bitmode = 0;
      && mips_opts.isa != ISA_MIPS3)                    \
     || mips_opts.arch == CPU_R4300                     \
     || mips_opts.micromips                             \
@@ -196,20 +178,20 @@ index c3e3e2a..8d64344 100644
     )
  
  /* Whether the processor uses hardware interlocks to protect reads
-@@ -18682,7 +18684,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
+@@ -18702,7 +18704,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
    /* Broadcom XLP.
       XLP is mostly like XLR, with the prominent exception that it is
       MIPS64R2 rather than MIPS64.  */
 -  { "xlp",           0, 0,                     ISA_MIPS64R2, CPU_XLR },
 +  { "xlp",           0, 0,                     ISA_MIPS64R2, CPU_XLP },
  
-   /* End marker */
-   { NULL, 0, 0, 0, 0 }
+   /* i6400.  */
+   { "i6400",         0, ASE_MSA,               ISA_MIPS64R6, CPU_MIPS64R6},
 diff --git a/gas/configure b/gas/configure
-index 074886f..8091f2f 100755
+index 1c2a665..c8010a8 100755
 --- a/gas/configure
 +++ b/gas/configure
-@@ -12808,6 +12808,9 @@ _ACEOF
+@@ -12826,6 +12826,9 @@ _ACEOF
           mipsisa64r6 | mipsisa64r6el)
             mips_cpu=mips64r6
             ;;
@@ -220,10 +202,10 @@ index 074886f..8091f2f 100755
             mips_cpu=r3900
             ;;
 diff --git a/gas/configure.tgt b/gas/configure.tgt
-index 1d92f55..06e8b4f 100644
+index 086e0d2..2b71270 100644
 --- a/gas/configure.tgt
 +++ b/gas/configure.tgt
-@@ -332,7 +332,7 @@ case ${generic_target} in
+@@ -339,7 +339,7 @@ case ${generic_target} in
    mips-*-sysv4*MP* | mips-*-gnu*)      fmt=elf em=tmips ;;
    mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
                                         fmt=elf em=tmips ;;
@@ -233,7 +215,7 @@ index 1d92f55..06e8b4f 100644
    mips-*-openbsd*)                     fmt=elf em=tmips ;;
  
 diff --git a/include/elf/mips.h b/include/elf/mips.h
-index 2ed6acd..e541f50 100644
+index 57de3bc..9ba141d 100644
 --- a/include/elf/mips.h
 +++ b/include/elf/mips.h
 @@ -285,6 +285,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
@@ -245,10 +227,10 @@ index 2ed6acd..e541f50 100644
  #define E_MIPS_MACH_OCTEON3    0x008e0000
  #define E_MIPS_MACH_5400       0x00910000
 diff --git a/include/opcode/mips.h b/include/opcode/mips.h
-index ef26167..ef53ec6 100644
+index 9318fcc..9be5645 100644
 --- a/include/opcode/mips.h
 +++ b/include/opcode/mips.h
-@@ -1227,8 +1227,10 @@ static const unsigned int mips_isa_table[] = {
+@@ -1228,8 +1228,10 @@ static const unsigned int mips_isa_table[] = {
  #define INSN_LOONGSON_2F          0x80000000
  /* Loongson 3A.  */
  #define INSN_LOONGSON_3A          0x00000400
@@ -261,15 +243,15 @@ index ef26167..ef53ec6 100644
  
  /* DSP ASE */
  #define ASE_DSP                        0x00000001
-@@ -1324,6 +1326,7 @@ static const unsigned int mips_isa_table[] = {
- #define CPU_OCTEONP    6601
+@@ -1326,6 +1328,7 @@ static const unsigned int mips_isa_table[] = {
  #define CPU_OCTEON2    6502
+ #define CPU_OCTEON3    6503
  #define CPU_XLR        887682          /* decimal 'XLR'   */
 +#define CPU_XLP         887680      /* decimal 'XLP'   */
  
  /* Return true if the given CPU is included in INSN_* mask MASK.  */
  
-@@ -1398,6 +1401,9 @@ cpu_is_member (int cpu, unsigned int mask)
+@@ -1403,6 +1406,9 @@ cpu_is_member (int cpu, unsigned int mask)
        return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
              || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
  
@@ -280,10 +262,10 @@ index ef26167..ef53ec6 100644
        return FALSE;
      }
 diff --git a/ld/configure.tgt b/ld/configure.tgt
-index 740b2ea..4df13a7 100644
+index b45b1e5..fb2f36a 100644
 --- a/ld/configure.tgt
 +++ b/ld/configure.tgt
-@@ -462,6 +462,8 @@ mips*el-sde-elf*)   targ_emul=elf32ltsmip
+@@ -495,6 +495,8 @@ mips*el-sde-elf*)   targ_emul=elf32ltsmip
  mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
                         targ_emul=elf32btsmip
                         targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
@@ -293,10 +275,10 @@ index 740b2ea..4df13a7 100644
                         targ_extra_emuls="elf32lr5900"
                         targ_extra_libpath=$targ_extra_emuls ;;
 diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
-index 1eb1d45..d6881af 100644
+index 8200920..40d9fe2 100644
 --- a/opcodes/mips-dis.c
 +++ b/opcodes/mips-dis.c
-@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] =
+@@ -648,13 +648,11 @@ const struct mips_arch_choice mips_arch_choices[] =
      mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
      mips_cp1_names_mips3264, mips_hwr_names_numeric },
  
@@ -311,25 +293,25 @@ index 1eb1d45..d6881af 100644
 +    ISA_MIPS64R2 | INSN_XLP, 0,
 +    mips_cp0_names_mips3264r2,
 +    mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
-+    mips_hwr_names_mips3264r2 },
++    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
  
    /* This entry, mips16, is here only for ISA/processor selection; do
       not print its name.  */
 diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
-index 2c3bbad..9785a7e 100644
+index 402f887..3764836 100644
 --- a/opcodes/mips-opc.c
 +++ b/opcodes/mips-opc.c
-@@ -319,7 +319,8 @@ decode_mips_operand (const char *p)
- #define IOCT   (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
- #define IOCTP  (INSN_OCTEONP | INSN_OCTEON2)
- #define IOCT2  INSN_OCTEON2
+@@ -320,7 +320,8 @@ decode_mips_operand (const char *p)
+ #define IOCTP  (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+ #define IOCT2  (INSN_OCTEON2 | INSN_OCTEON3)
+ #define IOCT3  INSN_OCTEON3
 -#define XLR     INSN_XLR
 +#define XLR    INSN_XLR
 +#define XLP    INSN_XLP
  #define IVIRT  ASE_VIRT
  #define IVIRT64        ASE_VIRT64
  
-@@ -956,6 +957,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -957,6 +958,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
  {"clz",                        "d,s",          0x00000050, 0xfc1f07ff, WR_1|RD_2,              0,              I37,            0,      0 },
  {"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
@@ -337,7 +319,7 @@ index 2c3bbad..9785a7e 100644
  /* ctc0 is at the bottom of the table.  */
  {"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
  {"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
-@@ -988,12 +990,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -989,12 +991,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"daddiu",             "t,r,j",        0x64000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
  {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
  {"daddu",              "t,r,I",        0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3,             0,      0 },
@@ -352,7 +334,7 @@ index 2c3bbad..9785a7e 100644
  /* dctr and dctw are used on the r5000.  */
  {"dctr",               "o(b)",         0xbc050000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
  {"dctw",               "o(b)",         0xbc090000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
-@@ -1065,6 +1068,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1066,6 +1069,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"dmfc0",              "t,G,H",        0x40200000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I64,            0,      0 },
  {"dmfgc0",             "t,G",          0x40600100, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT64, 0 },
  {"dmfgc0",             "t,G,H",        0x40600100, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              IVIRT64, 0 },
@@ -360,7 +342,7 @@ index 2c3bbad..9785a7e 100644
  {"dmt",                        "",             0x41600bc1, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
  {"dmt",                        "t",            0x41600bc1, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
  {"dmtc0",              "t,G",          0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I3,             0,      EE },
-@@ -1080,6 +1084,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1081,6 +1085,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
  /* dmfc3 is at the bottom of the table.  */
  /* dmtc3 is at the bottom of the table.  */
  {"dmuh",               "d,s,t",        0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
@@ -369,7 +351,7 @@ index 2c3bbad..9785a7e 100644
  {"dmul",               "d,s,t",        0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
  {"dmul",               "d,v,t",        0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              IOCT,           0,      0 },
  {"dmul",               "d,v,t",        0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,             0,      M32|I69 },
-@@ -1229,9 +1235,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1234,9 +1240,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"ld",                 "s,-b(+R)",     0xec180000, 0xfc1c0000, WR_1,                   RD_pc,          I69,            0,      0 },
  {"ld",                 "t,A(b)",       0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
  {"ld",                 "t,o(b)",       0xdc000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
@@ -382,7 +364,7 @@ index 2c3bbad..9785a7e 100644
  {"ldc1",               "T,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF },
  {"ldc1",               "E,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF },
  {"ldc1",               "T,A(b)",       0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
-@@ -1396,7 +1402,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1401,7 +1407,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"mflo",               "d,9",          0x00000012, 0xff9f07ff, WR_1|RD_LO,             0,              0,              D32,    0 },
  {"mflo1",              "d",            0x70000012, 0xffff07ff, WR_1|RD_LO,             0,              EE,             0,      0 },
  {"mflhxu",             "d",            0x00000052, 0xffff07ff, WR_1|MOD_HILO,          0,              0,              SMT,    0 },
@@ -391,7 +373,7 @@ index 2c3bbad..9785a7e 100644
  {"mfsa",               "d",            0x00000028, 0xffff07ff, WR_1,                   0,              EE,             0,      0 },
  {"min.ob",             "X,Y,Q",        0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
  {"min.ob",             "D,S,Q",        0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
-@@ -1441,10 +1447,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1446,10 +1452,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
  /* move is at the top of the table.  */
  {"msgn.qh",            "X,Y,Q",        0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
  {"msgsnd",             "t",            0,    (int) M_MSGSND,   INSN_MACRO,             0,              XLR,            0,      0 },
@@ -407,16 +389,16 @@ index 2c3bbad..9785a7e 100644
  {"msub.d",             "D,R,S,T",      0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      I37 },
  {"msub.d",             "D,S,T",        0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
  {"msub.d",             "D,S,T",        0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-@@ -1494,7 +1503,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1499,7 +1508,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"mtlo",               "s,7",          0x00000013, 0xfc1fe7ff, RD_1|WR_LO,             0,              0,              D32,    0 },
  {"mtlo1",              "s",            0x70000013, 0xfc1fffff, RD_1|WR_LO,             0,              EE,             0,      0 },
  {"mtlhx",              "s",            0x00000053, 0xfc1fffff, RD_1|MOD_HILO,          0,              0,              SMT,    0 },
 -{"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1|RD_2,              0,              XLR,            0,      0 },
 +{"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1,                   0,              XLR|XLP,        0,      0 },
  {"mtm0",               "s",            0x70000008, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+ {"mtm0",               "s,t",          0x70000008, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
  {"mtm1",               "s",            0x7000000c, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
- {"mtm2",               "s",            0x7000000d, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
-@@ -1924,9 +1933,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
+@@ -1936,9 +1945,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
  {"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      I37},
  {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
  {"sw",                 "t,A(b)",       0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -430,5 +412,5 @@ index 2c3bbad..9785a7e 100644
  {"swc0",               "E,A(b)",       0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
  {"swc1",               "T,o(b)",       0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S,      0,              I1,             0,      0 },
 -- 
-2.1.4
+2.7.0