diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch b/meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch index 10c3d80865..1041b7301e 100644 --- a/meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch +++ b/meta/recipes-devtools/binutils/binutils/0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 7836f8aa56ef0f18c8658dc7e4952a9d097ba7e8 Mon Sep 17 00:00:00 2001 | 1 | From 7f4938d062146e40b4e6d427a5eca6cc6acaaeee Mon Sep 17 00:00:00 2001 |
2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> | 2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> |
3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 | 3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 |
4 | Subject: [PATCH 11/17] fix the incorrect assembling for ppc wait mnemonic | 4 | Subject: [PATCH] fix the incorrect assembling for ppc wait mnemonic |
5 | 5 | ||
6 | Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> | 6 | Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> |
7 | 7 | ||
@@ -11,10 +11,10 @@ Upstream-Status: Pending | |||
11 | 1 file changed, 1 insertion(+), 3 deletions(-) | 11 | 1 file changed, 1 insertion(+), 3 deletions(-) |
12 | 12 | ||
13 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c | 13 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c |
14 | index 5e20d617664..4c9656ecf08 100644 | 14 | index bbbadffad8f..72092355e12 100644 |
15 | --- a/opcodes/ppc-opc.c | 15 | --- a/opcodes/ppc-opc.c |
16 | +++ b/opcodes/ppc-opc.c | 16 | +++ b/opcodes/ppc-opc.c |
17 | @@ -6265,8 +6265,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 17 | @@ -6302,8 +6302,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
18 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | 18 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, |
19 | {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, 0, {0}}, | 19 | {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, 0, {0}}, |
20 | {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, 0, {0}}, | 20 | {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, 0, {0}}, |
@@ -23,7 +23,7 @@ index 5e20d617664..4c9656ecf08 100644 | |||
23 | 23 | ||
24 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | 24 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
25 | 25 | ||
26 | @@ -6326,7 +6324,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 26 | @@ -6363,7 +6361,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
27 | 27 | ||
28 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | 28 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
29 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, | 29 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
@@ -32,6 +32,3 @@ index 5e20d617664..4c9656ecf08 100644 | |||
32 | 32 | ||
33 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, | 33 | {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
34 | 34 | ||
35 | -- | ||
36 | 2.28.0 | ||
37 | |||