diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch | 393 |
1 files changed, 393 insertions, 0 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch new file mode 100644 index 0000000000..20c5ed6308 --- /dev/null +++ b/meta/recipes-devtools/binutils/binutils/0011-Add-support-for-Netlogic-XLP.patch | |||
@@ -0,0 +1,393 @@ | |||
1 | From e4a0cd30c7e9334ed507c93014a8b2d1315ff937 Mon Sep 17 00:00:00 2001 | ||
2 | From: Khem Raj <raj.khem@gmail.com> | ||
3 | Date: Sun, 14 Feb 2016 17:06:19 +0000 | ||
4 | Subject: [PATCH 11/15] Add support for Netlogic XLP | ||
5 | |||
6 | Patch From: Nebu Philips <nphilips@netlogicmicro.com> | ||
7 | |||
8 | Using the mipsisa64r2nlm target, add support for XLP from | ||
9 | Netlogic. Also, update vendor name to NLM wherever applicable. | ||
10 | |||
11 | Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been | ||
12 | assigned to INSN_OCTEON3 | ||
13 | |||
14 | Upstream-Status: Pending | ||
15 | |||
16 | Signed-off-by: Khem Raj <raj.khem@gmail.com> | ||
17 | Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com> | ||
18 | Signed-off-by: Mark Hatle <mark.hatle@windriver.com> | ||
19 | --- | ||
20 | bfd/aoutx.h | 1 + | ||
21 | bfd/archures.c | 1 + | ||
22 | bfd/bfd-in2.h | 1 + | ||
23 | bfd/config.bfd | 5 +++++ | ||
24 | bfd/cpu-mips.c | 6 ++++-- | ||
25 | bfd/elfxx-mips.c | 8 ++++++++ | ||
26 | binutils/readelf.c | 1 + | ||
27 | gas/config/tc-mips.c | 4 +++- | ||
28 | gas/configure | 3 +++ | ||
29 | include/elf/mips.h | 1 + | ||
30 | include/opcode/mips.h | 6 ++++++ | ||
31 | ld/configure.tgt | 2 ++ | ||
32 | opcodes/mips-dis.c | 12 +++++------- | ||
33 | opcodes/mips-opc.c | 31 ++++++++++++++++++++----------- | ||
34 | 14 files changed, 61 insertions(+), 21 deletions(-) | ||
35 | |||
36 | diff --git a/bfd/aoutx.h b/bfd/aoutx.h | ||
37 | index e5d8dcf390..2cc74a2d61 100644 | ||
38 | --- a/bfd/aoutx.h | ||
39 | +++ b/bfd/aoutx.h | ||
40 | @@ -799,6 +799,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, | ||
41 | case bfd_mach_mipsisa64r6: | ||
42 | case bfd_mach_mips_sb1: | ||
43 | case bfd_mach_mips_xlr: | ||
44 | + case bfd_mach_mips_xlp: | ||
45 | /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ | ||
46 | arch_flags = M_MIPS2; | ||
47 | break; | ||
48 | diff --git a/bfd/archures.c b/bfd/archures.c | ||
49 | index 647cf0d8d4..7e1d0c810f 100644 | ||
50 | --- a/bfd/archures.c | ||
51 | +++ b/bfd/archures.c | ||
52 | @@ -185,6 +185,7 @@ DESCRIPTION | ||
53 | .#define bfd_mach_mips_octeon3 6503 | ||
54 | .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *} | ||
55 | .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *} | ||
56 | +.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP'. *} | ||
57 | .#define bfd_mach_mipsisa32 32 | ||
58 | .#define bfd_mach_mipsisa32r2 33 | ||
59 | .#define bfd_mach_mipsisa32r3 34 | ||
60 | diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h | ||
61 | index e25da50aaf..e251d7e7aa 100644 | ||
62 | --- a/bfd/bfd-in2.h | ||
63 | +++ b/bfd/bfd-in2.h | ||
64 | @@ -2084,6 +2084,7 @@ enum bfd_architecture | ||
65 | #define bfd_mach_mips_octeon3 6503 | ||
66 | #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */ | ||
67 | #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */ | ||
68 | +#define bfd_mach_mips_xlp 887680 /* decimal 'XLP'. */ | ||
69 | #define bfd_mach_mipsisa32 32 | ||
70 | #define bfd_mach_mipsisa32r2 33 | ||
71 | #define bfd_mach_mipsisa32r3 34 | ||
72 | diff --git a/bfd/config.bfd b/bfd/config.bfd | ||
73 | index cc65547588..3614ff79d4 100644 | ||
74 | --- a/bfd/config.bfd | ||
75 | +++ b/bfd/config.bfd | ||
76 | @@ -902,6 +902,11 @@ case "${targ}" in | ||
77 | targ_defvec=mips_elf32_le_vec | ||
78 | targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" | ||
79 | ;; | ||
80 | + mipsisa64*-*-elf*) | ||
81 | + targ_defvec=mips_elf32_trad_be_vec | ||
82 | + targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec" | ||
83 | + want64=true | ||
84 | + ;; | ||
85 | mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none) | ||
86 | targ_defvec=mips_elf32_be_vec | ||
87 | targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec" | ||
88 | diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c | ||
89 | index b359491305..61a3e7aaca 100644 | ||
90 | --- a/bfd/cpu-mips.c | ||
91 | +++ b/bfd/cpu-mips.c | ||
92 | @@ -107,7 +107,8 @@ enum | ||
93 | I_mipsocteon3, | ||
94 | I_xlr, | ||
95 | I_interaptiv_mr2, | ||
96 | - I_micromips | ||
97 | + I_micromips, | ||
98 | + I_xlp | ||
99 | }; | ||
100 | |||
101 | #define NN(index) (&arch_info_struct[(index) + 1]) | ||
102 | @@ -162,7 +163,8 @@ static const bfd_arch_info_type arch_info_struct[] = | ||
103 | N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)), | ||
104 | N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE, | ||
105 | NN(I_interaptiv_mr2)), | ||
106 | - N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0) | ||
107 | + N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)), | ||
108 | + N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0) | ||
109 | }; | ||
110 | |||
111 | /* The default architecture is mips:3000, but with a machine number of | ||
112 | diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c | ||
113 | index 5998bc43a8..0d5795222b 100644 | ||
114 | --- a/bfd/elfxx-mips.c | ||
115 | +++ b/bfd/elfxx-mips.c | ||
116 | @@ -6919,6 +6919,9 @@ _bfd_elf_mips_mach (flagword flags) | ||
117 | case E_MIPS_MACH_IAMR2: | ||
118 | return bfd_mach_mips_interaptiv_mr2; | ||
119 | |||
120 | + case E_MIPS_MACH_XLP: | ||
121 | + return bfd_mach_mips_xlp; | ||
122 | + | ||
123 | default: | ||
124 | switch (flags & EF_MIPS_ARCH) | ||
125 | { | ||
126 | @@ -12199,6 +12202,10 @@ mips_set_isa_flags (bfd *abfd) | ||
127 | val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; | ||
128 | break; | ||
129 | |||
130 | + case bfd_mach_mips_xlp: | ||
131 | + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP; | ||
132 | + break; | ||
133 | + | ||
134 | case bfd_mach_mipsisa32: | ||
135 | val = E_MIPS_ARCH_32; | ||
136 | break; | ||
137 | @@ -14214,6 +14221,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = | ||
138 | { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e }, | ||
139 | { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 }, | ||
140 | { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 }, | ||
141 | + { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 }, | ||
142 | |||
143 | /* MIPS64 extensions. */ | ||
144 | { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, | ||
145 | diff --git a/binutils/readelf.c b/binutils/readelf.c | ||
146 | index b13eb6a43b..9df3742682 100644 | ||
147 | --- a/binutils/readelf.c | ||
148 | +++ b/binutils/readelf.c | ||
149 | @@ -3412,6 +3412,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) | ||
150 | case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; | ||
151 | case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; | ||
152 | case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break; | ||
153 | + case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break; | ||
154 | case 0: | ||
155 | /* We simply ignore the field in this case to avoid confusion: | ||
156 | MIPS ELF does not specify EF_MIPS_MACH, it is a GNU | ||
157 | diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c | ||
158 | index ae55904229..d6882712f5 100644 | ||
159 | --- a/gas/config/tc-mips.c | ||
160 | +++ b/gas/config/tc-mips.c | ||
161 | @@ -554,6 +554,7 @@ static int mips_32bitmode = 0; | ||
162 | || mips_opts.arch == CPU_RM7000 \ | ||
163 | || mips_opts.arch == CPU_VR5500 \ | ||
164 | || mips_opts.micromips \ | ||
165 | + || mips_opts.arch == CPU_XLP \ | ||
166 | ) | ||
167 | |||
168 | /* Whether the processor uses hardware interlocks to protect reads | ||
169 | @@ -583,6 +584,7 @@ static int mips_32bitmode = 0; | ||
170 | && mips_opts.isa != ISA_MIPS3) \ | ||
171 | || mips_opts.arch == CPU_R4300 \ | ||
172 | || mips_opts.micromips \ | ||
173 | + || mips_opts.arch == CPU_XLP \ | ||
174 | ) | ||
175 | |||
176 | /* Whether the processor uses hardware interlocks to protect reads | ||
177 | @@ -19867,7 +19869,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = | ||
178 | /* Broadcom XLP. | ||
179 | XLP is mostly like XLR, with the prominent exception that it is | ||
180 | MIPS64R2 rather than MIPS64. */ | ||
181 | - { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, | ||
182 | + { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP }, | ||
183 | |||
184 | /* MIPS 64 Release 6 */ | ||
185 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, | ||
186 | diff --git a/gas/configure b/gas/configure | ||
187 | index a82fde7fa8..afc77c347a 100755 | ||
188 | --- a/gas/configure | ||
189 | +++ b/gas/configure | ||
190 | @@ -13364,6 +13364,9 @@ _ACEOF | ||
191 | mipsisa64r6 | mipsisa64r6el) | ||
192 | mips_cpu=mips64r6 | ||
193 | ;; | ||
194 | + mipsisa64r2nlm | mipsisa64r2nlmel) | ||
195 | + mips_cpu=xlp | ||
196 | + ;; | ||
197 | mipstx39 | mipstx39el) | ||
198 | mips_cpu=r3900 | ||
199 | ;; | ||
200 | diff --git a/include/elf/mips.h b/include/elf/mips.h | ||
201 | index b76d450ae2..7cddb365ad 100644 | ||
202 | --- a/include/elf/mips.h | ||
203 | +++ b/include/elf/mips.h | ||
204 | @@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) | ||
205 | #define E_MIPS_MACH_SB1 0x008a0000 | ||
206 | #define E_MIPS_MACH_OCTEON 0x008b0000 | ||
207 | #define E_MIPS_MACH_XLR 0x008c0000 | ||
208 | +#define E_MIPS_MACH_XLP 0x008f0000 | ||
209 | #define E_MIPS_MACH_OCTEON2 0x008d0000 | ||
210 | #define E_MIPS_MACH_OCTEON3 0x008e0000 | ||
211 | #define E_MIPS_MACH_5400 0x00910000 | ||
212 | diff --git a/include/opcode/mips.h b/include/opcode/mips.h | ||
213 | index abd52c8980..53b6752a1c 100644 | ||
214 | --- a/include/opcode/mips.h | ||
215 | +++ b/include/opcode/mips.h | ||
216 | @@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table[] = { | ||
217 | #define INSN_XLR 0x00000020 | ||
218 | /* Imagination interAptiv MR2. */ | ||
219 | #define INSN_INTERAPTIV_MR2 0x04000000 | ||
220 | +/* Netlogic XlP instruction */ | ||
221 | +#define INSN_XLP 0x00000080 | ||
222 | |||
223 | /* DSP ASE */ | ||
224 | #define ASE_DSP 0x00000001 | ||
225 | @@ -1381,6 +1383,7 @@ static const unsigned int mips_isa_table[] = { | ||
226 | #define CPU_OCTEON3 6503 | ||
227 | #define CPU_XLR 887682 /* decimal 'XLR' */ | ||
228 | #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ | ||
229 | +#define CPU_XLP 887680 /* decimal 'XLP' */ | ||
230 | |||
231 | /* Return true if the given CPU is included in INSN_* mask MASK. */ | ||
232 | |||
233 | @@ -1458,6 +1461,9 @@ cpu_is_member (int cpu, unsigned int mask) | ||
234 | return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) | ||
235 | || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); | ||
236 | |||
237 | + case CPU_XLP: | ||
238 | + return (mask & INSN_XLP) != 0; | ||
239 | + | ||
240 | default: | ||
241 | return FALSE; | ||
242 | } | ||
243 | diff --git a/ld/configure.tgt b/ld/configure.tgt | ||
244 | index 917be6f8eb..347df6c3f6 100644 | ||
245 | --- a/ld/configure.tgt | ||
246 | +++ b/ld/configure.tgt | ||
247 | @@ -454,6 +454,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) | ||
248 | mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) | ||
249 | targ_emul=elf32btsmip | ||
250 | targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; | ||
251 | +mipsisa64*-*-elf*) targ_emul=elf32btsmip | ||
252 | + targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;; | ||
253 | mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 | ||
254 | targ_extra_emuls="elf32lr5900" | ||
255 | targ_extra_libpath=$targ_extra_emuls ;; | ||
256 | diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c | ||
257 | index 0dd85e3779..1ea708dde7 100644 | ||
258 | --- a/opcodes/mips-dis.c | ||
259 | +++ b/opcodes/mips-dis.c | ||
260 | @@ -673,13 +673,11 @@ const struct mips_arch_choice mips_arch_choices[] = | ||
261 | mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), | ||
262 | mips_cp1_names_mips3264, mips_hwr_names_numeric }, | ||
263 | |||
264 | - /* XLP is mostly like XLR, with the prominent exception it is being | ||
265 | - MIPS64R2. */ | ||
266 | - { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR, | ||
267 | - ISA_MIPS64R2 | INSN_XLR, 0, | ||
268 | - mips_cp0_names_xlr, | ||
269 | - mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), | ||
270 | - mips_cp1_names_mips3264, mips_hwr_names_numeric }, | ||
271 | + { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP, | ||
272 | + ISA_MIPS64R2 | INSN_XLP, 0, | ||
273 | + mips_cp0_names_mips3264r2, | ||
274 | + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), | ||
275 | + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, | ||
276 | |||
277 | /* This entry, mips16, is here only for ISA/processor selection; do | ||
278 | not print its name. */ | ||
279 | diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c | ||
280 | index 837da6bd99..d3ea5b8877 100644 | ||
281 | --- a/opcodes/mips-opc.c | ||
282 | +++ b/opcodes/mips-opc.c | ||
283 | @@ -328,6 +328,7 @@ decode_mips_operand (const char *p) | ||
284 | #define IOCT3 INSN_OCTEON3 | ||
285 | #define XLR INSN_XLR | ||
286 | #define IAMR2 INSN_INTERAPTIV_MR2 | ||
287 | +#define XLP INSN_XLP | ||
288 | #define IVIRT ASE_VIRT | ||
289 | #define IVIRT64 ASE_VIRT64 | ||
290 | |||
291 | @@ -989,6 +990,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
292 | {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, | ||
293 | {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, | ||
294 | {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, | ||
295 | +{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, | ||
296 | /* ctc0 is at the bottom of the table. */ | ||
297 | {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, | ||
298 | {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, | ||
299 | @@ -1021,12 +1023,13 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
300 | {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, | ||
301 | {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, | ||
302 | {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, | ||
303 | -{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, | ||
304 | +{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 }, | ||
305 | {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, | ||
306 | {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, | ||
307 | {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, | ||
308 | {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, | ||
309 | {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, | ||
310 | +{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, | ||
311 | /* dctr and dctw are used on the r5000. */ | ||
312 | {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, | ||
313 | {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, | ||
314 | @@ -1098,6 +1101,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
315 | {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, | ||
316 | {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, | ||
317 | {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, | ||
318 | +{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 }, | ||
319 | {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, | ||
320 | {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, | ||
321 | {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, | ||
322 | @@ -1113,6 +1117,8 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
323 | /* dmfc3 is at the bottom of the table. */ | ||
324 | /* dmtc3 is at the bottom of the table. */ | ||
325 | {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, | ||
326 | +{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 }, | ||
327 | +{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 }, | ||
328 | {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, | ||
329 | {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, | ||
330 | {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, | ||
331 | @@ -1266,9 +1272,9 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
332 | {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, | ||
333 | {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, | ||
334 | {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, | ||
335 | -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
336 | -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
337 | -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
338 | +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
339 | +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
340 | +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
341 | {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | ||
342 | {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, | ||
343 | {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, | ||
344 | @@ -1433,7 +1439,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
345 | {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, | ||
346 | {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, | ||
347 | {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, | ||
348 | -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, | ||
349 | +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 }, | ||
350 | {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, | ||
351 | {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, | ||
352 | {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, | ||
353 | @@ -1478,10 +1484,13 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
354 | /* move is at the top of the table. */ | ||
355 | {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, | ||
356 | {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, | ||
357 | +{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, | ||
358 | {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 }, | ||
359 | {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, | ||
360 | -{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, | ||
361 | -{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, | ||
362 | +{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 }, | ||
363 | +{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 }, | ||
364 | +{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 }, | ||
365 | +{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 }, | ||
366 | {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, | ||
367 | {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, | ||
368 | {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, | ||
369 | @@ -1531,7 +1540,7 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
370 | {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, | ||
371 | {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, | ||
372 | {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, | ||
373 | -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, | ||
374 | +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 }, | ||
375 | {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | ||
376 | {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, | ||
377 | {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, | ||
378 | @@ -1968,9 +1977,9 @@ const struct mips_opcode mips_builtin_opcodes[] = | ||
379 | {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, | ||
380 | {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, | ||
381 | {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, | ||
382 | -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
383 | -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
384 | -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, | ||
385 | +{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
386 | +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
387 | +{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 }, | ||
388 | {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, | ||
389 | {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, | ||
390 | {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, | ||
391 | -- | ||
392 | 2.20.1 | ||
393 | |||