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-rw-r--r--meta/recipes-core/glibc/glibc/0022-eglibc-Clear-cache-lines-on-ppc8xx.patch81
1 files changed, 81 insertions, 0 deletions
diff --git a/meta/recipes-core/glibc/glibc/0022-eglibc-Clear-cache-lines-on-ppc8xx.patch b/meta/recipes-core/glibc/glibc/0022-eglibc-Clear-cache-lines-on-ppc8xx.patch
new file mode 100644
index 0000000000..8a4c9c3e89
--- /dev/null
+++ b/meta/recipes-core/glibc/glibc/0022-eglibc-Clear-cache-lines-on-ppc8xx.patch
@@ -0,0 +1,81 @@
1From be7273225698074347a71de58006977bb304d7f7 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Wed, 18 Mar 2015 00:53:47 +0000
4Subject: [PATCH 22/27] eglibc: Clear cache lines on ppc8xx
5
62007-06-13 Nathan Sidwell <nathan@codesourcery.com>
7 Mark Shinwell <shinwell@codesourcery.com>
8
9 * sysdeps/unix/sysv/linux/powerpc/libc-start.c
10 (__libc_start_main): Detect 8xx parts and clear
11 __cache_line_size if detected.
12 * sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
13 (DL_PLATFORM_AUXV): Likewise.
14
15Upstream-Status: Pending
16Signed-off-by: Khem Raj <raj.khem@gmail.com>
17---
18 sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c | 14 +++++++++++++-
19 sysdeps/unix/sysv/linux/powerpc/libc-start.c | 15 ++++++++++++++-
20 2 files changed, 27 insertions(+), 2 deletions(-)
21
22diff --git a/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c b/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
23index c2504ff..d50f1cb 100644
24--- a/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
25+++ b/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
26@@ -24,9 +24,21 @@ int __cache_line_size attribute_hidden;
27 /* Scan the Aux Vector for the "Data Cache Block Size" entry. If found
28 verify that the static extern __cache_line_size is defined by checking
29 for not NULL. If it is defined then assign the cache block size
30- value to __cache_line_size. */
31+ value to __cache_line_size. This is used by memset to
32+ optimize setting to zero. We have to detect 8xx processors, which
33+ have buggy dcbz implementations that cannot report page faults
34+ correctly. That requires reading SPR, which is a privileged
35+ operation. Fortunately 2.2.18 and later emulates PowerPC mfspr
36+ reads from the PVR register. */
37 #define DL_PLATFORM_AUXV \
38 case AT_DCACHEBSIZE: \
39+ if (__LINUX_KERNEL_VERSION >= 0x020218) \
40+ { \
41+ unsigned pvr = 0; \
42+ asm ("mfspr %0, 287" : "=r" (pvr)); \
43+ if ((pvr & 0xffff0000) == 0x00500000) \
44+ break; \
45+ } \
46 __cache_line_size = av->a_un.a_val; \
47 break;
48
49diff --git a/sysdeps/unix/sysv/linux/powerpc/libc-start.c b/sysdeps/unix/sysv/linux/powerpc/libc-start.c
50index a9364c7..a3ed1d4 100644
51--- a/sysdeps/unix/sysv/linux/powerpc/libc-start.c
52+++ b/sysdeps/unix/sysv/linux/powerpc/libc-start.c
53@@ -68,11 +68,24 @@ __libc_start_main (int argc, char **argv,
54 rtld_fini = NULL;
55 }
56
57- /* Initialize the __cache_line_size variable from the aux vector. */
58+ /* Initialize the __cache_line_size variable from the aux vector.
59+ This is used by memset to optimize setting to zero. We have to
60+ detect 8xx processors, which have buggy dcbz implementations that
61+ cannot report page faults correctly. That requires reading SPR,
62+ which is a privileged operation. Fortunately 2.2.18 and later
63+ emulates PowerPC mfspr reads from the PVR register. */
64 for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av)
65 switch (av->a_type)
66 {
67 case AT_DCACHEBSIZE:
68+ if (__LINUX_KERNEL_VERSION >= 0x020218)
69+ {
70+ unsigned pvr = 0;
71+
72+ asm ("mfspr %0, 287" : "=r" (pvr) :);
73+ if ((pvr & 0xffff0000) == 0x00500000)
74+ break;
75+ }
76 __cache_line_size = av->a_un.a_val;
77 break;
78 }
79--
802.1.4
81