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-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch1481
1 files changed, 1481 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch
new file mode 100644
index 0000000000..09392ad2cf
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch
@@ -0,0 +1,1481 @@
1Add support for the Samsung SMDK2440 development board
2
3Index: u-boot/Makefile
4===================================================================
5--- u-boot.orig/Makefile
6+++ u-boot/Makefile
7@@ -2035,6 +2035,9 @@
8 smdk2410_config : unconfig
9 @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
10
11+smdk2440_config : unconfig
12+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0
13+
14 SX1_config : unconfig
15 @$(MKCONFIG) $(@:_config=) arm arm925t sx1
16
17Index: u-boot/include/configs/smdk2440.h
18===================================================================
19--- /dev/null
20+++ u-boot/include/configs/smdk2440.h
21@@ -0,0 +1,296 @@
22+/*
23+ * (C) Copyright 2002
24+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
25+ * Marius Groeger <mgroeger@sysgo.de>
26+ * Gary Jennejohn <gj@denx.de>
27+ * David Mueller <d.mueller@elsoft.ch>
28+ *
29+ * Configuation settings for the SAMSUNG SMDK2440 board.
30+ *
31+ * See file CREDITS for list of people who contributed to this
32+ * project.
33+ *
34+ * This program is free software; you can redistribute it and/or
35+ * modify it under the terms of the GNU General Public License as
36+ * published by the Free Software Foundation; either version 2 of
37+ * the License, or (at your option) any later version.
38+ *
39+ * This program is distributed in the hope that it will be useful,
40+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
41+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42+ * GNU General Public License for more details.
43+ *
44+ * You should have received a copy of the GNU General Public License
45+ * along with this program; if not, write to the Free Software
46+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
47+ * MA 02111-1307 USA
48+ */
49+
50+#ifndef __CONFIG_H
51+#define __CONFIG_H
52+
53+#if 0
54+/* If we want to start u-boot from usb bootloader in NOR flash */
55+#define CONFIG_SKIP_RELOCATE_UBOOT 1
56+#define CONFIG_SKIP_LOWLEVEL_INIT 1
57+#else
58+/* If we want to start u-boot directly from within NAND flash */
59+#define CONFIG_LL_INIT_NAND_ONLY
60+#define CONFIG_S3C2410_NAND_BOOT 1
61+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
62+#endif
63+
64+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
65+
66+/*
67+ * High Level Configuration Options
68+ * (easy to change)
69+ */
70+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
71+#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
72+#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */
73+
74+/* input clock of PLL */
75+#define CONFIG_SYS_CLK_FREQ 16934400/* SMDK2440 has 16.9344MHz input clock */
76+
77+
78+#define USE_920T_MMU 1
79+#define CONFIG_USE_IRQ 1
80+//#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
81+
82+/*
83+ * Size of malloc() pool
84+ */
85+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024)
86+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
87+
88+/*
89+ * Hardware drivers
90+ */
91+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
92+#define CS8900_BASE 0x19000300
93+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
94+
95+/*
96+ * select serial console configuration
97+ */
98+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */
99+#define CONFIG_HWFLOW 1
100+
101+/************************************************************
102+ * RTC
103+ ************************************************************/
104+#define CONFIG_RTC_S3C24X0 1
105+
106+/* allow to overwrite serial and ethaddr */
107+#define CONFIG_ENV_OVERWRITE
108+
109+#define CONFIG_BAUDRATE 115200
110+
111+/***********************************************************
112+ * Command definition
113+ ***********************************************************/
114+#define CONFIG_COMMANDS \
115+ (CONFIG_CMD_DFL | \
116+ /*CFG_CMD_BSP | */ \
117+ CFG_CMD_CACHE | \
118+ CFG_CMD_DATE | \
119+ /*CFG_CMD_DHCP | */ \
120+ CFG_CMD_DIAG | \
121+ CFG_CMD_ELF | \
122+ CFG_CMD_EXT2 | \
123+ CFG_CMD_FAT | \
124+ /*CFG_CMD_HWFLOW | */ \
125+ /* CFG_CMD_IDE | */ \
126+ /* CFG_CMD_IRQ | */ \
127+ CFG_CMD_JFFS2 | \
128+ CFG_CMD_MMC | \
129+ CFG_CMD_NAND | \
130+ CFG_CMD_PING | \
131+ CFG_CMD_PORTIO | \
132+ CFG_CMD_REGINFO | \
133+ CFG_CMD_SAVES | \
134+ CFG_CMD_USB)
135+
136+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
137+#include <cmd_confdefs.h>
138+
139+#define CONFIG_BOOTDELAY 3
140+#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8"
141+#define CONFIG_ETHADDR 00:0c:20:02:0a:5b
142+#define CONFIG_NETMASK 255.255.255.0
143+#define CONFIG_IPADDR 192.168.1.100
144+#define CONFIG_SERVERIP 192.168.1.21
145+/*#define CONFIG_BOOTFILE "elinos-lart" */
146+//#define CONFIG_BOOTCOMMAND "nand read 0x32000000 0x34000 0x200000; bootm"
147+#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm"
148+
149+#define CONFIG_DOS_PARTITION 1
150+
151+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
152+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
153+/* what's this ? it's not used anywhere */
154+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
155+#endif
156+
157+/*
158+ * Miscellaneous configurable options
159+ */
160+#define CFG_LONGHELP /* undef to save memory */
161+#define CFG_PROMPT "SMDK2440 # " /* Monitor Command Prompt */
162+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
163+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
164+#define CFG_MAXARGS 32 /* max number of command args */
165+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
166+
167+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
168+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
169+
170+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
171+
172+#define CFG_LOAD_ADDR 0x32000000 /* default load address */
173+
174+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
175+/* it to wrap 100 times (total 1562500) to get 1 sec. */
176+#define CFG_HZ 1562500
177+
178+/* valid baudrates */
179+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
180+
181+/*-----------------------------------------------------------------------
182+ * Stack sizes
183+ *
184+ * The stack sizes are set up in start.S using the settings below
185+ */
186+#define CONFIG_STACKSIZE (512*1024) /* regular stack */
187+#ifdef CONFIG_USE_IRQ
188+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
189+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
190+#endif
191+
192+/* IDE/ATA config */
193+
194+#if 0
195+#define CFG_IDE_MAXBUS 1
196+#define CFG_IDE_MAXDEVICE 2
197+#define CFG_IDE_PREINIT 0
198+
199+#define CFG_ATA_BASE_ADDR
200+#endif
201+
202+#define CONFIG_USB_OHCI 1
203+
204+#define CONFIG_USB_DEVICE 1
205+#define CONFIG_USB_TTY 1
206+#define CFG_CONSOLE_IS_IN_ENV 1
207+#define CONFIG_USBD_VENDORID 0x1457 /* FIC */
208+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
209+#define CONFIG_USBD_PRODUCTID_CDCACM 0x511b /* SMDK2440 CDC ACM */
210+#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc."
211+#define CONFIG_USBD_PRODUCT_NAME "S3C2440 Bootloader " U_BOOT_VERSION
212+#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0"
213+#define CONFIG_USBD_DFU 1
214+#define CONFIG_USBD_DFU_XFER_SIZE 4096
215+#define CONFIG_USBD_DFU_INTERFACE 2
216+
217+/*-----------------------------------------------------------------------
218+ * Physical Memory Map
219+ */
220+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
221+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
222+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
223+
224+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
225+
226+#define CFG_FLASH_BASE PHYS_FLASH_1
227+
228+/*-----------------------------------------------------------------------
229+ * FLASH and environment organization
230+ */
231+
232+#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
233+#if 0
234+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
235+#endif
236+
237+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
238+#ifdef CONFIG_AMD_LV800
239+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
240+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
241+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
242+#endif
243+#ifdef CONFIG_AMD_LV400
244+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
245+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
246+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
247+#endif
248+
249+/* timeout values are in ticks */
250+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
251+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
252+
253+#define CFG_ENV_IS_IN_NAND 1
254+#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */
255+#define CFG_ENV_OFFSET_OOB 1
256+#define CFG_PREBOOT_OVERRIDE 1
257+
258+#define NAND_MAX_CHIPS 1
259+#define CFG_NAND_BASE 0x4e000000
260+#define CFG_MAX_NAND_DEVICE 1
261+
262+#define CONFIG_MMC 1
263+#define CFG_MMC_BASE 0xff000000
264+
265+#define CONFIG_EXT2 1
266+
267+#define CONFIG_NEW_QT2440 0
268+
269+/* FAT driver in u-boot is broken currently */
270+#define CONFIG_FAT 1
271+#define CONFIG_SUPPORT_VFAT
272+
273+#if 1
274+/* JFFS2 driver */
275+#define CONFIG_JFFS2_CMDLINE 1
276+#define CONFIG_JFFS2_NAND 1
277+#define CONFIG_JFFS2_NAND_DEV 0
278+//#define CONFIG_JFFS2_NAND_OFF 0x634000
279+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
280+#endif
281+
282+/* ATAG configuration */
283+#define CONFIG_INITRD_TAG 1
284+#define CONFIG_SETUP_MEMORY_TAGS 1
285+#define CONFIG_CMDLINE_TAG 1
286+#if 0
287+#define CONFIG_SERIAL_TAG 1
288+#define CONFIG_REVISION_TAG 1
289+#endif
290+
291+
292+#if 0
293+#define CONFIG_VIDEO
294+#define CONFIG_VIDEO_S3C2410
295+#define CONFIG_CFB_CONSOLE
296+#define CONFIG_VIDEO_LOGO
297+#define CONFIG_VGA_AS_SINGLE_DEVICE
298+
299+#define VIDEO_KBD_INIT_FCT 0
300+#define VIDEO_TSTC_FCT serial_tstc
301+#define VIDEO_GETC_FCT serial_getc
302+
303+#define LCD_VIDEO_ADDR 0x33d00000
304+#endif
305+
306+#define CONFIG_S3C2410_NAND_BBT 1
307+//#define CONFIG_S3C2410_NAND_HWECC 1
308+
309+#define CFG_NAND_YAFFS_WRITE
310+#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT
311+
312+#define MTDIDS_DEFAULT "nand0=smdk2440-nand"
313+#define MTPARTS_DEFAULT "smdk2440-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)"
314+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2440-nand"
315+#define CONFIG_NAND_DYNPART
316+
317+#endif /* __CONFIG_H */
318Index: u-boot/include/configs/smdk2440nand.h
319===================================================================
320--- /dev/null
321+++ u-boot/include/configs/smdk2440nand.h
322@@ -0,0 +1,47 @@
323+/*
324+ * (C) Copyright 2004
325+ * Samsung Electronics : SW.LEE <hitchcar@samsung.com>
326+ *
327+ * This program is free software; you can redistribute it and/or
328+ * modify it under the terms of the GNU General Public License as
329+ * published by the Free Software Foundation; either version 2 of
330+ * the License, or (at your option) any later version.
331+ *
332+ */
333+
334+#ifndef __SMDK2440_NAND_H
335+#define __SMDK2440_NAND_H
336+
337+#define CFG_ENV_NAND_BLOCK 8
338+
339+#if 0 //old flash
340+#define NAND_OOB_SIZE (16)
341+#define NAND_PAGES_IN_BLOCK (32)
342+#define NAND_PAGE_SIZE (512)
343+
344+#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK)
345+#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1)
346+#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1)
347+#else //new flash
348+#define NAND_OOB_SIZE (64)
349+#define NAND_PAGES_IN_BLOCK (64)
350+#define NAND_PAGE_SIZE (2048)
351+
352+#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK)
353+#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1)
354+#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1)
355+
356+#endif
357+
358+
359+
360+//#define NAND_3_ADDR_CYCLE 1
361+//#define S3C24X0_16BIT_NAND 1
362+
363+#ifdef KINGFISH
364+#undef S3C24X0_16BIT_NAND
365+#define S3C24X0_16BIT_NAND 1
366+#endif
367+
368+#endif
369+
370Index: u-boot/board/smdk2440/Makefile
371===================================================================
372--- /dev/null
373+++ u-boot/board/smdk2440/Makefile
374@@ -0,0 +1,67 @@
375+#
376+# (C) Copyright 2000-2006
377+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
378+#
379+# See file CREDITS for list of people who contributed to this
380+# project.
381+#
382+# This program is free software; you can redistribute it and/or
383+# modify it under the terms of the GNU General Public License as
384+# published by the Free Software Foundation; either version 2 of
385+# the License, or (at your option) any later version.
386+#
387+# This program is distributed in the hope that it will be useful,
388+# but WITHOUT ANY WARRANTY; without even the implied warranty of
389+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
390+# GNU General Public License for more details.
391+#
392+# You should have received a copy of the GNU General Public License
393+# along with this program; if not, write to the Free Software
394+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
395+# MA 02111-1307 USA
396+#
397+
398+include $(TOPDIR)/config.mk
399+
400+LIB = $(obj)lib$(BOARD).a
401+
402+COBJS := smdk2440.o flash.o udc.o
403+SOBJS := lowlevel_init.o
404+
405+.PHONY: all
406+
407+all: $(LIB) lowlevel_foo.bin
408+
409+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
410+OBJS := $(addprefix $(obj),$(COBJS))
411+SOBJS := $(addprefix $(obj),$(SOBJS))
412+
413+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
414+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
415+
416+lowlevel_foo.o: lowlevel_foo.S
417+ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
418+ -o lowlevel_foo.o lowlevel_foo.S
419+
420+lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds
421+ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
422+ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
423+
424+lowlevel_foo.bin: lowlevel_foo
425+ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
426+ lowlevel_foo lowlevel_foo.bin
427+
428+clean:
429+ rm -f $(SOBJS) $(OBJS)
430+
431+distclean: clean
432+ rm -f $(LIB) core *.bak .depend
433+
434+#########################################################################
435+
436+# defines $(obj).depend target
437+include $(SRCTREE)/rules.mk
438+
439+sinclude $(obj).depend
440+
441+#########################################################################
442Index: u-boot/board/smdk2440/config.mk
443===================================================================
444--- /dev/null
445+++ u-boot/board/smdk2440/config.mk
446@@ -0,0 +1,29 @@
447+#
448+# (C) Copyright 2002
449+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
450+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
451+#
452+# SAMSUNG SMDK2440 board with S3C2440 (ARM920T) cpu
453+#
454+# see http://www.samsung.com/ for more information on SAMSUNG
455+#
456+
457+CONFIG_USB_DFU_VENDOR=0x1457
458+CONFIG_USB_DFU_PRODUCT=0x511b
459+CONFIG_USB_DFU_REVISION=0x0100
460+
461+#
462+# SMDK2440 has 1 bank of 64 MB DRAM
463+#
464+# 3000'0000 to 3400'0000
465+#
466+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
467+# optionally with a ramdisk at 3080'0000
468+#
469+# we load ourself to 33F8'0000
470+#
471+# download area is 3300'0000
472+#
473+
474+
475+TEXT_BASE = 0x33F80000
476Index: u-boot/board/smdk2440/flash.c
477===================================================================
478--- /dev/null
479+++ u-boot/board/smdk2440/flash.c
480@@ -0,0 +1,433 @@
481+/*
482+ * (C) Copyright 2002
483+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
484+ * Alex Zuepke <azu@sysgo.de>
485+ *
486+ * See file CREDITS for list of people who contributed to this
487+ * project.
488+ *
489+ * This program is free software; you can redistribute it and/or
490+ * modify it under the terms of the GNU General Public License as
491+ * published by the Free Software Foundation; either version 2 of
492+ * the License, or (at your option) any later version.
493+ *
494+ * This program is distributed in the hope that it will be useful,
495+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
496+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
497+ * GNU General Public License for more details.
498+ *
499+ * You should have received a copy of the GNU General Public License
500+ * along with this program; if not, write to the Free Software
501+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
502+ * MA 02111-1307 USA
503+ */
504+
505+#include <common.h>
506+
507+ulong myflush (void);
508+
509+
510+#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
511+#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
512+
513+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
514+
515+
516+#define CMD_READ_ARRAY 0x000000F0
517+#define CMD_UNLOCK1 0x000000AA
518+#define CMD_UNLOCK2 0x00000055
519+#define CMD_ERASE_SETUP 0x00000080
520+#define CMD_ERASE_CONFIRM 0x00000030
521+#define CMD_PROGRAM 0x000000A0
522+#define CMD_UNLOCK_BYPASS 0x00000020
523+
524+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
525+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
526+
527+#define BIT_ERASE_DONE 0x00000080
528+#define BIT_RDY_MASK 0x00000080
529+#define BIT_PROGRAM_ERROR 0x00000020
530+#define BIT_TIMEOUT 0x80000000 /* our flag */
531+
532+#define READY 1
533+#define ERR 2
534+#define TMO 4
535+
536+/*-----------------------------------------------------------------------
537+ */
538+
539+ulong flash_init (void)
540+{
541+ int i, j;
542+ ulong size = 0;
543+
544+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
545+ ulong flashbase = 0;
546+
547+ flash_info[i].flash_id =
548+#if defined(CONFIG_AMD_LV400)
549+ (AMD_MANUFACT & FLASH_VENDMASK) |
550+ (AMD_ID_LV400B & FLASH_TYPEMASK);
551+#elif defined(CONFIG_AMD_LV800)
552+ (AMD_MANUFACT & FLASH_VENDMASK) |
553+ (AMD_ID_LV800B & FLASH_TYPEMASK);
554+#else
555+#error "Unknown flash configured"
556+#endif
557+ flash_info[i].size = FLASH_BANK_SIZE;
558+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
559+ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
560+ if (i == 0)
561+ flashbase = PHYS_FLASH_1;
562+ else
563+ panic ("configured too many flash banks!\n");
564+ for (j = 0; j < flash_info[i].sector_count; j++) {
565+ if (j <= 3) {
566+ /* 1st one is 16 KB */
567+ if (j == 0) {
568+ flash_info[i].start[j] =
569+ flashbase + 0;
570+ }
571+
572+ /* 2nd and 3rd are both 8 KB */
573+ if ((j == 1) || (j == 2)) {
574+ flash_info[i].start[j] =
575+ flashbase + 0x4000 + (j -
576+ 1) *
577+ 0x2000;
578+ }
579+
580+ /* 4th 32 KB */
581+ if (j == 3) {
582+ flash_info[i].start[j] =
583+ flashbase + 0x8000;
584+ }
585+ } else {
586+ flash_info[i].start[j] =
587+ flashbase + (j - 3) * MAIN_SECT_SIZE;
588+ }
589+ }
590+ size += flash_info[i].size;
591+ }
592+
593+ flash_protect (FLAG_PROTECT_SET,
594+ CFG_FLASH_BASE,
595+ CFG_FLASH_BASE + monitor_flash_len - 1,
596+ &flash_info[0]);
597+
598+ flash_protect (FLAG_PROTECT_SET,
599+ CFG_ENV_ADDR,
600+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
601+
602+ return size;
603+}
604+
605+/*-----------------------------------------------------------------------
606+ */
607+void flash_print_info (flash_info_t * info)
608+{
609+ int i;
610+
611+ switch (info->flash_id & FLASH_VENDMASK) {
612+ case (AMD_MANUFACT & FLASH_VENDMASK):
613+ printf ("AMD: ");
614+ break;
615+ default:
616+ printf ("Unknown Vendor ");
617+ break;
618+ }
619+
620+ switch (info->flash_id & FLASH_TYPEMASK) {
621+ case (AMD_ID_LV400B & FLASH_TYPEMASK):
622+ printf ("1x Amd29LV400BB (4Mbit)\n");
623+ break;
624+ case (AMD_ID_LV800B & FLASH_TYPEMASK):
625+ printf ("1x Amd29LV800BB (8Mbit)\n");
626+ break;
627+ default:
628+ printf ("Unknown Chip Type\n");
629+ goto Done;
630+ break;
631+ }
632+
633+ printf (" Size: %ld MB in %d Sectors\n",
634+ info->size >> 20, info->sector_count);
635+
636+ printf (" Sector Start Addresses:");
637+ for (i = 0; i < info->sector_count; i++) {
638+ if ((i % 5) == 0) {
639+ printf ("\n ");
640+ }
641+ printf (" %08lX%s", info->start[i],
642+ info->protect[i] ? " (RO)" : " ");
643+ }
644+ printf ("\n");
645+
646+ Done:;
647+}
648+
649+/*-----------------------------------------------------------------------
650+ */
651+
652+int flash_erase (flash_info_t * info, int s_first, int s_last)
653+{
654+ ushort result;
655+ int iflag, cflag, prot, sect;
656+ int rc = ERR_OK;
657+ int chip;
658+
659+ /* first look for protection bits */
660+
661+ if (info->flash_id == FLASH_UNKNOWN)
662+ return ERR_UNKNOWN_FLASH_TYPE;
663+
664+ if ((s_first < 0) || (s_first > s_last)) {
665+ return ERR_INVAL;
666+ }
667+
668+ if ((info->flash_id & FLASH_VENDMASK) !=
669+ (AMD_MANUFACT & FLASH_VENDMASK)) {
670+ return ERR_UNKNOWN_FLASH_VENDOR;
671+ }
672+
673+ prot = 0;
674+ for (sect = s_first; sect <= s_last; ++sect) {
675+ if (info->protect[sect]) {
676+ prot++;
677+ }
678+ }
679+ if (prot)
680+ return ERR_PROTECTED;
681+
682+ /*
683+ * Disable interrupts which might cause a timeout
684+ * here. Remember that our exception vectors are
685+ * at address 0 in the flash, and we don't want a
686+ * (ticker) exception to happen while the flash
687+ * chip is in programming mode.
688+ */
689+ cflag = icache_status ();
690+ icache_disable ();
691+ iflag = disable_interrupts ();
692+
693+ /* Start erase on unprotected sectors */
694+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
695+ printf ("Erasing sector %2d ... ", sect);
696+
697+ /* arm simple, non interrupt dependent timer */
698+ reset_timer_masked ();
699+
700+ if (info->protect[sect] == 0) { /* not protected */
701+ vu_short *addr = (vu_short *) (info->start[sect]);
702+
703+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
704+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
705+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
706+
707+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
708+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
709+ *addr = CMD_ERASE_CONFIRM;
710+
711+ /* wait until flash is ready */
712+ chip = 0;
713+
714+ do {
715+ result = *addr;
716+
717+ /* check timeout */
718+ if (get_timer_masked () >
719+ CFG_FLASH_ERASE_TOUT) {
720+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
721+ chip = TMO;
722+ break;
723+ }
724+
725+ if (!chip
726+ && (result & 0xFFFF) & BIT_ERASE_DONE)
727+ chip = READY;
728+
729+ if (!chip
730+ && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
731+ chip = ERR;
732+
733+ } while (!chip);
734+
735+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
736+
737+ if (chip == ERR) {
738+ rc = ERR_PROG_ERROR;
739+ goto outahere;
740+ }
741+ if (chip == TMO) {
742+ rc = ERR_TIMOUT;
743+ goto outahere;
744+ }
745+
746+ printf ("ok.\n");
747+ } else { /* it was protected */
748+
749+ printf ("protected!\n");
750+ }
751+ }
752+
753+ if (ctrlc ())
754+ printf ("User Interrupt!\n");
755+
756+ outahere:
757+ /* allow flash to settle - wait 10 ms */
758+ udelay_masked (10000);
759+
760+ if (iflag)
761+ enable_interrupts ();
762+
763+ if (cflag)
764+ icache_enable ();
765+
766+ return rc;
767+}
768+
769+/*-----------------------------------------------------------------------
770+ * Copy memory to flash
771+ */
772+
773+volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
774+{
775+ vu_short *addr = (vu_short *) dest;
776+ ushort result;
777+ int rc = ERR_OK;
778+ int cflag, iflag;
779+ int chip;
780+
781+ /*
782+ * Check if Flash is (sufficiently) erased
783+ */
784+ result = *addr;
785+ if ((result & data) != data)
786+ return ERR_NOT_ERASED;
787+
788+
789+ /*
790+ * Disable interrupts which might cause a timeout
791+ * here. Remember that our exception vectors are
792+ * at address 0 in the flash, and we don't want a
793+ * (ticker) exception to happen while the flash
794+ * chip is in programming mode.
795+ */
796+ cflag = icache_status ();
797+ icache_disable ();
798+ iflag = disable_interrupts ();
799+
800+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
801+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
802+ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
803+ *addr = CMD_PROGRAM;
804+ *addr = data;
805+
806+ /* arm simple, non interrupt dependent timer */
807+ reset_timer_masked ();
808+
809+ /* wait until flash is ready */
810+ chip = 0;
811+ do {
812+ result = *addr;
813+
814+ /* check timeout */
815+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
816+ chip = ERR | TMO;
817+ break;
818+ }
819+ if (!chip && ((result & 0x80) == (data & 0x80)))
820+ chip = READY;
821+
822+ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
823+ result = *addr;
824+
825+ if ((result & 0x80) == (data & 0x80))
826+ chip = READY;
827+ else
828+ chip = ERR;
829+ }
830+
831+ } while (!chip);
832+
833+ *addr = CMD_READ_ARRAY;
834+
835+ if (chip == ERR || *addr != data)
836+ rc = ERR_PROG_ERROR;
837+
838+ if (iflag)
839+ enable_interrupts ();
840+
841+ if (cflag)
842+ icache_enable ();
843+
844+ return rc;
845+}
846+
847+/*-----------------------------------------------------------------------
848+ * Copy memory to flash.
849+ */
850+
851+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
852+{
853+ ulong cp, wp;
854+ int l;
855+ int i, rc;
856+ ushort data;
857+
858+ wp = (addr & ~1); /* get lower word aligned address */
859+
860+ /*
861+ * handle unaligned start bytes
862+ */
863+ if ((l = addr - wp) != 0) {
864+ data = 0;
865+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
866+ data = (data >> 8) | (*(uchar *) cp << 8);
867+ }
868+ for (; i < 2 && cnt > 0; ++i) {
869+ data = (data >> 8) | (*src++ << 8);
870+ --cnt;
871+ ++cp;
872+ }
873+ for (; cnt == 0 && i < 2; ++i, ++cp) {
874+ data = (data >> 8) | (*(uchar *) cp << 8);
875+ }
876+
877+ if ((rc = write_hword (info, wp, data)) != 0) {
878+ return (rc);
879+ }
880+ wp += 2;
881+ }
882+
883+ /*
884+ * handle word aligned part
885+ */
886+ while (cnt >= 2) {
887+ data = *((vu_short *) src);
888+ if ((rc = write_hword (info, wp, data)) != 0) {
889+ return (rc);
890+ }
891+ src += 2;
892+ wp += 2;
893+ cnt -= 2;
894+ }
895+
896+ if (cnt == 0) {
897+ return ERR_OK;
898+ }
899+
900+ /*
901+ * handle unaligned tail bytes
902+ */
903+ data = 0;
904+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
905+ data = (data >> 8) | (*src++ << 8);
906+ --cnt;
907+ }
908+ for (; i < 2; ++i, ++cp) {
909+ data = (data >> 8) | (*(uchar *) cp << 8);
910+ }
911+
912+ return write_hword (info, wp, data);
913+}
914Index: u-boot/board/smdk2440/lowlevel_init.S
915===================================================================
916--- /dev/null
917+++ u-boot/board/smdk2440/lowlevel_init.S
918@@ -0,0 +1,167 @@
919+/*
920+ * Memory Setup stuff - taken from blob memsetup.S
921+ *
922+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
923+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
924+ *
925+ * Modified for the Samsung SMDK2410 by
926+ * (C) Copyright 2002
927+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
928+ *
929+ * See file CREDITS for list of people who contributed to this
930+ * project.
931+ *
932+ * This program is free software; you can redistribute it and/or
933+ * modify it under the terms of the GNU General Public License as
934+ * published by the Free Software Foundation; either version 2 of
935+ * the License, or (at your option) any later version.
936+ *
937+ * This program is distributed in the hope that it will be useful,
938+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
939+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
940+ * GNU General Public License for more details.
941+ *
942+ * You should have received a copy of the GNU General Public License
943+ * along with this program; if not, write to the Free Software
944+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
945+ * MA 02111-1307 USA
946+ */
947+
948+
949+#include <config.h>
950+#include <version.h>
951+
952+
953+/* some parameters for the board */
954+
955+/*
956+ *
957+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
958+ *
959+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
960+ *
961+ */
962+
963+#define BWSCON 0x48000000
964+
965+/* BWSCON */
966+#define DW8 (0x0)
967+#define DW16 (0x1)
968+#define DW32 (0x2)
969+#define WAIT (0x1<<2)
970+#define UBLB (0x1<<3)
971+
972+#define B1_BWSCON (DW32)
973+#define B2_BWSCON (DW16)
974+#define B3_BWSCON (DW16 + WAIT + UBLB)
975+#define B4_BWSCON (DW16)
976+#define B5_BWSCON (DW16)
977+#define B6_BWSCON (DW32)
978+#define B7_BWSCON (DW32)
979+
980+/* BANK0CON */
981+#define B0_Tacs 0x0 /* 0clk */
982+#define B0_Tcos 0x0 /* 0clk */
983+#define B0_Tacc 0x7 /* 14clk */
984+#define B0_Tcoh 0x0 /* 0clk */
985+#define B0_Tah 0x0 /* 0clk */
986+#define B0_Tacp 0x0
987+#define B0_PMC 0x0 /* normal */
988+
989+/* BANK1CON */
990+#define B1_Tacs 0x0 /* 0clk */
991+#define B1_Tcos 0x0 /* 0clk */
992+#define B1_Tacc 0x7 /* 14clk */
993+#define B1_Tcoh 0x0 /* 0clk */
994+#define B1_Tah 0x0 /* 0clk */
995+#define B1_Tacp 0x0
996+#define B1_PMC 0x0
997+
998+#define B2_Tacs 0x0
999+#define B2_Tcos 0x0
1000+#define B2_Tacc 0x7
1001+#define B2_Tcoh 0x0
1002+#define B2_Tah 0x0
1003+#define B2_Tacp 0x0
1004+#define B2_PMC 0x0
1005+
1006+#define B3_Tacs 0x0 /* 0clk */
1007+#define B3_Tcos 0x3 /* 4clk */
1008+#define B3_Tacc 0x7 /* 14clk */
1009+#define B3_Tcoh 0x1 /* 1clk */
1010+#define B3_Tah 0x0 /* 0clk */
1011+#define B3_Tacp 0x3 /* 6clk */
1012+#define B3_PMC 0x0 /* normal */
1013+
1014+#define B4_Tacs 0x0 /* 0clk */
1015+#define B4_Tcos 0x0 /* 0clk */
1016+#define B4_Tacc 0x7 /* 14clk */
1017+#define B4_Tcoh 0x0 /* 0clk */
1018+#define B4_Tah 0x0 /* 0clk */
1019+#define B4_Tacp 0x0
1020+#define B4_PMC 0x0 /* normal */
1021+
1022+#define B5_Tacs 0x0 /* 0clk */
1023+#define B5_Tcos 0x0 /* 0clk */
1024+#define B5_Tacc 0x7 /* 14clk */
1025+#define B5_Tcoh 0x0 /* 0clk */
1026+#define B5_Tah 0x0 /* 0clk */
1027+#define B5_Tacp 0x0
1028+#define B5_PMC 0x0 /* normal */
1029+
1030+#define B6_MT 0x3 /* SDRAM */
1031+#define B6_Trcd 0x1
1032+#define B6_SCAN 0x1 /* 9bit */
1033+
1034+#define B7_MT 0x3 /* SDRAM */
1035+#define B7_Trcd 0x1 /* 3clk */
1036+#define B7_SCAN 0x1 /* 9bit */
1037+
1038+/* REFRESH parameter */
1039+#define REFEN 0x1 /* Refresh enable */
1040+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
1041+#define Trp 0x0 /* 2clk */
1042+#define Trc 0x3 /* 7clk */
1043+#define Tchr 0x2 /* 3clk */
1044+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
1045+/**************************************/
1046+
1047+_TEXT_BASE:
1048+ .word TEXT_BASE
1049+
1050+.globl lowlevel_init
1051+lowlevel_init:
1052+ /* memory control configuration */
1053+ /* make r0 relative the current location so that it */
1054+ /* reads SMRDATA out of FLASH rather than memory ! */
1055+ ldr r0, =SMRDATA
1056+ ldr r1, _TEXT_BASE
1057+ sub r0, r0, r1
1058+ ldr r1, =BWSCON /* Bus Width Status Controller */
1059+ add r2, r0, #13*4
1060+0:
1061+ ldr r3, [r0], #4
1062+ str r3, [r1], #4
1063+ cmp r2, r0
1064+ bne 0b
1065+
1066+ /* everything is fine now */
1067+ mov pc, lr
1068+
1069+ .ltorg
1070+/* the literal pools origin */
1071+
1072+SMRDATA:
1073+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
1074+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
1075+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
1076+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
1077+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
1078+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
1079+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
1080+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
1081+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
1082+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
1083+ .word 0x32
1084+ .word 0x30
1085+ .word 0x30
1086Index: u-boot/board/smdk2440/smdk2440.c
1087===================================================================
1088--- /dev/null
1089+++ u-boot/board/smdk2440/smdk2440.c
1090@@ -0,0 +1,152 @@
1091+/*
1092+ * (C) Copyright 2002
1093+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
1094+ * Marius Groeger <mgroeger@sysgo.de>
1095+ *
1096+ * (C) Copyright 2002
1097+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
1098+ *
1099+ * See file CREDITS for list of people who contributed to this
1100+ * project.
1101+ *
1102+ * This program is free software; you can redistribute it and/or
1103+ * modify it under the terms of the GNU General Public License as
1104+ * published by the Free Software Foundation; either version 2 of
1105+ * the License, or (at your option) any later version.
1106+ *
1107+ * This program is distributed in the hope that it will be useful,
1108+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1109+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1110+ * GNU General Public License for more details.
1111+ *
1112+ * You should have received a copy of the GNU General Public License
1113+ * along with this program; if not, write to the Free Software
1114+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1115+ * MA 02111-1307 USA
1116+ */
1117+
1118+#include <common.h>
1119+#include <s3c2440.h>
1120+
1121+DECLARE_GLOBAL_DATA_PTR;
1122+
1123+#define FCLK_SPEED 1
1124+
1125+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
1126+#define M_MDIV 0xC3
1127+#define M_PDIV 0x4
1128+#define M_SDIV 0x1
1129+#elif FCLK_SPEED==1 /* Fout = 399.65MHz */
1130+#define M_MDIV 0x6e
1131+#define M_PDIV 0x3
1132+#define M_SDIV 0x1
1133+#endif
1134+
1135+#define USB_CLOCK 1
1136+
1137+#if USB_CLOCK==0
1138+#define U_M_MDIV 0xA1
1139+#define U_M_PDIV 0x3
1140+#define U_M_SDIV 0x1
1141+#elif USB_CLOCK==1
1142+#define U_M_MDIV 0x3c
1143+#define U_M_PDIV 0x4
1144+#define U_M_SDIV 0x2
1145+#endif
1146+
1147+static inline void delay (unsigned long loops)
1148+{
1149+ __asm__ volatile ("1:\n"
1150+ "subs %0, %1, #1\n"
1151+ "bne 1b":"=r" (loops):"0" (loops));
1152+}
1153+
1154+/*
1155+ * Miscellaneous platform dependent initialisations
1156+ */
1157+
1158+int board_init (void)
1159+{
1160+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1161+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1162+
1163+ /* to reduce PLL lock time, adjust the LOCKTIME register */
1164+ clk_power->LOCKTIME = 0xFFFFFF;
1165+
1166+ /* configure MPLL */
1167+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
1168+
1169+ /* some delay between MPLL and UPLL */
1170+ delay (4000);
1171+
1172+ /* configure UPLL */
1173+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
1174+
1175+ /* some delay between MPLL and UPLL */
1176+ delay (8000);
1177+
1178+ /* set up the I/O ports */
1179+ gpio->GPACON = 0x007FFFFF;
1180+ gpio->GPBCON = 0x002a9655;
1181+ gpio->GPBUP = 0x000007FF;
1182+ gpio->GPCCON = 0xAAAAAAAA;
1183+ gpio->GPCUP = 0x0000FFFF;
1184+ gpio->GPDCON = 0xAAAAAAAA;
1185+ gpio->GPDUP = 0x0000FFFF;
1186+ gpio->GPECON = 0xAAAAAAAA;
1187+ gpio->GPEUP = 0x0000FFFF;
1188+ gpio->GPFCON = 0x000055AA;
1189+ gpio->GPFUP = 0x000000FF;
1190+ gpio->GPGCON = 0xFD95FFBA;
1191+ gpio->GPGUP = 0x0000FFFF;
1192+#ifdef CONFIG_SERIAL3
1193+ gpio->GPHCON = 0x002AAAAA;
1194+#else
1195+ gpio->GPHCON = 0x002AFAAA;
1196+#endif
1197+ gpio->GPHUP = 0x000007FF;
1198+
1199+ gpio->GPJCON = 0x2AAAAAA;
1200+
1201+#if 0
1202+ /* USB Device Part */
1203+ /*GPGCON is reset for USB Device */
1204+ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
1205+ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
1206+
1207+ gpio->GPGDAT |= ( 1 << 12) ;
1208+ gpio->GPGDAT &= ~( 1 << 12) ;
1209+ udelay(20000);
1210+ gpio->GPGDAT |= ( 1 << 12) ;
1211+#endif
1212+
1213+ /* arch number of SMDK2440-Board */
1214+ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
1215+
1216+ /* adress of boot parameters */
1217+ gd->bd->bi_boot_params = 0x30000100;
1218+
1219+ icache_enable();
1220+ dcache_enable();
1221+
1222+ return 0;
1223+}
1224+
1225+int dram_init (void)
1226+{
1227+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
1228+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
1229+
1230+ return 0;
1231+}
1232+
1233+/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
1234+ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
1235+ images: 640*480*2*2 = 1228800 < 1245184. */
1236+
1237+unsigned int dynpart_size[] = {
1238+ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 };
1239+char *dynpart_names[] = {
1240+ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
1241+
1242+
1243Index: u-boot/board/smdk2440/u-boot.lds
1244===================================================================
1245--- /dev/null
1246+++ u-boot/board/smdk2440/u-boot.lds
1247@@ -0,0 +1,58 @@
1248+/*
1249+ * (C) Copyright 2002
1250+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1251+ *
1252+ * See file CREDITS for list of people who contributed to this
1253+ * project.
1254+ *
1255+ * This program is free software; you can redistribute it and/or
1256+ * modify it under the terms of the GNU General Public License as
1257+ * published by the Free Software Foundation; either version 2 of
1258+ * the License, or (at your option) any later version.
1259+ *
1260+ * This program is distributed in the hope that it will be useful,
1261+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1262+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1263+ * GNU General Public License for more details.
1264+ *
1265+ * You should have received a copy of the GNU General Public License
1266+ * along with this program; if not, write to the Free Software
1267+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1268+ * MA 02111-1307 USA
1269+ */
1270+
1271+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1272+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
1273+OUTPUT_ARCH(arm)
1274+ENTRY(_start)
1275+SECTIONS
1276+{
1277+ . = 0x00000000;
1278+
1279+ . = ALIGN(4);
1280+ .text :
1281+ {
1282+ cpu/arm920t/start.o (.text)
1283+ cpu/arm920t/s3c24x0/nand_read.o (.text)
1284+ *(.text)
1285+ }
1286+
1287+ . = ALIGN(4);
1288+ .rodata : { *(.rodata) }
1289+
1290+ . = ALIGN(4);
1291+ .data : { *(.data) }
1292+
1293+ . = ALIGN(4);
1294+ .got : { *(.got) }
1295+
1296+ . = .;
1297+ __u_boot_cmd_start = .;
1298+ .u_boot_cmd : { *(.u_boot_cmd) }
1299+ __u_boot_cmd_end = .;
1300+
1301+ . = ALIGN(4);
1302+ __bss_start = .;
1303+ .bss : { *(.bss) }
1304+ _end = .;
1305+}
1306Index: u-boot/board/smdk2440/udc.c
1307===================================================================
1308--- /dev/null
1309+++ u-boot/board/smdk2440/udc.c
1310@@ -0,0 +1,23 @@
1311+
1312+#include <common.h>
1313+#include <usbdcore.h>
1314+#include <s3c2440.h>
1315+
1316+void udc_ctrl(enum usbd_event event, int param)
1317+{
1318+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1319+
1320+ switch (event) {
1321+ case UDC_CTRL_PULLUP_ENABLE:
1322+ if (param)
1323+ gpio->GPGDAT |= (1 << 12);
1324+ else
1325+ gpio->GPGDAT &= ~(1 << 12);
1326+ break;
1327+ case UDC_CTRL_500mA_ENABLE:
1328+ /* IGNORE */
1329+ break;
1330+ default:
1331+ break;
1332+ }
1333+}
1334Index: u-boot/board/smdk2440/lowlevel_foo.S
1335===================================================================
1336--- /dev/null
1337+++ u-boot/board/smdk2440/lowlevel_foo.S
1338@@ -0,0 +1,82 @@
1339+
1340+_start:
1341+ b reset
1342+undefvec:
1343+ b undefvec
1344+swivec:
1345+ b swivec
1346+pabtvec:
1347+ b pabtvec
1348+dabtvec:
1349+ b dabtvec
1350+rsvdvec:
1351+ b rsvdvec
1352+irqvec:
1353+ b irqvec
1354+fiqvec:
1355+ b fiqvec
1356+
1357+reset:
1358+ /*
1359+ * set the cpu to SVC32 mode
1360+ */
1361+ mrs r0,cpsr
1362+ bic r0,r0,#0x1f
1363+ orr r0,r0,#0xd3
1364+ msr cpsr,r0
1365+
1366+/* turn off the watchdog */
1367+#define pWTCON 0x53000000
1368+#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
1369+#define INTSUBMSK 0x4A00001C
1370+#define CLKDIVN 0x4C000014 /* clock divisor register */
1371+
1372+ ldr r0, =pWTCON
1373+ mov r1, #0x0
1374+ str r1, [r0]
1375+
1376+ mov r1, #0xffffffff
1377+ ldr r0, =INTMSK
1378+ str r1, [r0]
1379+ ldr r1, =0x3ff
1380+ ldr r0, =INTSUBMSK
1381+ str r1, [r0]
1382+
1383+ /* FCLK:HCLK:PCLK = 1:2:4 */
1384+ /* default FCLK is 120 MHz ! */
1385+ ldr r0, =CLKDIVN
1386+ mov r1, #3
1387+ str r1, [r0]
1388+
1389+ bl cpu_init_crit
1390+ ldr r0,=TEXT_BASE
1391+ mov pc, r0
1392+
1393+cpu_init_crit:
1394+ /*
1395+ * flush v4 I/D caches
1396+ */
1397+ mov r0, #0
1398+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
1399+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
1400+
1401+ /*
1402+ * disable MMU stuff and caches
1403+ */
1404+ mrc p15, 0, r0, c1, c0, 0
1405+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
1406+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
1407+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
1408+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
1409+ mcr p15, 0, r0, c1, c0, 0
1410+
1411+ /*
1412+ * before relocating, we have to setup RAM timing
1413+ * because memory timing is board-dependend, you will
1414+ * find a lowlevel_init.S in your board directory.
1415+ */
1416+ mov ip, lr
1417+ bl lowlevel_init
1418+ mov lr, ip
1419+ mov pc, lr
1420+
1421Index: u-boot/board/smdk2440/lowlevel_foo.lds
1422===================================================================
1423--- /dev/null
1424+++ u-boot/board/smdk2440/lowlevel_foo.lds
1425@@ -0,0 +1,56 @@
1426+/*
1427+ * (C) Copyright 2002
1428+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1429+ *
1430+ * See file CREDITS for list of people who contributed to this
1431+ * project.
1432+ *
1433+ * This program is free software; you can redistribute it and/or
1434+ * modify it under the terms of the GNU General Public License as
1435+ * published by the Free Software Foundation; either version 2 of
1436+ * the License, or (at your option) any later version.
1437+ *
1438+ * This program is distributed in the hope that it will be useful,
1439+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1440+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1441+ * GNU General Public License for more details.
1442+ *
1443+ * You should have received a copy of the GNU General Public License
1444+ * along with this program; if not, write to the Free Software
1445+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1446+ * MA 02111-1307 USA
1447+ */
1448+
1449+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1450+OUTPUT_ARCH(arm)
1451+ENTRY(_start)
1452+SECTIONS
1453+{
1454+ . = 0x00000000;
1455+
1456+ . = ALIGN(4);
1457+ .text :
1458+ {
1459+ lowlevel_foo.o (.text)
1460+ *(.text)
1461+ }
1462+
1463+ . = ALIGN(4);
1464+ .rodata : { *(.rodata) }
1465+
1466+ . = ALIGN(4);
1467+ .data : { *(.data) }
1468+
1469+ . = ALIGN(4);
1470+ .got : { *(.got) }
1471+
1472+ . = .;
1473+ __u_boot_cmd_start = .;
1474+ .u_boot_cmd : { *(.u_boot_cmd) }
1475+ __u_boot_cmd_end = .;
1476+
1477+ . = ALIGN(4);
1478+ __bss_start = .;
1479+ .bss : { *(.bss) }
1480+ _end = .;
1481+}
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-12 08:00:04 +0000