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-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch1301
1 files changed, 1301 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch
new file mode 100644
index 0000000000..da0fb8cf2d
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch
@@ -0,0 +1,1301 @@
1Add proper support for S3C2440 CPU's
2
3Index: u-boot/include/s3c24x0.h
4===================================================================
5--- u-boot.orig/include/s3c24x0.h
6+++ u-boot/include/s3c24x0.h
7@@ -82,7 +82,7 @@
8 S3C24X0_REG32 PRIORITY;
9 S3C24X0_REG32 INTPND;
10 S3C24X0_REG32 INTOFFSET;
11-#ifdef CONFIG_S3C2410
12+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
13 S3C24X0_REG32 SUBSRCPND;
14 S3C24X0_REG32 INTSUBMSK;
15 #endif
16@@ -92,11 +92,11 @@
17 /* DMAS (see manual chapter 8) */
18 typedef struct {
19 S3C24X0_REG32 DISRC;
20-#ifdef CONFIG_S3C2410
21+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
22 S3C24X0_REG32 DISRCC;
23 #endif
24 S3C24X0_REG32 DIDST;
25-#ifdef CONFIG_S3C2410
26+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
27 S3C24X0_REG32 DIDSTC;
28 #endif
29 S3C24X0_REG32 DCON;
30@@ -107,7 +107,7 @@
31 #ifdef CONFIG_S3C2400
32 S3C24X0_REG32 res[1];
33 #endif
34-#ifdef CONFIG_S3C2410
35+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
36 S3C24X0_REG32 res[7];
37 #endif
38 } /*__attribute__((__packed__))*/ S3C24X0_DMA;
39@@ -126,6 +126,9 @@
40 S3C24X0_REG32 CLKCON;
41 S3C24X0_REG32 CLKSLOW;
42 S3C24X0_REG32 CLKDIVN;
43+#ifdef CONFIG_S3C2440
44+ S3C24X0_REG32 CAMDIVN;
45+#endif
46 } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
47
48
49@@ -145,7 +148,7 @@
50 S3C24X0_REG32 res[8];
51 S3C24X0_REG32 DITHMODE;
52 S3C24X0_REG32 TPAL;
53-#ifdef CONFIG_S3C2410
54+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
55 S3C24X0_REG32 LCDINTPND;
56 S3C24X0_REG32 LCDSRCPND;
57 S3C24X0_REG32 LCDINTMSK;
58@@ -157,6 +160,9 @@
59 /* NAND FLASH (see S3C2410 manual chapter 6) */
60 typedef struct {
61 S3C24X0_REG32 NFCONF;
62+#ifdef CONFIG_S3C2440
63+ S3C24X0_REG32 NFCONT;
64+#endif
65 S3C24X0_REG32 NFCMD;
66 S3C24X0_REG32 NFADDR;
67 S3C24X0_REG32 NFDATA;
68@@ -164,6 +170,15 @@
69 S3C24X0_REG32 NFECC;
70 } /*__attribute__((__packed__))*/ S3C2410_NAND;
71
72+/* NAND FLASH (see S3C2440 manual chapter 6) */
73+typedef struct {
74+ S3C24X0_REG32 NFCONF;
75+ S3C24X0_REG32 NFCMD;
76+ S3C24X0_REG32 NFADDR;
77+ S3C24X0_REG32 NFDATA;
78+ S3C24X0_REG32 NFSTAT;
79+ S3C24X0_REG32 NFECC;
80+} /*__attribute__((__packed__))*/ S3C2440_NAND;
81
82 /* UART (see manual chapter 11) */
83 typedef struct {
84@@ -451,6 +466,65 @@
85 S3C24X0_REG32 GSTATUS3;
86 S3C24X0_REG32 GSTATUS4;
87 #endif
88+#ifdef CONFIG_S3C2440
89+ S3C24X0_REG32 GPACON;
90+ S3C24X0_REG32 GPADAT;
91+ S3C24X0_REG32 res1[2];
92+ S3C24X0_REG32 GPBCON;
93+ S3C24X0_REG32 GPBDAT;
94+ S3C24X0_REG32 GPBUP;
95+ S3C24X0_REG32 res2;
96+ S3C24X0_REG32 GPCCON;
97+ S3C24X0_REG32 GPCDAT;
98+ S3C24X0_REG32 GPCUP;
99+ S3C24X0_REG32 res3;
100+ S3C24X0_REG32 GPDCON;
101+ S3C24X0_REG32 GPDDAT;
102+ S3C24X0_REG32 GPDUP;
103+ S3C24X0_REG32 res4;
104+ S3C24X0_REG32 GPECON;
105+ S3C24X0_REG32 GPEDAT;
106+ S3C24X0_REG32 GPEUP;
107+ S3C24X0_REG32 res5;
108+ S3C24X0_REG32 GPFCON;
109+ S3C24X0_REG32 GPFDAT;
110+ S3C24X0_REG32 GPFUP;
111+ S3C24X0_REG32 res6;
112+ S3C24X0_REG32 GPGCON;
113+ S3C24X0_REG32 GPGDAT;
114+ S3C24X0_REG32 GPGUP;
115+ S3C24X0_REG32 res7;
116+ S3C24X0_REG32 GPHCON;
117+ S3C24X0_REG32 GPHDAT;
118+ S3C24X0_REG32 GPHUP;
119+ S3C24X0_REG32 res8;
120+
121+ S3C24X0_REG32 MISCCR;
122+ S3C24X0_REG32 DCLKCON;
123+ S3C24X0_REG32 EXTINT0;
124+ S3C24X0_REG32 EXTINT1;
125+ S3C24X0_REG32 EXTINT2;
126+ S3C24X0_REG32 EINTFLT0;
127+ S3C24X0_REG32 EINTFLT1;
128+ S3C24X0_REG32 EINTFLT2;
129+ S3C24X0_REG32 EINTFLT3;
130+ S3C24X0_REG32 EINTMASK;
131+ S3C24X0_REG32 EINTPEND;
132+ S3C24X0_REG32 GSTATUS0;
133+ S3C24X0_REG32 GSTATUS1;
134+ S3C24X0_REG32 GSTATUS2;
135+ S3C24X0_REG32 GSTATUS3;
136+ S3C24X0_REG32 GSTATUS4;
137+
138+ S3C24X0_REG32 res9;
139+ S3C24X0_REG32 DSC0;
140+ S3C24X0_REG32 DSC1;
141+ S3C24X0_REG32 MSLCON;
142+ S3C24X0_REG32 GPJCON;
143+ S3C24X0_REG32 GPJDAT;
144+ S3C24X0_REG32 GPJUP;
145+ S3C24X0_REG32 res10;
146+#endif
147 } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
148
149
150@@ -637,8 +711,13 @@
151 S3C24X0_REG32 SDIDCNT;
152 S3C24X0_REG32 SDIDSTA;
153 S3C24X0_REG32 SDIFSTA;
154+#if defined(CONFIG_S3C2410)
155 S3C24X0_REG32 SDIDAT;
156 S3C24X0_REG32 SDIIMSK;
157+#elif defined(CONFIG_S3C2440)
158+ S3C24X0_REG32 SDIIMSK;
159+ S3C24X0_REG32 SDIDAT;
160+#endif
161 } /*__attribute__((__packed__))*/ S3C2410_SDI;
162
163
164Index: u-boot/rtc/s3c24x0_rtc.c
165===================================================================
166--- u-boot.orig/rtc/s3c24x0_rtc.c
167+++ u-boot/rtc/s3c24x0_rtc.c
168@@ -34,6 +34,8 @@
169 #include <s3c2400.h>
170 #elif defined(CONFIG_S3C2410)
171 #include <s3c2410.h>
172+#elif defined(CONFIG_S3C2440)
173+#include <s3c2440.h>
174 #endif
175
176 #include <rtc.h>
177Index: u-boot/include/s3c2440.h
178===================================================================
179--- /dev/null
180+++ u-boot/include/s3c2440.h
181@@ -0,0 +1,300 @@
182+/*
183+ * (C) Copyright 2003
184+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
185+ *
186+ * See file CREDITS for list of people who contributed to this
187+ * project.
188+ *
189+ * This program is free software; you can redistribute it and/or
190+ * modify it under the terms of the GNU General Public License as
191+ * published by the Free Software Foundation; either version 2 of
192+ * the License, or (at your option) any later version.
193+ *
194+ * This program is distributed in the hope that it will be useful,
195+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
196+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197+ * GNU General Public License for more details.
198+ *
199+ * You should have received a copy of the GNU General Public License
200+ * along with this program; if not, write to the Free Software
201+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
202+ * MA 02111-1307 USA
203+ */
204+
205+/************************************************
206+ * NAME : s3c2440.h
207+ * Version : 2007.
208+ *
209+ * Based on S3C2410X User's manual Rev 1.1
210+ ************************************************/
211+
212+#ifndef __S3C2440_H__
213+#define __S3C2440_H__
214+
215+#define S3C24X0_UART_CHANNELS 3
216+#define S3C24X0_SPI_CHANNELS 2
217+
218+/* S3C2440 only supports 512 Byte HW ECC */
219+#define S3C2440_ECCSIZE 512
220+#define S3C2440_ECCBYTES 3
221+
222+/* S3C2440 device base addresses */
223+#define S3C24X0_MEMCTL_BASE 0x48000000
224+#define S3C24X0_USB_HOST_BASE 0x49000000
225+#define S3C24X0_INTERRUPT_BASE 0x4A000000
226+#define S3C24X0_DMA_BASE 0x4B000000
227+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
228+#define S3C24X0_LCD_BASE 0x4D000000
229+#define S3C2440_NAND_BASE 0x4E000000
230+#define S3C24X0_UART_BASE 0x50000000
231+#define S3C24X0_TIMER_BASE 0x51000000
232+#define S3C24X0_USB_DEVICE_BASE 0x52000140
233+#define USB_DEVICE_PHYS_ADR 0x52000000
234+#define S3C24X0_WATCHDOG_BASE 0x53000000
235+#define S3C24X0_I2C_BASE 0x54000000
236+#define S3C24X0_I2S_BASE 0x55000000
237+#define S3C24X0_GPIO_BASE 0x56000000
238+#define S3C24X0_RTC_BASE 0x57000000
239+#define S3C2440_ADC_BASE 0x58000000
240+#define S3C24X0_SPI_BASE 0x59000000
241+#define S3C2440_SDI_BASE 0x5A000000
242+
243+#define oNFCONF 0x00
244+#define oNFCONT 0x04
245+
246+#ifndef __ASSEMBLER__
247+
248+/* include common stuff */
249+#include <s3c24x0.h>
250+
251+typedef enum {
252+ S3C24X0_UART0,
253+ S3C24X0_UART1,
254+ S3C24X0_UART2
255+} S3C24X0_UARTS_NR;
256+
257+static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
258+{
259+ return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
260+}
261+static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
262+{
263+ return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
264+}
265+static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
266+{
267+ return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
268+}
269+static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
270+{
271+ return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
272+}
273+static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
274+{
275+ return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
276+}
277+static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
278+{
279+ return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
280+}
281+static inline S3C2440_NAND * S3C2440_GetBase_NAND(void)
282+{
283+ return (S3C2440_NAND * const)S3C2440_NAND_BASE;
284+}
285+static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
286+{
287+ return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
288+}
289+static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
290+{
291+ return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
292+}
293+static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
294+{
295+ return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
296+}
297+static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
298+{
299+ return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
300+}
301+static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
302+{
303+ return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
304+}
305+static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
306+{
307+ return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
308+}
309+static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
310+{
311+ return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
312+}
313+static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
314+{
315+ return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
316+}
317+/*
318+static inline S3C2440_ADC * S3C2440_GetBase_ADC(void)
319+{
320+ return (S3C2440_ADC * const)S3C2440_ADC_BASE;
321+}
322+static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
323+{
324+ return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
325+}
326+*/
327+static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
328+{
329+ return (S3C2410_SDI * const)S3C2440_SDI_BASE;
330+}
331+
332+#endif /* __ASSEMBLER__ */
333+
334+/* ISR */
335+#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
336+#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
337+#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
338+#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
339+#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
340+#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
341+#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
342+#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
343+
344+#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
345+#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
346+#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
347+#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
348+#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
349+#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
350+#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
351+#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
352+#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
353+#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
354+#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
355+#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
356+#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
357+#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
358+#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
359+#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
360+#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
361+#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
362+#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
363+#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
364+#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
365+#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
366+#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
367+#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
368+#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
369+#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
370+#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
371+#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
372+#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
373+#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
374+
375+
376+/* PENDING BIT */
377+#define BIT_EINT0 (0x1)
378+#define BIT_EINT1 (0x1<<1)
379+#define BIT_EINT2 (0x1<<2)
380+#define BIT_EINT3 (0x1<<3)
381+#define BIT_EINT4_7 (0x1<<4)
382+#define BIT_EINT8_23 (0x1<<5)
383+#define BIT_BAT_FLT (0x1<<7)
384+#define BIT_TICK (0x1<<8)
385+#define BIT_WDT (0x1<<9)
386+#define BIT_TIMER0 (0x1<<10)
387+#define BIT_TIMER1 (0x1<<11)
388+#define BIT_TIMER2 (0x1<<12)
389+#define BIT_TIMER3 (0x1<<13)
390+#define BIT_TIMER4 (0x1<<14)
391+#define BIT_UART2 (0x1<<15)
392+#define BIT_LCD (0x1<<16)
393+#define BIT_DMA0 (0x1<<17)
394+#define BIT_DMA1 (0x1<<18)
395+#define BIT_DMA2 (0x1<<19)
396+#define BIT_DMA3 (0x1<<20)
397+#define BIT_SDI (0x1<<21)
398+#define BIT_SPI0 (0x1<<22)
399+#define BIT_UART1 (0x1<<23)
400+#define BIT_USBD (0x1<<25)
401+#define BIT_USBH (0x1<<26)
402+#define BIT_IIC (0x1<<27)
403+#define BIT_UART0 (0x1<<28)
404+#define BIT_SPI1 (0x1<<29)
405+#define BIT_RTC (0x1<<30)
406+#define BIT_ADC (0x1<<31)
407+#define BIT_ALLMSK (0xFFFFFFFF)
408+
409+#define ClearPending(bit) {\
410+ rSRCPND = bit;\
411+ rINTPND = bit;\
412+ rINTPND;\
413+ }
414+/* Wait until rINTPND is changed for the case that the ISR is very short. */
415+
416+#define __REG(x) (*(volatile unsigned long *)(x))
417+#define __REGl(x) (*(volatile unsigned long *)(x))
418+#define __REGw(x) (*(volatile unsigned short *)(x))
419+#define __REGb(x) (*(volatile unsigned char *)(x))
420+#define __REG2(x,y) (*(volatile unsigned long *)((x) + (y)))
421+
422+/*
423+ * * Nand flash controller
424+ * */
425+
426+#define NFDATA8 (*(volatile unsigned char *)0x4E000010)
427+#define NFDATA16 (*(volatile unsigned short *)0x4E000010)
428+#define NFDATA32 (*(volatile unsigned *)0x4E000010)
429+
430+#define NFCONF __REG(0x4E000000)
431+#define NFCONT __REG(0x4E000004)
432+#define NFCMD __REG(0x4E000008)
433+#define NFADDR __REGb(0x4E00000C)
434+#define NFMECCD0 __REG(0x4E000014)
435+#define NFMECCD1 __REG(0x4E000018)
436+#define NFSECCD __REG(0x4E00001C)
437+#define NFSTAT __REG(0x4E000020)
438+#define NFESTAT0 __REG(0x4E000024)
439+#define NFESTAT1 __REG(0x4E000028)
440+#define NFMECC0 __REG(0x4E00002C)
441+#define NFMECC1 __REG(0x4E000030)
442+#define NFSECC __REG(0x4E000034)
443+#define NFSBLK __REG(0x4E000038)
444+
445+
446+#define S3C2410_MISCCR_USBDEV (0<<3)
447+#define S3C2410_MISCCR_USBHOST (1<<3)
448+
449+#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
450+#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
451+#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
452+#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
453+#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
454+#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
455+#define S3C2410_MISCCR_CLK0_MASK (7<<4)
456+
457+#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
458+#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
459+#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
460+#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
461+#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
462+#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
463+#define S3C2410_MISCCR_CLK1_MASK (7<<8)
464+
465+#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
466+#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
467+
468+#define S3C2410_MISCCR_nRSTCON (1<<16)
469+
470+#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
471+#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
472+#define S3C2410_MISCCR_nEN_SCLKE (1<<19)
473+#define S3C2410_MISCCR_SDSLEEP (7<<17)
474+
475+#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
476+#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
477+#define S3C2410_CLKSLOW_SLOW (1<<4)
478+#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
479+#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
480+
481+#endif /*__S3C2440_H__*/
482Index: u-boot/include/common.h
483===================================================================
484--- u-boot.orig/include/common.h
485+++ u-boot/include/common.h
486@@ -454,7 +454,7 @@
487 ulong get_OPB_freq (void);
488 ulong get_PCI_freq (void);
489 #endif
490-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
491+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_LH7A40X)
492 void s3c2410_irq(void);
493 #define ARM920_IRQ_CALLBACK s3c2410_irq
494 ulong get_FCLK (void);
495Index: u-boot/cpu/arm920t/s3c24x0/usb_ohci.c
496===================================================================
497--- u-boot.orig/cpu/arm920t/s3c24x0/usb_ohci.c
498+++ u-boot/cpu/arm920t/s3c24x0/usb_ohci.c
499@@ -44,6 +44,8 @@
500 #include <s3c2400.h>
501 #elif defined(CONFIG_S3C2410)
502 #include <s3c2410.h>
503+#elif defined(CONFIG_S3C2440)
504+#include <s3c2440.h>
505 #endif
506
507 #include <malloc.h>
508Index: u-boot/cpu/arm920t/s3c24x0/speed.c
509===================================================================
510--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c
511+++ u-boot/cpu/arm920t/s3c24x0/speed.c
512@@ -30,12 +30,15 @@
513 */
514
515 #include <common.h>
516-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
517+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
518+ defined (CONFIG_S3C2440) || defined (CONFIG_TRAB)
519
520 #if defined(CONFIG_S3C2400)
521 #include <s3c2400.h>
522 #elif defined(CONFIG_S3C2410)
523 #include <s3c2410.h>
524+#elif defined(CONFIG_S3C2440)
525+#include <s3c2440.h>
526 #endif
527
528 #define MPLL 0
529@@ -66,8 +69,12 @@
530 m = ((r & 0xFF000) >> 12) + 8;
531 p = ((r & 0x003F0) >> 4) + 2;
532 s = r & 0x3;
533-
534+#ifndef CONFIG_S3C2440
535 return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
536+#else
537+ /* To avoid integer overflow, changed the calc order */
538+ return( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) );
539+#endif
540 }
541
542 /* return FCLK frequency */
543@@ -81,7 +88,21 @@
544 {
545 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
546
547+#ifndef CONFIG_S3C2440
548 return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
549+#else
550+ switch (clk_power->CLKDIVN & 0x6) {
551+ case 0x0:
552+ return get_FCLK();
553+ case 0x2:
554+ return get_FCLK()/2;
555+ case 0x4:
556+ return (clk_power->CAMDIVN & 0x200) ? get_FCLK()/8 : get_FCLK()/4;
557+ case 0x6:
558+ return (clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3;
559+ }
560+ return 0;
561+#endif
562 }
563
564 /* return PCLK frequency */
565@@ -98,4 +119,5 @@
566 return(get_PLLCLK(UPLL));
567 }
568
569-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
570+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
571+ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
572Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
573===================================================================
574--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
575+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
576@@ -30,13 +30,16 @@
577 */
578
579 #include <common.h>
580-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
581+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
582+ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
583
584 #include <arm920t.h>
585 #if defined(CONFIG_S3C2400)
586 #include <s3c2400.h>
587 #elif defined(CONFIG_S3C2410)
588 #include <s3c2410.h>
589+#elif defined(CONFIG_S3C2440)
590+#include <s3c2440.h>
591 #endif
592
593 int timer_load_val = 0;
594@@ -59,6 +62,7 @@
595 /* use PWM Timer 4 because it has no output */
596 /* prescaler for Timer 4 is 16 */
597 timers->TCFG0 = 0x0f00;
598+#ifndef CONFIG_S3C2440
599 if (timer_load_val == 0)
600 {
601 /*
602@@ -68,6 +72,9 @@
603 */
604 timer_load_val = get_PCLK()/(2 * 16 * 100);
605 }
606+#else
607+ timer_load_val = get_PCLK()/(2 * 16 * 100);
608+#endif
609 /* load value for 10 ms timeout */
610 lastdec = timers->TCNTB4 = timer_load_val;
611 /* auto load, manual update of Timer 4 */
612@@ -178,6 +185,7 @@
613 tbclk = timer_load_val * 100;
614 #elif defined(CONFIG_SBC2410X) || \
615 defined(CONFIG_SMDK2410) || \
616+ defined(CONFIG_SMDK2440) || \
617 defined(CONFIG_VCMA9)
618 tbclk = CFG_HZ;
619 #else
620@@ -232,4 +240,5 @@
621 }
622 #endif /* USE_IRQ */
623
624-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
625+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
626+ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
627Index: u-boot/cpu/arm920t/s3c24x0/serial.c
628===================================================================
629--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c
630+++ u-boot/cpu/arm920t/s3c24x0/serial.c
631@@ -19,12 +19,15 @@
632 */
633
634 #include <common.h>
635-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
636+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
637+ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
638
639 #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
640 #include <s3c2400.h>
641 #elif defined(CONFIG_S3C2410)
642 #include <s3c2410.h>
643+#elif defined(CONFIG_S3C2440)
644+#include <s3c2440.h>
645 #endif
646
647 DECLARE_GLOBAL_DATA_PTR;
648@@ -180,4 +183,5 @@
649 }
650 }
651
652-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
653+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) ||
654+ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */
655Index: u-boot/cpu/arm920t/s3c24x0/i2c.c
656===================================================================
657--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c
658+++ u-boot/cpu/arm920t/s3c24x0/i2c.c
659@@ -34,6 +34,8 @@
660 #include <s3c2400.h>
661 #elif defined(CONFIG_S3C2410)
662 #include <s3c2410.h>
663+#elif defined(CONFIG_S3C2440)
664+#include <s3c2440.h>
665 #endif
666 #include <i2c.h>
667
668@@ -63,7 +65,7 @@
669 {
670 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
671
672-#ifdef CONFIG_S3C2410
673+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
674 return (gpio->GPEDAT & 0x8000) >> 15;
675 #endif
676 #ifdef CONFIG_S3C2400
677@@ -82,7 +84,7 @@
678 {
679 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
680
681-#ifdef CONFIG_S3C2410
682+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
683 gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
684 #endif
685 #ifdef CONFIG_S3C2400
686@@ -139,7 +141,7 @@
687 }
688
689 if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
690-#ifdef CONFIG_S3C2410
691+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
692 ulong old_gpecon = gpio->GPECON;
693 #endif
694 #ifdef CONFIG_S3C2400
695@@ -147,7 +149,7 @@
696 #endif
697 /* bus still busy probably by (most) previously interrupted transfer */
698
699-#ifdef CONFIG_S3C2410
700+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
701 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
702 gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
703 #endif
704@@ -171,7 +173,7 @@
705 udelay (1000);
706
707 /* restore pin functions */
708-#ifdef CONFIG_S3C2410
709+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
710 gpio->GPECON = old_gpecon;
711 #endif
712 #ifdef CONFIG_S3C2400
713Index: u-boot/drivers/usbdcore_s3c2410.c
714===================================================================
715--- u-boot.orig/drivers/usbdcore_s3c2410.c
716+++ u-boot/drivers/usbdcore_s3c2410.c
717@@ -24,7 +24,7 @@
718
719 #include <config.h>
720
721-#if defined(CONFIG_S3C2410) && defined(CONFIG_USB_DEVICE)
722+#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE)
723
724 #include <common.h>
725
726Index: u-boot/drivers/usbtty.h
727===================================================================
728--- u-boot.orig/drivers/usbtty.h
729+++ u-boot/drivers/usbtty.h
730@@ -29,7 +29,7 @@
731 #include "usbdcore_mpc8xx.h"
732 #elif defined(CONFIG_OMAP1510)
733 #include "usbdcore_omap1510.h"
734-#elif defined(CONFIG_S3C2410)
735+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
736 #include "usbdcore_s3c2410.h"
737 #endif
738
739Index: u-boot/cpu/arm920t/start.S
740===================================================================
741--- u-boot.orig/cpu/arm920t/start.S
742+++ u-boot/cpu/arm920t/start.S
743@@ -31,7 +31,11 @@
744
745 #include <config.h>
746 #include <version.h>
747+#if defined(CONFIG_S3C2410)
748 #include <s3c2410.h>
749+#elif defined(CONFIG_S3C2440)
750+#include <s3c2440.h>
751+#endif
752
753
754 /*
755@@ -142,14 +146,32 @@
756 # define pWTCON 0x15300000
757 # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
758 # define CLKDIVN 0x14800014 /* clock divisor register */
759-#elif defined(CONFIG_S3C2410)
760+#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440)
761 # define pWTCON 0x53000000
762 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
763 # define INTSUBMSK 0x4A00001C
764 # define CLKDIVN 0x4C000014 /* clock divisor register */
765 #endif
766
767-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
768+#if defined(CONFIG_S3C2410)
769+# define INTSUBMSK_val 0x7ff
770+# define MPLLCON_val ((0x90 << 12) + (0x7 << 4) + 0x0) /* 202 MHz */
771+# define UPLLCON_val ((0x78 << 12) + (0x2 << 4) + 0x3)
772+# define CLKDIVN_val 3 /* FCLK:HCLK:PCLK = 1:2:4 */
773+#elif defined(CONFIG_S3C2440)
774+# define INTSUBMSK_val 0xffff
775+#if (CONFIG_SYS_CLK_FREQ == 16934400)
776+# define MPLLCON_val ((0x61 << 12) + (0x1 << 4) + 0x2) /* 296.35 MHz */
777+# define UPLLCON_val ((0x3c << 12) + (0x4 << 4) + 0x2) /* 47.98 MHz */
778+#else if (CONFIG_SYS_CLK_FREQ == 12000000)
779+# define MPLLCON_val ((0x44 << 12) + (0x1 << 4) + 0x1) /* 304.00 MHz */
780+# define UPLLCON_val ((0x38 << 12) + (0x2 << 4) + 0x2) /* 48.00 MHz */
781+#endif
782+# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
783+# define CAMDIVN 0x4C000018
784+#endif
785+
786+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
787 ldr r0, =pWTCON
788 mov r1, #0x0
789 str r1, [r0]
790@@ -160,24 +182,34 @@
791 mov r1, #0xffffffff
792 ldr r0, =INTMSK
793 str r1, [r0]
794-# if defined(CONFIG_S3C2410)
795- ldr r1, =0x3ff
796+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
797+ ldr r1, =INTSUBMSK_val
798 ldr r0, =INTSUBMSK
799 str r1, [r0]
800 # endif
801
802- /* default FCLK is 202 MHz ! */
803+#if defined(CONFIG_S3C2440)
804+ /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
805+ ldr r0, =CAMDIVN
806+ mov r1, #0
807+ str r1, [r0]
808+#endif
809+
810+ /* Clock asynchronous mode */
811+ mrc p15, 0, r1, c1, c0, 0
812+ orr r1, r1, #0xc0000000
813+ mcr p15, 0, r1, c1, c0, 0
814+
815+
816 #define LOCKTIME 0x4c000000
817 #define UPLLCON 0x4c000008
818-//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2)
819-#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0)
820-#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3)
821+
822 ldr r0, =LOCKTIME
823 mov r1, #0xffffff
824 str r1, [r0]
825
826 ldr r0, =UPLLCON
827- ldr r1, =UPLLCFG
828+ ldr r1, =UPLLCON_val
829 str r1, [r0]
830
831 /* Page 7-19, seven nops between UPLL and MPLL */
832@@ -189,12 +221,12 @@
833 nop
834 nop
835
836- ldr r1, =MPLLCFG
837+ ldr r1, =MPLLCON_val
838 str r1, [r0, #-4] /* MPLLCON */
839
840 /* FCLK:HCLK:PCLK = 1:2:4 */
841 ldr r0, =CLKDIVN
842- mov r1, #3
843+ mov r1, #CLKDIVN_val
844 str r1, [r0]
845
846 #if 1
847@@ -222,7 +254,7 @@
848 str r1, [r0, #0x28]
849 #endif
850
851-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
852+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
853
854 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
855 #ifndef CONFIG_LL_INIT_NAND_ONLY
856@@ -279,7 +311,7 @@
857 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
858 bl cpu_init_crit
859 #endif
860-#if defined(CONFIG_S3C2410)
861+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
862 /* ensure some refresh has happened */
863 ldr r1, =0xfffff
864 1: subs r1, r1, #1
865@@ -290,11 +322,12 @@
866 ldr r0, [ r1 ]
867 tst r0, #0x02 /* is this resume from power down */
868 ldrne pc, [r1, #4] /* gstatus3 */
869-#endif /* CONFIG_S3C2410 */
870+#endif /* CONFIG_S3C2410 || CONFIG_S3C2440 */
871 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
872
873 /* mov r10, lr */
874
875+#if defined(CONFIG_S3C2410)
876 @ reset NAND
877 mov r1, #S3C2410_NAND_BASE
878 ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0
879@@ -314,6 +347,17 @@
880 ldr r2, [r1, #oNFCONF]
881 orr r2, r2, #0x800 @ disable chip
882 str r2, [r1, #oNFCONF]
883+#elif defined(CONFIG_S3C2440)
884+ mov r1, #S3C2440_NAND_BASE
885+ ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7
886+ ldr r3, [r1, #oNFCONF]
887+ orr r3, r3, r2
888+ str r3, [r1, #oNFCONF]
889+
890+ ldr r3, [r1, #oNFCONT]
891+ orr r3, r3, #1 @ enable nand controller
892+ str r3, [r1, #oNFCONT]
893+#endif
894
895 #if 0
896 @ get ready to call C functions (for nand_read())
897@@ -382,7 +426,7 @@
898 #endif /* CONFIG_S3C2410_NAND_BOOT */
899 done_relocate:
900
901-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C2410)
902+#if defined(CONFIG_USE_IRQ) && (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440))
903 /* In the case of the S3C2410, if we've somehow magically (JTAG, ...)
904 ended up in RAM, then that ram is mapped to 0x30000000 and not 0.
905 So we need to copy the interrupt vectors, etc. */
906Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c
907===================================================================
908--- u-boot.orig/cpu/arm920t/s3c24x0/nand_read.c
909+++ u-boot/cpu/arm920t/s3c24x0/nand_read.c
910@@ -16,30 +16,141 @@
911 */
912
913 #include <common.h>
914+#include <linux/mtd/nand.h>
915
916 #ifdef CONFIG_S3C2410_NAND_BOOT
917
918 #define __REGb(x) (*(volatile unsigned char *)(x))
919+#define __REGw(x) (*(volatile unsigned short *)(x))
920 #define __REGi(x) (*(volatile unsigned int *)(x))
921 #define NF_BASE 0x4e000000
922+#if defined(CONFIG_S3C2410)
923 #define NFCONF __REGi(NF_BASE + 0x0)
924 #define NFCMD __REGb(NF_BASE + 0x4)
925 #define NFADDR __REGb(NF_BASE + 0x8)
926 #define NFDATA __REGb(NF_BASE + 0xc)
927 #define NFSTAT __REGb(NF_BASE + 0x10)
928+#define NFSTAT_BUSY 1
929+#define nand_select() (NFCONF &= ~0x800)
930+#define nand_deselect() (NFCONF |= 0x800)
931+#define nand_clear_RnB() do {} while (0)
932+#elif defined(CONFIG_S3C2440)
933+#define NFCONF __REGi(NF_BASE + 0x0)
934+#define NFCONT __REGi(NF_BASE + 0x4)
935+#define NFCMD __REGb(NF_BASE + 0x8)
936+#define NFADDR __REGb(NF_BASE + 0xc)
937+#define NFDATA __REGb(NF_BASE + 0x10)
938+#define NFDATA16 __REGw(NF_BASE + 0x10)
939+#define NFSTAT __REGb(NF_BASE + 0x20)
940+#define NFSTAT_BUSY 1
941+#define nand_select() (NFCONT &= ~(1 << 1))
942+#define nand_deselect() (NFCONT |= (1 << 1))
943+#define nand_clear_RnB() (NFSTAT |= (1 << 2))
944+#endif
945
946-#define BUSY 1
947-inline void wait_idle(void)
948+static inline void nand_wait(void)
949 {
950 int i;
951
952- while (!(NFSTAT & BUSY))
953+ while (!(NFSTAT & NFSTAT_BUSY))
954 for (i=0; i<10; i++);
955 }
956
957-#define NAND_SECTOR_SIZE 512
958-#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
959-#define NAND_PAGE_SIZE 0x4000
960+#if defined(CONFIG_S3C2410)
961+/* configuration for 2410 with 512byte sized flash */
962+#define NAND_PAGE_SIZE 512
963+#define BAD_BLOCK_OFFSET 517
964+#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1)
965+#define NAND_BLOCK_SIZE 0x4000
966+#else
967+/* configuration for 2440 with 2048byte sized flash */
968+#define NAND_5_ADDR_CYCLE
969+#define NAND_PAGE_SIZE 2048
970+#define BAD_BLOCK_OFFSET NAND_PAGE_SIZE
971+#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1)
972+#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE * 64)
973+#endif
974+
975+/* compile time failure in case of an invalid configuration */
976+#if defined(CONFIG_S3C2410) && (NAND_PAGE_SIZE != 512)
977+#error "S3C2410 does not support nand page size != 512"
978+#endif
979+
980+static int is_bad_block(unsigned long i)
981+{
982+ unsigned char data;
983+ unsigned long page_num;
984+
985+ /* FIXME: do this twice, for first and second page in block */
986+
987+ nand_clear_RnB();
988+#if (NAND_PAGE_SIZE == 512)
989+ NFCMD = NAND_CMD_READOOB; /* 0x50 */
990+ NFADDR = BAD_BLOCK_OFFSET & 0xf;
991+ NFADDR = (i >> 9) & 0xff;
992+ NFADDR = (i >> 17) & 0xff;
993+ NFADDR = (i >> 25) & 0xff;
994+#elif (NAND_PAGE_SIZE == 2048)
995+ page_num = i >> 11; /* addr / 2048 */
996+ NFCMD = NAND_CMD_READ0;
997+ NFADDR = BAD_BLOCK_OFFSET & 0xff;
998+ NFADDR = (BAD_BLOCK_OFFSET >> 8) & 0xff;
999+ NFADDR = page_num & 0xff;
1000+ NFADDR = (page_num >> 8) & 0xff;
1001+ NFADDR = (page_num >> 16) & 0xff;
1002+ NFCMD = NAND_CMD_READSTART;
1003+#endif
1004+ nand_wait();
1005+ data = (NFDATA & 0xff);
1006+ if (data != 0xff)
1007+ return 1;
1008+
1009+ return 0;
1010+}
1011+
1012+static int nand_read_page_ll(unsigned char *buf, unsigned long addr)
1013+{
1014+ unsigned short *ptr16 = (unsigned short *)buf;
1015+ unsigned int i, page_num;
1016+
1017+ nand_clear_RnB();
1018+
1019+ NFCMD = NAND_CMD_READ0;
1020+
1021+#if (NAND_PAGE_SIZE == 512)
1022+ /* Write Address */
1023+ NFADDR = addr & 0xff;
1024+ NFADDR = (addr >> 9) & 0xff;
1025+ NFADDR = (addr >> 17) & 0xff;
1026+ NFADDR = (addr >> 25) & 0xff;
1027+#elif (NAND_PAGE_SIZE == 2048)
1028+ page_num = addr >> 11; /* addr / 2048 */
1029+ /* Write Address */
1030+ NFADDR = 0;
1031+ NFADDR = 0;
1032+ NFADDR = page_num & 0xff;
1033+ NFADDR = (page_num >> 8) & 0xff;
1034+ NFADDR = (page_num >> 16) & 0xff;
1035+ NFCMD = NAND_CMD_READSTART;
1036+#else
1037+#error "unsupported nand page size"
1038+#endif
1039+ nand_wait();
1040+
1041+#if defined(CONFIG_S3C2410)
1042+ for (i = 0; i < NAND_PAGE_SIZE; i++) {
1043+ *buf = (NFDATA & 0xff);
1044+ buf++;
1045+ }
1046+#elif defined(CONFIG_S3C2440)
1047+ for (i = 0; i < NAND_PAGE_SIZE/2; i++) {
1048+ *ptr16 = NFDATA16;
1049+ ptr16++;
1050+ }
1051+#endif
1052+
1053+ return NAND_PAGE_SIZE;
1054+}
1055
1056 /* low level nand read function */
1057 int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
1058@@ -50,47 +161,28 @@
1059 return -1; /* invalid alignment */
1060
1061 /* chip Enable */
1062- NFCONF &= ~0x800;
1063+ nand_select();
1064+ nand_clear_RnB();
1065 for (i=0; i<10; i++);
1066
1067 for (i=start_addr; i < (start_addr + size);) {
1068 #ifdef CONFIG_S3C2410_NAND_SKIP_BAD
1069- if (start_addr % NAND_PAGE_SIZE == 0) {
1070- unsigned char data;
1071- NFCMD = 0x50;
1072- NFADDR = 517&0xf;
1073- NFADDR = (i >> 9) & 0xff;
1074- NFADDR = (i >> 17) & 0xff;
1075- NFADDR = (i >> 25) & 0xff;
1076- wait_idle();
1077- data = (NFDATA & 0xff);
1078- if (data != 0xff) {
1079+ if (start_addr % NAND_BLOCK_SIZE == 0) {
1080+ if (is_bad_block(i)) {
1081 /* Bad block */
1082- i += NAND_PAGE_SIZE;
1083- size += NAND_PAGE_SIZE;
1084+ i += NAND_BLOCK_SIZE;
1085+ size += NAND_BLOCK_SIZE;
1086 continue;
1087 }
1088 }
1089 #endif
1090- /* READ0 */
1091- NFCMD = 0;
1092-
1093- /* Write Address */
1094- NFADDR = i & 0xff;
1095- NFADDR = (i >> 9) & 0xff;
1096- NFADDR = (i >> 17) & 0xff;
1097- NFADDR = (i >> 25) & 0xff;
1098-
1099- wait_idle();
1100-
1101- for (j=0; j < NAND_SECTOR_SIZE; j++, i++) {
1102- *buf = (NFDATA & 0xff);
1103- buf++;
1104- }
1105+ j = nand_read_page_ll(buf, i);
1106+ i += j;
1107+ buf += j;
1108 }
1109
1110 /* chip Disable */
1111- NFCONF |= 0x800; /* chip disable */
1112+ nand_deselect();
1113
1114 return 0;
1115 }
1116Index: u-boot/cpu/arm920t/s3c24x0/nand.c
1117===================================================================
1118--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
1119+++ u-boot/cpu/arm920t/s3c24x0/nand.c
1120@@ -36,24 +36,54 @@
1121 #define __REGi(x) (*(volatile unsigned int *)(x))
1122
1123 #define NF_BASE 0x4e000000
1124+
1125 #define NFCONF __REGi(NF_BASE + 0x0)
1126-#define NFCMD __REGb(NF_BASE + 0x4)
1127-#define NFADDR __REGb(NF_BASE + 0x8)
1128-#define NFDATA __REGb(NF_BASE + 0xc)
1129-#define NFSTAT __REGb(NF_BASE + 0x10)
1130+
1131+#if defined(CONFIG_S3C2410)
1132+
1133+#define oNFCMD 0x4
1134+#define oNFADDR 0x8
1135+#define oNFDATA 0xc
1136+#define oNFSTAT 0x10
1137 #define NFECC0 __REGb(NF_BASE + 0x14)
1138 #define NFECC1 __REGb(NF_BASE + 0x15)
1139 #define NFECC2 __REGb(NF_BASE + 0x16)
1140+#define NFCONF_nFCE (1<<11)
1141
1142 #define S3C2410_NFCONF_EN (1<<15)
1143 #define S3C2410_NFCONF_512BYTE (1<<14)
1144 #define S3C2410_NFCONF_4STEP (1<<13)
1145 #define S3C2410_NFCONF_INITECC (1<<12)
1146-#define S3C2410_NFCONF_nFCE (1<<11)
1147 #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
1148 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
1149 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
1150
1151+#elif defined(CONFIG_S3C2440)
1152+
1153+#define oNFCMD 0x8
1154+#define oNFADDR 0xc
1155+#define oNFDATA 0x10
1156+#define oNFSTAT 0x20
1157+
1158+#define NFCONT __REGi(NF_BASE + 0x04)
1159+#define NFMECC0 __REGi(NF_BASE + 0x2C)
1160+#define NFCONF_nFCE (1<<1)
1161+#define S3C2440_NFCONF_INITECC (1<<4)
1162+#define S3C2440_NFCONF_MAINECCLOCK (1<<5)
1163+#define nand_select() (NFCONT &= ~(1 << 1))
1164+#define nand_deselect() (NFCONT |= (1 << 1))
1165+#define nand_clear_RnB() (NFSTAT |= (1 << 2))
1166+#define nand_detect_RB() { while(!(NFSTAT&(1<<2))); }
1167+#define nand_wait() { while(!(NFSTAT & 0x4)); } /* RnB_TransDectect */
1168+
1169+#endif
1170+
1171+#define NFCMD __REGb(NF_BASE + oNFCMD)
1172+#define NFADDR __REGb(NF_BASE + oNFADDR)
1173+#define NFDATA __REGb(NF_BASE + oNFDATA)
1174+#define NFSTAT __REGb(NF_BASE + oNFSTAT)
1175+
1176+
1177 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
1178 {
1179 struct nand_chip *chip = mtd->priv;
1180@@ -62,23 +92,31 @@
1181
1182 switch (cmd) {
1183 case NAND_CTL_SETNCE:
1184- NFCONF &= ~S3C2410_NFCONF_nFCE;
1185+#if defined(CONFIG_S3C2410)
1186+ NFCONF &= ~NFCONF_nFCE;
1187+#elif defined(CONFIG_S3C2440)
1188+ NFCONT &= ~NFCONF_nFCE;
1189+#endif
1190 DEBUGN("NFCONF=0x%08x\n", NFCONF);
1191 break;
1192 case NAND_CTL_CLRNCE:
1193- NFCONF |= S3C2410_NFCONF_nFCE;
1194+#if defined(CONFIG_S3C2410)
1195+ NFCONF |= NFCONF_nFCE;
1196+#elif defined(CONFIG_S3C2440)
1197+ NFCONT &= ~NFCONF_nFCE;
1198+#endif
1199 DEBUGN("NFCONF=0x%08x\n", NFCONF);
1200 break;
1201 case NAND_CTL_SETALE:
1202- chip->IO_ADDR_W = NF_BASE + 0x8;
1203+ chip->IO_ADDR_W = NF_BASE + oNFADDR;
1204 DEBUGN("SETALE\n");
1205 break;
1206 case NAND_CTL_SETCLE:
1207- chip->IO_ADDR_W = NF_BASE + 0x4;
1208+ chip->IO_ADDR_W = NF_BASE + oNFCMD;
1209 DEBUGN("SETCLE\n");
1210 break;
1211 default:
1212- chip->IO_ADDR_W = NF_BASE + 0xc;
1213+ chip->IO_ADDR_W = NF_BASE + oNFDATA;
1214 break;
1215 }
1216 return;
1217@@ -180,16 +218,21 @@
1218 /* initialize hardware */
1219 twrph0 = 3; twrph1 = 0; tacls = 0;
1220
1221+#if defined(CONFIG_S3C2410)
1222 cfg = S3C2410_NFCONF_EN;
1223 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
1224 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
1225 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
1226
1227 NFCONF = cfg;
1228- //NFCONF = 0xf842;
1229+#elif defined(CONFIG_S3C2440)
1230+ twrph0 = 7; twrph1 = 7; tacls = 7;
1231+ NFCONF = (tacls<<12)|(twrph0<<8)|(twrph1<<4)|(0<<0);
1232+ NFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
1233+#endif
1234
1235 /* initialize nand_chip data structure */
1236- nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c;
1237+ nand->IO_ADDR_R = nand->IO_ADDR_W = NF_BASE + oNFDATA;
1238
1239 /* read_buf and write_buf are default */
1240 /* read_byte and write_byte are default */
1241@@ -214,12 +257,23 @@
1242 nand->options = 0;
1243 #endif
1244
1245+#if defined(CONFIG_S3C2440)
1246+/*
1247+ nand_select();
1248+ nand_clear_RnB();
1249+ NFCMD = NAND_CMD_RESET;
1250+ { volatile int i; for (i = 0; i < 10; i ++); }
1251+ nand_detect_RB();
1252+ nand_deselect();
1253+*/
1254+#endif
1255+
1256 DEBUGN("end of nand_init\n");
1257
1258 return 0;
1259 }
1260
1261 #else
1262- #error "U-Boot legacy NAND support not available for S3C2410"
1263+ #error "U-Boot legacy NAND support not available for S3C24xx"
1264 #endif
1265 #endif
1266Index: u-boot/cpu/arm920t/s3c24x0/mmc.c
1267===================================================================
1268--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c
1269+++ u-boot/cpu/arm920t/s3c24x0/mmc.c
1270@@ -137,6 +137,9 @@
1271 dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART;
1272 if (wide)
1273 dcon |= S3C2410_SDIDCON_WIDEBUS;
1274+#if defined(CONFIG_S3C2440)
1275+ dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART;
1276+#endif
1277 sdi->SDIDCON = dcon;
1278
1279 /* send read command */
1280@@ -394,13 +397,18 @@
1281
1282 clk_power->CLKCON |= (1 << 9);
1283
1284+ sdi->SDIBSIZE = 512;
1285+#if defined(CONFIG_S3C2410)
1286 /* S3C2410 has some bug that prevents reliable operation at higher speed */
1287 //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
1288- sdi->SDIPRE = 0x02; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */
1289- sdi->SDIBSIZE = 512;
1290+ sdi->SDIPRE = 0x02; /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */
1291 sdi->SDIDTIMER = 0xffff;
1292+#elif defined(CONFIG_S3C2440)
1293+ sdi->SDIPRE = 0x05; /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */
1294+ sdi->SDIDTIMER = 0x7fffff;
1295+#endif
1296 sdi->SDIIMSK = 0x0;
1297- sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK;
1298+ sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2410_SDICON_CLOCKTYPE;
1299 udelay(125000); /* FIXME: 74 SDCLK cycles */
1300
1301 mmc_csd.c_size = 0;
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-01-12 13:43:26 +0000