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-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch1169
1 files changed, 1169 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch
new file mode 100644
index 0000000000..f85fdea836
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch
@@ -0,0 +1,1169 @@
1Patch to add HXD8 support
2
3Index: u-boot/Makefile
4===================================================================
5--- u-boot.orig/Makefile
6+++ u-boot/Makefile
7@@ -2026,6 +2026,9 @@
8 qt2410_config : unconfig
9 @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0
10
11+hxd8_config : unconfig
12+ @$(MKCONFIG) $(@:_config=) arm arm920t hxd8 NULL s3c24x0
13+
14 scb9328_config : unconfig
15 @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
16
17Index: u-boot/board/hxd8/Makefile
18===================================================================
19--- /dev/null
20+++ u-boot/board/hxd8/Makefile
21@@ -0,0 +1,65 @@
22+#
23+# (C) Copyright 2000-2006
24+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
25+#
26+# See file CREDITS for list of people who contributed to this
27+# project.
28+#
29+# This program is free software; you can redistribute it and/or
30+# modify it under the terms of the GNU General Public License as
31+# published by the Free Software Foundation; either version 2 of
32+# the License, or (at your option) any later version.
33+#
34+# This program is distributed in the hope that it will be useful,
35+# but WITHOUT ANY WARRANTY; without even the implied warranty of
36+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37+# GNU General Public License for more details.
38+#
39+# You should have received a copy of the GNU General Public License
40+# along with this program; if not, write to the Free Software
41+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42+# MA 02111-1307 USA
43+#
44+
45+include $(TOPDIR)/config.mk
46+
47+LIB = $(obj)lib$(BOARD).a
48+
49+COBJS := hxd8.o udc.o pcf50606.o
50+SOBJS := lowlevel_init.o
51+
52+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
53+OBJS := $(addprefix $(obj),$(COBJS))
54+SOBJS := $(addprefix $(obj),$(SOBJS))
55+
56+all: $(LIB) lowevel_foo.bin
57+
58+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
59+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
60+
61+lowlevel_foo.o: lowlevel_foo.S
62+ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
63+ -o lowlevel_foo.o lowlevel_foo.S
64+
65+lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds
66+ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
67+ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
68+
69+lowevel_foo.bin: lowlevel_foo
70+ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
71+ lowlevel_foo lowlevel_foo.bin
72+
73+clean:
74+ rm -f $(SOBJS) $(OBJS)
75+
76+distclean: clean
77+ rm -f $(LIB) core *.bak .depend
78+
79+#########################################################################
80+
81+# defines $(obj).depend target
82+include $(SRCTREE)/rules.mk
83+
84+sinclude $(obj).depend
85+
86+#########################################################################
87Index: u-boot/board/hxd8/hxd8.c
88===================================================================
89--- /dev/null
90+++ u-boot/board/hxd8/hxd8.c
91@@ -0,0 +1,189 @@
92+/*
93+ * (C) Copyright 2007 by OpenMoko, Inc.
94+ * Author: Harald Welte <laforge@openmoko.org>
95+ *
96+ * (C) Copyright 2002
97+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
98+ * Marius Groeger <mgroeger@sysgo.de>
99+ *
100+ * (C) Copyright 2002
101+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
102+ *
103+ * See file CREDITS for list of people who contributed to this
104+ * project.
105+ *
106+ * This program is free software; you can redistribute it and/or
107+ * modify it under the terms of the GNU General Public License as
108+ * published by the Free Software Foundation; either version 2 of
109+ * the License, or (at your option) any later version.
110+ *
111+ * This program is distributed in the hope that it will be useful,
112+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
113+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
114+ * GNU General Public License for more details.
115+ *
116+ * You should have received a copy of the GNU General Public License
117+ * along with this program; if not, write to the Free Software
118+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
119+ * MA 02111-1307 USA
120+ */
121+
122+#include <common.h>
123+#include <video_fb.h>
124+#include <nand.h>
125+#include <pcf50606.h>
126+#include <s3c2440.h>
127+
128+DECLARE_GLOBAL_DATA_PTR;
129+
130+#define FCLK_SPEED 1
131+
132+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
133+#define M_MDIV 0xC3
134+#define M_PDIV 0x4
135+#define M_SDIV 0x1
136+#elif FCLK_SPEED==1
137+#if 0
138+#define M_MDIV 0x6e /* Fout = 399.65MHz */
139+#define M_PDIV 0x3
140+#define M_SDIV 0x1
141+#else
142+#define M_MDIV 0x61 /* Fout = 296.35MHz due to wrong PLL capacitors */
143+#define M_PDIV 0x1
144+#define M_SDIV 0x2
145+#endif
146+#endif
147+
148+#define USB_CLOCK 1
149+
150+#if USB_CLOCK==0
151+#define U_M_MDIV 0xA1
152+#define U_M_PDIV 0x3
153+#define U_M_SDIV 0x1
154+#elif USB_CLOCK==1
155+#define U_M_MDIV 0x3c
156+#define U_M_PDIV 0x4
157+#define U_M_SDIV 0x2
158+#endif
159+
160+static inline void delay (unsigned long loops)
161+{
162+ __asm__ volatile ("1:\n"
163+ "subs %0, %1, #1\n"
164+ "bne 1b":"=r" (loops):"0" (loops));
165+}
166+
167+/*
168+ * Miscellaneous platform dependent initialisations
169+ */
170+
171+int board_init (void)
172+{
173+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
174+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
175+
176+ /* to reduce PLL lock time, adjust the LOCKTIME register */
177+ clk_power->LOCKTIME = 0xFFFFFF;
178+
179+ /* configure MPLL */
180+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
181+
182+ /* some delay between MPLL and UPLL */
183+ delay (4000);
184+
185+ /* configure UPLL */
186+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
187+
188+ /* some delay between MPLL and UPLL */
189+ delay (8000);
190+
191+ /* set up the I/O ports */
192+ gpio->GPACON = 0x005E0FFE;
193+ gpio->GPADAT = 0x0001C000;
194+ gpio->GPBCON = 0x00045542;
195+ gpio->GPBUP = 0x000007FF;
196+ gpio->GPCCON = 0xAAAA02A9;
197+ gpio->GPCUP = 0x0000FFFF;
198+ gpio->GPDCON = 0xAAAAAAAA;
199+ gpio->GPDUP = 0x0000FFFF;
200+ gpio->GPECON = 0xAAAAAAAA;
201+ gpio->GPEUP = 0x0000FFFF;
202+ gpio->GPFCON = 0x0000AAA9;
203+ gpio->GPFUP = 0x000000FF;
204+ gpio->GPGCON = 0x027D0316;
205+ gpio->GPGUP = 0x0000FFFF;
206+ gpio->GPHCON = 0x0014AAAA;
207+ gpio->GPHUP = 0x000007FF;
208+ gpio->GPJCON = 0x00000000;
209+
210+ /* USB CHG enable */
211+ gpio->GPGDAT |= ( 1 << 11);
212+#if 0
213+ /* USB Device Part */
214+ /*GPGCON is reset for USB Device */
215+ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
216+ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
217+
218+ gpio->GPGDAT |= ( 1 << 12);
219+ gpio->GPGDAT &= ~( 1 << 12);
220+ udelay(20000);
221+ gpio->GPGDAT |= ( 1 << 12);
222+#endif
223+
224+ /* arch number of SMDK2440-Board */
225+ gd->bd->bi_arch_number = MACH_TYPE_HXD8;
226+
227+ /* adress of boot parameters */
228+ gd->bd->bi_boot_params = 0x30000100;
229+
230+ icache_enable();
231+ dcache_enable();
232+
233+ return 0;
234+}
235+
236+void board_video_init(GraphicDevice *pGD)
237+{
238+ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
239+
240+ lcd->LCDCON1 = 0x0000057b;
241+ lcd->LCDCON2 = 0x0143c049;
242+ lcd->LCDCON3 = 0x0009df01;
243+ lcd->LCDCON4 = 0x00000028;
244+ lcd->LCDCON5 = 0x00000b08;
245+
246+ lcd->TPAL = 0x01202020;
247+
248+ //lcd->LCDCON5 |= (0x01 << 3);
249+}
250+
251+int board_late_init(void)
252+{
253+ /* Initialize the Power Management Unit with a safe register set */
254+ pcf50606_init();
255+
256+ return 0;
257+}
258+
259+int dram_init(void)
260+{
261+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
262+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
263+
264+ return 0;
265+}
266+
267+u_int32_t get_board_rev(void)
268+{
269+ return 0x00000110;
270+}
271+
272+/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
273+ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
274+ images: 640*480*2*2 = 1228800 < 1245184. */
275+
276+unsigned int dynpart_size[] = {
277+ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3fd00000, 0 };
278+char *dynpart_names[] = {
279+ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
280+
281Index: u-boot/board/hxd8/lowlevel_init.S
282===================================================================
283--- /dev/null
284+++ u-boot/board/hxd8/lowlevel_init.S
285@@ -0,0 +1,171 @@
286+/*
287+ * Memory Setup stuff - taken from blob memsetup.S
288+ *
289+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
290+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
291+ *
292+ * Modified for the FIC HXD8 by Harald Welte <laforge@openmoko.org>
293+ * (C) Copyright 2007 by OpenMoko, Inc.
294+ *
295+ * See file CREDITS for list of people who contributed to this
296+ * project.
297+ *
298+ * This program is free software; you can redistribute it and/or
299+ * modify it under the terms of the GNU General Public License as
300+ * published by the Free Software Foundation; either version 2 of
301+ * the License, or (at your option) any later version.
302+ *
303+ * This program is distributed in the hope that it will be useful,
304+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
305+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
306+ * GNU General Public License for more details.
307+ *
308+ * You should have received a copy of the GNU General Public License
309+ * along with this program; if not, write to the Free Software
310+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
311+ * MA 02111-1307 USA
312+ */
313+
314+
315+#include <config.h>
316+#include <version.h>
317+
318+
319+/* some parameters for the board */
320+
321+/*
322+ *
323+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
324+ *
325+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
326+ *
327+ */
328+
329+#define BWSCON 0x48000000
330+
331+/* BWSCON */
332+#define DW8 (0x0)
333+#define DW16 (0x1)
334+#define DW32 (0x2)
335+#define WAIT (0x1<<2)
336+#define UBLB (0x1<<3)
337+
338+#define B1_BWSCON (DW32)
339+#define B2_BWSCON (DW16)
340+#define B3_BWSCON (DW16 + WAIT + UBLB)
341+#define B4_BWSCON (DW16)
342+#define B5_BWSCON (DW16)
343+#define B6_BWSCON (DW32)
344+#define B7_BWSCON (DW32)
345+
346+/* BANK0CON */
347+#define B0_Tacs 0x0 /* 0clk */
348+#define B0_Tcos 0x0 /* 0clk */
349+#define B0_Tacc 0x7 /* 14clk */
350+#define B0_Tcoh 0x0 /* 0clk */
351+#define B0_Tah 0x0 /* 0clk */
352+#define B0_Tacp 0x0
353+#define B0_PMC 0x0 /* normal */
354+
355+/* BANK1CON */
356+#define B1_Tacs 0x0 /* 0clk */
357+#define B1_Tcos 0x0 /* 0clk */
358+#define B1_Tacc 0x7 /* 14clk */
359+#define B1_Tcoh 0x0 /* 0clk */
360+#define B1_Tah 0x0 /* 0clk */
361+#define B1_Tacp 0x0
362+#define B1_PMC 0x0
363+
364+#define B2_Tacs 0x0
365+#define B2_Tcos 0x0
366+#define B2_Tacc 0x7
367+#define B2_Tcoh 0x0
368+#define B2_Tah 0x0
369+#define B2_Tacp 0x0
370+#define B2_PMC 0x0
371+
372+#define B3_Tacs 0x0 /* 0clk */
373+#define B3_Tcos 0x3 /* 4clk */
374+#define B3_Tacc 0x7 /* 14clk */
375+#define B3_Tcoh 0x1 /* 1clk */
376+#define B3_Tah 0x0 /* 0clk */
377+#define B3_Tacp 0x3 /* 6clk */
378+#define B3_PMC 0x0 /* normal */
379+
380+#define B4_Tacs 0x0 /* 0clk */
381+#define B4_Tcos 0x0 /* 0clk */
382+#define B4_Tacc 0x7 /* 14clk */
383+#define B4_Tcoh 0x0 /* 0clk */
384+#define B4_Tah 0x0 /* 0clk */
385+#define B4_Tacp 0x0
386+#define B4_PMC 0x0 /* normal */
387+
388+#define B5_Tacs 0x0 /* 0clk */
389+#define B5_Tcos 0x0 /* 0clk */
390+#define B5_Tacc 0x7 /* 14clk */
391+#define B5_Tcoh 0x0 /* 0clk */
392+#define B5_Tah 0x0 /* 0clk */
393+#define B5_Tacp 0x0
394+#define B5_PMC 0x0 /* normal */
395+
396+#define B6_MT 0x3 /* SDRAM */
397+#define B6_Trcd 0x1 /* 3clk */
398+#define B6_SCAN 0x2 /* 10bit */
399+
400+#define B7_MT 0x3 /* SDRAM */
401+#define B7_Trcd 0x1 /* 3clk */
402+#define B7_SCAN 0x1 /* 9bit */
403+
404+/* REFRESH parameter */
405+#define REFEN 0x1 /* Refresh enable */
406+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
407+#define Trp 0x1 /* 3clk */
408+#define Trc 0x3 /* 7clk */
409+#define Tchr 0x2 /* 3clk */
410+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
411+/**************************************/
412+
413+_TEXT_BASE:
414+ .word TEXT_BASE
415+
416+.globl lowlevel_init
417+lowlevel_init:
418+ /* memory control configuration */
419+ /* make r0 relative the current location so that it */
420+ /* reads SMRDATA out of FLASH rather than memory ! */
421+ ldr r0, =SMRDATA
422+ ldr r1, _TEXT_BASE
423+ sub r0, r0, r1
424+ ldr r1, =BWSCON /* Bus Width Status Controller */
425+ add r2, r0, #13*4
426+0:
427+ ldr r3, [r0], #4
428+ str r3, [r1], #4
429+ cmp r2, r0
430+ bne 0b
431+
432+ /* setup asynchronous bus mode */
433+ mrc p15, 0, r1 ,c1 ,c0, 0
434+ orr r1, r1, #0xc0000000
435+ mcr p15, 0, r1, c1, c0, 0
436+
437+ /* everything is fine now */
438+ mov pc, lr
439+
440+ .ltorg
441+/* the literal pools origin */
442+
443+SMRDATA:
444+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
445+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
446+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
447+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
448+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
449+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
450+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
451+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
452+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
453+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
454+ .word 0x32
455+ .word 0x30
456+ .word 0x30
457Index: u-boot/include/configs/hxd8.h
458===================================================================
459--- /dev/null
460+++ u-boot/include/configs/hxd8.h
461@@ -0,0 +1,277 @@
462+/*
463+ * (C) Copyright 2007 OpenMoko, Inc.
464+ * Author: Harald Welte <laforge@openmoko.org>
465+ *
466+ * Configuation settings for the FIC HXD8
467+ *
468+ * See file CREDITS for list of people who contributed to this
469+ * project.
470+ *
471+ * This program is free software; you can redistribute it and/or
472+ * modify it under the terms of the GNU General Public License as
473+ * published by the Free Software Foundation; either version 2 of
474+ * the License, or (at your option) any later version.
475+ *
476+ * This program is distributed in the hope that it will be useful,
477+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
478+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
479+ * GNU General Public License for more details.
480+ *
481+ * You should have received a copy of the GNU General Public License
482+ * along with this program; if not, write to the Free Software
483+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
484+ * MA 02111-1307 USA
485+ */
486+
487+#ifndef __CONFIG_H
488+#define __CONFIG_H
489+
490+/* we want to be able to start u-boot directly from within NAND flash */
491+#define CONFIG_LL_INIT_NAND_ONLY
492+#define CONFIG_S3C2410_NAND_BOOT 1
493+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
494+
495+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
496+
497+/*
498+ * High Level Configuration Options
499+ * (easy to change)
500+ */
501+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
502+#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
503+#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */
504+#define CONFIG_HXD8 1 /* on a FIC HXD8 Board */
505+
506+/* input clock of PLL */
507+#define CONFIG_SYS_CLK_FREQ 16934400/* the HXD8 has this input clock */
508+
509+
510+#define USE_920T_MMU 1
511+#define CONFIG_USE_IRQ 1
512+
513+/*
514+ * Size of malloc() pool
515+ */
516+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024)
517+ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
518+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
519+
520+/*
521+ * Hardware drivers
522+ */
523+
524+/*
525+ * select serial console configuration
526+ */
527+#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on HXD8 */
528+
529+/************************************************************
530+ * RTC
531+ ************************************************************/
532+#define CONFIG_RTC_S3C24X0 1
533+
534+/* allow to overwrite serial and ethaddr */
535+#define CONFIG_ENV_OVERWRITE
536+
537+#define CONFIG_BAUDRATE 115200
538+
539+/***********************************************************
540+ * Command definition
541+ ***********************************************************/
542+#define CONFIG_COMMANDS (\
543+ CFG_CMD_BDI | \
544+ CFG_CMD_LOADS | \
545+ CFG_CMD_LAODB | \
546+ CFG_CMD_IMI | \
547+ CFG_CMD_CACHE | \
548+ CFG_CMD_MEMORY | \
549+ CFG_CMD_ENV | \
550+ /* CFG_CMD_IRQ | */ \
551+ CFG_CMD_BOOTD | \
552+ CFG_CMD_CONSOLE | \
553+ /* CFG_CMD_BMP | */ \
554+ CFG_CMD_ASKENV | \
555+ CFG_CMD_RUN | \
556+ CFG_CMD_ECHO | \
557+ CFG_CMD_I2C | \
558+ CFG_CMD_REGINFO | \
559+ CFG_CMD_IMMAP | \
560+ CFG_CMD_DATE | \
561+ CFG_CMD_AUTOSCRIPT | \
562+ CFG_CMD_BSP | \
563+ CFG_CMD_ELF | \
564+ CFG_CMD_MISC | \
565+ /* CFG_CMD_USB | */ \
566+ CFG_CMD_JFFS2 | \
567+ CFG_CMD_DIAG | \
568+ /* CFG_CMD_HWFLOW | */ \
569+ CFG_CMD_SAVES | \
570+ CFG_CMD_NAND | \
571+ CFG_CMD_PORTIO | \
572+ CFG_CMD_MMC | \
573+ CFG_CMD_FAT | \
574+ CFG_CMD_EXT2 | \
575+ 0)
576+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
577+#include <cmd_confdefs.h>
578+
579+#define CONFIG_BOOTDELAY 3
580+#define CONFIG_BOOTARGS ""
581+#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
582+
583+#define CONFIG_DOS_PARTITION 1
584+
585+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
586+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
587+/* what's this ? it's not used anywhere */
588+#define CONFIG_KGDB_SER_INDEX 3 /* which serial port to use */
589+#endif
590+
591+/*
592+ * Miscellaneous configurable options
593+ */
594+#define CFG_LONGHELP /* undef to save memory */
595+#define CFG_PROMPT "HXD8 # " /* Monitor Command Prompt */
596+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
597+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
598+#define CFG_MAXARGS 64 /* max number of command args */
599+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
600+
601+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
602+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
603+
604+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
605+
606+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
607+
608+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
609+/* it to wrap 100 times (total 1562500) to get 1 sec. */
610+#define CFG_HZ 1562500
611+
612+/* valid baudrates */
613+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
614+
615+/*-----------------------------------------------------------------------
616+ * Stack sizes
617+ *
618+ * The stack sizes are set up in start.S using the settings below
619+ */
620+#define CONFIG_STACKSIZE (512*1024) /* regular stack */
621+#ifdef CONFIG_USE_IRQ
622+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
623+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
624+#endif
625+
626+#if 0
627+#define CONFIG_USB_OHCI 1
628+#endif
629+
630+#if 1
631+#define CONFIG_USB_DEVICE 1
632+#define CONFIG_USB_TTY 1
633+#define CFG_CONSOLE_IS_IN_ENV 1
634+#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
635+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
636+#define CONFIG_USBD_PRODUCTID_CDCACM 0x511a /* CDC ACM */
637+#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc"
638+#define CONFIG_USBD_PRODUCT_NAME "HXD8 Bootloader " U_BOOT_VERSION
639+#define CONFIG_USBD_DFU 1
640+#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
641+#define CONFIG_USBD_DFU_INTERFACE 2
642+#endif
643+#define CFG_CONSOLE_IS_IN_ENV 1
644+
645+#define CONFIG_EXTRA_ENV_SETTINGS \
646+ "usbtty=cdc_acm\0" \
647+ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC2,115200 console=tty0 loglevel=8\0" \
648+ ""
649+
650+/*-----------------------------------------------------------------------
651+ * Physical Memory Map
652+ */
653+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
654+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
655+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
656+#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
657+
658+/*-----------------------------------------------------------------------
659+ * FLASH and environment organization
660+ */
661+
662+/* No NOR flash in this device */
663+#define CFG_NO_FLASH 1
664+
665+#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */
666+#define CFG_ENV_IS_IN_NAND 1
667+#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
668+#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
669+
670+#define NAND_MAX_CHIPS 3
671+#define CFG_NAND_BASE 0x4e000000
672+#define CFG_MAX_NAND_DEVICE NAND_MAX_CHIPS
673+#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_BASE, CFG_NAND_BASE }
674+
675+#define CONFIG_MMC 1
676+#define CFG_MMC_BASE 0xff000000
677+
678+/* EXT2 driver */
679+#define CONFIG_EXT2 1
680+
681+#define CONFIG_FAT 1
682+#define CONFIG_SUPPORT_VFAT
683+
684+#if 1
685+/* JFFS2 driver */
686+#define CONFIG_JFFS2_CMDLINE 1
687+#define CONFIG_JFFS2_NAND 1
688+#define CONFIG_JFFS2_NAND_DEV 0
689+//#define CONFIG_JFFS2_NAND_OFF 0x634000
690+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
691+#endif
692+
693+/* ATAG configuration */
694+#define CONFIG_INITRD_TAG 1
695+#define CONFIG_SETUP_MEMORY_TAGS 1
696+#define CONFIG_CMDLINE_TAG 1
697+#define CONFIG_REVISION_TAG 1
698+#if 0
699+#define CONFIG_SERIAL_TAG 1
700+#endif
701+
702+#define CONFIG_DRIVER_S3C24X0_I2C 1
703+#define CONFIG_HARD_I2C 1
704+#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */
705+#define CFG_I2C_SLAVE 0x7f
706+
707+/* we have a board_late_init() function */
708+#define BOARD_LATE_INIT 1
709+
710+#if 1
711+#define CONFIG_VIDEO
712+#define CONFIG_VIDEO_S3C2410
713+#define CONFIG_CFB_CONSOLE
714+#define CONFIG_VIDEO_LOGO
715+#define CONFIG_SPLASH_SCREEN
716+#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
717+#define CONFIG_VIDEO_BMP_GZIP
718+#define CONFIG_VGA_AS_SINGLE_DEVICE
719+#define CONFIG_UNZIP
720+
721+#define VIDEO_KBD_INIT_FCT 0
722+#define VIDEO_TSTC_FCT serial_tstc
723+#define VIDEO_GETC_FCT serial_getc
724+
725+#define LCD_VIDEO_ADDR 0x33d00000
726+#endif
727+
728+#define CONFIG_S3C2410_NAND_BBT 1
729+//#define CONFIG_S3C2410_NAND_HWECC 1
730+
731+#define CONFIG_DRIVER_PCF50606 1
732+
733+#define MTDIDS_DEFAULT "nand0=hxd8-nand"
734+#define MTPARTS_DEFAULT "hxd8-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),0x3fd00000(jffs2)"
735+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "hxd8-nand"
736+#define CONFIG_NAND_DYNPART
737+
738+#endif /* __CONFIG_H */
739Index: u-boot/board/hxd8/udc.c
740===================================================================
741--- /dev/null
742+++ u-boot/board/hxd8/udc.c
743@@ -0,0 +1,30 @@
744+
745+#include <common.h>
746+#include <usbdcore.h>
747+#include <s3c2440.h>
748+
749+#if defined(CONFIG_USB_DEVICE)
750+
751+void udc_ctrl(enum usbd_event event, int param)
752+{
753+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
754+
755+ switch (event) {
756+ case UDC_CTRL_PULLUP_ENABLE:
757+ if (param)
758+ gpio->GPBDAT |= (1 << 9); /* GPB9 */
759+ else
760+ gpio->GPBDAT &= ~(1 << 9); /* GPB9 */
761+ break;
762+ case UDC_CTRL_500mA_ENABLE:
763+ if (param)
764+ gpio->GPADAT |= (1 << 0); /* GPA0 */
765+ else
766+ gpio->GPADAT &= ~(1 << 0); /* GPA0 */
767+ break;
768+ default:
769+ break;
770+ }
771+}
772+
773+#endif /* CONFIG_USB_DEVICE */
774Index: u-boot/board/hxd8/pcf50606.c
775===================================================================
776--- /dev/null
777+++ u-boot/board/hxd8/pcf50606.c
778@@ -0,0 +1,67 @@
779+
780+#include <common.h>
781+#include <pcf50606.h>
782+
783+/* initial register set for PCF50606 in HXD8 devices */
784+const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = {
785+ [PCF50606_REG_OOCS] = 0x00,
786+ /* gap */
787+ [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND,
788+ [PCF50606_REG_INT2M] = PCF50606_INT2_CHGFOK |
789+ PCF50606_INT2_CHGERR |
790+ PCF50606_INT2_CHGFRDY |
791+ PCF50606_INT2_CHGPROT |
792+ PCF50606_INT2_CHGWD10S |
793+ PCF50606_INT2_CHGWDEXP,
794+ [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES,
795+ [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK |
796+ PCF50606_OOCC1_CHGWAK &
797+ PCF50606_OOCC1_EXTONWAK_NO_WAKEUP,
798+ [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms |
799+ PCF50606_OOCC2_EXTONDB_14ms,
800+ /* gap */
801+ [PCF50606_REG_PSSC] = 0x00,
802+ [PCF50606_REG_PWROKM] = 0x00,
803+ /* gap */
804+ [PCF50606_REG_DCDC1] = 0xf0, /* CORE_1V3: on */
805+ [PCF50606_REG_DCDC2] = 0x00,
806+ [PCF50606_REG_DCDC3] = 0x00,
807+ [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */
808+
809+ [PCF50606_REG_DCDEC1] = 0xe8, /* IO1_3V3: off */
810+ [PCF50606_REG_DCDEC2] = 0x00,
811+
812+ [PCF50606_REG_DCUDC1] = 0x08, /* RF_3V3: off */
813+ [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */
814+
815+ [PCF50606_REG_IOREGC] = 0xf8, /* AUDIO_3V3: on */
816+
817+ [PCF50606_REG_D1REGC1] = 0xf8, /* RC_3V3: on */
818+
819+ [PCF50606_REG_D2REGC1] = 0x18, /* GPS_3V3: off */
820+
821+ [PCF50606_REG_D3REGC1] = 0xf8, /* IO2_3V3: off */
822+
823+ [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */
824+ [PCF50606_REG_LPREGC2] = 0x00,
825+
826+ [PCF50606_REG_MBCC1] = 0x00, /* charger unused */
827+ [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */
828+ [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */
829+ [PCF50606_REG_BBCC] = 0x1f, /* 400uA */
830+ [PCF50606_REG_ADCC1] = 0x00,
831+ [PCF50606_REG_ADCC2] = 0x00,
832+ /* gap */
833+ [PCF50606_REG_ACDC1] = 0x00,
834+ [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3,
835+ [PCF50606_REG_PWMC1] = 0x1f, /* clock: 512 DC: 15/16*/
836+ [PCF50606_REG_LEDC1] = 0x00,
837+ [PCF50606_REG_LEDC2] = 0x00,
838+ [PCF50606_REG_GPOC1] = 0x03, /* PWM ACTIVE */
839+ [PCF50606_REG_GPOC2] = 0x07, /* back light pull low */
840+ [PCF50606_REG_GPOC3] = 0x00,
841+ [PCF50606_REG_GPOC4] = 0x00,
842+ [PCF50606_REG_GPOC5] = 0x00,
843+};
844+
845+
846Index: u-boot/board/hxd8/config.mk
847===================================================================
848--- /dev/null
849+++ u-boot/board/hxd8/config.mk
850@@ -0,0 +1,27 @@
851+#
852+# (C) Copyright 2002
853+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
854+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
855+#
856+# FIC HXD8 board with S3C2440X (ARM920T) cpu
857+#
858+# see http://www.samsung.com/ for more information on SAMSUNG
859+#
860+
861+CONFIG_USB_DFU_VENDOR=0x1457
862+CONFIG_USB_DFU_PRODUCT=0x511a
863+CONFIG_USB_DFU_REVISION=0x0100
864+
865+#
866+# HXD81v011 or later has 1 bank of 128 MB SDRAM
867+#
868+# 3000'0000 to 3800'0000
869+# we load ourself to 37F8'0000
870+#
871+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
872+# optionally with a ramdisk at 3080'0000
873+#
874+# download area is 3200'0000 or 3300'0000
875+
876+# FIXME: TEXT_BASE = 0x37F80000
877+TEXT_BASE = 0x33F80000
878Index: u-boot/board/hxd8/u-boot.lds
879===================================================================
880--- /dev/null
881+++ u-boot/board/hxd8/u-boot.lds
882@@ -0,0 +1,58 @@
883+/*
884+ * (C) Copyright 2002
885+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
886+ *
887+ * See file CREDITS for list of people who contributed to this
888+ * project.
889+ *
890+ * This program is free software; you can redistribute it and/or
891+ * modify it under the terms of the GNU General Public License as
892+ * published by the Free Software Foundation; either version 2 of
893+ * the License, or (at your option) any later version.
894+ *
895+ * This program is distributed in the hope that it will be useful,
896+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
897+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
898+ * GNU General Public License for more details.
899+ *
900+ * You should have received a copy of the GNU General Public License
901+ * along with this program; if not, write to the Free Software
902+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
903+ * MA 02111-1307 USA
904+ */
905+
906+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
907+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
908+OUTPUT_ARCH(arm)
909+ENTRY(_start)
910+SECTIONS
911+{
912+ . = 0x00000000;
913+
914+ . = ALIGN(4);
915+ .text :
916+ {
917+ cpu/arm920t/start.o (.text)
918+ cpu/arm920t/s3c24x0/nand_read.o (.text)
919+ *(.text)
920+ }
921+
922+ . = ALIGN(4);
923+ .rodata : { *(.rodata) }
924+
925+ . = ALIGN(4);
926+ .data : { *(.data) }
927+
928+ . = ALIGN(4);
929+ .got : { *(.got) }
930+
931+ . = .;
932+ __u_boot_cmd_start = .;
933+ .u_boot_cmd : { *(.u_boot_cmd) }
934+ __u_boot_cmd_end = .;
935+
936+ . = ALIGN(4);
937+ __bss_start = .;
938+ .bss : { *(.bss) }
939+ _end = .;
940+}
941Index: u-boot/board/hxd8/lowlevel_foo.S
942===================================================================
943--- /dev/null
944+++ u-boot/board/hxd8/lowlevel_foo.S
945@@ -0,0 +1,87 @@
946+
947+_start:
948+ b reset
949+undefvec:
950+ b undefvec
951+swivec:
952+ b swivec
953+pabtvec:
954+ b pabtvec
955+dabtvec:
956+ b dabtvec
957+rsvdvec:
958+ b rsvdvec
959+irqvec:
960+ b irqvec
961+fiqvec:
962+ b fiqvec
963+
964+reset:
965+ /*
966+ * set the cpu to SVC32 mode
967+ */
968+ mrs r0,cpsr
969+ bic r0,r0,#0x1f
970+ orr r0,r0,#0xd3
971+ msr cpsr,r0
972+
973+/* turn off the watchdog */
974+#define pWTCON 0x53000000
975+#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
976+#define INTSUBMSK 0x4A00001C
977+#define CLKDIVN 0x4C000014 /* clock divisor register */
978+#define CAMDIVN 0x4C000018
979+
980+ ldr r0, =pWTCON
981+ mov r1, #0x0
982+ str r1, [r0]
983+
984+ mov r1, #0xffffffff
985+ ldr r0, =INTMSK
986+ str r1, [r0]
987+ ldr r1, =0x7ff
988+ ldr r0, =INTSUBMSK
989+ str r1, [r0]
990+
991+ /* FCLK:HCLK:PCLK = 1:3:6 */
992+ ldr r0, =CAMDIVN
993+ mov r1, #0
994+ str r1, [r0]
995+
996+ /* FCLK:HCLK:PCLK = 1:3:6 */
997+ ldr r0, =CLKDIVN
998+ mov r1, #7
999+ str r1, [r0]
1000+
1001+ bl cpu_init_crit
1002+ ldr r0,=TEXT_BASE
1003+ mov pc, r0
1004+
1005+cpu_init_crit:
1006+ /*
1007+ * flush v4 I/D caches
1008+ */
1009+ mov r0, #0
1010+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
1011+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
1012+
1013+ /*
1014+ * disable MMU stuff and caches
1015+ */
1016+ mrc p15, 0, r0, c1, c0, 0
1017+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
1018+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
1019+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
1020+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
1021+ mcr p15, 0, r0, c1, c0, 0
1022+
1023+ /*
1024+ * before relocating, we have to setup RAM timing
1025+ * because memory timing is board-dependend, you will
1026+ * find a lowlevel_init.S in your board directory.
1027+ */
1028+ mov ip, lr
1029+ bl lowlevel_init
1030+ mov lr, ip
1031+ mov pc, lr
1032+
1033Index: u-boot/board/hxd8/lowlevel_foo.lds
1034===================================================================
1035--- /dev/null
1036+++ u-boot/board/hxd8/lowlevel_foo.lds
1037@@ -0,0 +1,56 @@
1038+/*
1039+ * (C) Copyright 2002
1040+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1041+ *
1042+ * See file CREDITS for list of people who contributed to this
1043+ * project.
1044+ *
1045+ * This program is free software; you can redistribute it and/or
1046+ * modify it under the terms of the GNU General Public License as
1047+ * published by the Free Software Foundation; either version 2 of
1048+ * the License, or (at your option) any later version.
1049+ *
1050+ * This program is distributed in the hope that it will be useful,
1051+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1052+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1053+ * GNU General Public License for more details.
1054+ *
1055+ * You should have received a copy of the GNU General Public License
1056+ * along with this program; if not, write to the Free Software
1057+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1058+ * MA 02111-1307 USA
1059+ */
1060+
1061+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1062+OUTPUT_ARCH(arm)
1063+ENTRY(_start)
1064+SECTIONS
1065+{
1066+ . = 0x00000000;
1067+
1068+ . = ALIGN(4);
1069+ .text :
1070+ {
1071+ lowlevel_foo.o (.text)
1072+ *(.text)
1073+ }
1074+
1075+ . = ALIGN(4);
1076+ .rodata : { *(.rodata) }
1077+
1078+ . = ALIGN(4);
1079+ .data : { *(.data) }
1080+
1081+ . = ALIGN(4);
1082+ .got : { *(.got) }
1083+
1084+ . = .;
1085+ __u_boot_cmd_start = .;
1086+ .u_boot_cmd : { *(.u_boot_cmd) }
1087+ __u_boot_cmd_end = .;
1088+
1089+ . = ALIGN(4);
1090+ __bss_start = .;
1091+ .bss : { *(.bss) }
1092+ _end = .;
1093+}
1094Index: u-boot/cpu/arm920t/s3c24x0/nand.c
1095===================================================================
1096--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c
1097+++ u-boot/cpu/arm920t/s3c24x0/nand.c
1098@@ -83,6 +83,59 @@
1099 #define NFDATA __REGb(NF_BASE + oNFDATA)
1100 #define NFSTAT __REGb(NF_BASE + oNFSTAT)
1101
1102+#if defined(CONFIG_HXD8)
1103+static int hxd8_nand_dev_ready(struct mtd_info *mtd)
1104+{
1105+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1106+ u_int32_t val = gpio->GPCDAT;
1107+
1108+ switch (nand_curr_device) {
1109+ case 0:
1110+ return (NFSTAT & 0x01);
1111+ case 1: /* RnB 3 */
1112+ return ((val>>6) & 0x01);
1113+ case 2: /* RnB 4 */
1114+ return ((val>>7) & 0x01);
1115+ case 3: /* RnB 2 */
1116+ return ((val>>5) & 0x01);
1117+ default:
1118+ return 0;
1119+ }
1120+}
1121+
1122+/* 4G Nand flash chip select function */
1123+static void hxd8_nand_select_chip(struct nand_chip *this, int chip)
1124+{
1125+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1126+
1127+ if (chip == 0)
1128+ gpio->GPGDAT &= ~(1 << 1);
1129+ else
1130+ gpio->GPGDAT |= (1 << 1);
1131+
1132+ if (chip == 1)
1133+ gpio->GPADAT &= ~(1 << 15);
1134+ else
1135+ gpio->GPADAT |= (1 << 15);
1136+
1137+ if (chip == 2)
1138+ gpio->GPADAT &= ~(1 << 16);
1139+ else
1140+ gpio->GPADAT |= (1 << 16);
1141+
1142+ if (chip == 3)
1143+ gpio->GPADAT &= ~(1 << 14);
1144+ else
1145+ gpio->GPADAT |= (1 << 14);
1146+
1147+ /* UGLY: ew don't have mtd_info pointer, but know that
1148+ * s3c24xx hwcontrol function does not use it for CLRNCE */
1149+ if (chip == -1)
1150+ this->hwcontrol(NULL, NAND_CTL_CLRNCE);
1151+ else
1152+ this->hwcontrol(NULL, NAND_CTL_SETNCE);
1153+}
1154+#endif
1155
1156 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
1157 {
1158@@ -251,6 +304,11 @@
1159 nand->eccmode = NAND_ECC_SOFT;
1160 #endif
1161
1162+#if defined(CONFIG_HXD8)
1163+ nand->dev_ready = hxd8_nand_dev_ready;
1164+ nand->select_chip = hxd8_nand_select_chip;
1165+#endif
1166+
1167 #ifdef CONFIG_S3C2410_NAND_BBT
1168 nand->options = NAND_USE_FLASH_BBT | NAND_DONT_CREATE_BBT;
1169 #else
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-11 21:56:28 +0000