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-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-gta02.patch1560
1 files changed, 1560 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-gta02.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-gta02.patch
new file mode 100644
index 0000000000..ca54ebeff7
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-gta02.patch
@@ -0,0 +1,1560 @@
1Add support for new GTA02 version of Neo1973
2
3Index: u-boot/Makefile
4===================================================================
5--- u-boot.orig/Makefile
6+++ u-boot/Makefile
7@@ -2038,6 +2038,10 @@
8 sbc2410x_config: unconfig
9 @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
10
11+gta02_config \
12+gta02v1_config : unconfig
13+ @sh board/neo1973/gta02/split_by_variant.sh $@
14+
15 gta01_config \
16 gta01v3_config \
17 gta01bv2_config \
18Index: u-boot/board/neo1973/gta02/Makefile
19===================================================================
20--- /dev/null
21+++ u-boot/board/neo1973/gta02/Makefile
22@@ -0,0 +1,64 @@
23+#
24+# (C) Copyright 2000, 2001, 2002
25+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
26+#
27+# See file CREDITS for list of people who contributed to this
28+# project.
29+#
30+# This program is free software; you can redistribute it and/or
31+# modify it under the terms of the GNU General Public License as
32+# published by the Free Software Foundation; either version 2 of
33+# the License, or (at your option) any later version.
34+#
35+# This program is distributed in the hope that it will be useful,
36+# but WITHOUT ANY WARRANTY; without even the implied warranty of
37+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38+# GNU General Public License for more details.
39+#
40+# You should have received a copy of the GNU General Public License
41+# along with this program; if not, write to the Free Software
42+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43+# MA 02111-1307 USA
44+#
45+
46+include $(TOPDIR)/config.mk
47+
48+LIB = lib$(BOARD).a
49+
50+OBJS := gta02.o pcf50633.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o
51+SOBJS := ../common/lowlevel_init.o
52+
53+.PHONY: all
54+
55+all: $(LIB) lowevel_foo.bin
56+
57+$(LIB): $(OBJS) $(SOBJS)
58+ $(AR) crv $@ $(OBJS) $(SOBJS)
59+
60+lowlevel_foo.o: ../common/lowlevel_foo.S
61+ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
62+ -o lowlevel_foo.o ../common/lowlevel_foo.S
63+
64+lowlevel_foo: lowlevel_foo.o ../common/lowlevel_init.o ../common/lowlevel_foo.lds
65+ $(LD) -T ../common/lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
66+ ../common/lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
67+
68+lowevel_foo.bin: lowlevel_foo
69+ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
70+ lowlevel_foo lowlevel_foo.bin
71+
72+
73+clean:
74+ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o
75+
76+distclean: clean
77+ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin
78+
79+#########################################################################
80+
81+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
82+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
83+
84+-include .depend
85+
86+#########################################################################
87Index: u-boot/board/neo1973/gta02/gta02.c
88===================================================================
89--- /dev/null
90+++ u-boot/board/neo1973/gta02/gta02.c
91@@ -0,0 +1,313 @@
92+/*
93+ * (C) 2006-2007 by OpenMoko, Inc.
94+ * Author: Harald Welte <laforge@openmoko.org>
95+ *
96+ * based on existing S3C2410 startup code in u-boot:
97+ *
98+ * (C) Copyright 2002
99+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
100+ * Marius Groeger <mgroeger@sysgo.de>
101+ *
102+ * (C) Copyright 2002
103+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
104+ *
105+ * See file CREDITS for list of people who contributed to this
106+ * project.
107+ *
108+ * This program is free software; you can redistribute it and/or
109+ * modify it under the terms of the GNU General Public License as
110+ * published by the Free Software Foundation; either version 2 of
111+ * the License, or (at your option) any later version.
112+ *
113+ * This program is distributed in the hope that it will be useful,
114+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
115+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
116+ * GNU General Public License for more details.
117+ *
118+ * You should have received a copy of the GNU General Public License
119+ * along with this program; if not, write to the Free Software
120+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
121+ * MA 02111-1307 USA
122+ */
123+
124+#include <common.h>
125+#include <s3c2440.h>
126+#include <i2c.h>
127+
128+#include "../common/neo1973.h"
129+#include "../common/jbt6k74.h"
130+
131+#include "pcf50633.h"
132+
133+DECLARE_GLOBAL_DATA_PTR;
134+
135+/* That many seconds the power key needs to be pressed to power up */
136+#define POWER_KEY_SECONDS 2
137+
138+#define M_MDIV 0x7f /* Fout = 405.00MHz */
139+#define M_PDIV 0x2
140+#define M_SDIV 0x1
141+
142+#define U_M_MDIV 0x38
143+#define U_M_PDIV 0x2
144+#define U_M_SDIV 0x2
145+
146+unsigned int neo1973_wakeup_cause;
147+extern int nobootdelay;
148+
149+static inline void delay (unsigned long loops)
150+{
151+ __asm__ volatile ("1:\n"
152+ "subs %0, %1, #1\n"
153+ "bne 1b":"=r" (loops):"0" (loops));
154+}
155+
156+/*
157+ * Miscellaneous platform dependent initialisations
158+ */
159+
160+int board_init (void)
161+{
162+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
163+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
164+
165+ /* to reduce PLL lock time, adjust the LOCKTIME register */
166+ clk_power->LOCKTIME = 0xFFFFFF;
167+
168+ /* configure MPLL */
169+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
170+
171+ /* some delay between MPLL and UPLL */
172+ delay (4000);
173+
174+ /* configure UPLL */
175+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
176+
177+ /* some delay between MPLL and UPLL */
178+ delay (8000);
179+
180+ /* set up the I/O ports */
181+#if defined(CONFIG_ARCH_GTA02_v1)
182+ gpio->GPACON = 0x007E1FFF;
183+ gpio->GPADAT |= (1 << 16); /* Set GPA16 to high (nNAND_WP) */
184+
185+ gpio->GPBCON = 0x00155555;
186+ gpio->GPBUP = 0x000007FF;
187+
188+ gpio->GPCCON = 0x55551155;
189+ gpio->GPCUP = 0x0000FFFF;
190+
191+ gpio->GPDCON = 0x55555555;
192+ gpio->GPDUP = 0x0000FFFF;
193+
194+ gpio->GPECON = 0xAAAAAAAA;
195+ gpio->GPEUP = 0x0000FFFF;
196+
197+ gpio->GPFCON = 0x0000AAAA;
198+ gpio->GPFUP = 0x000000FF;
199+
200+ gpio->GPGCON = 0x013DFDFA;
201+ gpio->GPGUP = 0x0000FFFF;
202+
203+ gpio->GPHCON = 0x0028AAAA;
204+ gpio->GPHUP = 0x000007FF;
205+
206+ gpio->GPJCON = 0x1545541;
207+#else
208+#error Please define GTA02 version
209+#endif
210+
211+ /* arch number of SMDK2410-Board */
212+ gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA02;
213+
214+ /* adress of boot parameters */
215+ gd->bd->bi_boot_params = 0x30000100;
216+
217+ icache_enable();
218+ dcache_enable();
219+
220+ return 0;
221+}
222+
223+int board_late_init(void)
224+{
225+ extern unsigned char booted_from_nand;
226+ unsigned char tmp;
227+ char buf[32];
228+ int menu_vote = 0; /* <= 0: no, > 0: yes */
229+ int seconds = 0;
230+
231+ /* Initialize the Power Management Unit with a safe register set */
232+ pcf50633_init();
233+#if 0
234+ /* if there's no other reason, must be regular reset */
235+ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET;
236+
237+ if (!booted_from_nand)
238+ goto woken_by_reset;
239+
240+ /* obtain wake-up reason, save INT1 in environment */
241+ tmp = pcf50606_reg_read(PCF50606_REG_INT1);
242+ sprintf(buf, "0x%02x", tmp);
243+ setenv("pcf50606_int1", buf);
244+
245+ if (tmp & PCF50606_INT1_ALARM) {
246+ /* we've been woken up by RTC alarm, boot */
247+ neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM;
248+ goto continue_boot;
249+ }
250+ if (tmp & PCF50606_INT1_EXTONR) {
251+ /* we've been woken up by charger insert */
252+ neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER;
253+ }
254+
255+ if (tmp & PCF50606_INT1_ONKEYF) {
256+ /* we've been woken up by a falling edge of the onkey */
257+ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY;
258+ }
259+
260+ if (neo1973_wakeup_cause == NEO1973_WAKEUP_CHARGER) {
261+ /* if we still think it was only a charger insert, boot */
262+ goto continue_boot;
263+ }
264+
265+woken_by_reset:
266+
267+ while (neo1973_wakeup_cause == NEO1973_WAKEUP_RESET ||
268+ neo1973_on_key_pressed()) {
269+ if (neo1973_aux_key_pressed())
270+ menu_vote++;
271+ else
272+ menu_vote--;
273+
274+ if (neo1973_new_second())
275+ seconds++;
276+ if (seconds >= POWER_KEY_SECONDS)
277+ goto continue_boot;
278+ }
279+ /* Power off if minimum number of seconds not reached */
280+ neo1973_poweroff();
281+
282+continue_boot:
283+ jbt6k74_init();
284+ jbt6k74_enter_state(JBT_STATE_NORMAL);
285+ jbt6k74_display_onoff(1);
286+#endif
287+
288+ /* issue a short pulse with the vibrator */
289+ neo1973_vibrator(1);
290+ udelay(50000);
291+ neo1973_vibrator(0);
292+
293+ /* switch on the backlight */
294+ neo1973_backlight(1);
295+
296+#if 0
297+ {
298+ /* check if sd card is inserted, and power-up if it is */
299+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
300+ if (!(gpio->GPFDAT & (1 << 5)))
301+ gpio->GPBDAT &= ~(1 << 2);
302+ }
303+
304+ if (menu_vote > 0) {
305+ bootmenu();
306+ nobootdelay = 1;
307+ }
308+#endif
309+
310+ return 0;
311+}
312+
313+int dram_init (void)
314+{
315+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
316+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
317+
318+ return 0;
319+}
320+
321+u_int32_t get_board_rev(void)
322+{
323+#if defined(CONFIG_ARCH_GTA02_v1)
324+ return 0x00000310;
325+#endif
326+}
327+
328+void neo1973_poweroff(void)
329+{
330+ printf("poweroff\n");
331+ udc_disconnect();
332+ pcf50633_reg_write(PCF50633_REG_OOCSHDWN, 0x01);
333+ /* don't return to caller */
334+ while (1) ;
335+}
336+
337+void neo1973_backlight(int on)
338+{
339+ /* FIXME: PMU based implementation */
340+}
341+
342+/* FIXME: shared */
343+void neo1973_vibrator(int on)
344+{
345+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
346+ if (on)
347+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
348+ gpio->GPGDAT |= (1 << 11); /* GPG11 */
349+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
350+ gpio->GPBDAT |= (1 << 10); /* GPB10 */
351+#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1)
352+ gpio->GPBDAT |= (1 << 3); /* GPB3 */
353+#endif
354+ else
355+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
356+ gpio->GPGDAT &= ~(1 << 11); /* GPG11 */
357+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
358+ gpio->GPBDAT &= ~(1 << 10); /* GPB10 */
359+#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1)
360+ gpio->GPBDAT &= ~(1 << 3); /* GPB3 */
361+#endif
362+}
363+
364+int neo1973_new_second(void)
365+{
366+ return pcf50633_reg_read(PCF50633_REG_INT1) & PCF50633_INT1_SECOND;
367+}
368+
369+int neo1973_on_key_pressed(void)
370+{
371+ return !(pcf50633_reg_read(PCF50633_REG_OOCSTAT)
372+ & PCF50633_OOCSTAT_ONKEY);
373+}
374+
375+/* FIXME: shared */
376+int neo1973_aux_key_pressed(void)
377+{
378+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
379+ if (gpio->GPFDAT & (1 << 6))
380+ return 0;
381+ return 1;
382+}
383+
384+/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
385+ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
386+ images: 640*480*2*2 = 1228800 < 1245184. */
387+
388+unsigned int dynpart_size[] = {
389+ CFG_UBOOT_SIZE, CFG_ENV_SIZE, 0x200000, 0xa0000, 0x1fce0000, 0 };
390+char *dynpart_names[] = {
391+ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
392+
393+
394+const char *neo1973_get_charge_status(void)
395+{
396+ /* FIXME */
397+ return "unknown";
398+}
399+
400+int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd)
401+{
402+ /* FIXME */
403+ return 0;
404+}
405Index: u-boot/board/neo1973/gta02/u-boot.lds
406===================================================================
407--- /dev/null
408+++ u-boot/board/neo1973/gta02/u-boot.lds
409@@ -0,0 +1,58 @@
410+/*
411+ * (C) Copyright 2002
412+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
413+ *
414+ * See file CREDITS for list of people who contributed to this
415+ * project.
416+ *
417+ * This program is free software; you can redistribute it and/or
418+ * modify it under the terms of the GNU General Public License as
419+ * published by the Free Software Foundation; either version 2 of
420+ * the License, or (at your option) any later version.
421+ *
422+ * This program is distributed in the hope that it will be useful,
423+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
424+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
425+ * GNU General Public License for more details.
426+ *
427+ * You should have received a copy of the GNU General Public License
428+ * along with this program; if not, write to the Free Software
429+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
430+ * MA 02111-1307 USA
431+ */
432+
433+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
434+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
435+OUTPUT_ARCH(arm)
436+ENTRY(_start)
437+SECTIONS
438+{
439+ . = 0x00000000;
440+
441+ . = ALIGN(4);
442+ .text :
443+ {
444+ cpu/arm920t/start.o (.text)
445+ cpu/arm920t/s3c24x0/nand_read.o (.text)
446+ *(.text)
447+ }
448+
449+ . = ALIGN(4);
450+ .rodata : { *(.rodata) }
451+
452+ . = ALIGN(4);
453+ .data : { *(.data) }
454+
455+ . = ALIGN(4);
456+ .got : { *(.got) }
457+
458+ . = .;
459+ __u_boot_cmd_start = .;
460+ .u_boot_cmd : { *(.u_boot_cmd) }
461+ __u_boot_cmd_end = .;
462+
463+ . = ALIGN(4);
464+ __bss_start = .;
465+ .bss : { *(.bss) }
466+ _end = .;
467+}
468Index: u-boot/include/configs/neo1973_gta02.h
469===================================================================
470--- /dev/null
471+++ u-boot/include/configs/neo1973_gta02.h
472@@ -0,0 +1,276 @@
473+/*
474+ * (C) Copyright 2007 OpenMoko, Inc.
475+ * Author: Harald Welte <laforge@openmoko.org>
476+ *
477+ * Configuation settings for the FIC Neo1973 GTA02 Linux GSM phone
478+ *
479+ * See file CREDITS for list of people who contributed to this
480+ * project.
481+ *
482+ * This program is free software; you can redistribute it and/or
483+ * modify it under the terms of the GNU General Public License as
484+ * published by the Free Software Foundation; either version 2 of
485+ * the License, or (at your option) any later version.
486+ *
487+ * This program is distributed in the hope that it will be useful,
488+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
489+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
490+ * GNU General Public License for more details.
491+ *
492+ * You should have received a copy of the GNU General Public License
493+ * along with this program; if not, write to the Free Software
494+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
495+ * MA 02111-1307 USA
496+ */
497+
498+#ifndef __CONFIG_H
499+#define __CONFIG_H
500+
501+/* we want to be able to start u-boot directly from within NAND flash */
502+#define CONFIG_LL_INIT_NAND_ONLY
503+#define CONFIG_S3C2410_NAND_BOOT 1
504+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
505+
506+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
507+
508+/*
509+ * High Level Configuration Options
510+ * (easy to change)
511+ */
512+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
513+#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC */
514+#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */
515+
516+/* input clock of PLL */
517+#define CONFIG_SYS_CLK_FREQ 12000000/* the GTA02 has this input clock */
518+
519+
520+#define USE_920T_MMU 1
521+#define CONFIG_USE_IRQ 1
522+
523+/*
524+ * Size of malloc() pool
525+ */
526+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024)
527+ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
528+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
529+
530+/*
531+ * Hardware drivers
532+ */
533+
534+/*
535+ * select serial console configuration
536+ */
537+#define CONFIG_SERIAL3 1 /* we use SERIAL 1 on GTA01 */
538+
539+/************************************************************
540+ * RTC
541+ ************************************************************/
542+#define CONFIG_RTC_S3C24X0 1
543+
544+/* allow to overwrite serial and ethaddr */
545+#define CONFIG_ENV_OVERWRITE
546+
547+#define CONFIG_BAUDRATE 115200
548+
549+/***********************************************************
550+ * Command definition
551+ ***********************************************************/
552+#define CONFIG_COMMANDS (\
553+ CFG_CMD_BDI | \
554+ CFG_CMD_LOADS | \
555+ CFG_CMD_LAODB | \
556+ CFG_CMD_IMI | \
557+ CFG_CMD_CACHE | \
558+ CFG_CMD_MEMORY | \
559+ CFG_CMD_ENV | \
560+ /* CFG_CMD_IRQ | */ \
561+ CFG_CMD_BOOTD | \
562+ CFG_CMD_CONSOLE | \
563+ /* CFG_CMD_BMP | */ \
564+ CFG_CMD_ASKENV | \
565+ CFG_CMD_RUN | \
566+ CFG_CMD_ECHO | \
567+ CFG_CMD_I2C | \
568+ CFG_CMD_REGINFO | \
569+ CFG_CMD_IMMAP | \
570+ CFG_CMD_DATE | \
571+ CFG_CMD_AUTOSCRIPT | \
572+ CFG_CMD_BSP | \
573+ CFG_CMD_ELF | \
574+ CFG_CMD_MISC | \
575+ /* CFG_CMD_USB | */ \
576+ CFG_CMD_JFFS2 | \
577+ CFG_CMD_DIAG | \
578+ /* CFG_CMD_HWFLOW | */ \
579+ CFG_CMD_SAVES | \
580+ CFG_CMD_NAND | \
581+ CFG_CMD_PORTIO | \
582+ CFG_CMD_MMC | \
583+ CFG_CMD_FAT | \
584+ CFG_CMD_EXT2 | \
585+ 0)
586+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
587+#include <cmd_confdefs.h>
588+
589+#define CONFIG_BOOTDELAY 3
590+#define CONFIG_BOOTARGS ""
591+#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
592+
593+#define CONFIG_DOS_PARTITION 1
594+
595+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
596+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
597+/* what's this ? it's not used anywhere */
598+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
599+#endif
600+
601+/*
602+ * Miscellaneous configurable options
603+ */
604+#define CFG_LONGHELP /* undef to save memory */
605+#if defined(CONFIG_ARCH_GTA02_v1)
606+#define CFG_PROMPT "GTA02v1 # " /* Monitor Command Prompt */
607+#endif
608+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
609+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
610+#define CFG_MAXARGS 64 /* max number of command args */
611+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
612+
613+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
614+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
615+
616+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
617+
618+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
619+
620+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
621+/* it to wrap 100 times (total 1562500) to get 1 sec. */
622+#define CFG_HZ 1562500
623+
624+/* valid baudrates */
625+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
626+
627+#define CFG_BOOTMENU
628+
629+/*-----------------------------------------------------------------------
630+ * Stack sizes
631+ *
632+ * The stack sizes are set up in start.S using the settings below
633+ */
634+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
635+#ifdef CONFIG_USE_IRQ
636+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
637+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
638+#endif
639+
640+#if 0
641+#define CONFIG_USB_OHCI 1
642+#endif
643+
644+#define CONFIG_USB_DEVICE 1
645+#define CONFIG_USB_TTY 1
646+#define CFG_CONSOLE_IS_IN_ENV 1
647+#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
648+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
649+#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
650+#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc"
651+#define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION
652+#define CONFIG_USBD_DFU 1
653+#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
654+#define CONFIG_USBD_DFU_INTERFACE 2
655+
656+#define CONFIG_EXTRA_ENV_SETTINGS \
657+ "usbtty=cdc_acm\0" \
658+ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8\0" \
659+ ""
660+
661+/*-----------------------------------------------------------------------
662+ * Physical Memory Map
663+ */
664+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
665+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
666+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
667+#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
668+
669+/*-----------------------------------------------------------------------
670+ * FLASH and environment organization
671+ */
672+
673+/* No NOR flash in this device */
674+#define CFG_NO_FLASH 1
675+
676+#define CFG_ENV_IS_IN_NAND 1
677+#define CFG_ENV_SIZE 0x40000 /* 128k Total Size of Environment Sector */
678+#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
679+#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
680+
681+#define NAND_MAX_CHIPS 1
682+#define CFG_NAND_BASE 0x4e000000
683+#define CFG_MAX_NAND_DEVICE 1
684+
685+#define CONFIG_MMC 1
686+#define CFG_MMC_BASE 0xff000000
687+
688+/* EXT2 driver */
689+#define CONFIG_EXT2 1
690+
691+#define CONFIG_FAT 1
692+#define CONFIG_SUPPORT_VFAT
693+
694+#if 1
695+/* JFFS2 driver */
696+#define CONFIG_JFFS2_CMDLINE 1
697+#define CONFIG_JFFS2_NAND 1
698+#define CONFIG_JFFS2_NAND_DEV 0
699+//#define CONFIG_JFFS2_NAND_OFF 0x634000
700+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
701+#endif
702+
703+/* ATAG configuration */
704+#define CONFIG_INITRD_TAG 1
705+#define CONFIG_SETUP_MEMORY_TAGS 1
706+#define CONFIG_CMDLINE_TAG 1
707+#define CONFIG_REVISION_TAG 1
708+#if 0
709+#define CONFIG_SERIAL_TAG 1
710+#endif
711+
712+#define CONFIG_DRIVER_S3C24X0_I2C 1
713+#define CONFIG_HARD_I2C 1
714+#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50633 data sheet */
715+#define CFG_I2C_SLAVE 0x7f
716+
717+/* we have a board_late_init() function */
718+#define BOARD_LATE_INIT 1
719+
720+#if 0
721+#define CONFIG_VIDEO
722+#define CONFIG_VIDEO_S3C2410
723+#define CONFIG_CFB_CONSOLE
724+#define CONFIG_VIDEO_LOGO
725+#define CONFIG_SPLASH_SCREEN
726+#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
727+#define CONFIG_VIDEO_BMP_GZIP
728+#define CONFIG_VGA_AS_SINGLE_DEVICE
729+#define CONFIG_UNZIP
730+
731+#define VIDEO_KBD_INIT_FCT 0
732+#define VIDEO_TSTC_FCT serial_tstc
733+#define VIDEO_GETC_FCT serial_getc
734+
735+#define LCD_VIDEO_ADDR 0x33d00000
736+#endif
737+
738+#define CONFIG_S3C2410_NAND_BBT 1
739+//#define CONFIG_S3C2410_NAND_HWECC 1
740+
741+#define CONFIG_DRIVER_PCF50633 1
742+
743+#define MTDIDS_DEFAULT "nand0=neo1973-nand"
744+#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),-(jffs2)"
745+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "neo1973-nand"
746+#define CONFIG_NAND_DYNPART
747+
748+#endif /* __CONFIG_H */
749Index: u-boot/board/neo1973/gta02/split_by_variant.sh
750===================================================================
751--- /dev/null
752+++ u-boot/board/neo1973/gta02/split_by_variant.sh
753@@ -0,0 +1,37 @@
754+#!/bin/sh
755+# ---------------------------------------------------------
756+# Set the core module defines according to Core Module
757+# ---------------------------------------------------------
758+# ---------------------------------------------------------
759+# Set up the GTA01 type define
760+# ---------------------------------------------------------
761+
762+CFGINC=${obj}include/config.h
763+CFGTMP=${obj}board/neo1973/gta02/config.tmp
764+
765+mkdir -p ${obj}include
766+if [ "$1" == "" ]
767+then
768+ echo "$0:: No parameters - using GTA02Bv1 config"
769+ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC
770+ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP
771+else
772+ case "$1" in
773+ gta02v1_config)
774+ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC
775+ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP
776+ ;;
777+
778+ *)
779+ echo "$0:: Unrecognised config - using GTA02v1 config"
780+ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC
781+ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP
782+ ;;
783+
784+ esac
785+
786+fi
787+# ---------------------------------------------------------
788+# Complete the configuration
789+# ---------------------------------------------------------
790+$MKCONFIG -a neo1973_gta02 arm arm920t gta02 neo1973 s3c24x0
791Index: u-boot/include/pcf50633.h
792===================================================================
793--- /dev/null
794+++ u-boot/include/pcf50633.h
795@@ -0,0 +1,235 @@
796+#ifndef _PCF50633_H
797+#define _PCF50633_H
798+
799+/* Philips PCF50633 Power Managemnt Unit (PMU) driver
800+ * (C) 2006-2007 by OpenMoko, Inc.
801+ * Author: Harald Welte <laforge@openmoko.org>
802+ *
803+ */
804+
805+enum pfc50633_regs {
806+ PCF50633_REG_VERSION = 0x00,
807+ PCF50633_REG_VARIANT = 0x01,
808+ PCF50633_REG_INT1 = 0x02, /* Interrupt Status */
809+ PCF50633_REG_INT2 = 0x03, /* Interrupt Status */
810+ PCF50633_REG_INT3 = 0x04, /* Interrupt Status */
811+ PCF50633_REG_INT4 = 0x05, /* Interrupt Status */
812+ PCF50633_REG_INT5 = 0x06, /* Interrupt Status */
813+ PCF50633_REG_INT1M = 0x07, /* Interrupt Mask */
814+ PCF50633_REG_INT2M = 0x08, /* Interrupt Mask */
815+ PCF50633_REG_INT3M = 0x09, /* Interrupt Mask */
816+ PCF50633_REG_INT4M = 0x0a, /* Interrupt Mask */
817+ PCF50633_REG_INT5M = 0x0b, /* Interrupt Mask */
818+ PCF50633_REG_OOCSHDWN = 0x0c,
819+ PCF50633_REG_OOCWAKE = 0x0d,
820+ PCF50633_REG_OOCTIM1 = 0x0e,
821+ PCF50633_REG_OOCTIM2 = 0x0f,
822+ PCF50633_REG_OOCMODE = 0x10,
823+ PCF50633_REG_OOCCTL = 0x11,
824+ PCF50633_REG_OOCSTAT = 0x12,
825+ PCF50633_REG_GPIOCTL = 0x13,
826+ PCF50633_REG_GPIO1CFG = 0x14,
827+ PCF50633_REG_GPIO2CFG = 0x15,
828+ PCF50633_REG_GPIO3CFG = 0x16,
829+ PCF50633_REG_GPOCFG = 0x17,
830+ PCF50633_REG_BVMCTL = 0x18,
831+ PCF50633_REG_SVMCTL = 0x19,
832+ PCF50633_REG_AUTOOUT = 0x1a,
833+ PCF50633_REG_AUTOENA = 0x1b,
834+ PCF50633_REG_AUTOCTL = 0x1c,
835+ PCF50633_REG_AUTOMXC = 0x1d,
836+ PCF50633_REG_DOWN1OUT = 0x1e,
837+ PCF50633_REG_DOWN1ENA = 0x1f,
838+ PCF50633_REG_DOWN1CTL = 0x20,
839+ PCF50633_REG_DOWN1MXC = 0x21,
840+ PCF50633_REG_DOWN2OUT = 0x22,
841+ PCF50633_REG_DOWN2ENA = 0x23,
842+ PCF50633_REG_DOWN2CTL = 0x24,
843+ PCF50633_REG_DOWN2MXC = 0x25,
844+ PCF50633_REG_MEMLDOOUT = 0x26,
845+ PCF50633_REG_MEMLDOENA = 0x27,
846+ PCF50633_REG_LEDOUT = 0x28,
847+ PCF50633_REG_LEDENA = 0x29,
848+ PCF50633_REG_LEDCTL = 0x2a,
849+ PCF50633_REG_LEDDIM = 0x2b,
850+ /* reserved */
851+ PCF50633_REG_LDO1OUT = 0x2d,
852+ PCF50633_REG_LDO1ENA = 0x2e,
853+ PCF50633_REG_LDO2OUT = 0x2f,
854+ PCF50633_REG_LDO2ENA = 0x30,
855+ PCF50633_REG_LDO3OUT = 0x31,
856+ PCF50633_REG_LDO3ENA = 0x32,
857+ PCF50633_REG_LDO4OUT = 0x33,
858+ PCF50633_REG_LDO4ENA = 0x34,
859+ PCF50633_REG_LDO5OUT = 0x35,
860+ PCF50633_REG_LDO5ENA = 0x36,
861+ PCF50633_REG_LDO6OUT = 0x37,
862+ PCF50633_REG_LDO6ENA = 0x38,
863+ PCF50633_REG_HCLDOOUT = 0x39,
864+ PCF50633_REG_HCLDOENA = 0x3a,
865+ PCF50633_REG_STBYCTL1 = 0x3b,
866+ PCF50633_REG_STBYCTL2 = 0x3c,
867+ PCF50633_REG_DEBPF1 = 0x3d,
868+ PCF50633_REG_DEBPF2 = 0x3e,
869+ PCF50633_REG_DEBPF3 = 0x3f,
870+ PCF50633_REG_HCLDOOVL = 0x40,
871+ PCF50633_REG_DCDCSTAT = 0x41,
872+ PCF50633_REG_LDOSTAT = 0x42,
873+ PCF50633_REG_MBCC1 = 0x43,
874+ PCF50633_REG_MBCC2 = 0x44,
875+ PCF50633_REG_MBCC3 = 0x45,
876+ PCF50633_REG_MBCC4 = 0x46,
877+ PCF50633_REG_MBCC5 = 0x47,
878+ PCF50633_REG_MBCC6 = 0x48,
879+ PCF50633_REG_MBCC7 = 0x49,
880+ PCF50633_REG_MBCC8 = 0x4a,
881+ PCF50633_REG_MBCS1 = 0x4b,
882+ PCF50633_REG_MBCS2 = 0x4c,
883+ PCF50633_REG_MBCS3 = 0x4d,
884+ PCF50633_REG_BBCCTL = 0x4e,
885+ PCF50633_REG_ALMGAIN = 0x4f,
886+ PCF50633_REG_ALMDATA = 0x50,
887+ /* reserved */
888+ PCF50633_REG_ADCC3 = 0x52,
889+ PCF50633_REG_ADCC2 = 0x53,
890+ PCF50633_REG_ADCC1 = 0x54,
891+ PCF50633_REG_ADCS1 = 0x55,
892+ PCF50633_REG_ADCS2 = 0x56,
893+ PCF50633_REG_ADCS3 = 0x57,
894+ /* reserved */
895+ PCF50633_REG_RTCSC = 0x59, /* Second */
896+ PCF50633_REG_RTCMN = 0x5a, /* Minute */
897+ PCF50633_REG_RTCHR = 0x5b, /* Hour */
898+ PCF50633_REG_RTCWD = 0x5c, /* Weekday */
899+ PCF50633_REG_RTCDT = 0x5d, /* Day */
900+ PCF50633_REG_RTCMT = 0x5e, /* Month */
901+ PCF50633_REG_RTCYR = 0x5f, /* Year */
902+ PCF50633_REG_RTCSCA = 0x60, /* Alarm Second */
903+ PCF50633_REG_RTCMNA = 0x61, /* Alarm Minute */
904+ PCF50633_REG_RTCHRA = 0x62, /* Alarm Hour */
905+ PCF50633_REG_RTCWDA = 0x63, /* Alarm Weekday */
906+ PCF50633_REG_RTCDTA = 0x64, /* Alarm Day */
907+ PCF50633_REG_RTCMTA = 0x65, /* Alarm Month */
908+ PCF50633_REG_RTCYRA = 0x66, /* Alarm Year */
909+
910+ PCF50633_REG_MEMBYTE0 = 0x67,
911+ PCF50633_REG_MEMBYTE1 = 0x68,
912+ PCF50633_REG_MEMBYTE2 = 0x69,
913+ PCF50633_REG_MEMBYTE3 = 0x6a,
914+ PCF50633_REG_MEMBYTE4 = 0x6b,
915+ PCF50633_REG_MEMBYTE5 = 0x6c,
916+ PCF50633_REG_MEMBYTE6 = 0x6d,
917+ PCF50633_REG_MEMBYTE7 = 0x6e,
918+ /* reserved */
919+ PCF50633_REG_DCDCPFM = 0x84,
920+ __NUM_PCF50633_REGS
921+};
922+
923+enum pcf50633_reg_int1 {
924+ PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
925+ PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
926+ PCF50633_INT1_USBINS = 0x04, /* USB inserted */
927+ PCF50633_INT1_USBREM = 0x08, /* USB removed */
928+ /* reserved */
929+ PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
930+ PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
931+};
932+
933+enum pcf50633_reg_int2 {
934+ PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
935+ PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
936+ PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
937+ PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
938+ PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
939+ PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
940+ PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
941+ PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
942+};
943+
944+enum pcf50633_reg_int3 {
945+ PCF50633_INT3_BATFULL = 0x01, /* Battery full */
946+ PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
947+ PCF50633_INT3_THLIMON = 0x04,
948+ PCF50633_INT3_THLIMOFF = 0x08,
949+ PCF50633_INT3_USBLIMON = 0x10,
950+ PCF50633_INT3_USBLIMOFF = 0x20,
951+ PCF50633_INT3_ADCRDY = 0x40, /* ADC conversion finished */
952+ PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
953+};
954+
955+enum pcf50633_reg_int4 {
956+ PCF50633_INT4_LOWSYS = 0x01,
957+ PCF50633_INT4_LOWBAT = 0x02,
958+ PCF50633_INT4_HIGHTMP = 0x04,
959+ PCF50633_INT4_AUTOPWRFAIL = 0x08,
960+ PCF50633_INT4_DWN1PWRFAIL = 0x10,
961+ PCF50633_INT4_DWN2PWRFAIL = 0x20,
962+ PCF50633_INT4_LEDPWRFAIL = 0x40,
963+ PCF50633_INT4_LEDOVP = 0x80,
964+};
965+
966+enum pcf50633_reg_int5 {
967+ PCF50633_INT4_LDO1PWRFAIL = 0x01,
968+ PCF50633_INT4_LDO2PWRFAIL = 0x02,
969+ PCF50633_INT4_LDO3PWRFAIL = 0x04,
970+ PCF50633_INT4_LDO4PWRFAIL = 0x08,
971+ PCF50633_INT4_LDO5PWRFAIL = 0x10,
972+ PCF50633_INT4_LDO6PWRFAIL = 0x20,
973+ PCF50633_INT4_HCLDOPWRFAIL = 0x40,
974+ PCF50633_INT4_HCLDOOVL = 0x80,
975+};
976+
977+enum pcf50633_reg_oocwake {
978+ PCF50633_OOCWAKE_ONKEY = 0x01,
979+ PCF50633_OOCWAKE_EXTON1 = 0x02,
980+ PCF50633_OOCWAKE_EXTON2 = 0x04,
981+ PCF50633_OOCWAKE_EXTON3 = 0x08,
982+ PCF50633_OOCWAKE_RTC = 0x10,
983+ /* reserved */
984+ PCF50633_OOCWAKE_USB = 0x40,
985+ PCF50633_OOCWAKE_ADP = 0x80,
986+};
987+
988+enum pcf50633_reg_mbcc1 {
989+ PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
990+ PCF50633_MBCC1_AUTOSTOP = 0x02,
991+ PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
992+ PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
993+ PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
994+ PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
995+ PCF50633_MBCC1_WDTIME_1H = 0x00,
996+ PCF50633_MBCC1_WDTIME_2H = 0x40,
997+ PCF50633_MBCC1_WDTIME_4H = 0x80,
998+ PCF50633_MBCC1_WDTIME_6H = 0xc0,
999+};
1000+#define PCF50633_MBCC1_WDTIME_MASK 0xc0
1001+
1002+enum pcf50633_reg_mbcc2 {
1003+ PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
1004+ PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
1005+ PCF50633_MBCC2_VBATCOND_3V = 0x02,
1006+ PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
1007+ PCF50633_MBCC2_VMAX_4V = 0x00,
1008+ PCF50633_MBCC2_VMAX_4V20 = 0x28,
1009+ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
1010+};
1011+#define PCF50633_MBCC2_VBATCOND_MASK 0x03
1012+#define PCF50633_MBCC2_VMAX_MASK 0x3c
1013+
1014+#define PCF50633_OOCSTAT_ONKEY 0x01
1015+
1016+/* this is to be provided by the board implementation */
1017+extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
1018+
1019+void pcf50633_reg_write(u_int8_t reg, u_int8_t val);
1020+
1021+u_int8_t pcf50633_reg_read(u_int8_t reg);
1022+
1023+void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val);
1024+void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits);
1025+
1026+void pcf50633_init(void);
1027+void pcf50633_usb_maxcurrent(unsigned int ma);
1028+
1029+#endif /* _PCF50633_H */
1030+
1031Index: u-boot/drivers/pcf50633.c
1032===================================================================
1033--- /dev/null
1034+++ u-boot/drivers/pcf50633.c
1035@@ -0,0 +1,142 @@
1036+#include <common.h>
1037+
1038+#ifdef CONFIG_DRIVER_PCF50633
1039+
1040+#include <i2c.h>
1041+#include <pcf50633.h>
1042+#include <asm/atomic.h>
1043+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
1044+
1045+#define PCF50633_I2C_ADDR 0x73
1046+
1047+void __pcf50633_reg_write(u_int8_t reg, u_int8_t val)
1048+{
1049+ i2c_write(PCF50633_I2C_ADDR, reg, 1, &val, 1);
1050+}
1051+
1052+u_int8_t __pcf50633_reg_read(u_int8_t reg)
1053+{
1054+ u_int8_t tmp;
1055+ i2c_read(PCF50633_I2C_ADDR, reg, 1, &tmp, 1);
1056+ return tmp;
1057+}
1058+
1059+void pcf50633_reg_write(u_int8_t reg, u_int8_t val)
1060+{
1061+ unsigned long flags;
1062+
1063+ local_irq_save(flags);
1064+ __pcf50633_reg_write(reg, val);
1065+ local_irq_restore(flags);
1066+}
1067+
1068+u_int8_t pcf50633_reg_read(u_int8_t reg)
1069+{
1070+ unsigned long flags;
1071+ u_int8_t tmp;
1072+
1073+ local_irq_save(flags);
1074+ tmp = __pcf50633_reg_read(reg);
1075+ local_irq_restore(flags);
1076+
1077+ return tmp;
1078+}
1079+
1080+void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val)
1081+{
1082+ unsigned long flags;
1083+ u_int8_t tmp;
1084+
1085+ local_irq_save(flags);
1086+ tmp = __pcf50633_reg_read(reg);
1087+ __pcf50633_reg_write(reg, (val & mask) | (tmp & ~mask));
1088+ local_irq_restore(flags);
1089+}
1090+
1091+void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits)
1092+{
1093+ unsigned long flags;
1094+ u_int8_t tmp;
1095+
1096+ local_irq_save(flags);
1097+ tmp = pcf50633_reg_read(reg);
1098+ pcf50633_reg_write(reg, (tmp & ~bits));
1099+ local_irq_restore(flags);
1100+}
1101+
1102+static const u_int8_t regs_invalid[] = {
1103+ PCF50633_REG_VERSION,
1104+ PCF50633_REG_VARIANT,
1105+ PCF50633_REG_OOCSHDWN,
1106+ PCF50633_REG_INT1,
1107+ PCF50633_REG_INT2,
1108+ PCF50633_REG_INT3,
1109+ PCF50633_REG_INT4,
1110+ PCF50633_REG_INT5,
1111+ PCF50633_REG_OOCSTAT,
1112+ 0x2c,
1113+ PCF50633_REG_DCDCSTAT,
1114+ PCF50633_REG_LDOSTAT,
1115+ PCF50633_REG_MBCS1,
1116+ PCF50633_REG_MBCS2,
1117+ PCF50633_REG_MBCS3,
1118+ PCF50633_REG_ALMDATA,
1119+ 0x51,
1120+ /* 0x55 ... 0x6e: don't write */
1121+ /* 0x6f ... 0x83: reserved */
1122+};
1123+#define PCF50633_LAST_REG 0x55
1124+
1125+static int reg_is_invalid(u_int8_t reg)
1126+{
1127+ int i;
1128+
1129+ /* all registers above 0x55 (ADCS1) except 0x84 */
1130+ if (reg == PCF50633_REG_DCDCPFM)
1131+ return 0;
1132+ if (reg >= 0x55)
1133+ return 1;
1134+
1135+ for (i = 0; i < ARRAY_SIZE(regs_invalid); i++) {
1136+ if (regs_invalid[i] > reg)
1137+ return 0;
1138+ if (regs_invalid[i] == reg)
1139+ return 1;
1140+ }
1141+
1142+ return 0;
1143+}
1144+
1145+
1146+/* initialize PCF50633 register set */
1147+void pcf50633_init(void)
1148+{
1149+ unsigned long flags;
1150+ u_int8_t i;
1151+
1152+ local_irq_save(flags);
1153+ for (i = 0; i < PCF50633_LAST_REG; i++) {
1154+ if (reg_is_invalid(i))
1155+ continue;
1156+ __pcf50633_reg_write(i, pcf50633_initial_regs[i]);
1157+ }
1158+ local_irq_restore(flags);
1159+}
1160+
1161+void pcf50633_usb_maxcurrent(unsigned int ma)
1162+{
1163+ u_int8_t val;
1164+
1165+ if (ma < 100)
1166+ val = 0x03;
1167+ else if (ma < 500)
1168+ val = 0x00;
1169+ else if (ma < 1000)
1170+ val = 0x01;
1171+ else
1172+ val = 0x02;
1173+
1174+ return pcf50633_reg_set_bit_mask(PCF50633_REG_MBCC7, 0x03, val);
1175+}
1176+
1177+#endif /* CONFIG DRIVER_PCF50633 */
1178Index: u-boot/board/neo1973/common/lowlevel_init.S
1179===================================================================
1180--- u-boot.orig/board/neo1973/common/lowlevel_init.S
1181+++ u-boot/board/neo1973/common/lowlevel_init.S
1182@@ -49,7 +49,7 @@
1183 #define WAIT (0x1<<2)
1184 #define UBLB (0x1<<3)
1185
1186-#define B1_BWSCON (DW32)
1187+#define B1_BWSCON (DW16 + WAIT + UBLB)
1188 #define B2_BWSCON (DW16)
1189 #define B3_BWSCON (DW16 + WAIT + UBLB)
1190 #define B4_BWSCON (DW16)
1191@@ -68,9 +68,9 @@
1192
1193 /* BANK1CON */
1194 #define B1_Tacs 0x0 /* 0clk */
1195-#define B1_Tcos 0x0 /* 0clk */
1196-#define B1_Tacc 0x7 /* 14clk */
1197-#define B1_Tcoh 0x0 /* 0clk */
1198+#define B1_Tcos 0x1 /* 1clk */
1199+#define B1_Tacc 0x4 /* 4clk */
1200+#define B1_Tcoh 0x1 /* 1clk */
1201 #define B1_Tah 0x0 /* 0clk */
1202 #define B1_Tacp 0x0
1203 #define B1_PMC 0x0
1204@@ -112,7 +112,7 @@
1205 #if defined (CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1206 #define B6_SCAN 0x1 /* 9bit */
1207 #elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
1208- defined(CONFIG_ARCH_GTA01B_v4)
1209+ defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1)
1210 #define B6_SCAN 0x2 /* 10bit */
1211 #endif
1212
1213@@ -165,6 +165,18 @@
1214 str r1, [r0]
1215 #endif
1216
1217+#if defined(CONFIG_ARCH_GTA02_v1)
1218+ /* enable KEEPACT to make sure PMU keeps us alive */
1219+ ldr r0, =0x56000000 /* GPJ base */
1220+ ldr r1, [r0, #0xd0] /* GPJCON */
1221+ orr r1, r1, #(1 << 6)
1222+ str r1, [r0, #0xd0]
1223+
1224+ ldr r1, [r0, #0xd4] /* GPJDAT */
1225+ orr r1, r1, #(1 << 3)
1226+ str r1, [r0, #0xd4]
1227+#endif
1228+
1229 /* everything is fine now */
1230 mov pc, lr
1231
1232Index: u-boot/board/neo1973/gta02/pcf50633.c
1233===================================================================
1234--- /dev/null
1235+++ u-boot/board/neo1973/gta02/pcf50633.c
1236@@ -0,0 +1,91 @@
1237+
1238+#include <common.h>
1239+#include <pcf50633.h>
1240+
1241+/* initial register set for PCF50633 in Neo1973 GTA02 devices */
1242+const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS] = {
1243+ /* gap */
1244+ [PCF50633_REG_INT1M] = PCF50633_INT1_SECOND,
1245+ [PCF50633_REG_INT2M] = PCF50633_INT2_EXTON3F |
1246+ PCF50633_INT2_EXTON3R |
1247+ PCF50633_INT2_EXTON2F |
1248+ PCF50633_INT2_EXTON2R |
1249+ PCF50633_INT2_EXTON1R |
1250+ PCF50633_INT2_EXTON1F,
1251+ [PCF50633_REG_INT3M] = PCF50633_INT3_ADCRDY,
1252+ [PCF50633_REG_INT4M] = 0x00,
1253+ [PCF50633_REG_INT5M] = 0x00,
1254+
1255+ [PCF50633_REG_OOCWAKE] = 0xd3, /* wake from ONKEY,EXTON!,RTC,USB,ADP */
1256+ [PCF50633_REG_OOCTIM1] = 0xaa, /* debounce 14ms everything */
1257+ [PCF50633_REG_OOCTIM2] = 0x4a,
1258+ [PCF50633_REG_OOCMODE] = 0x55,
1259+ [PCF50633_REG_OOCCTL] = 0x44,
1260+
1261+ [PCF50633_REG_GPIOCTL] = 0x01, /* only GPIO1 is input */
1262+ [PCF50633_REG_GPIO2CFG] = 0x00,
1263+ [PCF50633_REG_GPIO3CFG] = 0x00,
1264+ [PCF50633_REG_GPOCFG] = 0x00,
1265+
1266+ [PCF50633_REG_SVMCTL] = 0x08, /* 3.10V SYS voltage thresh. */
1267+ [PCF50633_REG_BVMCTL] = 0x02, /* 2.80V BAT voltage thresh. */
1268+
1269+ [PCF50633_REG_STBYCTL1] = 0x00,
1270+ [PCF50633_REG_STBYCTL2] = 0x00,
1271+
1272+ [PCF50633_REG_DEBPF1] = 0xff,
1273+ [PCF50633_REG_DEBPF2] = 0xff,
1274+ [PCF50633_REG_DEBPF2] = 0x3f,
1275+
1276+ [PCF50633_REG_AUTOOUT] = 0x6b, /* 3.300V */
1277+ [PCF50633_REG_AUTOENA] = 0x01, /* always on */
1278+ [PCF50633_REG_AUTOCTL] = 0x00, /* automatic up/down operation */
1279+ [PCF50633_REG_AUTOMXC] = 0x0a, /* 400mA at startup FIXME */
1280+
1281+ [PCF50633_REG_DOWN1OUT] = 0x1b, /* 1.3V (0x1b * .025V + 0.625V) */
1282+ [PCF50633_REG_DOWN1ENA] = 0x02, /* enabled if GPIO1 = HIGH */
1283+ [PCF50633_REG_DOWN1CTL] = 0x00, /* no DVM */
1284+ [PCF50633_REG_DOWN1MXC] = 0x22, /* limit to 510mA at startup */
1285+
1286+ [PCF50633_REG_DOWN2OUT] = 0x2f, /* 1.8V (0x2f * .025V + 0.625V) */
1287+ [PCF50633_REG_DOWN2ENA] = 0x02, /* enabled if GPIO1 = HIGH */
1288+ [PCF50633_REG_DOWN2CTL] = 0x00, /* no DVM */
1289+ [PCF50633_REG_DOWN2MXC] = 0x22, /* limit to 510mA at startup */
1290+
1291+ [PCF50633_REG_MEMLDOOUT] = 0x00,
1292+ [PCF50633_REG_MEMLDOENA] = 0x00,
1293+
1294+ [PCF50633_REG_LEDOUT] = 0x2f, /* full backlight power */
1295+ [PCF50633_REG_LEDENA] = 0x02, /* enabled if GPIO1 = HIGH */
1296+ [PCF50633_REG_LEDCTL] = 0x05, /* ovp enabled, ocp 500mA */
1297+ [PCF50633_REG_LEDDIM] = 0x20, /* dimming curve */
1298+
1299+ [PCF50633_REG_LDO1OUT] = 0x04, /* 1.3V (4 * 0.1V + 0.9V) */
1300+ [PCF50633_REG_LDO1ENA] = 0x01, /* always on */
1301+
1302+ [PCF50633_REG_LDO2OUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */
1303+ [PCF50633_REG_LDO2ENA] = 0x02, /* enabled if GPIO1 = HIGH */
1304+
1305+ [PCF50633_REG_LDO3OUT] = 0x15, /* 3.0V (21 * 0.1V + 0.9V) */
1306+ [PCF50633_REG_LDO3ENA] = 0x02, /* enabled if GPIO1 = HIGH */
1307+
1308+ [PCF50633_REG_LDO4ENA] = 0x00,
1309+ [PCF50633_REG_LDO5ENA] = 0x00,
1310+ [PCF50633_REG_LDO6ENA] = 0x00,
1311+
1312+ [PCF50633_REG_HCLDOOUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */
1313+ [PCF50633_REG_HCLDOENA] = 0x00, /* off by default*/
1314+
1315+ [PCF50633_REG_DCDCPFM] = 0x00, /* off by default*/
1316+
1317+ [PCF50633_REG_MBCC1] = 0xe6,
1318+ [PCF50633_REG_MBCC2] = 0x28, /* Vbatconid=2.7V, Vmax=4.20V */
1319+ [PCF50633_REG_MBCC3] = 0x19, /* 25/255 == 98mA pre-charge */
1320+ [PCF50633_REG_MBCC4] = 0xff, /* 255/255 == 1A adapter fast */
1321+ [PCF50633_REG_MBCC5] = 0x7f, /* 127/255 == 500mA usb fast */
1322+ [PCF50633_REG_MBCC6] = 0x00, /* cutoff current 1/32 * Ichg */
1323+ [PCF50633_REG_MBCC7] = 0x00, /* 1.6A max bat curr, USB 100mA */
1324+ [PCF50633_REG_MBCC8] = 0x00,
1325+
1326+ [PCF50633_REG_BBCCTL] = 0x19, /* 3V, 200uA, on */
1327+};
1328Index: u-boot/board/neo1973/gta02/config.mk
1329===================================================================
1330--- /dev/null
1331+++ u-boot/board/neo1973/gta02/config.mk
1332@@ -0,0 +1,32 @@
1333+#
1334+# (C) Copyright 2002
1335+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1336+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
1337+#
1338+# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu
1339+#
1340+# see http://www.samsung.com/ for more information on SAMSUNG
1341+#
1342+
1343+# GTA01v3 has 1 bank of 64 MB SDRAM
1344+# GTA01v4 has 1 bank of 64 MB SDRAM
1345+#
1346+# 3000'0000 to 3400'0000
1347+# we load ourself to 33F8'0000
1348+#
1349+# GTA01Bv2 or later has 1 bank of 128 MB SDRAM
1350+#
1351+# 3000'0000 to 3800'0000
1352+# we load ourself to 37F8'0000
1353+#
1354+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
1355+# optionally with a ramdisk at 3080'0000
1356+#
1357+# download area is 3200'0000 or 3300'0000
1358+
1359+CONFIG_USB_DFU_VENDOR=0x1457
1360+CONFIG_USB_DFU_PRODUCT=0x5119
1361+
1362+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
1363+
1364+TEXT_BASE = 0x33F80000
1365Index: u-boot/drivers/smedia3362.c
1366===================================================================
1367--- /dev/null
1368+++ u-boot/drivers/smedia3362.c
1369@@ -0,0 +1,125 @@
1370+/*
1371+ * (C) Copyright 2007 by OpenMoko, Inc.
1372+ * Author: Harald Welte <laforge@openmoko.org>
1373+ *
1374+ * This program is free software; you can redistribute it and/or
1375+ * modify it under the terms of the GNU General Public License as
1376+ * published by the Free Software Foundation; either version 2 of
1377+ * the License, or (at your option) any later version.
1378+ *
1379+ * This program is distributed in the hope that it will be useful,
1380+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1381+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1382+ * GNU General Public License for more details.
1383+ *
1384+ * You should have received a copy of the GNU General Public License
1385+ * along with this program; if not, write to the Free Software
1386+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1387+ * MA 02111-1307 USA
1388+ */
1389+
1390+#include <common.h>
1391+
1392+#if defined(CONFIG_VIDEO_GLAMO3362)
1393+
1394+#include <video_fb.h>
1395+#include "videomodes.h"
1396+#include <s3c2410.h>
1397+#include "smedia3362.h"
1398+
1399+/*
1400+ * Export Graphic Device
1401+ */
1402+GraphicDevice smi;
1403+
1404+
1405+struct glamo_script {
1406+ u_int16_t reg;
1407+ u_int16_t val;
1408+} __attribute__((packed));
1409+
1410+/* from 'initial glamo 3365 script' */
1411+static struct glamo_script gl3362_init_script[] = {
1412+ /* clock */
1413+ { GLAMO_REG_CLOCK_MEMORY, 0x300a },
1414+ { GLAMO_REG_CLOCK_LCD, 0x10aa },
1415+ { GLAMO_REG_CLOCK_MMC, 0x100a },
1416+ { GLAMO_REG_CLOCK_ISP, 0x32aa },
1417+ { GLAMO_REG_CLOCK_JPEG, 0x100a },
1418+ { GLAMO_REG_CLOCK_3D, 0x302a },
1419+ { GLAMO_REG_CLOCK_2D, 0x302a },
1420+ //{ GLAMO_REG_CLOCK_RISC1, 0x1aaa },
1421+ //{ GLAMO_REG_CLOCK_RISC2, 0x002a },
1422+ { GLAMO_REG_CLOCK_MPEG, 0x3aaa },
1423+ { GLAMO_REG_CLOCK_MPROC, 0x12aa },
1424+ { 0xfffe, 5 },
1425+ { GLAMO_REG_CLOCK_HOST, 0x000d },
1426+ { GLAMO_REG_CLOCK_MEMORY, 0x000a }I,
1427+ { GLAMO_REG_CLOCK_LCD, 0x00ee },
1428+ { GLAMO_REG_CLOCK_MMC, 0x000a },
1429+ { GLAMO_REG_CLOCK_ISP, 0x02aa },
1430+ { GLAMO_REG_CLOCK_JPEG, 0x000a },
1431+ { GLAMO_REG_CLOCK_3D, 0x002a },
1432+ { GLAMO_REG_CLOCK_2D, 0x002a },
1433+ //{ GLAMO_REG_CLOCK_RISC1, 0x0aaa },
1434+ //{ GLAMO_REG_CLOCK_RISC2, 0x002a },
1435+ { GLAMO_REG_CLOCK_MPEG, 0x0aaa },
1436+ { GLAMO_REG_CLOCK_MPROC, 0x02aa },
1437+ { 0xfffe, 5 },
1438+ { GLAMO_REG_PLL_GEN1, 0x061a }, /* PLL1=50MHz, OSCI=32kHz */
1439+ { GLAMO_REG_PLL_GEN3, 0x09c3 }, /* PLL2=80MHz, OSCI=32kHz */
1440+ { 0xfffe, 5 },
1441+ { GLAMO_REG_CLOCK_GEN5_1, 0x18ff },
1442+ { GLAMO_REG_CLOCK_GEN5_2, 0x051f },
1443+ { GLAMO_REG_CLOCK_GEN6, 0x2000 },
1444+ { GLAMO_REG_CLOCK_GEN7, 0x0105 },
1445+ { GLAMO_REG_CLOCK_GEN8, 0x0100 },
1446+ { GLAMO_REG_CLOCK_GEN10, 0x0017 },
1447+ { GLAMO_REG_CLOCK_GEN11, 0x0017 },
1448+
1449+ /* hostbus interface */
1450+ { GLAMO_REG_HOSTBUS(1), 0x0e00 },
1451+ { GLAMO_REG_HOSTBUS(2), 0x07ff },
1452+ { GLAMO_REG_HOSTBUS(4), 0x0080 },
1453+ { GLAMO_REG_HOSTBUS(5), 0x0244 },
1454+ { GLAMO_REG_HOSTBUS(6), 0x0600 },
1455+ { GLAMO_REG_HOSTBUS(12), 0xf00e },
1456+
1457+ /* memory */
1458+ { GLAMO_REG_MEM_TYPE, 0x0874 }, /* VRAM 8Mbyte */
1459+ { GLAMO_REG_MEM_GEN, 0xafaf },
1460+ { GLAMO_REG_MEM_TIMING(1), 0x0108 },
1461+ { GLAMO_REG_MEM_TIMING(2), 0x0010 },
1462+ { GLAMO_REG_MEM_TIMING(3), 0x0000 },
1463+ { GLAMO_REG_MEM_TIMING(4), 0x0000 },
1464+ { GLAMO_REG_MEM_TIMING(5), 0x0000 },
1465+ { GLAMO_REG_MEM_TIMING(6), 0x0000 },
1466+ { GLAMO_REG_MEM_TIMING(7), 0x0000 },
1467+ { GLAMO_REG_MEM_TIMING(8), 0x1002 },
1468+ { GLAMO_REG_MEM_TIMING(9), 0x6006 },
1469+ { GLAMO_REG_MEM_TIMING(10), 0x00ff },
1470+ { GLAMO_REG_MEM_TIMING(11), 0x0001 },
1471+ { GLAMO_REG_MEM_POWER1, 0x0020 },
1472+ { GLAMO_REG_MEM_POWRE2, 0x0000 },
1473+ { GLAMO_REG_MEM_DRAM1, 0x0000 },
1474+ { 0xfffe, 1 },
1475+ { GLAMO_REG_MEM_DRAM1, 0xc100 },
1476+ { GLAMO_REG_MEM_DRAM2, 0x01d6 },
1477+};
1478+
1479+static int glamo3362_init(void)
1480+{
1481+ int i;
1482+
1483+ for (i = 0; i < ARRAY_SIZE(gl3362_init_script); i++) {
1484+ struct glamo_reg *reg = gl3362_init_script[i];
1485+
1486+ if (reg->reg == 0xfffe)
1487+ delay(reg->val);
1488+ else
1489+ gl3362_reg_write(reg->reg, reg->val);
1490+ }
1491+ /* FIXME */
1492+}
1493+
1494+#endif /* CONFIG_VIDEO_GLAMO3362 */
1495Index: u-boot/drivers/Makefile
1496===================================================================
1497--- u-boot.orig/drivers/Makefile
1498+++ u-boot/drivers/Makefile
1499@@ -50,7 +50,7 @@
1500 usbdcore.o usbdfu.o usbdcore_ep0.o usbdcore_omap1510.o usbdcore_s3c2410.o usbtty.o \
1501 videomodes.o w83c553f.o \
1502 ks8695eth.o \
1503- pcf50606.o \
1504+ pcf50606.o pcf50633.o \
1505 pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
1506 rpx_pcmcia.o \
1507 fsl_i2c.o s3c2410_fb.o
1508Index: u-boot/common/cmd_nand.c
1509===================================================================
1510--- u-boot.orig/common/cmd_nand.c
1511+++ u-boot/common/cmd_nand.c
1512@@ -208,8 +208,10 @@
1513 putc('\n');
1514 for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
1515 if (nand_info[i].name)
1516- printf("Device %d: %s, sector size %lu KiB\n",
1517+ printf("Device %d: %s, page size %lu, "
1518+ "sector size %lu KiB\n",
1519 i, nand_info[i].name,
1520+ nand_info[i].oobblock,
1521 nand_info[i].erasesize >> 10);
1522 }
1523 return 0;
1524Index: u-boot/drivers/nand/nand_ids.c
1525===================================================================
1526--- u-boot.orig/drivers/nand/nand_ids.c
1527+++ u-boot/drivers/nand/nand_ids.c
1528@@ -67,7 +67,7 @@
1529
1530 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
1531
1532- {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0},
1533+ //{"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0},
1534
1535 /* These are the new chips with large page size. The pagesize
1536 * and the erasesize is determined from the extended id bytes
1537Index: u-boot/board/neo1973/common/udc.c
1538===================================================================
1539--- u-boot.orig/board/neo1973/common/udc.c
1540+++ u-boot/board/neo1973/common/udc.c
1541@@ -3,6 +3,7 @@
1542 #include <usbdcore.h>
1543 #include <s3c2410.h>
1544 #include <pcf50606.h>
1545+#include <pcf50633.h>
1546
1547 void udc_ctrl(enum usbd_event event, int param)
1548 {
1549@@ -23,6 +24,11 @@
1550 defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
1551 defined(CONFIG_ARCH_GTA01B_v4)
1552 pcf50606_charge_autofast(param);
1553+#elif defined(CONFIG_ARCH_GTA02_v1)
1554+ if (param)
1555+ pcf50633_usb_maxcurrent(500);
1556+ else
1557+ pcf50633_usb_maxcurrent(0);
1558 #endif
1559 break;
1560 default:
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-18 08:30:47 +0000