summaryrefslogtreecommitdiffstats
path: root/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch')
-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch2248
1 files changed, 2248 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch
new file mode 100644
index 0000000000..7c70244b38
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch
@@ -0,0 +1,2248 @@
1This patch adds neo1973 'board' (FIC Neo1973 phone) support to u-boot.
2Specifically, it adds support for the GTA01v3, GTA01v4, GTA01Bv2 and
3GTA01Bv3 hardware revisions.
4
5Signed-off-by: Harald Welte <laforge@openmoko.org>
6
7Index: u-boot/Makefile
8===================================================================
9--- u-boot.orig/Makefile
10+++ u-boot/Makefile
11@@ -2009,6 +2009,14 @@
12 sbc2410x_config: unconfig
13 @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
14
15+gta01_config \
16+gta01v3_config \
17+gta01bv2_config \
18+gta01bv3_config \
19+gta01bv4_config \
20+gta01v4_config : unconfig
21+ @sh board/neo1973/gta01/split_by_variant.sh $@
22+
23 qt2410_config : unconfig
24 @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0
25
26Index: u-boot/common/main.c
27===================================================================
28--- u-boot.orig/common/main.c
29+++ u-boot/common/main.c
30@@ -61,6 +61,7 @@
31 #undef DEBUG_PARSER
32
33 char console_buffer[CFG_CBSIZE]; /* console I/O buffer */
34+int nobootdelay;
35
36 #ifndef CONFIG_CMDLINE_EDITING
37 static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
38@@ -376,7 +377,7 @@
39
40 debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
41
42- if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
43+ if (!nobootdelay && bootdelay >= 0 && s && !abortboot (bootdelay)) {
44 # ifdef CONFIG_AUTOBOOT_KEYED
45 int prev = disable_ctrlc(1); /* disable Control C checking */
46 # endif
47Index: u-boot/drivers/Makefile
48===================================================================
49--- u-boot.orig/drivers/Makefile
50+++ u-boot/drivers/Makefile
51@@ -50,6 +50,7 @@
52 usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
53 videomodes.o w83c553f.o \
54 ks8695eth.o \
55+ pcf50606.o \
56 pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
57 rpx_pcmcia.o \
58 fsl_i2c.o s3c2410_fb.o
59Index: u-boot/drivers/pcf50606.c
60===================================================================
61--- /dev/null
62+++ u-boot/drivers/pcf50606.c
63@@ -0,0 +1,112 @@
64+
65+#include <common.h>
66+
67+#ifdef CONFIG_DRIVER_PCF50606
68+
69+#include <i2c.h>
70+#include <pcf50606.h>
71+#include <asm/atomic.h>
72+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
73+
74+#define PCF50606_I2C_ADDR 0x08
75+
76+void __pcf50606_reg_write(u_int8_t reg, u_int8_t val)
77+{
78+ i2c_write(PCF50606_I2C_ADDR, reg, 1, &val, 1);
79+}
80+
81+u_int8_t __pcf50606_reg_read(u_int8_t reg)
82+{
83+ u_int8_t tmp;
84+ i2c_read(PCF50606_I2C_ADDR, reg, 1, &tmp, 1);
85+ return tmp;
86+}
87+
88+void pcf50606_reg_write(u_int8_t reg, u_int8_t val)
89+{
90+ unsigned long flags;
91+
92+ local_irq_save(flags);
93+ __pcf50606_reg_write(reg, val);
94+ local_irq_restore(flags);
95+}
96+
97+u_int8_t pcf50606_reg_read(u_int8_t reg)
98+{
99+ unsigned long flags;
100+ u_int8_t tmp;
101+
102+ local_irq_save(flags);
103+ tmp = __pcf50606_reg_read(reg);
104+ local_irq_restore(flags);
105+
106+ return tmp;
107+}
108+
109+void pcf50606_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val)
110+{
111+ unsigned long flags;
112+ u_int8_t tmp;
113+
114+ local_irq_save(flags);
115+ tmp = __pcf50606_reg_read(reg);
116+ __pcf50606_reg_write(reg, (val & mask) | (tmp & ~mask));
117+ local_irq_restore(flags);
118+}
119+
120+void pcf50606_reg_clear_bits(u_int8_t reg, u_int8_t bits)
121+{
122+ unsigned long flags;
123+ u_int8_t tmp;
124+
125+ local_irq_save(flags);
126+ tmp = pcf50606_reg_read(reg);
127+ pcf50606_reg_write(reg, (tmp & ~bits));
128+ local_irq_restore(flags);
129+}
130+
131+static const u_int8_t regs_valid[] = {
132+ PCF50606_REG_OOCS, PCF50606_REG_INT1M, PCF50606_REG_INT2M,
133+ PCF50606_REG_INT3M, PCF50606_REG_OOCC1, PCF50606_REG_OOCC2,
134+ PCF50606_REG_PSSC, PCF50606_REG_PWROKM, PCF50606_REG_DCDC1,
135+ PCF50606_REG_DCDC2, PCF50606_REG_DCDC3, PCF50606_REG_DCDC4,
136+ PCF50606_REG_DCDEC1, PCF50606_REG_DCDEC2, PCF50606_REG_DCUDC1,
137+ PCF50606_REG_DCUDC2, PCF50606_REG_IOREGC, PCF50606_REG_D1REGC1,
138+ PCF50606_REG_D2REGC1, PCF50606_REG_D3REGC1, PCF50606_REG_LPREGC1,
139+ PCF50606_REG_LPREGC2, PCF50606_REG_MBCC1, PCF50606_REG_MBCC2,
140+ PCF50606_REG_MBCC3, PCF50606_REG_BBCC, PCF50606_REG_ADCC1,
141+ PCF50606_REG_ADCC2, PCF50606_REG_ACDC1, PCF50606_REG_BVMC,
142+ PCF50606_REG_PWMC1, PCF50606_REG_LEDC1, PCF50606_REG_LEDC2,
143+ PCF50606_REG_GPOC1, PCF50606_REG_GPOC2, PCF50606_REG_GPOC3,
144+ PCF50606_REG_GPOC4, PCF50606_REG_GPOC5,
145+};
146+
147+
148+/* initialize PCF50606 register set */
149+void pcf50606_init(void)
150+{
151+ unsigned long flags;
152+ int i;
153+
154+ local_irq_save(flags);
155+ for (i = 0; i < ARRAY_SIZE(regs_valid); i++) {
156+ __pcf50606_reg_write(regs_valid[i],
157+ pcf50606_initial_regs[regs_valid[i]]);
158+ }
159+ local_irq_restore(flags);
160+}
161+
162+void pcf50606_charge_autofast(int on)
163+{
164+ if (on) {
165+ printf("Enabling automatic fast charge\n");
166+ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1,
167+ PCF50606_MBCC1_AUTOFST,
168+ PCF50606_MBCC1_AUTOFST);
169+ } else {
170+ printf("Disabling fast charge\n");
171+ pcf50606_reg_write(PCF50606_REG_MBCC1, 0x00);
172+ }
173+}
174+
175+#endif /* CONFIG DRIVER_PCF50606 */
176Index: u-boot/include/pcf50606.h
177===================================================================
178--- /dev/null
179+++ u-boot/include/pcf50606.h
180@@ -0,0 +1,273 @@
181+#ifndef _PCF50606_H
182+#define _PCF50606_H
183+
184+/* Philips PCF50606 Power Managemnt Unit (PMU) driver
185+ * (C) 2006-2007 by OpenMoko, Inc.
186+ * Author: Harald Welte <laforge@openmoko.org>
187+ *
188+ */
189+
190+enum pfc50606_regs {
191+ PCF50606_REG_ID = 0x00,
192+ PCF50606_REG_OOCS = 0x01,
193+ PCF50606_REG_INT1 = 0x02, /* Interrupt Status */
194+ PCF50606_REG_INT2 = 0x03, /* Interrupt Status */
195+ PCF50606_REG_INT3 = 0x04, /* Interrupt Status */
196+ PCF50606_REG_INT1M = 0x05, /* Interrupt Mask */
197+ PCF50606_REG_INT2M = 0x06, /* Interrupt Mask */
198+ PCF50606_REG_INT3M = 0x07, /* Interrupt Mask */
199+ PCF50606_REG_OOCC1 = 0x08,
200+ PCF50606_REG_OOCC2 = 0x09,
201+ PCF50606_REG_RTCSC = 0x0a, /* Second */
202+ PCF50606_REG_RTCMN = 0x0b, /* Minute */
203+ PCF50606_REG_RTCHR = 0x0c, /* Hour */
204+ PCF50606_REG_RTCWD = 0x0d, /* Weekday */
205+ PCF50606_REG_RTCDT = 0x0e, /* Day */
206+ PCF50606_REG_RTCMT = 0x0f, /* Month */
207+ PCF50606_REG_RTCYR = 0x10, /* Year */
208+ PCF50606_REG_RTCSCA = 0x11, /* Alarm Second */
209+ PCF50606_REG_RTCMNA = 0x12, /* Alarm Minute */
210+ PCF50606_REG_RTCHRA = 0x13, /* Alarm Hour */
211+ PCF50606_REG_RTCWDA = 0x14, /* Alarm Weekday */
212+ PCF50606_REG_RTCDTA = 0x15, /* Alarm Day */
213+ PCF50606_REG_RTCMTA = 0x16, /* Alarm Month */
214+ PCF50606_REG_RTCYRA = 0x17, /* Alarm Year */
215+ PCF50606_REG_PSSC = 0x18, /* Power sequencing */
216+ PCF50606_REG_PWROKM = 0x19, /* PWROK mask */
217+ PCF50606_REG_PWROKS = 0x1a, /* PWROK status */
218+ PCF50606_REG_DCDC1 = 0x1b,
219+ PCF50606_REG_DCDC2 = 0x1c,
220+ PCF50606_REG_DCDC3 = 0x1d,
221+ PCF50606_REG_DCDC4 = 0x1e,
222+ PCF50606_REG_DCDEC1 = 0x1f,
223+ PCF50606_REG_DCDEC2 = 0x20,
224+ PCF50606_REG_DCUDC1 = 0x21,
225+ PCF50606_REG_DCUDC2 = 0x22,
226+ PCF50606_REG_IOREGC = 0x23,
227+ PCF50606_REG_D1REGC1 = 0x24,
228+ PCF50606_REG_D2REGC1 = 0x25,
229+ PCF50606_REG_D3REGC1 = 0x26,
230+ PCF50606_REG_LPREGC1 = 0x27,
231+ PCF50606_REG_LPREGC2 = 0x28,
232+ PCF50606_REG_MBCC1 = 0x29,
233+ PCF50606_REG_MBCC2 = 0x2a,
234+ PCF50606_REG_MBCC3 = 0x2b,
235+ PCF50606_REG_MBCS1 = 0x2c,
236+ PCF50606_REG_BBCC = 0x2d,
237+ PCF50606_REG_ADCC1 = 0x2e,
238+ PCF50606_REG_ADCC2 = 0x2f,
239+ PCF50606_REG_ADCS1 = 0x30,
240+ PCF50606_REG_ADCS2 = 0x31,
241+ PCF50606_REG_ADCS3 = 0x32,
242+ PCF50606_REG_ACDC1 = 0x33,
243+ PCF50606_REG_BVMC = 0x34,
244+ PCF50606_REG_PWMC1 = 0x35,
245+ PCF50606_REG_LEDC1 = 0x36,
246+ PCF50606_REG_LEDC2 = 0x37,
247+ PCF50606_REG_GPOC1 = 0x38,
248+ PCF50606_REG_GPOC2 = 0x39,
249+ PCF50606_REG_GPOC3 = 0x3a,
250+ PCF50606_REG_GPOC4 = 0x3b,
251+ PCF50606_REG_GPOC5 = 0x3c,
252+ __NUM_PCF50606_REGS
253+};
254+
255+enum pcf50606_reg_oocs {
256+ PFC50606_OOCS_ONKEY = 0x01,
257+ PCF50606_OOCS_EXTON = 0x02,
258+ PCF50606_OOCS_PWROKRST = 0x04,
259+ PCF50606_OOCS_BATOK = 0x08,
260+ PCF50606_OOCS_BACKOK = 0x10,
261+ PCF50606_OOCS_CHGOK = 0x20,
262+ PCF50606_OOCS_TEMPOK = 0x40,
263+ PCF50606_OOCS_WDTEXP = 0x80,
264+};
265+
266+enum pcf50606_reg_oocc1 {
267+ PCF50606_OOCC1_GOSTDBY = 0x01,
268+ PCF50606_OOCC1_TOTRST = 0x02,
269+ PCF50606_OOCC1_CLK32ON = 0x04,
270+ PCF50606_OOCC1_WDTRST = 0x08,
271+ PCF50606_OOCC1_RTCWAK = 0x10,
272+ PCF50606_OOCC1_CHGWAK = 0x20,
273+ PCF50606_OOCC1_EXTONWAK_HIGH = 0x40,
274+ PCF50606_OOCC1_EXTONWAK_LOW = 0x80,
275+ PCF50606_OOCC1_EXTONWAK_NO_WAKEUP = 0x3f,
276+};
277+
278+enum pcf50606_reg_oocc2 {
279+ PCF50606_OOCC2_ONKEYDB_NONE = 0x00,
280+ PCF50606_OOCC2_ONKEYDB_14ms = 0x01,
281+ PCF50606_OOCC2_ONKEYDB_62ms = 0x02,
282+ PCF50606_OOCC2_ONKEYDB_500ms = 0x03,
283+ PCF50606_OOCC2_EXTONDB_NONE = 0x00,
284+ PCF50606_OOCC2_EXTONDB_14ms = 0x04,
285+ PCF50606_OOCC2_EXTONDB_62ms = 0x08,
286+ PCF50606_OOCC2_EXTONDB_500ms = 0x0c,
287+};
288+
289+enum pcf50606_reg_int1 {
290+ PCF50606_INT1_ONKEYR = 0x01, /* ONKEY rising edge */
291+ PCF50606_INT1_ONKEYF = 0x02, /* ONKEY falling edge */
292+ PCF50606_INT1_ONKEY1S = 0x04, /* OMKEY at least 1sec low */
293+ PCF50606_INT1_EXTONR = 0x08, /* EXTON rising edge */
294+ PCF50606_INT1_EXTONF = 0x10, /* EXTON falling edge */
295+ PCF50606_INT1_SECOND = 0x40, /* RTC periodic second interrupt */
296+ PCF50606_INT1_ALARM = 0x80, /* RTC alarm time is reached */
297+};
298+
299+enum pcf50606_reg_int2 {
300+ PCF50606_INT2_CHGINS = 0x01, /* Charger inserted */
301+ PCF50606_INT2_CHGRM = 0x02, /* Charger removed */
302+ PCF50606_INT2_CHGFOK = 0x04, /* Fast charging OK */
303+ PCF50606_INT2_CHGERR = 0x08, /* Error in charging mode */
304+ PCF50606_INT2_CHGFRDY = 0x10, /* Fast charge completed */
305+ PCF50606_INT2_CHGPROT = 0x20, /* Charging protection interrupt */
306+ PCF50606_INT2_CHGWD10S = 0x40, /* Charger watchdig expires in 10s */
307+ PCF50606_INT2_CHGWDEXP = 0x80, /* Charger watchdog expires */
308+};
309+
310+enum pcf50606_reg_int3 {
311+ PCF50606_INT3_ADCRDY = 0x01, /* ADC conversion finished */
312+ PCF50606_INT3_ACDINS = 0x02, /* Accessory inserted */
313+ PCF50606_INT3_ACDREM = 0x04, /* Accessory removed */
314+ PCF50606_INT3_TSCPRES = 0x08, /* Touch screen pressed */
315+ PCF50606_INT3_LOWBAT = 0x40, /* Low battery voltage */
316+ PCF50606_INT3_HIGHTMP = 0x80, /* High temperature */
317+};
318+
319+/* used by PSSC, PWROKM, PWROKS, */
320+enum pcf50606_regu {
321+ PCF50606_REGU_DCD = 0x01, /* DCD in phase 2 */
322+ PCF50606_REGU_DCDE = 0x02, /* DCDE in phase 2 */
323+ PCF50606_REGU_DCUD = 0x04, /* DCDU in phase 2 */
324+ PCF50606_REGU_IO = 0x08, /* IO in phase 2 */
325+ PCF50606_REGU_D1 = 0x10, /* D1 in phase 2 */
326+ PCF50606_REGU_D2 = 0x20, /* D2 in phase 2 */
327+ PCF50606_REGU_D3 = 0x40, /* D3 in phase 2 */
328+ PCF50606_REGU_LP = 0x80, /* LP in phase 2 */
329+};
330+
331+enum pcf50606_reg_dcdc4 {
332+ PCF50606_DCDC4_MODE_AUTO = 0x00,
333+ PCF50606_DCDC4_MODE_PWM = 0x01,
334+ PCF50606_DCDC4_MODE_PCF = 0x02,
335+ PCF50606_DCDC4_OFF_FLOAT = 0x00,
336+ PCF50606_DCDC4_OFF_BYPASS = 0x04,
337+ PCF50606_DCDC4_OFF_PULLDOWN = 0x08,
338+ PCF50606_DCDC4_CURLIM_500mA = 0x00,
339+ PCF50606_DCDC4_CURLIM_750mA = 0x10,
340+ PCF50606_DCDC4_CURLIM_1000mA = 0x20,
341+ PCF50606_DCDC4_CURLIM_1250mA = 0x30,
342+ PCF50606_DCDC4_TOGGLE = 0x40,
343+ PCF50606_DCDC4_REGSEL_DCDC2 = 0x80,
344+};
345+
346+enum pcf50606_reg_dcdec2 {
347+ PCF50606_DCDEC2_MODE_AUTO = 0x00,
348+ PCF50606_DCDEC2_MODE_PWM = 0x01,
349+ PCF50606_DCDEC2_MODE_PCF = 0x02,
350+ PCF50606_DCDEC2_OFF_FLOAT = 0x00,
351+ PCF50606_DCDEC2_OFF_BYPASS = 0x04,
352+};
353+
354+enum pcf50606_reg_dcudc2 {
355+ PCF50606_DCUDC2_MODE_AUTO = 0x00,
356+ PCF50606_DCUDC2_MODE_PWM = 0x01,
357+ PCF50606_DCUDC2_MODE_PCF = 0x02,
358+ PCF50606_DCUDC2_OFF_FLOAT = 0x00,
359+ PCF50606_DCUDC2_OFF_BYPASS = 0x04,
360+};
361+
362+enum pcf50606_reg_adcc1 {
363+ PCF50606_ADCC1_TSCMODACT = 0x01,
364+ PCF50606_ADCC1_TSCMODSTB = 0x02,
365+ PCF50606_ADCC1_TRATSET = 0x04,
366+ PCF50606_ADCC1_NTCSWAPE = 0x08,
367+ PCF50606_ADCC1_NTCSWAOFF = 0x10,
368+ PCF50606_ADCC1_EXTSYNCBREAK = 0x20,
369+ /* reserved */
370+ PCF50606_ADCC1_TSCINT = 0x80,
371+};
372+
373+enum pcf50606_reg_adcc2 {
374+ PCF50606_ADCC2_ADCSTART = 0x01,
375+ /* see enum pcf50606_adcc2_adcmux */
376+ PCF50606_ADCC2_SYNC_NONE = 0x00,
377+ PCF50606_ADCC2_SYNC_TXON = 0x20,
378+ PCF50606_ADCC2_SYNC_PWREN1 = 0x40,
379+ PCF50606_ADCC2_SYNC_PWREN2 = 0x60,
380+ PCF50606_ADCC2_RES_10BIT = 0x00,
381+ PCF50606_ADCC2_RES_8BIT = 0x80,
382+};
383+
384+#define PCF50606_ADCC2_ADCMUX_MASK (0xf << 1)
385+
386+#define ADCMUX_SHIFT 1
387+enum pcf50606_adcc2_adcmux {
388+ PCF50606_ADCMUX_BATVOLT_RES = 0x0 << ADCMUX_SHIFT,
389+ PCF50606_ADCMUX_BATVOLT_SUBTR = 0x1 << ADCMUX_SHIFT,
390+ PCF50606_ADCMUX_ADCIN1_RES = 0x2 << ADCMUX_SHIFT,
391+ PCF50606_ADCMUX_ADCIN1_SUBTR = 0x3 << ADCMUX_SHIFT,
392+ PCF50606_ADCMUX_BATTEMP = 0x4 << ADCMUX_SHIFT,
393+ PCF50606_ADCMUX_ADCIN2 = 0x5 << ADCMUX_SHIFT,
394+ PCF50606_ADCMUX_ADCIN3 = 0x6 << ADCMUX_SHIFT,
395+ PCF50606_ADCMUX_ADCIN3_RATIO = 0x7 << ADCMUX_SHIFT,
396+ PCF50606_ADCMUX_XPOS = 0x8 << ADCMUX_SHIFT,
397+ PCF50606_ADCMUX_YPOS = 0x9 << ADCMUX_SHIFT,
398+ PCF50606_ADCMUX_P1 = 0xa << ADCMUX_SHIFT,
399+ PCF50606_ADCMUX_P2 = 0xb << ADCMUX_SHIFT,
400+ PCF50606_ADCMUX_BATVOLT_ADCIN1 = 0xc << ADCMUX_SHIFT,
401+ PCF50606_ADCMUX_XY_SEQUENCE = 0xe << ADCMUX_SHIFT,
402+ PCF50606_P1_P2_RESISTANCE = 0xf << ADCMUX_SHIFT,
403+};
404+
405+enum pcf50606_adcs2 {
406+ PCF50606_ADCS2_ADCRDY = 0x80,
407+};
408+
409+enum pcf50606_reg_mbcc1 {
410+ PCF50606_MBCC1_CHGAPE = 0x01,
411+ PCF50606_MBCC1_AUTOFST = 0x02,
412+#define PCF50606_MBCC1_CHGMOD_MASK 0x1c
413+#define PCF50606_MBCC1_CHGMOD_SHIFT 2
414+ PCF50606_MBCC1_CHGMOD_QUAL = 0x00,
415+ PCF50606_MBCC1_CHGMOD_PRE = 0x04,
416+ PCF50606_MBCC1_CHGMOD_TRICKLE = 0x08,
417+ PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
418+ PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
419+ PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
420+ PCF50606_MBCC1_CHGMOD_FAST_SW = 0x18,
421+ PCF50606_MBCC1_CHGMOD_IDLE = 0x1c,
422+ PCF50606_MBCC1_DETMOD_LOWCHG = 0x20,
423+ PCF50606_MBCC1_DETMOD_WDRST = 0x40,
424+};
425+
426+enum pcf50606_reg_bvmc {
427+ PCF50606_BVMC_LOWBAT = 0x01,
428+ PCF50606_BVMC_THRSHLD_NULL = 0x00,
429+ PCF50606_BVMC_THRSHLD_2V8 = 0x02,
430+ PCF50606_BVMC_THRSHLD_2V9 = 0x04,
431+ PCF50606_BVMC_THRSHLD_3V = 0x08,
432+ PCF50606_BVMC_THRSHLD_3V1 = 0x08,
433+ PCF50606_BVMC_THRSHLD_3V2 = 0x0a,
434+ PCF50606_BVMC_THRSHLD_3V3 = 0x0c,
435+ PCF50606_BVMC_THRSHLD_3V4 = 0x0e,
436+ PCF50606_BVMC_DISDB = 0x10,
437+};
438+
439+/* this is to be provided by the board implementation */
440+extern const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS];
441+
442+void pcf50606_reg_write(u_int8_t reg, u_int8_t val);
443+
444+u_int8_t pcf50606_reg_read(u_int8_t reg);
445+
446+void pcf50606_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val);
447+void pcf50606_reg_clear_bits(u_int8_t reg, u_int8_t bits);
448+
449+void pcf50606_init(void);
450+void pcf50606_charge_autofast(int on);
451+
452+#endif /* _PCF50606_H */
453+
454Index: u-boot/board/neo1973/common/cmd_neo1973.c
455===================================================================
456--- /dev/null
457+++ u-boot/board/neo1973/common/cmd_neo1973.c
458@@ -0,0 +1,99 @@
459+/*
460+ * (C) Copyright 2006 by OpenMoko, Inc.
461+ * Author: Harald Welte <laforge@openmoko.org>
462+ *
463+ * See file CREDITS for list of people who contributed to this
464+ * project.
465+ *
466+ * This program is free software; you can redistribute it and/or
467+ * modify it under the terms of the GNU General Public License as
468+ * published by the Free Software Foundation; either version 2 of
469+ * the License, or (at your option) any later version.
470+ *
471+ * This program is distributed in the hope that it will be useful,
472+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
473+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
474+ * GNU General Public License for more details.
475+ *
476+ * You should have received a copy of the GNU General Public License
477+ * along with this program; if not, write to the Free Software
478+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
479+ * MA 02111-1307 USA
480+ */
481+
482+/*
483+ * Boot support
484+ */
485+#include <common.h>
486+#include <command.h>
487+#include <net.h> /* for print_IPaddr */
488+#include <s3c2410.h>
489+
490+#include "neo1973.h"
491+
492+DECLARE_GLOBAL_DATA_PTR;
493+
494+#if (CONFIG_COMMANDS & CFG_CMD_BDI)
495+
496+int do_neo1973 ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
497+{
498+ int i;
499+
500+ if (!strcmp(argv[1], "info")) {
501+ printf("FIC Neo1973 Hardware Revision 0x%04x\n", get_board_rev());
502+ } else if (!strcmp(argv[1], "power-off")) {
503+ neo1973_poweroff();
504+ } else if (!strcmp(argv[1], "charger") || !strcmp(argv[1], "charge")) {
505+ if (argc < 3)
506+ goto out_help;
507+ if (!strcmp(argv[2], "status") || !strcmp(argv[2], "state")) {
508+ printf("%s\n", neo1973_get_charge_status());
509+ } else if (!strcmp(argv[2], "autofast")) {
510+ neo1973_set_charge_mode(NEO1973_CHGCMD_AUTOFAST);
511+ } else if (!strcmp(argv[2], "!autofast")) {
512+ neo1973_set_charge_mode(NEO1973_CHGCMD_NO_AUTOFAST);
513+ } else if (!strcmp(argv[2], "off")) {
514+ neo1973_set_charge_mode(NEO1973_CHGCMD_OFF);
515+ } else if (!strcmp(argv[2], "fast")) {
516+ neo1973_set_charge_mode(NEO1973_CHGCMD_FAST);
517+ } else
518+ goto out_help;
519+ } else if (!strcmp(argv[1], "backlight")) {
520+ if (argc < 3)
521+ goto out_help;
522+ if (!strcmp(argv[2], "on"))
523+ neo1973_backlight(1);
524+ else
525+ neo1973_backlight(0);
526+ } else if (!strcmp(argv[1], "vibrator")) {
527+ if (argc < 3)
528+ goto out_help;
529+ if (!strcmp(argv[2], "on"))
530+ neo1973_vibrator(1);
531+ else
532+ neo1973_vibrator(0);
533+ } else {
534+out_help:
535+ printf("Usage:\n%s\n", cmdtp->usage);
536+ return 1;
537+ }
538+
539+ return 0;
540+}
541+
542+/* -------------------------------------------------------------------- */
543+
544+U_BOOT_CMD(
545+ neo1973, 4, 1, do_neo1973,
546+ "neo1973 - phone specific commands\n",
547+ "neo1973 info - display phone informantion\n"
548+ "neo1973 power-off - switch off the phone\n"
549+ "neo1973 charger status - display charger status\n"
550+ "neo1973 charger autofast - enable automatic fast (500mA) charging\n"
551+ "neo1973 charger !autofast - disable automatic fast (500mA) charging\n"
552+ "neo1973 charger fast - enable fast (500mA) charging\n"
553+ "neo1973 charger off - disable charging\n"
554+ "neo1973 backlight (on|off) - switch backlight on or off\n"
555+ "neo1973 vibrator (on|off) - switch vibrator on or off\n"
556+);
557+#endif /* CFG_CMD_BDI */
558Index: u-boot/board/neo1973/common/jbt6k74.c
559===================================================================
560--- /dev/null
561+++ u-boot/board/neo1973/common/jbt6k74.c
562@@ -0,0 +1,420 @@
563+/* u-boot driver for the tpo JBT6K74-AS LCM ASIC
564+ *
565+ * Copyright (C) 2006-2007 by OpenMoko, Inc.
566+ * Author: Harald Welte <laforge@openmoko.org>
567+ * All rights reserved.
568+ *
569+ * This program is free software; you can redistribute it and/or
570+ * modify it under the terms of the GNU General Public License as
571+ * published by the Free Software Foundation; either version 2 of
572+ * the License, or (at your option) any later version.
573+ *
574+ * This program is distributed in the hope that it will be useful,
575+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
576+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
577+ * GNU General Public License for more details.
578+ *
579+ * You should have received a copy of the GNU General Public License
580+ * along with this program; if not, write to the Free Software
581+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
582+ * MA 02111-1307 USA
583+ *
584+ */
585+#include <common.h>
586+#include <spi.h>
587+#include <video_fb.h>
588+#include <asm/errno.h>
589+#include <s3c2410.h>
590+#include "jbt6k74.h"
591+
592+#if 0
593+#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args);
594+#define DEBUGPC(x, args...) printf(x, ## args);
595+#else
596+#define DEBUGP(x, args...) do { } while (0)
597+#define DEBUGPC(x, args...) do { } while (0)
598+#endif
599+
600+
601+enum jbt_register {
602+ JBT_REG_SLEEP_IN = 0x10,
603+ JBT_REG_SLEEP_OUT = 0x11,
604+
605+ JBT_REG_DISPLAY_OFF = 0x28,
606+ JBT_REG_DISPLAY_ON = 0x29,
607+
608+ JBT_REG_RGB_FORMAT = 0x3a,
609+ JBT_REG_QUAD_RATE = 0x3b,
610+
611+ JBT_REG_POWER_ON_OFF = 0xb0,
612+ JBT_REG_BOOSTER_OP = 0xb1,
613+ JBT_REG_BOOSTER_MODE = 0xb2,
614+ JBT_REG_BOOSTER_FREQ = 0xb3,
615+ JBT_REG_OPAMP_SYSCLK = 0xb4,
616+ JBT_REG_VSC_VOLTAGE = 0xb5,
617+ JBT_REG_VCOM_VOLTAGE = 0xb6,
618+ JBT_REG_EXT_DISPL = 0xb7,
619+ JBT_REG_OUTPUT_CONTROL = 0xb8,
620+ JBT_REG_DCCLK_DCEV = 0xb9,
621+ JBT_REG_DISPLAY_MODE1 = 0xba,
622+ JBT_REG_DISPLAY_MODE2 = 0xbb,
623+ JBT_REG_DISPLAY_MODE = 0xbc,
624+ JBT_REG_ASW_SLEW = 0xbd,
625+ JBT_REG_DUMMY_DISPLAY = 0xbe,
626+ JBT_REG_DRIVE_SYSTEM = 0xbf,
627+
628+ JBT_REG_SLEEP_OUT_FR_A = 0xc0,
629+ JBT_REG_SLEEP_OUT_FR_B = 0xc1,
630+ JBT_REG_SLEEP_OUT_FR_C = 0xc2,
631+ JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
632+ JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
633+ JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
634+ JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
635+
636+ JBT_REG_GAMMA1_FINE_1 = 0xc7,
637+ JBT_REG_GAMMA1_FINE_2 = 0xc8,
638+ JBT_REG_GAMMA1_INCLINATION = 0xc9,
639+ JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
640+
641+ JBT_REG_BLANK_CONTROL = 0xcf,
642+ JBT_REG_BLANK_TH_TV = 0xd0,
643+ JBT_REG_CKV_ON_OFF = 0xd1,
644+ JBT_REG_CKV_1_2 = 0xd2,
645+ JBT_REG_OEV_TIMING = 0xd3,
646+ JBT_REG_ASW_TIMING_1 = 0xd4,
647+ JBT_REG_ASW_TIMING_2 = 0xd5,
648+
649+ JBT_REG_HCLOCK_VGA = 0xec,
650+ JBT_REG_HCLOCK_QVGA = 0xed,
651+
652+};
653+
654+static const char *jbt_state_names[] = {
655+ [JBT_STATE_DEEP_STANDBY] = "deep-standby",
656+ [JBT_STATE_SLEEP] = "sleep",
657+ [JBT_STATE_NORMAL] = "normal",
658+};
659+
660+#define GTA01_SCLK (1 << 7) /* GPG7 */
661+#define GTA01_MOSI (1 << 6) /* GPG6 */
662+#define GTA01_MISO (1 << 5) /* GPG5 */
663+#define GTA01_CS (1 << 3) /* GPG3 */
664+
665+#define SPI_READ ((immr->GPGDAT & GTA01_MISO) != 0)
666+
667+#define SPI_CS(bit) if (bit) gpio->GPGDAT |= GTA01_CS; \
668+ else gpio->GPGDAT &= ~GTA01_CS
669+
670+#define SPI_SDA(bit) if (bit) gpio->GPGDAT |= GTA01_MOSI; \
671+ else gpio->GPGDAT &= ~GTA01_MOSI
672+
673+#define SPI_SCL(bit) if (bit) gpio->GPGDAT |= GTA01_SCLK; \
674+ else gpio->GPGDAT &= ~GTA01_SCLK
675+
676+/* 150uS minimum clock cycle, we have two of this plus our other
677+ * instructions */
678+#define SPI_DELAY udelay(100) /* 200uS */
679+
680+
681+#define JBT_TX_BUF_SIZE
682+struct jbt_info {
683+ enum jbt_state state;
684+ u_int16_t tx_buf[4];
685+ struct spi_device *spi_dev;
686+};
687+
688+static struct jbt_info _jbt, *jbt = &_jbt;
689+
690+static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout)
691+{
692+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
693+ u_int16_t tmpdout = 0;
694+ int i, j;
695+
696+ DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n",
697+ *(uint *)dout, wordnum, bitlen);
698+
699+ SPI_CS(0);
700+
701+ for (i = 0; i < wordnum; i ++) {
702+ tmpdout = dout[i];
703+
704+ for (j = 0; j < bitlen; j++) {
705+ SPI_SCL(0);
706+ if (tmpdout & (1 << bitlen-1)) {
707+ SPI_SDA(1);
708+ DEBUGPC("1");
709+ } else {
710+ SPI_SDA(0);
711+ DEBUGPC("0");
712+ }
713+ SPI_DELAY;
714+ SPI_SCL(1);
715+ SPI_DELAY;
716+ tmpdout <<= 1;
717+ }
718+ DEBUGPC(" ");
719+ }
720+ DEBUGPC("\n");
721+
722+ SPI_CS(1);
723+
724+ return 0;
725+}
726+
727+#define JBT_COMMAND 0x000
728+#define JBT_DATA 0x100
729+
730+static int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg)
731+{
732+ int rc;
733+
734+ jbt->tx_buf[0] = JBT_COMMAND | reg;
735+
736+ rc = jbt_spi_xfer(1, 9, jbt->tx_buf);
737+
738+ return rc;
739+}
740+
741+
742+static int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data)
743+{
744+ int rc;
745+
746+ jbt->tx_buf[0] = JBT_COMMAND | reg;
747+ jbt->tx_buf[1] = JBT_DATA | data;
748+
749+ rc = jbt_spi_xfer(2, 9, jbt->tx_buf);
750+
751+ return rc;
752+}
753+
754+static int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data)
755+{
756+ int rc;
757+
758+ jbt->tx_buf[0] = JBT_COMMAND | reg;
759+ jbt->tx_buf[1] = JBT_DATA | (data >> 8);
760+ jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
761+
762+ rc = jbt_spi_xfer(3, 9, jbt->tx_buf);
763+
764+ return rc;
765+}
766+
767+static int jbt_init_regs(struct jbt_info *jbt)
768+{
769+ int rc;
770+
771+ DEBUGP("entering\n");
772+
773+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
774+ rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
775+ rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
776+ rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
777+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
778+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
779+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
780+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
781+ rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
782+ rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
783+ rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
784+ rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
785+ rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
786+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x02);
787+ rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
788+
789+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
790+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
791+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
792+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
793+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
794+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
795+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
796+
797+ rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
798+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
799+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
800+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
801+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
802+
803+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
804+ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
805+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
806+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
807+
808+ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
809+ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
810+
811+ rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
812+ rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
813+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
814+
815+#if 0
816+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
817+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
818+#endif
819+
820+ return rc;
821+}
822+
823+static int standby_to_sleep(struct jbt_info *jbt)
824+{
825+ int rc;
826+
827+ DEBUGP("entering\n");
828+
829+ /* three times command zero */
830+ rc = jbt_reg_write_nodata(jbt, 0x00);
831+ udelay(1000);
832+ rc = jbt_reg_write_nodata(jbt, 0x00);
833+ udelay(1000);
834+ rc = jbt_reg_write_nodata(jbt, 0x00);
835+ udelay(1000);
836+
837+ /* deep standby out */
838+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
839+
840+ return rc;
841+}
842+
843+static int sleep_to_normal(struct jbt_info *jbt)
844+{
845+ int rc;
846+ DEBUGP("entering\n");
847+
848+ /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
849+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
850+
851+ /* Quad mode off */
852+ rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
853+
854+ /* AVDD on, XVDD on */
855+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
856+
857+ /* Output control */
858+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
859+
860+ /* Sleep mode off */
861+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
862+
863+ /* initialize register set */
864+ rc |= jbt_init_regs(jbt);
865+ return rc;
866+}
867+
868+static int normal_to_sleep(struct jbt_info *jbt)
869+{
870+ int rc;
871+ DEBUGP("entering\n");
872+
873+ rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
874+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
875+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
876+
877+ return rc;
878+}
879+
880+static int sleep_to_standby(struct jbt_info *jbt)
881+{
882+ DEBUGP("entering\n");
883+ return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
884+}
885+
886+/* frontend function */
887+int jbt6k74_enter_state(enum jbt_state new_state)
888+{
889+ int rc = -EINVAL;
890+
891+ DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state);
892+
893+ switch (jbt->state) {
894+ case JBT_STATE_DEEP_STANDBY:
895+ switch (new_state) {
896+ case JBT_STATE_DEEP_STANDBY:
897+ rc = 0;
898+ break;
899+ case JBT_STATE_SLEEP:
900+ rc = standby_to_sleep(jbt);
901+ break;
902+ case JBT_STATE_NORMAL:
903+ /* first transition into sleep */
904+ rc = standby_to_sleep(jbt);
905+ /* then transition into normal */
906+ rc |= sleep_to_normal(jbt);
907+ break;
908+ }
909+ break;
910+ case JBT_STATE_SLEEP:
911+ switch (new_state) {
912+ case JBT_STATE_SLEEP:
913+ rc = 0;
914+ break;
915+ case JBT_STATE_DEEP_STANDBY:
916+ rc = sleep_to_standby(jbt);
917+ break;
918+ case JBT_STATE_NORMAL:
919+ rc = sleep_to_normal(jbt);
920+ break;
921+ }
922+ break;
923+ case JBT_STATE_NORMAL:
924+ switch (new_state) {
925+ case JBT_STATE_NORMAL:
926+ rc = 0;
927+ break;
928+ case JBT_STATE_DEEP_STANDBY:
929+ /* first transition into sleep */
930+ rc = normal_to_sleep(jbt);
931+ /* then transition into deep standby */
932+ rc |= sleep_to_standby(jbt);
933+ break;
934+ case JBT_STATE_SLEEP:
935+ rc = normal_to_sleep(jbt);
936+ break;
937+ }
938+ break;
939+ }
940+
941+ return rc;
942+}
943+
944+int jbt6k74_display_onoff(int on)
945+{
946+ DEBUGP("entering\n");
947+ if (on)
948+ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
949+ else
950+ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
951+}
952+
953+int jbt6k74_init(void)
954+{
955+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
956+
957+ /* initialize SPI for GPIO bitbang */
958+ gpio->GPGCON &= 0xffff033f;
959+ gpio->GPGCON |= 0x00005440;
960+
961+ /* get LCM out of reset */
962+ gpio->GPCDAT |= (1 << 6);
963+
964+ /* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms
965+ * seems unreliable with later LCM batches, increasing to 90ms */
966+ udelay(90000);
967+
968+ return 0;
969+}
970+
971+void board_video_init(GraphicDevice *pGD)
972+{
973+ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
974+
975+ lcd->LCDCON1 = 0x00000178; /* CLKVAL=1, BPPMODE=16bpp, TFT, ENVID=0 */
976+
977+ lcd->LCDCON2 = 0x019fc3c1;
978+ lcd->LCDCON3 = 0x0039df67;
979+ lcd->LCDCON4 = 0x00000007;
980+ lcd->LCDCON5 = 0x0001cf09;
981+ lcd->LPCSEL = 0x00000000;
982+}
983Index: u-boot/board/neo1973/common/jbt6k74.h
984===================================================================
985--- /dev/null
986+++ u-boot/board/neo1973/common/jbt6k74.h
987@@ -0,0 +1,14 @@
988+#ifndef _JBT6K74_H
989+#define _JBT6K74_H
990+
991+enum jbt_state {
992+ JBT_STATE_DEEP_STANDBY,
993+ JBT_STATE_SLEEP,
994+ JBT_STATE_NORMAL,
995+};
996+
997+int jbt6k74_init(void);
998+int jbt6k74_display_onoff(int on);
999+int jbt6k74_enter_state(enum jbt_state new_state);
1000+
1001+#endif
1002Index: u-boot/board/neo1973/common/lowlevel_init.S
1003===================================================================
1004--- /dev/null
1005+++ u-boot/board/neo1973/common/lowlevel_init.S
1006@@ -0,0 +1,187 @@
1007+/*
1008+ * Memory Setup stuff - taken from blob memsetup.S
1009+ *
1010+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
1011+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
1012+ *
1013+ * Modified for the FIC Neo1973 GTA01 by Harald Welte <laforge@openmoko.org>
1014+ *
1015+ * See file CREDITS for list of people who contributed to this
1016+ * project.
1017+ *
1018+ * This program is free software; you can redistribute it and/or
1019+ * modify it under the terms of the GNU General Public License as
1020+ * published by the Free Software Foundation; either version 2 of
1021+ * the License, or (at your option) any later version.
1022+ *
1023+ * This program is distributed in the hope that it will be useful,
1024+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1025+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1026+ * GNU General Public License for more details.
1027+ *
1028+ * You should have received a copy of the GNU General Public License
1029+ * along with this program; if not, write to the Free Software
1030+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1031+ * MA 02111-1307 USA
1032+ */
1033+
1034+
1035+#include <config.h>
1036+#include <version.h>
1037+
1038+
1039+/* some parameters for the board */
1040+
1041+/*
1042+ *
1043+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
1044+ *
1045+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
1046+ *
1047+ */
1048+
1049+#define BWSCON 0x48000000
1050+
1051+/* BWSCON */
1052+#define DW8 (0x0)
1053+#define DW16 (0x1)
1054+#define DW32 (0x2)
1055+#define WAIT (0x1<<2)
1056+#define UBLB (0x1<<3)
1057+
1058+#define B1_BWSCON (DW32)
1059+#define B2_BWSCON (DW16)
1060+#define B3_BWSCON (DW16 + WAIT + UBLB)
1061+#define B4_BWSCON (DW16)
1062+#define B5_BWSCON (DW16)
1063+#define B6_BWSCON (DW32)
1064+#define B7_BWSCON (DW32)
1065+
1066+/* BANK0CON */
1067+#define B0_Tacs 0x0 /* 0clk */
1068+#define B0_Tcos 0x0 /* 0clk */
1069+#define B0_Tacc 0x7 /* 14clk */
1070+#define B0_Tcoh 0x0 /* 0clk */
1071+#define B0_Tah 0x0 /* 0clk */
1072+#define B0_Tacp 0x0
1073+#define B0_PMC 0x0 /* normal */
1074+
1075+/* BANK1CON */
1076+#define B1_Tacs 0x0 /* 0clk */
1077+#define B1_Tcos 0x0 /* 0clk */
1078+#define B1_Tacc 0x7 /* 14clk */
1079+#define B1_Tcoh 0x0 /* 0clk */
1080+#define B1_Tah 0x0 /* 0clk */
1081+#define B1_Tacp 0x0
1082+#define B1_PMC 0x0
1083+
1084+#define B2_Tacs 0x0
1085+#define B2_Tcos 0x0
1086+#define B2_Tacc 0x7
1087+#define B2_Tcoh 0x0
1088+#define B2_Tah 0x0
1089+#define B2_Tacp 0x0
1090+#define B2_PMC 0x0
1091+
1092+#define B3_Tacs 0x0 /* 0clk */
1093+#define B3_Tcos 0x3 /* 4clk */
1094+#define B3_Tacc 0x7 /* 14clk */
1095+#define B3_Tcoh 0x1 /* 1clk */
1096+#define B3_Tah 0x0 /* 0clk */
1097+#define B3_Tacp 0x3 /* 6clk */
1098+#define B3_PMC 0x0 /* normal */
1099+
1100+#define B4_Tacs 0x0 /* 0clk */
1101+#define B4_Tcos 0x0 /* 0clk */
1102+#define B4_Tacc 0x7 /* 14clk */
1103+#define B4_Tcoh 0x0 /* 0clk */
1104+#define B4_Tah 0x0 /* 0clk */
1105+#define B4_Tacp 0x0
1106+#define B4_PMC 0x0 /* normal */
1107+
1108+#define B5_Tacs 0x0 /* 0clk */
1109+#define B5_Tcos 0x0 /* 0clk */
1110+#define B5_Tacc 0x7 /* 14clk */
1111+#define B5_Tcoh 0x0 /* 0clk */
1112+#define B5_Tah 0x0 /* 0clk */
1113+#define B5_Tacp 0x0
1114+#define B5_PMC 0x0 /* normal */
1115+
1116+#define B6_MT 0x3 /* SDRAM */
1117+#define B6_Trcd 0x1 /* 3clk */
1118+#if defined (CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1119+#define B6_SCAN 0x1 /* 9bit */
1120+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
1121+ defined(CONFIG_ARCH_GTA01B_v4)
1122+#define B6_SCAN 0x2 /* 10bit */
1123+#endif
1124+
1125+#define B7_MT 0x3 /* SDRAM */
1126+#define B7_Trcd 0x1 /* 3clk */
1127+#define B7_SCAN 0x2 /* 10bit */
1128+
1129+/* REFRESH parameter */
1130+#define REFEN 0x1 /* Refresh enable */
1131+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
1132+#define Trp 0x1 /* 3clk */
1133+#define Trc 0x3 /* 7clk */
1134+#define Tchr 0x2 /* 3clk */
1135+//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
1136+#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */
1137+/**************************************/
1138+
1139+_TEXT_BASE:
1140+ .word TEXT_BASE
1141+
1142+.globl lowlevel_init
1143+lowlevel_init:
1144+ /* memory control configuration */
1145+ /* make r0 relative the current location so that it */
1146+ /* reads SMRDATA out of FLASH rather than memory ! */
1147+ adr r0, SMRDATA
1148+ ldr r1, =BWSCON /* Bus Width Status Controller */
1149+ add r2, r0, #13*4
1150+0:
1151+ ldr r3, [r0], #4
1152+ str r3, [r1], #4
1153+ cmp r2, r0
1154+ bne 0b
1155+
1156+ /* setup asynchronous bus mode */
1157+ mrc p15, 0, r1 ,c1 ,c0, 0
1158+ orr r1, r1, #0xc0000000
1159+ mcr p15, 0, r1, c1, c0, 0
1160+
1161+#if defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1162+ /* switch on power for NAND */
1163+ ldr r0, =0x56000010 /* GPBCON */
1164+ ldr r1, [r0]
1165+ orr r1, r1, #0x10
1166+ str r1, [r0]
1167+
1168+ ldr r0, =0x56000014 /* GPBDAT */
1169+ ldr r1, [r0]
1170+ orr r1, r1, #(1 <<2)
1171+ str r1, [r0]
1172+#endif
1173+
1174+ /* everything is fine now */
1175+ mov pc, lr
1176+
1177+ .ltorg
1178+/* the literal pools origin */
1179+
1180+SMRDATA:
1181+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
1182+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
1183+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
1184+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
1185+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
1186+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
1187+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
1188+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
1189+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
1190+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
1191+ .word 0xb2
1192+ .word 0x30
1193+ .word 0x30
1194Index: u-boot/board/neo1973/gta01/Makefile
1195===================================================================
1196--- /dev/null
1197+++ u-boot/board/neo1973/gta01/Makefile
1198@@ -0,0 +1,47 @@
1199+#
1200+# (C) Copyright 2000, 2001, 2002
1201+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1202+#
1203+# See file CREDITS for list of people who contributed to this
1204+# project.
1205+#
1206+# This program is free software; you can redistribute it and/or
1207+# modify it under the terms of the GNU General Public License as
1208+# published by the Free Software Foundation; either version 2 of
1209+# the License, or (at your option) any later version.
1210+#
1211+# This program is distributed in the hope that it will be useful,
1212+# but WITHOUT ANY WARRANTY; without even the implied warranty of
1213+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1214+# GNU General Public License for more details.
1215+#
1216+# You should have received a copy of the GNU General Public License
1217+# along with this program; if not, write to the Free Software
1218+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1219+# MA 02111-1307 USA
1220+#
1221+
1222+include $(TOPDIR)/config.mk
1223+
1224+LIB = lib$(BOARD).a
1225+
1226+OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o
1227+SOBJS := ../common/lowlevel_init.o
1228+
1229+$(LIB): $(OBJS) $(SOBJS)
1230+ $(AR) crv $@ $(OBJS) $(SOBJS)
1231+
1232+clean:
1233+ rm -f $(SOBJS) $(OBJS)
1234+
1235+distclean: clean
1236+ rm -f $(LIB) core *.bak .depend
1237+
1238+#########################################################################
1239+
1240+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
1241+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
1242+
1243+-include .depend
1244+
1245+#########################################################################
1246Index: u-boot/board/neo1973/gta01/config.mk
1247===================================================================
1248--- /dev/null
1249+++ u-boot/board/neo1973/gta01/config.mk
1250@@ -0,0 +1,34 @@
1251+#
1252+# (C) Copyright 2002
1253+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1254+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
1255+#
1256+# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu
1257+#
1258+# see http://www.samsung.com/ for more information on SAMSUNG
1259+#
1260+
1261+# GTA01v3 has 1 bank of 64 MB SDRAM
1262+# GTA01v4 has 1 bank of 64 MB SDRAM
1263+#
1264+# 3000'0000 to 3400'0000
1265+# we load ourself to 33F8'0000
1266+#
1267+# GTA01Bv2 or later has 1 bank of 128 MB SDRAM
1268+#
1269+# 3000'0000 to 3800'0000
1270+# we load ourself to 37F8'0000
1271+#
1272+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
1273+# optionally with a ramdisk at 3080'0000
1274+#
1275+# download area is 3200'0000 or 3300'0000
1276+
1277+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
1278+
1279+ifeq ($(GTA01_BIG_RAM),y)
1280+# FIXME: TEXT_BASE = 0x37F80000
1281+TEXT_BASE = 0x33F80000
1282+else
1283+TEXT_BASE = 0x33F80000
1284+endif
1285Index: u-boot/board/neo1973/gta01/gta01.c
1286===================================================================
1287--- /dev/null
1288+++ u-boot/board/neo1973/gta01/gta01.c
1289@@ -0,0 +1,422 @@
1290+/*
1291+ * (C) 2006 by OpenMoko, Inc.
1292+ * Author: Harald Welte <laforge@openmoko.org>
1293+ *
1294+ * based on existing S3C2410 startup code in u-boot:
1295+ *
1296+ * (C) Copyright 2002
1297+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
1298+ * Marius Groeger <mgroeger@sysgo.de>
1299+ *
1300+ * (C) Copyright 2002
1301+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
1302+ *
1303+ * See file CREDITS for list of people who contributed to this
1304+ * project.
1305+ *
1306+ * This program is free software; you can redistribute it and/or
1307+ * modify it under the terms of the GNU General Public License as
1308+ * published by the Free Software Foundation; either version 2 of
1309+ * the License, or (at your option) any later version.
1310+ *
1311+ * This program is distributed in the hope that it will be useful,
1312+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1313+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1314+ * GNU General Public License for more details.
1315+ *
1316+ * You should have received a copy of the GNU General Public License
1317+ * along with this program; if not, write to the Free Software
1318+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1319+ * MA 02111-1307 USA
1320+ */
1321+
1322+#include <common.h>
1323+#include <s3c2410.h>
1324+#include <i2c.h>
1325+
1326+#include "pcf50606.h"
1327+
1328+#include "../common/neo1973.h"
1329+#include "../common/jbt6k74.h"
1330+
1331+DECLARE_GLOBAL_DATA_PTR;
1332+
1333+/* That many seconds the power key needs to be pressed to power up */
1334+#define POWER_KEY_SECONDS 2
1335+
1336+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1337+//#define M_MDIV 0xA1 /* Fout = 202.8MHz */
1338+//#define M_PDIV 0x3
1339+//#define M_SDIV 0x1
1340+#define M_MDIV 0x90 /* Fout = 202.8MHz */
1341+#define M_PDIV 0x7
1342+#define M_SDIV 0x0
1343+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1344+/* In case the debug board is attached, we cannot go beyond 200 MHz */
1345+#if 0
1346+#define M_MDIV 0x7d /* Fout = 266MHz */
1347+#define M_PDIV 0x1
1348+#define M_SDIV 0x1
1349+#else
1350+#define M_MDIV 0x90 /* Fout = 202.8MHz */
1351+#define M_PDIV 0x7
1352+#define M_SDIV 0x0
1353+#endif
1354+#elif defined(CONFIG_ARCH_GTA01B_v4)
1355+/* This board doesn't have bus lines at teh debug port, and we can go to 266 */
1356+#define M_MDIV 0x7d /* Fout = 266MHz */
1357+#define M_PDIV 0x1
1358+#define M_SDIV 0x1
1359+#else
1360+#error Please define GTA01 revision
1361+#endif
1362+
1363+#define U_M_MDIV 0x78
1364+#define U_M_PDIV 0x2
1365+#define U_M_SDIV 0x3
1366+
1367+unsigned int neo1973_wakeup_cause;
1368+extern int nobootdelay;
1369+
1370+static inline void delay (unsigned long loops)
1371+{
1372+ __asm__ volatile ("1:\n"
1373+ "subs %0, %1, #1\n"
1374+ "bne 1b":"=r" (loops):"0" (loops));
1375+}
1376+
1377+/*
1378+ * Miscellaneous platform dependent initialisations
1379+ */
1380+
1381+int board_init (void)
1382+{
1383+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1384+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1385+
1386+ /* to reduce PLL lock time, adjust the LOCKTIME register */
1387+ clk_power->LOCKTIME = 0xFFFFFF;
1388+
1389+ /* configure MPLL */
1390+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
1391+
1392+ /* some delay between MPLL and UPLL */
1393+ delay (4000);
1394+
1395+ /* configure UPLL */
1396+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
1397+
1398+ /* some delay between MPLL and UPLL */
1399+ delay (8000);
1400+
1401+ /* set up the I/O ports */
1402+#if defined(CONFIG_ARCH_GTA01_v3)
1403+ gpio->GPACON = 0x007FFFFF;
1404+
1405+ gpio->GPBCON = 0x00005055;
1406+ gpio->GPBUP = 0x000007FF;
1407+
1408+ gpio->GPCCON = 0xAAAA12A8;
1409+ gpio->GPCUP = 0x0000FFFF;
1410+
1411+ gpio->GPDCON = 0xAAAAAAAA;
1412+ gpio->GPDUP = 0x0000FFFF;
1413+
1414+ gpio->GPECON = 0xAAAAAAAA;
1415+ gpio->GPEUP = 0x0000FFFF;
1416+
1417+ gpio->GPFCON = 0x00002AA9;
1418+ gpio->GPFUP = 0x000000FF;
1419+
1420+ gpio->GPGCON = 0xA846F0C0;
1421+ gpio->GPGUP = 0x0000AFEF;
1422+
1423+ gpio->GPHCON = 0x0008FAAA;
1424+ gpio->GPHUP = 0x000007FF;
1425+#elif defined(CONFIG_ARCH_GTA01_v4)
1426+ gpio->GPACON = 0x005E47FF;
1427+
1428+ gpio->GPBCON = 0x00045015;
1429+ gpio->GPBUP = 0x000007FF;
1430+ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (Flash power-up) */
1431+
1432+ gpio->GPCCON = 0xAAAA12A9;
1433+ gpio->GPCUP = 0x0000FFFF;
1434+
1435+ gpio->GPDCON = 0xAAAAAAAA;
1436+ gpio->GPDUP = 0x0000FFFF;
1437+
1438+ gpio->GPECON = 0xA02AAAAA;
1439+ gpio->GPEUP = 0x0000FFFF;
1440+
1441+ gpio->GPFCON = 0x0000aa09;
1442+ gpio->GPFUP = 0x000000FF;
1443+
1444+ gpio->GPGCON = 0xFF40F0C1;
1445+ gpio->GPGUP = 0x0000AFEF;
1446+
1447+ gpio->GPHCON = 0x0000FAAA;
1448+ gpio->GPHUP = 0x000007FF;
1449+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1450+ gpio->GPACON = 0x005E4FFF;
1451+
1452+ gpio->GPBCON = 0x00145415;
1453+ gpio->GPBUP = 0x000007FF;
1454+ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (Flash power-up) */
1455+
1456+ gpio->GPCCON = 0xAAAA12A9;
1457+ gpio->GPCUP = 0x0000FFFF;
1458+
1459+ gpio->GPDCON = 0xAAAAAAAA;
1460+ gpio->GPDUP = 0x0000FFFF;
1461+
1462+ gpio->GPECON = 0xA02AAAAA;
1463+ gpio->GPEUP = 0x0000FFFF;
1464+
1465+ gpio->GPFCON = 0x0000aa19;
1466+ gpio->GPFUP = 0x000000FF;
1467+ gpio->GPFDAT |= 0x4; /* Set GBF2 to high (nGSM_EN) */
1468+
1469+ gpio->GPGCON = 0xFF40F0C1;
1470+ gpio->GPGUP = 0x0000AFEF;
1471+
1472+ gpio->GPHCON = 0x0000FAAA;
1473+ gpio->GPHUP = 0x000007FF;
1474+#elif defined(CONFIG_ARCH_GTA01B_v4)
1475+ gpio->GPACON = 0x0005E0FFF;
1476+ gpio->GPADAT |= (1 << 16); /* Set GPA16 to high (nNAND_WP) */
1477+
1478+ gpio->GPBCON = 0x00045455;
1479+ gpio->GPBUP = 0x000007FF;
1480+ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (SD power down) */
1481+
1482+ gpio->GPCCON = 0xAAAA12A9;
1483+ gpio->GPCUP = 0x0000FFFF;
1484+
1485+ gpio->GPDCON = 0xAAAAAAAA;
1486+ gpio->GPDUP = 0x0000FFFF;
1487+
1488+ gpio->GPECON = 0xAAAAAAAA;
1489+ gpio->GPEUP = 0x0000FFFF;
1490+
1491+ gpio->GPFCON = 0x0000aa99;
1492+ gpio->GPFUP = 0x000000FF;
1493+ gpio->GPFDAT |= 0x4; /* Set GBF2 to high (nGSM_EN) */
1494+
1495+ gpio->GPGCON = 0xFF14F0F8;
1496+ gpio->GPGUP = 0x0000AFEF;
1497+
1498+ gpio->GPHCON = 0x0000FAAA;
1499+ gpio->GPHUP = 0x000007FF;
1500+#else
1501+#error Please define GTA01 version
1502+#endif
1503+
1504+ /* arch number of SMDK2410-Board */
1505+ gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA01;
1506+
1507+ /* adress of boot parameters */
1508+ gd->bd->bi_boot_params = 0x30000100;
1509+
1510+ icache_enable();
1511+ dcache_enable();
1512+
1513+ return 0;
1514+}
1515+
1516+int board_late_init(void)
1517+{
1518+ unsigned char tmp;
1519+ char buf[32];
1520+
1521+ /* Initialize the Power Management Unit with a safe register set */
1522+ pcf50606_init();
1523+
1524+ /* obtain wake-up reason, save INT1 in environment */
1525+ tmp = pcf50606_reg_read(PCF50606_REG_INT1);
1526+ sprintf(buf, "0x%02x", tmp);
1527+ setenv("pcf50606_int1", buf);
1528+
1529+ if (tmp & PCF50606_INT1_ALARM) {
1530+ /* we've been woken up by RTC alarm or charger insert, boot */
1531+ neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM;
1532+ goto continue_boot;
1533+ }
1534+ if (tmp & PCF50606_INT1_EXTONR) {
1535+ neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER;
1536+ }
1537+
1538+ if (tmp & PCF50606_INT1_ONKEYF) {
1539+ int seconds = 0;
1540+ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY;
1541+ /* we've been woken up by a falling edge of the onkey */
1542+
1543+ /* we can't just setenv(bootdelay,-1) because that would
1544+ * accidentially become permanent if the user does saveenv */
1545+ if (neo1973_911_key_pressed())
1546+ nobootdelay = 1;
1547+
1548+ while (1) {
1549+ u_int8_t int1, oocs;
1550+
1551+ oocs = pcf50606_reg_read(PCF50606_REG_OOCS);
1552+ if (oocs & PFC50606_OOCS_ONKEY)
1553+ break;
1554+
1555+ int1 = pcf50606_reg_read(PCF50606_REG_INT1);
1556+ if (int1 & PCF50606_INT1_SECOND)
1557+ seconds++;
1558+
1559+ if (seconds >= POWER_KEY_SECONDS)
1560+ goto continue_boot;
1561+ }
1562+ /* Power off if minimum number of seconds not reached */
1563+ neo1973_poweroff();
1564+ }
1565+
1566+ /* if there's no other reason, must be regular reset */
1567+ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET;
1568+
1569+continue_boot:
1570+ jbt6k74_init();
1571+ jbt6k74_enter_state(JBT_STATE_NORMAL);
1572+ jbt6k74_display_onoff(1);
1573+
1574+ /* issue a short pulse with the vibrator */
1575+ neo1973_vibrator(1);
1576+ udelay(50000);
1577+ neo1973_vibrator(0);
1578+
1579+ /* switch on the backlight */
1580+ neo1973_backlight(1);
1581+
1582+#if defined(CONFIG_ARCH_GTA01B_v4)
1583+ {
1584+ /* check if sd card is inserted, and power-up if it is */
1585+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1586+ if (!(gpio->GPFDAT & (1 << 5)))
1587+ gpio->GPBDAT &= ~(1 << 2);
1588+ }
1589+#endif
1590+
1591+ return 0;
1592+}
1593+
1594+int dram_init (void)
1595+{
1596+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
1597+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
1598+
1599+ return 0;
1600+}
1601+
1602+u_int32_t get_board_rev(void)
1603+{
1604+#if defined(CONFIG_ARCH_GTA01_v3)
1605+ return 0x00000130;
1606+#elif defined(CONFIG_ARCH_GTA01_v4)
1607+ return 0x00000140;
1608+#elif defined(CONFIG_ARCH_GTA01B_v2)
1609+ return 0x00000220;
1610+#elif defined(CONFIG_ARCH_GTA01B_v3)
1611+ return 0x00000230;
1612+#elif defined(CONFIG_ARCH_GTA01B_v4)
1613+ return 0x00000240;
1614+#endif
1615+}
1616+
1617+void neo1973_poweroff(void)
1618+{
1619+ serial_printf("poweroff\n");
1620+ udc_disconnect();
1621+ pcf50606_reg_write(PCF50606_REG_OOCC1, PCF50606_OOCC1_GOSTDBY);
1622+ /* don't return to caller */
1623+ while (1) ;
1624+}
1625+
1626+void neo1973_backlight(int on)
1627+{
1628+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1629+ if (on)
1630+ gpio->GPBDAT |= 0x01;
1631+ else
1632+ gpio->GPBDAT &= ~0x01;
1633+}
1634+
1635+void neo1973_vibrator(int on)
1636+{
1637+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1638+ if (on)
1639+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1640+ gpio->GPGDAT |= (1 << 11); /* GPG11 */
1641+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1642+ gpio->GPBDAT |= (1 << 10); /* GPB10 */
1643+#elif defined(CONFIG_ARCH_GTA01B_v4)
1644+ gpio->GPBDAT |= (1 << 3); /* GPB3 */
1645+#endif
1646+ else
1647+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1648+ gpio->GPGDAT &= ~(1 << 11); /* GPG11 */
1649+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1650+ gpio->GPBDAT &= ~(1 << 10); /* GPB10 */
1651+#elif defined(CONFIG_ARCH_GTA01B_v4)
1652+ gpio->GPBDAT &= ~(1 << 3); /* GPB3 */
1653+#endif
1654+}
1655+
1656+int neo1973_911_key_pressed(void)
1657+{
1658+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1659+ if (gpio->GPFDAT & (1 << 6))
1660+ return 0;
1661+ return 1;
1662+}
1663+
1664+static const char *chgstate_names[] = {
1665+ [PCF50606_MBCC1_CHGMOD_QUAL] = "qualification",
1666+ [PCF50606_MBCC1_CHGMOD_PRE] = "pre",
1667+ [PCF50606_MBCC1_CHGMOD_TRICKLE] = "trickle",
1668+ [PCF50606_MBCC1_CHGMOD_FAST_CCCV] = "fast_cccv",
1669+ [PCF50606_MBCC1_CHGMOD_FAST_NOCC] = "fast_nocc",
1670+ [PCF50606_MBCC1_CHGMOD_FAST_NOCV] = "fast_nocv",
1671+ [PCF50606_MBCC1_CHGMOD_FAST_SW] = "fast_switch",
1672+ [PCF50606_MBCC1_CHGMOD_IDLE] = "idle",
1673+};
1674+
1675+const char *neo1973_get_charge_status(void)
1676+{
1677+ u_int8_t mbcc1 = pcf50606_reg_read(PCF50606_REG_MBCC1);
1678+ u_int8_t chgmod = (mbcc1 & PCF50606_MBCC1_CHGMOD_MASK);
1679+ return chgstate_names[chgmod];
1680+}
1681+
1682+int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd)
1683+{
1684+ switch (cmd) {
1685+ case NEO1973_CHGCMD_NONE:
1686+ break;
1687+ case NEO1973_CHGCMD_AUTOFAST:
1688+ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1,
1689+ PCF50606_MBCC1_AUTOFST,
1690+ PCF50606_MBCC1_AUTOFST);
1691+ break;
1692+ case NEO1973_CHGCMD_NO_AUTOFAST:
1693+ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1,
1694+ PCF50606_MBCC1_AUTOFST, 0);
1695+ break;
1696+ case NEO1973_CHGCMD_OFF:
1697+ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1,
1698+ PCF50606_MBCC1_CHGMOD_MASK,
1699+ PCF50606_MBCC1_CHGMOD_IDLE);
1700+ break;
1701+
1702+ case NEO1973_CHGCMD_FAST:
1703+ case NEO1973_CHGCMD_FASTER:
1704+ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1,
1705+ PCF50606_MBCC1_CHGMOD_MASK,
1706+ PCF50606_MBCC1_CHGMOD_FAST_CCCV);
1707+ break;
1708+ }
1709+ return 0;
1710+}
1711+
1712Index: u-boot/board/neo1973/gta01/pcf50606.c
1713===================================================================
1714--- /dev/null
1715+++ u-boot/board/neo1973/gta01/pcf50606.c
1716@@ -0,0 +1,100 @@
1717+
1718+#include <common.h>
1719+#include <pcf50606.h>
1720+
1721+/* initial register set for PCF50606 in Neo1973 devices */
1722+const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = {
1723+ [PCF50606_REG_OOCS] = 0x00,
1724+ /* gap */
1725+ [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND,
1726+ [PCF50606_REG_INT2M] = 0x00,
1727+ [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES,
1728+ [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK |
1729+ PCF50606_OOCC1_CHGWAK |
1730+ PCF50606_OOCC1_EXTONWAK_HIGH,
1731+ [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms |
1732+ PCF50606_OOCC2_EXTONDB_14ms,
1733+ /* gap */
1734+ [PCF50606_REG_PSSC] = 0x00,
1735+ [PCF50606_REG_PWROKM] = 0x00,
1736+ /* gap */
1737+#if defined(CONFIG_ARCH_GTA01B_v2)
1738+ [PCF50606_REG_DCDC1] = 0x1e, /* GL_3V3: off */
1739+#elif defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
1740+ [PCF50606_REG_DCDC1] = 0x18, /* GL_1V5: off */
1741+#endif
1742+ [PCF50606_REG_DCDC2] = 0x00,
1743+ [PCF50606_REG_DCDC3] = 0x00,
1744+ [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */
1745+
1746+ [PCF50606_REG_DCDEC1] = 0xe8, /* IO_3V3: on */
1747+ [PCF50606_REG_DCDEC2] = 0x00,
1748+
1749+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1750+ [PCF50606_REG_DCUDC1] = 0xe3, /* CORE_1V8: 1.8V */
1751+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1752+ [PCF50606_REG_DCUDC1] = 0xe4, /* CORE_1V8: 2.1V */
1753+#elif defined(CONFIG_ARCH_GTA01B_v4)
1754+ [PCF50606_REG_DCUDC1] = 0xc4, /* CORE_1V8: 2.1V if PWREN2 = HIGH */
1755+#endif
1756+ [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */
1757+
1758+#if defined(CONFIG_ARCH_GTA01_v3)
1759+ [PCF50606_REG_IOREGC] = 0x13, /* VTCXO_2V8: off */
1760+#elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \
1761+ defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
1762+ //see internal bug 94 [PCF50606_REG_IOREGC] = 0x18, /* CODEC_3V3: off */
1763+ [PCF50606_REG_IOREGC] = 0xf8, /* CODEC_3V3: on */
1764+#endif
1765+
1766+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
1767+ [PCF50606_REG_D1REGC1] = 0x15, /* VRF_3V: off */
1768+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
1769+ defined(CONFIG_ARCH_GTA01B_v4)
1770+ [PCF50606_REG_D1REGC1] = 0x16, /* BT_3V15: off */
1771+#endif
1772+
1773+#if defined(CONFIG_ARCH_GTA01_v3)
1774+ [PCF50606_REG_D2REGC1] = 0xf8, /* SD_3V3: on */
1775+#elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \
1776+ defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
1777+ [PCF50606_REG_D2REGC1] = 0x10, /* GL_2V5: off */
1778+#endif
1779+
1780+#if defined(CONFIG_ARCH_GTA01_v3)
1781+ [PCF50606_REG_D3REGC1] = 0x18, /* CODEC_3V3: off */
1782+#elif defined(CONFIG_ARCH_GTA01_v4)
1783+ [PCF50606_REG_D3REGC1] = 0x13, /* VTXCO_2V8: off */
1784+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
1785+ [PCF50606_REG_D3REGC1] = 0x00, /* USER1: off */
1786+#elif defined(CONFIG_ARCH_GTA01B_v4)
1787+ [PCF50606_REG_D3REGC1] = 0xec, /* STBY_1V8: 2.1V */
1788+#endif
1789+
1790+ [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */
1791+ [PCF50606_REG_LPREGC2] = 0x00,
1792+
1793+ [PCF50606_REG_MBCC1] = 0x01, /* CHGAPE */
1794+ [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */
1795+ [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */
1796+ [PCF50606_REG_BBCC] = 0x1f, /* 400uA */
1797+ [PCF50606_REG_ADCC1] = 0x00,
1798+ [PCF50606_REG_ADCC2] = 0x00,
1799+ /* gap */
1800+#if defined(CONFIG_ARCH_GTA01B_v4)
1801+ [PCF50606_REG_ACDC1] = 0x86, /* ACD thresh 1.6V, enabled */
1802+#else
1803+ [PCF50606_REG_ACDC1] = 0x00,
1804+#endif
1805+ [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3,
1806+ [PCF50606_REG_PWMC1] = 0x00,
1807+ [PCF50606_REG_LEDC1] = 0x00,
1808+ [PCF50606_REG_LEDC2] = 0x00,
1809+ [PCF50606_REG_GPOC1] = 0x00,
1810+ [PCF50606_REG_GPOC2] = 0x00,
1811+ [PCF50606_REG_GPOC3] = 0x00,
1812+ [PCF50606_REG_GPOC4] = 0x00,
1813+ [PCF50606_REG_GPOC5] = 0x00,
1814+};
1815+
1816+
1817Index: u-boot/board/neo1973/gta01/split_by_variant.sh
1818===================================================================
1819--- /dev/null
1820+++ u-boot/board/neo1973/gta01/split_by_variant.sh
1821@@ -0,0 +1,57 @@
1822+#!/bin/sh
1823+# ---------------------------------------------------------
1824+# Set the core module defines according to Core Module
1825+# ---------------------------------------------------------
1826+# ---------------------------------------------------------
1827+# Set up the GTA01 type define
1828+# ---------------------------------------------------------
1829+
1830+CFGINC=${obj}include/config.h
1831+CFGTMP=${obj}board/neo1973/gta01/config.tmp
1832+
1833+mkdir -p ${obj}include
1834+if [ "$1" == "" ]
1835+then
1836+ echo "$0:: No parameters - using GTA01Bv3 config"
1837+ echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC
1838+ echo "GTA01_BIG_RAM=y" > $CFGTMP
1839+else
1840+ case "$1" in
1841+ gta01v4_config)
1842+ echo "#define CONFIG_ARCH_GTA01_v4" > $CFGINC
1843+ echo "GTA01_BIG_RAM=n" > $CFGTMP
1844+ ;;
1845+
1846+ gta01v3_config)
1847+ echo "#define CONFIG_ARCH_GTA01_v3" > $CFGINC
1848+ echo "GTA01_BIG_RAM=n" > $CFGTMP
1849+ ;;
1850+
1851+ gta01bv2_config)
1852+ echo "#define CONFIG_ARCH_GTA01B_v2" > $CFGINC
1853+ echo "GTA01_BIG_RAM=y" > $CFGTMP
1854+ ;;
1855+
1856+ gta01bv3_config)
1857+ echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC
1858+ echo "GTA01_BIG_RAM=y" > $CFGTMP
1859+ ;;
1860+
1861+ gta01bv4_config)
1862+ echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC
1863+ echo "GTA01_BIG_RAM=y" > $CFGTMP
1864+ ;;
1865+
1866+ *)
1867+ echo "$0:: Unrecognised config - using GTA01Bv4 config"
1868+ echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC
1869+ echo "GTA01_BIG_RAM=y" > $CFGTMP
1870+ ;;
1871+
1872+ esac
1873+
1874+fi
1875+# ---------------------------------------------------------
1876+# Complete the configuration
1877+# ---------------------------------------------------------
1878+$MKCONFIG -a neo1973_gta01 arm arm920t gta01 neo1973 s3c24x0
1879Index: u-boot/board/neo1973/gta01/u-boot.lds
1880===================================================================
1881--- /dev/null
1882+++ u-boot/board/neo1973/gta01/u-boot.lds
1883@@ -0,0 +1,58 @@
1884+/*
1885+ * (C) Copyright 2002
1886+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
1887+ *
1888+ * See file CREDITS for list of people who contributed to this
1889+ * project.
1890+ *
1891+ * This program is free software; you can redistribute it and/or
1892+ * modify it under the terms of the GNU General Public License as
1893+ * published by the Free Software Foundation; either version 2 of
1894+ * the License, or (at your option) any later version.
1895+ *
1896+ * This program is distributed in the hope that it will be useful,
1897+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1898+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1899+ * GNU General Public License for more details.
1900+ *
1901+ * You should have received a copy of the GNU General Public License
1902+ * along with this program; if not, write to the Free Software
1903+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1904+ * MA 02111-1307 USA
1905+ */
1906+
1907+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1908+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
1909+OUTPUT_ARCH(arm)
1910+ENTRY(_start)
1911+SECTIONS
1912+{
1913+ . = 0x00000000;
1914+
1915+ . = ALIGN(4);
1916+ .text :
1917+ {
1918+ cpu/arm920t/start.o (.text)
1919+ cpu/arm920t/s3c24x0/nand_read.o (.text)
1920+ *(.text)
1921+ }
1922+
1923+ . = ALIGN(4);
1924+ .rodata : { *(.rodata) }
1925+
1926+ . = ALIGN(4);
1927+ .data : { *(.data) }
1928+
1929+ . = ALIGN(4);
1930+ .got : { *(.got) }
1931+
1932+ . = .;
1933+ __u_boot_cmd_start = .;
1934+ .u_boot_cmd : { *(.u_boot_cmd) }
1935+ __u_boot_cmd_end = .;
1936+
1937+ . = ALIGN(4);
1938+ __bss_start = .;
1939+ .bss : { *(.bss) }
1940+ _end = .;
1941+}
1942Index: u-boot/include/configs/neo1973_gta01.h
1943===================================================================
1944--- /dev/null
1945+++ u-boot/include/configs/neo1973_gta01.h
1946@@ -0,0 +1,265 @@
1947+/*
1948+ * (C) Copyright 2006 OpenMoko, Inc.
1949+ * Author: Harald Welte <laforge@openmoko.org>
1950+ *
1951+ * Configuation settings for the FIC Neo1973 GTA01 Linux GSM phone
1952+ *
1953+ * See file CREDITS for list of people who contributed to this
1954+ * project.
1955+ *
1956+ * This program is free software; you can redistribute it and/or
1957+ * modify it under the terms of the GNU General Public License as
1958+ * published by the Free Software Foundation; either version 2 of
1959+ * the License, or (at your option) any later version.
1960+ *
1961+ * This program is distributed in the hope that it will be useful,
1962+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1963+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1964+ * GNU General Public License for more details.
1965+ *
1966+ * You should have received a copy of the GNU General Public License
1967+ * along with this program; if not, write to the Free Software
1968+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1969+ * MA 02111-1307 USA
1970+ */
1971+
1972+#ifndef __CONFIG_H
1973+#define __CONFIG_H
1974+
1975+#if defined(BUILD_FOR_RAM)
1976+/* If we want to start u-boot from inside RAM */
1977+#define CONFIG_SKIP_RELOCATE_UBOOT 1
1978+#define CONFIG_SKIP_LOWLEVEL_INIT 1
1979+#else
1980+/* we want to start u-boot directly from within NAND flash */
1981+#define CONFIG_S3C2410_NAND_BOOT 1
1982+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
1983+#endif
1984+
1985+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
1986+
1987+/*
1988+ * High Level Configuration Options
1989+ * (easy to change)
1990+ */
1991+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
1992+#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
1993+#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
1994+
1995+/* input clock of PLL */
1996+#define CONFIG_SYS_CLK_FREQ 12000000/* the GTA01 has 12MHz input clock */
1997+
1998+
1999+#define USE_920T_MMU 1
2000+#define CONFIG_USE_IRQ 1
2001+
2002+/*
2003+ * Size of malloc() pool
2004+ */
2005+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
2006+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
2007+
2008+/*
2009+ * Hardware drivers
2010+ */
2011+
2012+/*
2013+ * select serial console configuration
2014+ */
2015+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on GTA01 */
2016+
2017+/************************************************************
2018+ * RTC
2019+ ************************************************************/
2020+#define CONFIG_RTC_S3C24X0 1
2021+
2022+/* allow to overwrite serial and ethaddr */
2023+#define CONFIG_ENV_OVERWRITE
2024+
2025+#define CONFIG_BAUDRATE 115200
2026+
2027+/***********************************************************
2028+ * Command definition
2029+ ***********************************************************/
2030+#define CONFIG_COMMANDS (\
2031+ CFG_CMD_BDI | \
2032+ CFG_CMD_LOADS | \
2033+ CFG_CMD_LAODB | \
2034+ CFG_CMD_IMI | \
2035+ CFG_CMD_CACHE | \
2036+ CFG_CMD_MEMORY | \
2037+ CFG_CMD_ENV | \
2038+ /* CFG_CMD_IRQ | */ \
2039+ CFG_CMD_BOOTD | \
2040+ CFG_CMD_CONSOLE | \
2041+ CFG_CMD_ASKENV | \
2042+ CFG_CMD_RUN | \
2043+ CFG_CMD_ECHO | \
2044+ CFG_CMD_I2C | \
2045+ CFG_CMD_REGINFO | \
2046+ CFG_CMD_IMMAP | \
2047+ CFG_CMD_DATE | \
2048+ CFG_CMD_AUTOSCRIPT | \
2049+ CFG_CMD_BSP | \
2050+ CFG_CMD_ELF | \
2051+ CFG_CMD_MISC | \
2052+ /* CFG_CMD_USB | */ \
2053+ /* CFG_CMD_JFFS2 | */ \
2054+ CFG_CMD_DIAG | \
2055+ /* CFG_CMD_HWFLOW | */ \
2056+ CFG_CMD_SAVES | \
2057+ CFG_CMD_NAND | \
2058+ CFG_CMD_PORTIO | \
2059+ CFG_CMD_MMC | \
2060+ CFG_CMD_FAT | \
2061+ CFG_CMD_EXT2 | \
2062+ 0)
2063+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
2064+#include <cmd_confdefs.h>
2065+
2066+#define CONFIG_BOOTDELAY 3
2067+#define CONFIG_BOOTARGS "rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8"
2068+#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x34000 0x200000; bootm 0x32000000"
2069+
2070+#define CONFIG_DOS_PARTITION 1
2071+
2072+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
2073+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
2074+/* what's this ? it's not used anywhere */
2075+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
2076+#endif
2077+
2078+/*
2079+ * Miscellaneous configurable options
2080+ */
2081+#define CFG_LONGHELP /* undef to save memory */
2082+#if defined(CONFIG_ARCH_GTA01_v3)
2083+#define CFG_PROMPT "GTA01v3 # " /* Monitor Command Prompt */
2084+#elif defined(CONFIG_ARCH_GTA01_v4)
2085+#define CFG_PROMPT "GTA01v4 # " /* Monitor Command Prompt */
2086+#elif defined(CONFIG_ARCH_GTA01B_v2)
2087+#define CFG_PROMPT "GTA01Bv2 # " /* Monitor Command Prompt */
2088+#elif defined(CONFIG_ARCH_GTA01B_v3)
2089+#define CFG_PROMPT "GTA01Bv3 # " /* Monitor Command Prompt */
2090+#elif defined(CONFIG_ARCH_GTA01B_v4)
2091+#define CFG_PROMPT "GTA01Bv4 # " /* Monitor Command Prompt */
2092+#endif
2093+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
2094+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
2095+#define CFG_MAXARGS 16 /* max number of command args */
2096+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
2097+
2098+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
2099+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
2100+
2101+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
2102+
2103+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
2104+
2105+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
2106+/* it to wrap 100 times (total 1562500) to get 1 sec. */
2107+#define CFG_HZ 1562500
2108+
2109+/* valid baudrates */
2110+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
2111+
2112+/*-----------------------------------------------------------------------
2113+ * Stack sizes
2114+ *
2115+ * The stack sizes are set up in start.S using the settings below
2116+ */
2117+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
2118+#ifdef CONFIG_USE_IRQ
2119+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
2120+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
2121+#endif
2122+
2123+#if 0
2124+#define CONFIG_USB_OHCI 1
2125+#endif
2126+
2127+/*-----------------------------------------------------------------------
2128+ * Physical Memory Map
2129+ */
2130+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
2131+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
2132+#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
2133+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
2134+#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
2135+ defined(CONFIG_ARCH_GTA01B_v4)
2136+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
2137+#else
2138+#error Please define GTA01 variant
2139+#endif
2140+#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
2141+
2142+/*-----------------------------------------------------------------------
2143+ * FLASH and environment organization
2144+ */
2145+
2146+/* No NOR flash in this device */
2147+#define CFG_NO_FLASH 1
2148+
2149+#define CFG_ENV_IS_IN_NAND 1
2150+#define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */
2151+#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
2152+
2153+#define NAND_MAX_CHIPS 1
2154+#define CFG_NAND_BASE 0x4e000000
2155+#define CFG_MAX_NAND_DEVICE 1
2156+
2157+#define CONFIG_MMC 1
2158+#define CFG_MMC_BASE 0xff000000
2159+
2160+/* EXT2 driver */
2161+#define CONFIG_EXT2 1
2162+
2163+#define CONFIG_FAT 1
2164+#define CONFIG_SUPPORT_VFAT
2165+
2166+#if 0
2167+/* JFFS2 driver */
2168+#define CONFIG_JFFS2_CMDLINE 1
2169+#define CONFIG_JFFS2_NAND 1
2170+#define CONFIG_JFFS2_NAND_DEV 0
2171+#define CONFIG_JFFS2_NAND_OFF 0x634000
2172+#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
2173+#endif
2174+
2175+/* ATAG configuration */
2176+#define CONFIG_INITRD_TAG 1
2177+#define CONFIG_SETUP_MEMORY_TAGS 1
2178+#define CONFIG_CMDLINE_TAG 1
2179+#define CONFIG_REVISION_TAG 1
2180+#if 0
2181+#define CONFIG_SERIAL_TAG 1
2182+#endif
2183+
2184+#define CONFIG_DRIVER_S3C24X0_I2C 1
2185+#define CONFIG_HARD_I2C 1
2186+#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */
2187+#define CFG_I2C_SLAVE 0x7f
2188+
2189+/* we have a board_late_init() function */
2190+#define BOARD_LATE_INIT 1
2191+
2192+#if 1
2193+#define CONFIG_VIDEO
2194+#define CONFIG_VIDEO_S3C2410
2195+#define CONFIG_CFB_CONSOLE
2196+#define CONFIG_VIDEO_LOGO
2197+#define CONFIG_VGA_AS_SINGLE_DEVICE
2198+
2199+#define VIDEO_KBD_INIT_FCT 0
2200+#define VIDEO_TSTC_FCT serial_tstc
2201+#define VIDEO_GETC_FCT serial_getc
2202+
2203+#define LCD_VIDEO_ADDR 0x33d00000
2204+#endif
2205+
2206+#define CONFIG_S3C2410_NAND_BBT 1
2207+#define CONFIG_S3C2410_NAND_HWECC 1
2208+
2209+#define CONFIG_DRIVER_PCF50606 1
2210+
2211+#endif /* __CONFIG_H */
2212Index: u-boot/board/neo1973/common/neo1973.h
2213===================================================================
2214--- /dev/null
2215+++ u-boot/board/neo1973/common/neo1973.h
2216@@ -0,0 +1,32 @@
2217+#ifndef _NEO1973_H
2218+#define _NEO1973_H
2219+
2220+enum wakeup_reason {
2221+ NEO1973_WAKEUP_NONE,
2222+ NEO1973_WAKEUP_RESET,
2223+ NEO1973_WAKEUP_POWER_KEY,
2224+ NEO1973_WAKEUP_CHARGER,
2225+ NEO1973_WAKEUP_ALARM,
2226+};
2227+
2228+enum neo1973_charger_cmd {
2229+ NEO1973_CHGCMD_NONE,
2230+ NEO1973_CHGCMD_AUTOFAST,
2231+ NEO1973_CHGCMD_NO_AUTOFAST,
2232+ NEO1973_CHGCMD_OFF,
2233+ NEO1973_CHGCMD_FAST,
2234+ NEO1973_CHGCMD_FASTER,
2235+};
2236+
2237+extern unsigned int neo1973_wakeup_cause;
2238+
2239+void neo1973_poweroff(void);
2240+void neo1973_backlight(int on);
2241+void neo1973_vibrator(int on);
2242+
2243+int neo1973_911_key_pressed(void);
2244+
2245+const char *neo1973_get_charge_status(void);
2246+int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd);
2247+
2248+#endif
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-12 04:08:14 +0000