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-rw-r--r--meta/packages/oprofile/oprofile/xscale_events.patch39
1 files changed, 0 insertions, 39 deletions
diff --git a/meta/packages/oprofile/oprofile/xscale_events.patch b/meta/packages/oprofile/oprofile/xscale_events.patch
deleted file mode 100644
index 7f5d1f2bd0..0000000000
--- a/meta/packages/oprofile/oprofile/xscale_events.patch
+++ /dev/null
@@ -1,39 +0,0 @@
1---
2 events/arm/xscale1/events | 8 ++++++--
3 events/arm/xscale2/events | 8 ++++++--
4 2 files changed, 12 insertions(+), 4 deletions(-)
5
6Index: oprofile/events/arm/xscale1/events
7===================================================================
8--- oprofile.orig/events/arm/xscale1/events 2004-04-06 05:32:22.000000000 +0100
9+++ oprofile/events/arm/xscale1/events 2007-05-23 13:37:04.000000000 +0100
10@@ -14,6 +14,10 @@ event:0x0a counters:1,2 um:zero minimum:
11 event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss
12 event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
13 event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
14+event:0x10 counters:1,2 um:zero minimum:500 name:BCU_REQUEST : number of time the BCU received a new memory request from the core
15+event:0x11 counters:1,2 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full
16+event:0x12 counters:1,2 um:zero minimum:500 name:BCU_DRAIN : number of times the BCU queues were drained due to a Drain Write Buffer command or an I/O transaction on a non-cacheable and non-bufferable page
17+event:0x14 counters:1,2 um:zero minimum:500 name:BCU_ECC_NO_ELOG : number of times the BCU detected an ECC error, but no ELOG register was available in which to log the error
18+event:0x15 counters:1,2 um:zero minimum:500 name:BCU_1_BIT_ERR : number of times the BCU detected a 1-bit error while reading data from the bus
19+event:0x16 counters:1,2 um:zero minimum:500 name:RMW : number of times an RMW cycle occurred due to narrow write on ECC-protected memory
20 event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
21-#0x10 through 0x17 Defined by ASSP. See the Intel® XScale" core implementation option section of the ASSP
22-#architecture specification for more details.
23Index: oprofile/events/arm/xscale2/events
24===================================================================
25--- oprofile.orig/events/arm/xscale2/events 2004-04-06 05:32:23.000000000 +0100
26+++ oprofile/events/arm/xscale2/events 2007-05-23 13:37:34.000000000 +0100
27@@ -14,6 +14,10 @@ event:0x0a counters:1,2,3,4 um:zero mini
28 event:0x0b counters:1,2,3,4 um:zero minimum:500 name:DCACHE_MISS : data cache miss
29 event:0x0c counters:1,2,3,4 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
30 event:0x0d counters:1,2,3,4 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
31+event:0x10 counters:1,2,3,4 um:zero minimum:500 name:BCU_REQUEST : number of time the BCU received a new memory request from the core
32+event:0x11 counters:1,2,3,4 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full
33+event:0x12 counters:1,2,3,4 um:zero minimum:500 name:BCU_DRAIN : number of times the BCU queues were drained due to a Drain Write Buffer command or an I/O transaction on a non-cacheable and non-bufferable page
34+event:0x14 counters:1,2,3,4 um:zero minimum:500 name:BCU_ECC_NO_ELOG : number of times the BCU detected an ECC error, but no ELOG register was available in which to log the error
35+event:0x15 counters:1,2,3,4 um:zero minimum:500 name:BCU_1_BIT_ERR : number of times the BCU detected a 1-bit error while reading data from the bus
36+event:0x16 counters:1,2,3,4 um:zero minimum:500 name:RMW : number of times an RMW cycle occurred due to narrow write on ECC-protected memory
37 event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
38-#0x10 through 0x17 Defined by ASSP. See the Intel® XScale" core implementation option section of the ASSP
39-#architecture specification for more details.