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-rw-r--r--meta/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch1566
1 files changed, 1566 insertions, 0 deletions
diff --git a/meta/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch b/meta/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
new file mode 100644
index 0000000000..d33f4522f8
--- /dev/null
+++ b/meta/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
@@ -0,0 +1,1566 @@
1 drivers/video/Kconfig | 10 +
2 drivers/video/Makefile | 1
3 drivers/video/mbx/Makefile | 3
4 drivers/video/mbx/mbxfb.c | 646 ++++++++++++++++++++++++++++++++++++++++++
5 drivers/video/mbx/mbxsysfs.c | 129 ++++++++
6 drivers/video/mbx/reg_bits.h | 489 ++++++++++++++++++++++++++++++++
7 drivers/video/mbx/regs.h | 192 ++++++++++++
8 include/linux/mbxfb.h | 28 ++
9 8 files changed, 1498 insertions(+), 0 deletions(-)
10
11diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
12index 17de4c8..3f472d4 100644
13--- a/drivers/video/Kconfig
14+++ b/drivers/video/Kconfig
15@@ -1518,6 +1518,16 @@ config FB_PXA_PARAMETERS
16
17 <file:Documentation/fb/pxafb.txt> describes the available parameters.
18
19+config FB_MBX
20+ tristate "2700G LCD framebuffer support"
21+ depends on FB && ARCH_PXA
22+ select FB_CFB_FILLRECT
23+ select FB_CFB_COPYAREA
24+ select FB_CFB_IMAGEBLIT
25+ ---help---
26+
27+ If unsure, say N.
28+
29 config FB_W100
30 tristate "W100 frame buffer support"
31 depends on FB && PXA_SHARPSL
32diff --git a/drivers/video/Makefile b/drivers/video/Makefile
33index c335e9b..eabb5be 100644
34--- a/drivers/video/Makefile
35+++ b/drivers/video/Makefile
36@@ -38,6 +38,7 @@ obj-$(CONFIG_FB_SIS) += sis/
37 obj-$(CONFIG_FB_KYRO) += kyro/
38 obj-$(CONFIG_FB_SAVAGE) += savage/
39 obj-$(CONFIG_FB_GEODE) += geode/
40+obj-$(CONFIG_FB_MBX) += mbx/
41 obj-$(CONFIG_FB_I810) += vgastate.o
42 obj-$(CONFIG_FB_NEOMAGIC) += neofb.o vgastate.o
43 obj-$(CONFIG_FB_VIRGE) += virgefb.o
44diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
45new file mode 100644
46index 0000000..ad042f5
47--- /dev/null
48+++ b/drivers/video/mbx/Makefile
49@@ -0,0 +1,3 @@
50+# Makefile for the 2700G controller driver.
51+
52+obj-$(CONFIG_FB_MBX) += mbxfb.o
53diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
54new file mode 100644
55index 0000000..fcf164f
56--- /dev/null
57+++ b/drivers/video/mbx/mbxfb.c
58@@ -0,0 +1,646 @@
59+/*
60+ * linux/drivers/video/mbx/mbxfb.c
61+ *
62+ * Copyright (C) 2006 Compulab, Ltd.
63+ * Mike Rapoport <mike@compulab.co.il>
64+ *
65+ * Based on pxafb.c
66+ *
67+ * This file is subject to the terms and conditions of the GNU General Public
68+ * License. See the file COPYING in the main directory of this archive for
69+ * more details.
70+ *
71+ * Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
72+ *
73+ */
74+
75+#include <linux/config.h>
76+#include <linux/module.h>
77+#include <linux/fb.h>
78+#include <linux/delay.h>
79+#include <linux/init.h>
80+#include <linux/platform_device.h>
81+#include <linux/mbxfb.h>
82+
83+#include <asm/io.h>
84+
85+/* use defines from asm-arm/arch-pxa/bitfields.h for now */
86+/* review (and maybe rework) all bitfields access later */
87+#define UData(Data) ((unsigned long) (Data))
88+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
89+#define FSize(Field) ((Field) >> 16)
90+#define FShft(Field) ((Field) & 0x0000FFFF)
91+#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
92+#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
93+#define F1stBit(Field) (UData (1) << FShft (Field))
94+
95+static unsigned long virt_base_2700;
96+#include "regs.h"
97+#include "reg_bits.h"
98+
99+#define MIN_XRES 16
100+#define MIN_YRES 16
101+#define MAX_XRES 2048
102+#define MAX_YRES 2048
103+
104+/* FIXME: take care of different chip reivsions with different sizes
105+ of ODFB */
106+#define MEMORY_OFFSET 0x60000
107+
108+struct mbxfb_info {
109+ struct device *dev;
110+
111+ struct resource *fb_res;
112+ struct resource *fb_req;
113+
114+ struct resource *reg_res;
115+ struct resource *reg_req;
116+
117+ void __iomem *fb_virt_addr;
118+ unsigned long fb_phys_addr;
119+
120+ void __iomem *reg_virt_addr;
121+ unsigned long reg_phys_addr;
122+
123+ int (*platform_probe)(struct fb_info *fb);
124+ int (*platform_remove)(struct fb_info *fb);
125+};
126+
127+static struct fb_var_screeninfo mbxfb_default = {
128+ .xres = 640,
129+ .yres = 480,
130+ .xres_virtual = 640,
131+ .yres_virtual = 480,
132+ .bits_per_pixel = 16,
133+ .red = { 11, 5, 0 },
134+ .green = { 5, 6, 0 },
135+ .blue = { 0, 5, 0 },
136+ .activate = FB_ACTIVATE_TEST,
137+ .height = -1,
138+ .width = -1,
139+ .pixclock = 40000,
140+ .left_margin = 48,
141+ .right_margin = 16,
142+ .upper_margin = 33,
143+ .lower_margin = 10,
144+ .hsync_len = 96,
145+ .vsync_len = 2,
146+ .vmode = FB_VMODE_NONINTERLACED,
147+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
148+};
149+
150+static struct fb_fix_screeninfo mbxfb_fix = {
151+ .id = "MBX",
152+ .type = FB_TYPE_PACKED_PIXELS,
153+ .visual = FB_VISUAL_TRUECOLOR,
154+ .xpanstep = 0,
155+ .ypanstep = 0,
156+ .ywrapstep = 0,
157+ .accel = FB_ACCEL_NONE,
158+};
159+
160+struct pixclock_div {
161+ u8 m;
162+ u8 n;
163+ u8 p;
164+};
165+
166+static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps, struct pixclock_div *div)
167+{
168+ u8 m, n, p;
169+ unsigned int err = 0;
170+ unsigned int min_err = ~0x0;
171+ unsigned int clk;
172+ unsigned int best_clk = 0;
173+ unsigned int ref_clk = 13000; /* FIXME: take from platform data */
174+ unsigned int pixclock;
175+
176+ /* convert pixclock to KHz */
177+ pixclock = PICOS2KHZ(pixclock_ps);
178+
179+ for ( m = 1; m < 64; m++ ) {
180+ for ( n = 1; n < 8; n++ ) {
181+ for ( p = 0; p < 8; p++ ) {
182+ clk = (ref_clk * m) / (n * (1 << p));
183+ err = (clk > pixclock) ? (clk - pixclock) :
184+ (pixclock - clk);
185+ if ( err < min_err ) {
186+ min_err = err;
187+ best_clk = clk;
188+ div->m = m;
189+ div->n = n;
190+ div->p = p;
191+ }
192+ }
193+ }
194+ }
195+ return KHZ2PICOS(best_clk);
196+}
197+
198+static int
199+mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
200+ u_int trans, struct fb_info *info)
201+{
202+ uint val, ret = 1;
203+
204+ if ( regno < 255 ) {
205+ val = (red & 0xff) << 16;
206+ val |= (green & 0xff) << 8;
207+ val |= (blue & 0xff) << 0;
208+ GPLUT = Gplut_Lutadr(regno) | Gplut_Lutdata(val);
209+ udelay(1000);
210+ ret = 0;
211+ }
212+ return ret;
213+}
214+
215+static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
216+{
217+ struct pixclock_div div;
218+
219+ var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
220+
221+ if (var->xres < MIN_XRES)
222+ var->xres = MIN_XRES;
223+ if (var->yres < MIN_YRES)
224+ var->yres = MIN_YRES;
225+ if (var->xres > MAX_XRES)
226+ var->xres = MAX_XRES;
227+ if (var->yres > MAX_YRES)
228+ var->yres = MAX_YRES;
229+ var->xres_virtual =
230+ max(var->xres_virtual, var->xres);
231+ var->yres_virtual =
232+ max(var->yres_virtual, var->yres);
233+
234+ switch (var->bits_per_pixel) {
235+ /* FIXME: implement 8 bits-per-pixel */
236+ case 8:
237+ var->bits_per_pixel = 16;
238+ case 16:
239+ var->green.length = (var->green.length == 5) ? 5 : 6;
240+ var->red.length = 5;
241+ var->blue.length = 5;
242+ var->transp.length = 6 - var->green.length;
243+ var->blue.offset = 0;
244+ var->green.offset = 5;
245+ var->red.offset = 5 + var->green.length;
246+ var->transp.offset = (5 + var->red.offset) & 15;
247+ break;
248+ case 24: /* RGB 888 */
249+ case 32: /* RGBA 8888 */
250+ var->red.offset = 16;
251+ var->red.length = 8;
252+ var->green.offset = 8;
253+ var->green.length = 8;
254+ var->blue.offset = 0;
255+ var->blue.length = 8;
256+ var->transp.length = var->bits_per_pixel - 24;
257+ var->transp.offset = (var->transp.length) ? 24 : 0;
258+ break;
259+ }
260+ var->red.msb_right = 0;
261+ var->green.msb_right = 0;
262+ var->blue.msb_right = 0;
263+ var->transp.msb_right = 0;
264+
265+ return 0;
266+}
267+
268+static int mbxfb_set_par(struct fb_info *info)
269+{
270+ struct fb_var_screeninfo *var = &info->var;
271+ struct pixclock_div div;
272+ ushort hbps, ht, hfps, has;
273+ ushort vbps, vt, vfps, vas;
274+
275+ info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
276+
277+ /* setup color mode */
278+ GSCTRL &= ~(FMsk(GSCTRL_GPIXFMT));
279+ /* FIXME: add *WORKING* support for 8-bits per color */
280+ if ( info->var.bits_per_pixel == 8 ) {
281+ GSCTRL |= GSCTRL_GPIXFMT_INDEXED;
282+ GSCTRL |= GSCTRL_LUT_EN;
283+ GSCTRL &= ~GSCTRL_GAMMA_EN;
284+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
285+ fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
286+ }
287+ else {
288+ fb_dealloc_cmap(&info->cmap);
289+ GSCTRL &= ~GSCTRL_LUT_EN;
290+ info->fix.visual = FB_VISUAL_TRUECOLOR;
291+ switch ( info->var.bits_per_pixel ) {
292+ case 16:
293+ if ( info->var.green.length == 5 )
294+ GSCTRL |= GSCTRL_GPIXFMT_ARGB1555;
295+ else
296+ GSCTRL |= GSCTRL_GPIXFMT_RGB565;
297+ break;
298+ case 24:
299+ GSCTRL |= GSCTRL_GPIXFMT_RGB888;
300+ break;
301+ case 32:
302+ GSCTRL |= GSCTRL_GPIXFMT_ARGB8888;
303+ break;
304+ }
305+ }
306+
307+ /* setup resolution */
308+ GSCTRL &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
309+ GSCTRL |= Gsctrl_Width(info->var.xres - 1) |
310+ Gsctrl_Height(info->var.yres - 1);
311+
312+ GSADR &= ~(FMsk(GSADR_SRCSTRIDE)); udelay(1000);
313+ GSADR |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel / (8 * 16) - 1); udelay(1000);
314+
315+ /* setup timings */
316+ var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
317+
318+ DISPPLL = Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | Disp_Pll_P(div.p) | DISP_PLL_EN;
319+
320+ hbps = var->hsync_len;
321+ has = hbps + var->left_margin;
322+ hfps = has + var->xres;
323+ ht = hfps + var->right_margin;
324+
325+ vbps = var->vsync_len;
326+ vas = vbps + var->upper_margin;
327+ vfps = vas + var->yres;
328+ vt = vfps + var->lower_margin;
329+
330+ DHT01 = Dht01_Hbps(hbps) | Dht01_Ht(ht);
331+ DHT02 = Dht02_Hlbs(has) | Dht02_Has(has);
332+ DHT03 = Dht03_Hfps(hfps) | Dht03_Hrbs(hfps);
333+ DHDET = Dhdet_Hdes(has) | Dhdet_Hdef(hfps);
334+
335+ DVT01 = Dvt01_Vbps(vbps) | Dvt01_Vt(vt);
336+ DVT02 = Dvt02_Vtbs(vas) | Dvt02_Vas(vas);
337+ DVT03 = Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps);
338+ DVDET = Dvdet_Vdes(vas) | Dvdet_Vdef(vfps);
339+ DVECTRL = Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps);
340+ DSCTRL |= DSCTRL_SYNCGEN_EN;
341+
342+ return 0;
343+}
344+
345+static int mbxfb_blank(int blank, struct fb_info *info)
346+{
347+ switch (blank) {
348+ case FB_BLANK_POWERDOWN:
349+ case FB_BLANK_VSYNC_SUSPEND:
350+ case FB_BLANK_HSYNC_SUSPEND:
351+ case FB_BLANK_NORMAL:
352+ DSCTRL &= ~DSCTRL_SYNCGEN_EN; udelay(1000);
353+ PIXCLK &= ~PIXCLK_EN; udelay(1000);
354+ VOVRCLK &= ~VOVRCLK_EN; udelay(1000);
355+ break;
356+ case FB_BLANK_UNBLANK:
357+ DSCTRL |= DSCTRL_SYNCGEN_EN; udelay(1000);
358+ PIXCLK |= PIXCLK_EN; udelay(1000);
359+ break;
360+ }
361+ return 0;
362+}
363+
364+static struct fb_ops mbxfb_ops = {
365+ .owner = THIS_MODULE,
366+ .fb_check_var = mbxfb_check_var,
367+ .fb_set_par = mbxfb_set_par,
368+ .fb_setcolreg = mbxfb_setcolreg,
369+ .fb_fillrect = cfb_fillrect,
370+ .fb_copyarea = cfb_copyarea,
371+ .fb_imageblit = cfb_imageblit,
372+ .fb_blank = mbxfb_blank,
373+};
374+
375+/*
376+ Enable external SDRAM controller. Assume that all clocks are active
377+ by now.
378+*/
379+static void setup_memc(struct fb_info *fbi)
380+{
381+ unsigned long tmp;
382+
383+ /* FIXME: use platfrom specific parameters */
384+ /* setup SDRAM controller */
385+ LMCFG = LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS | LMCFG_LMA_TS;
386+ udelay(1000);
387+ LMPWR = LMPWR_MC_PWR_ACT;
388+ udelay(1000);
389+ /* setup SDRAM timings */
390+ LMTIM = Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) | Lmtim_Trc(9) |
391+ Lmtim_Tdpl(2);
392+ udelay(1000);
393+ /* setup SDRAM refresh rate */
394+ LMREFRESH = 0xc2b;
395+ udelay(1000);
396+ /* setup SDRAM type parameters */
397+ LMTYPE = LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
398+ LMTYPE_COLSZ_8;
399+ udelay(1000);
400+ /* enable memory controller */
401+ LMPWR = LMPWR_MC_PWR_ACT;
402+ udelay(1000);
403+
404+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
405+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
406+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
407+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
408+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
409+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
410+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
411+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
412+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
413+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
414+ tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
415+}
416+
417+static void enable_clocks(struct fb_info* fbi)
418+{
419+ /* enable clocks */
420+ SYSCLKSRC = SYSCLKSRC_PLL_2; udelay(1000);
421+ PIXCLKSRC = PIXCLKSRC_PLL_1; udelay(1000);
422+ CLKSLEEP = 0x00000000; udelay(1000);
423+ COREPLL = Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) | CORE_PLL_EN; udelay(1000);
424+ DISPPLL = Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) | DISP_PLL_EN;
425+
426+ VOVRCLK = 0x00000000; udelay(1000);
427+ PIXCLK = PIXCLK_EN; udelay(1000);
428+ MEMCLK = MEMCLK_EN; udelay(1000);
429+ M24CLK = 0x00000006; udelay(1000);
430+ MBXCLK = 0x00000006; udelay(1000);
431+ SDCLK = SDCLK_EN; udelay(1000);
432+ PIXCLKDIV = 0x00000001; udelay(1000);
433+}
434+
435+static void setup_graphics(struct fb_info* fbi)
436+{
437+ unsigned long gsctrl;
438+
439+ gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres-1) |
440+ Gsctrl_Height(fbi->var.yres-1);
441+ switch ( fbi->var.bits_per_pixel ) {
442+ case 16:
443+ if ( fbi->var.green.length == 5 )
444+ gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
445+ else
446+ gsctrl |= GSCTRL_GPIXFMT_RGB565;
447+ break;
448+ case 24: gsctrl |= GSCTRL_GPIXFMT_RGB888; break;
449+ case 32: gsctrl |= GSCTRL_GPIXFMT_ARGB8888; break;
450+ }
451+
452+ GSCTRL = gsctrl; udelay(1000);
453+ GBBASE = 0x00000000; udelay(1000);
454+ GDRCTRL = 0x00ffffff; udelay(1000);
455+ GSCADR = GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000); udelay(1000);
456+ GPLUT = 0x00000000; udelay(1000);
457+}
458+
459+static void setup_display(struct fb_info* fbi)
460+{
461+ unsigned long dsctrl = 0;
462+
463+ dsctrl = DSCTRL_BLNK_POL;
464+ if ( fbi->var.sync & FB_SYNC_HOR_HIGH_ACT )
465+ dsctrl |= DSCTRL_HS_POL;
466+ if ( fbi->var.sync & FB_SYNC_VERT_HIGH_ACT )
467+ dsctrl |= DSCTRL_VS_POL;
468+ DSCTRL = dsctrl; udelay(1000);
469+ DMCTRL = 0xd0303010; udelay(1000);
470+ DSCTRL |= DSCTRL_SYNCGEN_EN;
471+}
472+
473+static void enable_controller(struct fb_info* fbi)
474+{
475+ SYSRST = SYSRST_RST;
476+ udelay(1000);
477+
478+ enable_clocks(fbi);
479+ setup_memc(fbi);
480+ setup_graphics(fbi);
481+ setup_display(fbi);
482+}
483+
484+
485+#ifdef CONFIG_PM
486+/*
487+ * Power management hooks. Note that we won't be called from IRQ context,
488+ * unlike the blank functions above, so we may sleep.
489+ */
490+static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
491+{
492+ /* make frame buffer memory enter self-refresh mode */
493+ LMPWR = LMPWR_MC_PWR_SRM;
494+ while ( LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM );
495+
496+ /* reset the device, since it's initial state is 'mostly sleeping' */
497+ SYSRST = SYSRST_RST;
498+ return 0;
499+}
500+
501+static int mbxfb_resume(struct platform_device *dev)
502+{
503+ struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
504+
505+ enable_clocks(fbi);
506+/* setup_graphics(fbi); */
507+/* setup_display(fbi); */
508+
509+ DSCTRL |= DSCTRL_SYNCGEN_EN;
510+ return 0;
511+}
512+#else
513+#define mbxfb_suspend NULL
514+#define mbxfb_resume NULL
515+#endif
516+
517+#include "mbxsysfs.c"
518+
519+#define res_size(_r) (((_r)->end - (_r)->start) + 1)
520+
521+static int mbxfb_probe(struct platform_device *dev)
522+{
523+ int ret;
524+ struct fb_info *fbi;
525+ struct mbxfb_info *mfbi;
526+ struct mbxfb_platform_data *pdata;
527+
528+ dev_dbg(dev, "mbxfb_probe\n");
529+
530+ fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
531+ if ( fbi == NULL ) {
532+ dev_err(&dev->dev, "framebuffer_alloc failed\n");
533+ return -ENOMEM;
534+ }
535+
536+ mfbi = fbi->par;
537+ pdata = dev->dev.platform_data;
538+ if ( pdata->probe )
539+ mfbi->platform_probe = pdata->probe;
540+ if ( pdata->remove )
541+ mfbi->platform_remove = pdata->remove;
542+
543+ mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
544+ mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
545+
546+ if ( !mfbi->fb_res || !mfbi->reg_res ) {
547+ dev_err(&dev->dev, "no resources found\n");
548+ ret = -ENODEV;
549+ goto err1;
550+ }
551+
552+ mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
553+ res_size(mfbi->fb_res),
554+ dev->name);
555+ if ( mfbi->fb_req == NULL ) {
556+ dev_err(&dev->dev, "failed to claim framebuffer memory\n");
557+ ret = -EINVAL;
558+ goto err1;
559+ }
560+ mfbi->fb_phys_addr = mfbi->fb_res->start;
561+
562+ mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
563+ res_size(mfbi->reg_res),
564+ dev->name);
565+ if ( mfbi->reg_req == NULL ) {
566+ dev_err(&dev->dev, "failed to claim Marathon registers\n");
567+ ret = -EINVAL;
568+ goto err2;
569+ }
570+ mfbi->reg_phys_addr = mfbi->reg_res->start;
571+
572+ mfbi->reg_virt_addr = ioremap_nocache(mfbi->reg_phys_addr,
573+ res_size(mfbi->reg_req));
574+ if ( !mfbi->reg_virt_addr ) {
575+ dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
576+ ret = -EINVAL;
577+ goto err3;
578+ }
579+ virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
580+
581+ mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
582+ res_size(mfbi->fb_req));
583+ if ( !mfbi->reg_virt_addr ) {
584+ dev_err(&dev->dev, "failed to ioremap frame buffer\n");
585+ ret = -EINVAL;
586+ goto err4;
587+ }
588+
589+ fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000); /* FIXME: */
590+ fbi->screen_size = 8*1024*1024; /* 8 Megs */ /* FIXME: get from platform */
591+ fbi->fbops = &mbxfb_ops;
592+
593+ fbi->var = mbxfb_default;
594+ fbi->fix = mbxfb_fix;
595+ fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
596+ fbi->fix.smem_len = 8*1024*1024;
597+ fbi->fix.line_length = 640*2;
598+
599+ ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
600+ if (ret < 0) {
601+ dev_err(&dev->dev, "fb_alloc_cmap failed\n");
602+ ret = -EINVAL;
603+ goto err5;
604+ }
605+
606+ ret = register_framebuffer(fbi);
607+ if (ret < 0) {
608+ dev_err(&dev->dev, "register_framebuffer failed\n");
609+ ret = -EINVAL;
610+ goto err6;
611+ }
612+
613+ platform_set_drvdata(dev, fbi);
614+
615+ printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
616+
617+ if ( mfbi->platform_probe )
618+ mfbi->platform_probe(fbi);
619+
620+ enable_controller(fbi);
621+
622+ mbxfb_sysfs_register(fbi);
623+
624+ return 0;
625+
626+ err6:
627+ fb_dealloc_cmap(&fbi->cmap);
628+ err5:
629+ iounmap(mfbi->fb_virt_addr);
630+ err4:
631+ iounmap(mfbi->reg_virt_addr);
632+ err3:
633+ release_mem_region(mfbi->reg_res->start,
634+ res_size(mfbi->reg_res));
635+ err2:
636+ release_mem_region(mfbi->fb_res->start,
637+ res_size(mfbi->fb_res));
638+ err1:
639+ framebuffer_release(fbi);
640+
641+ return ret;
642+}
643+
644+static int mbxfb_remove(struct platform_device *dev)
645+{
646+ struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
647+
648+ SYSRST = SYSRST_RST;
649+ udelay(1000);
650+
651+ if (fbi) {
652+ struct mbxfb_info *mfbi = fbi->par;
653+
654+ unregister_framebuffer(fbi);
655+ if ( mfbi ) {
656+ if ( mfbi->platform_remove )
657+ mfbi->platform_remove(fbi);
658+
659+ if ( mfbi->fb_virt_addr )
660+ iounmap(mfbi->fb_virt_addr);
661+ if ( mfbi->reg_virt_addr )
662+ iounmap(mfbi->reg_virt_addr);
663+ if ( mfbi->reg_req )
664+ release_mem_region(mfbi->reg_req->start,
665+ res_size(mfbi->reg_req));
666+ if ( mfbi->fb_req )
667+ release_mem_region(mfbi->fb_req->start,
668+ res_size(mfbi->fb_req));
669+ }
670+ framebuffer_release(fbi);
671+ }
672+
673+ return 0;
674+}
675+
676+static struct platform_driver mbxfb_driver = {
677+ .probe = mbxfb_probe,
678+ .remove = mbxfb_remove,
679+
680+#ifdef CONFIG_PM
681+ .suspend = mbxfb_suspend,
682+ .resume = mbxfb_resume,
683+#endif
684+ .driver = {
685+ .name = "mbx-fb",
686+ },
687+};
688+
689+int __devinit mbxfb_init(void)
690+{
691+ return platform_driver_register(&mbxfb_driver);
692+}
693+
694+static void __exit mbxfb_exit(void)
695+{
696+ platform_driver_unregister(&mbxfb_driver);
697+}
698+
699+module_init(mbxfb_init);
700+module_exit(mbxfb_exit);
701+
702+MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
703+MODULE_AUTHOR("Mike Rapoport, Compulab");
704+MODULE_LICENSE("GPL");
705diff --git a/drivers/video/mbx/mbxsysfs.c b/drivers/video/mbx/mbxsysfs.c
706new file mode 100644
707index 0000000..4b9571a
708--- /dev/null
709+++ b/drivers/video/mbx/mbxsysfs.c
710@@ -0,0 +1,129 @@
711+static ssize_t sysconf_show(struct class_device * subsys, char * buf)
712+{
713+ char * s = buf;
714+
715+ s += sprintf(s, "SYSCFG = %08lx\n", SYSCFG);
716+ s += sprintf(s, "PFBASE = %08lx\n", PFBASE);
717+ s += sprintf(s, "PFCEIL = %08lx\n", PFCEIL);
718+ s += sprintf(s, "POLLFLAG = %08lx\n", POLLFLAG);
719+ s += sprintf(s, "SYSRST = %08lx\n", SYSRST);
720+ return (s - buf);
721+}
722+
723+static ssize_t sysconf_store(struct class_device * subsys, const char * buf, size_t n)
724+{
725+ return n;
726+}
727+
728+static ssize_t gsctl_show(struct class_device * subsys, char * buf)
729+{
730+ char * s = buf;
731+
732+ s += sprintf(s, "GSCTRL = %08lx\n", GSCTRL);
733+ s += sprintf(s, "VSCTRL = %08lx\n", VSCTRL);
734+ s += sprintf(s, "GBBASE = %08lx\n", GBBASE);
735+ s += sprintf(s, "VBBASE = %08lx\n", VBBASE);
736+ s += sprintf(s, "GDRCTRL = %08lx\n", GDRCTRL);
737+ s += sprintf(s, "VCMSK = %08lx\n", VCMSK);
738+ s += sprintf(s, "GSCADR = %08lx\n", GSCADR);
739+ s += sprintf(s, "VSCADR = %08lx\n", VSCADR);
740+ s += sprintf(s, "VUBASE = %08lx\n", VUBASE);
741+ s += sprintf(s, "VVBASE = %08lx\n", VVBASE);
742+ s += sprintf(s, "GSADR = %08lx\n", GSADR);
743+ s += sprintf(s, "VSADR = %08lx\n", VSADR);
744+ s += sprintf(s, "HCCTRL = %08lx\n", HCCTRL);
745+ s += sprintf(s, "HCSIZE = %08lx\n", HCSIZE);
746+ s += sprintf(s, "HCPOS = %08lx\n", HCPOS);
747+ s += sprintf(s, "HCBADR = %08lx\n", HCBADR);
748+ s += sprintf(s, "HCCKMSK = %08lx\n", HCCKMSK);
749+ s += sprintf(s, "GPLUT = %08lx\n", GPLUT);
750+ return (s - buf);
751+}
752+
753+static ssize_t gsctl_store(struct class_device * subsys, const char * buf, size_t n)
754+{
755+ return n;
756+}
757+
758+static ssize_t display_show(struct class_device * subsys, char * buf)
759+{
760+ char * s = buf;
761+
762+ s += sprintf(s, "DSCTRL = %08lx\n", DSCTRL);
763+ s += sprintf(s, "DHT01 = %08lx\n", DHT01);
764+ s += sprintf(s, "DHT02 = %08lx\n", DHT02);
765+ s += sprintf(s, "DHT03 = %08lx\n", DHT03);
766+ s += sprintf(s, "DVT01 = %08lx\n", DVT01);
767+ s += sprintf(s, "DVT02 = %08lx\n", DVT02);
768+ s += sprintf(s, "DVT03 = %08lx\n", DVT03);
769+ s += sprintf(s, "DBCOL = %08lx\n", DBCOL);
770+ s += sprintf(s, "BGCOLOR = %08lx\n", BGCOLOR);
771+ s += sprintf(s, "DINTRS = %08lx\n", DINTRS);
772+ s += sprintf(s, "DINTRE = %08lx\n", DINTRE);
773+ s += sprintf(s, "DINTRCNT = %08lx\n", DINTRCNT);
774+ s += sprintf(s, "DSIG = %08lx\n", DSIG);
775+ s += sprintf(s, "DMCTRL = %08lx\n", DMCTRL);
776+ s += sprintf(s, "CLIPCTRL = %08lx\n", CLIPCTRL);
777+ s += sprintf(s, "SPOCTRL = %08lx\n", SPOCTRL);
778+ s += sprintf(s, "SVCTRL = %08lx\n", SVCTRL);
779+ s += sprintf(s, "DLSTS = %08lx\n", DLSTS);
780+ s += sprintf(s, "DLLCTRL = %08lx\n", DLLCTRL);
781+ s += sprintf(s, "DVLNUM = %08lx\n", DVLNUM);
782+ s += sprintf(s, "DUCTRL = %08lx\n", DUCTRL);
783+ s += sprintf(s, "DVECTRL = %08lx\n", DVECTRL);
784+ s += sprintf(s, "DHDET = %08lx\n", DHDET);
785+ s += sprintf(s, "DVDET = %08lx\n", DVDET);
786+ s += sprintf(s, "DODMSK = %08lx\n", DODMSK);
787+ s += sprintf(s, "CSC01 = %08lx\n", CSC01);
788+ s += sprintf(s, "CSC02 = %08lx\n", CSC02);
789+ s += sprintf(s, "CSC03 = %08lx\n", CSC03);
790+ s += sprintf(s, "CSC04 = %08lx\n", CSC04);
791+ s += sprintf(s, "CSC05 = %08lx\n", CSC05);
792+ return (s - buf);
793+}
794+
795+static ssize_t display_store(struct class_device * subsys, const char * buf, size_t n)
796+{
797+ return n;
798+}
799+
800+static ssize_t clock_show(struct class_device * subsys, char * buf)
801+{
802+ char * s = buf;
803+
804+ s += sprintf(s, "SYSCLKSRC = %08lx\n", SYSCLKSRC);
805+ s += sprintf(s, "PIXCLKSRC = %08lx\n", PIXCLKSRC);
806+ s += sprintf(s, "CLKSLEEP = %08lx\n", CLKSLEEP);
807+ s += sprintf(s, "COREPLL = %08lx\n", COREPLL);
808+ s += sprintf(s, "DISPPLL = %08lx\n", DISPPLL);
809+ s += sprintf(s, "PLLSTAT = %08lx\n", PLLSTAT);
810+ s += sprintf(s, "VOVRCLK = %08lx\n", VOVRCLK);
811+ s += sprintf(s, "PIXCLK = %08lx\n", PIXCLK);
812+ s += sprintf(s, "MEMCLK = %08lx\n", MEMCLK);
813+ s += sprintf(s, "M24CLK = %08lx\n", M24CLK);
814+ s += sprintf(s, "MBXCLK = %08lx\n", MBXCLK);
815+ s += sprintf(s, "SDCLK = %08lx\n", SDCLK);
816+ s += sprintf(s, "PIXCLKDIV = %08lx\n", PIXCLKDIV);
817+ return (s - buf);
818+}
819+
820+static ssize_t clock_store(struct class_device * subsys, const char * buf, size_t n)
821+{
822+ return n;
823+}
824+
825+static struct class_device_attribute mbx_class_attrs[] = {
826+ __ATTR(sysconf,0644,sysconf_show,sysconf_store),
827+ __ATTR(gsctl,0644,gsctl_show,gsctl_store),
828+ __ATTR(display,0644,display_show,display_store),
829+ __ATTR(clock,0644,clock_show,clock_store),
830+};
831+
832+
833+static void mbxfb_sysfs_register(struct fb_info *fbi)
834+{
835+ int i;
836+ for (i = 0; i < ARRAY_SIZE(mbx_class_attrs); i++)
837+ class_device_create_file(fbi->class_device,
838+ &mbx_class_attrs[i]);
839+}
840diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
841new file mode 100644
842index 0000000..be152f6
843--- /dev/null
844+++ b/drivers/video/mbx/reg_bits.h
845@@ -0,0 +1,489 @@
846+#ifndef __REG_BITS_2700G_
847+#define __REG_BITS_2700G_
848+
849+/* /\* System Configuration Registers (0x03FE_0000 0x03FE_0010) *\/ */
850+/* #define SYSCFG __REG_2700G(0x03FE0000) */
851+/* #define PFBASE __REG_2700G(0x03FE0004) */
852+/* #define PFCEIL __REG_2700G(0x03FE0008) */
853+/* #define POLLFLAG __REG_2700G(0x03FE000C) */
854+
855+#define SYSRST_RST (1 << 0)
856+
857+/* /\* Interrupt Control Registers (0x03FE_0014 0x03FE_002F) *\/ */
858+/* #define NINTPW __REG_2700G(0x03FE0014) */
859+/* #define MINTENABLE __REG_2700G(0x03FE0018) */
860+/* #define MINTSTAT __REG_2700G(0x03FE001C) */
861+/* #define SINTENABLE __REG_2700G(0x03FE0020) */
862+/* #define SINTSTAT __REG_2700G(0x03FE0024) */
863+/* #define SINTCLR __REG_2700G(0x03FE0028) */
864+
865+/* SYSCLKSRC - SYSCLK Source Control Register */
866+#define SYSCLKSRC_SEL Fld(2,0)
867+#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
868+#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
869+#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
870+
871+/* PIXCLKSRC - PIXCLK Source Control Register */
872+#define PIXCLKSRC_SEL Fld(2,0)
873+#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
874+#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
875+#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
876+
877+/* Clock Disable Register */
878+#define CLKSLEEP_SLP (1 << 0)
879+
880+/* Core PLL Control Register */
881+#define CORE_PLL_M Fld(6,7)
882+#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
883+#define CORE_PLL_N Fld(3,4)
884+#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
885+#define CORE_PLL_P Fld(3,1)
886+#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
887+#define CORE_PLL_EN (1 << 0)
888+
889+/* Display PLL Control Register */
890+#define DISP_PLL_M Fld(6,7)
891+#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
892+#define DISP_PLL_N Fld(3,4)
893+#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
894+#define DISP_PLL_P Fld(3,1)
895+#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
896+#define DISP_PLL_EN (1 << 0)
897+
898+/* PLL status register */
899+#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
900+#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
901+#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
902+#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
903+
904+/* Video and scale clock control register */
905+#define VOVRCLK_EN (1 << 0)
906+
907+/* Pixel clock control register */
908+#define PIXCLK_EN (1 << 0)
909+
910+/* Memory clock control register */
911+#define MEMCLK_EN (1 << 0)
912+
913+/* MBX clock control register */
914+#define MBXCLK_DIV Fld(2,2)
915+#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
916+#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
917+#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
918+#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
919+#define MBXCLK_EN Fld(2,0)
920+#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
921+#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
922+#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
923+
924+/* M24 clock control register */
925+#define M24CLK_DIV Fld(2,1)
926+#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
927+#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
928+#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
929+#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
930+#define M24CLK_EN (1 << 0)
931+
932+/* SDRAM clock control register */
933+#define SDCLK_EN (1 << 0)
934+
935+/* PixClk Divisor Register */
936+#define PIXCLKDIV_PD Fld(9,0)
937+#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
938+
939+/* LCD Config control register */
940+#define LCDCFG_IN_FMT Fld(3,28)
941+#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
942+#define LCDCFG_LCD1DEN_POL (1 << 27)
943+#define LCDCFG_LCD1FCLK_POL (1 << 26)
944+#define LCDCFG_LCD1LCLK_POL (1 << 25)
945+#define LCDCFG_LCD1D_POL (1 << 24)
946+#define LCDCFG_LCD2DEN_POL (1 << 23)
947+#define LCDCFG_LCD2FCLK_POL (1 << 22)
948+#define LCDCFG_LCD2LCLK_POL (1 << 21)
949+#define LCDCFG_LCD2D_POL (1 << 20)
950+#define LCDCFG_LCD1_TS (1 << 19)
951+#define LCDCFG_LCD1D_DS (1 << 18)
952+#define LCDCFG_LCD1C_DS (1 << 17)
953+#define LCDCFG_LCD1_IS_IN (1 << 16)
954+#define LCDCFG_LCD2_TS (1 << 3)
955+#define LCDCFG_LCD2D_DS (1 << 2)
956+#define LCDCFG_LCD2C_DS (1 << 1)
957+#define LCDCFG_LCD2_IS_IN (1 << 0)
958+
959+/* On-Die Frame Buffer Power Control Register */
960+#define ODFBPWR_SLOW (1 << 2)
961+#define ODFBPWR_MODE Fld(2,0)
962+#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
963+#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
964+#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
965+#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
966+
967+/* On-Die Frame Buffer Power State Status Register */
968+#define ODFBSTAT_ACT (1 << 2)
969+#define ODFBSTAT_SLP (1 << 1)
970+#define ODFBSTAT_SDN (1 << 0)
971+
972+/* /\* GPIO Registers (0x03FE_006C 0x03FE_007F) *\/ */
973+/* #define GPIOCGF __REG_2700G(0x03FE006C) */
974+/* #define GPIOHI __REG_2700G(0x03FE0070) */
975+/* #define GPIOLO __REG_2700G(0x03FE0074) */
976+/* #define GPIOSTAT __REG_2700G(0x03FE0078) */
977+
978+/* /\* Pulse Width Modulator (PWM) Registers (0x03FE_0200 0x03FE_02FF) *\/ */
979+/* #define PWMRST __REG_2700G(0x03FE0200) */
980+/* #define PWMCFG __REG_2700G(0x03FE0204) */
981+/* #define PWM0DIV __REG_2700G(0x03FE0210) */
982+/* #define PWM0DUTY __REG_2700G(0x03FE0214) */
983+/* #define PWM0PER __REG_2700G(0x03FE0218) */
984+/* #define PWM1DIV __REG_2700G(0x03FE0220) */
985+/* #define PWM1DUTY __REG_2700G(0x03FE0224) */
986+/* #define PWM1PER __REG_2700G(0x03FE0228) */
987+
988+
989+/* LMRST - Local Memory (SDRAM) Reset */
990+#define LMRST_MC_RST (1 << 0)
991+
992+/* LMCFG - Local Memory (SDRAM) Configuration Register */
993+#define LMCFG_LMC_DS (1 << 5)
994+#define LMCFG_LMD_DS (1 << 4)
995+#define LMCFG_LMA_DS (1 << 3)
996+#define LMCFG_LMC_TS (1 << 2)
997+#define LMCFG_LMD_TS (1 << 1)
998+#define LMCFG_LMA_TS (1 << 0)
999+
1000+/* LMPWR - Local Memory (SDRAM) Power Control Register */
1001+#define LMPWR_MC_PWR_CNT Fld(2,0)
1002+#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
1003+#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
1004+#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
1005+
1006+/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
1007+#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
1008+#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
1009+#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
1010+#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
1011+
1012+/* LMTYPE - Local Memory (SDRAM) Type Register */
1013+#define LMTYPE_CASLAT Fld(3,10)
1014+#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
1015+#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
1016+#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
1017+#define LMTYPE_BKSZ Fld(2,8)
1018+#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
1019+#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
1020+#define LMTYPE_ROWSZ Fld(4,4)
1021+#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
1022+#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
1023+#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
1024+#define LMTYPE_COLSZ Fld(4,0)
1025+#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
1026+#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
1027+#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
1028+#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
1029+#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
1030+#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
1031+
1032+/* LMTIM - Local Memory (SDRAM) Timing Register */
1033+#define LMTIM_TRAS Fld(4,16)
1034+#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
1035+#define LMTIM_TRP Fld(4,12)
1036+#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
1037+#define LMTIM_TRCD Fld(4,8)
1038+#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
1039+#define LMTIM_TRC Fld(4,4)
1040+#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
1041+#define LMTIM_TDPL Fld(4,0)
1042+#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
1043+
1044+/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
1045+#define LMREFRESH_TREF Fld(2,0)
1046+#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
1047+
1048+/* #define LMCEMR __REG_2700G(0x03FE1010) */
1049+/* #define LMPROTMIN __REG_2700G(0x03FE1020) */
1050+/* #define LMPROTMAX __REG_2700G(0x03FE1024) */
1051+/* #define LMPROTCFG __REG_2700G(0x03FE1028) */
1052+/* #define LMPROTERR __REG_2700G(0x03FE102C) */
1053+
1054+/* GSCTRL - Graphics surface control register */
1055+#define GSCTRL_LUT_EN (1 << 31)
1056+#define GSCTRL_GPIXFMT Fld(4,27)
1057+#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
1058+#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
1059+#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
1060+#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
1061+#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
1062+#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
1063+#define GSCTRL_GAMMA_EN (1 << 26)
1064+
1065+#define GSCTRL_GSWIDTH Fld(11,11)
1066+#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
1067+ (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
1068+
1069+#define GSCTRL_GSHEIGHT Fld(11,0)
1070+#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
1071+ (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
1072+
1073+/* GBBASE fileds */
1074+#define GBBASE_GLALPHA Fld(8,24)
1075+#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
1076+
1077+#define GBBASE_COLKEY Fld(24,0)
1078+#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
1079+
1080+/* GDRCTRL fields */
1081+#define GDRCTRL_PIXDBL (1 << 31)
1082+#define GDRCTRL_PIXHLV (1 << 30)
1083+#define GDRCTRL_LNDBL (1 << 29)
1084+#define GDRCTRL_LNHLV (1 << 28)
1085+#define GDRCTRL_COLKEYM Fld(24,0)
1086+#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
1087+
1088+/* GSCADR graphics stream control address register fields */
1089+#define GSCADR_STR_EN (1 << 31)
1090+#define GSCADR_COLKEY_EN (1 << 30)
1091+#define GSCADR_COLKEYSCR (1 << 29)
1092+#define GSCADR_BLEND_M Fld(2,27)
1093+#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
1094+#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
1095+#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
1096+#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
1097+#define GSCADR_BLEND_POS Fld(2,24)
1098+#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
1099+#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
1100+#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
1101+#define GSCADR_GBASE_ADR Fld(23,0)
1102+#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
1103+
1104+/* GSADR graphics stride address register fields */
1105+#define GSADR_SRCSTRIDE Fld(10,22)
1106+#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
1107+#define GSADR_XSTART Fld(11,11)
1108+#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
1109+#define GSADR_YSTART Fld(11,0)
1110+#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
1111+
1112+/* GPLUT graphics palette register fields */
1113+#define GPLUT_LUTADR Fld(8,24)
1114+#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
1115+#define GPLUT_LUTDATA Fld(24,0)
1116+#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
1117+
1118+/* #define VSCTRL __REG_2700G(0x03FE2004) */
1119+/* #define VBBASE __REG_2700G(0x03FE2024) */
1120+/* #define VCMSK __REG_2700G(0x03FE2044) */
1121+/* #define VSCADR __REG_2700G(0x03FE2064) */
1122+/* #define VUBASE __REG_2700G(0x03FE2084) */
1123+/* #define VVBASE __REG_2700G(0x03FE20A4) */
1124+/* #define VSADR __REG_2700G(0x03FE20C4) */
1125+
1126+
1127+/* HCCTRL - Hardware Cursor Register fields */
1128+#define HCCTRL_CUR_EN (1 << 31)
1129+#define HCCTRL_COLKEY_EN (1 << 29)
1130+#define HCCTRL_COLKEYSRC (1 << 28)
1131+#define HCCTRL_BLEND_M Fld(2,26)
1132+#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
1133+#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
1134+#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
1135+#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
1136+#define HCCTRL_CPIXFMT Fld(3,23)
1137+#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
1138+#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
1139+#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
1140+#define HCCTRL_CBASE_ADR Fld(23,0)
1141+#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
1142+
1143+/* HCSIZE Hardware Cursor Size Register fields */
1144+#define HCSIZE_BLEND_POS Fld(2,29)
1145+#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
1146+#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
1147+#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
1148+#define HCSIZE_CWIDTH Fld(3,16)
1149+#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
1150+#define HCSIZE_CHEIGHT Fld(3,0)
1151+#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
1152+
1153+/* HCPOS Hardware Cursor Position Register fields */
1154+#define HCPOS_SWITCHSRC (1 << 30)
1155+#define HCPOS_CURBLINK Fld(6,24)
1156+#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
1157+#define HCPOS_XSTART Fld(12,12)
1158+#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
1159+#define HCPOS_YSTART Fld(12,0)
1160+#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
1161+
1162+/* HCBADR Hardware Cursor Blend Address Register */
1163+#define HCBADR_GLALPHA Fld(8,24)
1164+#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
1165+#define HCBADR_COLKEY Fld(24,0)
1166+#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
1167+
1168+/* HCCKMSK - Hardware Cursor Color Key Mask Register */
1169+#define HCCKMSK_COLKEY_M Fld(24,0)
1170+#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
1171+
1172+/* DSCTRL - Display sync control register */
1173+#define DSCTRL_SYNCGEN_EN (1 << 31)
1174+#define DSCTRL_DPL_RST (1 << 29)
1175+#define DSCTRL_PWRDN_M (1 << 28)
1176+#define DSCTRL_UPDSYNCCNT (1 << 26)
1177+#define DSCTRL_UPDINTCNT (1 << 25)
1178+#define DSCTRL_UPDCNT (1 << 24)
1179+#define DSCTRL_UPDWAIT Fld(4,16)
1180+#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
1181+#define DSCTRL_CLKPOL (1 << 11)
1182+#define DSCTRL_CSYNC_EN (1 << 10)
1183+#define DSCTRL_VS_SLAVE (1 << 7)
1184+#define DSCTRL_HS_SLAVE (1 << 6)
1185+#define DSCTRL_BLNK_POL (1 << 5)
1186+#define DSCTRL_BLNK_DIS (1 << 4)
1187+#define DSCTRL_VS_POL (1 << 3)
1188+#define DSCTRL_VS_DIS (1 << 2)
1189+#define DSCTRL_HS_POL (1 << 1)
1190+#define DSCTRL_HS_DIS (1 << 0)
1191+
1192+/* DHT01 - Display horizontal timing register 01 */
1193+#define DHT01_HBPS Fld(12,16)
1194+#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
1195+#define DHT01_HT Fld(12,0)
1196+#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
1197+
1198+/* DHT02 - Display horizontal timing register 02 */
1199+#define DHT02_HAS Fld(12,16)
1200+#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
1201+#define DHT02_HLBS Fld(12,0)
1202+#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
1203+
1204+/* DHT03 - Display horizontal timing register 03 */
1205+#define DHT03_HFPS Fld(12,16)
1206+#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
1207+#define DHT03_HRBS Fld(12,0)
1208+#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
1209+
1210+/* DVT01 - Display vertical timing register 01 */
1211+#define DVT01_VBPS Fld(12,16)
1212+#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
1213+#define DVT01_VT Fld(12,0)
1214+#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
1215+
1216+/* DVT02 - Display vertical timing register 02 */
1217+#define DVT02_VAS Fld(12,16)
1218+#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
1219+#define DVT02_VTBS Fld(12,0)
1220+#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
1221+
1222+/* DVT03 - Display vertical timing register 03 */
1223+#define DVT03_VFPS Fld(12,16)
1224+#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
1225+#define DVT03_VBBS Fld(12,0)
1226+#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
1227+
1228+/* DVECTRL - display vertical event control register */
1229+#define DVECTRL_VEVENT Fld(12,16)
1230+#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
1231+#define DVECTRL_VFETCH Fld(12,0)
1232+#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
1233+
1234+/* DHDET - display horizontal DE timing register */
1235+#define DHDET_HDES Fld(12,16)
1236+#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
1237+#define DHDET_HDEF Fld(12,0)
1238+#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
1239+
1240+/* DVDET - display vertical DE timing register */
1241+#define DVDET_VDES Fld(12,16)
1242+#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
1243+#define DVDET_VDEF Fld(12,0)
1244+#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
1245+
1246+/* DODMSK - display output data mask register */
1247+#define DODMSK_MASK_LVL (1 << 31)
1248+#define DODMSK_BLNK_LVL (1 << 30)
1249+#define DODMSK_MASK_B Fld(8,16)
1250+#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
1251+#define DODMSK_MASK_G Fld(8,8)
1252+#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
1253+#define DODMSK_MASK_R Fld(8,0)
1254+#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
1255+
1256+/* DBCOL - display border color control register */
1257+#define DBCOL_BORDCOL Fld(24,0)
1258+#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
1259+
1260+/* DVLNUM - display vertical line number register */
1261+#define DVLNUM_VLINE Fld(12,0)
1262+#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
1263+
1264+/* DMCTRL - Display Memory Control Register */
1265+#define DMCTRL_MEM_REF Fld(2,30)
1266+#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
1267+#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
1268+#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
1269+#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
1270+#define DMCTRL_UV_THRHLD Fld(6,24)
1271+#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
1272+#define DMCTRL_V_THRHLD Fld(7,16)
1273+#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
1274+#define DMCTRL_D_THRHLD Fld(7,8)
1275+#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
1276+#define DMCTRL_BURSTLEN Fld(6,0)
1277+#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
1278+
1279+
1280+/* DLSTS - display load status register */
1281+#define DLSTS_RLD_ADONE (1 << 23)
1282+/* #define DLSTS_RLD_ADOUT Fld(23,0) */
1283+
1284+/* DLLCTRL - display list load control register */
1285+#define DLLCTRL_RLD_ADRLN Fld(8,24)
1286+#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
1287+
1288+/* #define DSIG __REG_2700G(0x03FE2184) */
1289+/* #define DINTRS __REG_2700G(0x03FE2178) */
1290+/* #define DINTRE __REG_2700G(0x03FE217C) */
1291+/* #define DINTRCNT __REG_2700G(0x03FE2180) */
1292+/* #define DUCTRL __REG_2700G(0x03FE230C) */
1293+
1294+/* BGCOLOR - background color control register */
1295+/* #define BGCOLOR __REG_2700G(0x03FE2174) */
1296+
1297+/* #define CLIPCTRL __REG_2700G(0x03FE218C) */
1298+/* SPOCTRL - Scale Pitch/Order Control Register */
1299+#define SPOCTRL_H_SC_BP (1 << 31)
1300+#define SPOCTRL_V_SC_BP (1 << 30)
1301+#define SPOCTRL_HV_SC_OR (1 << 29)
1302+#define SPOCTRL_VS_UR_C (1 << 27)
1303+#define SPOCTRL_VORDER Fld(2,16)
1304+#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
1305+#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
1306+#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
1307+#define SPOCTRL_VPITCH Fld(16,0)
1308+#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
1309+
1310+/* #define SVCTRL __REG_2700G(0x03FE2194) */
1311+
1312+/* /\* 0x03FE_2198 *\/ */
1313+/* /\* 0x03FE_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 *\/ */
1314+
1315+/* #define SHCTRL __REG_2700G(0x03FE21B0) */
1316+
1317+/* /\* 0x03FE_21B4 *\/ */
1318+/* /\* 0x03FE_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 *\/ */
1319+
1320+/* #define SSSIZE __REG_2700G(0x03FE21D8) */
1321+
1322+/* /\* 0x03FE_2200 *\/ */
1323+/* /\* 0x03FE_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 *\/ */
1324+
1325+/* /\* 0x03FE_2250 *\/ */
1326+/* /\* 0x03FE_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 *\/ */
1327+
1328+/* #define CSC01 __REG_2700G(0x03FE2330) */
1329+/* #define CSC02 __REG_2700G(0x03FE2334) */
1330+/* #define CSC03 __REG_2700G(0x03FE2338) */
1331+/* #define CSC04 __REG_2700G(0x03FE233C) */
1332+/* #define CSC05 __REG_2700G(0x03FE2340) */
1333+
1334+#endif /* __REG_BITS_2700G_ */
1335diff --git a/drivers/video/mbx/regs.h b/drivers/video/mbx/regs.h
1336new file mode 100644
1337index 0000000..edf0f14
1338--- /dev/null
1339+++ b/drivers/video/mbx/regs.h
1340@@ -0,0 +1,192 @@
1341+#ifndef __REGS_2700G_
1342+#define __REGS_2700G_
1343+
1344+/* extern unsigned long virt_base_2700; */
1345+#define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700))
1346+
1347+/* System Configuration Registers (0x0000_0000 0x0000_0010) */
1348+#define SYSCFG __REG_2700G(0x00000000)
1349+#define PFBASE __REG_2700G(0x00000004)
1350+#define PFCEIL __REG_2700G(0x00000008)
1351+#define POLLFLAG __REG_2700G(0x0000000c)
1352+#define SYSRST __REG_2700G(0x00000010)
1353+
1354+/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
1355+#define NINTPW __REG_2700G(0x00000014)
1356+#define MINTENABLE __REG_2700G(0x00000018)
1357+#define MINTSTAT __REG_2700G(0x0000001c)
1358+#define SINTENABLE __REG_2700G(0x00000020)
1359+#define SINTSTAT __REG_2700G(0x00000024)
1360+#define SINTCLR __REG_2700G(0x00000028)
1361+
1362+/* Clock Control Registers (0x0000_002C 0x0000_005F) */
1363+#define SYSCLKSRC __REG_2700G(0x0000002c)
1364+#define PIXCLKSRC __REG_2700G(0x00000030)
1365+#define CLKSLEEP __REG_2700G(0x00000034)
1366+#define COREPLL __REG_2700G(0x00000038)
1367+#define DISPPLL __REG_2700G(0x0000003c)
1368+#define PLLSTAT __REG_2700G(0x00000040)
1369+#define VOVRCLK __REG_2700G(0x00000044)
1370+#define PIXCLK __REG_2700G(0x00000048)
1371+#define MEMCLK __REG_2700G(0x0000004c)
1372+#define M24CLK __REG_2700G(0x00000054)
1373+#define MBXCLK __REG_2700G(0x00000054)
1374+#define SDCLK __REG_2700G(0x00000058)
1375+#define PIXCLKDIV __REG_2700G(0x0000005c)
1376+
1377+/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
1378+#define LCD_CONFIG __REG_2700G(0x00000060)
1379+
1380+/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
1381+#define ODFBPWR __REG_2700G(0x00000064)
1382+#define ODFBSTAT __REG_2700G(0x00000068)
1383+
1384+/* GPIO Registers (0x0000_006C 0x0000_007F) */
1385+#define GPIOCGF __REG_2700G(0x0000006c)
1386+#define GPIOHI __REG_2700G(0x00000070)
1387+#define GPIOLO __REG_2700G(0x00000074)
1388+#define GPIOSTAT __REG_2700G(0x00000078)
1389+
1390+/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
1391+#define PWMRST __REG_2700G(0x00000200)
1392+#define PWMCFG __REG_2700G(0x00000204)
1393+#define PWM0DIV __REG_2700G(0x00000210)
1394+#define PWM0DUTY __REG_2700G(0x00000214)
1395+#define PWM0PER __REG_2700G(0x00000218)
1396+#define PWM1DIV __REG_2700G(0x00000220)
1397+#define PWM1DUTY __REG_2700G(0x00000224)
1398+#define PWM1PER __REG_2700G(0x00000228)
1399+
1400+/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
1401+#define ID __REG_2700G(0x00000FF0)
1402+
1403+/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
1404+#define LMRST __REG_2700G(0x00001000)
1405+#define LMCFG __REG_2700G(0x00001004)
1406+#define LMPWR __REG_2700G(0x00001008)
1407+#define LMPWRSTAT __REG_2700G(0x0000100c)
1408+#define LMCEMR __REG_2700G(0x00001010)
1409+#define LMTYPE __REG_2700G(0x00001014)
1410+#define LMTIM __REG_2700G(0x00001018)
1411+#define LMREFRESH __REG_2700G(0x0000101c)
1412+#define LMPROTMIN __REG_2700G(0x00001020)
1413+#define LMPROTMAX __REG_2700G(0x00001024)
1414+#define LMPROTCFG __REG_2700G(0x00001028)
1415+#define LMPROTERR __REG_2700G(0x0000102c)
1416+
1417+/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
1418+#define GSCTRL __REG_2700G(0x00002000)
1419+#define VSCTRL __REG_2700G(0x00002004)
1420+#define GBBASE __REG_2700G(0x00002020)
1421+#define VBBASE __REG_2700G(0x00002024)
1422+#define GDRCTRL __REG_2700G(0x00002040)
1423+#define VCMSK __REG_2700G(0x00002044)
1424+#define GSCADR __REG_2700G(0x00002060)
1425+#define VSCADR __REG_2700G(0x00002064)
1426+#define VUBASE __REG_2700G(0x00002084)
1427+#define VVBASE __REG_2700G(0x000020a4)
1428+#define GSADR __REG_2700G(0x000020c0)
1429+#define VSADR __REG_2700G(0x000020c4)
1430+#define HCCTRL __REG_2700G(0x00002100)
1431+#define HCSIZE __REG_2700G(0x00002110)
1432+#define HCPOS __REG_2700G(0x00002120)
1433+#define HCBADR __REG_2700G(0x00002130)
1434+#define HCCKMSK __REG_2700G(0x00002140)
1435+#define GPLUT __REG_2700G(0x00002150)
1436+#define DSCTRL __REG_2700G(0x00002154)
1437+#define DHT01 __REG_2700G(0x00002158)
1438+#define DHT02 __REG_2700G(0x0000215c)
1439+#define DHT03 __REG_2700G(0x00002160)
1440+#define DVT01 __REG_2700G(0x00002164)
1441+#define DVT02 __REG_2700G(0x00002168)
1442+#define DVT03 __REG_2700G(0x0000216c)
1443+#define DBCOL __REG_2700G(0x00002170)
1444+#define BGCOLOR __REG_2700G(0x00002174)
1445+#define DINTRS __REG_2700G(0x00002178)
1446+#define DINTRE __REG_2700G(0x0000217c)
1447+#define DINTRCNT __REG_2700G(0x00002180)
1448+#define DSIG __REG_2700G(0x00002184)
1449+#define DMCTRL __REG_2700G(0x00002188)
1450+#define CLIPCTRL __REG_2700G(0x0000218c)
1451+#define SPOCTRL __REG_2700G(0x00002190)
1452+#define SVCTRL __REG_2700G(0x00002194)
1453+
1454+/* 0x0000_2198 */
1455+/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
1456+#define VSCOEFF0 __REG_2700G(0x00002198)
1457+#define VSCOEFF1 __REG_2700G(0x0000219c)
1458+#define VSCOEFF2 __REG_2700G(0x000021a0)
1459+#define VSCOEFF3 __REG_2700G(0x000021a4)
1460+#define VSCOEFF4 __REG_2700G(0x000021a8)
1461+
1462+#define SHCTRL __REG_2700G(0x000021b0)
1463+
1464+/* 0x0000_21B4 */
1465+/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
1466+#define HSCOEFF0 __REG_2700G(0x000021b4)
1467+#define HSCOEFF1 __REG_2700G(0x000021b8)
1468+#define HSCOEFF2 __REG_2700G(0x000021bc)
1469+#define HSCOEFF3 __REG_2700G(0x000021b0)
1470+#define HSCOEFF4 __REG_2700G(0x000021c4)
1471+#define HSCOEFF5 __REG_2700G(0x000021c8)
1472+#define HSCOEFF6 __REG_2700G(0x000021cc)
1473+#define HSCOEFF7 __REG_2700G(0x000021d0)
1474+#define HSCOEFF8 __REG_2700G(0x000021d4)
1475+
1476+#define SSSIZE __REG_2700G(0x000021D8)
1477+
1478+/* 0x0000_2200 */
1479+/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
1480+#define VIDGAM0 __REG_2700G(0x00002200)
1481+#define VIDGAM1 __REG_2700G(0x00002204)
1482+#define VIDGAM2 __REG_2700G(0x00002208)
1483+#define VIDGAM3 __REG_2700G(0x0000220c)
1484+#define VIDGAM4 __REG_2700G(0x00002210)
1485+#define VIDGAM5 __REG_2700G(0x00002214)
1486+#define VIDGAM6 __REG_2700G(0x00002218)
1487+#define VIDGAM7 __REG_2700G(0x0000221c)
1488+#define VIDGAM8 __REG_2700G(0x00002220)
1489+#define VIDGAM9 __REG_2700G(0x00002224)
1490+#define VIDGAM10 __REG_2700G(0x00002228)
1491+#define VIDGAM11 __REG_2700G(0x0000222c)
1492+#define VIDGAM12 __REG_2700G(0x00002230)
1493+#define VIDGAM13 __REG_2700G(0x00002234)
1494+#define VIDGAM14 __REG_2700G(0x00002238)
1495+#define VIDGAM15 __REG_2700G(0x0000223c)
1496+#define VIDGAM16 __REG_2700G(0x00002240)
1497+
1498+/* 0x0000_2250 */
1499+/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
1500+#define GFXGAM0 __REG_2700G(0x00002250)
1501+#define GFXGAM1 __REG_2700G(0x00002254)
1502+#define GFXGAM2 __REG_2700G(0x00002258)
1503+#define GFXGAM3 __REG_2700G(0x0000225c)
1504+#define GFXGAM4 __REG_2700G(0x00002260)
1505+#define GFXGAM5 __REG_2700G(0x00002264)
1506+#define GFXGAM6 __REG_2700G(0x00002268)
1507+#define GFXGAM7 __REG_2700G(0x0000226c)
1508+#define GFXGAM8 __REG_2700G(0x00002270)
1509+#define GFXGAM9 __REG_2700G(0x00002274)
1510+#define GFXGAM10 __REG_2700G(0x00002278)
1511+#define GFXGAM11 __REG_2700G(0x0000227c)
1512+#define GFXGAM12 __REG_2700G(0x00002280)
1513+#define GFXGAM13 __REG_2700G(0x00002284)
1514+#define GFXGAM14 __REG_2700G(0x00002288)
1515+#define GFXGAM15 __REG_2700G(0x0000228c)
1516+#define GFXGAM16 __REG_2700G(0x00002290)
1517+
1518+#define DLSTS __REG_2700G(0x00002300)
1519+#define DLLCTRL __REG_2700G(0x00002304)
1520+#define DVLNUM __REG_2700G(0x00002308)
1521+#define DUCTRL __REG_2700G(0x0000230c)
1522+#define DVECTRL __REG_2700G(0x00002310)
1523+#define DHDET __REG_2700G(0x00002314)
1524+#define DVDET __REG_2700G(0x00002318)
1525+#define DODMSK __REG_2700G(0x0000231c)
1526+#define CSC01 __REG_2700G(0x00002330)
1527+#define CSC02 __REG_2700G(0x00002334)
1528+#define CSC03 __REG_2700G(0x00002338)
1529+#define CSC04 __REG_2700G(0x0000233c)
1530+#define CSC05 __REG_2700G(0x00002340)
1531+
1532+#endif /* __REGS_2700G_ */
1533diff --git a/include/linux/mbxfb.h b/include/linux/mbxfb.h
1534new file mode 100644
1535index 0000000..3bde0f5
1536--- /dev/null
1537+++ b/include/linux/mbxfb.h
1538@@ -0,0 +1,28 @@
1539+#ifndef __MBX_FB_H
1540+#define __MBX_FB_H
1541+
1542+struct mbxfb_val {
1543+ unsigned int defval;
1544+ unsigned int min;
1545+ unsigned int max;
1546+};
1547+
1548+struct fb_info;
1549+
1550+struct mbxfb_platform_data {
1551+ /* Screen info */
1552+ struct mbxfb_val xres;
1553+ struct mbxfb_val yres;
1554+ struct mbxfb_val bpp;
1555+
1556+ /* Memory info */
1557+ unsigned long memsize; /* if 0 use ODFB? */
1558+ unsigned long timings1;
1559+ unsigned long timings2;
1560+ unsigned long timings3;
1561+
1562+ int (*probe)(struct fb_info *fb);
1563+ int (*remove)(struct fb_info *fb);
1564+};
1565+
1566+#endif /* __MBX_FB_H */
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-02 05:51:53 +0000