summaryrefslogtreecommitdiffstats
path: root/meta/classes-recipe/siteinfo.bbclass
diff options
context:
space:
mode:
Diffstat (limited to 'meta/classes-recipe/siteinfo.bbclass')
-rw-r--r--meta/classes-recipe/siteinfo.bbclass232
1 files changed, 232 insertions, 0 deletions
diff --git a/meta/classes-recipe/siteinfo.bbclass b/meta/classes-recipe/siteinfo.bbclass
new file mode 100644
index 0000000000..d31c9b2571
--- /dev/null
+++ b/meta/classes-recipe/siteinfo.bbclass
@@ -0,0 +1,232 @@
1#
2# Copyright OpenEmbedded Contributors
3#
4# SPDX-License-Identifier: MIT
5#
6
7# This class exists to provide information about the targets that
8# may be needed by other classes and/or recipes. If you add a new
9# target this will probably need to be updated.
10
11#
12# Returns information about 'what' for the named target 'target'
13# where 'target' == "<arch>-<os>"
14#
15# 'what' can be one of
16# * target: Returns the target name ("<arch>-<os>")
17# * endianness: Return "be" for big endian targets, "le" for little endian
18# * bits: Returns the bit size of the target, either "32" or "64"
19# * libc: Returns the name of the c library used by the target
20#
21# It is an error for the target not to exist.
22# If 'what' doesn't exist then an empty value is returned
23#
24def siteinfo_data_for_machine(arch, os, d):
25 archinfo = {
26 "allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for allarch
27 "aarch64": "endian-little bit-64 arm-common arm-64",
28 "aarch64_be": "endian-big bit-64 arm-common arm-64",
29 "arc": "endian-little bit-32 arc-common",
30 "arceb": "endian-big bit-32 arc-common",
31 "arm": "endian-little bit-32 arm-common arm-32",
32 "armeb": "endian-big bit-32 arm-common arm-32",
33 "avr32": "endian-big bit-32 avr32-common",
34 "bfin": "endian-little bit-32 bfin-common",
35 "epiphany": "endian-little bit-32",
36 "i386": "endian-little bit-32 ix86-common",
37 "i486": "endian-little bit-32 ix86-common",
38 "i586": "endian-little bit-32 ix86-common",
39 "i686": "endian-little bit-32 ix86-common",
40 "ia64": "endian-little bit-64",
41 "lm32": "endian-big bit-32",
42 "m68k": "endian-big bit-32",
43 "microblaze": "endian-big bit-32 microblaze-common",
44 "microblazeel": "endian-little bit-32 microblaze-common",
45 "mips": "endian-big bit-32 mips-common",
46 "mips64": "endian-big bit-64 mips-common",
47 "mips64el": "endian-little bit-64 mips-common",
48 "mipsisa64r6": "endian-big bit-64 mips-common",
49 "mipsisa64r6el": "endian-little bit-64 mips-common",
50 "mipsel": "endian-little bit-32 mips-common",
51 "mipsisa32r6": "endian-big bit-32 mips-common",
52 "mipsisa32r6el": "endian-little bit-32 mips-common",
53 "powerpc": "endian-big bit-32 powerpc-common",
54 "powerpcle": "endian-little bit-32 powerpc-common",
55 "nios2": "endian-little bit-32 nios2-common",
56 "powerpc64": "endian-big bit-64 powerpc-common",
57 "powerpc64le": "endian-little bit-64 powerpc-common",
58 "ppc": "endian-big bit-32 powerpc-common",
59 "ppc64": "endian-big bit-64 powerpc-common",
60 "ppc64le" : "endian-little bit-64 powerpc-common",
61 "riscv32": "endian-little bit-32 riscv-common",
62 "riscv64": "endian-little bit-64 riscv-common",
63 "sh3": "endian-little bit-32 sh-common",
64 "sh3eb": "endian-big bit-32 sh-common",
65 "sh4": "endian-little bit-32 sh-common",
66 "sh4eb": "endian-big bit-32 sh-common",
67 "sparc": "endian-big bit-32",
68 "viac3": "endian-little bit-32 ix86-common",
69 "x86_64": "endian-little", # bitinfo specified in targetinfo
70 }
71 osinfo = {
72 "darwin": "common-darwin",
73 "darwin9": "common-darwin",
74 "linux": "common-linux common-glibc",
75 "linux-gnu": "common-linux common-glibc",
76 "linux-gnu_ilp32": "common-linux common-glibc",
77 "linux-gnux32": "common-linux common-glibc",
78 "linux-gnun32": "common-linux common-glibc",
79 "linux-gnueabi": "common-linux common-glibc",
80 "linux-gnuspe": "common-linux common-glibc",
81 "linux-musl": "common-linux common-musl",
82 "linux-muslx32": "common-linux common-musl",
83 "linux-musleabi": "common-linux common-musl",
84 "linux-muslspe": "common-linux common-musl",
85 "uclinux-uclibc": "common-uclibc",
86 "cygwin": "common-cygwin",
87 "mingw32": "common-mingw",
88 }
89 targetinfo = {
90 "aarch64-linux-gnu": "aarch64-linux",
91 "aarch64_be-linux-gnu": "aarch64_be-linux",
92 "aarch64-linux-gnu_ilp32": "bit-32 aarch64_be-linux arm-32",
93 "aarch64_be-linux-gnu_ilp32": "bit-32 aarch64_be-linux arm-32",
94 "aarch64-linux-musl": "aarch64-linux",
95 "aarch64_be-linux-musl": "aarch64_be-linux",
96 "arm-linux-gnueabi": "arm-linux",
97 "arm-linux-musleabi": "arm-linux",
98 "armeb-linux-gnueabi": "armeb-linux",
99 "armeb-linux-musleabi": "armeb-linux",
100 "microblazeel-linux" : "microblaze-linux",
101 "microblazeel-linux-musl" : "microblaze-linux",
102 "mips-linux-musl": "mips-linux",
103 "mipsel-linux-musl": "mipsel-linux",
104 "mips64-linux-musl": "mips64-linux",
105 "mips64el-linux-musl": "mips64el-linux",
106 "mips64-linux-gnun32": "mips-linux bit-32",
107 "mips64el-linux-gnun32": "mipsel-linux bit-32",
108 "mipsisa64r6-linux-gnun32": "mipsisa32r6-linux bit-32",
109 "mipsisa64r6el-linux-gnun32": "mipsisa32r6el-linux bit-32",
110 "powerpc-linux": "powerpc32-linux powerpc32-linux-glibc",
111 "powerpc-linux-musl": "powerpc-linux powerpc32-linux powerpc32-linux-musl",
112 "powerpcle-linux": "powerpc32-linux powerpc32-linux-glibc",
113 "powerpcle-linux-musl": "powerpc-linux powerpc32-linux powerpc32-linux-musl",
114 "powerpc-linux-gnuspe": "powerpc-linux powerpc32-linux powerpc32-linux-glibc",
115 "powerpc-linux-muslspe": "powerpc-linux powerpc32-linux powerpc32-linux-musl",
116 "powerpc64-linux-gnuspe": "powerpc-linux powerpc64-linux powerpc64-linux-glibc",
117 "powerpc64-linux-muslspe": "powerpc-linux powerpc64-linux powerpc64-linux-musl",
118 "powerpc64-linux": "powerpc-linux powerpc64-linux powerpc64-linux-glibc",
119 "powerpc64-linux-musl": "powerpc-linux powerpc64-linux powerpc64-linux-musl",
120 "powerpc64le-linux": "powerpc-linux powerpc64-linux powerpc64-linux-glibc",
121 "powerpc64le-linux-musl": "powerpc-linux powerpc64-linux powerpc64-linux-musl",
122 "riscv32-linux": "riscv32-linux",
123 "riscv32-linux-musl": "riscv32-linux",
124 "riscv64-linux": "riscv64-linux",
125 "riscv64-linux-musl": "riscv64-linux",
126 "x86_64-cygwin": "bit-64",
127 "x86_64-darwin": "bit-64",
128 "x86_64-darwin9": "bit-64",
129 "x86_64-linux": "bit-64",
130 "x86_64-linux-musl": "x86_64-linux bit-64",
131 "x86_64-linux-muslx32": "bit-32 ix86-common x32-linux",
132 "x86_64-elf": "bit-64",
133 "x86_64-linux-gnu": "bit-64 x86_64-linux",
134 "x86_64-linux-gnux32": "bit-32 ix86-common x32-linux",
135 "x86_64-mingw32": "bit-64",
136 }
137
138 # Add in any extra user supplied data which may come from a BSP layer, removing the
139 # need to always change this class directly
140 extra_siteinfo = (d.getVar("SITEINFO_EXTRA_DATAFUNCS") or "").split()
141 for m in extra_siteinfo:
142 call = m + "(archinfo, osinfo, targetinfo, d)"
143 locs = { "archinfo" : archinfo, "osinfo" : osinfo, "targetinfo" : targetinfo, "d" : d}
144 archinfo, osinfo, targetinfo = bb.utils.better_eval(call, locs)
145
146 target = "%s-%s" % (arch, os)
147
148 sitedata = []
149 if arch in archinfo:
150 sitedata.extend(archinfo[arch].split())
151 if os in osinfo:
152 sitedata.extend(osinfo[os].split())
153 if target in targetinfo:
154 sitedata.extend(targetinfo[target].split())
155 sitedata.append(target)
156 sitedata.append("common")
157
158 bb.debug(1, "SITE files %s" % sitedata);
159 return sitedata
160
161def siteinfo_data(d):
162 return siteinfo_data_for_machine(d.getVar("HOST_ARCH"), d.getVar("HOST_OS"), d)
163
164python () {
165 sitedata = set(siteinfo_data(d))
166 if "endian-little" in sitedata:
167 d.setVar("SITEINFO_ENDIANNESS", "le")
168 elif "endian-big" in sitedata:
169 d.setVar("SITEINFO_ENDIANNESS", "be")
170 else:
171 bb.error("Unable to determine endianness for architecture '%s'" %
172 d.getVar("HOST_ARCH"))
173 bb.fatal("Please add your architecture to siteinfo.bbclass")
174
175 if "bit-32" in sitedata:
176 d.setVar("SITEINFO_BITS", "32")
177 elif "bit-64" in sitedata:
178 d.setVar("SITEINFO_BITS", "64")
179 else:
180 bb.error("Unable to determine bit size for architecture '%s'" %
181 d.getVar("HOST_ARCH"))
182 bb.fatal("Please add your architecture to siteinfo.bbclass")
183}
184
185# Layers with siteconfig need to add a replacement path to this variable so the
186# sstate isn't path specific
187SITEINFO_PATHVARS = "COREBASE"
188
189def siteinfo_get_files(d, sysrootcache=False):
190 sitedata = siteinfo_data(d)
191 sitefiles = []
192 searched = []
193 for path in d.getVar("BBPATH").split(":"):
194 for element in sitedata:
195 filename = os.path.join(path, "site", element)
196 if os.path.exists(filename):
197 searched.append(filename + ":True")
198 sitefiles.append(filename)
199 else:
200 searched.append(filename + ":False")
201
202 # Have to parameterise out hardcoded paths such as COREBASE for the main site files
203 for var in d.getVar("SITEINFO_PATHVARS").split():
204 searched2 = []
205 replace = os.path.normpath(d.getVar(var))
206 for s in searched:
207 searched2.append(s.replace(replace, "${" + var + "}"))
208 searched = searched2
209
210 if bb.data.inherits_class('native', d) or bb.data.inherits_class('cross', d) or bb.data.inherits_class('crosssdk', d):
211 # We need sstate sigs for native/cross not to vary upon arch so we can't depend on the site files.
212 # In future we may want to depend upon all site files?
213 # This would show up as breaking sstatetests.SStateTests.test_sstate_32_64_same_hash for example
214 searched = []
215
216 if not sysrootcache:
217 return sitefiles, searched
218
219 # Now check for siteconfig cache files in sysroots
220 path_siteconfig = d.getVar('SITECONFIG_SYSROOTCACHE')
221 if path_siteconfig and os.path.isdir(path_siteconfig):
222 for i in os.listdir(path_siteconfig):
223 if not i.endswith("_config"):
224 continue
225 filename = os.path.join(path_siteconfig, i)
226 sitefiles.append(filename)
227 return sitefiles, searched
228
229#
230# Make some information available via variables
231#
232SITECONFIG_SYSROOTCACHE = "${STAGING_DATADIR}/${TARGET_SYS}_config_site.d"