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-rw-r--r--meta-moblin/packages/linux/linux-moblin-2.6.31.5/linux-2.6.31-iegd.patch9290
1 files changed, 9290 insertions, 0 deletions
diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.31.5/linux-2.6.31-iegd.patch b/meta-moblin/packages/linux/linux-moblin-2.6.31.5/linux-2.6.31-iegd.patch
new file mode 100644
index 0000000000..fa6a3ea9f1
--- /dev/null
+++ b/meta-moblin/packages/linux/linux-moblin-2.6.31.5/linux-2.6.31-iegd.patch
@@ -0,0 +1,9290 @@
1diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/Kconfig patch_script_temp/drivers/gpu/drm/Kconfig
2--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/Kconfig 2009-08-27 11:30:10.000000000 -0700
3+++ patch_script_temp/drivers/gpu/drm/Kconfig 2009-10-06 10:30:05.000000000 -0700
4@@ -154,3 +154,10 @@
5 Choose this option if you have a Poulsbo or Moorestown platform.
6 If M is selected the module will be called psb.
7
8+
9+config IEGD
10+ tristate "Intel IEGD"
11+ depends on DRM
12+ help
13+ Choose this option for the Intel Embedded Graphics Driver (IEGD)
14+
15diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/Makefile patch_script_temp/drivers/gpu/drm/Makefile
16--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/Makefile 2009-08-27 11:30:10.000000000 -0700
17+++ patch_script_temp/drivers/gpu/drm/Makefile 2009-10-06 10:30:05.000000000 -0700
18@@ -32,3 +32,4 @@
19 obj-$(CONFIG_DRM_SIS) += sis/
20 obj-$(CONFIG_DRM_SAVAGE)+= savage/
21 obj-$(CONFIG_DRM_VIA) +=via/
22+obj-$(CONFIG_IEGD) += iegd/
23diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/Makefile patch_script_temp/drivers/gpu/drm/iegd/Makefile
24--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/Makefile 1969-12-31 17:00:00.000000000 -0700
25+++ patch_script_temp/drivers/gpu/drm/iegd/Makefile 2009-10-06 10:30:05.000000000 -0700
26@@ -0,0 +1,9 @@
27+
28+
29+ccflags-y := -Idrivers/gpu/drm/iegd/include
30+ccflags-y += -Idrivers/char/agp -Iinclude/drm
31+
32+iegd_mod-objs := agp/pci.o agp/global.o agp/drv_alm.o agp/drv_nap.o agp/drv_plb.o agp/drv_cmn.o agp/drv_gn4.o drm/iegd_drv.o drm/iegd_interface.o drm/iegd_interface_265.o drm/iegd_interface_2611.o drm/iegd_interface_2615.o drm/iegd_interface_2624.o drm/psb_irq.o
33+
34+obj-$(CONFIG_IEGD) += iegd_mod.o
35+
36diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/agp_test.c patch_script_temp/drivers/gpu/drm/iegd/agp/agp_test.c
37--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/agp_test.c 1969-12-31 17:00:00.000000000 -0700
38+++ patch_script_temp/drivers/gpu/drm/iegd/agp/agp_test.c 2009-10-06 10:30:05.000000000 -0700
39@@ -0,0 +1,314 @@
40+/* -*- pse-c -*-
41+ *----------------------------------------------------------------------------
42+ * Filename: agp_test.c
43+ * $Revision: 1.5 $
44+ *----------------------------------------------------------------------------
45+ * Unit level test for IEGD AGP
46+ * Copyright © 2009 Intel Corporation.
47+ *
48+ * This program is free software; you can redistribute it and/or modify it
49+ * under the terms and conditions of the GNU General Public License,
50+ * version 2, as published by the Free Software Foundation.
51+ *
52+ * This program is distributed in the hope it will be useful, but WITHOUT
53+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
54+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
55+ * more details.
56+ *
57+ * You should have received a copy of the GNU General Public License along with
58+ * this program; if not, write to the Free Software Foundation, Inc.,
59+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
60+ *
61+ */
62+
63+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
64+ *
65+ * Redistribution and use in source and binary forms, with or without
66+ * modification, are permitted provided that the following conditions are met:
67+ * Redistributions of source code must retain the above copyright notice,
68+ * this list of conditions and the following disclaimer.
69+ *
70+ * Redistributions in binary form must reproduce the above copyright
71+ * notice, this list of conditions and the following disclaimer in the
72+ * documentation and/or other materials provided with the distribution.
73+ *
74+ * Neither the name Intel Corporation nor the names of its contributors
75+ * may be used to endorse or promote products derived from this software
76+ * without specific prior written permission.
77+ *
78+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
79+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
80+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
81+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
82+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
83+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
84+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
85+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
86+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
87+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
88+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
89+ *
90+ */
91+#include <fcntl.h>
92+#include <unistd.h>
93+#include <sys/ioctl.h>
94+#include <stdlib.h>
95+#include <stdio.h>
96+#include <linux/agpgart.h>
97+#include <sys/mman.h>
98+
99+/*#define PAGE_SIZE 1024*/
100+
101+#define VERBOSE "-v"
102+
103+int verbose = 0;
104+int file_desc, temp, length;
105+unsigned char *mmap_gart;
106+
107+int init_agp(void)
108+{
109+ agp_info info;
110+ agp_setup setup;
111+
112+ if (verbose)
113+ {
114+ printf("Testing ioctl AGPIOC_ACQUIRE.\n");
115+ }
116+ if(ioctl(file_desc, AGPIOC_ACQUIRE) != 0)
117+ {
118+ printf("Error on AGPIOC_ACQUIRE.\n");
119+ printf("Reinstall IKM.\n");
120+ exit(-1);
121+ }
122+ if (verbose)
123+ {
124+ printf("Testing ioctl call for info init\n");
125+ }
126+ if(ioctl(file_desc, AGPIOC_INFO, &info) != 0)
127+ {
128+ printf("Error on AGPIOC_INFO\n");
129+ printf("Reinstall IKM.\n");
130+ exit(-1);
131+ }
132+ if (verbose)
133+ {
134+ printf("Testing init info\n version:%i.%i,\n id:0x%lx,\n mode:0x%lx,\n"
135+ " base:0x%lx,\n size:%i,\n total mem:%i,\n system mem:%i,\n"
136+ " used mem:%i\n", info.version.major, info.version.minor,
137+ info.bridge_id, info.agp_mode, info.aper_base, info.aper_size,
138+ info.pg_total, info.pg_system, info.pg_used);
139+
140+ printf("Testing mmap the device\n");
141+ }
142+ length = info.aper_size*0x100000;
143+ mmap_gart = mmap(NULL, info.aper_size*0x100000,
144+ PROT_READ | PROT_WRITE, MAP_SHARED, file_desc, 0);
145+ if(mmap_gart == (unsigned char *) 0xFFFFFFFF)
146+ {
147+ printf("Error on mmap\n");
148+ printf("Reinstall IKM.\n");
149+ close(file_desc);
150+ exit(-1);
151+ }
152+
153+ setup.agp_mode = info.agp_mode;
154+ if (verbose)
155+ {
156+ printf("Testing ioctl AGPIOC_SETUP\n");
157+ }
158+ if(ioctl(file_desc, AGPIOC_SETUP, &setup) != 0)
159+ {
160+ printf("Error on AGPIOC_SETUP\n");
161+ printf("Reinstall IKM.\n");
162+ exit(-1);
163+ }
164+}
165+
166+void gart_unbind(int key)
167+{
168+ agp_unbind unbind;
169+ unbind.key = key;
170+ unbind.priority = 0;
171+ if (verbose)
172+ {
173+ printf("Testing ioctl AGPIOC_UNBIND\n");
174+ }
175+ if(ioctl(file_desc, AGPIOC_UNBIND, &unbind) != 0)
176+ {
177+ printf("Error on AGPIOC_UNBIND\n");
178+ printf("Reinstall IKM.\n");
179+ exit(-1);
180+ }
181+}
182+
183+void gart_bind(int key)
184+{
185+ agp_bind bind;
186+ bind.key = key;
187+ agp_info info;
188+
189+ int page_size = 4000;
190+ int aper_size, gtt_entries, bind_error;
191+
192+ if(ioctl(file_desc, AGPIOC_INFO, &info) != 0)
193+ {
194+ printf("Error on AGPIOC_INFO\n");
195+ printf("Reinstall IKM.\n");
196+ exit(-1);
197+ }
198+ aper_size = info.aper_size;
199+ gtt_entries = aper_size*1000000/page_size;
200+ if (verbose)
201+ {
202+ printf("max memory: %i\n", gtt_entries);
203+ }
204+
205+ do
206+ {
207+ bind_error = 0;
208+ bind.pg_start = page_size;
209+ printf("Testing ioctl AGPIOC_BIND\n");
210+ if(ioctl(file_desc, AGPIOC_BIND, &bind) != 0)
211+ {
212+ if (page_size < gtt_entries)
213+ {
214+ page_size = page_size+4000;
215+ printf("Trying new address for bind %i.\n", page_size);
216+ bind_error = 1;
217+ }
218+ else
219+ {
220+ printf("Error on AGPIOC_BIND\n");
221+ printf("Reinstall IKM.");
222+ exit(-1);
223+ }
224+ }
225+ } while (bind_error);
226+ printf("Sucessful bind.\n");
227+}
228+
229+int gart_alloc(int count)
230+{
231+ agp_allocate allocate;
232+
233+ allocate.type = 0;
234+ allocate.pg_count = count;
235+ if (verbose)
236+ {
237+ printf("Testing ioctl AGPIOC_ALLOCATE\n");
238+ }
239+ if(ioctl(file_desc, AGPIOC_ALLOCATE, &allocate) != 0)
240+ {
241+ printf("Error on AGPIOC_ALLOCATE\n");
242+ printf("Reinstall IKM.");
243+ exit(-1);
244+ }
245+
246+ gart_bind(allocate.key);
247+
248+ return(allocate.key);
249+}
250+
251+void gart_free(int key)
252+{
253+
254+ gart_unbind(key);
255+ if (verbose)
256+ {
257+ printf("Testing ioctl AGPIOC_DEALLOCATE\n");
258+ }
259+ if(ioctl(file_desc, AGPIOC_DEALLOCATE, key) != 0)
260+ {
261+ printf("Error on AGPIOC_DEALLOCATE\n");
262+ printf("Reinstall IKM.\n");
263+ exit(-1);
264+ }
265+}
266+
267+int main(int argc, char *argv[])
268+{
269+ /* Check for verbose mode */
270+ int i, key, key1;
271+ agp_info info;
272+
273+ for (i = 1; i < argc; i++)
274+ {
275+ if(strcmp(argv[1], VERBOSE) == 0)
276+ {
277+ verbose = 1;
278+ printf("Verbose mode.\n");
279+ }
280+ }
281+
282+ /* Open the agpgart */
283+ file_desc=open("/dev/agpgart",O_RDWR);
284+
285+ if(file_desc<0){
286+ printf("Cannot open device file:%d\n",file_desc);
287+ printf("Check for root level permissions.");
288+ exit(-1);
289+ }
290+
291+ if (verbose)
292+ {
293+ printf("Open device file:%d\n",file_desc);
294+ /* This the ioctl that allocates physical memory */
295+ printf("Testing ioctl for memory allocation\n");
296+ }
297+
298+ init_agp();
299+
300+ key = gart_alloc(64);
301+ key1 = gart_alloc(0);
302+ if (verbose)
303+ {
304+ printf("Testing ioctl call for info\n");
305+ }
306+ if(ioctl(file_desc, AGPIOC_INFO, &info) != 0)
307+ {
308+ close(file_desc);
309+ printf("Error on AGPIOC_INFO\n");
310+ printf("Reinstall IKM.\n");
311+ exit(-1);
312+ }
313+
314+ if (verbose)
315+ {
316+ printf("Testing init info\n version:%i.%i,\n id:0x%lx,\n mode:0x%lx,\n"
317+ " base:0x%lx,\n size:%i,\n total mem:%i,\n system mem:%i,\n"
318+ " used mem:%i\n", info.version.major, info.version.minor,
319+ info.bridge_id, info.agp_mode, info.aper_base, info.aper_size,
320+ info.pg_total, info.pg_system, info.pg_used);
321+ }
322+
323+ gart_free(key);
324+ gart_free(key1);
325+
326+ if (munmap(mmap_gart, length) < 0)
327+ {
328+ close(file_desc);
329+ printf("Error on munmap\n");
330+ printf("Reinstall IKM.\n");
331+ exit(-1);
332+ }
333+
334+ if (verbose)
335+ {
336+ printf("Testing ioctl AGPIOC_RELEASE\n");
337+ }
338+ if(ioctl(file_desc, AGPIOC_RELEASE) != 0)
339+ {
340+ close(file_desc);
341+ printf("Error on AGPIOC_RELEASE\n");
342+ printf("Reinstall IKM.");
343+ exit(-1);
344+ }
345+
346+ printf("AGPGART successfully loaded\n");
347+
348+ close(file_desc);
349+
350+ return 0;
351+
352+
353+}
354diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_alm.c patch_script_temp/drivers/gpu/drm/iegd/agp/drv_alm.c
355--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_alm.c 1969-12-31 17:00:00.000000000 -0700
356+++ patch_script_temp/drivers/gpu/drm/iegd/agp/drv_alm.c 2009-10-06 10:30:05.000000000 -0700
357@@ -0,0 +1,447 @@
358+/* -*- pse-c -*-
359+ *----------------------------------------------------------------------------
360+ * Filename: drv_alm.c
361+ * $Revision: 1.7 $
362+ *----------------------------------------------------------------------------
363+ * Gart and DRM driver for Intel Embedded Graphics Driver
364+ * Copyright © 2008, Intel Corporation.
365+ *
366+ * This program is free software; you can redistribute it and/or modify it
367+ * under the terms and conditions of the GNU General Public License,
368+ * version 2, as published by the Free Software Foundation.
369+ *
370+ * This program is distributed in the hope it will be useful, but WITHOUT
371+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
372+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
373+ * more details.
374+ *
375+ * You should have received a copy of the GNU General Public License along with
376+ * this program; if not, write to the Free Software Foundation, Inc.,
377+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
378+ *
379+ */
380+
381+#include "global.h"
382+#include "intelpci.h"
383+
384+static int iegd_alm_configure(void);
385+static int iegd_alm_fetch_size(void);
386+static void iegd_alm_cleanup(void);
387+static void iegd_alm_tlbflush(struct agp_memory *mem);
388+
389+static int iegd_alm_insert_entries(
390+ struct agp_memory *mem,
391+ off_t pg_start,
392+ int type);
393+
394+static int iegd_alm_remove_entries(
395+ struct agp_memory *mem,
396+ off_t pg_start,
397+ int type);
398+
399+struct aper_size_info_fixed intel_i830_sizes[] =
400+{
401+ {128, 32768, 5},
402+ /* The 64M mode still requires a 128k gatt */
403+ {64, 16384, 5},
404+ {256, 65536, 6},
405+ {512, 131072, 7},
406+};
407+
408+struct aper_size_info_fixed intel_i810_sizes[] =
409+{
410+ {64, 16384, 4},
411+ {32, 8192, 4},
412+};
413+
414+bridge_driver_t drv_alm = {
415+ .owner = THIS_MODULE,
416+ .size_type = FIXED_APER_SIZE,
417+ .aperture_sizes = 0,
418+ .num_aperture_sizes = 0,
419+ .needs_scratch_page = TRUE,
420+ .configure = iegd_alm_configure,
421+ .fetch_size = iegd_alm_fetch_size,
422+ .cleanup = iegd_alm_cleanup,
423+ .tlb_flush = iegd_alm_tlbflush,
424+ .mask_memory = iegd_cmn_mask_memory,
425+ .masks = iegd_cmn_masks,
426+ .agp_enable = iegd_cmn_agp_enable,
427+ .cache_flush = global_cache_flush,
428+ .create_gatt_table = NULL,
429+ .free_gatt_table = NULL,
430+ .insert_memory = iegd_alm_insert_entries,
431+ .remove_memory = iegd_alm_remove_entries,
432+ .alloc_by_type = iegd_cmn_alloc_by_type,
433+ .free_by_type = iegd_cmn_free_by_type,
434+ .agp_alloc_page = agp_generic_alloc_page,
435+ .agp_destroy_page = agp_generic_destroy_page,
436+};
437+
438+static int iegd_alm_configure(void)
439+{
440+ struct aper_size_info_fixed *current_size;
441+ u32 temp;
442+ u16 gmch_ctrl;
443+ int i;
444+ int entries_start = 0;
445+
446+ AGN_DEBUG("Enter");
447+
448+ current_size = A_SIZE_FIX(agp_bridge->current_size);
449+
450+ if(private_data.pdev->device == PCI_DEVICE_ID_810 ||
451+ private_data.pdev->device == PCI_DEVICE_ID_810DC ||
452+ private_data.pdev->device == PCI_DEVICE_ID_810E ||
453+ private_data.pdev->device == PCI_DEVICE_ID_815) {
454+
455+ pci_read_config_dword(private_data.pdev, I810_MMADDR, &temp);
456+ temp &= 0xfff80000;
457+
458+ private_data.registers = ioremap(temp, 128*4096);
459+ if(!private_data.registers) {
460+ AGN_ERROR("Unable to remap memory");
461+ return -ENOMEM;
462+ }
463+
464+ if((readl(private_data.registers+I810_DRAM_CTL)
465+ & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
466+ AGN_LOG("Detected 4MB dedicated video RAM.");
467+ private_data.num_dcache_entries = 1024;
468+ }
469+ } else if(private_data.pdev->device == PCI_DEVICE_ID_830M ||
470+ private_data.pdev->device == PCI_DEVICE_ID_845G ||
471+ private_data.pdev->device == PCI_DEVICE_ID_855 ||
472+ private_data.pdev->device == PCI_DEVICE_ID_865G) {
473+
474+ entries_start = private_data.gtt_entries;
475+ pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
476+ gmch_ctrl |= I830_GMCH_ENABLED;
477+ pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
478+ }
479+
480+ /* Get based address of the graphic aperture */
481+ pci_read_config_dword(private_data.pdev, I810_GMADDR, &temp);
482+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
483+
484+ /* Write the based address of the gtt table to the
485+ * page table control register */
486+ writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED,
487+ private_data.registers+I810_PGETBL_CTL);
488+ readl(private_data.registers+I810_PGETBL_CTL);
489+
490+ if (agp_bridge->driver->needs_scratch_page) {
491+ for (i = entries_start; i < current_size->num_entries; i++) {
492+ writel(agp_bridge->scratch_page,
493+ private_data.registers+I810_PTE_BASE+(i*4));
494+ /* PCI Posting. */
495+ readl(private_data.registers+I810_PTE_BASE+(i*4));
496+ }
497+ }
498+
499+ global_cache_flush();
500+
501+ AGN_DEBUG("Exit");
502+ return 0;
503+}
504+
505+
506+static int iegd_alm_fetch_size(void)
507+{
508+ u32 smram_miscc;
509+ u16 gmch_ctrl;
510+ struct aper_size_info_fixed *values;
511+
512+ AGN_DEBUG("Enter");
513+
514+ values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
515+
516+ if(private_data.pdev->device == PCI_DEVICE_ID_810 ||
517+ private_data.pdev->device == PCI_DEVICE_ID_810DC ||
518+ private_data.pdev->device == PCI_DEVICE_ID_810E ||
519+ private_data.pdev->device == PCI_DEVICE_ID_815) {
520+
521+ pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC,
522+ &smram_miscc);
523+
524+ if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
525+ printk(KERN_WARNING PFX "i810 is disabled\n");
526+ return 0;
527+ }
528+ if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) ==
529+ I810_GFX_MEM_WIN_32M) {
530+ agp_bridge->previous_size =
531+ agp_bridge->current_size = (void *) (values + 1);
532+ agp_bridge->aperture_size_idx = 1;
533+ return values[1].size;
534+ } else {
535+ agp_bridge->previous_size =
536+ agp_bridge->current_size = (void *) (values);
537+ agp_bridge->aperture_size_idx = 0;
538+ return values[0].size;
539+ }
540+ } else if(private_data.pdev->device == PCI_DEVICE_ID_830M ||
541+ private_data.pdev->device == PCI_DEVICE_ID_845G ||
542+ private_data.pdev->device == PCI_DEVICE_ID_855 ||
543+ private_data.pdev->device == PCI_DEVICE_ID_865G) {
544+
545+ if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
546+ agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
547+ /* 855GM/852GM/865G has 128MB aperture size */
548+ agp_bridge->previous_size =
549+ agp_bridge->current_size = (void *) values;
550+ agp_bridge->aperture_size_idx = 0;
551+ return values[0].size;
552+ }
553+
554+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
555+
556+ if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
557+ agp_bridge->previous_size =
558+ agp_bridge->current_size = (void *) values;
559+ agp_bridge->aperture_size_idx = 0;
560+ return values[0].size;
561+ } else {
562+ agp_bridge->previous_size =
563+ agp_bridge->current_size = (void *) (values + 1);
564+ agp_bridge->aperture_size_idx = 1;
565+ return values[1].size;
566+ }
567+ }
568+
569+ AGN_DEBUG("Exit");
570+
571+ return 0;
572+}
573+
574+static void iegd_alm_cleanup(void)
575+{
576+
577+ AGN_DEBUG("Enter");
578+
579+ if(private_data.pdev->device == PCI_DEVICE_ID_810 ||
580+ private_data.pdev->device == PCI_DEVICE_ID_810DC ||
581+ private_data.pdev->device == PCI_DEVICE_ID_810E ||
582+ private_data.pdev->device == PCI_DEVICE_ID_815) {
583+
584+ writel(0, private_data.registers+I810_PGETBL_CTL);
585+ readl(private_data.registers); /* PCI Posting. */
586+ }
587+
588+ /* Unmap the mapping of the mmio */
589+ iounmap((void *) private_data.registers);
590+
591+ AGN_DEBUG("Exit");
592+}
593+
594+static void iegd_alm_tlbflush(struct agp_memory *mem)
595+{
596+ AGN_DEBUG("Enter");
597+ return;
598+ AGN_DEBUG("Exit");
599+}
600+
601+int AGP_CREATE_GATT(iegd_alm_create_gatt_table)
602+{
603+ int num_entries = 0;
604+ int i830_gtt_page_order = 0;
605+ u32 gtt_bus_addr = 0;
606+ u32 mmio_bus_addr = 0;
607+ char *gtt_table = NULL;
608+ char *gtt_table_end = NULL;
609+ char *current_entry = NULL;
610+ int gtt_enabled = FALSE;
611+ struct page *gtt_table_page = NULL;
612+ struct aper_size_info_fixed *aper_size = NULL;
613+
614+ AGN_DEBUG("Enter");
615+
616+ agp_bridge->gatt_table_real = NULL;
617+ agp_bridge->gatt_table = NULL;
618+ aper_size = (struct aper_size_info_fixed *)agp_bridge->current_size;
619+
620+ /* Find and save the address of the MMIO registers */
621+ pci_read_config_dword(private_data.pdev, I810_MMADDR,
622+ &mmio_bus_addr);
623+ mmio_bus_addr &= 0xFFF80000;
624+
625+ private_data.registers = (volatile u8 *)
626+ ioremap(mmio_bus_addr, 128 * 4096);
627+
628+ if (!private_data.registers) {
629+ AGN_ERROR("ioremap failed to map");
630+ return (-ENOMEM);
631+ }
632+
633+ /* Get value on the control register */
634+ gtt_bus_addr = readl(private_data.registers+I810_PGETBL_CTL) &
635+ 0xFFFFF000;
636+ gtt_enabled = readl(private_data.registers+I810_PGETBL_CTL) &
637+ I810_PGETBL_ENABLED;
638+ global_cache_flush();
639+
640+ /* we have to call this as early as possible after the MMIO base address
641+ * is known */
642+ iegd_cmn_init_gtt_entries();
643+
644+ /* If GTT does not exist, which can happen if a PCI graphics card is the
645+ * boot-up display device, then we will have to allocate the GTT table
646+ * ourselves
647+ */
648+ if (!gtt_enabled) {
649+
650+ AGN_DEBUG("Gtt is disabled");
651+
652+ i830_gtt_page_order = aper_size->page_order;
653+ num_entries = aper_size->num_entries;
654+ gtt_table = (char *) __get_free_pages(
655+ GFP_KERNEL, i830_gtt_page_order);
656+ gtt_table_end = gtt_table +
657+ ((PAGE_SIZE * (1<<i830_gtt_page_order)) - 1);
658+
659+ /* Make sure allocation was successful */
660+ if (NULL == gtt_table) {
661+ AGN_ERROR("Fail to allocate kernel memory");
662+ return -ENOMEM;
663+ }
664+
665+ for (current_entry = gtt_table; current_entry < gtt_table_end;
666+ current_entry += PAGE_SIZE) {
667+ gtt_table_page = virt_to_page(current_entry);
668+ set_bit(PG_reserved, &gtt_table_page->flags);
669+ }
670+ agp_bridge->gatt_bus_addr = virt_to_phys(gtt_table);
671+ } else {
672+ agp_bridge->gatt_bus_addr = gtt_bus_addr;
673+ }
674+
675+ AGN_DEBUG("Exit");
676+ return(0);
677+}
678+
679+
680+static int iegd_alm_insert_entries(
681+ struct agp_memory *mem,
682+ off_t pg_start,
683+ int type)
684+{
685+ int i, j, num_entries;
686+ void *temp;
687+
688+ AGN_DEBUG("Enter");
689+
690+ temp = agp_bridge->current_size;
691+ num_entries = A_SIZE_FIX(temp)->num_entries;
692+
693+ if ((pg_start + mem->page_count) > num_entries) {
694+ AGN_ERROR("Trying to write beyond aperture limit");
695+ AGN_DEBUG("pg_start=0x%.8lx, mem->page_count=%d,"
696+ "num_entries=%d", pg_start, mem->page_count,
697+ num_entries);
698+ return -EINVAL;
699+ }
700+
701+ if(private_data.pdev->device == PCI_DEVICE_ID_830M ||
702+ private_data.pdev->device == PCI_DEVICE_ID_845G ||
703+ private_data.pdev->device == PCI_DEVICE_ID_855 ||
704+ private_data.pdev->device == PCI_DEVICE_ID_865G) {
705+
706+ if (pg_start < private_data.gtt_entries) {
707+ AGN_ERROR("Trying to insert into local/stolen memory");
708+ AGN_DEBUG("pg_start == 0x%.8lx,private_data.gtt_entries =="
709+ "0x%.8x", pg_start,private_data.gtt_entries);
710+ return -EINVAL;
711+ }
712+ } else if(private_data.pdev->device == PCI_DEVICE_ID_810 ||
713+ private_data.pdev->device == PCI_DEVICE_ID_810DC ||
714+ private_data.pdev->device == PCI_DEVICE_ID_810E ||
715+ private_data.pdev->device == PCI_DEVICE_ID_815) {
716+
717+ for (j = pg_start; j < (pg_start + mem->page_count); j++) {
718+ if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
719+ AGN_ERROR("Device busy");
720+ return -EBUSY;
721+ }
722+ }
723+ if (type != 0 || mem->type != 0) {
724+ if ((type == AGP_DCACHE_MEMORY) &&
725+ (mem->type == AGP_DCACHE_MEMORY)) {
726+ /* special insert */
727+ global_cache_flush();
728+ for (i = pg_start; i < (pg_start + mem->page_count);
729+ i++) {
730+ writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
731+ private_data.registers+I810_PTE_BASE+(i*4));
732+ /* PCI Posting. */
733+ readl(private_data.registers +
734+ I810_PTE_BASE+(i*4));
735+ }
736+ global_cache_flush();
737+ agp_bridge->driver->tlb_flush(mem);
738+ AGN_DEBUG("AGP_DCACHE_MEMORY.. Exit");
739+ return 0;
740+ }
741+ }
742+ }
743+
744+ if ((type != 0 && type != AGP_PHYS_MEMORY) ||
745+ (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) {
746+ AGN_ERROR("Unsupported memory type");
747+ AGN_DEBUG("mem->type=%x", mem->type);
748+ return -EINVAL;
749+ }
750+
751+ global_cache_flush();
752+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
753+ writel(AGP_MASK_GTT(), private_data.registers+I810_PTE_BASE+(j*4));
754+ /* PCI Posting. */
755+ readl(private_data.registers+I810_PTE_BASE+(j*4));
756+ }
757+
758+ global_cache_flush();
759+ agp_bridge->driver->tlb_flush(mem);
760+
761+ AGN_DEBUG("Exit");
762+
763+ return 0;
764+}
765+
766+static int iegd_alm_remove_entries(
767+ struct agp_memory *mem,
768+ off_t pg_start,
769+ int type)
770+{
771+ int i;
772+
773+ AGN_DEBUG("Enter");
774+
775+ global_cache_flush();
776+
777+ if(private_data.pdev->device == PCI_DEVICE_ID_830M ||
778+ private_data.pdev->device == PCI_DEVICE_ID_845G ||
779+ private_data.pdev->device == PCI_DEVICE_ID_855 ||
780+ private_data.pdev->device == PCI_DEVICE_ID_865G) {
781+
782+ if (pg_start < private_data.gtt_entries) {
783+ AGN_ERROR("Trying to disable local/stolen memory");
784+ AGN_DEBUG("pg_start=0x%.8lx, private_data.gtt_entries=%d",
785+ pg_start, private_data.gtt_entries);
786+ return -EINVAL;
787+ }
788+ }
789+
790+ for (i = pg_start; i < (mem->page_count + pg_start); i++) {
791+ writel(agp_bridge->scratch_page,
792+ private_data.registers+I810_PTE_BASE+(i*4));
793+ /* PCI Posting. */
794+ readl(private_data.registers+I810_PTE_BASE+(i*4));
795+ }
796+
797+ global_cache_flush();
798+ agp_bridge->driver->tlb_flush(mem);
799+
800+ AGN_DEBUG("Exit");
801+
802+ return 0;
803+}
804+
805diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_cmn.c patch_script_temp/drivers/gpu/drm/iegd/agp/drv_cmn.c
806--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_cmn.c 1969-12-31 17:00:00.000000000 -0700
807+++ patch_script_temp/drivers/gpu/drm/iegd/agp/drv_cmn.c 2009-10-06 10:30:05.000000000 -0700
808@@ -0,0 +1,682 @@
809+/* -*- pse-c -*-
810+ *----------------------------------------------------------------------------
811+ * Filename: drv_cmn.c
812+ * $Revision: 1.28 $
813+ *----------------------------------------------------------------------------
814+ * Gart and DRM driver for Intel Embedded Graphics Driver
815+ * Copyright © 2008, Intel Corporation.
816+ *
817+ * This program is free software; you can redistribute it and/or modify it
818+ * under the terms and conditions of the GNU General Public License,
819+ * version 2, as published by the Free Software Foundation.
820+ *
821+ * This program is distributed in the hope it will be useful, but WITHOUT
822+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
823+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
824+ * more details.
825+ *
826+ * You should have received a copy of the GNU General Public License along with
827+ * this program; if not, write to the Free Software Foundation, Inc.,
828+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
829+ *
830+ */
831+
832+#include <linux/pagemap.h>
833+#include "global.h"
834+#include "intelpci.h"
835+#include "interface_abs.h"
836+#include "igd_abs.h"
837+
838+static struct agp_memory *alloc_agpphysmem_i8xx(
839+ size_t pg_count, int type);
840+static AGP_MEM_TYPE i8xx_alloc_pages(size_t pg_count,
841+ unsigned int order);
842+
843+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
844+static void i8xx_destroy_pages_by_addr(void *addr,
845+ size_t pg_count, unsigned int order);
846+#define PAGES_OR_MEMORY(a) gart_to_virt(a->memory[0])
847+#define DESTROY_PAGES i8xx_destroy_pages_by_addr
848+#else
849+static void i8xx_destroy_pages(struct page **pages,
850+ size_t pg_count, unsigned int order);
851+#define PAGES_OR_MEMORY(a) a->pages
852+#define DESTROY_PAGES i8xx_destroy_pages
853+#endif
854+
855+dispatch_table_t driver_dispatch_list[] = {
856+ { PCI_DEVICE_ID_810, &drv_alm },
857+ { PCI_DEVICE_ID_810DC, &drv_alm },
858+ { PCI_DEVICE_ID_810E, &drv_alm },
859+ { PCI_DEVICE_ID_815, &drv_alm },
860+ { PCI_DEVICE_ID_830M, &drv_alm },
861+ { PCI_DEVICE_ID_845G, &drv_alm },
862+ { PCI_DEVICE_ID_855, &drv_alm },
863+ { PCI_DEVICE_ID_865G, &drv_alm },
864+ { PCI_DEVICE_ID_915GD, &drv_nap },
865+ { PCI_DEVICE_ID_915AL, &drv_nap },
866+ { PCI_DEVICE_ID_945G, &drv_nap },
867+ { PCI_DEVICE_ID_945GM, &drv_nap },
868+ { PCI_DEVICE_ID_945GME,&drv_nap },
869+ { PCI_DEVICE_ID_Q35, &drv_nap },
870+ { PCI_DEVICE_ID_Q35A2, &drv_nap },
871+ { PCI_DEVICE_ID_965G, &drv_gn4 },
872+ { PCI_DEVICE_ID_946GZ, &drv_gn4 },
873+ { PCI_DEVICE_ID_G965, &drv_gn4 },
874+ { PCI_DEVICE_ID_Q965, &drv_gn4 },
875+ { PCI_DEVICE_ID_GM965, &drv_gn4 },
876+ { PCI_DEVICE_ID_GME965,&drv_gn4 },
877+ { PCI_DEVICE_ID_GM45, &drv_gm45},
878+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
879+ { PCI_DEVICE_ID_PLB, &drv_plb },
880+#endif
881+ { PCI_DEVICE_ID_ELK, &drv_gm45},
882+ { PCI_DEVICE_ID_Q45, &drv_gm45},
883+ { PCI_DEVICE_ID_G45, &drv_gm45},
884+ { PCI_DEVICE_ID_G41, &drv_gm45},
885+ { 0, NULL },
886+};
887+
888+/* Structure contained bit mask for the page table entries */
889+struct gatt_mask iegd_cmn_masks[] =
890+{
891+ {.mask = I810_PTE_VALID, .type = 0},
892+ {.mask = (I810_PTE_VALID | I810_PTE_LOCAL),
893+ .type = AGP_DCACHE_MEMORY},
894+ {.mask = I810_PTE_VALID, .type = 0}
895+};
896+
897+
898+int iegd_cmn_configure(void)
899+{
900+ struct aper_size_info_fixed *current_size;
901+ u32 temp;
902+ u16 gmch_ctrl;
903+ int i;
904+
905+ AGN_DEBUG("Enter");
906+
907+ current_size = A_SIZE_FIX(agp_bridge->current_size);
908+
909+ pci_read_config_dword(private_data.pdev, I915_GMADDR, &temp);
910+
911+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
912+
913+ if(!((private_data.pdev->device == PCI_DEVICE_ID_Q35) ||
914+ (private_data.pdev->device == PCI_DEVICE_ID_Q35A2))) {
915+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
916+ gmch_ctrl |= I830_GMCH_ENABLED;
917+ pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
918+
919+ global_cache_flush();
920+ agp_bridge->driver->tlb_flush(0);
921+
922+ writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED,
923+ private_data.registers+I810_PGETBL_CTL);
924+ /* PCI Posting. */
925+ readl(private_data.registers+I810_PGETBL_CTL);
926+ }
927+
928+ AGN_DEBUG ("gtt_entries: %X", private_data.gtt_entries);
929+ if (agp_bridge->driver->needs_scratch_page) {
930+ for (i = private_data.gtt_entries;
931+ i < current_size->num_entries; i++) {
932+ writel(agp_bridge->scratch_page, private_data.gtt+i);
933+ readl(private_data.gtt+i); /* PCI Posting. */
934+ }
935+ }
936+ global_cache_flush();
937+
938+ AGN_DEBUG("Exit");
939+
940+ return 0;
941+}
942+
943+void iegd_cmn_init_gtt_entries(void)
944+{
945+ u16 gmch_ctrl;
946+ u32 iegd_scratch, iegd_scratch2;
947+ int gtt_entries;
948+ u8 rdct;
949+ int local = 0;
950+ static const int ddt[4] = { 0, 16, 32, 64 };
951+ int size;
952+ int gtt_enabled = FALSE;
953+
954+ AGN_DEBUG("Enter");
955+
956+ /* This code original read the GMCH_CTRL register of the host
957+ * bridge. This register is also mirrored on the VGA device at
958+ * the same address. In the PLB family, the host bridge no
959+ * longer contains the register. As a result, all platforms
960+ * will now use the mirrored register. This breaks
961+ * compatability with chipsets prior to 915G
962+ */
963+ pci_read_config_word(private_data.pdev, I830_GMCH_CTRL, &gmch_ctrl);
964+
965+ gtt_enabled = readl(private_data.registers + I810_PGETBL_CTL) &
966+ I810_PGETBL_ENABLED;
967+
968+ /* A note on stolen memory:
969+ * Intel chipsets set aside a small area at the top of system memory
970+ * for VGA framebuffers etc. When the Intel device is the VGA
971+ * device, this memory is used to contain the GTT itself, and a scratch
972+ * memory page. Therefore the actual available memory already populated
973+ * in the GTT is the stolen memory minus the 4k scratch page minus the
974+ * 128 page table.
975+ *
976+ * Additionally, the embedded firmware may further alter this amount.
977+ * It can either allocate additional memory to be placed in the GTT
978+ * or use some stolen memory for data. If the IEGD vBIOS has altered
979+ * the amount we can detect it by reading a well-defined scratch
980+ * register.
981+ *
982+ * When the Intel Graphics Device is not the VGA device, i.e.
983+ * the system boots with a PCI card, then this driver discards
984+ * the stolen memory.
985+ *
986+ * We obtain the size of the GTT, which is also stored (for some
987+ * reason) at the top of stolen memory. Then we add 4KB to that
988+ * for the video BIOS popup, which is also stored in there. */
989+
990+ size = agp_bridge->driver->fetch_size() + 4;
991+ AGN_DEBUG("Size from fetch size + 4 = %x", size);
992+
993+ if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
994+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
995+ switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
996+ case I830_GMCH_GMS_STOLEN_512:
997+ gtt_entries = KB(512) - KB(size);
998+ break;
999+ case I830_GMCH_GMS_STOLEN_1024:
1000+ gtt_entries = MB(1) - KB(size);
1001+ break;
1002+ case I830_GMCH_GMS_STOLEN_8192:
1003+ gtt_entries = MB(8) - KB(size);
1004+ break;
1005+ case I830_GMCH_GMS_LOCAL:
1006+ rdct = readb(private_data.registers+I830_RDRAM_CHANNEL_TYPE);
1007+ gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
1008+ MB(ddt[I830_RDRAM_DDT(rdct)]);
1009+ local = 1;
1010+ break;
1011+ default:
1012+ gtt_entries = 0;
1013+ break;
1014+ }
1015+ } else {
1016+ switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
1017+ case I855_GMCH_GMS_STOLEN_1M:
1018+ gtt_entries = MB(1) - KB(size);
1019+ break;
1020+ case I855_GMCH_GMS_STOLEN_4M:
1021+ gtt_entries = MB(4) - KB(size);
1022+ break;
1023+ case I855_GMCH_GMS_STOLEN_8M:
1024+ gtt_entries = MB(8) - KB(size);
1025+ break;
1026+ case I855_GMCH_GMS_STOLEN_16M:
1027+ gtt_entries = MB(16) - KB(size);
1028+ break;
1029+ case I855_GMCH_GMS_STOLEN_32M:
1030+ gtt_entries = MB(32) - KB(size);
1031+ break;
1032+ case I915_GMCH_GMS_STOLEN_48M:
1033+ /* Check it's really I915G */
1034+ if (agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_915GD ||
1035+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_915AL ||
1036+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945G ||
1037+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945GM ||
1038+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945GME ||
1039+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_965G ||
1040+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_G965 ||
1041+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_Q965 ||
1042+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_GM965 ||
1043+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_GME965 ||
1044+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_946GZ )
1045+ gtt_entries = MB(48) - KB(size);
1046+ else
1047+ gtt_entries = 0;
1048+ break;
1049+ case I915_GMCH_GMS_STOLEN_64M:
1050+ /* Check it's really I915G */
1051+ if (agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_915GD ||
1052+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_915AL ||
1053+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945G ||
1054+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945GM ||
1055+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_945GME ||
1056+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_965G ||
1057+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_G965 ||
1058+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_Q965 ||
1059+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_GM965 ||
1060+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_GME965 ||
1061+ agp_bridge->dev->device == PCI_DEVICE_ID_BRIDGE_946GZ )
1062+ gtt_entries = MB(64) - KB(size);
1063+ else
1064+ gtt_entries = 0;
1065+ default:
1066+ gtt_entries = 0;
1067+ break;
1068+ }
1069+ }
1070+
1071+ /* if GTT is not enabled, then initialize gtt entries to 0 */
1072+
1073+ if (!gtt_entries) {
1074+ AGN_DEBUG("GTT is disabled");
1075+ AGN_LOG("IGD not primary, throwing away stolen memory.");
1076+
1077+ /* Update the scratch registers to say that we have no stolen memory */
1078+ writel((0xE1DF << 16), private_data.registers + 0x71410);
1079+
1080+ iegd_scratch = readl(private_data.registers + 0x71410);
1081+ iegd_scratch |= 0x4;
1082+
1083+ writel(iegd_scratch, private_data.registers + 0x71410);
1084+
1085+ /* say that we have 0 stolen memory regardless of what was
1086+ * really in there */
1087+ writel(0, private_data.registers + 0x71418);
1088+
1089+ gtt_entries = 0;
1090+ }
1091+
1092+ iegd_scratch = readl(private_data.registers + 0x71410);
1093+
1094+ if(((iegd_scratch>>16) == 0xE1DF) && (iegd_scratch & 0x4)) {
1095+ AGN_LOG("IEGD Firmware Detected");
1096+ /* IEGD firmware found, and Mem Reservation Flag present */
1097+ iegd_scratch2 = readl(private_data.registers + 0x71418);
1098+ gtt_entries = (iegd_scratch2 & 0xFFFF) * 4096;
1099+ }
1100+
1101+ if (gtt_entries > 0)
1102+ AGN_LOG("Detected %dK %s memory.",
1103+ gtt_entries / KB(1), local ? "local" : "stolen");
1104+ else
1105+ AGN_LOG("No pre-allocated video memory detected.\n");
1106+
1107+ gtt_entries /= KB(4);
1108+ private_data.gtt_entries = gtt_entries;
1109+
1110+ AGN_DEBUG("Exit");
1111+}
1112+
1113+int AGP_FREE_GATT(iegd_cmn_free_gatt_table)
1114+{
1115+ AGN_DEBUG("Enter");
1116+ return 0;
1117+ AGN_DEBUG("Exit");
1118+}
1119+
1120+void AGP_ENABLE(iegd_cmn_agp_enable)
1121+{
1122+ AGN_DEBUG("Enter");
1123+ return;
1124+ AGN_DEBUG("Exit");
1125+}
1126+
1127+struct agp_memory *iegd_cmn_alloc_by_type(
1128+ size_t pg_count, int type)
1129+{
1130+ struct agp_memory *new;
1131+
1132+ AGN_DEBUG("Enter");
1133+
1134+ /* AGP_DCACHE_MEMORY use by certain chipset only, especially
1135+ * chipset from almador family. */
1136+ if(private_data.pdev->device == PCI_DEVICE_ID_810 ||
1137+ private_data.pdev->device == PCI_DEVICE_ID_810DC ||
1138+ private_data.pdev->device == PCI_DEVICE_ID_810E ||
1139+ private_data.pdev->device == PCI_DEVICE_ID_815) {
1140+ if (type == AGP_DCACHE_MEMORY) {
1141+ if (pg_count != private_data.num_dcache_entries) {
1142+ AGN_ERROR("Page count error");
1143+ AGN_DEBUG("pg_count=%d, num_dcache_entries=%d",
1144+ pg_count, private_data.num_dcache_entries);
1145+ return NULL;
1146+ }
1147+
1148+ new = agp_create_memory(1);
1149+ if (new == NULL) {
1150+ AGN_ERROR("Allocating memory failed");
1151+ return NULL;
1152+ }
1153+
1154+ new->type = AGP_DCACHE_MEMORY;
1155+ new->page_count = pg_count;
1156+ new->num_scratch_pages = 0;
1157+ vfree(new->AGP_MEMORY_MEMBER); //free pages or memory
1158+ AGN_DEBUG("AGP_DCACHE_MEMORY.. Exit");
1159+ return new;
1160+ }
1161+ }
1162+
1163+ if (type == AGP_PHYS_MEMORY) {
1164+ AGN_DEBUG("AGP_PHYS_MEMORY.. Exit");
1165+ return alloc_agpphysmem_i8xx(pg_count, type);
1166+ }
1167+
1168+ AGN_DEBUG("NULL.. Exit");
1169+ return NULL;
1170+}
1171+
1172+void iegd_cmn_free_by_type(struct agp_memory *curr)
1173+{
1174+ unsigned int order;
1175+
1176+ AGN_DEBUG("Enter");
1177+
1178+ switch (curr->page_count) {
1179+ case 1:
1180+ order = 0; /* pg_count = 1 => 2 ^ 0 */
1181+ break;
1182+ case 4:
1183+ order = 2; /* pg_count = 4 => 2 ^ 2 */
1184+ break;
1185+ case 8:
1186+ order = 3; /* pg_count = 8 => 2 ^ 3 */
1187+ break;
1188+ default:
1189+ /* This case should never happen */
1190+ return;
1191+ }
1192+
1193+ agp_free_key(curr->key);
1194+ if(curr->type == AGP_PHYS_MEMORY) {
1195+ DESTROY_PAGES(PAGES_OR_MEMORY(curr), curr->page_count,
1196+ order);
1197+ IGD_FREE_MEM(curr);
1198+ }
1199+ kfree(curr);
1200+
1201+ AGN_DEBUG("Exit");
1202+}
1203+
1204+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
1205+static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
1206+{
1207+ struct agp_memory *new;
1208+ void *addr;
1209+ unsigned int order, i;
1210+
1211+ AGN_DEBUG("Enter");
1212+
1213+ /* To support RGBA hardware cursor which may require contiguous physical
1214+ * * memory to be allocated with either 1, 4 or 8 pages. 8 pages is
1215+ * * the worst case for 830 which requires 4 pages and 4 page alignment.
1216+ * */
1217+ switch (pg_count) {
1218+ case 1:
1219+ order = 0; /* pg_count = 1 => 2 ^ 0 */
1220+ break;
1221+ case 4:
1222+ order = 2; /* pg_count = 4 => 2 ^ 2 */
1223+ break;
1224+ case 8:
1225+ order = 3; /* pg_count = 8 => 2 ^ 3 */
1226+ break;
1227+ default:
1228+ return NULL;
1229+ }
1230+
1231+ addr = i8xx_alloc_pages(pg_count, order);
1232+ if (addr == NULL) {
1233+ AGN_ERROR("Allocating pages failed");
1234+ return NULL;
1235+ }
1236+
1237+ new = agp_create_memory(pg_count);
1238+ if (new == NULL) {
1239+ AGN_ERROR("Allocating memory failed");
1240+ return NULL;
1241+ }
1242+
1243+ new->memory[0] = virt_to_gart(addr);
1244+ for (i = 1; i < pg_count; i++) {
1245+ new->memory[i] = new->memory[i-1] + PAGE_SIZE;
1246+ }
1247+ new->page_count = pg_count;
1248+ new->num_scratch_pages = pg_count;
1249+ new->type = AGP_PHYS_MEMORY;
1250+ new->physical = new->memory[0];
1251+
1252+ AGN_DEBUG("Exit");
1253+ return new;
1254+}
1255+#else // kernel 31 or newer
1256+static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
1257+{
1258+ struct agp_memory *new;
1259+ struct page *page;
1260+ unsigned int order, i;
1261+
1262+ AGN_DEBUG("Enter");
1263+
1264+ /* To support RGBA hardware cursor which may require contiguous physical
1265+ * memory to be allocated with either 1, 4 or 8 pages. 8 pages is
1266+ * the worst case for 830 which requires 4 pages and 4 page alignment.
1267+ */
1268+ switch (pg_count) {
1269+ case 1:
1270+ order = 0; /* pg_count = 1 => 2 ^ 0 */
1271+ break;
1272+ case 4:
1273+ order = 2; /* pg_count = 4 => 2 ^ 2 */
1274+ break;
1275+ case 8:
1276+ order = 3; /* pg_count = 8 => 2 ^ 3 */
1277+ break;
1278+ default:
1279+ return NULL;
1280+ }
1281+
1282+ page = i8xx_alloc_pages(pg_count, order);
1283+ if (page == NULL) {
1284+ AGN_ERROR("Allocating pages failed");
1285+ return NULL;
1286+ }
1287+
1288+ new = agp_create_memory(pg_count);
1289+ if (new == NULL) {
1290+ AGN_ERROR("Allocating memory failed");
1291+ return NULL;
1292+ }
1293+
1294+ new->pages[0] = page;
1295+ if (pg_count > 1) { // if page count is 4 or 8
1296+ for (i=0; i< pg_count-1; i++) {
1297+ new->pages[i+1] = new->pages[i] + 1;
1298+ }
1299+ }
1300+ new->page_count = pg_count;
1301+ new->num_scratch_pages = pg_count;
1302+ new->type = AGP_PHYS_MEMORY;
1303+ new->physical = page_to_phys(new->pages[0]);
1304+ return new;
1305+
1306+ AGN_DEBUG("Exit");
1307+}
1308+#endif
1309+
1310+static AGP_MEM_TYPE i8xx_alloc_pages(size_t pg_count, unsigned int order)
1311+{
1312+ struct page * page;
1313+
1314+ AGN_DEBUG("Enter");
1315+
1316+ page = alloc_pages(GFP_KERNEL, order);
1317+ if (page == NULL) {
1318+ AGN_ERROR("Allocating kernel page failed");
1319+ return NULL;
1320+ }
1321+
1322+ if (SET_PAGES_UC(page, pg_count) < 0) {
1323+ SET_PAGES_WB(page, pg_count);
1324+ GLOBAL_FLUSH_TLB();
1325+ __free_pages(page, pg_count);
1326+ AGN_ERROR("Change page attribute failed");
1327+ return NULL;
1328+ }
1329+ GLOBAL_FLUSH_TLB();
1330+ get_page(page);
1331+
1332+ /*
1333+ * Starting kernel 2.6.23 locking will causing lot of trouble. This is
1334+ * because of the changes in page fault handler in the kernel.
1335+ */
1336+ AGP_LOCK_PAGE(page);
1337+ atomic_inc(&agp_bridge->current_memory_agp);
1338+ return PAGE_ADDRESS(page); //returns page or addr depending on kernel
1339+
1340+ AGN_DEBUG("Exit");
1341+}
1342+
1343+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
1344+static void i8xx_destroy_pages_by_addr(void *addr,
1345+ size_t pg_count, unsigned int order)
1346+{
1347+ struct page *page;
1348+
1349+ AGN_DEBUG("Enter");
1350+
1351+ if (addr == NULL)
1352+ return;
1353+
1354+ page = virt_to_page(addr);
1355+ SET_PAGES_WB(page, pg_count);
1356+ GLOBAL_FLUSH_TLB();
1357+ put_page(page);
1358+ /*
1359+ * Starting kernel 2.6.23 locking will causing lot of trouble. This is
1360+ * because of the changes in page fault handler in the kernel.
1361+ */
1362+ AGP_UNLOCK_PAGE(page);
1363+
1364+ free_pages((unsigned long)addr, order);
1365+ atomic_dec(&agp_bridge->current_memory_agp);
1366+
1367+ AGN_DEBUG("Exit");
1368+}
1369+
1370+#else //kernel is 31 or newer
1371+static void i8xx_destroy_pages(struct page **pages,
1372+ size_t pg_count, unsigned int order)
1373+{
1374+ struct page *page;
1375+ int i;
1376+
1377+ AGN_DEBUG("Enter");
1378+
1379+ if (pages == NULL)
1380+ return;
1381+
1382+ GLOBAL_FLUSH_TLB();
1383+ //The following code is based on agp_generic_destroy_pages in generic.c
1384+ for (i = 0; i < pg_count; i++) {
1385+ page = pages[i];
1386+
1387+ put_page(page);
1388+ __free_page(page);
1389+ atomic_dec(&agp_bridge->current_memory_agp);
1390+ pages[i] = NULL;
1391+ }
1392+
1393+ AGN_DEBUG("Exit");
1394+}
1395+#endif
1396+
1397+unsigned long AGP_MASK_MEMORY(iegd_cmn_mask_memory)
1398+{
1399+ struct agp_bridge_data *brdg = AGP_BRIDGE_VAR;
1400+
1401+ // only converts if kernel is 2.6.31 or newer
1402+ unsigned long address = CONVERT_PAGE_TO_GART(addr);
1403+
1404+ /* Type checking must be done elsewhere */
1405+ return address | AGP_MASK_ADDR(brdg);
1406+}
1407+
1408+int iegd_cmn_insert_entries(struct agp_memory *mem,
1409+ off_t pg_start, int type)
1410+{
1411+ int i,j,num_entries;
1412+ void *temp;
1413+
1414+ AGN_DEBUG("Enter");
1415+
1416+ temp = agp_bridge->current_size;
1417+ num_entries = A_SIZE_FIX(temp)->num_entries;
1418+
1419+ if (pg_start < private_data.gtt_entries) {
1420+ AGN_ERROR("Trying to insert into local/stolen memory");
1421+ AGN_DEBUG("pg_start == 0x%.8lx,private_data.gtt_entries =="
1422+ "%d", pg_start,private_data.gtt_entries);
1423+ return -EINVAL;
1424+ }
1425+
1426+ /* If we try to write beyond gtt table, return error */
1427+ if ((pg_start + mem->page_count) > num_entries) {
1428+ AGN_ERROR("Trying to write beyond aperture limit");
1429+ AGN_DEBUG("pg_start=0x%.8lx, mem->page_count=%d,"
1430+ "num_entries=%d", pg_start, mem->page_count,
1431+ num_entries);
1432+ return -EINVAL;
1433+ }
1434+
1435+ /* The i830 can't check the GTT for entries since its read only,
1436+ * depend on the caller to make the correct offset decisions.
1437+ */
1438+
1439+ if ((type != 0 && type != AGP_PHYS_MEMORY) ||
1440+ (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) {
1441+ AGN_ERROR("Unsupported memory type");
1442+ AGN_DEBUG("mem->type=%x, type=%x", mem->type, type);
1443+ return -EINVAL;
1444+ }
1445+
1446+ global_cache_flush();
1447+ agp_bridge->driver->tlb_flush(mem);
1448+
1449+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1450+ writel(AGP_MASK_GTT(), private_data.gtt+j);
1451+ readl(private_data.gtt+j); /* PCI Posting. */
1452+ }
1453+
1454+ global_cache_flush();
1455+ agp_bridge->driver->tlb_flush(mem);
1456+
1457+ AGN_DEBUG("Exit");
1458+
1459+ return 0;
1460+}
1461+
1462+int iegd_cmn_remove_entries(struct agp_memory *mem,
1463+ off_t pg_start, int type)
1464+{
1465+ int i;
1466+
1467+ AGN_DEBUG("Enter");
1468+
1469+ global_cache_flush();
1470+ agp_bridge->driver->tlb_flush(mem);
1471+
1472+ if (pg_start < private_data.gtt_entries) {
1473+ AGN_ERROR("Trying to disable local/stolen memory");
1474+ AGN_DEBUG("pg_start=0x%.8lx, private_data.gtt_entries=%d",
1475+ pg_start, private_data.gtt_entries);
1476+ return -EINVAL;
1477+ }
1478+
1479+ for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1480+ writel(agp_bridge->scratch_page, private_data.gtt+i);
1481+ readl(private_data.gtt+i);
1482+ }
1483+
1484+ global_cache_flush();
1485+ agp_bridge->driver->tlb_flush(mem);
1486+
1487+ AGN_DEBUG("Exit");
1488+
1489+ return 0;
1490+}
1491diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_gn4.c patch_script_temp/drivers/gpu/drm/iegd/agp/drv_gn4.c
1492--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_gn4.c 1969-12-31 17:00:00.000000000 -0700
1493+++ patch_script_temp/drivers/gpu/drm/iegd/agp/drv_gn4.c 2009-10-06 10:30:05.000000000 -0700
1494@@ -0,0 +1,455 @@
1495+/* -*- pse-c -*-
1496+ *----------------------------------------------------------------------------
1497+ * Filename: iegd_interface.c
1498+ * $Revision: 1.17 $
1499+ *----------------------------------------------------------------------------
1500+ * Gart and DRM driver for Intel Embedded Graphics Driver
1501+ * Copyright © 2007, Intel Corporation.
1502+ *
1503+ * This program is free software; you can redistribute it and/or modify it
1504+ * under the terms and conditions of the GNU General Public License,
1505+ * version 2, as published by the Free Software Foundation.
1506+ *
1507+ * This program is distributed in the hope it will be useful, but WITHOUT
1508+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1509+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1510+ * more details.
1511+ *
1512+ * You should have received a copy of the GNU General Public License along with
1513+ * this program; if not, write to the Free Software Foundation, Inc.,
1514+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1515+ *
1516+ */
1517+
1518+#include "global.h"
1519+#include "intelpci.h"
1520+
1521+static int iegd_gn4_fetch_size(void);
1522+static void iegd_gn4_cleanup(void);
1523+static void iegd_gn4_tlbflush(struct agp_memory *mem);
1524+static int AGP_CREATE_GATT(iegd_gn4_create_gatt_table);
1525+
1526+/* GM45 functions */
1527+static int iegd_igm45_fetch_size(void);
1528+static int iegd_igm45_configure(void);
1529+static int AGP_CREATE_GATT(iegd_igm45_create_gatt_table);
1530+
1531+struct aper_size_info_fixed iegd_i965_sizes[] =
1532+{
1533+ /* VBIOS always allocates enough space for 512MB aperture */
1534+ /* Size KB, # of entries, ? */
1535+ {128, 131072, 7},
1536+ {64, 131072, 7},
1537+ {256, 131072, 7},
1538+ {512, 131072, 7},
1539+};
1540+
1541+struct aper_size_info_fixed iegd_igm45_sizes[] =
1542+{
1543+ /* GM45 has 2MB GTT (EDS page 217) size */
1544+ /* Size_KB #_of_entries ? */
1545+ {256, 524288, 7},
1546+ {512, 524288, 7},
1547+};
1548+
1549+
1550+bridge_driver_t drv_gn4 = {
1551+ .owner = THIS_MODULE,
1552+ .size_type = FIXED_APER_SIZE,
1553+ .aperture_sizes = 0,
1554+ .num_aperture_sizes = 0,
1555+ .needs_scratch_page = TRUE,
1556+ .configure = iegd_cmn_configure,
1557+ .fetch_size = iegd_gn4_fetch_size,
1558+ .cleanup = iegd_gn4_cleanup,
1559+ .tlb_flush = iegd_gn4_tlbflush,
1560+ .mask_memory = iegd_cmn_mask_memory,
1561+ .masks = iegd_cmn_masks,
1562+ .agp_enable = iegd_cmn_agp_enable,
1563+ .cache_flush = global_cache_flush,
1564+ .create_gatt_table = iegd_gn4_create_gatt_table,
1565+ .free_gatt_table = iegd_cmn_free_gatt_table,
1566+ .insert_memory = iegd_cmn_insert_entries,
1567+ .remove_memory = iegd_cmn_remove_entries,
1568+ .alloc_by_type = iegd_cmn_alloc_by_type,
1569+ .free_by_type = iegd_cmn_free_by_type,
1570+ .agp_alloc_page = agp_generic_alloc_page,
1571+ .agp_destroy_page = agp_generic_destroy_page,
1572+};
1573+
1574+/* GM45 */
1575+bridge_driver_t drv_gm45 = {
1576+ .owner = THIS_MODULE,
1577+ .size_type = FIXED_APER_SIZE,
1578+ .aperture_sizes = (void *)iegd_igm45_sizes,
1579+ .num_aperture_sizes = 3,
1580+ .needs_scratch_page = TRUE,
1581+ .configure = iegd_igm45_configure,
1582+ .fetch_size = iegd_igm45_fetch_size,
1583+ .cleanup = iegd_gn4_cleanup,
1584+ .tlb_flush = iegd_gn4_tlbflush,
1585+ .mask_memory = iegd_cmn_mask_memory,
1586+ .masks = iegd_cmn_masks,
1587+ .agp_enable = iegd_cmn_agp_enable,
1588+ .cache_flush = global_cache_flush,
1589+ .create_gatt_table = iegd_igm45_create_gatt_table,
1590+ .free_gatt_table = iegd_cmn_free_gatt_table,
1591+ .insert_memory = iegd_cmn_insert_entries,
1592+ .remove_memory = iegd_cmn_remove_entries,
1593+ .alloc_by_type = iegd_cmn_alloc_by_type,
1594+ .free_by_type = iegd_cmn_free_by_type,
1595+ .agp_alloc_page = agp_generic_alloc_page,
1596+ .agp_destroy_page = agp_generic_destroy_page,
1597+};
1598+
1599+
1600+static int iegd_gn4_fetch_size(void)
1601+{
1602+ struct aper_size_info_fixed *values;
1603+ u32 offset = 0;
1604+ u8 temp;
1605+
1606+#define IG965_GMCH_MSAC 0x62
1607+#define IGM965_GMCH_MSAC 0x66
1608+
1609+ AGN_DEBUG("Enter");
1610+
1611+ values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
1612+
1613+ if(private_data.pdev->device == PCI_DEVICE_ID_GM965) {
1614+ pci_read_config_byte(private_data.pdev, IGM965_GMCH_MSAC, &temp);
1615+ } else {
1616+ pci_read_config_byte(private_data.pdev, IG965_GMCH_MSAC, &temp);
1617+ }
1618+
1619+ switch (temp & 6) {
1620+ case 0:
1621+ offset = 0; /* 128MB aperture */
1622+ break;
1623+ case 2:
1624+ offset = 2; /* 256MB aperture */
1625+ break;
1626+ case 6:
1627+ offset = 3; /* 512MB aperture */
1628+ break;
1629+ }
1630+
1631+ /* Set the actual size here */
1632+ agp_bridge->previous_size = agp_bridge->current_size =
1633+ (void *)(values + offset);
1634+
1635+ AGN_DEBUG("Exit");
1636+
1637+ /* Always return 512KB GTT when calculating available stolen memory */
1638+ return values[3].size;
1639+}
1640+
1641+static void iegd_gn4_cleanup(void)
1642+{
1643+ AGN_DEBUG("Enter");
1644+ iounmap((void *)private_data.registers);
1645+ AGN_DEBUG("Exit");
1646+}
1647+
1648+static void iegd_gn4_tlbflush(struct agp_memory *mem)
1649+{
1650+ AGN_DEBUG("Enter");
1651+ /* Gen4 must flush the GTT or simple 2D rendering will lock the engine. */
1652+ writel(0, private_data.registers+0x2170);
1653+ writel(0, private_data.registers+0x2174);
1654+ AGN_DEBUG("Exit");
1655+ return;
1656+}
1657+
1658+static int AGP_CREATE_GATT(iegd_gn4_create_gatt_table)
1659+{
1660+ const u32 i965_gtt_table_order = 7;
1661+
1662+ int i;
1663+ u16 j = 0;
1664+ int num_entries;
1665+ u32 gtt_bus_addr;
1666+ u32 mmio_bus_addr;
1667+ u32 gtt_enabled = FALSE;
1668+ u32 gtt_table_size = (1 << i965_gtt_table_order) * PAGE_SIZE - 1;
1669+ u32 gtt_pgctl_reg;
1670+ char *gtt_table, *gtt_table_end, *current_entry;
1671+ struct page *gtt_table_page;
1672+
1673+ AGN_DEBUG("Enter");
1674+
1675+ agp_bridge->gatt_table_real = NULL;
1676+
1677+ /* Find and save the address of the MMIO register */
1678+ pci_read_config_dword(private_data.pdev, I915_MMADDR, &mmio_bus_addr);
1679+
1680+ mmio_bus_addr &= 0xFFF80000;
1681+ private_data.registers =(volatile u8 *)
1682+ ioremap(mmio_bus_addr,1024 * 4096);
1683+ if (!private_data.registers) {
1684+ AGN_ERROR("ioremap failed to map");
1685+ return (-ENOMEM);
1686+ }
1687+ /* GTT is mapped 512KB after the registers */
1688+ private_data.gtt = (u32 __iomem *)((u32)private_data.registers +
1689+ 512*1024);
1690+
1691+ /* Extract the content of the control register */
1692+ gtt_pgctl_reg = readl(private_data.registers+I810_PGETBL_CTL);
1693+ gtt_bus_addr = gtt_pgctl_reg & 0xFFFFF000;
1694+ gtt_enabled = gtt_pgctl_reg & I810_PGETBL_ENABLED;
1695+
1696+ global_cache_flush();
1697+ agp_bridge->driver->tlb_flush(0);
1698+
1699+ /* we have to call this as early as possible after the MMIO base address is known */
1700+ iegd_cmn_init_gtt_entries();
1701+
1702+ if( !gtt_enabled ) {
1703+ num_entries = iegd_i965_sizes[0].num_entries;
1704+ gtt_table = (char *) __get_free_pages(GFP_KERNEL,
1705+ i965_gtt_table_order);
1706+ gtt_table_end = gtt_table + gtt_table_size;
1707+
1708+ /* Make sure allocation was successful */
1709+ if( NULL == gtt_table ) {
1710+ AGN_ERROR("Fail to allocate kernel pages");
1711+ return (-ENOMEM);
1712+ }
1713+
1714+ for( current_entry = gtt_table; current_entry < gtt_table_end;
1715+ current_entry += PAGE_SIZE ) {
1716+ gtt_table_page = virt_to_page( current_entry );
1717+ set_bit( PG_reserved, &gtt_table_page->flags );
1718+ }
1719+
1720+ agp_bridge->gatt_bus_addr = virt_to_phys( gtt_table );
1721+
1722+ for( i = 0; i < num_entries; i++ ) {
1723+ *(gtt_table + j) = (unsigned long) agp_bridge->scratch_page;
1724+ j += 4;
1725+ }
1726+ }
1727+ else {
1728+ agp_bridge->gatt_bus_addr = gtt_bus_addr;
1729+ }
1730+
1731+ agp_bridge->gatt_table = NULL;
1732+
1733+ AGN_DEBUG("Exit");
1734+
1735+ return(0);
1736+}
1737+
1738+static int AGP_CREATE_GATT(iegd_igm45_create_gatt_table)
1739+{
1740+ u32 mmio_bus_addr;
1741+
1742+ u32 gtt_mem_size;
1743+ u32 base_stolen_mem;
1744+ u16 gmch_ctrl;
1745+
1746+ u32 iegd_scratch, iegd_scratch2;
1747+ int gtt_entries;
1748+ int size = 4; /* Scratch page 4KB */
1749+
1750+ AGN_DEBUG("Enter");
1751+
1752+ agp_bridge->gatt_table_real = NULL;
1753+
1754+ /* Find and save the address of the MMIO register */
1755+ pci_read_config_dword(private_data.pdev, I915_MMADDR, &mmio_bus_addr);
1756+
1757+ /* Bits 35-22 */
1758+ mmio_bus_addr &= 0xFFC00000;
1759+
1760+ /* Map 4MB: 512KB MMIO, 2MB GTT */
1761+ private_data.registers =(volatile u8 *) ioremap(mmio_bus_addr, MB(4));
1762+
1763+ if (!private_data.registers) {
1764+ AGN_ERROR("ioremap failed to map");
1765+ return (-ENOMEM);
1766+ }
1767+
1768+ /* GTT is mapped 2MB after the registers */
1769+ private_data.gtt = (u32 __iomem *)((u32)private_data.registers + MB(2));
1770+
1771+ global_cache_flush();
1772+ agp_bridge->driver->tlb_flush(0);
1773+
1774+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL, &gmch_ctrl);
1775+
1776+#define IGM45_GMCH_GMS_STOLEN_128M (0x8 << 4)
1777+#define IGM45_GMCH_GMS_STOLEN_256M (0x9 << 4)
1778+#define IGM45_BASE_STOLEN 0x5C
1779+ pci_read_config_dword(private_data.pdev,IGM45_BASE_STOLEN,&base_stolen_mem);
1780+ base_stolen_mem &= 0xFFF00000;
1781+
1782+ /* Bits [7:4] will tell the amount of stolen memory */
1783+ /* Stolen memory = Amount specfied - 1 scratch page */
1784+ switch (gmch_ctrl & 0xf0) {
1785+ case I855_GMCH_GMS_STOLEN_1M:
1786+ gtt_entries = MB(1) - KB(size);
1787+ break;
1788+ case I855_GMCH_GMS_STOLEN_4M:
1789+ gtt_entries = MB(4) - KB(size);
1790+ break;
1791+ case I855_GMCH_GMS_STOLEN_8M:
1792+ gtt_entries = MB(8) - KB(size);
1793+ break;
1794+ case I855_GMCH_GMS_STOLEN_16M:
1795+ gtt_entries = MB(16) - KB(size);
1796+ break;
1797+ case I855_GMCH_GMS_STOLEN_32M:
1798+ gtt_entries = MB(32) - KB(size);
1799+ break;
1800+ case I915_GMCH_GMS_STOLEN_48M:
1801+ gtt_entries = MB(48) - KB(size);
1802+ break;
1803+ case I915_GMCH_GMS_STOLEN_64M:
1804+ gtt_entries = MB(64) - KB(size);
1805+ break;
1806+ case IGM45_GMCH_GMS_STOLEN_128M:
1807+ gtt_entries = MB(128) - KB(size);
1808+ break;
1809+ case IGM45_GMCH_GMS_STOLEN_256M:
1810+ gtt_entries = MB(256) - KB(size);
1811+ break;
1812+ default:
1813+ gtt_entries = 0;
1814+ break;
1815+ }
1816+
1817+ iegd_scratch = readl(private_data.registers + 0x71410);
1818+
1819+ /* check for the pci card as primary */
1820+ if (iegd_scratch == 0) {
1821+ /* No stolen memory has been used */
1822+ /*
1823+ * In Gen4, GTT is 2MB below stolen memory, which is a fix location
1824+ * The GTT is empty.
1825+ * Populate the GTT with PTE point to the stolen memory.
1826+ * This will not waste the stolen memory which BIOS already allocated.
1827+ */
1828+ int num_entries;
1829+ int i;
1830+ u16 j = 0;
1831+
1832+ AGN_DEBUG("PCI as primary.\n");
1833+
1834+ num_entries = gtt_entries / KB (4);
1835+
1836+ for (i = 0; i < num_entries; i++) {
1837+ writel(((base_stolen_mem + i * KB(4)) | 1), private_data.gtt+j);
1838+ j+=1;
1839+ }
1840+
1841+ gtt_entries = num_entries * KB(4);
1842+
1843+ AGN_DEBUG("PCI as primary scratch_page = %08lx gtt_entries = %d",
1844+ agp_bridge->scratch_page, gtt_entries);
1845+ } else if (((iegd_scratch>>16) == 0xE1DF) && (iegd_scratch & 0x4)) {
1846+ AGN_LOG("IEGD Firmware Detected");
1847+ /* IEGD firmware found, and Mem Reservation Flag present */
1848+ iegd_scratch2 = readl(private_data.registers + 0x71418);
1849+ /* Stolen memory = # of pages * 4KB */
1850+ gtt_entries = (iegd_scratch2 & 0xFFFF) * 4096;
1851+ }
1852+
1853+ if (gtt_entries > 0) {
1854+ AGN_LOG("Detected %d KB = %d MB stolen memory.", gtt_entries / KB(1),
1855+ gtt_entries/MB(1));
1856+ } else {
1857+ AGN_LOG("No pre-allocated video memory detected.");
1858+ }
1859+
1860+ /* Divide by 4KB to get the # of GTT entries */
1861+ private_data.gtt_entries = gtt_entries/KB(4);
1862+
1863+
1864+ /* On GM45, GTTADR size is 2MB. EDS page 217 */
1865+ gtt_mem_size = MB(2);
1866+
1867+ AGN_DEBUG("gtt_mem_size = %uMB", gtt_mem_size/MB(1));
1868+
1869+ /* Minus base stolen memory to get the base of gtt. This address
1870+ * can also get from register 0xA8 of config space device 0 */
1871+ agp_bridge->gatt_bus_addr = base_stolen_mem - gtt_mem_size;
1872+ agp_bridge->gatt_table = NULL;
1873+ AGN_DEBUG("Exit");
1874+
1875+ return(0);
1876+}
1877+
1878+/* GM45: configure */
1879+static int iegd_igm45_configure(void)
1880+{
1881+ struct aper_size_info_fixed *current_size;
1882+ u32 temp;
1883+ int i;
1884+
1885+ AGN_DEBUG("Enter");
1886+
1887+ current_size = A_SIZE_FIX(agp_bridge->current_size);
1888+
1889+ pci_read_config_dword(private_data.pdev, I915_GMADDR, &temp);
1890+ AGN_DEBUG("1. Reg[0x%x] = 0x%x\n", I915_GMADDR, temp);
1891+
1892+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1893+ AGN_DEBUG("2. Reg[0x%x] = 0x%x\n", I915_GMADDR, temp);
1894+
1895+ if (agp_bridge->driver->needs_scratch_page) {
1896+ for (i = private_data.gtt_entries;
1897+ i < current_size->num_entries; i++) {
1898+ writel(agp_bridge->scratch_page, private_data.gtt+i);
1899+ readl(private_data.gtt+i); /* PCI Posting. */
1900+ }
1901+ }
1902+ global_cache_flush();
1903+
1904+ AGN_DEBUG("Exit");
1905+
1906+ return 0;
1907+}
1908+
1909+/* GM45: fetch_size() */
1910+static int iegd_igm45_fetch_size(void)
1911+{
1912+ struct aper_size_info_fixed *values;
1913+ u32 offset = 0;
1914+ u8 temp;
1915+
1916+#define IGM45_GMCH_MSAC 0x66
1917+#define Q45_GMCH_MSAC 0x62
1918+
1919+ AGN_DEBUG("Enter");
1920+
1921+ values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
1922+
1923+ if(private_data.pdev->device == PCI_DEVICE_ID_ELK ||
1924+ private_data.pdev->device == PCI_DEVICE_ID_Q45 ||
1925+ private_data.pdev->device == PCI_DEVICE_ID_G45 ||
1926+ private_data.pdev->device == PCI_DEVICE_ID_G41) {
1927+ pci_read_config_byte(private_data.pdev, Q45_GMCH_MSAC, &temp);
1928+ } else {
1929+ pci_read_config_byte(private_data.pdev, IGM45_GMCH_MSAC, &temp);
1930+ }
1931+
1932+ /* GM45 has only 2 aperture sizes (EDS 227) : 256MB/512MB */
1933+ switch (temp & 6) {
1934+ case 2:
1935+ offset = 0; /* 256MB aperture */
1936+ break;
1937+ case 6:
1938+ offset = 1; /* 512MB aperture */
1939+ break;
1940+ }
1941+
1942+ /* Set the actual size here */
1943+ agp_bridge->previous_size = agp_bridge->current_size =
1944+ (void *)(values + offset);
1945+
1946+ AGN_DEBUG("Exit");
1947+ /* For GM45 always return 2MB as GTT size */
1948+ return values[0].size;
1949+}
1950diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_nap.c patch_script_temp/drivers/gpu/drm/iegd/agp/drv_nap.c
1951--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_nap.c 1969-12-31 17:00:00.000000000 -0700
1952+++ patch_script_temp/drivers/gpu/drm/iegd/agp/drv_nap.c 2009-10-06 10:30:05.000000000 -0700
1953@@ -0,0 +1,470 @@
1954+/* -*- pse-c -*-
1955+ *----------------------------------------------------------------------------
1956+ * Filename: drv_nap.c
1957+ * $Revision: 1.14 $
1958+ *----------------------------------------------------------------------------
1959+ * Gart and DRM driver for Intel Embedded Graphics Driver
1960+ * Copyright © 2008, Intel Corporation.
1961+ *
1962+ * This program is free software; you can redistribute it and/or modify it
1963+ * under the terms and conditions of the GNU General Public License,
1964+ * version 2, as published by the Free Software Foundation.
1965+ *
1966+ * This program is distributed in the hope it will be useful, but WITHOUT
1967+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1968+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1969+ * more details.
1970+ *
1971+ * You should have received a copy of the GNU General Public License along with
1972+ * this program; if not, write to the Free Software Foundation, Inc.,
1973+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1974+ *
1975+ */
1976+
1977+#include "global.h"
1978+#include "intelpci.h"
1979+
1980+static int iegd_nap_fetch_size(void);
1981+static void iegd_nap_tlbflush(struct agp_memory *mem);
1982+
1983+static void iegd_iq35_init_gtt_entries(void);
1984+static void iegd_nap_iq35_gatt(void);
1985+static int iegd_nap_9series(u32 order);
1986+static int AGP_CREATE_GATT(iegd_nap_create_gatt_table);
1987+static void iegd_nap_cleanup(void);
1988+
1989+
1990+struct aper_size_info_fixed iegd_i915_sizes[] =
1991+{
1992+ {128, 32768, 5},
1993+ /* The 64M mode still requires a 128k gatt */
1994+ {64, 16384, 5},
1995+ {256, 65536, 6},
1996+ {512, 131072, 7},
1997+};
1998+
1999+struct aper_size_info_fixed iegd_iq35_sizes[] =
2000+{
2001+ {128, 32768, 5},
2002+ {256, 65536, 6},
2003+ {512, 131072, 7},
2004+};
2005+
2006+bridge_driver_t drv_nap = {
2007+ .owner = THIS_MODULE,
2008+ .size_type = FIXED_APER_SIZE,
2009+ .aperture_sizes = 0,
2010+ .num_aperture_sizes = 0,
2011+ .needs_scratch_page = TRUE,
2012+ .configure = iegd_cmn_configure,
2013+ .fetch_size = iegd_nap_fetch_size,
2014+ .cleanup = iegd_nap_cleanup,
2015+ .tlb_flush = iegd_nap_tlbflush,
2016+ .mask_memory = iegd_cmn_mask_memory,
2017+ .masks = iegd_cmn_masks,
2018+ .agp_enable = iegd_cmn_agp_enable,
2019+ .cache_flush = global_cache_flush,
2020+ .create_gatt_table = iegd_nap_create_gatt_table,
2021+ .free_gatt_table = iegd_cmn_free_gatt_table,
2022+ .insert_memory = iegd_cmn_insert_entries,
2023+ .remove_memory = iegd_cmn_remove_entries,
2024+ .alloc_by_type = iegd_cmn_alloc_by_type,
2025+ .free_by_type = iegd_cmn_free_by_type,
2026+ .agp_alloc_page = agp_generic_alloc_page,
2027+ .agp_destroy_page = agp_generic_destroy_page,
2028+};
2029+
2030+static int iegd_nap_fetch_size()
2031+{
2032+ struct aper_size_info_fixed *values;
2033+ u32 offset = 0;
2034+ u32 temp2;
2035+ u8 temp;
2036+
2037+#define IQ35_GMCH_MSAC 0x62
2038+#define I915_256MB_ADDRESS_MASK (1<<27)
2039+
2040+ AGN_DEBUG("Enter");
2041+
2042+ values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
2043+
2044+ switch(private_data.pdev->device) {
2045+ case PCI_DEVICE_ID_Q35:
2046+ case PCI_DEVICE_ID_Q35A2:
2047+ pci_read_config_byte(private_data.pdev,
2048+ IQ35_GMCH_MSAC, &temp);
2049+ switch(temp & 0x3) {
2050+ case 1:
2051+ offset = 2; /* 512MB aperture size */
2052+ break;
2053+ case 2:
2054+ offset = 1; /* 256MB aperture size */
2055+ break;
2056+ case 3:
2057+ offset = 0; /* 128MB aperture size */
2058+ break;
2059+ }
2060+ break;
2061+ case PCI_DEVICE_ID_915GD:
2062+ case PCI_DEVICE_ID_915AL:
2063+ case PCI_DEVICE_ID_945G:
2064+ case PCI_DEVICE_ID_945GM:
2065+ case PCI_DEVICE_ID_945GME:
2066+ pci_read_config_dword(private_data.pdev,
2067+ I915_GMADDR, &temp2);
2068+ if (temp2 & I915_256MB_ADDRESS_MASK) {
2069+ offset = 0; /* 128MB aperture */
2070+ } else {
2071+ offset = 2; /* 256MB aperture */
2072+ }
2073+ break;
2074+ }
2075+
2076+ agp_bridge->previous_size = agp_bridge->current_size =
2077+ (void *)(values + offset);
2078+
2079+ AGN_DEBUG("Exit");
2080+
2081+ return values[offset].size;
2082+}
2083+
2084+static void iegd_nap_tlbflush(struct agp_memory *mem)
2085+{
2086+ AGN_DEBUG("Enter");
2087+ return;
2088+ AGN_DEBUG("Exit");
2089+}
2090+
2091+static void iegd_iq35_init_gtt_entries(void)
2092+{
2093+ u16 gmch_ctrl;
2094+ u32 iegd_scratch, iegd_scratch2;
2095+ int gtt_entries;
2096+ int local = 0;
2097+ int size = 4;
2098+
2099+#define I35_GMCH_GMS_STOLEN_128M (0x8 << 4)
2100+#define I35_GMCH_GMS_STOLEN_256M (0x9 << 4)
2101+#define I35_GMCH_GMS_MASK 0xf0
2102+
2103+ AGN_DEBUG("Enter");
2104+
2105+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
2106+
2107+ switch (gmch_ctrl & I35_GMCH_GMS_MASK) {
2108+ case I855_GMCH_GMS_STOLEN_1M:
2109+ gtt_entries = MB(1) - KB(size);
2110+ break;
2111+ case I855_GMCH_GMS_STOLEN_4M:
2112+ gtt_entries = MB(4) - KB(size);
2113+ break;
2114+ case I855_GMCH_GMS_STOLEN_8M:
2115+ gtt_entries = MB(8) - KB(size);
2116+ break;
2117+ case I855_GMCH_GMS_STOLEN_16M:
2118+ gtt_entries = MB(16) - KB(size);
2119+ break;
2120+ case I855_GMCH_GMS_STOLEN_32M:
2121+ gtt_entries = MB(32) - KB(size);
2122+ break;
2123+ case I915_GMCH_GMS_STOLEN_48M:
2124+ gtt_entries = MB(48) - KB(size);
2125+ break;
2126+ case I915_GMCH_GMS_STOLEN_64M:
2127+ gtt_entries = MB(64) - KB(size);
2128+ break;
2129+ case I35_GMCH_GMS_STOLEN_128M:
2130+ gtt_entries = MB(128) - KB(size);
2131+ break;
2132+ case I35_GMCH_GMS_STOLEN_256M:
2133+ gtt_entries = MB(256) - KB(size);
2134+ break;
2135+ default:
2136+ gtt_entries = 0;
2137+ break;
2138+ }
2139+
2140+ iegd_scratch = readl(private_data.registers + 0x71410);
2141+
2142+ /* FIXME: check for the pci card as primary */
2143+ if(iegd_scratch == 0) {
2144+ gtt_entries = 0;
2145+ } else if (((iegd_scratch>>16) == 0xE1DF) && (iegd_scratch & 0x4)) {
2146+ AGN_LOG("IEGD Firmware Detected");
2147+ /* IEGD firmware found, and Mem Reservation Flag present */
2148+ iegd_scratch2 = readl(private_data.registers + 0x71418);
2149+ gtt_entries = (iegd_scratch2 & 0xFFFF) * 4096;
2150+ }
2151+
2152+ if (gtt_entries > 0) {
2153+ AGN_LOG("Detected %dK %s memory.",
2154+ gtt_entries / KB(1), local ? "local" : "stolen");
2155+ } else {
2156+ AGN_LOG("No pre-allocated video memory detected.");
2157+ }
2158+
2159+ gtt_entries /= KB(4);
2160+
2161+ private_data.gtt_entries = gtt_entries;
2162+
2163+ AGN_DEBUG("Exit");
2164+}
2165+
2166+static void iegd_nap_iq35_gatt()
2167+{
2168+ u32 gtt_mem_size;
2169+ u32 base_stolen_mem;
2170+ u16 gmch_ctrl;
2171+
2172+ AGN_DEBUG("Enter");
2173+
2174+ iegd_iq35_init_gtt_entries();
2175+
2176+ pci_read_config_dword(private_data.pdev,
2177+ IQ35_BASE_STOLEN, &base_stolen_mem);
2178+ base_stolen_mem &= 0xFFF00000;
2179+
2180+ pci_read_config_word(private_data.pdev,
2181+ I830_GMCH_CTRL, &gmch_ctrl);
2182+
2183+ switch(gmch_ctrl & IQ35_GTT_MEM_SIZE) {
2184+ case IQ35_GGMS_1MB:
2185+ gtt_mem_size = MB(1); /* Normal mode */
2186+ break;
2187+ case IQ35_GGMS_2MB:
2188+ gtt_mem_size = MB(2); /* VT mode */
2189+ break;
2190+ default:
2191+ gtt_mem_size = 0;
2192+ }
2193+
2194+ AGN_DEBUG("gtt_mem_size = %uMB", gtt_mem_size);
2195+
2196+ /* Minus based stolen memory to get the base of gtt. This address
2197+ * can also get from register 0xA8 of config space device 0 */
2198+ agp_bridge->gatt_bus_addr = base_stolen_mem - gtt_mem_size;
2199+
2200+ AGN_DEBUG("Exit");
2201+}
2202+
2203+static int iegd_nap_9series(u32 order)
2204+{
2205+ u32 gtt_pgctl_reg;
2206+ u32 gtt_bus_addr;
2207+ u32 gtt_enabled = FALSE;
2208+ u32 iegd_scratch;
2209+
2210+ gtt_pgctl_reg = readl(private_data.registers +
2211+ I810_PGETBL_CTL);
2212+ global_cache_flush();
2213+ gtt_bus_addr = gtt_pgctl_reg & 0xFFFFF000;
2214+ gtt_enabled = gtt_pgctl_reg & I810_PGETBL_ENABLED;
2215+
2216+
2217+ /* we have to call this as early as possible after the MMIO base
2218+ * address is known */
2219+ iegd_cmn_init_gtt_entries();
2220+
2221+ /*
2222+ * If GTT not enabled created our own gtt table from kernel memory
2223+ * and initialize it to scratch page. This in case the VBIOS is
2224+ * not our VBIOS
2225+ */
2226+ iegd_scratch = readl(private_data.registers + 0x71410);
2227+
2228+ if (iegd_scratch == 0) {
2229+ /* PCI as primary device. IEGD VBIOS is not loaded.
2230+ * Need to setup the GTT in stolen memory
2231+ * GTT will located at the bottom of stolen memory.
2232+ * The rest of the memory will use as video memory and map the PTE except
2233+ * the last page, which use as sratch page.
2234+ */
2235+ u32 gtt_end;
2236+ u32 gtt_addr_reg;
2237+ u32 base_stolen_mem;
2238+ u16 gmch_ctrl;
2239+ int aperture_size = 0;
2240+ int total_stolen_pages = 0;
2241+ int total_gtt_entries = 0;
2242+ int num_entries;
2243+ int i;
2244+ u16 j = 0;
2245+ u32 temp2;
2246+ u8 temp;
2247+
2248+ /* read the stolen memory address.
2249+ * use 512 bytes as GTT table, and use the rest table for memory. */
2250+ pci_read_config_dword(private_data.pdev,
2251+ IQ35_BASE_STOLEN, &base_stolen_mem);
2252+ base_stolen_mem &= 0xFFF00000;
2253+
2254+ /* have to determine the stolen memory size.
2255+ * We can't use the private_data.gtt_entries value because the value assume VBIOS is present. */
2256+ pci_read_config_word(private_data.pdev, I830_GMCH_CTRL, &gmch_ctrl);
2257+ gmch_ctrl = (gmch_ctrl >> 4) & 0xf;
2258+ /* Translate the stolen memory size to num of pages available. */
2259+ if (gmch_ctrl == 1) {
2260+ total_stolen_pages = 1024 / 4 ;
2261+ } else if (gmch_ctrl > 1) {
2262+ total_stolen_pages = (2 << (gmch_ctrl - 1)) * (1024 / 4);
2263+ }
2264+
2265+ /* We need to allocate the last page as scratch page. */
2266+ total_stolen_pages = total_stolen_pages - 1;
2267+
2268+ /* Need to program the PGETBL_CTL to enable page table. */
2269+ writel(base_stolen_mem | 1, private_data.registers + I810_PGETBL_CTL);
2270+
2271+#define I810_GTT_ADDR 0x1c
2272+ /* Find and save the address of the MMIO register */
2273+ pci_read_config_dword(private_data.pdev, I810_GTT_ADDR, &gtt_addr_reg);
2274+ private_data.gtt = (volatile u32 *) ioremap(gtt_addr_reg, KB(512));
2275+
2276+ if (!private_data.gtt) {
2277+ AGN_ERROR("ioremap failed to map");
2278+ return (-ENOMEM);
2279+ }
2280+
2281+
2282+ switch(private_data.pdev->device) {
2283+ case PCI_DEVICE_ID_Q35:
2284+ case PCI_DEVICE_ID_Q35A2:
2285+ pci_read_config_byte(private_data.pdev,
2286+ IQ35_GMCH_MSAC, &temp);
2287+ switch(temp & 0x3) {
2288+ case 1:
2289+ aperture_size = 512; /* 512MB aperture size */
2290+ break;
2291+ case 2:
2292+ aperture_size = 256; /* 256MB aperture size */
2293+ break;
2294+ case 3:
2295+ aperture_size = 128; /* 128MB aperture size */
2296+ break;
2297+ }
2298+ break;
2299+ case PCI_DEVICE_ID_915GD:
2300+ case PCI_DEVICE_ID_915AL:
2301+ case PCI_DEVICE_ID_945G:
2302+ case PCI_DEVICE_ID_945GM:
2303+ case PCI_DEVICE_ID_945GME:
2304+ pci_read_config_dword(private_data.pdev,
2305+ I915_GMADDR, &temp2);
2306+ if (temp2 & I915_256MB_ADDRESS_MASK) {
2307+ aperture_size = 128; /* 128MB aperture */
2308+ } else {
2309+ aperture_size = 256; /* 256MB aperture */
2310+ }
2311+ break;
2312+ default: AGN_ERROR("Illegal Device ID");
2313+ break;
2314+ }
2315+ /* Number of GTT entries available based on the aperture size. */
2316+ total_gtt_entries = aperture_size * 1024 / 4;
2317+ /* gtt_end is the last entry of the GTT, and start of video memory. */
2318+ gtt_end = base_stolen_mem + KB(aperture_size);
2319+
2320+ /* This num_entries mean total of PTE can be populate based on the
2321+ * remaining stolen memory size.*/
2322+ num_entries = ((total_stolen_pages * 4) - aperture_size) / 4;
2323+
2324+ /* Have to program the PTE through the GTT ADDRESS.*/
2325+ for (i=0; i < num_entries; i++) {
2326+ writel(((gtt_end + i * KB(4)) | 1), (private_data.gtt + j));
2327+ j+=1;
2328+ }
2329+
2330+ /* I believe this will be the reserved memory refer by GMM.
2331+ * So, have to update the actual PTE has been used.*/
2332+ private_data.gtt_entries = num_entries - 1;
2333+
2334+ /* This num_entries is the remaining GTT table not fill up. Have to
2335+ * populate with scratch page. */
2336+ num_entries = total_gtt_entries - num_entries;
2337+
2338+ for (i=0; i < num_entries; i++)
2339+ {
2340+ writel(agp_bridge->scratch_page, private_data.gtt + j);
2341+ j+=1;
2342+ }
2343+
2344+ agp_bridge->gatt_bus_addr = base_stolen_mem;
2345+ } else {
2346+ agp_bridge->gatt_bus_addr = gtt_bus_addr;
2347+ }
2348+
2349+ agp_bridge->gatt_table = NULL;
2350+
2351+ AGN_DEBUG("Exit");
2352+
2353+ return 0;
2354+}
2355+
2356+
2357+static int AGP_CREATE_GATT(iegd_nap_create_gatt_table)
2358+{
2359+ const u32 i915_gtt_table_order = 6;
2360+ u32 mmio_bus_addr, temp2;
2361+ int ret;
2362+
2363+ AGN_DEBUG("Enter");
2364+
2365+ agp_bridge->gatt_table_real = NULL;
2366+
2367+ /* Find and save the address of the MMIO register */
2368+ pci_read_config_dword(private_data.pdev, I915_MMADDR,
2369+ &mmio_bus_addr);
2370+ mmio_bus_addr &= 0xFFF80000;
2371+
2372+ private_data.registers = (volatile u8 *) ioremap(mmio_bus_addr,
2373+ 128 * 4096);
2374+ if (!private_data.registers) {
2375+ AGN_ERROR("ioremap failed to map mmio");
2376+ return (-ENOMEM);
2377+ }
2378+
2379+ pci_read_config_dword(private_data.pdev, I915_PTEADDR,&temp2);
2380+
2381+ /* FIXME: double check the size of area to map to pci space */
2382+ private_data.gtt = (volatile u32 *)ioremap(temp2, 512 * 1024);
2383+ if (!private_data.gtt) {
2384+ AGN_ERROR("ioremap failed to map gtt");
2385+ return (-ENOMEM);
2386+ }
2387+
2388+ switch(private_data.pdev->device) {
2389+ case PCI_DEVICE_ID_Q35:
2390+ case PCI_DEVICE_ID_Q35A2:
2391+ /* Bearlake B is difference from other chipset, especially
2392+ * when reading gtt based address. Probably future chipset
2393+ * will have same architecture as Bearlake-B and this
2394+ * code can move to common file*/
2395+ iegd_nap_iq35_gatt();
2396+ break;
2397+ case PCI_DEVICE_ID_915GD:
2398+ case PCI_DEVICE_ID_915AL:
2399+ case PCI_DEVICE_ID_945G:
2400+ case PCI_DEVICE_ID_945GM:
2401+ case PCI_DEVICE_ID_945GME:
2402+ if((ret = iegd_nap_9series(i915_gtt_table_order))) {
2403+ return (ret);
2404+ }
2405+ break;
2406+ }
2407+
2408+ agp_bridge->gatt_table = NULL;
2409+
2410+ AGN_DEBUG("Exit");
2411+
2412+ return (0);
2413+}
2414+
2415+static void iegd_nap_cleanup(void)
2416+{
2417+
2418+ AGN_DEBUG("Enter");
2419+ iounmap((void *)private_data.gtt);
2420+ iounmap((void *)private_data.registers);
2421+ AGN_DEBUG("Exit");
2422+}
2423+
2424diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_plb.c patch_script_temp/drivers/gpu/drm/iegd/agp/drv_plb.c
2425--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/drv_plb.c 1969-12-31 17:00:00.000000000 -0700
2426+++ patch_script_temp/drivers/gpu/drm/iegd/agp/drv_plb.c 2009-10-06 10:30:05.000000000 -0700
2427@@ -0,0 +1,945 @@
2428+/* -*- pse-c -*-
2429+ *----------------------------------------------------------------------------
2430+ * Filename: iegd_interface.c
2431+ * $Revision: 1.36 $
2432+ *----------------------------------------------------------------------------
2433+ * Gart and DRM driver for Intel Embedded Graphics Driver
2434+ * Copyright © 2007, Intel Corporation.
2435+ *
2436+ * This program is free software; you can redistribute it and/or modify it
2437+ * under the terms and conditions of the GNU General Public License,
2438+ * version 2, as published by the Free Software Foundation.
2439+ *
2440+ * This program is distributed in the hope it will be useful, but WITHOUT
2441+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2442+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2443+ * more details.
2444+ *
2445+ * You should have received a copy of the GNU General Public License along with
2446+ * this program; if not, write to the Free Software Foundation, Inc.,
2447+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2448+ *
2449+ */
2450+
2451+#include "global.h"
2452+#include "intelpci.h"
2453+#include <linux/pagemap.h>
2454+#include <linux/list.h>
2455+
2456+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
2457+
2458+static int iegd_plb_fetch_size(void);
2459+static void iegd_plb_tlbflush(struct agp_memory *mem);
2460+static int iegd_plb_init_gtt(u32 order);
2461+static int AGP_CREATE_GATT(iegd_plb_create_gatt_table);
2462+static void iegd_plb_cleanup(void);
2463+static struct page *iegd_plb_vm_nopage(struct vm_area_struct *,
2464+ unsigned long, int *);
2465+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
2466+static int iegd_plb_vm_fault(struct vm_area_struct *vma,
2467+ struct vm_fault *vmf);
2468+#endif
2469+static void iegd_plb_vm_close(struct vm_area_struct *);
2470+int iegd_plb_insert_entries(struct agp_memory *, off_t, int);
2471+int iegd_plb_remove_entries(struct agp_memory *, off_t, int);
2472+void iegd_plb_free_by_type(struct agp_memory *);
2473+int iegd_plb_configure(void);
2474+
2475+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
2476+#define PLB_DESTROY_PAGES(a,b,c) plb_destroy_pages(a->pages[0],b,c)
2477+#else
2478+#define PLB_DESTROY_PAGES(a,b,c) plb_destroy_pages_by_addr(gart_to_virt(a->memory[0]),b,c)
2479+#endif
2480+
2481+
2482+/* Each structure in this array contains three elements:
2483+ * Size of GTT in KB
2484+ * Number of 32-bit entries that make up the GTT
2485+ * Page "order" -- 2^order == number of contiguous CPU pages
2486+ * required to store the GTT
2487+ */
2488+struct aper_size_info_fixed iegd_plb_sizes[] =
2489+{
2490+ {256, 65536, 6},
2491+};
2492+
2493+bridge_driver_t drv_plb = {
2494+ .owner = THIS_MODULE,
2495+ .size_type = FIXED_APER_SIZE,
2496+ .aperture_sizes = iegd_plb_sizes,
2497+ .num_aperture_sizes = 1,
2498+ .needs_scratch_page = TRUE,
2499+ .configure = iegd_plb_configure,
2500+ .fetch_size = iegd_plb_fetch_size,
2501+ .cleanup = iegd_plb_cleanup,
2502+ .tlb_flush = iegd_plb_tlbflush,
2503+ .mask_memory = iegd_cmn_mask_memory,
2504+ .masks = iegd_cmn_masks,
2505+ .agp_enable = iegd_cmn_agp_enable,
2506+ .cache_flush = global_cache_flush,
2507+ .create_gatt_table = iegd_plb_create_gatt_table,
2508+ .free_gatt_table = iegd_cmn_free_gatt_table,
2509+ .insert_memory = iegd_plb_insert_entries,
2510+ .remove_memory = iegd_plb_remove_entries,
2511+ .alloc_by_type = iegd_cmn_alloc_by_type,
2512+ .free_by_type = iegd_plb_free_by_type,
2513+ .agp_alloc_page = agp_generic_alloc_page,
2514+ .agp_destroy_page = agp_generic_destroy_page,
2515+};
2516+
2517+struct vm_operations_struct iegd_plb_vm_ops = {
2518+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
2519+ .fault = iegd_plb_vm_fault,
2520+#else
2521+ .nopage = iegd_plb_vm_nopage,
2522+#endif
2523+ .close = iegd_plb_vm_close
2524+};
2525+
2526+static DECLARE_MUTEX(client_sem);
2527+
2528+struct client_list_struct {
2529+ struct list_head list;
2530+ struct vm_area_struct *vma;
2531+ pid_t pid;
2532+};
2533+
2534+static LIST_HEAD(client_list);
2535+
2536+
2537+static int iegd_plb_fetch_size()
2538+{
2539+ struct aper_size_info_fixed *values;
2540+
2541+ values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
2542+
2543+
2544+ agp_bridge->previous_size = agp_bridge->current_size =
2545+ (void *)(values);
2546+
2547+ return values[0].size;
2548+}
2549+
2550+static void iegd_plb_tlbflush(struct agp_memory *mem)
2551+{
2552+ u32 sgx_mmu;
2553+
2554+ /* Flush TLB */
2555+ sgx_mmu = readl(private_data.registers + 0x40C00);
2556+ sgx_mmu &= 0xFFFFFFE0;
2557+ sgx_mmu |= 0x0C;
2558+ writel(sgx_mmu, private_data.registers + 0x40C00);
2559+
2560+ wmb();
2561+ sgx_mmu = readl(private_data.registers + 0x40C00);
2562+ sgx_mmu &= 0xFFFFFFE0;
2563+ writel(sgx_mmu, private_data.registers + 0x40C00);
2564+
2565+ return;
2566+}
2567+
2568+#define IUS15_GMCH_MSAC 0x62
2569+
2570+static int iegd_plb_init_gtt(u32 order)
2571+{
2572+ u32 gtt_pgctl_reg;
2573+ u32 gtt_bus_addr;
2574+ u32 gtt_enabled = FALSE;
2575+ int num_entries;
2576+ u32 *gtt_table, *dstvirt;
2577+ u32 *sgx_dir, sgx_mmu;
2578+ u32 iegd_scratch, aperphys;
2579+ u8 temp;
2580+ struct page *gtt_table_page;
2581+ int i,j;
2582+ u32 new_order;
2583+
2584+ /* Has the system BIOS only allocateda GTT for 128MB? If
2585+ * so we need to replace it with one sized for 256MB
2586+ */
2587+ pci_read_config_byte(private_data.pdev, IUS15_GMCH_MSAC, &temp);
2588+ if ((temp & 0x03) == 0x03) {
2589+ AGN_DEBUG("Graphics aperture is configured for 128MB");
2590+ AGN_DEBUG("Enabling 256MB split aperture");
2591+ private_data.split_gtt = 1;
2592+ } else {
2593+ private_data.split_gtt = 0;
2594+ }
2595+
2596+ gtt_pgctl_reg = readl(private_data.registers +
2597+ I810_PGETBL_CTL);
2598+ global_cache_flush();
2599+ gtt_bus_addr = gtt_pgctl_reg & 0xFFFFF000;
2600+ gtt_enabled = gtt_pgctl_reg & I810_PGETBL_ENABLED;
2601+
2602+ /* we have to call this as early as possible after the MMIO base
2603+ * address is known */
2604+ iegd_cmn_init_gtt_entries();
2605+
2606+ /* Update the scratch registers to say that we have no stolen memory */
2607+ iegd_scratch = readl(private_data.registers + 0x71410);
2608+ if ((iegd_scratch & 0xE1DF0000) == 0xE1DF0000) {
2609+ /* if our vBios modify only the stolen memory bit */
2610+ iegd_scratch |= 0x00000004;
2611+ writel(iegd_scratch, private_data.registers + 0x71410);
2612+ } else {
2613+ /* Not our vBIOS but set the stolen memory anyway */
2614+ writel(0xE1DF0004, private_data.registers + 0x71410);
2615+ }
2616+
2617+ /* Reportthat we have 0 stolen memory regardless of what was
2618+ * really in there. We _want_ to insert fresh pages on top of
2619+ * stolen memory. */
2620+ writel(0, private_data.registers + 0x71418);
2621+
2622+ num_entries = (1 << order) * KB(1);
2623+
2624+ private_data.upper_gtt=NULL;
2625+
2626+ /*
2627+ * If GTT not enabled created our own gtt table from kernel memory
2628+ * and initialize it to scratch page. This in case the VBIOS is
2629+ * not our VBIOS
2630+ */
2631+ if (!gtt_enabled) {
2632+ gtt_table = (u32 *)__get_free_pages(GFP_KERNEL, order);
2633+
2634+ /* Make sure allocation was successful */
2635+ if (NULL == gtt_table) {
2636+ AGN_ERROR("Failed to allocate kernel pages");
2637+ return (-ENOMEM);
2638+ }
2639+
2640+ for (i=0; i < (1 << order); i++) {
2641+ dstvirt = gtt_table + (PAGE_SIZE * i);
2642+ gtt_table_page = virt_to_page(dstvirt);
2643+ AGN_DEBUG("Setting reserved bit on %p", gtt_table_page);
2644+ set_bit(PG_reserved, &gtt_table_page->flags);
2645+ }
2646+
2647+ private_data.upper_gtt = gtt_table + 0x8000;
2648+ agp_bridge->gatt_bus_addr = virt_to_phys(gtt_table);
2649+
2650+ for (i = 0; i < num_entries; i++) {
2651+ gtt_table[i] = (unsigned long) agp_bridge->scratch_page;
2652+ }
2653+
2654+ /* Enable the newly created GTT */
2655+ AGN_DEBUG("Enabling new GTT");
2656+ writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED,
2657+ private_data.registers+I810_PGETBL_CTL);
2658+ readl(private_data.registers+I810_PGETBL_CTL);
2659+
2660+ } else if (private_data.split_gtt) {
2661+ /* We're keeping the system BIOS created normal gtt but
2662+ * augmenting it with more entries
2663+ */
2664+ gtt_table = (u32 *)__get_free_pages(GFP_KERNEL, order - 1);
2665+
2666+ //AGN_DEBUG("Allocated secondary GTT at %p:%p (virt:phys)", gtt_table,
2667+ // virt_to_phys(gtt_table));
2668+
2669+ /* Make sure allocation was successful */
2670+ if (NULL == gtt_table) {
2671+ AGN_ERROR("Failed to allocate kernel pages");
2672+ return (-ENOMEM);
2673+ }
2674+
2675+ private_data.upper_gtt = gtt_table;
2676+
2677+ for (i = 0; i < num_entries/2; i++) {
2678+ gtt_table[i] = (unsigned long) agp_bridge->scratch_page;
2679+ }
2680+
2681+ agp_bridge->gatt_bus_addr = gtt_bus_addr;
2682+
2683+ } else {
2684+
2685+ agp_bridge->gatt_bus_addr = gtt_bus_addr;
2686+
2687+ }
2688+
2689+ /*
2690+ * Now that the GTT exists and has been configured, enable
2691+ * the SGX MMU to point to the GTT as its page tables
2692+ */
2693+
2694+ /* The directory level is a single page of memory */
2695+ sgx_dir = (u32 *)__get_free_pages(GFP_KERNEL, 0);
2696+ if (NULL == sgx_dir ) {
2697+ AGN_ERROR("Failed to allocate kernel page");
2698+ return (-ENOMEM);
2699+ }
2700+
2701+ /* Mark the directory so that it is not swappable */
2702+ gtt_table_page = virt_to_page( sgx_dir );
2703+ set_bit(PG_reserved, &gtt_table_page->flags);
2704+
2705+ memset (sgx_dir, 0, PAGE_SIZE);
2706+
2707+ /* Initialize the directory so that each used page table
2708+ * is addressed
2709+ */
2710+
2711+ /* Make sure entire SGX directory is populated */
2712+ for (i = 0; i < 0x400; i++) {
2713+ sgx_dir[i] = agp_bridge->gatt_bus_addr | 0x01;
2714+ }
2715+
2716+ pci_read_config_dword(private_data.pdev, I915_GMADDR, &aperphys);
2717+ aperphys &= PCI_BASE_ADDRESS_MEM_MASK;
2718+ aperphys = aperphys >> 22;
2719+
2720+ if (private_data.split_gtt) {
2721+ /* Only use half of the entries */
2722+ new_order = order-1;
2723+ } else {
2724+ /* Full GTT, use all entries */
2725+ new_order = order;
2726+ }
2727+
2728+ for (i = 0; i < (1 << new_order); i++) {
2729+ /* Set the address for 2D/3D*/
2730+ sgx_dir[i] = agp_bridge->gatt_bus_addr + (PAGE_SIZE * i);
2731+ /* Set the address for hostport */
2732+ sgx_dir[i+aperphys] = agp_bridge->gatt_bus_addr + (PAGE_SIZE * i);
2733+
2734+ /* Mark them as valid */
2735+ sgx_dir[i] |= 0x01;
2736+ sgx_dir[i+aperphys] |= 0x01;
2737+
2738+ //AGN_DEBUG("Directory %d is %08lx", i, sgx_dir[i]);
2739+ }
2740+
2741+ /* If we're in split gtt mode, set the directory entries of the second
2742+ * gtt
2743+ */
2744+
2745+ if (private_data.split_gtt) {
2746+ j=0;
2747+ for (i = (1 << (order - 1)); i < (1 << order); i++) {
2748+ /* Set the address for 2D/3D*/
2749+ sgx_dir[i] = virt_to_phys(private_data.upper_gtt) + (PAGE_SIZE * j);
2750+ /* Set the address for hostport */
2751+ sgx_dir[i+aperphys] = virt_to_phys(private_data.upper_gtt) + (PAGE_SIZE * j);
2752+
2753+ j++;
2754+
2755+ /* Mark them as valid */
2756+ sgx_dir[i] |= 0x01;
2757+ sgx_dir[i+aperphys] |= 0x01;
2758+ //AGN_DEBUG("Directory %d is %08lx", i, sgx_dir[i]);
2759+ }
2760+ }
2761+
2762+ /*
2763+ * Program the directory's address into the MMU control
2764+ * register
2765+ */
2766+
2767+ /* Flush the cache */
2768+ flush_cache_all();
2769+ global_cache_flush();
2770+
2771+ /* Invalidate directory cache */
2772+ sgx_mmu = readl(private_data.registers + 0x40C00);
2773+ sgx_mmu |= 0x1E;
2774+ writel(sgx_mmu, private_data.registers + 0x40C00);
2775+ wmb();
2776+ readl(private_data.registers + 0x40C00);
2777+
2778+ writel(virt_to_phys(sgx_dir), private_data.registers + 0x40C84);
2779+ wmb();
2780+ readl(private_data.registers + 0x40C84);
2781+
2782+ /* Turn on host access to aperture via the MMU */
2783+ sgx_mmu = readl(private_data.registers + 0x40C00);
2784+ sgx_mmu &= 0xFFFE0000;
2785+ writel(sgx_mmu, private_data.registers + 0x40C00);
2786+ wmb();
2787+ readl(private_data.registers + 0x40C00);
2788+
2789+ return 0;
2790+}
2791+
2792+
2793+static int AGP_CREATE_GATT(iegd_plb_create_gatt_table)
2794+{
2795+ u32 order;
2796+ u32 mmio_bus_addr, temp2;
2797+ int ret;
2798+ u32 gtt_size;
2799+ unsigned char msac;
2800+ u32 msac_gtt_size;
2801+
2802+ agp_bridge->gatt_table_real = NULL;
2803+
2804+ order=A_SIZE_FIX(agp_bridge->current_size)->page_order;
2805+
2806+ /* Find and save the address of the MMIO register */
2807+ pci_read_config_dword(private_data.pdev, I915_MMADDR,
2808+ &mmio_bus_addr);
2809+ mmio_bus_addr &= 0xFFF80000;
2810+
2811+ private_data.registers = (volatile u8 *) ioremap(mmio_bus_addr,
2812+ KB(512));
2813+
2814+ if (!private_data.registers) {
2815+ AGN_ERROR("ioremap failed to map mmio");
2816+ return (-ENOMEM);
2817+ }
2818+
2819+ pci_read_config_dword(private_data.pdev, I915_PTEADDR, &temp2);
2820+
2821+ /* Get the GTT size via MSAC */
2822+ pci_read_config_byte(private_data.pdev, IUS15_GMCH_MSAC, &msac);
2823+
2824+ switch (msac & 0x03) {
2825+ case 0x02: /* 256K GTT size */
2826+ msac_gtt_size = KB(256);
2827+ break;
2828+ case 0x03: /* 128K GTT size */
2829+ default:
2830+ msac_gtt_size = KB(128);
2831+ break;
2832+ }
2833+
2834+ gtt_size = A_SIZE_FIX(agp_bridge->current_size)->num_entries * sizeof(u32);
2835+
2836+ if (gtt_size!=msac_gtt_size) {
2837+ AGN_DEBUG("MSAC GTT size 0x%08x, bridge GTT size 0x%08x; using MSAC",
2838+ msac_gtt_size, gtt_size);
2839+ gtt_size = msac_gtt_size;
2840+ }
2841+
2842+ private_data.gtt = (volatile u32 *)ioremap(temp2, gtt_size);
2843+
2844+ if (!private_data.gtt) {
2845+ AGN_ERROR("ioremap failed to map gtt");
2846+ return (-ENOMEM);
2847+ }
2848+
2849+ if((ret = iegd_plb_init_gtt(order))) {
2850+ return (ret);
2851+ }
2852+
2853+ agp_bridge->gatt_table = NULL;
2854+
2855+ return (0);
2856+}
2857+
2858+static void iegd_plb_cleanup(void)
2859+{
2860+
2861+ iounmap((void *)private_data.gtt);
2862+ iounmap((void *)private_data.registers);
2863+}
2864+
2865+
2866+static void iegd_plb_vm_close(struct vm_area_struct *vma)
2867+{
2868+ struct list_head *tmp;
2869+ struct client_list_struct *entry;
2870+
2871+ down(&client_sem);
2872+ list_for_each(tmp, &client_list) {
2873+ entry = list_entry(tmp, struct client_list_struct, list);
2874+ if (entry->vma == vma) {
2875+ list_del(&entry->list);
2876+ kfree(entry);
2877+ AGN_DEBUG("Removed VMA %p from client list", vma);
2878+ break;
2879+ }
2880+ }
2881+ up(&client_sem);
2882+}
2883+
2884+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
2885+static int iegd_plb_vm_fault(struct vm_area_struct *vma,
2886+ struct vm_fault *vmf)
2887+{
2888+ int type=0; /* New fault handler doesn't use type */
2889+ unsigned long address = (unsigned long) vmf->virtual_address;
2890+
2891+ vmf->page = iegd_plb_vm_nopage(vma, address, &type);
2892+
2893+ return 0;
2894+}
2895+#endif
2896+
2897+static struct page *iegd_plb_vm_nopage(struct vm_area_struct *vma,
2898+ unsigned long address,
2899+ int *type)
2900+{
2901+ unsigned long offset=0;
2902+ unsigned long physaddr=0;
2903+ struct page *page;
2904+ struct list_head *tmp;
2905+ struct client_list_struct *entry;
2906+ int flag=0;
2907+
2908+ /* On the Intel SCH US15, we don't have a traditional aperture. As
2909+ * a result, we're substituting the base of stolen memory
2910+ * as the aperture address.
2911+ *
2912+ * Mmaps relative to the base of stolen memory will be
2913+ * treated as mmaps covering parts of our virtual aperture.
2914+ *
2915+ * Given that a single surface may be mapped, and not the
2916+ * whole virtual aperture, we must translate the values
2917+ * received so that they are relative to our 0-based virtual
2918+ * aperture.
2919+ */
2920+ offset = (vma->vm_pgoff << PAGE_SHIFT) - agp_bridge->gart_bus_addr;
2921+
2922+ /* All pages returned must be noncached or write-combined*/
2923+ if (agp_use_pat()) {
2924+ pgprot_val(vma->vm_page_prot) &= ~(_PAGE_PCD | _PAGE_PWT);
2925+ pgprot_val(vma->vm_page_prot) |= _PAGE_PAT;
2926+ } else {
2927+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2928+ }
2929+
2930+ /* Access to the virtual frame buffer does not appear to
2931+ * call open properly before faulting. As a result, we
2932+ * need to do this housekeeping at each fault.
2933+ */
2934+ down(&client_sem);
2935+ list_for_each(tmp, &client_list) {
2936+ entry = list_entry(tmp, struct client_list_struct, list);
2937+ if (entry->vma == vma) {
2938+ flag=1;
2939+ }
2940+ }
2941+
2942+ if (!flag) {
2943+ entry = kmalloc(sizeof(struct client_list_struct), GFP_KERNEL);
2944+ if (entry) {
2945+ entry->vma = vma;
2946+ list_add(&(entry->list), &client_list);
2947+ AGN_DEBUG("Added VMA %p to client list", vma);
2948+
2949+ AGN_DEBUG("Scratch: %p", virt_to_page(agp_bridge->scratch_page));
2950+
2951+ } else {
2952+ AGN_ERROR("Failed to add VMA to client list");
2953+ }
2954+ }
2955+ up(&client_sem);
2956+
2957+ offset += address - vma->vm_start;
2958+
2959+ if (private_data.split_gtt && ((offset >> PAGE_SHIFT)) >= 0x8000) {
2960+ physaddr = readl(private_data.upper_gtt + (offset >> PAGE_SHIFT)
2961+ - 0x8000);
2962+ } else {
2963+ physaddr = readl(private_data.gtt + (offset >> PAGE_SHIFT));
2964+ }
2965+
2966+
2967+ physaddr &= PAGE_MASK;
2968+
2969+ if (!pfn_valid(physaddr >> PAGE_SHIFT)) {
2970+ AGN_ERROR("Referencing non-existant struct page.\n");
2971+ }
2972+
2973+ if (physaddr >= agp_bridge->gart_bus_addr) {
2974+ AGN_DEBUG("Faulted before insert, returning scratch page");
2975+ page = virt_to_page(__va(agp_bridge->scratch_page));
2976+ } else {
2977+ page = virt_to_page(__va(physaddr));
2978+ }
2979+
2980+ get_page(page);
2981+
2982+ if (type) {
2983+ *type = VM_FAULT_MINOR;
2984+ }
2985+
2986+ return (page);
2987+}
2988+
2989+
2990+int iegd_plb_insert_entries(struct agp_memory *mem,
2991+ off_t pg_start, int type)
2992+{
2993+ int i,j,num_entries, zap;
2994+ void *temp;
2995+ struct list_head *tmp;
2996+ struct client_list_struct *entry;
2997+ unsigned long addr_start=0;
2998+ unsigned long addr_end=0;
2999+ unsigned long addr_offset=0;
3000+ unsigned long vaddr;
3001+ char *srcvirt;
3002+ unsigned long srcphys;
3003+ unsigned long dstphys;
3004+ pgd_t *pgd;
3005+ pud_t *pud;
3006+ pmd_t *pmd;
3007+ pte_t *pte;
3008+
3009+ temp = agp_bridge->current_size;
3010+ num_entries = A_SIZE_FIX(temp)->num_entries;
3011+
3012+ /* If we try to write beyond gtt table, return error */
3013+ if ((pg_start + mem->page_count) > num_entries) {
3014+ AGN_ERROR("Trying to write beyond aperture limit");
3015+ AGN_DEBUG("pg_start=0x%.8lx, mem->page_count=%d,"
3016+ "num_entries=%d", pg_start, mem->page_count,
3017+ num_entries);
3018+ return -EINVAL;
3019+ }
3020+
3021+ /* The i830 can't check the GTT for entries since its read only,
3022+ * depend on the caller to make the correct offset decisions.
3023+ */
3024+
3025+ if ((type != 0 && type != AGP_PHYS_MEMORY) ||
3026+ (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) {
3027+ AGN_ERROR("Unsupported memory type");
3028+ AGN_DEBUG("mem->type=%x, type=%x", mem->type, type);
3029+ return -EINVAL;
3030+ }
3031+
3032+ global_cache_flush();
3033+ agp_bridge->driver->tlb_flush(mem);
3034+
3035+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
3036+
3037+ /* If we're inserting into stolen memory, we need to read
3038+ * the contents of the original page that occupied this space
3039+ */
3040+ if (j < private_data.gtt_entries) {
3041+ srcphys=readl(private_data.gtt+j);
3042+ srcphys &= PAGE_MASK;
3043+
3044+ if (srcphys >= agp_bridge->gart_bus_addr) {
3045+ srcvirt=ioremap(srcphys, PAGE_SIZE);
3046+
3047+ if (!srcvirt) {
3048+ AGN_ERROR("Could not map stolen memory source %d:%08lX", j, srcphys);
3049+ return -ENOMEM;
3050+ }
3051+
3052+ dstphys=AGP_MASK_GTT();
3053+ dstphys &= PAGE_MASK;
3054+
3055+ copy_page(__va(dstphys), srcvirt);
3056+
3057+ iounmap(srcvirt);
3058+ } else {
3059+ AGN_ERROR ("Tried to copy a page not in stolen memory %d:%08lX", j, srcphys);
3060+ }
3061+ }
3062+
3063+ if (private_data.split_gtt && (j >= 0x8000)) {
3064+ writel(AGP_MASK_GTT(), private_data.upper_gtt + j - 0x8000);
3065+ } else {
3066+ writel(AGP_MASK_GTT(), private_data.gtt+j);
3067+ readl(private_data.gtt+j); /* PCI Posting. */
3068+ }
3069+
3070+ down(&client_sem);
3071+ list_for_each(tmp, &client_list) {
3072+ entry = list_entry(tmp, struct client_list_struct, list);
3073+
3074+ /* We need to handle invalidating VMA's that are only mapping
3075+ * a portion of the virtual aperture. Calculate what if
3076+ * any invalidated pages need to be zapped
3077+ */
3078+ addr_start = (entry->vma->vm_pgoff << PAGE_SHIFT)
3079+ - agp_bridge->gart_bus_addr;
3080+ addr_end = addr_start + (entry->vma->vm_end - entry->vma->vm_start);
3081+ addr_offset = j << PAGE_SHIFT;
3082+
3083+ vaddr = entry->vma->vm_start + (addr_offset - addr_start);
3084+
3085+ zap=0;
3086+ pgd=NULL;
3087+ pud=NULL;
3088+ pmd=NULL;
3089+ pte=NULL;
3090+
3091+ pgd = pgd_offset(entry->vma->vm_mm, vaddr);
3092+ if (!pgd_none(*pgd)) {
3093+ pud = pud_offset(pgd, vaddr);
3094+ if (!pud_none(*pud)) {
3095+ pmd = pmd_offset(pud, vaddr);
3096+ if (!pmd_none(*pmd)) {
3097+ pte = pte_offset_map(pmd, vaddr);
3098+ if (!pte_none(*pte)) {
3099+ zap=1;
3100+ }
3101+ }
3102+ }
3103+ }
3104+
3105+ /* Only zap a page if it falls within the mapped region
3106+ * and it has previously faulted
3107+ */
3108+ if (zap && (addr_offset >= addr_start) &&
3109+ (addr_offset < addr_end)) {
3110+
3111+ if (!page_mapcount(pte_page(*pte))) {
3112+ AGN_ERROR("ERROR No mapcount");
3113+ AGN_DEBUG("ZI %p %08lX %d %d %p", pte_page(*pte),
3114+ pte_page(*pte)->flags, page_count(pte_page(*pte)),
3115+ page_mapcount(pte_page(*pte)), pte_page(*pte)->mapping);
3116+ } else {
3117+ atomic_add_negative(-1, &pte_page(*pte)->_mapcount);
3118+ put_page(pte_page(*pte));
3119+ dec_mm_counter(entry->vma->vm_mm, file_rss);
3120+ }
3121+
3122+ pte_clear(entry->vma->vm_mm, vaddr, pte);
3123+ }
3124+
3125+ if(pte) {
3126+ pte_unmap(pte);
3127+ }
3128+ }
3129+ up(&client_sem);
3130+ }
3131+
3132+ global_cache_flush();
3133+ agp_bridge->driver->tlb_flush(mem);
3134+
3135+ AGN_DEBUG("Exit");
3136+ return 0;
3137+}
3138+
3139+
3140+int iegd_plb_remove_entries(struct agp_memory *mem,
3141+ off_t pg_start, int type)
3142+{
3143+ int i, zap;
3144+ struct list_head *tmp;
3145+ struct client_list_struct *entry;
3146+ unsigned long physaddr;
3147+ unsigned long addr_start=0;
3148+ unsigned long addr_end=0;
3149+ unsigned long addr_offset=0;
3150+ unsigned long vaddr;
3151+ pgd_t *pgd;
3152+ pud_t *pud;
3153+ pmd_t *pmd;
3154+ pte_t *pte;
3155+
3156+ global_cache_flush();
3157+ agp_bridge->driver->tlb_flush(mem);
3158+
3159+ for (i = pg_start; i < (mem->page_count + pg_start); i++) {
3160+ if (i < private_data.gtt_entries) {
3161+ physaddr = agp_bridge->gart_bus_addr + (i * PAGE_SIZE);
3162+ physaddr |= 0x01;
3163+ writel(physaddr, private_data.gtt+i);
3164+ readl(private_data.gtt+i); /* PCI Posting. */
3165+ } else {
3166+ if (private_data.split_gtt && (i >= 0x8000)) {
3167+ writel(agp_bridge->scratch_page, private_data.upper_gtt + i - 0x8000);
3168+ } else {
3169+ writel(agp_bridge->scratch_page, private_data.gtt+i);
3170+ readl(private_data.gtt+i); /* PCI Posting. */
3171+ }
3172+ }
3173+
3174+ down(&client_sem);
3175+ list_for_each(tmp, &client_list) {
3176+ entry = list_entry(tmp, struct client_list_struct, list);
3177+
3178+ /* We need to handle invalidating VMA's that are only mapping
3179+ * a portion of the virtual aperture. Calculate what if
3180+ * any invalidated pages need to be zapped
3181+ */
3182+ addr_start = (entry->vma->vm_pgoff << PAGE_SHIFT)
3183+ - agp_bridge->gart_bus_addr;
3184+ addr_end = addr_start + (entry->vma->vm_end - entry->vma->vm_start);
3185+ addr_offset = i << PAGE_SHIFT;
3186+
3187+ vaddr = entry->vma->vm_start + (addr_offset - addr_start);
3188+
3189+ zap=0;
3190+ pgd=NULL;
3191+ pud=NULL;
3192+ pmd=NULL;
3193+ pte=NULL;
3194+
3195+ /* Look up page table entries for all VMAs that currently
3196+ * have the virtual aperture mapped -- to see if the page
3197+ * has ever faulted
3198+ */
3199+ pgd = pgd_offset(entry->vma->vm_mm, vaddr);
3200+ if (!pgd_none(*pgd)) {
3201+ pud = pud_offset(pgd, vaddr);
3202+ if (!pud_none(*pud)) {
3203+ pmd = pmd_offset(pud, vaddr);
3204+ if (!pmd_none(*pmd)) {
3205+ pte = pte_offset_map(pmd, vaddr);
3206+ if (!pte_none(*pte)) {
3207+ zap=1;
3208+ }
3209+ }
3210+ }
3211+ }
3212+
3213+ /* Only zap a page if it falls within the mapped region
3214+ * and it has previously faulted
3215+ */
3216+ if (zap && (addr_offset >= addr_start) &&
3217+ (addr_offset < addr_end)) {
3218+
3219+
3220+ if (!page_mapcount(pte_page(*pte))) {
3221+ AGN_ERROR("ERROR No mapcount");
3222+ AGN_DEBUG("ZR %p %08lX %d %d %p", pte_page(*pte),
3223+ pte_page(*pte)->flags, page_count(pte_page(*pte)),
3224+ page_mapcount(pte_page(*pte)), pte_page(*pte)->mapping);
3225+ } else {
3226+ atomic_add_negative(-1, &pte_page(*pte)->_mapcount);
3227+ put_page(pte_page(*pte));
3228+ dec_mm_counter(entry->vma->vm_mm, file_rss);
3229+ }
3230+
3231+ pte_clear(entry->vma->vm_mm, vaddr, pte);
3232+ }
3233+
3234+ if(pte) {
3235+ pte_unmap(pte);
3236+ }
3237+ }
3238+ up(&client_sem);
3239+ }
3240+
3241+ global_cache_flush();
3242+ agp_bridge->driver->tlb_flush(mem);
3243+
3244+ return 0;
3245+}
3246+
3247+
3248+int iegd_plb_configure(void)
3249+{
3250+ struct aper_size_info_fixed *current_size;
3251+ u32 temp;
3252+ u16 gmch_ctrl;
3253+ int i;
3254+
3255+ current_size = A_SIZE_FIX(agp_bridge->current_size);
3256+
3257+ /* SCH US15 uses the Base of Stolen Memory as it's artificial
3258+ * aperture address
3259+ */
3260+ pci_read_config_dword(private_data.pdev, 0x5C, &temp);
3261+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
3262+
3263+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
3264+ gmch_ctrl |= I830_GMCH_ENABLED;
3265+ pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
3266+
3267+ global_cache_flush();
3268+ agp_bridge->driver->tlb_flush(0);
3269+
3270+ writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED,
3271+ private_data.registers+I810_PGETBL_CTL);
3272+ /* PCI Posting. */
3273+ readl(private_data.registers+I810_PGETBL_CTL);
3274+
3275+ if (agp_bridge->driver->needs_scratch_page) {
3276+
3277+ for (i = private_data.gtt_entries; i < current_size->num_entries; i++) {
3278+ if ((private_data.split_gtt) && (i >= 0x8000)) {
3279+ writel(agp_bridge->scratch_page, private_data.upper_gtt+i-0x8000);
3280+ readl(private_data.upper_gtt+i-0x8000);
3281+ } else {
3282+ writel(agp_bridge->scratch_page, private_data.gtt+i);
3283+ readl(private_data.gtt+i); /* PCI Posting. */
3284+ }
3285+ }
3286+ }
3287+
3288+ global_cache_flush();
3289+
3290+ return 0;
3291+}
3292+
3293+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31)
3294+static void plb_destroy_pages_by_addr(void *addr, size_t pg_count, unsigned int order)
3295+{
3296+ struct page *page;
3297+
3298+ AGN_DEBUG("Enter");
3299+
3300+ if (addr == NULL) {
3301+ return;
3302+ }
3303+
3304+ page = virt_to_page(addr);
3305+ SET_PAGES_WB(page, pg_count);
3306+ GLOBAL_FLUSH_TLB();
3307+ put_page(page);
3308+ AGP_UNLOCK_PAGE(page);
3309+
3310+ if(page_count(page) > 1) {
3311+ free_pages((unsigned long)addr, order);
3312+ }
3313+
3314+ atomic_dec(&agp_bridge->current_memory_agp);
3315+
3316+ AGN_DEBUG("Exit");
3317+}
3318+#else
3319+static void plb_destroy_pages(struct page *page, size_t pg_count, unsigned int order)
3320+{
3321+ //AGN_LOG("IN plb_destroy_pages");
3322+ AGN_DEBUG("Enter");
3323+
3324+ if (page == NULL) {
3325+ return;
3326+ }
3327+
3328+ SET_PAGES_WB(page, pg_count);
3329+ GLOBAL_FLUSH_TLB();
3330+ put_page(page);
3331+ AGP_UNLOCK_PAGE(page);
3332+
3333+ if(page_count(page) > 1) {
3334+ __free_pages(page, order);
3335+ }
3336+
3337+ atomic_dec(&agp_bridge->current_memory_agp);
3338+
3339+ AGN_DEBUG("Exit");
3340+}
3341+#endif
3342+
3343+void iegd_plb_free_by_type(struct agp_memory *curr)
3344+{
3345+ unsigned int order;
3346+
3347+ switch (curr->page_count) {
3348+ case 1:
3349+ order = 0; /* pg_count = 1 => 2 ^ 0 */
3350+ break;
3351+ case 4:
3352+ order = 2; /* pg_count = 4 => 2 ^ 2 */
3353+ break;
3354+ case 8:
3355+ order = 3; /* pg_count = 8 => 2 ^ 3 */
3356+ break;
3357+ default:
3358+ /* This case should never happen */
3359+ return;
3360+ }
3361+
3362+ agp_free_key(curr->key);
3363+ if(curr->type == AGP_PHYS_MEMORY) {
3364+ PLB_DESTROY_PAGES(curr, curr->page_count, order);
3365+ IGD_FREE_MEM(curr);
3366+ }
3367+
3368+ kfree(curr);
3369+
3370+}
3371+
3372+#endif
3373diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/global.c patch_script_temp/drivers/gpu/drm/iegd/agp/global.c
3374--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/global.c 1969-12-31 17:00:00.000000000 -0700
3375+++ patch_script_temp/drivers/gpu/drm/iegd/agp/global.c 2009-10-06 10:30:05.000000000 -0700
3376@@ -0,0 +1,142 @@
3377+/* -*- pse-c -*-
3378+ *----------------------------------------------------------------------------
3379+ * Filename: global.c
3380+ * $Revision: 1.17 $
3381+ *----------------------------------------------------------------------------
3382+ * Gart and DRM driver for Intel Embedded Graphics Driver
3383+ * Copyright © 2008, Intel Corporation.
3384+ *
3385+ * This program is free software; you can redistribute it and/or modify it
3386+ * under the terms and conditions of the GNU General Public License,
3387+ * version 2, as published by the Free Software Foundation.
3388+ *
3389+ * This program is distributed in the hope it will be useful, but WITHOUT
3390+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3391+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3392+ * more details.
3393+ *
3394+ * You should have received a copy of the GNU General Public License along with
3395+ * this program; if not, write to the Free Software Foundation, Inc.,
3396+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3397+ *
3398+ */
3399+
3400+#include "global.h"
3401+#include "intelpci.h"
3402+
3403+/* will point to the current table entries for
3404+ * current chipset */
3405+gart_dispatch_t *gart_id;
3406+
3407+/* Private data that contained chipset information */
3408+dev_private_data_t private_data;
3409+
3410+int iegd_find_device(u16 device)
3411+{
3412+ struct pci_dev *device_pdev;
3413+
3414+ device_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
3415+ /* Check for function 0. */
3416+ if(device_pdev && PCI_FUNC(device_pdev->devfn) != 0) {
3417+ device_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3418+ device, device_pdev);
3419+ }
3420+
3421+ if(!device_pdev) {
3422+ return 0;
3423+ }
3424+
3425+ AGN_DEBUG("Device found = 0x%x\n", device);
3426+ private_data.pdev = device_pdev;
3427+ return 1;
3428+
3429+}
3430+
3431+/**
3432+ * This function is to hook the function pointer that
3433+ * belong to specific chipset, other than that this
3434+ * is the place for customization of the structure
3435+ * in case chipset in the same family have different
3436+ * architecture. Make sure to add new device id here
3437+ * if new device been introduce.
3438+ *
3439+ * parameter:
3440+ * driver_hook - Pointer to hold the structure
3441+ * did - device id
3442+ * list - lookup table for the chipset family
3443+ *
3444+ * return value:
3445+ * 0 - success
3446+ * 1 - No function hook
3447+ */
3448+int bridge_driver_init(bridge_driver_t **driver_hook,
3449+ unsigned short did, dispatch_table_t *list )
3450+{
3451+
3452+ (*driver_hook) = (bridge_driver_t *)dispatch_acquire(
3453+ gart_id->device_id, list);
3454+
3455+ /* For specific chipset implementation assign the pointer
3456+ * here. */
3457+ switch(did) {
3458+ case PCI_DEVICE_ID_GM45:
3459+ case PCI_DEVICE_ID_ELK:
3460+ case PCI_DEVICE_ID_Q45:
3461+ case PCI_DEVICE_ID_G45:
3462+ case PCI_DEVICE_ID_G41:
3463+ (*driver_hook)->aperture_sizes = iegd_igm45_sizes;
3464+ (*driver_hook)->num_aperture_sizes = 2;
3465+ break;
3466+ case PCI_DEVICE_ID_Q35:
3467+ case PCI_DEVICE_ID_Q35A2:
3468+ (*driver_hook)->aperture_sizes = iegd_iq35_sizes;
3469+ (*driver_hook)->num_aperture_sizes = 3;
3470+ break;
3471+ case PCI_DEVICE_ID_915GD:
3472+ case PCI_DEVICE_ID_915AL:
3473+ case PCI_DEVICE_ID_945G:
3474+ case PCI_DEVICE_ID_945GM:
3475+ case PCI_DEVICE_ID_945GME:
3476+ (*driver_hook)->aperture_sizes = iegd_i915_sizes;
3477+ (*driver_hook)->num_aperture_sizes = 4;
3478+ break;
3479+ case PCI_DEVICE_ID_965G:
3480+ case PCI_DEVICE_ID_946GZ:
3481+ case PCI_DEVICE_ID_G965:
3482+ case PCI_DEVICE_ID_Q965:
3483+ case PCI_DEVICE_ID_GM965:
3484+ case PCI_DEVICE_ID_GME965:
3485+ (*driver_hook)->aperture_sizes = iegd_i965_sizes;
3486+ (*driver_hook)->num_aperture_sizes = 4;
3487+ break;
3488+ case PCI_DEVICE_ID_810:
3489+ case PCI_DEVICE_ID_810DC:
3490+ case PCI_DEVICE_ID_810E:
3491+ case PCI_DEVICE_ID_815:
3492+ (*driver_hook)->aperture_sizes = intel_i810_sizes;
3493+ (*driver_hook)->num_aperture_sizes = 2;
3494+ (*driver_hook)->create_gatt_table = agp_generic_create_gatt_table;
3495+ (*driver_hook)->free_gatt_table = agp_generic_free_gatt_table;
3496+ break;
3497+ case PCI_DEVICE_ID_830M:
3498+ case PCI_DEVICE_ID_845G:
3499+ case PCI_DEVICE_ID_855:
3500+ case PCI_DEVICE_ID_865G:
3501+ (*driver_hook)->aperture_sizes = intel_i830_sizes;
3502+ (*driver_hook)->num_aperture_sizes = 4;
3503+ (*driver_hook)->create_gatt_table = iegd_alm_create_gatt_table;
3504+ (*driver_hook)->free_gatt_table = iegd_cmn_free_gatt_table;
3505+ break;
3506+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
3507+ case PCI_DEVICE_ID_PLB:
3508+ (*driver_hook)->aperture_sizes = iegd_plb_sizes;
3509+ (*driver_hook)->num_aperture_sizes = 1;
3510+ break;
3511+#endif
3512+ default:
3513+ return -1;
3514+ }
3515+
3516+ return 0;
3517+
3518+}
3519diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/pci.c patch_script_temp/drivers/gpu/drm/iegd/agp/pci.c
3520--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/agp/pci.c 1969-12-31 17:00:00.000000000 -0700
3521+++ patch_script_temp/drivers/gpu/drm/iegd/agp/pci.c 2009-10-06 10:30:05.000000000 -0700
3522@@ -0,0 +1,501 @@
3523+/* -*- pse-c -*-
3524+ *----------------------------------------------------------------------------
3525+ * Filename: pci.c
3526+ * $Revision: 1.31 $
3527+ *----------------------------------------------------------------------------
3528+ * Gart and DRM driver for Intel Embedded Graphics Driver
3529+ * Copyright © 2008, Intel Corporation.
3530+ *
3531+ * This program is free software; you can redistribute it and/or modify it
3532+ * under the terms and conditions of the GNU General Public License,
3533+ * version 2, as published by the Free Software Foundation.
3534+ *
3535+ * This program is distributed in the hope it will be useful, but WITHOUT
3536+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3537+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3538+ * more details.
3539+ *
3540+ * You should have received a copy of the GNU General Public License along with
3541+ * this program; if not, write to the Free Software Foundation, Inc.,
3542+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3543+ *
3544+ */
3545+
3546+#include <linux/init.h>
3547+#include <linux/module.h>
3548+#include <linux/pci.h>
3549+#include <linux/agp_backend.h>
3550+#include "agp.h"
3551+#include "global.h"
3552+#include "igd_gart.h"
3553+#include "intelpci.h"
3554+#include "igd_abs.h"
3555+
3556+static gart_dispatch_t gart_pci_device_table[] = {
3557+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_810, PCI_DEVICE_ID_810,
3558+ "810", 0, 0, 0,
3559+ },
3560+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_810DC, PCI_DEVICE_ID_810DC,
3561+ "810DC", 0, 0, 0,
3562+ },
3563+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_810E, PCI_DEVICE_ID_810E,
3564+ "810E", 0, 0, 0,
3565+ },
3566+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_815, PCI_DEVICE_ID_815,
3567+ "815", 0, 0, 0,
3568+ },
3569+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_830M, PCI_DEVICE_ID_830M,
3570+ "830M", 0, 0, 0,
3571+ },
3572+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_835, PCI_DEVICE_ID_835,
3573+ "835", 0, 0, 0,
3574+ },
3575+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_845G, PCI_DEVICE_ID_845G,
3576+ "845G", 0, 0, 0,
3577+ },
3578+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_855, PCI_DEVICE_ID_855,
3579+ "855", 0, 0, 0,
3580+ },
3581+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_865G, PCI_DEVICE_ID_865G,
3582+ "865G", 0, 0, 0,
3583+ },
3584+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_915GD, PCI_DEVICE_ID_915GD,
3585+ "915GD", 0, 0, 0,
3586+ },
3587+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_910GL, PCI_DEVICE_ID_910GL,
3588+ "910GL", 0, 0, 0,
3589+ },
3590+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_915AL, PCI_DEVICE_ID_915AL,
3591+ "915AL", 0, 0, 0,
3592+ },
3593+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_945G, PCI_DEVICE_ID_945G,
3594+ "945G", 0, 0, 0,
3595+ },
3596+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_945GM, PCI_DEVICE_ID_945GM,
3597+ "945GM", 0, 0, 0,
3598+ },
3599+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_945GME, PCI_DEVICE_ID_945GME,
3600+ "945GME/GSE", 0, 0, 0,
3601+ },
3602+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_Q35, PCI_DEVICE_ID_Q35,
3603+ "Q33/Q35", 0, 0, 0,
3604+ },
3605+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_Q35A2, PCI_DEVICE_ID_Q35A2,
3606+ "Q33/Q35", 0, 0, 0,
3607+ },
3608+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_965G, PCI_DEVICE_ID_965G,
3609+ "965G", 0, 0, 0,
3610+ },
3611+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_946GZ, PCI_DEVICE_ID_946GZ,
3612+ "946GZ", 0, 0, 0,
3613+ },
3614+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_G965, PCI_DEVICE_ID_G965,
3615+ "G965", 0, 0, 0,
3616+ },
3617+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_Q965, PCI_DEVICE_ID_Q965,
3618+ "Q965", 0, 0, 0,
3619+ },
3620+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_GM965, PCI_DEVICE_ID_GM965,
3621+ "GM965", 0, 0, 0,
3622+ },
3623+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_GME965, PCI_DEVICE_ID_GME965,
3624+ "GLE960/GME965", 0, 0, 0,
3625+ },
3626+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
3627+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_PLB, PCI_DEVICE_ID_PLB,
3628+ "US15", 0, 0, 0,
3629+ },
3630+#endif
3631+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_GM45, PCI_DEVICE_ID_GM45,
3632+ "GM45/GS45/GL40", 0, 0, 0,
3633+ },
3634+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_ELK, PCI_DEVICE_ID_ELK,
3635+ "Q45", 0, 0, 0,
3636+ },
3637+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_Q45, PCI_DEVICE_ID_Q45,
3638+ "Q45", 0, 0, 0,
3639+ },
3640+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_G45, PCI_DEVICE_ID_G45,
3641+ "G45", 0, 0, 0,
3642+ },
3643+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRIDGE_G41, PCI_DEVICE_ID_G41,
3644+ "G41", 0, 0, 0,
3645+ },
3646+};
3647+
3648+/* PCI device id that supported by IEGD */
3649+struct pci_device_id iegd_pci_table[] = {
3650+ ID(PCI_DEVICE_ID_BRIDGE_810),
3651+ ID(PCI_DEVICE_ID_BRIDGE_810DC),
3652+ ID(PCI_DEVICE_ID_BRIDGE_810E),
3653+ ID(PCI_DEVICE_ID_BRIDGE_815),
3654+ ID(PCI_DEVICE_ID_BRIDGE_830M),
3655+ ID(PCI_DEVICE_ID_BRIDGE_845G),
3656+ ID(PCI_DEVICE_ID_BRIDGE_855),
3657+ ID(PCI_DEVICE_ID_BRIDGE_865G),
3658+ ID(PCI_DEVICE_ID_BRIDGE_915GD),
3659+ ID(PCI_DEVICE_ID_BRIDGE_915AL),
3660+ ID(PCI_DEVICE_ID_BRIDGE_945G),
3661+ ID(PCI_DEVICE_ID_BRIDGE_945GM),
3662+ ID(PCI_DEVICE_ID_BRIDGE_945GME),
3663+ ID(PCI_DEVICE_ID_BRIDGE_965G),
3664+ ID(PCI_DEVICE_ID_BRIDGE_946GZ),
3665+ ID(PCI_DEVICE_ID_BRIDGE_G965),
3666+ ID(PCI_DEVICE_ID_BRIDGE_Q965),
3667+ ID(PCI_DEVICE_ID_BRIDGE_GM965),
3668+ ID(PCI_DEVICE_ID_BRIDGE_GME965),
3669+ ID(PCI_DEVICE_ID_BRIDGE_Q35),
3670+ ID(PCI_DEVICE_ID_BRIDGE_Q35A2),
3671+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
3672+ ID(PCI_DEVICE_ID_BRIDGE_PLB),
3673+#endif
3674+ ID(PCI_DEVICE_ID_BRIDGE_GM45),
3675+ ID(PCI_DEVICE_ID_BRIDGE_ELK),
3676+ ID(PCI_DEVICE_ID_BRIDGE_Q45),
3677+ ID(PCI_DEVICE_ID_BRIDGE_G45),
3678+ ID(PCI_DEVICE_ID_BRIDGE_G41),
3679+ { }
3680+};
3681+
3682+MODULE_DEVICE_TABLE(pci, iegd_pci_table);
3683+
3684+#include <asm/tlbflush.h>
3685+
3686+static int agp_has_pat = 0;
3687+
3688+int agp_use_pat(void)
3689+{
3690+ return agp_has_pat;
3691+}
3692+EXPORT_SYMBOL(agp_use_pat);
3693+
3694+static void agp_pat_ipi_handler(void *notused)
3695+{
3696+ u32 v1, v2;
3697+
3698+ rdmsr(MSR_IA32_CR_PAT, v1, v2);
3699+ v2 &= 0xFFFFFFF8;
3700+ v2 |= 0x00000001;
3701+ wbinvd();
3702+ wrmsr(MSR_IA32_CR_PAT, v1, v2);
3703+ __flush_tlb_all();
3704+}
3705+
3706+/*
3707+ * Set i386 PAT entry PAT4 to Write-combining memory type on all processors.
3708+ */
3709+
3710+void agp_init_pat(void)
3711+{
3712+
3713+ if (!boot_cpu_has(X86_FEATURE_PAT)) {
3714+ AGN_ERROR("PAT Feature not available\n");
3715+ return;
3716+ }
3717+ AGN_DEBUG("Enabled PAT");
3718+ if (ON_EACH_CPU(agp_pat_ipi_handler, NULL, 1, 1) != 0) {
3719+ AGN_ERROR("Timed out setting up CPU PAT.\n");
3720+ return;
3721+ }
3722+ agp_has_pat = 1;
3723+}
3724+EXPORT_SYMBOL(agp_init_pat);
3725+
3726+
3727+/* This function get called by PCI core when one of the chipset
3728+ * above detected */
3729+static int __devinit iegd_intel_probe(
3730+ struct pci_dev *pdev,
3731+ const struct pci_device_id *ent)
3732+{
3733+ bridge_data_t *bridge_device;
3734+ u8 cap_ptr = 0;
3735+ struct resource *r;
3736+ int ret;
3737+
3738+ AGN_DEBUG("Enter");
3739+ AGN_LOG("Initialize IEGD agpgart and drm");
3740+
3741+ /* Make sure this probing is called because of prefered
3742+ * chipsets. This is because to make sure we initialize
3743+ * chipset that belong to deregister gart module */
3744+ if(!gart_id->bridge_pdev ||
3745+ (gart_id->bridge_pdev->device != pdev->device)) {
3746+ return -ENODEV;
3747+ }
3748+
3749+ cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
3750+
3751+ /* Allocate memory for the bridge. This data structure then will be
3752+ * used by the agp backend and frontend */
3753+ gart_id->bridge_info = agp_alloc_bridge();
3754+ if(gart_id->bridge_info == NULL) {
3755+ return -ENOMEM;
3756+ }
3757+
3758+ /* Check for the device and initialize private data */
3759+ if(!iegd_find_device(gart_id->device_id)) {
3760+ agp_put_bridge(gart_id->bridge_info);
3761+ AGN_ERROR("Unsupported device: %x", gart_id->device_id);
3762+ return -ENODEV;
3763+ }
3764+
3765+ bridge_device = gart_id->bridge_info;
3766+
3767+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
3768+ if (gart_id->device_id == PCI_DEVICE_ID_PLB) {
3769+ agp_init_pat();
3770+ bridge_device->vm_ops = &iegd_plb_vm_ops;
3771+ }
3772+#endif
3773+
3774+ AGN_DEBUG("driver %p, id %X, list %p", bridge_device->driver,
3775+ gart_id->device_id, driver_dispatch_list);
3776+ /* Dispatch the core function based on the chipset id */
3777+ ret = bridge_driver_init((bridge_driver_t **) &bridge_device->driver,
3778+ gart_id->device_id, driver_dispatch_list);
3779+
3780+ if(ret) {
3781+ agp_put_bridge(gart_id->bridge_info);
3782+ AGN_ERROR("Device found but no function hook");
3783+ return -ENODEV;
3784+ }
3785+
3786+ bridge_device->dev = pdev;
3787+ bridge_device->capndx = cap_ptr;
3788+ bridge_device->dev_private_data = &private_data;
3789+
3790+ AGN_LOG("Intel %s chipset detected", gart_id->name);
3791+
3792+ r = &pdev->resource[0];
3793+ if (!r->start && r->end) {
3794+ if (pci_assign_resource(pdev, 0)) {
3795+ AGN_ERROR("could not assign resource 0");
3796+ agp_put_bridge(gart_id->bridge_info);
3797+ return -ENODEV;
3798+ }
3799+ }
3800+
3801+ if(pci_enable_device(pdev)) {
3802+ AGN_ERROR("Unable to enable PCI device");
3803+ agp_put_bridge(gart_id->bridge_info);
3804+ return -ENODEV;
3805+ }
3806+
3807+ if(cap_ptr) {
3808+ pci_read_config_dword(pdev,
3809+ bridge_device->capndx+PCI_AGP_STATUS,
3810+ &bridge_device->mode);
3811+ }
3812+
3813+ pci_set_drvdata(pdev, bridge_device);
3814+ AGN_DEBUG("Exit");
3815+ return agp_add_bridge(bridge_device);
3816+}
3817+
3818+static void iegd_intel_remove(struct pci_dev *pdev)
3819+{
3820+ AGN_LOG("Exit from module");
3821+}
3822+
3823+int iegd_intel_suspend(struct pci_dev *dev, pm_message_t state)
3824+{
3825+ int pm_cap;
3826+ struct pci_dev *iegd_dev;
3827+ unsigned short pci_pm_csr;
3828+
3829+ AGN_DEBUG("Enter");
3830+
3831+ if (!(IGD_IS_SUSPEND(state))) {
3832+ AGN_DEBUG("Unsupported PM event %d", state.event);
3833+ return -EINVAL;
3834+ }
3835+
3836+ iegd_dev = private_data.pdev;
3837+
3838+ /* Save our resources */
3839+ IGD_PCI_SAVE_STATE(iegd_dev, private_data.pm_save);
3840+
3841+ /* Find the PM CSR */
3842+ pm_cap = pci_find_capability(iegd_dev, PCI_CAP_ID_PM);
3843+
3844+ if (!pm_cap) {
3845+ AGN_DEBUG("No PCI PM capability record.. Exit");
3846+ return 0;
3847+ }
3848+
3849+ /* Power down the device */
3850+ pci_read_config_word(iegd_dev, pm_cap + PCI_PM_CTRL, &pci_pm_csr);
3851+ pci_pm_csr |= PCI_PM_CTRL_STATE_MASK;
3852+ pci_write_config_word(iegd_dev, pm_cap + PCI_PM_CTRL, pci_pm_csr);
3853+
3854+ AGN_DEBUG("Suspended.. Exit");
3855+ return 0;
3856+}
3857+
3858+int iegd_intel_resume(struct pci_dev *dev)
3859+{
3860+ int pm_cap;
3861+ struct pci_dev *iegd_dev;
3862+ unsigned short pci_pm_csr;
3863+
3864+ AGN_DEBUG("Enter");
3865+
3866+ iegd_dev = private_data.pdev;
3867+
3868+ /* Get back our resources */
3869+ IGD_PCI_RESTORE_STATE(iegd_dev, private_data.pm_save);
3870+
3871+ /* Find the PM CSR */
3872+ pm_cap = pci_find_capability(iegd_dev, PCI_CAP_ID_PM);
3873+
3874+ if (!pm_cap) {
3875+ AGN_DEBUG("No PCI PM capability record.. Exit");
3876+ return 0;
3877+ }
3878+
3879+ /* Power on device */
3880+ pci_read_config_word(iegd_dev, pm_cap + PCI_PM_CTRL, &pci_pm_csr);
3881+ pci_pm_csr &= ~PCI_PM_CTRL_STATE_MASK;
3882+ pci_write_config_word(iegd_dev, pm_cap + PCI_PM_CTRL, pci_pm_csr);
3883+
3884+ AGN_DEBUG("Resumed.. Exit");
3885+ return 0;
3886+}
3887+
3888+static struct pci_driver iegd_pci_driver = {
3889+ .name = "iegd-intel",
3890+ .id_table = iegd_pci_table,
3891+ .probe = iegd_intel_probe,
3892+ .remove = __devexit_p(iegd_intel_remove),
3893+ .suspend = iegd_intel_suspend,
3894+ .resume = iegd_intel_resume,
3895+};
3896+
3897+struct pci_dev *iegd_probe_device()
3898+{
3899+ int i;
3900+ struct pci_dev *dev;
3901+
3902+ AGN_DEBUG("Enter");
3903+
3904+ /* Probed for the supported devices */
3905+ for(i=0 ; i<sizeof(gart_pci_device_table)/sizeof(gart_dispatch_t);
3906+ i++) {
3907+ dev = pci_get_device(PCI_VENDOR_ID_INTEL,
3908+ (unsigned int)gart_pci_device_table[i].bridge_id, NULL);
3909+ if(dev){
3910+ gart_id = &gart_pci_device_table[i];
3911+ AGN_DEBUG("Device found.. Exit");
3912+ return dev;
3913+ }
3914+ }
3915+ AGN_DEBUG("Device not found.. Exit");
3916+ return NULL;
3917+}
3918+
3919+/**
3920+ * This is the first routine been called by the init function.
3921+ * This function will probe for devices that supported by IEGD.
3922+ * Once it found the device, it will check whether driver for
3923+ * this device exist. If it exist, get the pci_driver structure
3924+ * for the existing driver and call the pci unregister fucntion
3925+ * to deregister existing driver and register iegd agpgart
3926+ */
3927+static int iegd_agp_init(void)
3928+{
3929+ struct pci_driver *curr_driver;
3930+ struct pci_dev *temp_pdev;
3931+
3932+ AGN_DEBUG("Enter");
3933+
3934+ /* Probe for the intel embedded graphic device chipset */
3935+ temp_pdev = iegd_probe_device();
3936+
3937+ if(!temp_pdev) {
3938+ AGN_ERROR("Probe device failed");
3939+ return -ENODEV;
3940+ }
3941+
3942+ gart_id->bridge_pdev = temp_pdev;
3943+ curr_driver = pci_dev_driver(gart_id->bridge_pdev);
3944+
3945+ if(curr_driver) {
3946+ /* FIXME: Don't know whether we have to make separate copy of this
3947+ * structure */
3948+ gart_id->old_gart = curr_driver;
3949+
3950+ /* deregister pci driver from pci core. This is needed since we
3951+ * don't want 2 agpgart reside in the kernel that respond to the
3952+ * same device id */
3953+ AGN_LOG("Unregister agpgart name %s", curr_driver->name);
3954+ pci_unregister_driver(curr_driver);
3955+ }
3956+
3957+ AGN_LOG("Registering iegd gart module");
3958+ /* Register our own to pci core */
3959+ AGN_DEBUG("Exit");
3960+ return pci_register_driver(&iegd_pci_driver);
3961+
3962+}
3963+
3964+static void iegd_restore_device(void)
3965+{
3966+ int ret;
3967+
3968+ AGN_DEBUG("Enter");
3969+
3970+ /* Decrement the reference for this pci device */
3971+ pci_dev_put(gart_id->bridge_pdev);
3972+
3973+ if(gart_id->old_gart) {
3974+ /* Register the original driver */
3975+ ret = pci_register_driver(gart_id->old_gart);
3976+ }
3977+
3978+ AGN_DEBUG("Exit");
3979+
3980+}
3981+
3982+static int iegd_gart_init(void)
3983+{
3984+ int ret;
3985+
3986+ AGN_DEBUG("Enter");
3987+
3988+ /* Find bridge based on chipset supported by IEGD */
3989+ ret = iegd_agp_init();
3990+ if(AGP_RET(ret)) {
3991+ AGN_LOG("Registering iegd drm module");
3992+ /* Initialize DRM module by calling DRM init function */
3993+ return DRM_INIT_MODULE();
3994+ } else {
3995+ /* Log the driver failed to register */
3996+ AGN_LOG("Driver registration failed");
3997+ }
3998+
3999+ AGN_DEBUG("Exit");
4000+
4001+ /* Return agp error if agp init failed */
4002+ return ret;
4003+}
4004+
4005+static void iegd_gart_exit(void)
4006+{
4007+ /* Unregister DRM module */
4008+ AGN_DEBUG("Unregister iegd DRM module");
4009+ DRM_EXIT_MODULE();
4010+
4011+ /* Remove our device from the kernel */
4012+ AGN_DEBUG("Unregister IKM module");
4013+ pci_unregister_driver(&iegd_pci_driver);
4014+
4015+ /* Restore back the old agp gart */
4016+ AGN_DEBUG("Register original module");
4017+ iegd_restore_device();
4018+}
4019+
4020+MODULE_LICENSE("GPL and additional rights");
4021+
4022+module_init(iegd_gart_init);
4023+module_exit(iegd_gart_exit);
4024diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/drm_test.c patch_script_temp/drivers/gpu/drm/iegd/drm/drm_test.c
4025--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/drm_test.c 1969-12-31 17:00:00.000000000 -0700
4026+++ patch_script_temp/drivers/gpu/drm/iegd/drm/drm_test.c 2009-10-06 10:30:05.000000000 -0700
4027@@ -0,0 +1,288 @@
4028+/* -*- pse-c -*-
4029+ *----------------------------------------------------------------------------
4030+ * Filename: drm_test.c
4031+ * $Revision: 1.3 $
4032+ *----------------------------------------------------------------------------
4033+ * Unit level test for IEGD DRM
4034+ * Copyright © 2009 Intel Corporation.
4035+ *
4036+ * This program is free software; you can redistribute it and/or modify it
4037+ * under the terms and conditions of the GNU General Public License,
4038+ * version 2, as published by the Free Software Foundation.
4039+ *
4040+ * This program is distributed in the hope it will be useful, but WITHOUT
4041+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4042+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4043+ * more details.
4044+ *
4045+ * You should have received a copy of the GNU General Public License along with
4046+ * this program; if not, write to the Free Software Foundation, Inc.,
4047+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4048+ *
4049+ */
4050+
4051+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
4052+ *
4053+ * Redistribution and use in source and binary forms, with or without
4054+ * modification, are permitted provided that the following conditions are met:
4055+ * Redistributions of source code must retain the above copyright notice,
4056+ * this list of conditions and the following disclaimer.
4057+ *
4058+ * Redistributions in binary form must reproduce the above copyright
4059+ * notice, this list of conditions and the following disclaimer in the
4060+ * documentation and/or other materials provided with the distribution.
4061+ *
4062+ * Neither the name Intel Corporation nor the names of its contributors
4063+ * may be used to endorse or promote products derived from this software
4064+ * without specific prior written permission.
4065+ *
4066+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4067+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4068+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4069+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
4070+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4071+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4072+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
4073+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4074+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
4075+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4076+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4077+ *
4078+ */
4079+
4080+#include <fcntl.h>
4081+#include <unistd.h>
4082+#include <sys/ioctl.h>
4083+#include <stdlib.h>
4084+#include <stdio.h>
4085+#include <string.h>
4086+
4087+#include "iegd.h"
4088+#include "iegd_drm_client.h"
4089+
4090+#define DRM_IOCTL_BASE 'd'
4091+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
4092+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
4093+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
4094+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
4095+
4096+#define DRM_IOCTL_INTEL_GETPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4097+ DRM_INTEL_GETPAGES, drm_intel_getpages_t)
4098+#define DRM_IOCTL_INTEL_FREEPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4099+ DRM_INTEL_FREEPAGES, drm_intel_freepages_t)
4100+#define DRM_IOCTL_INTEL_INFO_INIT DRM_IOW( DRM_BASE_COMMAND + \
4101+ DRM_INTEL_INFO_INIT, intel_drm_info_t)
4102+#define DRM_IOCTL_INTEL_INFO_GET DRM_IOR( DRM_BASE_COMMAND + \
4103+ DRM_INTEL_INFO_GET, intel_drm_info_t)
4104+
4105+#define PAGE_SIZE 4096
4106+
4107+#define VERBOSE "-v"
4108+
4109+int main(int argc, char *argv[])
4110+{
4111+ int file_desc, ret_value, i;
4112+ unsigned long *virt_ptr;
4113+ int failed=0;
4114+
4115+ /* Check for verbose mode */
4116+ int index;
4117+ int verbose = 0;
4118+
4119+ for (index = 1; index < argc; index++)
4120+ {
4121+ if(strcmp(argv[index], VERBOSE) == 0)
4122+ {
4123+ verbose = 1;
4124+ printf("Verbose mode.\n");
4125+ }
4126+ }
4127+
4128+ if (verbose)
4129+ {
4130+ printf("Starting client\n");
4131+ }
4132+ /* Open the drm */
4133+ file_desc=open("/dev/dri/card0",O_RDWR);
4134+
4135+ if(file_desc<0){
4136+ /* In case of a different /dev tree struct.
4137+ * try /dev/card0
4138+ */
4139+ file_desc=open("/dev/card0",O_RDWR);
4140+ }
4141+
4142+ if(file_desc<0){
4143+ printf("Can't open device file:%s\n",DRIVER_DESC);
4144+ printf("Check for root level permissions.");
4145+ printf("Reinstall IKM.\n");
4146+ exit(-1);
4147+ }
4148+
4149+ if (verbose)
4150+ {
4151+ printf("Open device file:%d\n",file_desc);
4152+ /* This the ioctl that allocates physical memory */
4153+ printf("Testing ioctl for memory allocation\n");
4154+ }
4155+
4156+ drm_intel_getpages_t getpages;
4157+ /* set the number of bytes we want the drm to allocate */
4158+ getpages.size=(PAGE_SIZE- 1000);
4159+
4160+ ret_value=ioctl(file_desc,DRM_IOCTL_INTEL_GETPAGES,&getpages);
4161+ if (verbose)
4162+ {
4163+ printf("IOCTL call memory allocation test:");
4164+ }
4165+ if(ret_value<0){
4166+ printf("DRM module failed memory allocation test.\n");
4167+ printf("Reinstall IKM.\n");
4168+ exit(-1);
4169+ }
4170+ if (verbose)
4171+ {
4172+ printf(" Success\n");
4173+ printf("size: %d,phy_address: %#x,virt_address: %#x,offset: %#x\n",
4174+ getpages.size, getpages.phy_address, getpages.virt_address,
4175+ getpages.offset);
4176+
4177+ /* test for memory access */
4178+
4179+ printf("Testing ioctl for memory access\n");
4180+ }
4181+
4182+ virt_ptr=(unsigned long *)getpages.virt_address;
4183+
4184+ /* input 0..10 into subsequent memory */
4185+
4186+ for(i=0;i<=11;i++){
4187+ *virt_ptr=i;
4188+ virt_ptr++;
4189+ }
4190+
4191+ /*read from subsequent memory */
4192+ virt_ptr=(unsigned long *)getpages.virt_address;
4193+ for(i=0;i<=11;i++){
4194+ if (verbose)
4195+ {
4196+ printf("virt_ptr @ %#x,value: %d\n",virt_ptr,*virt_ptr);
4197+ }
4198+ if(*virt_ptr!=i){
4199+ printf("Failed memory read.\n");
4200+ }
4201+ virt_ptr++;
4202+ }
4203+ if (verbose)
4204+ {
4205+ printf("IOCTL call memory access test:");
4206+ }
4207+ if(failed){
4208+ printf("DRM module failed memory access test.\n");
4209+ printf("Reinstall IKM.\n");
4210+ exit(-1);
4211+ }
4212+ if (verbose)
4213+ {
4214+ printf(" Success\n");
4215+ }
4216+ /* freeing memory */
4217+
4218+ drm_intel_freepages_t freepages;
4219+ freepages.size=getpages.size;
4220+ freepages.phy_address=getpages.phy_address;
4221+ freepages.virt_address=getpages.virt_address;
4222+ if (verbose)
4223+ {
4224+ printf("Freeing phy_address:%#x,size:%#x\n",
4225+ freepages.phy_address,freepages.size);
4226+
4227+ printf("Testing ioctl call for info init\n");
4228+ }
4229+ /* init the drm info structure in the drm and test its value */
4230+ intel_drm_info_t info;
4231+ intel_drm_info_t test_info;
4232+ info.device_id=0x456;
4233+ info.revision=333;
4234+ info.video_memory_offset=0x10245;
4235+ info.video_memory_size=987;
4236+ info.hw_status_offset=0x444;
4237+ if (verbose)
4238+ {
4239+
4240+ printf("Testing init info device_id: %#x,revision: %d,offset: %#x,"
4241+ " size: %d, hw_status_offset: %lx\n", info.device_id, info.revision,
4242+ info.video_memory_offset, info.video_memory_size,
4243+ info.hw_status_offset);
4244+ }
4245+
4246+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
4247+
4248+ if (verbose)
4249+ {
4250+ printf("Alternative data to init\n");
4251+ }
4252+ /* init the drm info structure in the drm and test its value */
4253+ info.device_id=0x123;
4254+ info.revision=456;
4255+ info.video_memory_offset=0x789;
4256+ info.video_memory_size=111;
4257+ info.hw_status_offset=0x555;
4258+
4259+ if (verbose)
4260+ {
4261+ printf("Testing init 2nd info device_id: %#x,revision: %d,offset: %#x,"
4262+ " size: %d, hw_status_offset: %lx\n", info.device_id, info.revision,
4263+ info.video_memory_offset, info.video_memory_size,
4264+ info.hw_status_offset);
4265+
4266+ printf("Get init info\n");
4267+ }
4268+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_GET,&test_info);
4269+
4270+ if (verbose)
4271+ {
4272+ printf("IOCTL call for info init:");
4273+ printf("Got init info device_id: %#x,revision: %d,"
4274+ "offset: %#x,size:%d, hw_status_offset: %lx\n", test_info.device_id,
4275+ test_info.revision, test_info.video_memory_offset,
4276+ test_info.video_memory_size, test_info.hw_status_offset);
4277+ }
4278+
4279+ /* compare with original data to see if its still the same */
4280+ info.device_id=0x456;
4281+ info.revision=333;
4282+ info.video_memory_offset=0x10245;
4283+ info.video_memory_size=987;
4284+ info.hw_status_offset=0x444;
4285+ failed=0;
4286+
4287+ if(info.device_id!=test_info.device_id){
4288+ failed=1;
4289+ }
4290+ if(info.revision!=test_info.revision){
4291+ failed=1;
4292+ }
4293+ if(info.video_memory_offset!=test_info.video_memory_offset){
4294+ failed=1;
4295+ }
4296+ if(info.video_memory_size!=test_info.video_memory_size){
4297+ failed=1;
4298+ }
4299+ if(info.hw_status_offset!=test_info.hw_status_offset){
4300+ failed=1;
4301+ }
4302+
4303+ if(failed){
4304+ printf("DRM module failed IOCTL info did not match.\n");
4305+ printf("Reinstall IKM.");
4306+ exit(-1);
4307+ }
4308+
4309+ printf("DRM successfully loaded\n");
4310+
4311+ close(file_desc);
4312+
4313+ return 0;
4314+
4315+}
4316diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/drmult.c patch_script_temp/drivers/gpu/drm/iegd/drm/drmult.c
4317--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/drmult.c 1969-12-31 17:00:00.000000000 -0700
4318+++ patch_script_temp/drivers/gpu/drm/iegd/drm/drmult.c 2009-10-06 10:30:05.000000000 -0700
4319@@ -0,0 +1,270 @@
4320+/* -*- pse-c -*-
4321+ *----------------------------------------------------------------------------
4322+ * Filename: drmult.c
4323+ * $Revision: 1.7 $
4324+ *----------------------------------------------------------------------------
4325+ * Unit level test for IEGD DRM
4326+ * Copyright © 2008, Intel Corporation.
4327+ *
4328+ * This program is free software; you can redistribute it and/or modify it
4329+ * under the terms and conditions of the GNU General Public License,
4330+ * version 2, as published by the Free Software Foundation.
4331+ *
4332+ * This program is distributed in the hope it will be useful, but WITHOUT
4333+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4334+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4335+ * more details.
4336+ *
4337+ * You should have received a copy of the GNU General Public License along with
4338+ * this program; if not, write to the Free Software Foundation, Inc.,
4339+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4340+ *
4341+ */
4342+
4343+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
4344+ *
4345+ * Redistribution and use in source and binary forms, with or without
4346+ * modification, are permitted provided that the following conditions are met:
4347+ * Redistributions of source code must retain the above copyright notice,
4348+ * this list of conditions and the following disclaimer.
4349+ *
4350+ * Redistributions in binary form must reproduce the above copyright
4351+ * notice, this list of conditions and the following disclaimer in the
4352+ * documentation and/or other materials provided with the distribution.
4353+ *
4354+ * Neither the name Intel Corporation nor the names of its contributors
4355+ * may be used to endorse or promote products derived from this software
4356+ * without specific prior written permission.
4357+ *
4358+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4359+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4360+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4361+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
4362+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4363+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4364+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
4365+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4366+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
4367+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4368+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4369+ *
4370+ */
4371+
4372+/*client to test the ioctl
4373+ * make sure you change the permission bits in intel.h to 0,0
4374+ * before you start using this
4375+ */
4376+
4377+#include "iegd.h"
4378+
4379+#include <fcntl.h>
4380+#include <unistd.h>
4381+#include <sys/ioctl.h>
4382+#include <stdlib.h>
4383+#include <stdio.h>
4384+
4385+#if 0
4386+#define DRM_IOCTL_BASE 'd'
4387+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
4388+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
4389+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
4390+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
4391+#endif
4392+
4393+#include "iegd_drm_client.h"
4394+
4395+#if 0
4396+#define DRM_IOCTL_INTEL_GETPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4397+ DRM_INTEL_GETPAGES, drm_intel_getpages_t)
4398+#define DRM_IOCTL_INTEL_FREEPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4399+ DRM_INTEL_FREEPAGES, drm_intel_freepages_t)
4400+#define DRM_IOCTL_INTEL_INFO_INIT DRM_IOW( DRM_BASE_COMMAND + \
4401+ DRM_INTEL_INFO_INIT, intel_drm_info_t)
4402+#define DRM_IOCTL_INTEL_INFO_GET DRM_IOR( DRM_BASE_COMMAND + \
4403+ DRM_INTEL_INFO_GET, intel_drm_info_t)
4404+#endif
4405+
4406+
4407+#define PAGE_SIZE 4096
4408+int main()
4409+{
4410+int file_desc, ret_value;
4411+printf("Starting client\n");
4412+/* Open the drm */
4413+file_desc=open("/dev/dri/card0",O_RDWR);
4414+
4415+if(file_desc<0){
4416+/* Suse has a different /dev tree struct.
4417+ * try /dev/card0
4418+ */
4419+
4420+file_desc=open("/dev/card0",O_RDWR);
4421+
4422+}
4423+
4424+if(file_desc<0){
4425+ printf("Can't open device file:%s\n",DRIVER_DESC);
4426+ exit(-1);
4427+}
4428+
4429+printf("Open device file:%d\n",file_desc);
4430+
4431+
4432+/* Test interrupt IOCTL */
4433+interrupt_info_t irq_info;
4434+
4435+irq_info.req_status = 0;
4436+irq_info.req_type = READ_INT; /* CLEAR_INT, WAIT_INT */
4437+irq_info.in[0] = 0xffffffff;
4438+irq_info.in[1] = 0xffffffff;
4439+irq_info.in[2] = 0xffffffff;
4440+irq_info.in[3] = 0xffffffff;
4441+irq_info.in[4] = 0xa5a5a5a5;
4442+irq_info.in[5] = 0xdeadbeef;
4443+
4444+ret_value = ioctl(file_desc, DRM_IOCTL_INTEL_INTERRUPT, &irq_info);
4445+printf("ULT IOCTL call read interrupt tests: %d\n\n", irq_info.req_status);
4446+
4447+irq_info.req_status = 0;
4448+irq_info.req_type = WAIT_INT;
4449+irq_info.in[0] = 0xffffffff;
4450+irq_info.in[1] = 0xffffffff;
4451+irq_info.in[2] = 0xffffffff;
4452+irq_info.in[3] = 0xffffffff;
4453+
4454+ret_value = ioctl(file_desc, DRM_IOCTL_INTEL_INTERRUPT, &irq_info);
4455+printf("ULT IOCTL call wait interrupt tests: %d\n\n", irq_info.req_status);
4456+
4457+
4458+
4459+/* This the ioctl that allocates physical memory */
4460+printf("ULT: Testing ioctl for memory allocation\n");
4461+
4462+drm_intel_getpages_t getpages;
4463+/* set the number of bytes we want the drm to allocate */
4464+getpages.size=(PAGE_SIZE- 1000);
4465+
4466+ret_value=ioctl(file_desc,DRM_IOCTL_INTEL_GETPAGES,&getpages);
4467+printf("ULT IOCTL call memory allocation test:");
4468+if(ret_value<0){
4469+ printf(" Failed\n");
4470+ exit(-1);
4471+}
4472+printf(" Success\n");
4473+printf("size%d,phy_address:%#x,virt_address:%#x,offset:%#x\n",getpages.size,getpages.phy_address,getpages.virt_address,getpages.offset);
4474+
4475+/* test for memory access */
4476+
4477+printf("ULT: Testing ioctl for memory access\n");
4478+int i;
4479+unsigned long *virt_ptr;
4480+
4481+virt_ptr=(unsigned long *)getpages.virt_address;
4482+
4483+/* input 0..10 into subsequent memory */
4484+
4485+for(i=0;i<=11;i++){
4486+*virt_ptr=i;
4487+virt_ptr++;
4488+
4489+}
4490+
4491+/*read from subsequent memory */
4492+int failed=0;
4493+virt_ptr=(unsigned long *)getpages.virt_address;
4494+for(i=0;i<=11;i++){
4495+ printf("virt_ptr@%#x,value:%d\n",virt_ptr,*virt_ptr);
4496+ if(*virt_ptr!=i){
4497+ printf("Test failed!\n");
4498+ }
4499+virt_ptr++;
4500+}
4501+printf("ULT IOCTL call memory access test:");
4502+if(failed){
4503+ printf(" Failed\n");
4504+ exit(-1);
4505+}
4506+
4507+ printf(" Success\n");
4508+/* freeing memory */
4509+
4510+drm_intel_freepages_t freepages;
4511+freepages.size=getpages.size;
4512+freepages.phy_address=getpages.phy_address;
4513+freepages.virt_address=getpages.virt_address;
4514+printf("Freeing phy_address:%#x,size:%#x\n",freepages.phy_address,freepages.size);
4515+
4516+/* init the drm info structure in the drm and test its value */
4517+
4518+printf("ULT: Testing ioctl call for info init\n");
4519+ intel_drm_info_t info;
4520+ intel_drm_info_t test_info;
4521+ info.device_id=0x456;
4522+ info.revision=333;
4523+ info.video_memory_offset=0x10245;
4524+ info.video_memory_size=987;
4525+ info.hw_status_offset=0x444;
4526+
4527+ printf("Testing init info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
4528+ info.device_id,info.revision,info.video_memory_offset,info.video_memory_size,info.hw_status_offset);
4529+
4530+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
4531+
4532+/* init the drm info structure in the drm and test its value */
4533+printf("Alternative data to init\n");
4534+ info.device_id=0x123;
4535+ info.revision=456;
4536+ info.video_memory_offset=0x789;
4537+ info.video_memory_size=111;
4538+ info.hw_status_offset=0x555;
4539+
4540+ printf("Testing init 2nd info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
4541+ info.device_id,info.revision,info.video_memory_offset,info.video_memory_size,info.hw_status_offset);
4542+
4543+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
4544+
4545+
4546+printf("Get init info\n");
4547+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_GET,&test_info);
4548+
4549+ printf("Got init info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
4550+ test_info.device_id,test_info.revision,test_info.video_memory_offset,test_info.video_memory_size,test_info.hw_status_offset);
4551+/* compare with original data to see if its still the same */
4552+info.device_id=0x456;
4553+info.revision=333;
4554+info.video_memory_offset=0x10245;
4555+info.video_memory_size=987;
4556+info.hw_status_offset=0x444;
4557+failed=0;
4558+
4559+if(info.device_id!=test_info.device_id){
4560+ failed=1;
4561+}
4562+if(info.revision!=test_info.revision){
4563+ failed=1;
4564+}
4565+if(info.video_memory_offset!=test_info.video_memory_offset){
4566+ failed=1;
4567+}
4568+if(info.video_memory_size!=test_info.video_memory_size){
4569+ failed=1;
4570+}
4571+if(info.hw_status_offset!=test_info.hw_status_offset){
4572+ failed=1;
4573+}
4574+
4575+printf("ULT IOCTL call for info init:");
4576+if(failed){
4577+ printf(" Failed\n");
4578+ exit(-1);
4579+}
4580+
4581+ printf(" Success\n");
4582+
4583+close(file_desc);
4584+/*
4585+sleep(100000000000);
4586+*/
4587+return 0;
4588+
4589+}
4590diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd.h
4591--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd.h 1969-12-31 17:00:00.000000000 -0700
4592+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd.h 2009-10-06 10:30:05.000000000 -0700
4593@@ -0,0 +1,117 @@
4594+
4595+/* -*- pse-c -*-
4596+ *----------------------------------------------------------------------------
4597+ * Filename: iegd.h
4598+ * $Revision: 1.7 $
4599+ *----------------------------------------------------------------------------
4600+ * Gart and DRM driver for Intel Embedded Graphics Driver
4601+ * Copyright © 2008, Intel Corporation.
4602+ *
4603+ * This program is free software; you can redistribute it and/or modify it
4604+ * under the terms and conditions of the GNU General Public License,
4605+ * version 2, as published by the Free Software Foundation.
4606+ *
4607+ * This program is distributed in the hope it will be useful, but WITHOUT
4608+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4609+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4610+ * more details.
4611+ *
4612+ * You should have received a copy of the GNU General Public License along with
4613+ * this program; if not, write to the Free Software Foundation, Inc.,
4614+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4615+ *
4616+ */
4617+
4618+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
4619+ *
4620+ * Redistribution and use in source and binary forms, with or without
4621+ * modification, are permitted provided that the following conditions are met:
4622+ * Redistributions of source code must retain the above copyright notice,
4623+ * this list of conditions and the following disclaimer.
4624+ *
4625+ * Redistributions in binary form must reproduce the above copyright
4626+ * notice, this list of conditions and the following disclaimer in the
4627+ * documentation and/or other materials provided with the distribution.
4628+ *
4629+ * Neither the name Intel Corporation nor the names of its contributors
4630+ * may be used to endorse or promote products derived from this software
4631+ * without specific prior written permission.
4632+ *
4633+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4634+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4635+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4636+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
4637+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4638+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4639+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
4640+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4641+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
4642+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4643+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4644+ *
4645+ */
4646+#include <linux/version.h>
4647+#ifndef __IEGD_H__
4648+#define __IEGD_H__
4649+
4650+/* General customization:
4651+ */
4652+#define __HAVE_AGP 1
4653+#define __MUST_HAVE_AGP 0
4654+#define __HAVE_MTRR 0
4655+#define __HAVE_CTX_BITMAP 1
4656+
4657+#define DRIVER_AUTHOR " "
4658+
4659+#define DRIVER_NAME "iegd"
4660+#define DRIVER_DESC "Intel DRM"
4661+#define DRIVER_DATE "20081022"
4662+
4663+#define DRIVER_MAJOR 1
4664+#define DRIVER_MINOR 0
4665+#define DRIVER_PATCHLEVEL 1
4666+
4667+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,5)
4668+#define KERNEL265 1
4669+#endif
4670+
4671+#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)) && \
4672+ (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)))
4673+#define KERNEL2611 1
4674+#endif
4675+
4676+#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)) && \
4677+ (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)))
4678+#define KERNEL2615 1
4679+#endif
4680+
4681+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
4682+#define KERNEL2624 1
4683+#endif
4684+
4685+#ifndef KERNEL265
4686+#define KERNEL265 0
4687+#endif
4688+
4689+#ifndef KERNEL2611
4690+#define KERNEL2611 0
4691+#endif
4692+
4693+#ifndef KERNEL2615
4694+#define KERNEL2615 0
4695+#endif
4696+
4697+#ifndef KERNEL2624
4698+#define KERNEL2624 0
4699+#endif
4700+
4701+/* For some arcane reasons certain stuff needs to be defined in this file.
4702+ * This is being defined in intel_interface_265.h.If not the drm won't
4703+ * compile properly.
4704+ */
4705+#include "iegd_interface_265.h"
4706+#include "iegd_interface_2611.h"
4707+#include "iegd_interface_2615.h"
4708+#include "iegd_interface_2624.h"
4709+
4710+#endif
4711diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drm.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drm.h
4712--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drm.h 1969-12-31 17:00:00.000000000 -0700
4713+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drm.h 2009-10-06 10:30:05.000000000 -0700
4714@@ -0,0 +1,116 @@
4715+/* -*- pse-c -*-
4716+ *----------------------------------------------------------------------------
4717+ * Filename: iegd_drm.h
4718+ * $Revision: 1.7 $
4719+ *----------------------------------------------------------------------------
4720+ * Gart and DRM driver for Intel Embedded Graphics Driver
4721+ * Copyright © 2008, Intel Corporation.
4722+ *
4723+ * This program is free software; you can redistribute it and/or modify it
4724+ * under the terms and conditions of the GNU General Public License,
4725+ * version 2, as published by the Free Software Foundation.
4726+ *
4727+ * This program is distributed in the hope it will be useful, but WITHOUT
4728+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4729+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4730+ * more details.
4731+ *
4732+ * You should have received a copy of the GNU General Public License along with
4733+ * this program; if not, write to the Free Software Foundation, Inc.,
4734+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4735+ *
4736+ */
4737+
4738+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
4739+ *
4740+ * Redistribution and use in source and binary forms, with or without
4741+ * modification, are permitted provided that the following conditions are met:
4742+ * Redistributions of source code must retain the above copyright notice,
4743+ * this list of conditions and the following disclaimer.
4744+ *
4745+ * Redistributions in binary form must reproduce the above copyright
4746+ * notice, this list of conditions and the following disclaimer in the
4747+ * documentation and/or other materials provided with the distribution.
4748+ *
4749+ * Neither the name Intel Corporation nor the names of its contributors
4750+ * may be used to endorse or promote products derived from this software
4751+ * without specific prior written permission.
4752+ *
4753+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4754+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4755+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4756+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
4757+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4758+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4759+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
4760+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4761+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
4762+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4763+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4764+ *
4765+ */
4766+
4767+#ifndef _IEGD_DRM_H__
4768+#define _IEGD_DRM_H__
4769+
4770+#include "iegd_drm_client.h"
4771+
4772+/* INTEL specific ioctls
4773+ * The device specific ioctl range is 0x40 to 0x79.
4774+ */
4775+
4776+#define DRM_IOCTL_INTEL_GETPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4777+ DRM_INTEL_GETPAGES, drm_intel_getpages_t)
4778+#define DRM_IOCTL_INTEL_FREEPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4779+ DRM_INTEL_FREEPAGES, drm_intel_freepages_t)
4780+#define DRM_IOCTL_INTEL_INFO_INIT DRM_IOW( DRM_BASE_COMMAND + \
4781+ DRM_INTEL_INFO_INIT, intel_drm_info_t)
4782+#define DRM_IOCTL_INTEL_INFO_GET DRM_IOR( DRM_BASE_COMMAND + \
4783+ DRM_INTEL_INFO_GET, intel_drm_info_t)
4784+#define DRM_IOCTL_INTEL_INTERRUPT DRM_IOWR( DRM_BASE_COMMAND + \
4785+ DRM_INTEL_INTERRUPT, interrupt_info_t)
4786+
4787+/* New ioctl to set kernel params:
4788+ */
4789+typedef struct drm_intel_listpages {
4790+ int pid;
4791+ int size;
4792+ unsigned long phy_address;
4793+ unsigned long virt_address;
4794+ unsigned long offset;
4795+} drm_intel_listpages_t;
4796+
4797+typedef struct drm_intel_list{
4798+ struct list_head head;
4799+ drm_intel_listpages_t *page;
4800+}drm_intel_list_t;
4801+/*
4802+ * This is the basic information structure that is obtained from the
4803+ * IEGD XFree driver.
4804+ */
4805+typedef struct intel_device_private{
4806+ drm_intel_list_t *pagelist;
4807+ intel_drm_info_t *info_ptr;
4808+ spinlock_t irqmask_lock;
4809+ uint8_t *sgx_reg;
4810+ uint8_t *vdc_reg;
4811+ uint8_t *msvdx_reg;
4812+ uint32_t sgx_irq_mask;
4813+ uint32_t sgx_irq_mask2;
4814+ uint32_t vdc_irq_mask;
4815+ uint32_t msvdx_irq_mask;
4816+ /* interrupt status bits returned once woken up */
4817+ uint32_t interrupt_status;
4818+ int irq_enabled;
4819+ /* condition to wake up on */
4820+ unsigned int event_present;
4821+ wait_queue_head_t event_queue;
4822+ /* interrupts that have already occured */
4823+ unsigned int out_vdc;
4824+ unsigned int out_sgx;
4825+ unsigned int out_sgx2;
4826+ unsigned int out_mtx;
4827+} intel_device_private_t;
4828+
4829+#endif /* _INTEL_DRM_H_ */
4830+
4831diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drm_client.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drm_client.h
4832--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drm_client.h 1969-12-31 17:00:00.000000000 -0700
4833+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drm_client.h 2009-10-06 10:30:05.000000000 -0700
4834@@ -0,0 +1,139 @@
4835+/* -*- pse-c -*-
4836+ *----------------------------------------------------------------------------
4837+ * Filename: iegd_drm_client.h
4838+ * $Revision: 1.7 $
4839+ *----------------------------------------------------------------------------
4840+ * Gart and DRM driver for Intel Embedded Graphics Driver
4841+ * Copyright © 2008, Intel Corporation.
4842+ *
4843+ * This program is free software; you can redistribute it and/or modify it
4844+ * under the terms and conditions of the GNU General Public License,
4845+ * version 2, as published by the Free Software Foundation.
4846+ *
4847+ * This program is distributed in the hope it will be useful, but WITHOUT
4848+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4849+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4850+ * more details.
4851+ *
4852+ * You should have received a copy of the GNU General Public License along with
4853+ * this program; if not, write to the Free Software Foundation, Inc.,
4854+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4855+ *
4856+ */
4857+
4858+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
4859+ *
4860+ * Redistribution and use in source and binary forms, with or without
4861+ * modification, are permitted provided that the following conditions are met:
4862+ * Redistributions of source code must retain the above copyright notice,
4863+ * this list of conditions and the following disclaimer.
4864+ *
4865+ * Redistributions in binary form must reproduce the above copyright
4866+ * notice, this list of conditions and the following disclaimer in the
4867+ * documentation and/or other materials provided with the distribution.
4868+ *
4869+ * Neither the name Intel Corporation nor the names of its contributors
4870+ * may be used to endorse or promote products derived from this software
4871+ * without specific prior written permission.
4872+ *
4873+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4874+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
4875+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4876+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
4877+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
4878+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
4879+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
4880+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
4881+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
4882+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4883+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4884+ *
4885+ */
4886+
4887+#ifndef __IEGD_DRM_CLIENT_H__
4888+#define __IEGD_DRM_CLIENT_H__
4889+
4890+/* Requests made from client to drm */
4891+#define CLEAR_INT 1
4892+#define WAIT_INT 2
4893+#define READ_INT 3
4894+#define UNMASK_INT 4
4895+#define MASK_INT 5
4896+
4897+/* Responses returned to the client from drm */
4898+#define INT_INVALID -1
4899+#define INT_NOOP 0
4900+#define INT_CLEARED 1
4901+#define INT_HANDLED 2
4902+#define INT_READ 3
4903+#define INT_STORED 4
4904+#define INT_TIMEOUT 5
4905+
4906+typedef struct drm_intel_getpages {
4907+ int size;
4908+ unsigned long phy_address;
4909+ unsigned long virt_address;
4910+ unsigned long offset;
4911+} drm_intel_getpages_t;
4912+
4913+typedef struct drm_intel_freepages {
4914+ int size;
4915+ unsigned long phy_address;
4916+ unsigned long virt_address;
4917+ unsigned long offset;
4918+} drm_intel_freepages_t;
4919+
4920+/*
4921+ * This is the basic information structure that is is obtained from the
4922+ * IEGD drm driver.
4923+ */
4924+typedef struct _intel_drm_info {
4925+ unsigned long device_id;
4926+ unsigned long revision;
4927+ unsigned long video_memory_offset;
4928+ unsigned long video_memory_size;
4929+ unsigned long hw_status_offset;
4930+} intel_drm_info_t;
4931+
4932+typedef struct {
4933+ /* request status returned to client */
4934+ unsigned int req_status;
4935+ /* what type of request is being made to drm (clear/wait/read) */
4936+ unsigned int req_type;
4937+ /* which interrupts to clear or look for */
4938+ unsigned long in[8]; /* Array of device dependant mask/request bits */
4939+ /* interrupts that have already occured, returned to the client */
4940+ unsigned long out[8]; /* Array of device dependant status bits */
4941+} interrupt_info_t;
4942+
4943+#define DRM_IOCTL_BASE 'd'
4944+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
4945+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
4946+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
4947+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
4948+
4949+/* IOCTL numbers to be used along side drmCommand* in Xserver
4950+ * example taken from intel_dri.c:
4951+ * drmCommandWrite(iptr->drm_sub_fd
4952+ * , DRM_INTEL_INFO_INIT
4953+ * , &info,sizeof(intel_drm_info_t)
4954+ */
4955+
4956+#define DRM_BASE_COMMAND 0x40
4957+#define DRM_INTEL_GETPAGES 0x01
4958+#define DRM_INTEL_FREEPAGES 0x02
4959+#define DRM_INTEL_INFO_INIT 0x03
4960+#define DRM_INTEL_INFO_GET 0x04
4961+#define DRM_INTEL_INTERRUPT 0x05
4962+
4963+#define DRM_IOCTL_INTEL_GETPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4964+ DRM_INTEL_GETPAGES, drm_intel_getpages_t)
4965+#define DRM_IOCTL_INTEL_FREEPAGES DRM_IOWR(DRM_BASE_COMMAND + \
4966+ DRM_INTEL_FREEPAGES, drm_intel_freepages_t)
4967+#define DRM_IOCTL_INTEL_INFO_INIT DRM_IOW( DRM_BASE_COMMAND + \
4968+ DRM_INTEL_INFO_INIT, intel_drm_info_t)
4969+#define DRM_IOCTL_INTEL_INFO_GET DRM_IOR( DRM_BASE_COMMAND + \
4970+ DRM_INTEL_INFO_GET, intel_drm_info_t)
4971+#define DRM_IOCTL_INTEL_INTERRUPT DRM_IOWR( DRM_BASE_COMMAND + \
4972+ DRM_INTEL_INTERRUPT, interrupt_info_t)
4973+#endif
4974diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drv.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drv.c
4975--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drv.c 1969-12-31 17:00:00.000000000 -0700
4976+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drv.c 2009-10-06 10:30:05.000000000 -0700
4977@@ -0,0 +1,59 @@
4978+/* -*- pse-c -*-
4979+ *----------------------------------------------------------------------------
4980+ * Filename: iegd_drv.c
4981+ * $Revision: 1.5 $
4982+ *----------------------------------------------------------------------------
4983+ * Gart and DRM driver for Intel Embedded Graphics Driver
4984+ * Copyright © 2008, Intel Corporation.
4985+ *
4986+ * This program is free software; you can redistribute it and/or modify it
4987+ * under the terms and conditions of the GNU General Public License,
4988+ * version 2, as published by the Free Software Foundation.
4989+ *
4990+ * This program is distributed in the hope it will be useful, but WITHOUT
4991+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4992+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
4993+ * more details.
4994+ *
4995+ * You should have received a copy of the GNU General Public License along with
4996+ * this program; if not, write to the Free Software Foundation, Inc.,
4997+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
4998+ *
4999+ */
5000+
5001+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
5002+ *
5003+ * Redistribution and use in source and binary forms, with or without
5004+ * modification, are permitted provided that the following conditions are met:
5005+ * Redistributions of source code must retain the above copyright notice,
5006+ * this list of conditions and the following disclaimer.
5007+ *
5008+ * Redistributions in binary form must reproduce the above copyright
5009+ * notice, this list of conditions and the following disclaimer in the
5010+ * documentation and/or other materials provided with the distribution.
5011+ *
5012+ * Neither the name Intel Corporation nor the names of its contributors
5013+ * may be used to endorse or promote products derived from this software
5014+ * without specific prior written permission.
5015+ *
5016+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
5017+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
5018+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
5019+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
5020+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5021+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5022+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
5023+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
5024+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
5025+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
5026+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5027+ *
5028+ */
5029+
5030+#include <linux/config.h>
5031+#include "iegd.h"
5032+#include <drmP.h>
5033+#include <drm.h>
5034+#include "iegd_drm.h"
5035+#include "iegd_drv.h"
5036+
5037diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drv.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drv.h
5038--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_drv.h 1969-12-31 17:00:00.000000000 -0700
5039+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_drv.h 2009-10-06 10:30:05.000000000 -0700
5040@@ -0,0 +1,216 @@
5041+
5042+/* -*- pse-c -*-
5043+ *----------------------------------------------------------------------------
5044+ * Filename: iegd_drv.h
5045+ * $Revision: 1.15 $
5046+ *----------------------------------------------------------------------------
5047+ * Gart and DRM driver for Intel Embedded Graphics Driver
5048+ * Copyright © 2008, Intel Corporation.
5049+ *
5050+ * This program is free software; you can redistribute it and/or modify it
5051+ * under the terms and conditions of the GNU General Public License,
5052+ * version 2, as published by the Free Software Foundation.
5053+ *
5054+ * This program is distributed in the hope it will be useful, but WITHOUT
5055+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5056+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5057+ * more details.
5058+ *
5059+ * You should have received a copy of the GNU General Public License along with
5060+ * this program; if not, write to the Free Software Foundation, Inc.,
5061+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5062+ *
5063+ */
5064+
5065+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
5066+ *
5067+ * Redistribution and use in source and binary forms, with or without
5068+ * modification, are permitted provided that the following conditions are met:
5069+ * Redistributions of source code must retain the above copyright notice,
5070+ * this list of conditions and the following disclaimer.
5071+ *
5072+ * Redistributions in binary form must reproduce the above copyright
5073+ * notice, this list of conditions and the following disclaimer in the
5074+ * documentation and/or other materials provided with the distribution.
5075+ *
5076+ * Neither the name Intel Corporation nor the names of its contributors
5077+ * may be used to endorse or promote products derived from this software
5078+ * without specific prior written permission.
5079+ *
5080+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
5081+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
5082+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
5083+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
5084+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5085+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5086+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
5087+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
5088+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
5089+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
5090+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5091+ *
5092+ */
5093+
5094+#ifndef _IEGD_DRV_H_
5095+#define _IEGD_DRV_H_
5096+
5097+#define KB(x) ((x) * 1024)
5098+#define MB(x) (KB (KB (x)))
5099+#define GB(x) (MB (KB (x)))
5100+#include "iegd_drm.h"
5101+#include "igd_gart.h"
5102+
5103+/* Define the PCI IDs below */
5104+#define INTEL_PCI_IDS \
5105+ {0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5106+ {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5107+ {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5108+ {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5109+ {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5110+ {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5111+ {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5112+ {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5113+ {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5114+ {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5115+ {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5116+ {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5117+ {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5118+ {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5119+ {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5120+ {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5121+ {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5122+ {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5123+ {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5124+ {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5125+ {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5126+ {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5127+ {0x8086, 0x2e32, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
5128+ {0, 0, 0}
5129+
5130+/* Latest kernel remove this macro from drmP.h */
5131+#ifndef VM_OFFSET
5132+#define VM_OFFSET(vma) ((vma)->vm_pgoff << PAGE_SHIFT)
5133+#endif
5134+
5135+#ifndef DRMFILE
5136+#define DRMFILE struct file *
5137+#endif
5138+
5139+/*
5140+ * We check kernel version here because in kernel 2.6.23 onward some of the
5141+ * structure definition for the drm have been change. They have remove all the
5142+ * typedef for the drm data structure to follow kernel coding guidelines. This
5143+ * causing backward compatibility problem with IKM. Since only the typedef and
5144+ * the way they handling link list are changing, to create separate file just
5145+ * for handling this changes are redundant since implementation wise are
5146+ * still the same.
5147+ */
5148+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
5149+typedef struct drm_device drm_device_t;
5150+typedef struct drm_file drm_file_t;
5151+typedef struct drm_map drm_map_t;
5152+typedef struct drm_map_list drm_map_list_t;
5153+typedef struct drm_vma_entry drm_vma_entry_t;
5154+typedef struct drm_ioctl_desc drm_ioctl_desc_t;
5155+
5156+#define INSERT_VMA() \
5157+ mutex_lock(&dev->struct_mutex); \
5158+ vma_entry->vma = vma; \
5159+ vma_entry->pid = current->pid; \
5160+ list_add(&vma_entry->head, &dev->vmalist); \
5161+ mutex_unlock(&dev->struct_mutex);
5162+
5163+#define LIST_FOR_EACH(l, d) list_for_each((l), &(d)->maplist)
5164+
5165+#else
5166+
5167+#define INSERT_VMA() \
5168+ mutex_lock(&dev->struct_mutex); \
5169+ vma_entry->vma = vma; \
5170+ vma_entry->next = dev->vmalist; \
5171+ vma_entry->pid = current->pid; \
5172+ dev->vmalist = vma_entry; \
5173+ mutex_unlock(&dev->struct_mutex);
5174+
5175+#define LIST_FOR_EACH(l, d) list_for_each((l), &(d)->maplist->head)
5176+
5177+#endif /* #if LINUX_VERSION_CODE */
5178+
5179+/* Define the prototype and interfaces for functions for the different
5180+ * kernel version below.
5181+ */
5182+
5183+/* function definition in intel_interface.c */
5184+extern int intel_mmap_buffers(struct file *filp,struct vm_area_struct *vma);
5185+
5186+/* function definition to get pages this is in intel_interface*/
5187+extern int intel_getpages( drm_device_t *dev,struct file *filp, unsigned long arg );
5188+
5189+extern int intel_freepages(drm_device_t *dev , unsigned long arg );
5190+
5191+extern int intel_drm_info_init( drm_device_t *dev, unsigned long arg );
5192+
5193+extern int intel_drm_info_get( drm_device_t *dev, unsigned long arg );
5194+
5195+extern int intel_postinit(intel_device_private_t **priv);
5196+
5197+extern int intel_prerelease(drm_device_t *dev);
5198+
5199+/* Functions in intel_interface_265.c used in 2.6.5 kernel and below */
5200+
5201+extern int intel_postinit_265(drm_device_t *dev);
5202+
5203+extern int intel_prerelease_265(drm_device_t *dev);
5204+
5205+extern int intel_getpages_265( struct inode *inode, struct file *filp,
5206+ unsigned int cmd, unsigned long arg );
5207+
5208+extern int intel_freepages_265( struct inode *inode, struct file *filp,
5209+ unsigned int cmd, unsigned long arg );
5210+
5211+extern int intel_drm_info_init_265( struct inode *inode, struct file *filp,
5212+ unsigned int cmd, unsigned long arg );
5213+
5214+extern int intel_drm_info_get_265( struct inode *inode, struct file *filp,
5215+ unsigned int cmd, unsigned long arg );
5216+
5217+/* Functions in intel_interface_2611.c used in 2.6.11 kernel and above */
5218+
5219+extern int intel_postinit_2611(struct drm_device *dev,unsigned long flags);
5220+
5221+extern void intel_prerelease_2611(drm_device_t *dev,DRMFILE filp);
5222+
5223+extern int intel_getpages_2611( struct inode *inode, struct file *filp,
5224+ unsigned int cmd, unsigned long arg );
5225+
5226+extern int intel_freepages_2611( struct inode *inode, struct file *filp,
5227+ unsigned int cmd, unsigned long arg );
5228+
5229+extern int intel_drm_info_init_2611( struct inode *inode, struct file *filp,
5230+ unsigned int cmd, unsigned long arg );
5231+
5232+extern int intel_drm_info_get_2611( struct inode *inode, struct file *filp,
5233+ unsigned int cmd, unsigned long arg );
5234+
5235+extern unsigned long intel_alloc_pages(int order, int area);
5236+
5237+extern void intel_free_pages(unsigned long address, int order, int area);
5238+
5239+extern int drm_plb_mmap(struct file *, struct vm_area_struct *);
5240+
5241+extern struct vm_operations_struct iegd_plb_vm_ops_drm;
5242+extern gart_dispatch_t *gart_id;
5243+extern dev_private_data_t private_data;
5244+
5245+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
5246+extern void psb_irq_preinstall(struct drm_device *dev);
5247+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
5248+extern void psb_irq_postinstall(struct drm_device *dev);
5249+#else
5250+extern int psb_irq_postinstall(struct drm_device *dev);
5251+#endif
5252+extern void psb_irq_uninstall(struct drm_device *dev);
5253+extern int psb_init(intel_device_private_t *priv);
5254+int intel_drm_plb_interrupts( drm_device_t *dev, void *data );
5255+#endif
5256+
5257diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface.c
5258--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface.c 1969-12-31 17:00:00.000000000 -0700
5259+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface.c 2009-10-06 10:30:05.000000000 -0700
5260@@ -0,0 +1,888 @@
5261+/* -*- pse-c -*-
5262+ *----------------------------------------------------------------------------
5263+ * Filename: iegd_interface.c
5264+ * $Revision: 1.23 $
5265+ *----------------------------------------------------------------------------
5266+ * Gart and DRM driver for Intel Embedded Graphics Driver
5267+ * Copyright © 2008, Intel Corporation.
5268+ *
5269+ * This program is free software; you can redistribute it and/or modify it
5270+ * under the terms and conditions of the GNU General Public License,
5271+ * version 2, as published by the Free Software Foundation.
5272+ *
5273+ * This program is distributed in the hope it will be useful, but WITHOUT
5274+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
5275+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
5276+ * more details.
5277+ *
5278+ * You should have received a copy of the GNU General Public License along with
5279+ * this program; if not, write to the Free Software Foundation, Inc.,
5280+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
5281+ *
5282+ */
5283+
5284+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
5285+ *
5286+ * Redistribution and use in source and binary forms, with or without
5287+ * modification, are permitted provided that the following conditions are met:
5288+ * Redistributions of source code must retain the above copyright notice,
5289+ * this list of conditions and the following disclaimer.
5290+ *
5291+ * Redistributions in binary form must reproduce the above copyright
5292+ * notice, this list of conditions and the following disclaimer in the
5293+ * documentation and/or other materials provided with the distribution.
5294+ *
5295+ * Neither the name Intel Corporation nor the names of its contributors
5296+ * may be used to endorse or promote products derived from this software
5297+ * without specific prior written permission.
5298+ *
5299+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
5300+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
5301+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
5302+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
5303+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5304+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5305+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
5306+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
5307+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
5308+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
5309+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5310+ *
5311+ */
5312+
5313+#include "iegd.h"
5314+#include "igd_abs.h"
5315+#include "drmP.h"
5316+#include "drm.h"
5317+
5318+#include "iegd_drm.h"
5319+#include "iegd_drv.h"
5320+#include "psb_intregs.h"
5321+
5322+#ifndef MSR_IA32_CR_PAT
5323+#define MSR_IA32_CR_PAT 0x0277
5324+#endif
5325+#ifndef _PAGE_PAT
5326+#define _PAGE_PAT 0x080
5327+#endif
5328+
5329+extern void agp_init_pat(void);
5330+extern int agp_use_pat (void);
5331+
5332+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
5333+int drm_irq_install(drm_device_t *dev);
5334+#endif
5335+
5336+/* get intel_buffer_fops from the interface_###.c files */
5337+extern struct file_operations intel_buffer_fops;
5338+
5339+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
5340+extern struct vm_operations_struct iegd_plb_vm_ops;
5341+#endif
5342+
5343+
5344+/* Global variable to keep track the amount of memory we are using */
5345+static int memory;
5346+
5347+/* Our own mmap function to memory map physical to user space memory
5348+ */
5349+int intel_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
5350+{
5351+ DRM_DEBUG("\n");
5352+
5353+ lock_kernel();
5354+ vma->vm_flags |= (VM_IO | VM_RESERVED);
5355+ vma->vm_file = filp;
5356+ unlock_kernel();
5357+
5358+ DRM_DEBUG("VM_OFFSET(vma):%#x\n",(unsigned int)VM_OFFSET(vma));
5359+ if (REMAP_PAGE( vma,
5360+ vma->vm_start,
5361+ VM_OFFSET(vma),
5362+ (vma->vm_end - vma->vm_start),
5363+ pgprot_noncached(vma->vm_page_prot))){
5364+ return -EAGAIN;
5365+ }
5366+
5367+ return 0;
5368+}
5369+
5370+/* IOCTL to Allocate size pages and mmap it to the client calling it with
5371+ * corresponding virtual address
5372+ */
5373+int intel_getpages( drm_device_t *dev, struct file *filp, unsigned long arg ){
5374+
5375+ drm_intel_getpages_t getpages;
5376+ /* allocate some bytes */
5377+ unsigned long bytes;
5378+ int order;
5379+ int size;
5380+
5381+ unsigned long address;
5382+ unsigned long phy_address;
5383+ unsigned long offset;
5384+
5385+ struct page *pg;
5386+
5387+ unsigned long virtual;
5388+ struct file_operations *old_fops;
5389+
5390+ intel_device_private_t *dev_ptr=dev->dev_private;
5391+ drm_intel_listpages_t *page;
5392+ drm_intel_list_t *list;
5393+
5394+ DRM_DEBUG("\n");
5395+ /* copy user arguments */
5396+ if(copy_from_user(&getpages, (void __user *) arg, sizeof(getpages))){
5397+ return -EFAULT;
5398+ }
5399+
5400+ bytes=getpages.size;
5401+ /* Check to see if this allocation would exceed 16MEG in total memory
5402+ * This is to prevent denial of service attack. 16Meg should be enough.
5403+ */
5404+ if((memory+bytes)>MB(16) ){
5405+ /* We exceeded 16MEG. Bail out */
5406+ DRM_ERROR("Total memory allocated exceeded 16Meg!\n");
5407+ return -EFAULT;
5408+ }
5409+
5410+ /*number of pages that are needed*/
5411+ size=bytes>>PAGE_SHIFT;
5412+ if(bytes & ~(PAGE_SIZE*size)){
5413+ ++size;
5414+ }
5415+ order=ORDER(size);
5416+ DRM_DEBUG("Allocating bytes:%#lx,size:%d,order:%d\n",
5417+ (unsigned long)bytes,size,order);
5418+ /* allocate the pages */
5419+ /* returns kernel logical address.
5420+ * Is this the same as the kernel virtual address??
5421+ */
5422+ address=ALLOC_PAGES(order,0);
5423+ if(!address){
5424+ DRM_ERROR("Can't get pages\n");
5425+ return -EFAULT;
5426+ }
5427+ phy_address=__pa(address);
5428+
5429+ /* Find virtual address of the phys address */
5430+ pg=virt_to_page((void *)address);
5431+ offset=pg->index;
5432+ /* Find the number of bytes that is actually allocated */
5433+ size=PAGE_SIZE<<order;
5434+ DRM_DEBUG("Allocated address:%#lx,page offset:%#lx,phy_address:%#lx\n",
5435+ address,offset,phy_address);
5436+
5437+ /*do_mmap on the logical address and return virtual address */
5438+ down_write(&current->mm->mmap_sem);
5439+
5440+ old_fops= (struct file_operations *)filp->f_op;
5441+ filp->f_op=&intel_buffer_fops;
5442+
5443+ virtual=do_mmap(filp,0,size,PROT_READ|PROT_WRITE,MAP_SHARED,phy_address);
5444+
5445+ filp->f_op=old_fops;
5446+ up_write(&current->mm->mmap_sem);
5447+ DRM_DEBUG("Mmaped virtual:%#lx,address:%#lx\n",virtual,
5448+ (unsigned long)__va(phy_address));
5449+ if(virtual > -1024UL){
5450+ DRM_ERROR("mmap failed:%d\n",(int)virtual);
5451+ return -EFAULT;
5452+ }
5453+ getpages.phy_address=phy_address;
5454+ getpages.virt_address=virtual;
5455+ getpages.size=size;
5456+ getpages.offset=offset;
5457+
5458+ DRM_DEBUG("Mmap success requested size:%d (%d)\n",
5459+ getpages.size,(int)bytes);
5460+
5461+ /* alloc the page to be put into the linked list */
5462+ page=ALLOC(sizeof(*page),DRM_MEM_DRIVER);
5463+ if(!page){
5464+ DRM_DEBUG("Can't alloc list for page\n");
5465+ return -ENOMEM;
5466+ }
5467+
5468+ /*page->pid=current->pid;*/
5469+ page->pid=current->group_leader->pid;
5470+ page->size=size;
5471+ page->phy_address=phy_address;
5472+ page->virt_address=virtual;
5473+ page->offset=offset;
5474+
5475+ DRM_DEBUG("parent pid:%d,pid:%d,group_leader->pid:%d\n"
5476+ ,current->parent->pid,current->pid,current->group_leader->pid);
5477+ /* Alloc the list to be added then add it to the linked list */
5478+ list=ALLOC(sizeof(*list),DRM_MEM_DRIVER);
5479+ if(!list){
5480+ DRM_DEBUG("Can't alloc list for page\n");
5481+ FREE(page,sizeof(*page),0);
5482+ return -ENOMEM;
5483+ }
5484+ memset(list,0,sizeof(*list));
5485+ list->page=page;
5486+ LOCK_DRM(dev);
5487+ list_add(&list->head,&dev_ptr->pagelist->head);
5488+ UNLOCK_DRM(dev);
5489+ if(copy_to_user((void __user *) arg,&getpages,sizeof(getpages))){
5490+ return -EFAULT;
5491+ }
5492+ /* update the total amount of memory we use */
5493+ memory+=size;
5494+ DRM_DEBUG("memory has:%d bytes\n",memory);
5495+
5496+return 0;
5497+}
5498+
5499+/* IOCTL to free pages that are allocated by getpages
5500+ */
5501+int intel_freepages( drm_device_t *dev, unsigned long arg ){
5502+
5503+ drm_intel_freepages_t freepages;
5504+ /* allocate some bytes */
5505+ unsigned long bytes;
5506+ int order;
5507+ int size;
5508+
5509+ intel_device_private_t *dev_ptr=dev->dev_private;
5510+ drm_intel_listpages_t *page;
5511+ drm_intel_list_t *r_list=NULL;
5512+ struct list_head *pagelist;
5513+
5514+ DRM_DEBUG("Freeing pages\n");
5515+ /* copy user arguments */
5516+ if(copy_from_user(&freepages, (void __user *) arg, sizeof(freepages))){
5517+ return -EFAULT;
5518+ }
5519+
5520+ bytes=freepages.size;
5521+ /*number of pages that are needed*/
5522+ size=bytes>>PAGE_SHIFT;
5523+ if(bytes & ~(PAGE_SIZE*size)){
5524+ ++size;
5525+ }
5526+ order=ORDER(size);
5527+ DRM_DEBUG("bytes:%d,size:%d,order:%d,phy_address:%#lx\n",(int)bytes,(int)size,(int)order,freepages.phy_address);
5528+
5529+ /* free the pages */
5530+ DRM_DEBUG("freeing address:%#lx,size:%#lx\n",(unsigned long)__va(freepages.phy_address),(unsigned long)bytes);
5531+
5532+ DRM_DEBUG("parent pid:%d,pid:%d,group_leader->pid:%d\n"
5533+ ,current->parent->pid,current->pid,current->group_leader->pid);
5534+ /* See if the requested address is in our page list */
5535+ LOCK_DRM(dev);
5536+ pagelist=&dev_ptr->pagelist->head;
5537+ list_for_each(pagelist,&dev_ptr->pagelist->head){
5538+ r_list=list_entry(pagelist,drm_intel_list_t,head);
5539+ if((r_list->page->pid==current->group_leader->pid)
5540+ && (r_list->page->phy_address==freepages.phy_address)){
5541+
5542+ DRM_DEBUG("found pid:%d\n",current->group_leader->pid);
5543+ DRM_DEBUG("size:%d\n",r_list->page->size);
5544+ DRM_DEBUG("phy_address:%#lx\n",r_list->page->phy_address);
5545+ DRM_DEBUG("virt_add:%#lx\n",r_list->page->virt_address);
5546+ DRM_DEBUG("offset:%#lx\n",r_list->page->offset);
5547+
5548+ break;
5549+ }
5550+
5551+ }
5552+ if(pagelist==(&dev_ptr->pagelist->head)){
5553+ DRM_DEBUG("Can't find pages alloc for pid:%d\n",current->pid);
5554+ UNLOCK_DRM(dev);
5555+ return -EINVAL;
5556+ }
5557+
5558+ /* munmap the region 1st */
5559+ down_write(&current->mm->mmap_sem);
5560+ DRM_DEBUG("Unmapping virt_address:%#lx\n",freepages.virt_address);
5561+ do_munmap(current->mm,freepages.virt_address,bytes);
5562+ up_write(&current->mm->mmap_sem);
5563+
5564+ /* Free the pages! */
5565+ FREE_PAGES((unsigned long)__va(freepages.phy_address),order,0);
5566+
5567+ /* Free the page list */
5568+ page=r_list->page;
5569+ list_del(pagelist);
5570+ size=r_list->page->size;
5571+ FREE(pagelist,sizeof(*pagelist),0);
5572+ FREE(page,sizeof(*page),0);
5573+ UNLOCK_DRM(dev);
5574+
5575+ /* update the total memory that we use */
5576+ memory-=size;
5577+ DRM_DEBUG("memory has:%d bytes\n",memory);
5578+ return 0;
5579+}
5580+
5581+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
5582+/* This code is copied verbatim from the DRM module code in
5583+ * IKM/val/drm/drmv11p0/drm_irq.c. It's here because we
5584+ * need to activate interrupt handling, but for some reason the DRM module
5585+ * only exports the routine to disable interrupt handling drm_irq_uninstall(),
5586+ * and not the one to install.
5587+ *
5588+ * This could be problematic when new DRM versions appear.
5589+ *
5590+ * Fortunately, should a new DRM version appear, it should export
5591+ * drm_irq_install(), and then this source won't be needed at all; the
5592+ * code should compile cleanly with an external reference if this
5593+ * static version is removed completely.
5594+ */
5595+int drm_irq_install(drm_device_t * dev)
5596+{
5597+ int ret;
5598+ unsigned long sh_flags = 0;
5599+ int dev_irq = 0;
5600+
5601+ if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
5602+ return -EINVAL;
5603+
5604+ dev_irq = DRM_DEV_TO_IRQ(dev);
5605+ if (dev_irq == 0)
5606+ return -EINVAL;
5607+
5608+ mutex_lock(&dev->struct_mutex);
5609+
5610+ /* Driver must have been initialized */
5611+ if (!dev->dev_private) {
5612+ mutex_unlock(&dev->struct_mutex);
5613+ return -EINVAL;
5614+ }
5615+
5616+ if (dev->irq_enabled) {
5617+ mutex_unlock(&dev->struct_mutex);
5618+ return -EBUSY;
5619+ }
5620+ dev->irq_enabled = 1;
5621+ mutex_unlock(&dev->struct_mutex);
5622+
5623+ DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev_irq);
5624+
5625+ /*
5626+ if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) {
5627+ init_waitqueue_head(&dev->vbl_queue);
5628+
5629+ spin_lock_init(&dev->vbl_lock);
5630+
5631+ INIT_LIST_HEAD(&dev->vbl_sigs.head);
5632+ INIT_LIST_HEAD(&dev->vbl_sigs2.head);
5633+
5634+ dev->vbl_pending = 0;
5635+ }
5636+ */
5637+
5638+ /* Before installing handler */
5639+ dev->driver->irq_preinstall(dev);
5640+
5641+ /* Install handler */
5642+ if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
5643+ sh_flags = IRQF_SHARED;
5644+
5645+ ret = request_irq(dev_irq, dev->driver->irq_handler,
5646+ sh_flags, dev->devname, dev);
5647+ if (ret < 0) {
5648+ mutex_lock(&dev->struct_mutex);
5649+ dev->irq_enabled = 0;
5650+ mutex_unlock(&dev->struct_mutex);
5651+ return ret;
5652+ }
5653+
5654+ /* After installing handler */
5655+ dev->driver->irq_postinstall(dev);
5656+
5657+ return 0;
5658+}
5659+#endif
5660+
5661+/* IOCTL to init the info that is needed by the client
5662+ */
5663+int intel_drm_info_init( drm_device_t *dev, unsigned long arg ){
5664+
5665+ intel_drm_info_t info;
5666+ intel_drm_info_t *info_ptr;
5667+ intel_device_private_t *dev_ptr;
5668+
5669+ DRM_DEBUG("info init succesful dev_private:%#lx\n",(unsigned long)dev->dev_private);
5670+ dev_ptr=dev->dev_private;
5671+ /* See if dev_private is already allocated */
5672+ if(!dev->dev_private){
5673+ DRM_ERROR("dev_private not allocated!\n");
5674+ return 0;
5675+ }
5676+ info_ptr=dev_ptr->info_ptr;
5677+ /* See if info is already allocated */
5678+ if(info_ptr->device_id){
5679+ DRM_ERROR("Info already allocated!\n");
5680+ return 0;
5681+ }
5682+
5683+ /* copy user arguments */
5684+ if(copy_from_user(&info, (void __user *) arg, sizeof(info))){
5685+ return -EFAULT;
5686+ }
5687+
5688+ info_ptr->device_id=info.device_id;
5689+ info_ptr->revision=info.revision;
5690+ info_ptr->video_memory_offset=info.video_memory_offset;
5691+ info_ptr->video_memory_size=info.video_memory_size;
5692+ info_ptr->hw_status_offset=info.hw_status_offset;
5693+ DRM_DEBUG("device_id:%#lx,revision:%#lx,offset:%#lx,size:%#lx,hw_status_offset:%lx\n",
5694+ info_ptr->device_id,info_ptr->revision,
5695+ info_ptr->video_memory_offset,info_ptr->video_memory_size,
5696+ info_ptr->hw_status_offset);
5697+return 0;
5698+}
5699+/* IOCTL to get the info that is needed by the client
5700+ */
5701+int intel_drm_info_get( drm_device_t *dev, unsigned long arg ){
5702+
5703+ intel_drm_info_t info;
5704+ intel_device_private_t *dev_ptr=dev->dev_private;
5705+ intel_drm_info_t *info_ptr=dev_ptr->info_ptr;
5706+
5707+ DRM_DEBUG("Info get device_id:%#lx,revision:%#lx,offset:%#lx,size:%#lx, hw_status_offset:%lx\n",
5708+ info_ptr->device_id,info_ptr->revision,
5709+ info_ptr->video_memory_offset,info_ptr->video_memory_size,
5710+ info_ptr->hw_status_offset);
5711+
5712+ info.device_id=info_ptr->device_id;
5713+ info.revision=info_ptr->revision;
5714+ info.video_memory_offset=info_ptr->video_memory_offset;
5715+ info.video_memory_size=info_ptr->video_memory_size;
5716+ info.hw_status_offset=info_ptr->hw_status_offset;
5717+
5718+ if(copy_to_user((void __user *) arg,&info,sizeof(info))){
5719+ return -EFAULT;
5720+ }
5721+
5722+return 0;
5723+}
5724+
5725+/* initialise structure for link list and driver info in dev_private */
5726+int intel_postinit(intel_device_private_t **priv){
5727+
5728+ intel_drm_info_t *info_ptr;
5729+ intel_device_private_t *dev_ptr;
5730+ DRM_DEBUG("\n");
5731+ /* allocate info to be stored */
5732+ dev_ptr=ALLOC(sizeof(intel_device_private_t),DRM_MEM_DRIVER);
5733+
5734+ if(!dev_ptr){
5735+ return -ENOMEM;
5736+ }
5737+
5738+ DRM_DEBUG("dev_ptr allocation succesful\n");
5739+
5740+ memset(dev_ptr,0,sizeof(intel_device_private_t));
5741+ *priv=dev_ptr;
5742+
5743+ info_ptr=ALLOC(sizeof(intel_drm_info_t),DRM_MEM_DRIVER);
5744+
5745+ if(!info_ptr){
5746+ return -ENOMEM;
5747+ }
5748+
5749+ DRM_DEBUG("Info_ptr allocation succesful\n");
5750+ memset(info_ptr,0,sizeof(intel_drm_info_t));
5751+ dev_ptr->info_ptr=info_ptr;
5752+
5753+ dev_ptr->pagelist=ALLOC(sizeof(*dev_ptr->pagelist),DRM_MEM_DRIVER);
5754+
5755+ if(!dev_ptr->pagelist){
5756+ return -ENOMEM;
5757+ }
5758+
5759+ DRM_DEBUG("pagelist allocation succesful\n");
5760+ memset(dev_ptr->pagelist,0,sizeof(*dev_ptr->pagelist));
5761+ INIT_LIST_HEAD(&dev_ptr->pagelist->head);
5762+ /* Initialise global variable to zero when we start up */
5763+ memory=0;
5764+ DRM_DEBUG("Initialised memory:%d\n",memory);
5765+
5766+return 0;
5767+
5768+}
5769+/* check and free pages of client that is closing the fd */
5770+int intel_prerelease(drm_device_t *dev){
5771+ unsigned long bytes;
5772+ int order;
5773+ int size;
5774+
5775+ intel_device_private_t *dev_ptr=dev->dev_private;
5776+ drm_intel_listpages_t *page;
5777+ drm_intel_list_t *r_list=NULL;
5778+ struct list_head *pagelist, *pagelist_next;
5779+
5780+ DRM_DEBUG("Client closing freeing pages alloc to it\n");
5781+
5782+
5783+ /* Search for the page list has been added and free it */
5784+
5785+ LOCK_DRM(dev);
5786+
5787+ /* The changes to this function are copied form 8.1 */
5788+ /* I've no idea why, but sometimes during bootup the dev_private
5789+ * field can show up as NULL. Guarding against this for now...
5790+ */
5791+ if (dev_ptr != NULL) {
5792+
5793+ pagelist=&dev_ptr->pagelist->head;
5794+ list_for_each_safe(pagelist,pagelist_next,&dev_ptr->pagelist->head){
5795+ r_list=list_entry(pagelist,drm_intel_list_t,head);
5796+ if(r_list->page->pid==current->group_leader->pid){
5797+#if 0
5798+ printk("found pid:%d\n",current->pid);
5799+ printk("size:%d\n",r_list->page->size);
5800+ printk("phy_address:%#lx\n",r_list->page->phy_address);
5801+ printk("virt_add:%#lx\n",r_list->page->virt_address);
5802+ printk("offset:%#lx\n",r_list->page->offset);
5803+#endif
5804+ bytes=r_list->page->size;
5805+
5806+ /*number of pages that are needed*/
5807+
5808+ size=bytes>>PAGE_SHIFT;
5809+ if(bytes & ~(PAGE_SIZE*size)){
5810+ ++size;
5811+ }
5812+ order=ORDER(size);
5813+ /* free the pages */
5814+
5815+#if 0
5816+ printk("freeing address:%#lx,size:%#lx\n"
5817+ ,(unsigned long)__va(r_list->page->phy_address)
5818+ ,(unsigned long)bytes);
5819+#endif
5820+
5821+ FREE_PAGES((unsigned long)__va(r_list->page->phy_address)
5822+ ,order,0);
5823+
5824+ /* remove from list and free the resource */
5825+
5826+ page=r_list->page;
5827+ list_del(pagelist);
5828+ FREE(pagelist,sizeof(*pagelist),0);
5829+ FREE(page,sizeof(*page),0);
5830+ /* update the total memory that we use */
5831+ memory-=bytes;
5832+ DRM_DEBUG("memory:%d bytes\n",memory);
5833+ }
5834+ }
5835+ }
5836+
5837+ UNLOCK_DRM(dev);
5838+
5839+ return 0;
5840+
5841+}
5842+
5843+int drm_plb_mmap(struct file *filp, struct vm_area_struct *vma)
5844+{
5845+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
5846+ drm_file_t *priv = filp->private_data;
5847+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26))
5848+ drm_device_t *dev = priv->minor->dev;
5849+#else
5850+ drm_device_t *dev = priv->head->dev;
5851+#endif
5852+
5853+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
5854+ drm_local_map_t *map = NULL;
5855+#else
5856+ drm_map_t *map = NULL;
5857+#endif
5858+ drm_map_list_t *r_list;
5859+ unsigned long offset = 0;
5860+ struct list_head *list;
5861+ drm_vma_entry_t *vma_entry;
5862+
5863+ DRM_DEBUG("drm_plb_mmap: start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
5864+ vma->vm_start, vma->vm_end, VM_OFFSET(vma));
5865+
5866+ if (!priv->authenticated) {
5867+ DRM_DEBUG("Did not authenticate");
5868+ return -EACCES;
5869+ } else {
5870+ DRM_DEBUG("Authenticate successful");
5871+ }
5872+
5873+ /* A sequential search of a linked list is
5874+ * fine here because: 1) there will only be
5875+ * about 5-10 entries in the list and, 2) a
5876+ * DRI client only has to do this mapping
5877+ * once, so it doesn't have to be optimized
5878+ * for performance, even if the list was a
5879+ * bit longer. */
5880+
5881+ /* FIXME: Temporary fix. */
5882+ LIST_FOR_EACH(list, dev) {
5883+
5884+ r_list = list_entry(list, drm_map_list_t, head);
5885+ map = r_list->map;
5886+ if (!map)
5887+ continue;
5888+ if (r_list->user_token == VM_OFFSET(vma))
5889+ break;
5890+ }
5891+
5892+ if (!map || ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN)))
5893+ return -EPERM;
5894+
5895+ /* Check for valid size. */
5896+ if (map->size != vma->vm_end - vma->vm_start) {
5897+ return -EINVAL;
5898+ }
5899+
5900+ if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) {
5901+ vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE);
5902+ pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW;
5903+ }
5904+
5905+ switch (map->type) {
5906+
5907+ case _DRM_AGP:
5908+ case _DRM_FRAME_BUFFER:
5909+ if (agp_use_pat()) {
5910+ pgprot_val(vma->vm_page_prot) &= ~(_PAGE_PWT | _PAGE_PCD);
5911+ pgprot_val(vma->vm_page_prot) |= _PAGE_PAT;
5912+ vma->vm_flags |= VM_IO; /* not in core dump */
5913+
5914+ offset = VM_OFFSET(vma) - agp_bridge->gart_bus_addr;
5915+ vma->vm_ops = &iegd_plb_vm_ops;
5916+ break;
5917+ }
5918+
5919+ /* Fallthrough */
5920+ case _DRM_REGISTERS:
5921+ if (boot_cpu_data.x86 > 3 && map->type != _DRM_AGP) {
5922+ pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
5923+ pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT;
5924+ }
5925+ vma->vm_flags |= VM_IO; /* not in core dump */
5926+ offset = VM_OFFSET(vma) - agp_bridge->gart_bus_addr;
5927+
5928+ vma->vm_ops = &iegd_plb_vm_ops;
5929+ break;
5930+ case _DRM_SHM:
5931+ case _DRM_CONSISTENT:
5932+ case _DRM_SCATTER_GATHER:
5933+ DRM_DEBUG("Fall through to original mmap\n");
5934+ return drm_mmap(filp, vma);
5935+ break;
5936+ default:
5937+ return -EINVAL; /* This should never happen. */
5938+ }
5939+
5940+
5941+ vma->vm_flags |= VM_RESERVED; /* Don't swap */
5942+
5943+ vma->vm_file = filp; /* Needed for drm_vm_open() */
5944+
5945+ vma_entry = ALLOC(sizeof(*vma_entry), DRM_MEM_VMAS);
5946+ if (vma_entry) {
5947+ /*
5948+ * FIXME: Temporary fix. Will figure out later
5949+ */
5950+ INSERT_VMA();
5951+ }
5952+
5953+#endif
5954+ return 0;
5955+}
5956+
5957+int psb_init(intel_device_private_t *priv)
5958+{
5959+ DRM_INIT_WAITQUEUE(&priv->event_queue);
5960+ spin_lock_init(&priv->irqmask_lock);
5961+ priv->event_present = 0;
5962+ priv->out_vdc = 0;
5963+ priv->out_sgx = 0;
5964+ priv->out_sgx2 = 0;
5965+ priv->out_mtx = 0;
5966+
5967+ return 0;
5968+}
5969+
5970+int intel_drm_plb_interrupts( drm_device_t *dev, void *data )
5971+{
5972+ intel_device_private_t *priv;
5973+ interrupt_info_t plb_info;
5974+ unsigned long irqflags;
5975+ int ret = 0;
5976+ int rv;
5977+ priv=(intel_device_private_t *)dev->dev_private;
5978+
5979+ if(copy_from_user(&plb_info, (void __user *) data, sizeof(plb_info))) {
5980+ return -EFAULT;
5981+ }
5982+
5983+ /* USW15 definition of in and out
5984+ *
5985+ * in/out[0] VDC
5986+ * in/out[1] sgx
5987+ * in/out[2] sgx2
5988+ * in/out[3] msvdx
5989+ */
5990+
5991+ plb_info.out[0]=0;
5992+ plb_info.out[1]=0;
5993+ plb_info.out[2]=0;
5994+ plb_info.out[3]=0;
5995+
5996+ switch (plb_info.req_type) {
5997+ case CLEAR_INT:
5998+
5999+ plb_info.in[0] &= priv->vdc_irq_mask;
6000+ plb_info.in[1] &= priv->sgx_irq_mask;
6001+ plb_info.in[2] &= priv->sgx_irq_mask2;
6002+ plb_info.in[3] &= priv->msvdx_irq_mask;
6003+
6004+ if (plb_info.in[0] || plb_info.in[1] ||
6005+ plb_info.in[2] || plb_info.in[3]) {
6006+
6007+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
6008+ priv->out_vdc &= ~plb_info.in[0];
6009+ plb_info.out[0] = priv->out_vdc;
6010+
6011+ priv->out_sgx &= ~plb_info.in[1];
6012+ plb_info.out[1] = priv->out_sgx;
6013+
6014+ priv->out_sgx2 &= ~plb_info.in[2];
6015+ plb_info.out[2] = priv->out_sgx2;
6016+
6017+ priv->out_mtx &= ~plb_info.in[3];
6018+ plb_info.out[3] = priv->out_mtx;
6019+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
6020+
6021+ plb_info.req_status = INT_CLEARED;
6022+
6023+ } else {
6024+ plb_info.req_status = INT_NOOP;
6025+ }
6026+
6027+ break;
6028+
6029+ case READ_INT:
6030+
6031+
6032+ plb_info.out[0] = priv->out_vdc;
6033+ plb_info.out[1] = priv->out_sgx;
6034+ plb_info.out[2] = priv->out_sgx2;
6035+ plb_info.out[3] = priv->out_mtx;
6036+ plb_info.req_status = INT_READ;
6037+
6038+ break;
6039+
6040+ case WAIT_INT:
6041+
6042+ plb_info.in[0] &= priv->vdc_irq_mask;
6043+ plb_info.in[1] &= priv->sgx_irq_mask;
6044+ plb_info.in[2] &= priv->sgx_irq_mask2;
6045+ plb_info.in[3] &= priv->msvdx_irq_mask;
6046+
6047+ if (plb_info.in[0] || plb_info.in[1] ||
6048+ plb_info.in[2] || plb_info.in[3]) {
6049+
6050+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
6051+
6052+ /* none of the interrupts have ocurred */
6053+ if ((priv->out_vdc & plb_info.in[0]) ||
6054+ (priv->out_sgx & plb_info.in[1]) ||
6055+ (priv->out_sgx2 & plb_info.in[2]) ||
6056+ (priv->out_mtx & plb_info.in[3])) {
6057+
6058+ /* At least one of the interrupts has already occurred */
6059+ plb_info.req_status = INT_STORED;
6060+
6061+ } else {
6062+
6063+ /* Wait for an interrupt to occur */
6064+ priv->event_present = 0;
6065+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
6066+
6067+ DRM_WAIT_ON(ret, priv->event_queue, 20 * DRM_HZ,
6068+ priv->event_present);
6069+
6070+ if (ret) {
6071+ plb_info.req_status = INT_TIMEOUT;
6072+ break;
6073+ }
6074+
6075+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
6076+
6077+ plb_info.req_status = INT_HANDLED;
6078+
6079+ }
6080+
6081+ plb_info.out[0] = priv->out_vdc;
6082+ plb_info.out[1] = priv->out_sgx;
6083+ plb_info.out[2] = priv->out_sgx2;
6084+ plb_info.out[3] = priv->out_mtx;
6085+
6086+ /* Clear the outstanding interrupts that have just been
6087+ * retrieved
6088+ */
6089+ priv->out_vdc &= ~(plb_info.out[0] & plb_info.in[0]);
6090+ priv->out_sgx &= ~(plb_info.out[1] & plb_info.in[1]) ;
6091+ priv->out_sgx2 &= ~(plb_info.out[2] & plb_info.in[2]);
6092+ priv->out_mtx &= ~(plb_info.out[3] & plb_info.in[3]);
6093+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
6094+
6095+ } else {
6096+
6097+ /* Unsupported interrupt */
6098+ plb_info.req_status = INT_NOOP;
6099+
6100+ }
6101+
6102+ break;
6103+
6104+ case UNMASK_INT:
6105+
6106+ if (!dev->irq_enabled) {
6107+ rv = drm_irq_install(dev);
6108+ if (rv != 0) {
6109+ DRM_ERROR("%s: could not install IRQs: rv = %d\n", __FUNCTION__, rv);
6110+ return rv;
6111+ }
6112+ }
6113+
6114+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
6115+ PSB_WVDC32(0x00000000, IMR);
6116+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
6117+
6118+ break;
6119+
6120+ case MASK_INT:
6121+
6122+ if (dev->irq_enabled) {
6123+ rv = drm_irq_uninstall(dev);
6124+ if (rv != 0) {
6125+ DRM_ERROR("%s: could not uninstall IRQs: rv = %d\n", __FUNCTION__, rv);
6126+ return rv;
6127+ }
6128+ }
6129+
6130+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
6131+ PSB_WVDC32(0xFFFFFFFF, IMR);
6132+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
6133+
6134+ break;
6135+
6136+ default:
6137+
6138+ plb_info.req_status = INT_INVALID;
6139+
6140+ }
6141+
6142+
6143+ if (copy_to_user((void __user *) data, &plb_info, sizeof(plb_info))) {
6144+ return -EFAULT;
6145+ }
6146+
6147+ return 0;
6148+}
6149diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2611.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2611.c
6150--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2611.c 1969-12-31 17:00:00.000000000 -0700
6151+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2611.c 2009-10-06 10:30:05.000000000 -0700
6152@@ -0,0 +1,250 @@
6153+/* -*- pse-c -*-
6154+ *----------------------------------------------------------------------------
6155+ * Filename: iegd_interface_2611.c
6156+ * $Revision: 1.6 $
6157+ *----------------------------------------------------------------------------
6158+ * Gart and DRM driver for Intel Embedded Graphics Driver
6159+ * Copyright © 2008, Intel Corporation.
6160+ *
6161+ * This program is free software; you can redistribute it and/or modify it
6162+ * under the terms and conditions of the GNU General Public License,
6163+ * version 2, as published by the Free Software Foundation.
6164+ *
6165+ * This program is distributed in the hope it will be useful, but WITHOUT
6166+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6167+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6168+ * more details.
6169+ *
6170+ * You should have received a copy of the GNU General Public License along with
6171+ * this program; if not, write to the Free Software Foundation, Inc.,
6172+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6173+ *
6174+ */
6175+
6176+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
6177+ *
6178+ * Redistribution and use in source and binary forms, with or without
6179+ * modification, are permitted provided that the following conditions are met:
6180+ * Redistributions of source code must retain the above copyright notice,
6181+ * this list of conditions and the following disclaimer.
6182+ *
6183+ * Redistributions in binary form must reproduce the above copyright
6184+ * notice, this list of conditions and the following disclaimer in the
6185+ * documentation and/or other materials provided with the distribution.
6186+ *
6187+ * Neither the name Intel Corporation nor the names of its contributors
6188+ * may be used to endorse or promote products derived from this software
6189+ * without specific prior written permission.
6190+ *
6191+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
6192+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
6193+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6194+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
6195+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6196+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6197+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
6198+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
6199+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
6200+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6201+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6202+ *
6203+ */
6204+
6205+#include "iegd.h"
6206+#include "drmP.h"
6207+#include "drm.h"
6208+
6209+#include "iegd_drm.h"
6210+#include "iegd_drv.h"
6211+
6212+#if KERNEL2611
6213+int intel_postinit_2611(struct drm_device *dev,unsigned long flags){
6214+
6215+ intel_device_private_t *priv;
6216+ priv=(intel_device_private_t *)dev->dev_private;
6217+
6218+ intel_postinit(&priv);
6219+ dev->dev_private=priv;
6220+
6221+ return 0;
6222+
6223+}
6224+
6225+void intel_prerelease_2611(drm_device_t *dev,DRMFILE filp){
6226+
6227+ intel_prerelease(dev);
6228+
6229+}
6230+
6231+int intel_getpages_2611( struct inode *inode, struct file *filp,
6232+ unsigned int cmd, unsigned long arg ){
6233+
6234+ drm_file_t *priv=filp->private_data;
6235+ drm_device_t *dev=priv->head->dev;
6236+ return intel_getpages(dev,filp,arg);
6237+
6238+}
6239+
6240+int intel_freepages_2611( struct inode *inode, struct file *filp,
6241+ unsigned int cmd, unsigned long arg ){
6242+
6243+ drm_file_t *priv=filp->private_data;
6244+ drm_device_t *dev=priv->head->dev;
6245+ return intel_freepages(dev,arg);
6246+}
6247+
6248+int intel_drm_info_init_2611( struct inode *inode, struct file *filp,
6249+ unsigned int cmd, unsigned long arg ){
6250+
6251+ drm_file_t *priv=filp->private_data;
6252+ drm_device_t *dev=priv->head->dev;
6253+ return intel_drm_info_init(dev,arg);
6254+
6255+}
6256+
6257+int intel_drm_info_get_2611( struct inode *inode, struct file *filp,
6258+ unsigned int cmd, unsigned long arg ){
6259+
6260+ drm_file_t *priv=filp->private_data;
6261+ drm_device_t *dev=priv->head->dev;
6262+ return intel_drm_info_get(dev,arg);
6263+
6264+}
6265+
6266+/* Following 2 functions were taken from drm_memory.c
6267+ * For some reason they are not being exported to use
6268+ * by the other drm.
6269+ */
6270+
6271+/**
6272+ * Allocate pages.
6273+ *
6274+ * \param order size order.
6275+ * \param area memory area. (Not used.)
6276+ * \return page address on success, or zero on failure.
6277+ *
6278+ * Allocate and reserve free pages.
6279+ */
6280+unsigned long intel_alloc_pages(int order, int area)
6281+{
6282+ unsigned long address;
6283+ unsigned long bytes = PAGE_SIZE << order;
6284+ unsigned long addr;
6285+ unsigned int sz;
6286+
6287+ address = __get_free_pages(GFP_KERNEL, order);
6288+ if (!address)
6289+ return 0;
6290+
6291+ /* Zero */
6292+ memset((void *)address, 0, bytes);
6293+
6294+ /* Reserve */
6295+ for (addr = address, sz = bytes;
6296+ sz > 0;
6297+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
6298+ SetPageReserved(virt_to_page(addr));
6299+ }
6300+
6301+ return address;
6302+}
6303+
6304+/**
6305+ * Free pages.
6306+ *
6307+ * \param address address of the pages to free.
6308+ * \param order size order.
6309+ * \param area memory area. (Not used.)
6310+ *
6311+ * Unreserve and free pages allocated by alloc_pages().
6312+ */
6313+void intel_free_pages(unsigned long address, int order, int area)
6314+{
6315+ unsigned long bytes = PAGE_SIZE << order;
6316+ unsigned long addr;
6317+ unsigned int sz;
6318+
6319+ if (!address)
6320+ return;
6321+
6322+ /* Unreserve */
6323+ for (addr = address, sz = bytes;
6324+ sz > 0;
6325+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
6326+ ClearPageReserved(virt_to_page(addr));
6327+ }
6328+
6329+ free_pages(address, order);
6330+}
6331+
6332+drm_ioctl_desc_t intel_ioctls[]={
6333+ [DRM_IOCTL_NR(DRM_INTEL_GETPAGES)] = { intel_getpages_2611, 0,0 },
6334+ [DRM_IOCTL_NR(DRM_INTEL_FREEPAGES)] = { intel_freepages_2611, 0,0 },
6335+ [DRM_IOCTL_NR(DRM_INTEL_INFO_INIT)] = { intel_drm_info_init_2611, 0,0 },
6336+ [DRM_IOCTL_NR(DRM_INTEL_INFO_GET)] = { intel_drm_info_get_2611, 0,0 }
6337+};
6338+
6339+int intel_max_ioctl = DRM_ARRAY_SIZE(intel_ioctls);
6340+
6341+
6342+static int version( drm_version_t *version )
6343+{
6344+ int len;
6345+
6346+ version->version_major = DRIVER_MAJOR;
6347+ version->version_minor = DRIVER_MINOR;
6348+ version->version_patchlevel = DRIVER_PATCHLEVEL;
6349+ DRM_COPY( version->name, DRIVER_NAME );
6350+ DRM_COPY( version->date, DRIVER_DATE );
6351+ DRM_COPY( version->desc, DRIVER_DESC );
6352+ return 0;
6353+}
6354+
6355+static struct pci_device_id pciidlist[] = {
6356+ INTEL_PCI_IDS
6357+};
6358+
6359+static struct drm_driver driver = {
6360+ .driver_features = DRIVER_USE_AGP|DRIVER_REQUIRE_AGP|DRIVER_USE_MTRR,
6361+ .prerelease = intel_prerelease_2611,
6362+ .postinit =intel_postinit_2611,
6363+ .reclaim_buffers=drm_core_reclaim_buffers,
6364+ .get_map_ofs=drm_core_get_map_ofs,
6365+ .get_reg_ofs=drm_core_get_reg_ofs,
6366+ .version = version,
6367+ .ioctls = intel_ioctls,
6368+ .fops = {
6369+ .owner = THIS_MODULE,
6370+ .open = drm_open,
6371+ .release = drm_release,
6372+ .ioctl = drm_ioctl,
6373+ .mmap = drm_mmap,
6374+ .poll = drm_poll,
6375+ .fasync = drm_fasync,
6376+ },
6377+ .pci_driver = {
6378+ .name = DRIVER_NAME,
6379+ .id_table = pciidlist,
6380+ }
6381+};
6382+
6383+int __init intel_init(void)
6384+{
6385+ driver.num_ioctls = intel_max_ioctl;
6386+ return drm_init(&driver);
6387+}
6388+
6389+void __exit intel_exit(void)
6390+{
6391+ drm_exit(&driver);
6392+}
6393+
6394+struct file_operations intel_buffer_fops = {
6395+ .open = drm_open,
6396+ .flush = drm_flush,
6397+ .release = drm_release,
6398+ .ioctl = drm_ioctl,
6399+ .mmap = intel_mmap_buffers,
6400+ .fasync = drm_fasync,
6401+};
6402+#endif
6403diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2611.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2611.h
6404--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2611.h 1969-12-31 17:00:00.000000000 -0700
6405+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2611.h 2009-10-06 10:30:05.000000000 -0700
6406@@ -0,0 +1,71 @@
6407+/* -*- pse-c -*-
6408+ *----------------------------------------------------------------------------
6409+ * Filename: iegd_interface_2611.h
6410+ * $Revision: 1.6 $
6411+ *----------------------------------------------------------------------------
6412+ * Gart and DRM driver for Intel Embedded Graphics Driver
6413+ * Copyright © 2008, Intel Corporation.
6414+ *
6415+ * This program is free software; you can redistribute it and/or modify it
6416+ * under the terms and conditions of the GNU General Public License,
6417+ * version 2, as published by the Free Software Foundation.
6418+ *
6419+ * This program is distributed in the hope it will be useful, but WITHOUT
6420+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6421+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6422+ * more details.
6423+ *
6424+ * You should have received a copy of the GNU General Public License along with
6425+ * this program; if not, write to the Free Software Foundation, Inc.,
6426+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6427+ *
6428+ */
6429+
6430+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
6431+ *
6432+ * Redistribution and use in source and binary forms, with or without
6433+ * modification, are permitted provided that the following conditions are met:
6434+ * Redistributions of source code must retain the above copyright notice,
6435+ * this list of conditions and the following disclaimer.
6436+ *
6437+ * Redistributions in binary form must reproduce the above copyright
6438+ * notice, this list of conditions and the following disclaimer in the
6439+ * documentation and/or other materials provided with the distribution.
6440+ *
6441+ * Neither the name Intel Corporation nor the names of its contributors
6442+ * may be used to endorse or promote products derived from this software
6443+ * without specific prior written permission.
6444+ *
6445+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
6446+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
6447+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6448+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
6449+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6450+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6451+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
6452+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
6453+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
6454+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6455+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6456+ *
6457+ */
6458+
6459+/* Macros are defined here such that only kernel specific functions can be
6460+ * used.
6461+ */
6462+#if KERNEL2611
6463+#define REMAP_PAGE(a,b,c,d,e) io_remap_pfn_range(a,b, \
6464+ c >>PAGE_SHIFT, \
6465+ d,e)
6466+
6467+#define ORDER(a) drm_order(a)
6468+#define ALLOC_PAGES(a,b) intel_alloc_pages(a,b)
6469+#define ALLOC(a,b) drm_alloc(a,b)
6470+#define FREE(a,b,c) drm_free(a,b,c)
6471+#define FREE_PAGES(a,b,c) intel_free_pages(a,b,c)
6472+
6473+#define LOCK_DRM(d) down(&d->struct_sem)
6474+#define UNLOCK_DRM(d) up(&d->struct_sem)
6475+#endif
6476+
6477+/* endif for KERNEL2611 */
6478diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2615.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2615.c
6479--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2615.c 1969-12-31 17:00:00.000000000 -0700
6480+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2615.c 2009-10-06 10:30:05.000000000 -0700
6481@@ -0,0 +1,394 @@
6482+
6483+/* -*- pse-c -*-
6484+ *----------------------------------------------------------------------------
6485+ * Filename: iegd_interface_2615.c
6486+ * $Revision: 1.11 $
6487+ *----------------------------------------------------------------------------
6488+ * Gart and DRM driver for Intel Embedded Graphics Driver
6489+ * Copyright © 2008, Intel Corporation.
6490+ *
6491+ * This program is free software; you can redistribute it and/or modify it
6492+ * under the terms and conditions of the GNU General Public License,
6493+ * version 2, as published by the Free Software Foundation.
6494+ *
6495+ * This program is distributed in the hope it will be useful, but WITHOUT
6496+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6497+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6498+ * more details.
6499+ *
6500+ * You should have received a copy of the GNU General Public License along with
6501+ * this program; if not, write to the Free Software Foundation, Inc.,
6502+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6503+ *
6504+ */
6505+
6506+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
6507+ *
6508+ * Redistribution and use in source and binary forms, with or without
6509+ * modification, are permitted provided that the following conditions are met:
6510+ * Redistributions of source code must retain the above copyright notice,
6511+ * this list of conditions and the following disclaimer.
6512+ *
6513+ * Redistributions in binary form must reproduce the above copyright
6514+ * notice, this list of conditions and the following disclaimer in the
6515+ * documentation and/or other materials provided with the distribution.
6516+ *
6517+ * Neither the name Intel Corporation nor the names of its contributors
6518+ * may be used to endorse or promote products derived from this software
6519+ * without specific prior written permission.
6520+ *
6521+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
6522+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
6523+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6524+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
6525+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6526+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6527+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
6528+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
6529+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
6530+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6531+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6532+ *
6533+ */
6534+
6535+#include "iegd.h"
6536+#include "drmP.h"
6537+#include "drm.h"
6538+
6539+#include "iegd_drm.h"
6540+
6541+#include "iegd_drv.h"
6542+#include "psb_intregs.h"
6543+#include "intelpci.h"
6544+#include <linux/i2c.h>
6545+
6546+int drm_irq_install(drm_device_t *dev);
6547+
6548+#if KERNEL2615
6549+int intel_firstopen_2615(struct drm_device *dev)
6550+{
6551+
6552+ intel_device_private_t *priv;
6553+ priv=(intel_device_private_t *)dev->dev_private;
6554+
6555+ intel_postinit(&priv);
6556+ dev->dev_private=priv;
6557+
6558+ return 0;
6559+
6560+}
6561+
6562+
6563+int intel_psb_firstopen_2615(struct drm_device *dev)
6564+{
6565+
6566+ unsigned long resource_start;
6567+ intel_device_private_t *priv;
6568+ priv=(intel_device_private_t *)dev->dev_private;
6569+
6570+ intel_postinit(&priv);
6571+ psb_init(priv);
6572+ dev->dev_private=priv;
6573+
6574+
6575+ /*
6576+ * Map MMIO addresses so that the DRM can control interrupt support
6577+ */
6578+
6579+ resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
6580+
6581+ priv->vdc_reg = ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
6582+
6583+ if (!priv->vdc_reg) {
6584+ /* Normally we'd want to unload the driver on failure. But due
6585+ * to circular dependancies, we can only return failure.
6586+ */
6587+ /* psb_driver_unload(dev); */
6588+ return 1;
6589+ }
6590+
6591+ priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET, PSB_SGX_SIZE);
6592+ if (!priv->sgx_reg) {
6593+ /* Normally we'd want to unload the driver on failure. But due
6594+ * to circular dependancies, we can only return failure.
6595+ */
6596+ /* psb_driver_unload(dev); */
6597+ return 1;
6598+ }
6599+
6600+ priv->msvdx_reg = ioremap(resource_start + PSB_MSVDX_OFFSET, PSB_MSVDX_SIZE);
6601+ if (!priv->msvdx_reg) {
6602+ /* Normally we'd want to unload the driver on failure. But due
6603+ * to circular dependancies, we can only return failure.
6604+ */
6605+ /* psb_driver_unload(dev); */
6606+ return 1;
6607+ }
6608+
6609+ return 0;
6610+
6611+}
6612+
6613+void intel_preclose_2615(drm_device_t *dev,DRMFILE filp)
6614+{
6615+ intel_prerelease(dev);
6616+}
6617+
6618+
6619+int intel_getpages_2615( struct inode *inode, struct file *filp,
6620+ unsigned int cmd, unsigned long arg)
6621+{
6622+ drm_file_t *priv=filp->private_data;
6623+ drm_device_t *dev=priv->head->dev;
6624+ return intel_getpages(dev,filp,arg);
6625+}
6626+
6627+
6628+int intel_freepages_2615( struct inode *inode, struct file *filp,
6629+ unsigned int cmd, unsigned long arg )
6630+{
6631+
6632+ drm_file_t *priv=filp->private_data;
6633+ drm_device_t *dev=priv->head->dev;
6634+ return intel_freepages(dev,arg);
6635+}
6636+
6637+
6638+int intel_drm_info_init_2615( struct inode *inode, struct file *filp,
6639+ unsigned int cmd, unsigned long arg )
6640+{
6641+
6642+ drm_file_t *priv=filp->private_data;
6643+ drm_device_t *dev=priv->head->dev;
6644+ return intel_drm_info_init(dev,arg);
6645+
6646+}
6647+
6648+
6649+int intel_drm_info_get_2615( struct inode *inode, struct file *filp,
6650+ unsigned int cmd, unsigned long arg )
6651+{
6652+
6653+ drm_file_t *priv=filp->private_data;
6654+ drm_device_t *dev=priv->head->dev;
6655+ return intel_drm_info_get(dev,arg);
6656+
6657+}
6658+
6659+
6660+/* Following 2 functions were taken from drm_memory.c
6661+ * For some reason they are not being exported to use
6662+ * by the other drm.
6663+ */
6664+
6665+/**
6666+ * Allocate pages.
6667+ *
6668+ * \param order size order.
6669+ * \param area memory area. (Not used.)
6670+ * \return page address on success, or zero on failure.
6671+ *
6672+ * Allocate and reserve free pages.
6673+ */
6674+unsigned long intel_alloc_pages(int order, int area)
6675+{
6676+ unsigned long address;
6677+ unsigned long bytes = PAGE_SIZE << order;
6678+ unsigned long addr;
6679+ unsigned int sz;
6680+
6681+ address = __get_free_pages(GFP_KERNEL, order);
6682+ if (!address)
6683+ return 0;
6684+
6685+ /* Zero */
6686+ memset((void *)address, 0, bytes);
6687+
6688+ /* Reserve */
6689+ for (addr = address, sz = bytes;
6690+ sz > 0;
6691+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
6692+ SetPageReserved(virt_to_page(addr));
6693+ }
6694+
6695+ return address;
6696+}
6697+
6698+
6699+/**
6700+ * Free pages.
6701+ *
6702+ * \param address address of the pages to free.
6703+ * \param order size order.
6704+ * \param area memory area. (Not used.)
6705+ *
6706+ * Unreserve and free pages allocated by alloc_pages().
6707+ */
6708+void intel_free_pages(unsigned long address, int order, int area)
6709+{
6710+ unsigned long bytes = PAGE_SIZE << order;
6711+ unsigned long addr;
6712+ unsigned int sz;
6713+
6714+ if (!address) {
6715+ return;
6716+ }
6717+
6718+ /* Unreserve */
6719+ for (addr = address, sz = bytes;
6720+ sz > 0;
6721+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
6722+ ClearPageReserved(virt_to_page(addr));
6723+ }
6724+
6725+ free_pages(address, order);
6726+}
6727+
6728+static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
6729+{
6730+ intel_device_private_t *priv;
6731+
6732+ priv=(intel_device_private_t *)dev->dev_private;
6733+
6734+ return 0;
6735+}
6736+
6737+int intel_drm_plb_interrupts_2615 ( struct inode *inode,
6738+ struct file *filp,
6739+ unsigned int cmd, void *arg )
6740+{
6741+ drm_file_t *priv=filp->private_data;
6742+ drm_device_t *dev=priv->head->dev;
6743+
6744+ return intel_drm_plb_interrupts( dev, arg );
6745+}
6746+
6747+drm_ioctl_desc_t intel_ioctls[] = {
6748+ [DRM_IOCTL_NR(DRM_INTEL_GETPAGES)] = { intel_getpages_2615, 0},
6749+ [DRM_IOCTL_NR(DRM_INTEL_FREEPAGES)] = { intel_freepages_2615, 0},
6750+ [DRM_IOCTL_NR(DRM_INTEL_INFO_INIT)] = { intel_drm_info_init_2615, 0},
6751+ [DRM_IOCTL_NR(DRM_INTEL_INFO_GET)] = { intel_drm_info_get_2615, 0},
6752+ [DRM_IOCTL_NR(DRM_INTEL_INTERRUPT)] = {intel_drm_plb_interrupts_2615,0}
6753+};
6754+
6755+int intel_max_ioctl = DRM_ARRAY_SIZE(intel_ioctls);
6756+
6757+
6758+
6759+static struct pci_device_id pciidlist[] = {
6760+ INTEL_PCI_IDS
6761+};
6762+
6763+int device_is_agp_2615(drm_device_t * dev)
6764+{
6765+ return 1;
6766+}
6767+
6768+
6769+static struct drm_driver driver = {
6770+ .firstopen = intel_firstopen_2615,
6771+ .preclose = intel_preclose_2615,
6772+ .reclaim_buffers=drm_core_reclaim_buffers,
6773+ .get_map_ofs=drm_core_get_map_ofs,
6774+ .get_reg_ofs=drm_core_get_reg_ofs,
6775+
6776+ .device_is_agp = device_is_agp_2615,
6777+
6778+ .major = DRIVER_MAJOR,
6779+ .minor = DRIVER_MINOR,
6780+ .patchlevel = DRIVER_PATCHLEVEL,
6781+ .name = DRIVER_NAME,
6782+ .desc = DRIVER_DESC,
6783+ .date = DRIVER_DATE,
6784+
6785+ .driver_features = DRIVER_USE_AGP|DRIVER_REQUIRE_AGP|DRIVER_USE_MTRR,
6786+ .ioctls = intel_ioctls,
6787+ .fops = {
6788+ .owner = THIS_MODULE,
6789+ .open = drm_open,
6790+ .release = drm_release,
6791+ .ioctl = drm_ioctl,
6792+ .mmap = drm_mmap,
6793+ .poll = drm_poll,
6794+ .fasync = drm_fasync,
6795+ },
6796+ .pci_driver = {
6797+ .name = DRIVER_NAME,
6798+ .id_table = pciidlist,
6799+ }
6800+};
6801+
6802+static struct drm_driver driver_plb = {
6803+ .load = psb_driver_load,
6804+ .firstopen = intel_psb_firstopen_2615,
6805+ .preclose = intel_preclose_2615,
6806+ .reclaim_buffers=drm_core_reclaim_buffers,
6807+ .get_map_ofs=drm_core_get_map_ofs,
6808+ .get_reg_ofs=drm_core_get_reg_ofs,
6809+
6810+ .device_is_agp = device_is_agp_2615,
6811+
6812+ .major = DRIVER_MAJOR,
6813+ .minor = DRIVER_MINOR,
6814+ .patchlevel = DRIVER_PATCHLEVEL,
6815+ .name = DRIVER_NAME,
6816+ .desc = DRIVER_DESC,
6817+ .date = DRIVER_DATE,
6818+
6819+ .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
6820+ DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
6821+ .ioctls = intel_ioctls,
6822+ .irq_preinstall = psb_irq_preinstall,
6823+ .irq_postinstall = psb_irq_postinstall,
6824+ .irq_uninstall = psb_irq_uninstall,
6825+ .irq_handler = psb_irq_handler,
6826+
6827+ .fops = {
6828+ .owner = THIS_MODULE,
6829+ .open = drm_open,
6830+ .release = drm_release,
6831+ .ioctl = drm_ioctl,
6832+ .mmap = drm_plb_mmap,
6833+ .poll = drm_poll,
6834+ .fasync = drm_fasync,
6835+ },
6836+ .pci_driver = {
6837+ .name = DRIVER_NAME,
6838+ .id_table = pciidlist,
6839+ }
6840+};
6841+
6842+
6843+int intel_init(void)
6844+{
6845+ driver.num_ioctls = intel_max_ioctl;
6846+ driver_plb.num_ioctls = intel_max_ioctl;
6847+
6848+ /* We are peeking into the global AGP structures that
6849+ * we have access to in order to determine what chipset we're
6850+ * on. This isn't necessarily a good thing to do.
6851+ */
6852+
6853+ if (gart_id->device_id == PCI_DEVICE_ID_PLB) {
6854+ printk(KERN_ERR "Initializing DRM for Intel US15 SCH\n");
6855+ return drm_init(&driver_plb);
6856+ } else {
6857+ return drm_init(&driver);
6858+ }
6859+
6860+}
6861+
6862+void intel_exit(void)
6863+{
6864+ drm_exit(&driver);
6865+}
6866+
6867+struct file_operations intel_buffer_fops = {
6868+ .open = drm_open,
6869+ .release = drm_release,
6870+ .ioctl = drm_ioctl,
6871+ .mmap = intel_mmap_buffers,
6872+ .poll = drm_poll,
6873+ .fasync = drm_fasync,
6874+};
6875+#endif
6876diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2615.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2615.h
6877--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2615.h 1969-12-31 17:00:00.000000000 -0700
6878+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2615.h 2009-10-06 10:30:05.000000000 -0700
6879@@ -0,0 +1,72 @@
6880+
6881+/* -*- pse-c -*-
6882+ *----------------------------------------------------------------------------
6883+ * Filename: iegd_interface_2615.h
6884+ * $Revision: 1.6 $
6885+ *----------------------------------------------------------------------------
6886+ * Gart and DRM driver for Intel Embedded Graphics Driver
6887+ * Copyright © 2008, Intel Corporation.
6888+ *
6889+ * This program is free software; you can redistribute it and/or modify it
6890+ * under the terms and conditions of the GNU General Public License,
6891+ * version 2, as published by the Free Software Foundation.
6892+ *
6893+ * This program is distributed in the hope it will be useful, but WITHOUT
6894+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6895+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6896+ * more details.
6897+ *
6898+ * You should have received a copy of the GNU General Public License along with
6899+ * this program; if not, write to the Free Software Foundation, Inc.,
6900+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6901+ *
6902+ */
6903+
6904+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
6905+ *
6906+ * Redistribution and use in source and binary forms, with or without
6907+ * modification, are permitted provided that the following conditions are met:
6908+ * Redistributions of source code must retain the above copyright notice,
6909+ * this list of conditions and the following disclaimer.
6910+ *
6911+ * Redistributions in binary form must reproduce the above copyright
6912+ * notice, this list of conditions and the following disclaimer in the
6913+ * documentation and/or other materials provided with the distribution.
6914+ *
6915+ * Neither the name Intel Corporation nor the names of its contributors
6916+ * may be used to endorse or promote products derived from this software
6917+ * without specific prior written permission.
6918+ *
6919+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
6920+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
6921+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6922+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
6923+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6924+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
6925+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
6926+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
6927+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
6928+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6929+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6930+ *
6931+ */
6932+
6933+/* Macros are defined here such that only kernel specific functions can be
6934+ * used.
6935+ */
6936+#if KERNEL2615
6937+#define REMAP_PAGE(a,b,c,d,e) io_remap_pfn_range(a,b, \
6938+ c >>PAGE_SHIFT, \
6939+ d,e)
6940+
6941+#define ORDER(a) drm_order(a)
6942+#define ALLOC_PAGES(a,b) intel_alloc_pages(a,b)
6943+#define ALLOC(a,b) drm_alloc(a,b)
6944+#define FREE(a,b,c) drm_free(a,b,c)
6945+#define FREE_PAGES(a,b,c) intel_free_pages(a,b,c)
6946+
6947+#define LOCK_DRM(d) mutex_lock(&d->struct_mutex)
6948+#define UNLOCK_DRM(d) mutex_unlock(&d->struct_mutex)
6949+#endif
6950+
6951+/* endif for KERNEL2615 */
6952diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2624.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2624.c
6953--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2624.c 1969-12-31 17:00:00.000000000 -0700
6954+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2624.c 2009-10-06 10:30:05.000000000 -0700
6955@@ -0,0 +1,820 @@
6956+/* -*- pse-c -*-
6957+ *----------------------------------------------------------------------------
6958+ * Filename: iegd_interface_2611.c
6959+ * $Revision: 1.8 $
6960+ *----------------------------------------------------------------------------
6961+ * Gart and DRM driver for Intel Embedded Graphics Driver
6962+ * Copyright © 2008, Intel Corporation.
6963+ *
6964+ * This program is free software; you can redistribute it and/or modify it
6965+ * under the terms and conditions of the GNU General Public License,
6966+ * version 2, as published by the Free Software Foundation.
6967+ *
6968+ * This program is distributed in the hope it will be useful, but WITHOUT
6969+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6970+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
6971+ * more details.
6972+ *
6973+ * You should have received a copy of the GNU General Public License along with
6974+ * this program; if not, write to the Free Software Foundation, Inc.,
6975+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
6976+ *
6977+ */
6978+
6979+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
6980+ *
6981+ * Redistribution and use in source and binary forms, with or without
6982+ * modification, are permitted provided that the following conditions are met:
6983+ * Redistributions of source code must retain the above copyright notice,
6984+ * this list of conditions and the following disclaimer.
6985+ *
6986+ * Redistributions in binary form must reproduce the above copyright
6987+ * notice, this list of conditions and the following disclaimer in the
6988+ * documentation and/or other materials provided with the distribution.
6989+ *
6990+ * Neither the name Intel Corporation nor the names of its contributors
6991+ * may be used to endorse or promote products derived from this software
6992+ * without specific prior written permission.
6993+ *
6994+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
6995+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
6996+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6997+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
6998+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
6999+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
7000+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
7001+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
7002+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
7003+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
7004+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7005+ *
7006+ */
7007+
7008+#include "iegd.h"
7009+#include "drmP.h"
7010+#include "drm.h"
7011+
7012+#include "iegd_drm.h"
7013+#include "iegd_drv.h"
7014+#include "psb_intregs.h"
7015+#include "intelpci.h"
7016+
7017+int drm_irq_install(drm_device_t *dev);
7018+
7019+#if KERNEL2624
7020+
7021+/* get intel_buffer_fops from the interface_###.c files */
7022+extern struct file_operations intel_buffer_fops;
7023+
7024+/* Global variable to keep track the amount of memory we are using */
7025+static int memory = 0;
7026+
7027+int intel_firstopen_2624(struct drm_device *dev)
7028+{
7029+ intel_device_private_t *priv;
7030+ priv=(intel_device_private_t *)dev->dev_private;
7031+
7032+ intel_postinit(&priv);
7033+ dev->dev_private=priv;
7034+
7035+ return 0;
7036+
7037+}
7038+
7039+int intel_plb_firstopen_2624(struct drm_device *dev)
7040+{
7041+
7042+ unsigned long resource_start;
7043+ intel_device_private_t *priv;
7044+ priv=(intel_device_private_t *)dev->dev_private;
7045+
7046+ intel_postinit(&priv);
7047+ psb_init(priv);
7048+ dev->dev_private=priv;
7049+
7050+ /*
7051+ * Map MMIO addresses so that the DRM can control interrupt support
7052+ */
7053+
7054+ resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
7055+ priv->vdc_reg = ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
7056+ if (!priv->vdc_reg) {
7057+ /*
7058+ * Normally we'd want to unload the driver on failure. But due
7059+ * to circular dependancies, we can only return failure.
7060+ */
7061+ /* psb_driver_unload(dev); */
7062+ return 1;
7063+ }
7064+
7065+ priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET, PSB_SGX_SIZE);
7066+ if (!priv->sgx_reg) {
7067+ /*
7068+ * Normally we'd want to unload the driver on failure. But due
7069+ * to circular dependancies, we can only return failure.
7070+ */
7071+ /* psb_driver_unload(dev); */
7072+ return 1;
7073+ }
7074+
7075+ priv->msvdx_reg = ioremap(resource_start + PSB_MSVDX_OFFSET, PSB_MSVDX_SIZE);
7076+ if (!priv->msvdx_reg) {
7077+ /*
7078+ * Normally we'd want to unload the driver on failure. But due
7079+ * to circular dependancies, we can only return failure.
7080+ */
7081+ /* psb_driver_unload(dev); */
7082+ return 1;
7083+ }
7084+
7085+ return 0;
7086+
7087+}
7088+
7089+void intel_preclose_2624(drm_device_t *dev, struct drm_file *filp)
7090+{
7091+ intel_prerelease(dev);
7092+}
7093+
7094+/*
7095+ * Implement the 2.6.24 kernel interface for the device specific IOCTL
7096+ * that gets pages of memory from the DRM and returns them to the caller.
7097+ */
7098+int intel_getpages_2624(struct drm_device *dev,
7099+ void *data,
7100+ struct drm_file *filepriv)
7101+{
7102+ drm_intel_getpages_t *getpages;
7103+ unsigned long bytes;
7104+ int order;
7105+ int size;
7106+
7107+ unsigned long address;
7108+ unsigned long phy_address;
7109+ unsigned long offset;
7110+
7111+ struct page *pg;
7112+
7113+ unsigned long virtual;
7114+ struct file_operations *old_fops;
7115+
7116+ intel_device_private_t *dev_ptr = dev->dev_private;
7117+ drm_intel_listpages_t *page;
7118+ drm_intel_list_t *list;
7119+
7120+ DRM_DEBUG("\n");
7121+ DRM_INFO("in intel_getpages_2624, calling intel_getpages\n");
7122+ getpages = (drm_intel_getpages_t *)data;
7123+
7124+ bytes = getpages->size;
7125+
7126+ /*
7127+ * Check to see if this allocation would exceed 16MEG in total memory
7128+ * This is to prevent denial of service attack. 16Meg should be enough.
7129+ */
7130+ if((memory + bytes) > MB(16) ){
7131+ /* We exceeded 16MEG. Bail out */
7132+ DRM_ERROR("Total memory allocated exceeded 16Meg!\n");
7133+ DRM_INFO("Total memory allocated exceeded 16Meg!\n");
7134+ return -EFAULT;
7135+ }
7136+
7137+ /* number of pages that are needed */
7138+ size = bytes>>PAGE_SHIFT;
7139+ if(bytes & ~(PAGE_SIZE*size)){
7140+ ++size;
7141+ }
7142+ order = ORDER(size);
7143+ DRM_DEBUG("Allocating bytes:%#lx,size:%d,order:%d\n",
7144+ (unsigned long)bytes,size,order);
7145+
7146+ /*
7147+ * Allocate the pages.
7148+ * returns kernel logical address.
7149+ * Is this the same as the kernel virtual address??
7150+ */
7151+ address = ALLOC_PAGES(order,0);
7152+ if(!address){
7153+ DRM_ERROR("Can't get pages\n");
7154+ DRM_INFO("Can't get pages\n");
7155+ return -EFAULT;
7156+ }
7157+ phy_address = __pa(address);
7158+
7159+ /* Find virtual address of the phys address */
7160+ pg = virt_to_page((void *)address);
7161+ offset = pg->index;
7162+
7163+ /* Find the number of bytes that is actually allocated */
7164+ size = PAGE_SIZE<<order;
7165+ DRM_DEBUG("Allocated address:%#lx,page offset:%#lx,phy_address:%#lx\n",
7166+ address,offset,phy_address);
7167+
7168+ /*do_mmap on the logical address and return virtual address */
7169+ down_write(&current->mm->mmap_sem);
7170+
7171+ old_fops = (struct file_operations *) (filepriv->filp->f_op);
7172+ filepriv->filp->f_op = &intel_buffer_fops;
7173+
7174+ virtual = do_mmap(filepriv->filp, 0, size,
7175+ PROT_READ|PROT_WRITE,MAP_SHARED, phy_address);
7176+ filepriv->filp->f_op = old_fops;
7177+
7178+ up_write(&current->mm->mmap_sem);
7179+ DRM_DEBUG("Mmaped virtual:%#lx,address:%#lx\n",virtual,
7180+ (unsigned long)__va(phy_address));
7181+
7182+ if(virtual > -1024UL){
7183+ DRM_ERROR("mmap failed:%d\n",(int)virtual);
7184+ DRM_INFO("mmap failed:%d\n",(int)virtual);
7185+ return -EFAULT;
7186+ }
7187+
7188+ getpages->phy_address = phy_address;
7189+ getpages->virt_address = virtual;
7190+ getpages->size = size;
7191+ getpages->offset = offset;
7192+
7193+ DRM_DEBUG("Mmap success requested size:%d (%d)\n",
7194+ getpages->size,(int)bytes);
7195+
7196+ /* alloc the page to be put into the linked list */
7197+ page = ALLOC(sizeof(*page),DRM_MEM_DRIVER);
7198+ if(!page){
7199+ DRM_DEBUG("Can't alloc list for page\n");
7200+ DRM_INFO("Can't alloc list for page\n");
7201+ return -ENOMEM;
7202+ }
7203+
7204+ /*page->pid=current->pid;*/
7205+ page->pid = current->group_leader->pid;
7206+ page->size = size;
7207+ page->phy_address = phy_address;
7208+ page->virt_address = virtual;
7209+ page->offset = offset;
7210+
7211+ DRM_DEBUG("parent pid:%d,pid:%d,group_leader->pid:%d\n"
7212+ ,current->parent->pid,current->pid,current->group_leader->pid);
7213+
7214+ /* Alloc the list to be added then add it to the linked list */
7215+ list = ALLOC(sizeof(*list),DRM_MEM_DRIVER);
7216+ if(!list){
7217+ DRM_DEBUG("Can't alloc list for page\n");
7218+ DRM_INFO("Can't alloc list for page\n");
7219+ FREE(page,sizeof(*page),0);
7220+ return -ENOMEM;
7221+ }
7222+ memset(list,0,sizeof(*list));
7223+ list->page = page;
7224+ LOCK_DRM(dev);
7225+ list_add(&list->head,&dev_ptr->pagelist->head);
7226+ UNLOCK_DRM(dev);
7227+
7228+ /* update the total amount of memory we use */
7229+ memory += size;
7230+ DRM_DEBUG("memory has:%d bytes\n",memory);
7231+
7232+ DRM_INFO("intel_getpages Exit\n");
7233+ return 0;
7234+}
7235+
7236+
7237+/*
7238+ * Implement the 2.6.24 kernel interface for the device specific IOCTL
7239+ * that frees pages of memory that were previouslly allocated from the DRM.
7240+ */
7241+int intel_freepages_2624(struct drm_device *dev,
7242+ void *data,
7243+ struct drm_file *filepriv)
7244+{
7245+ drm_intel_freepages_t *freepages;
7246+ unsigned long bytes;
7247+ int order;
7248+ int size;
7249+
7250+ intel_device_private_t *dev_ptr=dev->dev_private;
7251+ drm_intel_listpages_t *page;
7252+ drm_intel_list_t *r_list=NULL;
7253+ struct list_head *pagelist;
7254+
7255+ DRM_DEBUG("Freeing pages\n");
7256+ freepages = (drm_intel_freepages_t *)data;
7257+
7258+ /* number of pages that are needed */
7259+ bytes = freepages->size;
7260+ size = bytes>>PAGE_SHIFT;
7261+ if(bytes & ~(PAGE_SIZE*size)){
7262+ ++size;
7263+ }
7264+ order = ORDER(size);
7265+ DRM_DEBUG("bytes:%d,size:%d,order:%d,phy_address:%#lx\n", (int)bytes,
7266+ (int)size,(int)order,freepages->phy_address);
7267+
7268+ /* free the pages */
7269+ DRM_DEBUG("freeing address:%#lx,size:%#lx\n",
7270+ (unsigned long)__va(freepages->phy_address),(unsigned long)bytes);
7271+
7272+ DRM_DEBUG("parent pid:%d,pid:%d,group_leader->pid:%d\n"
7273+ ,current->parent->pid,current->pid,current->group_leader->pid);
7274+
7275+ /* See if the requested address is in our page list */
7276+ LOCK_DRM(dev);
7277+ pagelist = &dev_ptr->pagelist->head;
7278+ list_for_each(pagelist, &dev_ptr->pagelist->head){
7279+ r_list=list_entry(pagelist, drm_intel_list_t, head);
7280+ if((r_list->page->pid==current->group_leader->pid)
7281+ && (r_list->page->phy_address==freepages->phy_address)){
7282+
7283+ DRM_DEBUG("found pid:%d\n",current->group_leader->pid);
7284+ DRM_DEBUG("size:%d\n",r_list->page->size);
7285+ DRM_DEBUG("phy_address:%#lx\n",r_list->page->phy_address);
7286+ DRM_DEBUG("virt_add:%#lx\n",r_list->page->virt_address);
7287+ DRM_DEBUG("offset:%#lx\n",r_list->page->offset);
7288+
7289+ break;
7290+ }
7291+
7292+ }
7293+
7294+ if(pagelist == (&dev_ptr->pagelist->head)){
7295+ DRM_DEBUG("Can't find pages alloc for pid:%d\n",current->pid);
7296+ UNLOCK_DRM(dev);
7297+ return -EINVAL;
7298+ }
7299+
7300+ /* munmap the region 1st */
7301+ down_write(&current->mm->mmap_sem);
7302+ DRM_DEBUG("Unmapping virt_address:%#lx\n",freepages->virt_address);
7303+ do_munmap(current->mm,freepages->virt_address,bytes);
7304+ up_write(&current->mm->mmap_sem);
7305+
7306+ /* Free the pages! */
7307+ FREE_PAGES((unsigned long)__va(freepages->phy_address), order, 0);
7308+
7309+ /* Free the page list */
7310+ page = r_list->page;
7311+ list_del(pagelist);
7312+ size = r_list->page->size;
7313+ FREE(pagelist,sizeof(*pagelist),0);
7314+ FREE(page,sizeof(*page),0);
7315+ UNLOCK_DRM(dev);
7316+
7317+ /* update the total memory that we use */
7318+ memory -= size;
7319+ DRM_DEBUG("memory has:%d bytes\n", memory);
7320+ return 0;
7321+}
7322+
7323+
7324+/*
7325+ * Implement the 2.6.24 kernel interface for the device specific IOCTL
7326+ * that stores client specific information.
7327+ */
7328+int intel_drm_info_init_2624(struct drm_device *dev,
7329+ void *data,
7330+ struct drm_file *filepriv)
7331+{
7332+ intel_drm_info_t *info;
7333+ intel_drm_info_t *info_ptr;
7334+ intel_device_private_t *dev_ptr;
7335+
7336+ if (dev == NULL) {
7337+ DRM_INFO("ERROR ERROR, drm device is NULL\n");
7338+ return -EFAULT;
7339+ }
7340+ DRM_DEBUG("info init succesful dev_private:%#lx\n",
7341+ (unsigned long)dev->dev_private);
7342+ dev_ptr = dev->dev_private;
7343+
7344+ /* See if dev_private is already allocated */
7345+ if(!dev->dev_private){
7346+ DRM_ERROR("dev_private not allocated!\n");
7347+ return 0;
7348+ }
7349+ info_ptr = dev_ptr->info_ptr;
7350+
7351+ /* See if info is already allocated */
7352+ if(info_ptr->device_id){
7353+ DRM_DEBUG("Info already allocated: device id = 0x%lx\n",
7354+ info_ptr->device_id);
7355+ DRM_ERROR("Info already allocated!\n");
7356+ return 0;
7357+ }
7358+
7359+ info = (intel_drm_info_t *)data;
7360+
7361+ info_ptr->device_id = info->device_id;
7362+ info_ptr->revision = info->revision;
7363+ info_ptr->video_memory_offset = info->video_memory_offset;
7364+ info_ptr->video_memory_size = info->video_memory_size;
7365+ info_ptr->hw_status_offset = info->hw_status_offset;
7366+ DRM_DEBUG("Saving dev_id:%#lx rev:%#lx offset:%#lx size:%#lx, "
7367+ "hwst_offset:%lx\n",
7368+ info_ptr->device_id, info_ptr->revision,
7369+ info_ptr->video_memory_offset, info_ptr->video_memory_size,
7370+ info_ptr->hw_status_offset);
7371+
7372+ return 0;
7373+}
7374+
7375+
7376+/*
7377+ * Implement the 2.6.24 kernel interface for the device specific IOCTL
7378+ * that retrieves client specific information.
7379+ */
7380+int intel_drm_info_get_2624(struct drm_device *dev,
7381+ void *data,
7382+ struct drm_file *filepriv)
7383+{
7384+ intel_drm_info_t *info;
7385+ intel_device_private_t *dev_ptr = dev->dev_private;
7386+ intel_drm_info_t *info_ptr = dev_ptr->info_ptr;
7387+
7388+ DRM_DEBUG("Info get dev_id:%#lx rev:%#lx offset:%#lx size:%#lx "
7389+ "hwst_offset:%lx\n",
7390+ info_ptr->device_id,info_ptr->revision,
7391+ info_ptr->video_memory_offset,info_ptr->video_memory_size,
7392+ info_ptr->hw_status_offset);
7393+
7394+ info = (intel_drm_info_t *)data;
7395+
7396+ info->device_id = info_ptr->device_id;
7397+ info->revision = info_ptr->revision;
7398+ info->video_memory_offset = info_ptr->video_memory_offset;
7399+ info->video_memory_size = info_ptr->video_memory_size;
7400+ info->hw_status_offset = info_ptr->hw_status_offset;
7401+
7402+ return 0;
7403+}
7404+
7405+/*
7406+ * The following 2 functions were taken from drm_memory.c
7407+ * For some reason they are not being exported to use by the other drm.
7408+ */
7409+
7410+/**
7411+ * Allocate pages.
7412+ *
7413+ * \param order size order.
7414+ * \param area memory area. (Not used.)
7415+ * \return page address on success, or zero on failure.
7416+ *
7417+ * Allocate and reserve free pages.
7418+ */
7419+unsigned long intel_alloc_pages(int order, int area)
7420+{
7421+ unsigned long address;
7422+ unsigned long bytes = PAGE_SIZE << order;
7423+ unsigned long addr;
7424+ unsigned int sz;
7425+
7426+ address = __get_free_pages(GFP_KERNEL, order);
7427+ if (!address)
7428+ return 0;
7429+
7430+ /* Zero */
7431+ memset((void *)address, 0, bytes);
7432+
7433+ /* Reserve */
7434+ for (addr = address, sz = bytes;
7435+ sz > 0;
7436+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
7437+ SetPageReserved(virt_to_page(addr));
7438+ }
7439+
7440+ return address;
7441+}
7442+
7443+/**
7444+ * Free pages.
7445+ *
7446+ * \param address address of the pages to free.
7447+ * \param order size order.
7448+ * \param area memory area. (Not used.)
7449+ *
7450+ * Unreserve and free pages allocated by alloc_pages().
7451+ */
7452+void intel_free_pages(unsigned long address, int order, int area)
7453+{
7454+ unsigned long bytes = PAGE_SIZE << order;
7455+ unsigned long addr;
7456+ unsigned int sz;
7457+
7458+ if (!address) {
7459+ return;
7460+ }
7461+
7462+ /* Unreserve */
7463+ for (addr = address, sz = bytes; sz > 0;
7464+ addr += PAGE_SIZE, sz -= PAGE_SIZE) {
7465+ ClearPageReserved(virt_to_page(addr));
7466+ }
7467+
7468+ free_pages(address, order);
7469+}
7470+
7471+static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
7472+{
7473+ intel_device_private_t *priv;
7474+
7475+ priv=(intel_device_private_t *)dev->dev_private;
7476+
7477+ return 0;
7478+}
7479+
7480+int intel_drm_plb_interrupts_2624 (struct drm_device *dev,
7481+ void *data,
7482+ struct drm_file *filepriv)
7483+{
7484+ intel_device_private_t *priv = dev->dev_private;
7485+ interrupt_info_t *plb_info;
7486+ unsigned long irqflags;
7487+ int ret = 0;
7488+ int rv;
7489+
7490+ plb_info = (interrupt_info_t *)data;
7491+
7492+ /* USW15 definition of in and out
7493+ *
7494+ * in/out[0] VDC
7495+ * in/out[1] sgx
7496+ * in/out[2] sgx2
7497+ * in/out[3] msvdx
7498+ */
7499+
7500+ plb_info->out[0]=0;
7501+ plb_info->out[1]=0;
7502+ plb_info->out[2]=0;
7503+ plb_info->out[3]=0;
7504+
7505+ switch (plb_info->req_type) {
7506+ case CLEAR_INT:
7507+ plb_info->in[0] &= priv->vdc_irq_mask;
7508+ plb_info->in[1] &= priv->sgx_irq_mask;
7509+ plb_info->in[2] &= priv->sgx_irq_mask2;
7510+ plb_info->in[3] &= priv->msvdx_irq_mask;
7511+
7512+ if (plb_info->in[0] || plb_info->in[1] ||
7513+ plb_info->in[2] || plb_info->in[3]) {
7514+
7515+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
7516+ priv->out_vdc &= ~plb_info->in[0];
7517+ plb_info->out[0] = priv->out_vdc;
7518+
7519+ priv->out_sgx &= ~plb_info->in[1];
7520+ plb_info->out[1] = priv->out_sgx;
7521+
7522+ priv->out_sgx2 &= ~plb_info->in[2];
7523+ plb_info->out[2] = priv->out_sgx2;
7524+
7525+ priv->out_mtx &= ~plb_info->in[3];
7526+ plb_info->out[3] = priv->out_mtx;
7527+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
7528+
7529+ plb_info->req_status = INT_CLEARED;
7530+
7531+ } else {
7532+ plb_info->req_status = INT_NOOP;
7533+ }
7534+
7535+ break;
7536+
7537+ case READ_INT:
7538+ plb_info->out[0] = priv->out_vdc;
7539+ plb_info->out[1] = priv->out_sgx;
7540+ plb_info->out[2] = priv->out_sgx2;
7541+ plb_info->out[3] = priv->out_mtx;
7542+ plb_info->req_status = INT_READ;
7543+
7544+ break;
7545+
7546+ case WAIT_INT:
7547+ plb_info->in[0] &= priv->vdc_irq_mask;
7548+ plb_info->in[1] &= priv->sgx_irq_mask;
7549+ plb_info->in[2] &= priv->sgx_irq_mask2;
7550+ plb_info->in[3] &= priv->msvdx_irq_mask;
7551+
7552+ if (plb_info->in[0] || plb_info->in[1] ||
7553+ plb_info->in[2] || plb_info->in[3]) {
7554+
7555+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
7556+
7557+ /* none of the interrupts have ocurred */
7558+ if ((priv->out_vdc & plb_info->in[0]) ||
7559+ (priv->out_sgx & plb_info->in[1]) ||
7560+ (priv->out_sgx2 & plb_info->in[2]) ||
7561+ (priv->out_mtx & plb_info->in[3])) {
7562+
7563+ /* At least one of the interrupts has already occurred */
7564+ plb_info->req_status = INT_STORED;
7565+
7566+ } else {
7567+
7568+ /* Wait for an interrupt to occur */
7569+ priv->event_present = 0;
7570+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
7571+
7572+ DRM_WAIT_ON(ret, priv->event_queue, 20 * DRM_HZ,
7573+ priv->event_present);
7574+
7575+ if (ret) {
7576+ plb_info->req_status = INT_TIMEOUT;
7577+ break;
7578+ }
7579+
7580+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
7581+
7582+ plb_info->req_status = INT_HANDLED;
7583+
7584+ }
7585+ plb_info->out[0] = priv->out_vdc;
7586+ plb_info->out[1] = priv->out_sgx;
7587+ plb_info->out[2] = priv->out_sgx2;
7588+ plb_info->out[3] = priv->out_mtx;
7589+
7590+ /* Clear the outstanding interrupts that have just been
7591+ * retrieved
7592+ */
7593+ priv->out_vdc &= ~(plb_info->out[0] & plb_info->in[0]);
7594+ priv->out_sgx &= ~(plb_info->out[1] & plb_info->in[1]) ;
7595+ priv->out_sgx2 &= ~(plb_info->out[2] & plb_info->in[2]);
7596+ priv->out_mtx &= ~(plb_info->out[3] & plb_info->in[3]);
7597+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
7598+
7599+ } else {
7600+
7601+ /* Unsupported interrupt */
7602+ plb_info->req_status = INT_NOOP;
7603+
7604+ }
7605+
7606+ break;
7607+
7608+ case UNMASK_INT:
7609+
7610+ if (!dev->irq_enabled) {
7611+ rv = drm_irq_install(dev);
7612+ if (rv != 0) {
7613+ DRM_ERROR("%s: could not install IRQs: rv = %d\n", __FUNCTION__, rv);
7614+ return rv;
7615+ }
7616+ }
7617+
7618+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
7619+ PSB_WVDC32(0x00000000, IMR);
7620+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
7621+
7622+ break;
7623+
7624+ case MASK_INT:
7625+
7626+ if (dev->irq_enabled) {
7627+ rv = drm_irq_uninstall(dev);
7628+ if (rv != 0) {
7629+ DRM_ERROR("%s: could not uninstall IRQs: rv = %d\n", __FUNCTION__, rv);
7630+ return rv;
7631+ }
7632+ }
7633+
7634+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
7635+ PSB_WVDC32(0xFFFFFFFF, IMR);
7636+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
7637+
7638+ break;
7639+
7640+ default:
7641+
7642+ plb_info->req_status = INT_INVALID;
7643+ }
7644+
7645+ return 0;
7646+}
7647+
7648+
7649+drm_ioctl_desc_t intel_ioctls[] = {
7650+ DRM_IOCTL_DEF(DRM_INTEL_GETPAGES, intel_getpages_2624, 0),
7651+ DRM_IOCTL_DEF(DRM_INTEL_FREEPAGES, intel_freepages_2624, 0),
7652+ DRM_IOCTL_DEF(DRM_INTEL_INFO_INIT, intel_drm_info_init_2624, 0),
7653+ DRM_IOCTL_DEF(DRM_INTEL_INFO_GET, intel_drm_info_get_2624, 0),
7654+ DRM_IOCTL_DEF(DRM_INTEL_INTERRUPT, intel_drm_plb_interrupts_2624, 0)
7655+};
7656+
7657+int intel_max_ioctl = DRM_ARRAY_SIZE(intel_ioctls);
7658+
7659+
7660+
7661+static struct pci_device_id pciidlist[] = {
7662+ INTEL_PCI_IDS
7663+};
7664+
7665+int device_is_agp_2624(drm_device_t * dev)
7666+{
7667+ return 1;
7668+}
7669+
7670+static struct drm_driver driver = {
7671+ .firstopen = intel_firstopen_2624,
7672+ .preclose = intel_preclose_2624,
7673+ .reclaim_buffers=drm_core_reclaim_buffers,
7674+ .get_map_ofs=drm_core_get_map_ofs,
7675+ .get_reg_ofs=drm_core_get_reg_ofs,
7676+
7677+ .device_is_agp = device_is_agp_2624,
7678+
7679+ .major = DRIVER_MAJOR,
7680+ .minor = DRIVER_MINOR,
7681+ .patchlevel = DRIVER_PATCHLEVEL,
7682+ .name = DRIVER_NAME,
7683+ .desc = DRIVER_DESC,
7684+ .date = DRIVER_DATE,
7685+
7686+ .driver_features = DRIVER_USE_AGP|DRIVER_REQUIRE_AGP|DRIVER_USE_MTRR,
7687+ .ioctls = intel_ioctls,
7688+ .fops = {
7689+ .owner = THIS_MODULE,
7690+ .open = drm_open,
7691+ .release = drm_release,
7692+ .ioctl = drm_ioctl,
7693+ .mmap = drm_mmap,
7694+ .poll = drm_poll,
7695+ .fasync = drm_fasync,
7696+ },
7697+ .pci_driver = {
7698+ .name = DRIVER_NAME,
7699+ .id_table = pciidlist,
7700+ }
7701+};
7702+
7703+static struct drm_driver driver_plb = {
7704+ .load = psb_driver_load,
7705+ .firstopen = intel_plb_firstopen_2624,
7706+ .preclose = intel_preclose_2624,
7707+ .reclaim_buffers=drm_core_reclaim_buffers,
7708+ .get_map_ofs=drm_core_get_map_ofs,
7709+ .get_reg_ofs=drm_core_get_reg_ofs,
7710+
7711+ .device_is_agp = device_is_agp_2624,
7712+
7713+ .major = DRIVER_MAJOR,
7714+ .minor = DRIVER_MINOR,
7715+ .patchlevel = DRIVER_PATCHLEVEL,
7716+ .name = DRIVER_NAME,
7717+ .desc = DRIVER_DESC,
7718+ .date = DRIVER_DATE,
7719+
7720+ .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
7721+ DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_USE_MTRR,
7722+ .ioctls = intel_ioctls,
7723+ .irq_preinstall = psb_irq_preinstall,
7724+ .irq_postinstall = psb_irq_postinstall,
7725+ .irq_uninstall = psb_irq_uninstall,
7726+ .irq_handler = psb_irq_handler,
7727+
7728+ .fops = {
7729+ .owner = THIS_MODULE,
7730+ .open = drm_open,
7731+ .release = drm_release,
7732+ .ioctl = drm_ioctl,
7733+ .mmap = drm_plb_mmap,
7734+ .poll = drm_poll,
7735+ .fasync = drm_fasync,
7736+ },
7737+ .pci_driver = {
7738+ .name = DRIVER_NAME,
7739+ .id_table = pciidlist,
7740+ }
7741+};
7742+
7743+int intel_init(void)
7744+{
7745+ driver.num_ioctls = intel_max_ioctl;
7746+ driver_plb.num_ioctls = intel_max_ioctl;
7747+
7748+ /* We are peeking into the global AGP structures that
7749+ * we have access to in order to determine what chipset we're
7750+ * on. This isn't necessarily a good thing to do.
7751+ */
7752+
7753+ if (gart_id->device_id == PCI_DEVICE_ID_PLB) {
7754+ printk(KERN_ERR "Initializing DRM for Intel US15 SCH\n");
7755+ return drm_init(&driver_plb);
7756+ } else {
7757+ return drm_init(&driver);
7758+ }
7759+
7760+}
7761+
7762+void intel_exit(void)
7763+{
7764+ drm_exit(&driver);
7765+}
7766+
7767+struct file_operations intel_buffer_fops = {
7768+ .open = drm_open,
7769+ .release = drm_release,
7770+ .ioctl = drm_ioctl,
7771+ .mmap = intel_mmap_buffers,
7772+ .poll = drm_poll,
7773+ .fasync = drm_fasync,
7774+};
7775+#endif
7776diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2624.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2624.h
7777--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_2624.h 1969-12-31 17:00:00.000000000 -0700
7778+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_2624.h 2009-10-06 10:30:05.000000000 -0700
7779@@ -0,0 +1,78 @@
7780+/* -*- pse-c -*-
7781+ *----------------------------------------------------------------------------
7782+ * Filename: iegd_interface_2611.h
7783+ * $Revision: 1.5 $
7784+ *----------------------------------------------------------------------------
7785+ * Gart and DRM driver for Intel Embedded Graphics Driver
7786+ * Copyright © 2008, Intel Corporation.
7787+ *
7788+ * This program is free software; you can redistribute it and/or modify it
7789+ * under the terms and conditions of the GNU General Public License,
7790+ * version 2, as published by the Free Software Foundation.
7791+ *
7792+ * This program is distributed in the hope it will be useful, but WITHOUT
7793+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
7794+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7795+ * more details.
7796+ *
7797+ * You should have received a copy of the GNU General Public License along with
7798+ * this program; if not, write to the Free Software Foundation, Inc.,
7799+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
7800+ *
7801+ */
7802+
7803+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
7804+ *
7805+ * Redistribution and use in source and binary forms, with or without
7806+ * modification, are permitted provided that the following conditions are met:
7807+ * Redistributions of source code must retain the above copyright notice,
7808+ * this list of conditions and the following disclaimer.
7809+ *
7810+ * Redistributions in binary form must reproduce the above copyright
7811+ * notice, this list of conditions and the following disclaimer in the
7812+ * documentation and/or other materials provided with the distribution.
7813+ *
7814+ * Neither the name Intel Corporation nor the names of its contributors
7815+ * may be used to endorse or promote products derived from this software
7816+ * without specific prior written permission.
7817+ *
7818+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7819+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
7820+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
7821+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
7822+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
7823+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
7824+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
7825+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
7826+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
7827+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
7828+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7829+ *
7830+ */
7831+
7832+/* Macros are defined here such that only kernel specific functions can be
7833+ * used.
7834+ */
7835+#if KERNEL2624
7836+#define REMAP_PAGE(a,b,c,d,e) io_remap_pfn_range(a,b, \
7837+ c >>PAGE_SHIFT, \
7838+ d,e)
7839+
7840+#define ORDER(a) drm_order(a)
7841+#define ALLOC_PAGES(a,b) intel_alloc_pages(a,b)
7842+
7843+//kernel version 31 removed some wrapper functions
7844+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
7845+#define ALLOC(a, b) kmalloc(a, GFP_KERNEL)
7846+#define FREE(a,b,c) kfree(a)
7847+#else
7848+#define ALLOC(a,b) drm_alloc(a,b)
7849+#define FREE(a,b,c) drm_free(a,b,c)
7850+#endif
7851+
7852+#define FREE_PAGES(a,b,c) intel_free_pages(a,b,c)
7853+#define LOCK_DRM(d) mutex_lock(&d->struct_mutex)
7854+#define UNLOCK_DRM(d) mutex_unlock(&d->struct_mutex)
7855+#endif
7856+
7857+/* endif for KERNEL2624 */
7858diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_265.c patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_265.c
7859--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_265.c 1969-12-31 17:00:00.000000000 -0700
7860+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_265.c 2009-10-06 10:30:05.000000000 -0700
7861@@ -0,0 +1,147 @@
7862+/* -*- pse-c -*-
7863+ *----------------------------------------------------------------------------
7864+ * Filename: iegd_interface_265.c
7865+ * $Revision: 1.6 $
7866+ *----------------------------------------------------------------------------
7867+ * Gart and DRM driver for Intel Embedded Graphics Driver
7868+ * Copyright © 2008, Intel Corporation.
7869+ *
7870+ * This program is free software; you can redistribute it and/or modify it
7871+ * under the terms and conditions of the GNU General Public License,
7872+ * version 2, as published by the Free Software Foundation.
7873+ *
7874+ * This program is distributed in the hope it will be useful, but WITHOUT
7875+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
7876+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7877+ * more details.
7878+ *
7879+ * You should have received a copy of the GNU General Public License along with
7880+ * this program; if not, write to the Free Software Foundation, Inc.,
7881+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
7882+ *
7883+ */
7884+
7885+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
7886+ *
7887+ * Redistribution and use in source and binary forms, with or without
7888+ * modification, are permitted provided that the following conditions are met:
7889+ * Redistributions of source code must retain the above copyright notice,
7890+ * this list of conditions and the following disclaimer.
7891+ *
7892+ * Redistributions in binary form must reproduce the above copyright
7893+ * notice, this list of conditions and the following disclaimer in the
7894+ * documentation and/or other materials provided with the distribution.
7895+ *
7896+ * Neither the name Intel Corporation nor the names of its contributors
7897+ * may be used to endorse or promote products derived from this software
7898+ * without specific prior written permission.
7899+ *
7900+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
7901+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
7902+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
7903+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
7904+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
7905+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
7906+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
7907+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
7908+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
7909+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
7910+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7911+ *
7912+ */
7913+
7914+#include "iegd.h"
7915+#include "drmP.h"
7916+#include "drm.h"
7917+
7918+#include "iegd_drm.h"
7919+#include "iegd_drv.h"
7920+
7921+#if KERNEL265
7922+#include "drm_agpsupport.h"
7923+#include "drm_auth.h"
7924+#include "drm_bufs.h"
7925+#include "drm_context.h"
7926+#include "drm_dma.h"
7927+#include "drm_drawable.h"
7928+#include "drm_drv.h"
7929+
7930+#include "drm_fops.h"
7931+#include "drm_init.h"
7932+#include "drm_ioctl.h"
7933+#include "drm_lock.h"
7934+#include "drm_memory.h"
7935+#include "drm_proc.h"
7936+#include "drm_vm.h"
7937+#include "drm_stub.h"
7938+
7939+int intel_postinit_265(drm_device_t *dev){
7940+
7941+ intel_device_private_t *priv;
7942+ priv=(intel_device_private_t *)dev->dev_private;
7943+
7944+ intel_postinit(&priv);
7945+ dev->dev_private=priv;
7946+
7947+ return 0;
7948+
7949+}
7950+
7951+int intel_prerelease_265(drm_device_t *dev){
7952+
7953+ intel_prerelease(dev);
7954+
7955+ return 0;
7956+
7957+}
7958+
7959+int intel_getpages_265( struct inode *inode, struct file *filp,
7960+ unsigned int cmd, unsigned long arg ){
7961+
7962+ drm_file_t *priv=filp->private_data;
7963+ drm_device_t *dev=priv->dev;
7964+ return intel_getpages(dev,filp,arg);
7965+
7966+
7967+}
7968+
7969+int intel_freepages_265( struct inode *inode, struct file *filp,
7970+ unsigned int cmd, unsigned long arg ){
7971+
7972+ drm_file_t *priv=filp->private_data;
7973+ drm_device_t *dev=priv->dev;
7974+ return intel_freepages(dev,arg);
7975+
7976+}
7977+
7978+int intel_drm_info_init_265( struct inode *inode, struct file *filp,
7979+ unsigned int cmd, unsigned long arg ){
7980+
7981+ drm_file_t *priv=filp->private_data;
7982+ drm_device_t *dev=priv->dev;
7983+ return intel_drm_info_init(dev,arg);
7984+
7985+}
7986+
7987+int intel_drm_info_get_265( struct inode *inode, struct file *filp,
7988+ unsigned int cmd, unsigned long arg ){
7989+
7990+ drm_file_t *priv=filp->private_data;
7991+ drm_device_t *dev=priv->dev;
7992+ return intel_drm_info_get(dev,arg);
7993+
7994+}
7995+
7996+struct file_operations intel_buffer_fops = {
7997+ .open = DRM(open),
7998+ .flush = DRM(flush),
7999+ .release = DRM(release),
8000+ .ioctl = DRM(ioctl),
8001+ .mmap = intel_mmap_buffers,
8002+ .fasync = DRM(fasync),
8003+};
8004+
8005+#endif
8006+/*end of 2.6.5 definition */
8007+
8008+
8009diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_265.h patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_265.h
8010--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/iegd_interface_265.h 1969-12-31 17:00:00.000000000 -0700
8011+++ patch_script_temp/drivers/gpu/drm/iegd/drm/iegd_interface_265.h 2009-10-06 10:30:05.000000000 -0700
8012@@ -0,0 +1,129 @@
8013+/* -*- pse-c -*-
8014+ *----------------------------------------------------------------------------
8015+ * Filename: iegd_interface_265.h
8016+ * $Revision: 1.6 $
8017+ *----------------------------------------------------------------------------
8018+ * Gart and DRM driver for Intel Embedded Graphics Driver
8019+ * Copyright © 2008, Intel Corporation.
8020+ *
8021+ * This program is free software; you can redistribute it and/or modify it
8022+ * under the terms and conditions of the GNU General Public License,
8023+ * version 2, as published by the Free Software Foundation.
8024+ *
8025+ * This program is distributed in the hope it will be useful, but WITHOUT
8026+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8027+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8028+ * more details.
8029+ *
8030+ * You should have received a copy of the GNU General Public License along with
8031+ * this program; if not, write to the Free Software Foundation, Inc.,
8032+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8033+ *
8034+ */
8035+
8036+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
8037+ *
8038+ * Redistribution and use in source and binary forms, with or without
8039+ * modification, are permitted provided that the following conditions are met:
8040+ * Redistributions of source code must retain the above copyright notice,
8041+ * this list of conditions and the following disclaimer.
8042+ *
8043+ * Redistributions in binary form must reproduce the above copyright
8044+ * notice, this list of conditions and the following disclaimer in the
8045+ * documentation and/or other materials provided with the distribution.
8046+ *
8047+ * Neither the name Intel Corporation nor the names of its contributors
8048+ * may be used to endorse or promote products derived from this software
8049+ * without specific prior written permission.
8050+ *
8051+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
8052+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
8053+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
8054+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
8055+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
8056+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
8057+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
8058+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
8059+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
8060+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
8061+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8062+ *
8063+ */
8064+
8065+/* For some arcane reasons this must be defined for 2.6.5 kernel in
8066+ * intel.h if not the drm won't compile properly.
8067+ */
8068+#if KERNEL265
8069+
8070+
8071+/* KERNEL265 defines these functions in the drm directory
8072+ * that got expanded when you #define DRM(x) intel_##x. This is very ugly and
8073+ * confusing. Luckily 2.6.11 don't have this. Can't do much here but follow
8074+ * the rules for it.
8075+ */
8076+#define DRM(x) intel_##x
8077+
8078+/* Changing the permission bits to 0,0 for testing. auth,root permission */
8079+#define DRIVER_IOCTLS \
8080+ [DRM_IOCTL_NR(DRM_IOCTL_INTEL_GETPAGES)] = { intel_getpages_265, 0, 0 }, \
8081+ [DRM_IOCTL_NR(DRM_IOCTL_INTEL_FREEPAGES)] = { intel_freepages_265, 0, 0 },\
8082+ [DRM_IOCTL_NR(DRM_IOCTL_INTEL_INFO_INIT)] = { intel_drm_info_init_265, 0, 0 },\
8083+ [DRM_IOCTL_NR(DRM_IOCTL_INTEL_INFO_GET)] = { intel_drm_info_get_265, 0, 0 }
8084+
8085+/* Driver customization:
8086+ */
8087+#define __HAVE_RELEASE 1
8088+#define DRIVER_PRERELEASE() do { \
8089+ intel_prerelease_265(dev); \
8090+} while (0)
8091+
8092+#define DRIVER_RELEASE() do { \
8093+} while (0)
8094+
8095+#define DRIVER_PRETAKEDOWN() do { \
8096+} while (0)
8097+
8098+#define DRIVER_POSTSETUP() do { \
8099+} while (0)
8100+
8101+#define DRIVER_POSTCLEANUP() do { \
8102+} while (0)
8103+
8104+#define DRIVER_POSTINIT() do { \
8105+ intel_postinit_265(dev); \
8106+} while (0)
8107+
8108+/*
8109+ * Explaination: For unknown reasons the DRM infrastructure has a lot
8110+ * of really horrid programming techniques to generate custom init
8111+ * code using header files (containing c code) and macros. Apparently
8112+ * this is to save a few nano seconds during init.
8113+ *
8114+ * This logic here is that if you define this magic macro you will use
8115+ * this code to count the number of devices you are supporting. We
8116+ * need to support 2 devices and we don't know the device IDs at startup
8117+ * and there is usually not 2 PCI devices anyway. So we just return 2
8118+ * and worry about it later.
8119+ *
8120+ * Note: DRM has issues with DIH so for now we'll live with one drm
8121+ *#define DRIVER_COUNT_CARDS() 2
8122+ */
8123+
8124+/* KERNEL265 defines these functions in the drm directory
8125+ * that got expanded when you #define DRM(x) intel_##x. This is very ugly and
8126+ * confusing. Luckily 2.6.11 don't have this
8127+ */
8128+#define REMAP_PAGE(a,b,c,d,e) remap_page_range( \
8129+ DRM_RPR_ARG(a) b , \
8130+ c,d,e)
8131+#define ORDER(a) DRM(order)(a)
8132+#define ALLOC_PAGES(a,b) DRM(alloc_pages)(a,b)
8133+#define ALLOC(a,b) DRM(alloc)(a,b)
8134+#define FREE(a,b,c) DRM(free)(a,b,c)
8135+#define FREE_PAGES(a,b,c) DRM(free_pages)(a,b,c)
8136+
8137+#define LOCK_DRM(d) down(&d->struct_sem)
8138+#define UNLOCK_DRM(d) up(&d->struct_sem)
8139+
8140+#endif
8141+/* endif for KERNEL265 */
8142diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/myclient.c patch_script_temp/drivers/gpu/drm/iegd/drm/myclient.c
8143--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/myclient.c 1969-12-31 17:00:00.000000000 -0700
8144+++ patch_script_temp/drivers/gpu/drm/iegd/drm/myclient.c 2009-10-06 10:30:05.000000000 -0700
8145@@ -0,0 +1,210 @@
8146+/* -*- pse-c -*-
8147+ *----------------------------------------------------------------------------
8148+ * Filename: myclient.c
8149+ * $Revision: 1.5 $
8150+ *----------------------------------------------------------------------------
8151+ * DRM test program
8152+ * Copyright © 2008, Intel Corporation.
8153+ *
8154+ * This program is free software; you can redistribute it and/or modify it
8155+ * under the terms and conditions of the GNU General Public License,
8156+ * version 2, as published by the Free Software Foundation.
8157+ *
8158+ * This program is distributed in the hope it will be useful, but WITHOUT
8159+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8160+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8161+ * more details.
8162+ *
8163+ * You should have received a copy of the GNU General Public License along with
8164+ * this program; if not, write to the Free Software Foundation, Inc.,
8165+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8166+ *
8167+ */
8168+
8169+/* Copyright 2003 - 2005 Intel Corporation. All Rights Reserved.
8170+ *
8171+ * Redistribution and use in source and binary forms, with or without
8172+ * modification, are permitted provided that the following conditions are met:
8173+ * Redistributions of source code must retain the above copyright notice,
8174+ * this list of conditions and the following disclaimer.
8175+ *
8176+ * Redistributions in binary form must reproduce the above copyright
8177+ * notice, this list of conditions and the following disclaimer in the
8178+ * documentation and/or other materials provided with the distribution.
8179+ *
8180+ * Neither the name Intel Corporation nor the names of its contributors
8181+ * may be used to endorse or promote products derived from this software
8182+ * without specific prior written permission.
8183+ *
8184+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
8185+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
8186+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
8187+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
8188+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
8189+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
8190+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
8191+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
8192+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
8193+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
8194+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8195+ *
8196+ */
8197+
8198+/*client to test the ioctl
8199+ * make sure you change the permission bits in intel.h to 0,0
8200+ * before you start using this
8201+ */
8202+
8203+#include "iegd.h"
8204+
8205+#include <fcntl.h>
8206+#include <unistd.h>
8207+#include <sys/ioctl.h>
8208+#include <stdlib.h>
8209+#include <stdio.h>
8210+
8211+#define DRM_IOCTL_BASE 'd'
8212+#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
8213+#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
8214+#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
8215+#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
8216+
8217+#include "intel_drm_client.h"
8218+
8219+#define DRM_IOCTL_INTEL_GETPAGES DRM_IOWR(DRM_BASE_COMMAND + \
8220+ DRM_INTEL_GETPAGES, drm_intel_getpages_t)
8221+#define DRM_IOCTL_INTEL_FREEPAGES DRM_IOWR(DRM_BASE_COMMAND + \
8222+ DRM_INTEL_FREEPAGES, drm_intel_freepages_t)
8223+#define DRM_IOCTL_INTEL_INFO_INIT DRM_IOW( DRM_BASE_COMMAND + \
8224+ DRM_INTEL_INFO_INIT, intel_drm_info_t)
8225+#define DRM_IOCTL_INTEL_INFO_GET DRM_IOR( DRM_BASE_COMMAND + \
8226+ DRM_INTEL_INFO_GET, intel_drm_info_t)
8227+
8228+
8229+#define PAGE_SIZE 4096
8230+int main()
8231+{
8232+int file_desc, ret_value;
8233+printf("ytay starting client\n");
8234+/* Open the drm */
8235+file_desc=open("/dev/dri/card0",O_RDWR);
8236+
8237+if(file_desc<0){
8238+/* probably Suse distro since the dev tree is different.
8239+ * try /dev/card0
8240+ */
8241+file_desc=open("/dev/card0",O_RDWR);
8242+
8243+}
8244+
8245+if(file_desc<0){
8246+
8247+printf("ytay can't open device file:%s\n",DRIVER_DESC);
8248+ exit(-1);
8249+}
8250+
8251+printf("ytay open device file:%d\n",file_desc);
8252+drm_intel_getpages_t getpages;
8253+/* set the number of bytes we want the drm to allocate */
8254+getpages.size=(PAGE_SIZE- 1000);
8255+
8256+ret_value=ioctl(file_desc,DRM_IOCTL_INTEL_GETPAGES,&getpages);
8257+if(ret_value<0){
8258+printf("ytay ioctl failed!\n");
8259+ exit(-1);
8260+}
8261+printf("ytay ioctl success\n");
8262+printf("ytay size%d,phy_address:%#x,virt_address:%#x,offset:%#x\n",getpages.size,getpages.phy_address,getpages.virt_address,getpages.offset);
8263+
8264+/* test for memory access */
8265+
8266+int i;
8267+unsigned long *virt_ptr;
8268+
8269+virt_ptr=(unsigned long *)getpages.virt_address;
8270+
8271+/* input 0..10 into subsequent memory */
8272+
8273+for(i=0;i<=11;i++){
8274+*virt_ptr=i;
8275+virt_ptr++;
8276+
8277+}
8278+
8279+/*read from subsequent memory */
8280+
8281+virt_ptr=(unsigned long *)getpages.virt_address;
8282+for(i=0;i<=15;i++){
8283+printf("virt_ptr@%#x,value:%d\n",virt_ptr,*virt_ptr);
8284+virt_ptr++;
8285+}
8286+/* set the number of bytes we want the drm to allocate */
8287+getpages.size=(PAGE_SIZE- 1000);
8288+
8289+ret_value=ioctl(file_desc,DRM_IOCTL_INTEL_GETPAGES,&getpages);
8290+if(ret_value<0){
8291+printf("ytay ioctl failed!\n");
8292+ exit(-1);
8293+}
8294+printf("ytay ioctl success\n");
8295+printf("ytay size%d,phy_address:%#x,virt_address:%#x,offset:%#x\n",getpages.size,getpages.phy_address,getpages.virt_address,getpages.offset);
8296+
8297+
8298+/* freeing memory */
8299+
8300+drm_intel_freepages_t freepages;
8301+freepages.size=getpages.size;
8302+freepages.phy_address=getpages.phy_address;
8303+freepages.virt_address=getpages.virt_address;
8304+printf("ytay freeing phy_address:%#x,size:%#x\n",freepages.phy_address,freepages.size);
8305+/*
8306+ioctl(file_desc,DRM_IOCTL_INTEL_FREEPAGES,&freepages);
8307+*/
8308+/* init the drm info structure in the drm and test its value */
8309+
8310+ intel_drm_info_t info;
8311+ intel_drm_info_t test_info;
8312+ info.device_id=0x456;
8313+ info.revision=333;
8314+ info.video_memory_offset=0x10245;
8315+ info.video_memory_size=987;
8316+ info.hw_status_offset=0x444;
8317+
8318+ printf("Testing init info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
8319+ info.device_id,info.revision,info.video_memory_offset,info.video_memory_size,info.hw_status_offset);
8320+
8321+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
8322+
8323+/* init the drm info structure in the drm and test its value */
8324+
8325+ info.device_id=0x123;
8326+ info.revision=456;
8327+ info.video_memory_offset=0x789;
8328+ info.video_memory_size=111;
8329+ info.hw_status_offset=0x555;
8330+
8331+ printf("Testing init 2nd info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
8332+ info.device_id,info.revision,info.video_memory_offset,info.video_memory_size,info.hw_status_offset);
8333+
8334+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
8335+
8336+ printf("Testing init 2nd info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
8337+ info.device_id,info.revision,info.video_memory_offset,info.video_memory_size,info.hw_status_offset);
8338+
8339+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_INIT,&info);
8340+
8341+
8342+
8343+ ioctl(file_desc,DRM_IOCTL_INTEL_INFO_GET,&test_info);
8344+
8345+ printf("Got init info device_id:%#x,revision:%d,offset:%#x,size:%d,hw_status_offset:%lx\n",
8346+ test_info.device_id,test_info.revision,test_info.video_memory_offset,test_info.video_memory_size,test_info.hw_status_offset);
8347+
8348+
8349+close(file_desc);
8350+/*
8351+sleep(100000000000);
8352+*/
8353+return 0;
8354+
8355+}
8356diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/psb_intregs.h patch_script_temp/drivers/gpu/drm/iegd/drm/psb_intregs.h
8357--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/psb_intregs.h 1969-12-31 17:00:00.000000000 -0700
8358+++ patch_script_temp/drivers/gpu/drm/iegd/drm/psb_intregs.h 2009-10-06 10:30:05.000000000 -0700
8359@@ -0,0 +1,114 @@
8360+/* -*- pse-c -*-
8361+ *-----------------------------------------------------------------------------
8362+ * Filename: psb_intregs.h
8363+ *-----------------------------------------------------------------------------
8364+ * INTEL CONFIDENTIAL
8365+ * Copyright (2002-2008) Intel Corporation All Rights Reserved.
8366+ * The source code contained or described herein and all documents related to
8367+ * the source code ("Material") are owned by Intel Corporation or its suppliers
8368+ * or licensors. Title to the Material remains with Intel Corporation or its
8369+ * suppliers and licensors. The Material contains trade secrets and proprietary
8370+ * and confidential information of Intel or its suppliers and licensors. The
8371+ * Material is protected by worldwide copyright and trade secret laws and
8372+ * treaty provisions. No part of the Material may be used, copied, reproduced,
8373+ * modified, published, uploaded, posted, transmitted, distributed, or
8374+ * disclosed in any way without Intel's prior express written permission.
8375+ *
8376+ * No license under any patent, copyright, trade secret or other intellectual
8377+ * property right is granted to or conferred upon you by disclosure or
8378+ * delivery of the Materials, either expressly, by implication, inducement,
8379+ * estoppel or otherwise. Any license under such intellectual property rights
8380+ * must be express and approved by Intel in writing.
8381+ *
8382+ *
8383+ *-----------------------------------------------------------------------------
8384+ * Description:
8385+ * This file contains the interrupt related register definition and
8386+ * macros for the PLB platform.
8387+ *-----------------------------------------------------------------------------
8388+ */
8389+
8390+#ifndef _REGS_H_
8391+#define _REGS_H_
8392+
8393+/*-----------------------------------------------------------------------------
8394+ * SGX, VDC, and MSVDX interrupt registers
8395+ ----------------------------------------------------------------------------*/
8396+//#define SGX_BASE 0x40000
8397+
8398+#define PSB_MMIO_RESOURCE 0
8399+
8400+#define PSB_VDC_OFFSET 0x00000000
8401+#define PSB_VDC_SIZE 0x000080000
8402+#define PSB_SGX_OFFSET 0x00040000
8403+#define PSB_SGX_SIZE 0x8000
8404+#define PSB_MSVDX_OFFSET 0x00050000
8405+#define PSB_MSVDX_SIZE 0x1000
8406+
8407+/* bits in PSB_CR_EVENT_STATUS */
8408+#define PSB_DPM_3D_MEM_FREE (1<<0)
8409+#define PSB_OUT_OF_MEM_MT (1<<1)
8410+#define PSB_OUT_OF_MEM_GBL (1<<2)
8411+#define PSB_REACHED_MEM_THRESH (1<<3)
8412+#define PSB_TA_TERMINATE (1<<12)
8413+#define PSB_TA_FINISHED (1<<13)
8414+#define PSB_PIXELBE_END_RENDER (1<<18)
8415+#define PSB_DPM_TA_MEM_FREE (1<<24)
8416+#define PSB_DPM_OUT_OF_MEM_ZLS (1<<25)
8417+#define PSB_TWOD_COMPLETE (1<<27)
8418+#define PSB_TA_DPM_FAULT (1<<28)
8419+
8420+#define PSB_BIF_REQ_FAULT (1<<4)
8421+#define PSB_TRIG_DL (1<<5)
8422+#define PSB_TRIG_3D (1<<6)
8423+#define PSB_TRIG_TA (1<<7)
8424+
8425+#define PSB_CR_EVENT_HOST_ENABLE2 0x0110
8426+#define PSB_CR_EVENT_HOST_CLEAR2 0x0114
8427+#define PSB_CR_EVENT_STATUS2 0x0118
8428+
8429+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
8430+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
8431+#define PSB_CR_EVENT_STATUS 0x012C
8432+
8433+#define PSB_MTX_EVENT_HOST_ENABLE 0x0610
8434+#define PSB_MTX_EVENT_CLEAR 0x060C
8435+#define PSB_MTX_EVENT_STATUS 0x0608
8436+
8437+/*-----------------------------------------------------------------------------
8438+ * Memory mapped I/O Registers Definitions
8439+ *---------------------------------------------------------------------------*/
8440+
8441+/*-----------------------------------------------------------------------------
8442+ * Instruction and Interrupt Control Registers (01000h - 02FFFh)
8443+ *---------------------------------------------------------------------------*/
8444+#define HWSTAM 0x02098 /* Hardware Status Mask */
8445+#define IER 0x020A0 /* Interrupt Enable */
8446+#define IIR 0x020A4 /* Interrupt Identity */
8447+#define IMR 0x020A8 /* Interrupt Mask */
8448+#define ISR 0x020AC /* Interrupt Status */
8449+
8450+#define PIPEA_STAT 0x70024 /* Pipe A Display Status */
8451+#define PIPEB_STAT 0x71024 /* Pipe B Display Status */
8452+
8453+#define VBLANK_CLEAR (1<<1)
8454+#define VSYNC_PIPEB_FLAG (1<<5)
8455+#define VSYNC_PIPEA_FLAG (1<<7)
8456+#define VBLANK_INTERRUPT_ENABLE (1<<17)
8457+#define IRQ_SGX_FLAG (1<<18)
8458+#define IRQ_MSVDX_FLAG (1<<19)
8459+
8460+#define PSB_WVDC32(_val, _offs) \
8461+ iowrite32(_val, priv->vdc_reg + (_offs))
8462+#define PSB_RVDC32(_offs) \
8463+ ioread32(priv->vdc_reg + (_offs))
8464+#define PSB_WSGX32(_val, _offs) \
8465+ iowrite32(_val, priv->sgx_reg + (_offs))
8466+#define PSB_RSGX32(_offs) \
8467+ ioread32(priv->sgx_reg + (_offs))
8468+#define PSB_WMSVDX32(_val, _offs) \
8469+ iowrite32(_val, priv->msvdx_reg + (_offs))
8470+#define PSB_RMSVDX32(_offs) \
8471+ ioread32(priv->msvdx_reg + (_offs))
8472+
8473+#endif /* _REGS_H_ */
8474diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/psb_irq.c patch_script_temp/drivers/gpu/drm/iegd/drm/psb_irq.c
8475--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/drm/psb_irq.c 1969-12-31 17:00:00.000000000 -0700
8476+++ patch_script_temp/drivers/gpu/drm/iegd/drm/psb_irq.c 2009-10-06 10:30:05.000000000 -0700
8477@@ -0,0 +1,185 @@
8478+/* -*- pse-c -*-
8479+ *-----------------------------------------------------------------------------
8480+ * Filename: psb_intregs.h
8481+ *-----------------------------------------------------------------------------
8482+ * INTEL CONFIDENTIAL
8483+ * Copyright (2002-2008) Intel Corporation All Rights Reserved.
8484+ * The source code contained or described herein and all documents related to
8485+ * the source code ("Material") are owned by Intel Corporation or its suppliers
8486+ * or licensors. Title to the Material remains with Intel Corporation or its
8487+ * suppliers and licensors. The Material contains trade secrets and proprietary
8488+ * and confidential information of Intel or its suppliers and licensors. The
8489+ * Material is protected by worldwide copyright and trade secret laws and
8490+ * treaty provisions. No part of the Material may be used, copied, reproduced,
8491+ * modified, published, uploaded, posted, transmitted, distributed, or
8492+ * disclosed in any way without Intel's prior express written permission.
8493+ *
8494+ * No license under any patent, copyright, trade secret or other intellectual
8495+ * property right is granted to or conferred upon you by disclosure or
8496+ * delivery of the Materials, either expressly, by implication, inducement,
8497+ * estoppel or otherwise. Any license under such intellectual property rights
8498+ * must be express and approved by Intel in writing.
8499+ *
8500+ *
8501+ *-----------------------------------------------------------------------------
8502+ * Description:
8503+ * This file contains nterrupt related routines for the PLB platform.
8504+ *-----------------------------------------------------------------------------
8505+ */
8506+
8507+#include <linux/version.h>
8508+#include "drmP.h"
8509+#include "psb_intregs.h"
8510+#include "iegd_drm.h"
8511+
8512+
8513+irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
8514+{
8515+ int handled = 0;
8516+ struct drm_device *dev = (struct drm_device *)arg;
8517+ intel_device_private_t *priv=dev->dev_private;
8518+ uint32_t vdc_stat, sgx_stat, sgx_stat2, mtx_stat;
8519+
8520+ spin_lock(&priv->irqmask_lock);
8521+ vdc_stat = PSB_RVDC32(IIR);
8522+ sgx_stat = PSB_RSGX32(PSB_CR_EVENT_STATUS);
8523+ sgx_stat2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
8524+ mtx_stat = PSB_RMSVDX32(PSB_MTX_EVENT_STATUS);
8525+ vdc_stat &= priv->vdc_irq_mask;
8526+ sgx_stat &= priv->sgx_irq_mask;
8527+ sgx_stat2 &= priv->sgx_irq_mask2;
8528+ mtx_stat &= priv->msvdx_irq_mask;
8529+
8530+ if (vdc_stat) {
8531+ PSB_WVDC32(vdc_stat, IIR);
8532+ (void)PSB_RVDC32(IIR);
8533+
8534+ priv->out_vdc |= vdc_stat;
8535+ handled = 1;
8536+
8537+ if (sgx_stat || sgx_stat2 || mtx_stat) {
8538+ PSB_WSGX32(sgx_stat, PSB_CR_EVENT_HOST_CLEAR);
8539+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR);
8540+ PSB_WSGX32(sgx_stat2, PSB_CR_EVENT_HOST_CLEAR2);
8541+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
8542+ PSB_WMSVDX32(mtx_stat, PSB_MTX_EVENT_CLEAR);
8543+ (void)PSB_RMSVDX32(PSB_MTX_EVENT_CLEAR);
8544+
8545+ priv->out_sgx |= sgx_stat;
8546+ priv->out_sgx2 |= sgx_stat2;
8547+ priv->out_mtx |= mtx_stat;
8548+
8549+ priv->event_present = 1;
8550+ spin_unlock(&priv->irqmask_lock);
8551+ DRM_WAKEUP(&priv->event_queue);
8552+
8553+ } else {
8554+
8555+ spin_unlock(&priv->irqmask_lock);
8556+
8557+ }
8558+
8559+ } else {
8560+
8561+ spin_unlock(&priv->irqmask_lock);
8562+
8563+ }
8564+
8565+ if (!handled) {
8566+ return IRQ_NONE;
8567+ }
8568+
8569+ return IRQ_HANDLED;
8570+}
8571+
8572+void psb_irq_preinstall(struct drm_device *dev)
8573+{
8574+ intel_device_private_t *priv =
8575+ (intel_device_private_t *)dev->dev_private;
8576+
8577+ spin_lock(&priv->irqmask_lock);
8578+ PSB_WVDC32(0xFFFFFFFF, HWSTAM);
8579+ PSB_WVDC32(0xFFFFFFFF, IMR);
8580+ PSB_WVDC32(0x00000000, IER);
8581+
8582+ PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
8583+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
8584+ PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE2);
8585+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE2);
8586+ PSB_WMSVDX32(0x00000000, PSB_MTX_EVENT_HOST_ENABLE);
8587+ (void)PSB_RMSVDX32(PSB_MTX_EVENT_HOST_ENABLE);
8588+
8589+ priv->sgx_irq_mask = PSB_TWOD_COMPLETE |
8590+ PSB_TA_FINISHED | PSB_TA_TERMINATE |
8591+ PSB_PIXELBE_END_RENDER | PSB_DPM_3D_MEM_FREE |
8592+ PSB_OUT_OF_MEM_MT | PSB_OUT_OF_MEM_GBL |
8593+ PSB_REACHED_MEM_THRESH | PSB_DPM_TA_MEM_FREE |
8594+ PSB_DPM_OUT_OF_MEM_ZLS | PSB_TA_DPM_FAULT;
8595+
8596+ priv->sgx_irq_mask2 = PSB_BIF_REQ_FAULT | PSB_TRIG_TA | PSB_TRIG_3D |
8597+ PSB_TRIG_DL;
8598+
8599+ priv->vdc_irq_mask = IRQ_SGX_FLAG | IRQ_MSVDX_FLAG;
8600+
8601+ priv->msvdx_irq_mask = (1<<14); /* Enable only MTX interrupt */
8602+
8603+ spin_unlock(&priv->irqmask_lock);
8604+}
8605+
8606+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)
8607+void psb_irq_postinstall(struct drm_device *dev)
8608+#else
8609+int psb_irq_postinstall(struct drm_device *dev)
8610+#endif
8611+{
8612+ intel_device_private_t *priv =
8613+ (intel_device_private_t *)dev->dev_private;
8614+ unsigned long irqflags;
8615+
8616+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
8617+ PSB_WVDC32(priv->vdc_irq_mask, IER);
8618+ PSB_WSGX32(priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
8619+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
8620+ PSB_WSGX32(priv->sgx_irq_mask2, PSB_CR_EVENT_HOST_ENABLE2);
8621+ (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE2);
8622+ PSB_WMSVDX32(priv->msvdx_irq_mask, PSB_MTX_EVENT_HOST_ENABLE);
8623+ (void)PSB_RMSVDX32(PSB_MTX_EVENT_HOST_ENABLE);
8624+
8625+ priv->irq_enabled = 1;
8626+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
8627+
8628+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
8629+ return 0;
8630+#endif
8631+
8632+}
8633+
8634+void psb_irq_uninstall(struct drm_device *dev)
8635+{
8636+ intel_device_private_t *priv =
8637+ (intel_device_private_t *)dev->dev_private;
8638+ unsigned long irqflags;
8639+
8640+ spin_lock_irqsave(&priv->irqmask_lock, irqflags);
8641+
8642+ priv->sgx_irq_mask = 0x00000000;
8643+ priv->sgx_irq_mask2 = 0x00000000;
8644+ priv->vdc_irq_mask = 0x00000000;
8645+ priv->msvdx_irq_mask = 0x00000000;
8646+
8647+ /* By default, we're enabling interrupts buy leaving them masked */
8648+ PSB_WVDC32(0xFFFFFFFF, HWSTAM);
8649+ PSB_WVDC32(0xFFFFFFFF, IMR);
8650+ PSB_WVDC32(priv->vdc_irq_mask, IER);
8651+ PSB_WSGX32(priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE);
8652+ PSB_WSGX32(priv->sgx_irq_mask2, PSB_CR_EVENT_HOST_ENABLE2);
8653+ PSB_WMSVDX32(priv->msvdx_irq_mask, PSB_MTX_EVENT_HOST_ENABLE);
8654+ wmb();
8655+ PSB_WVDC32(PSB_RVDC32(IIR), IIR);
8656+ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS), PSB_CR_EVENT_HOST_CLEAR);
8657+ PSB_WSGX32(PSB_RSGX32(PSB_CR_EVENT_STATUS2), PSB_CR_EVENT_HOST_CLEAR2);
8658+ PSB_WMSVDX32(PSB_RMSVDX32(PSB_MTX_EVENT_STATUS), PSB_MTX_EVENT_CLEAR);
8659+
8660+ priv->irq_enabled = 0;
8661+ spin_unlock_irqrestore(&priv->irqmask_lock, irqflags);
8662+}
8663diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/global.h patch_script_temp/drivers/gpu/drm/iegd/include/global.h
8664--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/global.h 1969-12-31 17:00:00.000000000 -0700
8665+++ patch_script_temp/drivers/gpu/drm/iegd/include/global.h 2009-10-06 10:30:05.000000000 -0700
8666@@ -0,0 +1,160 @@
8667+/* -*- pse-c -*-
8668+ * Filename: iegd_interface.c
8669+ * $Revision: 1.19 $
8670+ *----------------------------------------------------------------------------
8671+ * <>
8672+ * Copyright © 2008, Intel Corporation.
8673+ *
8674+ * This program is free software; you can redistribute it and/or modify it
8675+ * under the terms and conditions of the GNU General Public License,
8676+ * version 2, as published by the Free Software Foundation.
8677+ *
8678+ * This program is distributed in the hope it will be useful, but WITHOUT
8679+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8680+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8681+ * more details.
8682+ *
8683+ * You should have received a copy of the GNU General Public License along with
8684+ * this program; if not, write to the Free Software Foundation, Inc.,
8685+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8686+ *
8687+ *
8688+ *----------------------------------------------------------------------------
8689+ * Functions:
8690+ *
8691+ *
8692+ *----------------------------------------------------------------------------
8693+ */
8694+
8695+#ifndef _GART_GLOBAL_DEF
8696+#define _GART_GLOBAL_DEF
8697+#include "igd_gart.h"
8698+#include "igd_abs.h"
8699+#include "interface_abs.h"
8700+
8701+
8702+#define APER_ENTRY(a,b) sizeof((a))/(b)
8703+#define AGP_DCACHE_MEMORY 1
8704+#define AGP_PHYS_MEMORY 2
8705+
8706+#define IEGD "IEGD"
8707+
8708+/**
8709+ * This is global data that is shared across file. New global
8710+ * data should goes here.
8711+ */
8712+extern gart_dispatch_t *gart_id;
8713+extern dev_private_data_t private_data;
8714+extern struct pci_device_id iegd_pci_table[];
8715+extern dispatch_table_t driver_dispatch_list[];
8716+extern struct gatt_mask iegd_cmn_masks[];
8717+extern struct aper_size_info_fixed iegd_i915_sizes[];
8718+extern struct aper_size_info_fixed iegd_iq35_sizes[];
8719+extern struct aper_size_info_fixed iegd_i965_sizes[];
8720+extern struct aper_size_info_fixed intel_i830_sizes[];
8721+extern struct aper_size_info_fixed intel_i810_sizes[];
8722+extern struct aper_size_info_fixed iegd_igm45_sizes[];
8723+
8724+/* All dispatch table for the chipset family goes here */
8725+extern bridge_driver_t drv_alm;
8726+extern bridge_driver_t drv_nap;
8727+extern bridge_driver_t drv_gn4;
8728+extern bridge_driver_t drv_gm45;
8729+
8730+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
8731+/* Poulsbo */
8732+extern struct aper_size_info_fixed iegd_plb_sizes[];
8733+extern bridge_driver_t drv_plb;
8734+
8735+/* Poulsbo specific structure so that the DRM can utilize the
8736+ * AGP's virtual aperture management code
8737+ */
8738+extern struct vm_operations_struct iegd_plb_vm_ops;
8739+#endif
8740+
8741+
8742+/*
8743+ * Macro to fill device information for PCI devices registration.
8744+ * Copy from public agpgart in kernel source
8745+ */
8746+#define ID(x) { \
8747+ .class = (PCI_CLASS_BRIDGE_HOST << 8), \
8748+ .class_mask = ~0, \
8749+ .vendor = PCI_VENDOR_ID_INTEL, \
8750+ .device = x, \
8751+ .subvendor = PCI_ANY_ID, \
8752+ .subdevice = PCI_ANY_ID, \
8753+}
8754+
8755+#ifdef CONFIG_AGP_DEBUG
8756+#define AGN_DEBUG(x,y...) printk(KERN_INFO "[" IEGD \
8757+ ":DEBUG]:%s " x "\n", __FUNCTION__, ##y)
8758+#else
8759+#define AGN_DEBUG(x,y...) do {} while(0)
8760+#endif
8761+
8762+#define AGN_ERROR(x,y...) printk(KERN_ALERT "[" IEGD \
8763+ ":ERROR]:%s: " x "\n", __FUNCTION__, ##y)
8764+#define AGN_LOG(x,y...) printk(KERN_INFO "[" IEGD "]: " x "\n", ##y)
8765+
8766+/**
8767+ * Global extern function prototype, basically common function
8768+ * should goes here. Most of this function extern is from
8769+ * drv_cmn.c
8770+ */
8771+extern int iegd_find_device(u16 device);
8772+extern struct pci_dev *iegd_probe_device(void);
8773+extern void iegd_cmn_init_gtt_entries(void);
8774+extern int AGP_FREE_GATT(iegd_cmn_free_gatt_table);
8775+extern void iegd_cmn_free_by_type(struct agp_memory *curr);
8776+extern struct agp_memory *iegd_cmn_alloc_by_type(
8777+ size_t pg_count, int type);
8778+extern int iegd_cmn_insert_entries(struct agp_memory *mem,
8779+ off_t pg_start, int type);
8780+extern int iegd_cmn_remove_entries(struct agp_memory *mem, off_t pg_start,
8781+ int type);
8782+extern int bridge_driver_init(bridge_driver_t **driver_hook,
8783+ unsigned short did, dispatch_table_t *list );
8784+
8785+#ifndef MSR_IA32_CR_PAT
8786+#define MSR_IA32_CR_PAT 0x0277
8787+#endif
8788+#ifndef _PAGE_PAT
8789+#define _PAGE_PAT 0x080
8790+#endif
8791+extern void agp_init_pat(void);
8792+extern int agp_use_pat (void);
8793+
8794+/**
8795+ * masking valid bit for page table entries before
8796+ * put it insert it to gtt table
8797+ */
8798+unsigned long AGP_MASK_MEMORY(iegd_cmn_mask_memory);
8799+int AGP_CREATE_GATT(iegd_alm_create_gatt_table);
8800+extern int iegd_cmn_configure(void);
8801+extern void AGP_ENABLE(iegd_cmn_agp_enable);
8802+
8803+/* Global DRM function prototype */
8804+extern int intel_init(void);
8805+extern void intel_exit(void);
8806+extern int drm_init(void);
8807+extern void drm_cleanup(void);
8808+
8809+/* Generic function to dispatch the information according to
8810+ * chipset id */
8811+static __inline void *dispatch_acquire(
8812+
8813+ unsigned short did,
8814+ dispatch_table_t *table_list) {
8815+
8816+ dispatch_table_t *curr = table_list;
8817+ while(curr && (curr->did != 0)) {
8818+ if(curr->did == did) {
8819+ return curr->table;
8820+ }
8821+ curr++;
8822+ }
8823+
8824+ return NULL;
8825+}
8826+#endif
8827diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/igd_abs.h patch_script_temp/drivers/gpu/drm/iegd/include/igd_abs.h
8828--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/igd_abs.h 1969-12-31 17:00:00.000000000 -0700
8829+++ patch_script_temp/drivers/gpu/drm/iegd/include/igd_abs.h 2009-10-06 10:30:05.000000000 -0700
8830@@ -0,0 +1,136 @@
8831+/* -*- pse-c -*-
8832+ *----------------------------------------------------------------------------
8833+ * Filename: iegd_interface.c
8834+ * $Revision: 1.15 $
8835+ *----------------------------------------------------------------------------
8836+ * <>
8837+ * Copyright © 2008, Intel Corporation.
8838+ *
8839+ * This program is free software; you can redistribute it and/or modify it
8840+ * under the terms and conditions of the GNU General Public License,
8841+ * version 2, as published by the Free Software Foundation.
8842+ *
8843+ * This program is distributed in the hope it will be useful, but WITHOUT
8844+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8845+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8846+ * more details.
8847+ *
8848+ * You should have received a copy of the GNU General Public License along with
8849+ * this program; if not, write to the Free Software Foundation, Inc.,
8850+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8851+ *
8852+ *
8853+ *----------------------------------------------------------------------------
8854+ * Functions:
8855+ *
8856+ *
8857+ *----------------------------------------------------------------------------
8858+ */
8859+
8860+#ifndef _KERNEL_ABS_LAYER
8861+#define _KERNEL_ABS_LAYER
8862+
8863+#include <linux/version.h>
8864+
8865+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
8866+#define IGD_FREE_MEM(a) agp_free_page_array(a)
8867+#else
8868+#define IGD_FREE_MEM(a) vfree((a)->memory)
8869+#endif
8870+
8871+#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,5)
8872+#define DRM_INIT_MODULE() drm_init()
8873+#define DRM_EXIT_MODULE() drm_cleanup()
8874+#define AGP_RET(a) ((a)>=0) ? 1 : 0
8875+#else
8876+#define DRM_INIT_MODULE() intel_init()
8877+#define DRM_EXIT_MODULE() intel_exit()
8878+#define AGP_RET(a) ((a)==0) ? 1 : 0
8879+#endif
8880+
8881+#if LINUX_VERSION_CODE<KERNEL_VERSION(2,6,10)
8882+#define IGD_PCI_SAVE_STATE(a,b) pci_save_state(a,b)
8883+#define IGD_PCI_RESTORE_STATE(a,b) pci_restore_state(a,b)
8884+#define pm_message_t u32
8885+#define IGD_IS_SUSPEND(state) ((state)==3)
8886+#else
8887+#define IGD_PCI_SAVE_STATE(a,b) pci_save_state(a)
8888+#define IGD_PCI_RESTORE_STATE(a,b) pci_restore_state(a)
8889+#define IGD_IS_SUSPEND(state) \
8890+ (((state.event)==PM_EVENT_SUSPEND) | ((state.event)==PM_EVENT_FREEZE))
8891+#endif
8892+
8893+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
8894+#define AGP_LOCK_PAGE(a)
8895+#define AGP_UNLOCK_PAGE(a)
8896+#else
8897+#define AGP_LOCK_PAGE(a) SetPageLocked((a))
8898+#define AGP_UNLOCK_PAGE(a) unlock_page((a))
8899+#endif
8900+
8901+#define MASK_PTE(a,b) (a)->driver->masks[(b)].mask
8902+#define AGP_MASK_ADDR(x) MASK_PTE((x),type)
8903+
8904+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
8905+#ifndef TRUE
8906+#define TRUE 1
8907+#endif
8908+#ifndef FALSE
8909+#define FALSE 0
8910+#endif
8911+#define SET_PAGES_UC(a,b) set_pages_uc(a,b)
8912+#define SET_PAGES_WB(a,b) set_pages_wb(a,b)
8913+#define GLOBAL_FLUSH_TLB()
8914+#ifndef SetPageLocked
8915+#define SetPageLocked(page) set_bit(PG_locked, &page->flags);
8916+#endif
8917+#else
8918+#define SET_PAGES_UC(a,b) change_page_attr(a,b,PAGE_KERNEL_NOCACHE)
8919+#define SET_PAGES_WB(a,b) change_page_attr(a,b,PAGE_KERNEL)
8920+#define GLOBAL_FLUSH_TLB() global_flush_tlb()
8921+#endif
8922+
8923+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
8924+#define ON_EACH_CPU(a,b,c,d) on_each_cpu(a,b,d)
8925+/* Note: drm_dev_to_irq appears 2.6.28, but some distros
8926+ * have pulled it into earlier versions of their kernel.
8927+ * That's why it's defined here.
8928+ */
8929+#define DRM_DEV_TO_IRQ(a) drm_dev_to_irq(a)
8930+#else
8931+#define ON_EACH_CPU(a,b,c,d) on_each_cpu(a,b,c,d)
8932+#define DRM_DEV_TO_IRQ(a) (a->irq)
8933+#endif
8934+
8935+
8936+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
8937+#define AGP_MEM_TYPE struct page*
8938+#define CONVERT_PAGE_TO_GART(a) phys_to_gart(page_to_phys(a));
8939+#define AGP_MEMORY_MEMBER pages
8940+#define PAGE_ADDRESS(a) a
8941+#else
8942+#define AGP_MEM_TYPE void*
8943+#define CONVERT_PAGE_TO_GART(a) a
8944+#define AGP_MEMORY_MEMBER memory
8945+#define PAGE_ADDRESS(a) page_address(a)
8946+#endif
8947+
8948+
8949+/*
8950+ * Kernel interface abstraction. This macro will
8951+ * point to the proper definition for that particular
8952+ * kernel
8953+ */
8954+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
8955+#define AGP_MASK_MEMORY(f) _MASK_MEMORY_PAGE(f)
8956+#else
8957+#define AGP_MASK_MEMORY(f) _MASK_MEMORY(f)
8958+#endif
8959+#define AGP_CREATE_GATT(f) _CREATE_GATT_TABLE(f)
8960+#define AGP_FREE_GATT(f) _FREE_GATT_TABLE(f)
8961+#define AGP_ALLOC_PAGE(f) _ALLOC_PAGE_AGP(f)
8962+#define AGP_ENABLE(f) _ENABLE_AGP(f)
8963+#define AGP_TYPE_TO_MASK_TYPE(f) _TYPE_TO_MASK_TYPE(f)
8964+
8965+#define AGP_MASK_GTT() _mask_gtt()
8966+#endif
8967diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/igd_gart.h patch_script_temp/drivers/gpu/drm/iegd/include/igd_gart.h
8968--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/igd_gart.h 1969-12-31 17:00:00.000000000 -0700
8969+++ patch_script_temp/drivers/gpu/drm/iegd/include/igd_gart.h 2009-10-06 10:30:05.000000000 -0700
8970@@ -0,0 +1,81 @@
8971+/* -*- pse-c -*-
8972+ *----------------------------------------------------------------------------
8973+ * Filename: igd_gart.h
8974+ * $Revision: 1.10 $
8975+ *----------------------------------------------------------------------------
8976+ * <>
8977+ * Copyright © 2008, Intel Corporation.
8978+ *
8979+ * This program is free software; you can redistribute it and/or modify it
8980+ * under the terms and conditions of the GNU General Public License,
8981+ * version 2, as published by the Free Software Foundation.
8982+ *
8983+ * This program is distributed in the hope it will be useful, but WITHOUT
8984+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8985+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
8986+ * more details.
8987+ *
8988+ * You should have received a copy of the GNU General Public License along with
8989+ * this program; if not, write to the Free Software Foundation, Inc.,
8990+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
8991+ *
8992+ *
8993+ *----------------------------------------------------------------------------
8994+ * Functions:
8995+ *
8996+ *
8997+ *----------------------------------------------------------------------------
8998+ */
8999+
9000+#ifndef _INIT_GART_DISPATCH
9001+#define _INIT_GART_DISPATCH
9002+
9003+#include <linux/pci.h>
9004+#include <linux/agp_backend.h>
9005+#include "agp.h"
9006+
9007+typedef struct agp_bridge_driver bridge_driver_t;
9008+typedef struct agp_bridge_data bridge_data_t;
9009+
9010+/* Dispatch table that contained information about
9011+ * specific chipset */
9012+typedef struct _gart_dispatch {
9013+ unsigned short vendor_id;
9014+ unsigned short bridge_id; /* Bridge device id */
9015+ unsigned short device_id; /* chipset id */
9016+ char *name; /* Name for the chipset */
9017+ unsigned short dev_flag;
9018+ struct pci_driver *old_gart; /* old gart info */
9019+ struct pci_dev *bridge_pdev; /* Bridge device info */
9020+ bridge_data_t *bridge_info; /* bridge information for gart */
9021+}gart_dispatch_t;
9022+
9023+/* Structure that keep the private data for chipset */
9024+typedef struct _dev_private_data {
9025+ struct pci_dev *pdev;
9026+ volatile u8 __iomem *registers;
9027+ volatile u32 __iomem *gtt;
9028+ union {
9029+ int num_dcache_entries;
9030+ int gtt_entries;
9031+ };
9032+ u32 pm_save[16]; /* PCI config saved here on suspend/resume. */
9033+ /* Required for older kernel versions. */
9034+ int split_gtt;
9035+ volatile u32 __iomem *upper_gtt;
9036+}dev_private_data_t;
9037+
9038+/* Dispatch table for function hook */
9039+typedef struct _dispatch_table {
9040+ unsigned short did;
9041+ void *table;
9042+}dispatch_table_t;
9043+
9044+/* Table contained function pointer for specific chipset */
9045+typedef struct _driver_func_table {
9046+ bridge_driver_t driver_func; /* Contained actual function */
9047+ void (*config_private)(void); /* config private */
9048+}driver_func_table_t;
9049+
9050+
9051+#endif
9052diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/intelpci.h patch_script_temp/drivers/gpu/drm/iegd/include/intelpci.h
9053--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/intelpci.h 1969-12-31 17:00:00.000000000 -0700
9054+++ patch_script_temp/drivers/gpu/drm/iegd/include/intelpci.h 2009-10-06 10:30:05.000000000 -0700
9055@@ -0,0 +1,178 @@
9056+/* -*- pse-c -*-
9057+ *----------------------------------------------------------------------------
9058+ * Filename: intelpci.h
9059+ * $Revision: 1.16 $
9060+ *----------------------------------------------------------------------------
9061+ * <>
9062+ * Copyright © 2008, Intel Corporation.
9063+ *
9064+ * This program is free software; you can redistribute it and/or modify it
9065+ * under the terms and conditions of the GNU General Public License,
9066+ * version 2, as published by the Free Software Foundation.
9067+ *
9068+ * This program is distributed in the hope it will be useful, but WITHOUT
9069+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9070+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9071+ * more details.
9072+ *
9073+ * You should have received a copy of the GNU General Public License along with
9074+ * this program; if not, write to the Free Software Foundation, Inc.,
9075+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
9076+ *
9077+ *
9078+ *----------------------------------------------------------------------------
9079+ * Functions:
9080+ *
9081+ *
9082+ *----------------------------------------------------------------------------
9083+ */
9084+
9085+#define PCI_VENDOR_ID_INTEL 0x8086
9086+
9087+
9088+/* Start: Whitney core specific */
9089+#define PCI_DEVICE_ID_BRIDGE_810 0x7120
9090+#define PCI_DEVICE_ID_810 0x7121
9091+
9092+#define PCI_DEVICE_ID_BRIDGE_810DC 0x7122
9093+#define PCI_DEVICE_ID_810DC 0x7123
9094+
9095+#define PCI_DEVICE_ID_BRIDGE_810E 0x7124
9096+#define PCI_DEVICE_ID_810E 0x7125
9097+
9098+#define PCI_DEVICE_ID_BRIDGE_815 0x1130
9099+#define PCI_DEVICE_ID_815 0x1132
9100+
9101+
9102+/* Start: Almador core specific */
9103+#define PCI_DEVICE_ID_BRIDGE_830M 0x3575
9104+#define PCI_DEVICE_ID_830M 0x3577
9105+#define PCI_DEVICE_ID_AGP_830M 0x3576
9106+
9107+#define PCI_DEVICE_ID_BRIDGE_835 0x3579
9108+#define PCI_DEVICE_ID_835 0x357b
9109+#define PCI_DEVICE_ID_AGP_835 0x357a
9110+
9111+#define PCI_DEVICE_ID_BRIDGE_845G 0x2560
9112+#define PCI_DEVICE_ID_845G 0x2562
9113+#define PCI_DEVICE_ID_AGP_845G 0x0000
9114+
9115+#define PCI_DEVICE_ID_BRIDGE_855 0x3580 /* Montara-G */
9116+#define PCI_DEVICE_ID_MEM_855 0x3584
9117+#define PCI_DEVICE_ID_855 0x3582
9118+#define PCI_DEVICE_ID_AGP_855 0x0000
9119+
9120+#define PCI_DEVICE_ID_BRIDGE_865G 0x2570
9121+#define PCI_DEVICE_ID_865G 0x2572
9122+#define PCI_DEVICE_ID_AGP_865G 0x0000
9123+
9124+
9125+/* Start: Napa core specific */
9126+/* Grantsdale - 915G/915GV */
9127+#define PCI_DEVICE_ID_BRIDGE_915GD 0x2580
9128+#define PCI_DEVICE_ID_PEG_915GD 0x2581
9129+#define PCI_DEVICE_ID_915GD 0x2582
9130+/* Grantsdale - 910GL*/
9131+#define PCI_DEVICE_ID_BRIDGE_910GL 0x258C
9132+#define PCI_DEVICE_ID_PEG_910GL PCI_DEVICE_ID_PEG_915GD
9133+#define PCI_DEVICE_ID_910GL PCI_DEVICE_ID_915GD
9134+/* Alviso - 915GM/GMS/910GML*/
9135+#define PCI_DEVICE_ID_BRIDGE_915AL 0x2590
9136+#define PCI_DEVICE_ID_PEG_915AL 0x2591
9137+#define PCI_DEVICE_ID_915AL 0x2592
9138+
9139+/* Lakeport - 945G */
9140+#define PCI_DEVICE_ID_BRIDGE_945G 0x2770
9141+#define PCI_DEVICE_ID_PEG_945G 0x2771
9142+#define PCI_DEVICE_ID_945G 0x2772
9143+
9144+/* Calistoga - 945GM */
9145+#define PCI_DEVICE_ID_BRIDGE_945GM 0x27A0
9146+#define PCI_DEVICE_ID_PEG_945GM 0x27A1
9147+#define PCI_DEVICE_ID_945GM 0x27A2
9148+
9149+/* Calistoga Westbriar - 945GME/GSE */
9150+#define PCI_DEVICE_ID_BRIDGE_945GME 0x27AC
9151+#define PCI_DEVICE_ID_PEG_945GME 0x27AD
9152+#define PCI_DEVICE_ID_945GME 0x27AE
9153+
9154+/* Bearlake B - Q35 */
9155+#define PCI_DEVICE_ID_BRIDGE_Q35 0x29C0
9156+#define PCI_DEVICE_ID_PEG_Q35 0x29C1
9157+#define PCI_DEVICE_ID_Q35 0x29C2
9158+
9159+/* Bearlake B - Q35 */
9160+#define PCI_DEVICE_ID_BRIDGE_Q35A2 0x29B0
9161+#define PCI_DEVICE_ID_PEG_Q35A2 0x29B1
9162+#define PCI_DEVICE_ID_Q35A2 0x29B2
9163+
9164+/* Start: Gen4 core specific*/
9165+/* Broadwater - Unlocked - 965G */
9166+#define PCI_DEVICE_ID_BRIDGE_965G 0x2980
9167+#define PCI_DEVICE_ID_PEG_965G 0x2981
9168+#define PCI_DEVICE_ID_965G 0x2982
9169+
9170+/* Broadwater - Value - 945GZ */
9171+#define PCI_DEVICE_ID_BRIDGE_946GZ 0x2970
9172+#define PCI_DEVICE_ID_PEG_946GZ 0x2971
9173+#define PCI_DEVICE_ID_946GZ 0x2972
9174+
9175+/* Broadwater - Consumer - G965 */
9176+#define PCI_DEVICE_ID_BRIDGE_G965 0x29A0
9177+#define PCI_DEVICE_ID_PEG_G965 0x29A1
9178+#define PCI_DEVICE_ID_G965 0x29A2
9179+
9180+/* Broadwater - Corporate - Q965/Q963 */
9181+#define PCI_DEVICE_ID_BRIDGE_Q965 0x2990
9182+#define PCI_DEVICE_ID_PEG_Q965 0x2991
9183+#define PCI_DEVICE_ID_Q965 0x2992
9184+
9185+/* Crestline - Generic GM965 */
9186+#define PCI_DEVICE_ID_BRIDGE_GM965 0x2A00
9187+#define PCI_DEVICE_ID_PEG_GM965 0x2A01
9188+#define PCI_DEVICE_ID_GM965 0x2A02
9189+
9190+/* Crestline Westbriar GME965 */
9191+#define PCI_DEVICE_ID_BRIDGE_GME965 0x2A10
9192+#define PCI_DEVICE_ID_PEG_GME965 0x2A11
9193+#define PCI_DEVICE_ID_GME965 0x2A12
9194+
9195+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,5)
9196+/* Poulsbo */
9197+#define PCI_DEVICE_ID_BRIDGE_PLB 0x8100
9198+#define PCI_DEVICE_ID_PEG_PLB 0x8101
9199+#define PCI_DEVICE_ID_PLB 0x8108
9200+#endif
9201+
9202+/* Cantiga GM45 */
9203+#define PCI_DEVICE_ID_BRIDGE_GM45 0x2A40
9204+#define PCI_DEVICE_ID_PEG_GM45 0x2A41
9205+#define PCI_DEVICE_ID_GM45 0x2A42
9206+
9207+#define PCI_DEVICE_ID_BRIDGE_ELK 0x2E00
9208+#define PCI_DEVICE_ID_PEG_ELK 0x2E01
9209+#define PCI_DEVICE_ID_ELK 0x2E02
9210+
9211+#define PCI_DEVICE_ID_BRIDGE_Q45 0x2E10
9212+#define PCI_DEVICE_ID_PEG_Q45 0x2E11
9213+#define PCI_DEVICE_ID_Q45 0x2E12
9214+
9215+#define PCI_DEVICE_ID_BRIDGE_G45 0x2E20
9216+#define PCI_DEVICE_ID_PEG_G45 0x2E21
9217+#define PCI_DEVICE_ID_G45 0x2E22
9218+
9219+#define PCI_DEVICE_ID_BRIDGE_G41 0x2E30
9220+#define PCI_DEVICE_ID_PEG_G41 0x2E31
9221+#define PCI_DEVICE_ID_G41 0x2E32
9222+
9223+#define I915_GMADDR 0x18
9224+#define I915_MMADDR 0x10
9225+#define I915_PTEADDR 0x1C
9226+#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
9227+#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
9228+
9229+/* intel Q35 register */
9230+#define IQ35_BASE_STOLEN 0x5c
9231+#define IQ35_GTT_MEM_SIZE 0x300
9232+#define IQ35_GGMS_1MB 0x100
9233+#define IQ35_GGMS_2MB 0x200
9234diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/interface_abs.h patch_script_temp/drivers/gpu/drm/iegd/include/interface_abs.h
9235--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/drivers/gpu/drm/iegd/include/interface_abs.h 1969-12-31 17:00:00.000000000 -0700
9236+++ patch_script_temp/drivers/gpu/drm/iegd/include/interface_abs.h 2009-10-06 10:30:05.000000000 -0700
9237@@ -0,0 +1,48 @@
9238+/* -*- pse-c -*-
9239+ *----------------------------------------------------------------------------
9240+ * Filename: iegd_interface.c
9241+ * $Revision: 1.4 $
9242+ *----------------------------------------------------------------------------
9243+ * <>
9244+ * Copyright © 2006, Intel Corporation.
9245+ *
9246+ * This program is free software; you can redistribute it and/or modify it
9247+ * under the terms and conditions of the GNU General Public License,
9248+ * version 2, as published by the Free Software Foundation.
9249+ *
9250+ * This program is distributed in the hope it will be useful, but WITHOUT
9251+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9252+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9253+ * more details.
9254+ *
9255+ * You should have received a copy of the GNU General Public License along with
9256+ * this program; if not, write to the Free Software Foundation, Inc.,
9257+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
9258+ *
9259+ *----------------------------------------------------------------------------
9260+ * Functions:
9261+ *
9262+ *
9263+ *----------------------------------------------------------------------------
9264+ */
9265+
9266+#ifndef _AGP_INTERFACE_ABS_LAYER
9267+#define _AGP_INTERFACE_ABS_LAYER
9268+
9269+#define AGP_BRIDGE_VAR bridge
9270+
9271+#define _MASK_MEMORY_PAGE(f) f( struct agp_bridge_data *bridge, \
9272+ struct page* addr, int type)
9273+
9274+#define _MASK_MEMORY(f) f( struct agp_bridge_data *bridge, \
9275+ unsigned long addr, int type)
9276+
9277+#define _CREATE_GATT_TABLE(f) f(struct agp_bridge_data *bridge)
9278+#define _FREE_GATT_TABLE(f) f(struct agp_bridge_data *bridge)
9279+#define _ALLOC_PAGE_AGP(f) f(struct agp_bridge_data *bridge)
9280+#define _ENABLE_AGP(f) f(struct agp_bridge_data *bridge, u32 mode)
9281+#define _TYPE_TO_MASK_TYPE(f) f(struct agp_bridge_data *bridge, int x)
9282+
9283+#define _mask_gtt() agp_bridge->driver->mask_memory( \
9284+ agp_bridge, mem->pages[i], mem->type)
9285+#endif
9286diff -uNr vanilla.2.6.31.rc6-67.1.moblin2-ivi/include/linux/config.h patch_script_temp/include/linux/config.h
9287--- vanilla.2.6.31.rc6-67.1.moblin2-ivi/include/linux/config.h 1969-12-31 17:00:00.000000000 -0700
9288+++ patch_script_temp/include/linux/config.h 2009-10-06 10:30:05.000000000 -0700
9289@@ -0,0 +1 @@
9290+
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-29 04:26:49 +0000