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-rw-r--r--meta-moblin/packages/linux/linux-moblin-2.6.29.1/linux-2.6.29-pnv-drm.patch336
1 files changed, 336 insertions, 0 deletions
diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.29.1/linux-2.6.29-pnv-drm.patch b/meta-moblin/packages/linux/linux-moblin-2.6.29.1/linux-2.6.29-pnv-drm.patch
new file mode 100644
index 0000000000..1e7b866949
--- /dev/null
+++ b/meta-moblin/packages/linux/linux-moblin-2.6.29.1/linux-2.6.29-pnv-drm.patch
@@ -0,0 +1,336 @@
1From 8b941bea1d0fe0c5cf0de938cd0bd89ce6640dbb Mon Sep 17 00:00:00 2001
2From: Shaohua Li <shaohua.li@intel.com>
3Date: Mon, 23 Feb 2009 15:19:19 +0800
4Subject: drm/i915: Add support for new G33-like chipset.
5
6This chip is nearly the same, but has new clock settings required.
7
8Signed-off-by: Shaohua Li <shaohua.li@intel.com>
9Signed-off-by: Eric Anholt <eric@anholt.net>
10---
11 drivers/gpu/drm/i915/i915_drv.h | 10 +++-
12 drivers/gpu/drm/i915/i915_reg.h | 4 +
13 drivers/gpu/drm/i915/intel_display.c | 111 +++++++++++++++++++++++++++++-----
14 include/drm/drm_pciids.h | 2 +
15 4 files changed, 109 insertions(+), 18 deletions(-)
16
17diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
18index 0e27854..36d6bc3 100644
19--- a/drivers/gpu/drm/i915/i915_drv.h
20+++ b/drivers/gpu/drm/i915/i915_drv.h
21@@ -787,15 +787,21 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
22 (dev)->pci_device == 0x2E22 || \
23 IS_GM45(dev))
24
25+#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
26+#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
27+#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
28+
29 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
30 (dev)->pci_device == 0x29B2 || \
31- (dev)->pci_device == 0x29D2)
32+ (dev)->pci_device == 0x29D2 || \
33+ (IS_IGD(dev)))
34
35 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
36 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
37
38 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
39- IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
40+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
41+ IS_IGD(dev))
42
43 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
44 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
45diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
46index 9d6539a..f07d315 100644
47--- a/drivers/gpu/drm/i915/i915_reg.h
48+++ b/drivers/gpu/drm/i915/i915_reg.h
49@@ -358,6 +358,7 @@
50 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
51 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
52 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
53+#define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
54
55 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
56 #define I915_CRC_ERROR_ENABLE (1UL<<29)
57@@ -434,6 +435,7 @@
58 */
59 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
60 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
61+#define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
62 /* i830, required in DVO non-gang */
63 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
64 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
65@@ -500,10 +502,12 @@
66 #define FPB0 0x06048
67 #define FPB1 0x0604c
68 #define FP_N_DIV_MASK 0x003f0000
69+#define FP_N_IGD_DIV_MASK 0x00ff0000
70 #define FP_N_DIV_SHIFT 16
71 #define FP_M1_DIV_MASK 0x00003f00
72 #define FP_M1_DIV_SHIFT 8
73 #define FP_M2_DIV_MASK 0x0000003f
74+#define FP_M2_IGD_DIV_MASK 0x000000ff
75 #define FP_M2_DIV_SHIFT 0
76 #define DPLL_TEST 0x606c
77 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
78diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
79index a283427..1702564 100644
80--- a/drivers/gpu/drm/i915/intel_display.c
81+++ b/drivers/gpu/drm/i915/intel_display.c
82@@ -90,18 +90,32 @@ typedef struct {
83 #define I9XX_DOT_MAX 400000
84 #define I9XX_VCO_MIN 1400000
85 #define I9XX_VCO_MAX 2800000
86+#define IGD_VCO_MIN 1700000
87+#define IGD_VCO_MAX 3500000
88 #define I9XX_N_MIN 1
89 #define I9XX_N_MAX 6
90+/* IGD's Ncounter is a ring counter */
91+#define IGD_N_MIN 3
92+#define IGD_N_MAX 6
93 #define I9XX_M_MIN 70
94 #define I9XX_M_MAX 120
95+#define IGD_M_MIN 2
96+#define IGD_M_MAX 256
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 22
99 #define I9XX_M2_MIN 5
100 #define I9XX_M2_MAX 9
101+/* IGD M1 is reserved, and must be 0 */
102+#define IGD_M1_MIN 0
103+#define IGD_M1_MAX 0
104+#define IGD_M2_MIN 0
105+#define IGD_M2_MAX 254
106 #define I9XX_P_SDVO_DAC_MIN 5
107 #define I9XX_P_SDVO_DAC_MAX 80
108 #define I9XX_P_LVDS_MIN 7
109 #define I9XX_P_LVDS_MAX 98
110+#define IGD_P_LVDS_MIN 7
111+#define IGD_P_LVDS_MAX 112
112 #define I9XX_P1_MIN 1
113 #define I9XX_P1_MAX 8
114 #define I9XX_P2_SDVO_DAC_SLOW 10
115@@ -115,6 +129,8 @@ typedef struct {
116 #define INTEL_LIMIT_I8XX_LVDS 1
117 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
118 #define INTEL_LIMIT_I9XX_LVDS 3
119+#define INTEL_LIMIT_IGD_SDVO_DAC 4
120+#define INTEL_LIMIT_IGD_LVDS 5
121
122 static const intel_limit_t intel_limits[] = {
123 { /* INTEL_LIMIT_I8XX_DVO_DAC */
124@@ -168,6 +184,32 @@ static const intel_limit_t intel_limits[] = {
125 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
126 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
127 },
128+ { /* INTEL_LIMIT_IGD_SDVO */
129+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
130+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
131+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
132+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
133+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
134+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
135+ .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
136+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
137+ .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
138+ .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
139+ },
140+ { /* INTEL_LIMIT_IGD_LVDS */
141+ .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
142+ .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
143+ .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
144+ .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
145+ .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
146+ .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
147+ .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
148+ .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
149+ /* IGD only supports single-channel mode. */
150+ .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
151+ .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
152+ },
153+
154 };
155
156 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
157@@ -175,11 +217,16 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
158 struct drm_device *dev = crtc->dev;
159 const intel_limit_t *limit;
160
161- if (IS_I9XX(dev)) {
162+ if (IS_I9XX(dev) && !IS_IGD(dev)) {
163 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
164 limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
165 else
166 limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
167+ } else if (IS_IGD(dev)) {
168+ if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
169+ limit = &intel_limits[INTEL_LIMIT_IGD_LVDS];
170+ else
171+ limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC];
172 } else {
173 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
174 limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
175@@ -189,8 +236,21 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
176 return limit;
177 }
178
179-static void intel_clock(int refclk, intel_clock_t *clock)
180+/* m1 is reserved as 0 in IGD, n is a ring counter */
181+static void igd_clock(int refclk, intel_clock_t *clock)
182 {
183+ clock->m = clock->m2 + 2;
184+ clock->p = clock->p1 * clock->p2;
185+ clock->vco = refclk * clock->m / clock->n;
186+ clock->dot = clock->vco / clock->p;
187+}
188+
189+static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
190+{
191+ if (IS_IGD(dev)) {
192+ igd_clock(refclk, clock);
193+ return;
194+ }
195 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
196 clock->p = clock->p1 * clock->p2;
197 clock->vco = refclk * clock->m / (clock->n + 2);
198@@ -226,6 +286,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
199 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
200 {
201 const intel_limit_t *limit = intel_limit (crtc);
202+ struct drm_device *dev = crtc->dev;
203
204 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
205 INTELPllInvalid ("p1 out of range\n");
206@@ -235,7 +296,7 @@ static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
207 INTELPllInvalid ("m2 out of range\n");
208 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
209 INTELPllInvalid ("m1 out of range\n");
210- if (clock->m1 <= clock->m2)
211+ if (clock->m1 <= clock->m2 && !IS_IGD(dev))
212 INTELPllInvalid ("m1 <= m2\n");
213 if (clock->m < limit->m.min || limit->m.max < clock->m)
214 INTELPllInvalid ("m out of range\n");
215@@ -289,15 +350,17 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
216 memset (best_clock, 0, sizeof (*best_clock));
217
218 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
219- for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
220- clock.m2 <= limit->m2.max; clock.m2++) {
221+ for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
222+ /* m1 is always 0 in IGD */
223+ if (clock.m2 >= clock.m1 && !IS_IGD(dev))
224+ break;
225 for (clock.n = limit->n.min; clock.n <= limit->n.max;
226 clock.n++) {
227 for (clock.p1 = limit->p1.min;
228 clock.p1 <= limit->p1.max; clock.p1++) {
229 int this_err;
230
231- intel_clock(refclk, &clock);
232+ intel_clock(dev, refclk, &clock);
233
234 if (!intel_PLL_is_valid(crtc, &clock))
235 continue;
236@@ -634,7 +697,7 @@ static int intel_get_core_clock_speed(struct drm_device *dev)
237 return 400000;
238 else if (IS_I915G(dev))
239 return 333000;
240- else if (IS_I945GM(dev) || IS_845G(dev))
241+ else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
242 return 200000;
243 else if (IS_I915GM(dev)) {
244 u16 gcfgc = 0;
245@@ -782,7 +845,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
246 return -EINVAL;
247 }
248
249- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
250+ if (IS_IGD(dev))
251+ fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
252+ else
253+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
254
255 dpll = DPLL_VGA_MODE_DIS;
256 if (IS_I9XX(dev)) {
257@@ -799,7 +865,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
258 }
259
260 /* compute bitmask from p1 value */
261- dpll |= (1 << (clock.p1 - 1)) << 16;
262+ if (IS_IGD(dev))
263+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
264+ else
265+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
266 switch (clock.p2) {
267 case 5:
268 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
269@@ -1279,10 +1348,20 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
270 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
271
272 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
273- clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
274- clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
275+ if (IS_IGD(dev)) {
276+ clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
277+ clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
278+ } else {
279+ clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
280+ clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
281+ }
282+
283 if (IS_I9XX(dev)) {
284- clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
285+ if (IS_IGD(dev))
286+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
287+ DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
288+ else
289+ clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
290 DPLL_FPA01_P1_POST_DIV_SHIFT);
291
292 switch (dpll & DPLL_MODE_MASK) {
293@@ -1301,7 +1380,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
294 }
295
296 /* XXX: Handle the 100Mhz refclk */
297- intel_clock(96000, &clock);
298+ intel_clock(dev, 96000, &clock);
299 } else {
300 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
301
302@@ -1313,9 +1392,9 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
303 if ((dpll & PLL_REF_INPUT_MASK) ==
304 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
305 /* XXX: might not be 66MHz */
306- intel_clock(66000, &clock);
307+ intel_clock(dev, 66000, &clock);
308 } else
309- intel_clock(48000, &clock);
310+ intel_clock(dev, 48000, &clock);
311 } else {
312 if (dpll & PLL_P1_DIVIDE_BY_TWO)
313 clock.p1 = 2;
314@@ -1328,7 +1407,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
315 else
316 clock.p2 = 2;
317
318- intel_clock(48000, &clock);
319+ intel_clock(dev, 48000, &clock);
320 }
321 }
322
323diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
324index 5165f24..76c4c82 100644
325--- a/include/drm/drm_pciids.h
326+++ b/include/drm/drm_pciids.h
327@@ -418,4 +418,6 @@
328 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
329 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
330 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
331+ {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
332+ {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
333 {0, 0, 0}
334--
3351.6.1.3
336
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