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-rw-r--r--meta/recipes-devtools/binutils/binutils-2.22.inc2
-rw-r--r--meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch918
2 files changed, 872 insertions, 48 deletions
diff --git a/meta/recipes-devtools/binutils/binutils-2.22.inc b/meta/recipes-devtools/binutils/binutils-2.22.inc
index 6f1e0dc4ed..ca2d30eca9 100644
--- a/meta/recipes-devtools/binutils/binutils-2.22.inc
+++ b/meta/recipes-devtools/binutils/binutils-2.22.inc
@@ -1,4 +1,4 @@
1PR = "r10" 1PR = "r11"
2 2
3LIC_FILES_CHKSUM="\ 3LIC_FILES_CHKSUM="\
4 file://src-release;endline=17;md5=4830a9ef968f3b18dd5e9f2c00db2d35\ 4 file://src-release;endline=17;md5=4830a9ef968f3b18dd5e9f2c00db2d35\
diff --git a/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch b/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch
index cd42a77324..1f146ce68e 100644
--- a/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch
+++ b/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch
@@ -1,103 +1,501 @@
1Upstream-Status: Pending 1Upstream-Status: Backport
2Signed-off- by: Khem Raj <raj.khem@gmail.com>
2 3
3Add support for FSL PowerPC e5500 core. 4From 4f017a6dfe0c3e84c21431c85e82ce2af0941ac1 Mon Sep 17 00:00:00 2001
5From: Alan Modra <amodra@bigpond.net.au>
6Date: Fri, 9 Mar 2012 23:39:02 +0000
7Subject: [PATCH] include/opcode/ * ppc.h: Add PPC_OPCODE_ALTIVEC2,
8 PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c
9 (ppc_opts): Add entries for "e5500" and "e6500". *
10 ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
11 (PPCVEC2, PPCTMR, E6500): New short names.
12 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni,
13 mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq.,
14 miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx,
15 lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl,
16 lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
17 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS,
18 ESYNC optional operands on sync instruction for E6500
19 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and
20 bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. *
21 cpu-powerpc.c (bfd_powerpc_archs): Add entryies for
22 bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ *
23 config/tc-ppc.c (md_show_usage): Document -me5500 and
24 -me6500. (ppc_handle_align): Add termination nop
25 opcode for e500mc family. * doc/as.texinfo: Document
26 options -me5500 and -me6500. * doc/c-ppc.texi: Likewise.
27 gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test
28 case for e500mc family termination nops. *
29 gas/ppc/e500mc64_nop.d: Likewise. *
30 gas/ppc/e5500_nop.s: Likewise. *
31 gas/ppc/e5500_nop.d: Likewise. *
32 gas/ppc/e6500_nop.s: Likewise. *
33 gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s:
34 New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp:
35 Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
4 36
5Signed-off-by: Edmar Wienskoski <edmar@freescale.com> 37---
6Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 38 bfd/ChangeLog | 7 +++
39 bfd/archures.c | 6 +-
40 bfd/bfd-in2.h | 2 +
41 bfd/cpu-powerpc.c | 34 ++++++++++-
42 gas/ChangeLog | 7 +++
43 gas/config/tc-ppc.c | 14 ++++-
44 gas/doc/as.texinfo | 6 +-
45 gas/doc/c-ppc.texi | 8 ++-
46 gas/testsuite/ChangeLog | 13 ++++
47 gas/testsuite/gas/ppc/e500mc64_nop.d | 13 ++++
48 gas/testsuite/gas/ppc/e500mc64_nop.s | 5 ++
49 gas/testsuite/gas/ppc/e5500_nop.d | 13 ++++
50 gas/testsuite/gas/ppc/e5500_nop.s | 5 ++
51 gas/testsuite/gas/ppc/e6500.d | 75 +++++++++++++++++++++++
52 gas/testsuite/gas/ppc/e6500.s | 69 +++++++++++++++++++++
53 gas/testsuite/gas/ppc/e6500_nop.d | 13 ++++
54 gas/testsuite/gas/ppc/e6500_nop.s | 5 ++
55 gas/testsuite/gas/ppc/ppc.exp | 4 ++
56 include/opcode/ChangeLog | 4 ++
57 include/opcode/ppc.h | 11 +++-
58 opcodes/ChangeLog | 12 ++++
59 opcodes/ppc-dis.c | 14 ++++-
60 opcodes/ppc-opc.c | 112 +++++++++++++++++++++++++++++++---
61 23 files changed, 432 insertions(+), 20 deletions(-)
62 create mode 100644 gas/testsuite/gas/ppc/e500mc64_nop.d
63 create mode 100644 gas/testsuite/gas/ppc/e500mc64_nop.s
64 create mode 100644 gas/testsuite/gas/ppc/e5500_nop.d
65 create mode 100644 gas/testsuite/gas/ppc/e5500_nop.s
66 create mode 100644 gas/testsuite/gas/ppc/e6500.d
67 create mode 100644 gas/testsuite/gas/ppc/e6500.s
68 create mode 100644 gas/testsuite/gas/ppc/e6500_nop.d
69 create mode 100644 gas/testsuite/gas/ppc/e6500_nop.s
7 70
8Index: binutils-2.22/bfd/archures.c 71Index: binutils-2.22/bfd/archures.c
9=================================================================== 72===================================================================
10--- binutils-2.22.orig/bfd/archures.c 73--- binutils-2.22.orig/bfd/archures.c 2012-07-06 20:40:40.000000000 -0700
11+++ binutils-2.22/bfd/archures.c 74+++ binutils-2.22/bfd/archures.c 2012-07-06 20:41:27.822780001 -0700
12@@ -239,6 +239,7 @@ DESCRIPTION 75@@ -1,7 +1,7 @@
76 /* BFD library support routines for architectures.
77 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
78- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
79- Free Software Foundation, Inc.
80+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
81+ 2012 Free Software Foundation, Inc.
82 Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
83
84 This file is part of BFD, the Binary File Descriptor library.
85@@ -239,6 +239,8 @@
13 .#define bfd_mach_ppc_e500 500 86 .#define bfd_mach_ppc_e500 500
14 .#define bfd_mach_ppc_e500mc 5001 87 .#define bfd_mach_ppc_e500mc 5001
15 .#define bfd_mach_ppc_e500mc64 5005 88 .#define bfd_mach_ppc_e500mc64 5005
16+.#define bfd_mach_ppc_e5500 5006 89+.#define bfd_mach_ppc_e5500 5006
90+.#define bfd_mach_ppc_e6500 5007
17 .#define bfd_mach_ppc_titan 83 91 .#define bfd_mach_ppc_titan 83
18 . bfd_arch_rs6000, {* IBM RS/6000 *} 92 . bfd_arch_rs6000, {* IBM RS/6000 *}
19 .#define bfd_mach_rs6k 6000 93 .#define bfd_mach_rs6k 6000
20Index: binutils-2.22/bfd/bfd-in2.h 94Index: binutils-2.22/bfd/bfd-in2.h
21=================================================================== 95===================================================================
22--- binutils-2.22.orig/bfd/bfd-in2.h 96--- binutils-2.22.orig/bfd/bfd-in2.h 2012-07-06 20:40:40.000000000 -0700
23+++ binutils-2.22/bfd/bfd-in2.h 97+++ binutils-2.22/bfd/bfd-in2.h 2012-07-06 20:41:27.822780001 -0700
24@@ -1946,6 +1946,7 @@ enum bfd_architecture 98@@ -1946,6 +1946,8 @@
25 #define bfd_mach_ppc_e500 500 99 #define bfd_mach_ppc_e500 500
26 #define bfd_mach_ppc_e500mc 5001 100 #define bfd_mach_ppc_e500mc 5001
27 #define bfd_mach_ppc_e500mc64 5005 101 #define bfd_mach_ppc_e500mc64 5005
28+#define bfd_mach_ppc_e5500 5006 102+#define bfd_mach_ppc_e5500 5006
103+#define bfd_mach_ppc_e6500 5007
29 #define bfd_mach_ppc_titan 83 104 #define bfd_mach_ppc_titan 83
30 bfd_arch_rs6000, /* IBM RS/6000 */ 105 bfd_arch_rs6000, /* IBM RS/6000 */
31 #define bfd_mach_rs6k 6000 106 #define bfd_mach_rs6k 6000
32Index: binutils-2.22/bfd/cpu-powerpc.c 107Index: binutils-2.22/bfd/cpu-powerpc.c
33=================================================================== 108===================================================================
34--- binutils-2.22.orig/bfd/cpu-powerpc.c 109--- binutils-2.22.orig/bfd/cpu-powerpc.c 2012-07-06 20:40:40.000000000 -0700
35+++ binutils-2.22/bfd/cpu-powerpc.c 110+++ binutils-2.22/bfd/cpu-powerpc.c 2012-07-06 20:41:27.822780001 -0700
36@@ -352,6 +352,20 @@ const bfd_arch_info_type bfd_powerpc_arc 111@@ -1,6 +1,6 @@
37 FALSE, /* not the default */ 112 /* BFD PowerPC CPU definition
38 powerpc_compatible, 113- Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2010
39 bfd_default_scan, 114- Free Software Foundation, Inc.
40+ &bfd_powerpc_archs[19] 115+ Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008,
41+ }, 116+ 2010, 2012 Free Software Foundation, Inc.
42+ { 117 Contributed by Ian Lance Taylor, Cygnus Support.
43+ 64, /* 64 bits in a word */ 118
44+ 64, /* 64 bits in an address */ 119 This file is part of BFD, the Binary File Descriptor library.
45+ 8, /* 8 bits in a byte */
46+ bfd_arch_powerpc,
47+ bfd_mach_ppc_e5500,
48+ "powerpc",
49+ "powerpc:e5500",
50+ 3,
51+ FALSE, /* not the default */
52+ powerpc_compatible,
53+ bfd_default_scan,
54 0
55 }
56 };
57Index: binutils-2.22/gas/config/tc-ppc.c 120Index: binutils-2.22/gas/config/tc-ppc.c
58=================================================================== 121===================================================================
59--- binutils-2.22.orig/gas/config/tc-ppc.c 122--- binutils-2.22.orig/gas/config/tc-ppc.c 2012-07-06 20:40:40.000000000 -0700
60+++ binutils-2.22/gas/config/tc-ppc.c 123+++ binutils-2.22/gas/config/tc-ppc.c 2012-07-06 20:41:27.826780001 -0700
61@@ -1265,6 +1265,7 @@ PowerPC options:\n\ 124@@ -1,6 +1,6 @@
125 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
126 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
127- 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
128+ 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
129 Free Software Foundation, Inc.
130 Written by Ian Lance Taylor, Cygnus Support.
131
132@@ -1265,6 +1265,8 @@
62 -me500, -me500x2 generate code for Motorola e500 core complex\n\ 133 -me500, -me500x2 generate code for Motorola e500 core complex\n\
63 -me500mc, generate code for Freescale e500mc core complex\n\ 134 -me500mc, generate code for Freescale e500mc core complex\n\
64 -me500mc64, generate code for Freescale e500mc64 core complex\n\ 135 -me500mc64, generate code for Freescale e500mc64 core complex\n\
65+-me5500, generate code for Freescale e5500 core complex\n\ 136+-me5500, generate code for Freescale e5500 core complex\n\
137+-me6500, generate code for Freescale e6500 core complex\n\
66 -mspe generate code for Motorola SPE instructions\n\ 138 -mspe generate code for Motorola SPE instructions\n\
67 -mtitan generate code for AppliedMicro Titan core complex\n\ 139 -mtitan generate code for AppliedMicro Titan core complex\n\
68 -mregnames Allow symbolic names for registers\n\ 140 -mregnames Allow symbolic names for registers\n\
141@@ -6012,8 +6014,14 @@
142 }
143
144 if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
145- /* power7 group terminating nop: "ori 2,2,0". */
146- md_number_to_chars (dest, 0x60420000, 4);
147+ {
148+ if (ppc_cpu & PPC_OPCODE_E500MC)
149+ /* e500mc group terminating nop: "ori 0,0,0". */
150+ md_number_to_chars (dest, 0x60000000, 4);
151+ else
152+ /* power7 group terminating nop: "ori 2,2,0". */
153+ md_number_to_chars (dest, 0x60420000, 4);
154+ }
155 else
156 /* power6 group terminating nop: "ori 1,1,0". */
157 md_number_to_chars (dest, 0x60210000, 4);
69Index: binutils-2.22/gas/doc/as.texinfo 158Index: binutils-2.22/gas/doc/as.texinfo
70=================================================================== 159===================================================================
71--- binutils-2.22.orig/gas/doc/as.texinfo 160--- binutils-2.22.orig/gas/doc/as.texinfo 2012-07-06 20:40:40.000000000 -0700
72+++ binutils-2.22/gas/doc/as.texinfo 161+++ binutils-2.22/gas/doc/as.texinfo 2012-07-06 20:41:27.826780001 -0700
73@@ -434,7 +434,7 @@ gcc(1), ld(1), and the Info entries for 162@@ -1,6 +1,6 @@
163 \input texinfo @c -*-Texinfo-*-
164 @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
165-@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
166+@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
167 @c Free Software Foundation, Inc.
168 @c UPDATE!! On future updates--
169 @c (1) check for new machine-dep cmdline options in
170@@ -434,8 +434,8 @@
74 [@b{-a32}|@b{-a64}] 171 [@b{-a32}|@b{-a64}]
75 [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}| 172 [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
76 @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}| 173 @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
77- @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-mppc64bridge}|@b{-mbooke}| 174- @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-mppc64bridge}|@b{-mbooke}|
78+ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-mppc64bridge}|@b{-mbooke}| 175- @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
79 @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| 176+ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
177+ @b{-mbooke}|@b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
80 @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}] 178 @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
81 [@b{-many}] [@b{-maltivec}|@b{-mvsx}] 179 [@b{-many}] [@b{-maltivec}|@b{-mvsx}]
180 [@b{-mregnames}|@b{-mno-regnames}]
82Index: binutils-2.22/gas/doc/c-ppc.texi 181Index: binutils-2.22/gas/doc/c-ppc.texi
83=================================================================== 182===================================================================
84--- binutils-2.22.orig/gas/doc/c-ppc.texi 183--- binutils-2.22.orig/gas/doc/c-ppc.texi 2012-07-06 20:40:40.000000000 -0700
85+++ binutils-2.22/gas/doc/c-ppc.texi 184+++ binutils-2.22/gas/doc/c-ppc.texi 2012-07-06 20:41:27.826780001 -0700
86@@ -88,6 +88,9 @@ Generate code for Freescale e500mc core 185@@ -1,5 +1,5 @@
186 @c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
187-@c Free Software Foundation, Inc.
188+@c 2012 Free Software Foundation, Inc.
189 @c This is part of the GAS manual.
190 @c For copying conditions, see the file as.texinfo.
191 @c man end
192@@ -88,6 +88,12 @@
87 @item -me500mc64 193 @item -me500mc64
88 Generate code for Freescale e500mc64 core complex. 194 Generate code for Freescale e500mc64 core complex.
89 195
90+@item -me5500 196+@item -me5500
91+Generate code for Freescale e5500 core complex. 197+Generate code for Freescale e5500 core complex.
92+ 198+
199+@item -me6500
200+Generate code for Freescale e6500 core complex.
201+
93 @item -mspe 202 @item -mspe
94 Generate code for Motorola SPE instructions. 203 Generate code for Motorola SPE instructions.
95 204
205Index: binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.d
206===================================================================
207--- /dev/null 1970-01-01 00:00:00.000000000 +0000
208+++ binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.d 2012-07-06 20:41:27.826780001 -0700
209@@ -0,0 +1,13 @@
210+#as: -mppc -me500mc64
211+#objdump: -dr -Me500mc64
212+#name: Power E500MC64 nop tests
213+
214+.*: +file format elf(32)?(64)?-powerpc.*
215+
216+Disassembly of section \.text:
217+
218+0+00 <start>:
219+ 0: 60 00 00 00 nop
220+ 4: 60 00 00 00 nop
221+ 8: 60 00 00 00 nop
222+ c: 60 00 00 00 nop
223Index: binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.s
224===================================================================
225--- /dev/null 1970-01-01 00:00:00.000000000 +0000
226+++ binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.s 2012-07-06 20:41:27.826780001 -0700
227@@ -0,0 +1,5 @@
228+# Power E500MC64 nop tests
229+ .section ".text"
230+start:
231+ nop
232+ .p2align 4,,15
233Index: binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.d
234===================================================================
235--- /dev/null 1970-01-01 00:00:00.000000000 +0000
236+++ binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.d 2012-07-06 20:41:27.826780001 -0700
237@@ -0,0 +1,13 @@
238+#as: -mppc -me5500
239+#objdump: -dr -Me5500
240+#name: Power E5500 nop tests
241+
242+.*: +file format elf(32)?(64)?-powerpc.*
243+
244+Disassembly of section \.text:
245+
246+0+00 <start>:
247+ 0: 60 00 00 00 nop
248+ 4: 60 00 00 00 nop
249+ 8: 60 00 00 00 nop
250+ c: 60 00 00 00 nop
251Index: binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.s
252===================================================================
253--- /dev/null 1970-01-01 00:00:00.000000000 +0000
254+++ binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.s 2012-07-06 20:41:27.826780001 -0700
255@@ -0,0 +1,5 @@
256+# Power E5500 nop tests
257+ .section ".text"
258+start:
259+ nop
260+ .p2align 4,,15
261Index: binutils-2.22/gas/testsuite/gas/ppc/e6500.d
262===================================================================
263--- /dev/null 1970-01-01 00:00:00.000000000 +0000
264+++ binutils-2.22/gas/testsuite/gas/ppc/e6500.d 2012-07-06 20:41:27.826780001 -0700
265@@ -0,0 +1,75 @@
266+#as: -mppc -me6500
267+#objdump: -dr -Me6500
268+#name: Power E6500 tests
269+
270+.*: +file format elf(32)?(64)?-powerpc.*
271+
272+Disassembly of section \.text:
273+
274+0+00 <start>:
275+ 0: 10 01 10 c0 vabsdub v0,v1,v2
276+ 4: 10 01 11 00 vabsduh v0,v1,v2
277+ 8: 10 01 11 40 vabsduw v0,v1,v2
278+ c: 7c 01 10 dc mvidsplt v0,r1,r2
279+ 10: 7c 01 11 1c mviwsplt v0,r1,r2
280+ 14: 7c 00 12 0a lvexbx v0,0,r2
281+ 18: 7c 01 12 0a lvexbx v0,r1,r2
282+ 1c: 7c 00 12 4a lvexhx v0,0,r2
283+ 20: 7c 01 12 4a lvexhx v0,r1,r2
284+ 24: 7c 00 12 8a lvexwx v0,0,r2
285+ 28: 7c 01 12 8a lvexwx v0,r1,r2
286+ 2c: 7c 00 13 0a stvexbx v0,0,r2
287+ 30: 7c 01 13 0a stvexbx v0,r1,r2
288+ 34: 7c 00 13 4a stvexhx v0,0,r2
289+ 38: 7c 01 13 4a stvexhx v0,r1,r2
290+ 3c: 7c 00 13 8a stvexwx v0,0,r2
291+ 40: 7c 01 13 8a stvexwx v0,r1,r2
292+ 44: 7c 00 12 4e lvepx v0,0,r2
293+ 48: 7c 01 12 4e lvepx v0,r1,r2
294+ 4c: 7c 00 12 0e lvepxl v0,0,r2
295+ 50: 7c 01 12 0e lvepxl v0,r1,r2
296+ 54: 7c 00 16 4e stvepx v0,0,r2
297+ 58: 7c 01 16 4e stvepx v0,r1,r2
298+ 5c: 7c 00 16 0e stvepxl v0,0,r2
299+ 60: 7c 01 16 0e stvepxl v0,r1,r2
300+ 64: 7c 00 14 8a lvtlx v0,0,r2
301+ 68: 7c 01 14 8a lvtlx v0,r1,r2
302+ 6c: 7c 00 16 8a lvtlxl v0,0,r2
303+ 70: 7c 01 16 8a lvtlxl v0,r1,r2
304+ 74: 7c 00 14 4a lvtrx v0,0,r2
305+ 78: 7c 01 14 4a lvtrx v0,r1,r2
306+ 7c: 7c 00 16 4a lvtrxl v0,0,r2
307+ 80: 7c 01 16 4a lvtrxl v0,r1,r2
308+ 84: 7c 00 15 8a stvflx v0,0,r2
309+ 88: 7c 01 15 8a stvflx v0,r1,r2
310+ 8c: 7c 00 17 8a stvflxl v0,0,r2
311+ 90: 7c 01 17 8a stvflxl v0,r1,r2
312+ 94: 7c 00 15 4a stvfrx v0,0,r2
313+ 98: 7c 01 15 4a stvfrx v0,r1,r2
314+ 9c: 7c 00 17 4a stvfrxl v0,0,r2
315+ a0: 7c 01 17 4a stvfrxl v0,r1,r2
316+ a4: 7c 00 14 ca lvswx v0,0,r2
317+ a8: 7c 01 14 ca lvswx v0,r1,r2
318+ ac: 7c 00 16 ca lvswxl v0,0,r2
319+ b0: 7c 01 16 ca lvswxl v0,r1,r2
320+ b4: 7c 00 15 ca stvswx v0,0,r2
321+ b8: 7c 01 15 ca stvswx v0,r1,r2
322+ bc: 7c 00 17 ca stvswxl v0,0,r2
323+ c0: 7c 01 17 ca stvswxl v0,r1,r2
324+ c4: 7c 00 16 0a lvsm v0,0,r2
325+ c8: 7c 01 16 0a lvsm v0,r1,r2
326+ cc: 7f 5a d3 78 miso
327+ d0: 7c 00 04 ac sync
328+ d4: 7c 00 04 ac sync
329+ d8: 7c 20 04 ac lwsync
330+ dc: 7c 00 04 ac sync
331+ e0: 7c 07 04 ac sync 0,7
332+ e4: 7c 28 04 ac sync 1,8
333+ e8: 7c 00 00 c3 dni 0,0
334+ ec: 7f ff 00 c3 dni 31,31
335+ f0: 7c 40 0b 4d dcblq. 2,0,r1
336+ f4: 7c 43 0b 4d dcblq. 2,r3,r1
337+ f8: 7c 40 09 8d icblq. 2,0,r1
338+ fc: 7c 43 09 8d icblq. 2,r3,r1
339+ 100: 7c 10 02 dc mftmr r0,16
340+ 104: 7c 10 03 dc mttmr 16,r0
341Index: binutils-2.22/gas/testsuite/gas/ppc/e6500.s
342===================================================================
343--- /dev/null 1970-01-01 00:00:00.000000000 +0000
344+++ binutils-2.22/gas/testsuite/gas/ppc/e6500.s 2012-07-06 20:41:27.830780001 -0700
345@@ -0,0 +1,69 @@
346+# Power E6500 tests
347+ .section ".text"
348+start:
349+ vabsdub 0, 1, 2
350+ vabsduh 0, 1, 2
351+ vabsduw 0, 1, 2
352+ mvidsplt 0, 1, 2
353+ mviwsplt 0, 1, 2
354+ lvexbx 0, 0, 2
355+ lvexbx 0, 1, 2
356+ lvexhx 0, 0, 2
357+ lvexhx 0, 1, 2
358+ lvexwx 0, 0, 2
359+ lvexwx 0, 1, 2
360+ stvexbx 0, 0, 2
361+ stvexbx 0, 1, 2
362+ stvexhx 0, 0, 2
363+ stvexhx 0, 1, 2
364+ stvexwx 0, 0, 2
365+ stvexwx 0, 1, 2
366+ lvepx 0, 0, 2
367+ lvepx 0, 1, 2
368+ lvepxl 0, 0, 2
369+ lvepxl 0, 1, 2
370+ stvepx 0, 0, 2
371+ stvepx 0, 1, 2
372+ stvepxl 0, 0, 2
373+ stvepxl 0, 1, 2
374+ lvtlx 0, 0, 2
375+ lvtlx 0, 1, 2
376+ lvtlxl 0, 0, 2
377+ lvtlxl 0, 1, 2
378+ lvtrx 0, 0, 2
379+ lvtrx 0, 1, 2
380+ lvtrxl 0, 0, 2
381+ lvtrxl 0, 1, 2
382+ stvflx 0, 0, 2
383+ stvflx 0, 1, 2
384+ stvflxl 0, 0, 2
385+ stvflxl 0, 1, 2
386+ stvfrx 0, 0, 2
387+ stvfrx 0, 1, 2
388+ stvfrxl 0, 0, 2
389+ stvfrxl 0, 1, 2
390+ lvswx 0, 0, 2
391+ lvswx 0, 1, 2
392+ lvswxl 0, 0, 2
393+ lvswxl 0, 1, 2
394+ stvswx 0, 0, 2
395+ stvswx 0, 1, 2
396+ stvswxl 0, 0, 2
397+ stvswxl 0, 1, 2
398+ lvsm 0, 0, 2
399+ lvsm 0, 1, 2
400+ miso
401+ sync
402+ sync 0,0
403+ sync 1,0
404+ sync 2,0
405+ sync 3,7
406+ sync 3,8
407+ dni 0,0
408+ dni 31,31
409+ dcblq. 2,0,1
410+ dcblq. 2,3,1
411+ icblq. 2,0,1
412+ icblq. 2,3,1
413+ mftmr 0,16
414+ mttmr 16,0
415Index: binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.d
416===================================================================
417--- /dev/null 1970-01-01 00:00:00.000000000 +0000
418+++ binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.d 2012-07-06 20:41:27.830780001 -0700
419@@ -0,0 +1,13 @@
420+#as: -mppc -me6500
421+#objdump: -dr -Me6500
422+#name: Power E6500 nop tests
423+
424+.*: +file format elf(32)?(64)?-powerpc.*
425+
426+Disassembly of section \.text:
427+
428+0+00 <start>:
429+ 0: 60 00 00 00 nop
430+ 4: 60 00 00 00 nop
431+ 8: 60 00 00 00 nop
432+ c: 60 00 00 00 nop
433Index: binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.s
434===================================================================
435--- /dev/null 1970-01-01 00:00:00.000000000 +0000
436+++ binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.s 2012-07-06 20:41:27.830780001 -0700
437@@ -0,0 +1,5 @@
438+# Power E6500 nop tests
439+ .section ".text"
440+start:
441+ nop
442+ .p2align 4,,15
443Index: binutils-2.22/gas/testsuite/gas/ppc/ppc.exp
444===================================================================
445--- binutils-2.22.orig/gas/testsuite/gas/ppc/ppc.exp 2010-02-07 17:59:38.000000000 -0800
446+++ binutils-2.22/gas/testsuite/gas/ppc/ppc.exp 2012-07-06 20:41:27.830780001 -0700
447@@ -42,6 +42,10 @@
448 run_list_test "range" "-a32"
449 run_dump_test "ppc750ps"
450 run_dump_test "e500mc"
451+ run_dump_test "e6500"
452+ run_dump_test "e500mc64_nop"
453+ run_dump_test "e5500_nop"
454+ run_dump_test "e6500_nop"
455 run_dump_test "a2"
456 run_dump_test "cell"
457 run_dump_test "common"
458Index: binutils-2.22/include/opcode/ppc.h
459===================================================================
460--- binutils-2.22.orig/include/opcode/ppc.h 2010-07-02 23:51:53.000000000 -0700
461+++ binutils-2.22/include/opcode/ppc.h 2012-07-06 20:41:27.830780001 -0700
462@@ -1,6 +1,6 @@
463 /* ppc.h -- Header file for PowerPC opcode table
464 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
465- 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
466+ 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
467 Written by Ian Lance Taylor, Cygnus Support
468
469 This file is part of GDB, GAS, and the GNU binutils.
470@@ -174,6 +174,15 @@
471 /* Opcode which is supported by the e500 family */
472 #define PPC_OPCODE_E500 0x100000000ull
473
474+/* Opcode is supported by Extended Altivec Vector Unit */
475+#define PPC_OPCODE_ALTIVEC2 0x200000000ull
476+
477+/* Opcode is supported by Power E6500 */
478+#define PPC_OPCODE_E6500 0x400000000ull
479+
480+/* Opcode is supported by Thread management APU */
481+#define PPC_OPCODE_TMR 0x800000000ull
482+
483 /* A macro to extract the major opcode from an instruction. */
484 #define PPC_OP(i) (((i) >> 26) & 0x3f)
485
96Index: binutils-2.22/opcodes/ppc-dis.c 486Index: binutils-2.22/opcodes/ppc-dis.c
97=================================================================== 487===================================================================
98--- binutils-2.22.orig/opcodes/ppc-dis.c 488--- binutils-2.22.orig/opcodes/ppc-dis.c 2012-07-06 20:40:40.000000000 -0700
99+++ binutils-2.22/opcodes/ppc-dis.c 489+++ binutils-2.22/opcodes/ppc-dis.c 2012-07-06 20:41:27.830780001 -0700
100@@ -114,6 +114,12 @@ struct ppc_mopt ppc_opts[] = { 490@@ -1,6 +1,6 @@
491 /* ppc-dis.c -- Disassemble PowerPC instructions
492 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
493- 2008, 2009, 2010 Free Software Foundation, Inc.
494+ 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
495 Written by Ian Lance Taylor, Cygnus Support
496
497 This file is part of the GNU opcodes library.
498@@ -114,6 +114,18 @@
101 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 499 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
102 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 500 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
103 0 }, 501 0 },
@@ -107,6 +505,432 @@ Index: binutils-2.22/opcodes/ppc-dis.c
107+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 505+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
108+ | PPC_OPCODE_POWER7), 506+ | PPC_OPCODE_POWER7),
109+ 0 }, 507+ 0 },
508+ { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
509+ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
510+ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
511+ | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
512+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
513+ 0 },
110 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 514 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
111 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 515 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
112 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 516 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
517Index: binutils-2.22/opcodes/ppc-opc.c
518===================================================================
519--- binutils-2.22.orig/opcodes/ppc-opc.c 2011-11-21 01:29:40.000000000 -0800
520+++ binutils-2.22/opcodes/ppc-opc.c 2012-07-06 20:41:27.834780001 -0700
521@@ -1,6 +1,6 @@
522 /* ppc-opc.c -- PowerPC opcode list
523 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
524- 2005, 2006, 2007, 2008, 2009, 2010, 2011
525+ 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
526 Free Software Foundation, Inc.
527 Written by Ian Lance Taylor, Cygnus Support
528
529@@ -53,6 +53,7 @@
530 static long extract_boe (unsigned long, ppc_cpu_t, int *);
531 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
532 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
533+static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
534 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
535 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
536 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
537@@ -477,6 +478,7 @@
538 lower 5 bits are stored in the upper 5 and vice- versa. */
539 #define SPR SISIGNOPT + 1
540 #define PMR SPR
541+#define TMR SPR
542 #define SPR_MASK (0x3ff << 11)
543 { 0x3ff, 11, insert_spr, extract_spr, 0 },
544
545@@ -499,8 +501,12 @@
546 #define T STRM
547 { 0x3, 21, NULL, NULL, 0 },
548
549+ /* The ESYNC field in an X (sync) form instruction. */
550+#define ESYNC STRM + 1
551+ { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
552+
553 /* The SV field in a POWER SC form instruction. */
554-#define SV STRM + 1
555+#define SV ESYNC + 1
556 { 0x3fff, 2, NULL, NULL, 0 },
557
558 /* The TBR field in an XFX form instruction. This is like the SPR
559@@ -542,6 +548,7 @@
560
561 /* The UIMM field in a VX form instruction. */
562 #define UIMM SIMM + 1
563+#define DCTL UIMM
564 { 0x1f, 16, NULL, NULL, 0 },
565
566 /* The SHB field in a VA form instruction. */
567@@ -1027,6 +1034,32 @@
568 return mask;
569 }
570
571+/* The LS field in a sync instruction that accepts 2 operands
572+ Values 2 and 3 are reserved,
573+ must be treated as 0 for future compatibility
574+ Values 0 and 1 can be accepted, if field ESYNC is zero
575+ Otherwise L = complement of ESYNC-bit2 (1<<18) */
576+
577+static unsigned long
578+insert_ls (unsigned long insn,
579+ long value,
580+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
581+ const char **errmsg ATTRIBUTE_UNUSED)
582+{
583+ unsigned long ls;
584+
585+ ls = (insn >> 21) & 0x03;
586+ if (value == 0)
587+ {
588+ if (ls > 1)
589+ return insn & ~(0x3 << 21);
590+ return insn;
591+ }
592+ if ((value & 0x2) != 0)
593+ return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16);
594+ return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16);
595+}
596+
597 /* The MB and ME fields in an M form instruction expressed as a single
598 operand which is itself a bitmask. The extraction function always
599 marks it as invalid, since we never want to recognize an
600@@ -1795,6 +1828,9 @@
601 /* An X form sync instruction with everything filled in except the LS field. */
602 #define XSYNC_MASK (0xff9fffff)
603
604+/* An X form sync instruction with everything filled in except the L and E fields. */
605+#define XSYNCLE_MASK (0xff90ffff)
606+
607 /* An X_MASK, but with the EH bit clear. */
608 #define XEH_MASK (X_MASK & ~((unsigned long )1))
609
610@@ -1989,6 +2025,7 @@
611 #define PPC860 PPC
612 #define PPCPS PPC_OPCODE_PPCPS
613 #define PPCVEC PPC_OPCODE_ALTIVEC
614+#define PPCVEC2 PPC_OPCODE_ALTIVEC2
615 #define PPCVSX PPC_OPCODE_VSX
616 #define POWER PPC_OPCODE_POWER
617 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
618@@ -2007,6 +2044,7 @@
619 #define PPCEFS PPC_OPCODE_EFS
620 #define PPCBRLK PPC_OPCODE_BRLOCK
621 #define PPCPMR PPC_OPCODE_PMR
622+#define PPCTMR PPC_OPCODE_TMR
623 #define PPCCHLK PPC_OPCODE_CACHELCK
624 #define PPCRFMCI PPC_OPCODE_RFMCI
625 #define E500MC PPC_OPCODE_E500MC
626@@ -2014,6 +2052,7 @@
627 #define TITAN PPC_OPCODE_TITAN
628 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
629 #define E500 PPC_OPCODE_E500
630+#define E6500 PPC_OPCODE_E6500
631
632 /* The opcode table.
633
634@@ -2179,12 +2218,14 @@
635 {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
636 {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
637 {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
638+{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
639 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
640 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
641 {"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
642 {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
643 {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
644 {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
645+{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
646 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
647 {"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
648 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
649@@ -2197,6 +2238,7 @@
650 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}},
651 {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
652 {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}},
653+{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
654 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
655 {"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
656 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
657@@ -3680,6 +3722,8 @@
658
659 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}},
660
661+{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}},
662+
663 {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}},
664 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
665
666@@ -3689,6 +3733,8 @@
667 {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
668 {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
669
670+{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
671+
672 {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
673
674 {"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}},
675@@ -3723,7 +3769,9 @@
676 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}},
677 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
678
679-{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
680+{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
681+
682+{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
683
684 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
685 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}},
686@@ -3760,7 +3808,7 @@
687 {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
688 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
689
690-{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
691+{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
692
693 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
694
695@@ -3778,6 +3826,8 @@
696
697 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}},
698
699+{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
700+
701 {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}},
702 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
703
704@@ -3855,8 +3905,12 @@
705 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
706 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}},
707
708+{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
709+
710 {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}},
711
712+{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
713+
714 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
715 {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
716 {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
717@@ -3890,6 +3944,9 @@
718
719 {"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}},
720
721+{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
722+{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
723+
724 {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
725 {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
726
727@@ -3941,6 +3998,8 @@
728 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}},
729 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}},
730
731+{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
732+
733 {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}},
734
735 {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
736@@ -3949,6 +4008,7 @@
737 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
738
739 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}},
740+{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}},
741
742 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}},
743 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}},
744@@ -4179,6 +4239,8 @@
745 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
746 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}},
747
748+{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
749+
750 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}},
751 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
752
753@@ -4187,7 +4249,7 @@
754 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
755 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
756
757-{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
758+{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
759
760 {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
761
762@@ -4203,6 +4265,10 @@
763
764 {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}},
765
766+{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
767+
768+{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}},
769+
770 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
771 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
772 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
773@@ -4216,6 +4282,8 @@
774
775 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}},
776
777+{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}},
778+
779 {"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
780 {"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}},
781 {"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}},
782@@ -4258,6 +4326,8 @@
783 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}},
784 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}},
785
786+{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
787+
788 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
789 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
790
791@@ -4268,6 +4338,7 @@
792 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
793
794 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}},
795+{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}},
796
797 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}},
798 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}},
799@@ -4453,7 +4524,7 @@
800 {"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
801 {"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}},
802
803-{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}},
804+{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
805
806 {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}},
807
808@@ -4512,6 +4583,8 @@
809
810 {"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
811
812+{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
813+
814 {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}},
815
816 {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
817@@ -4528,6 +4601,8 @@
818
819 {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
820
821+{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
822+
823 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
824
825 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
826@@ -4539,9 +4614,10 @@
827
828 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
829 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}},
830+{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}},
831 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
832 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
833-{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
834+{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
835 {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}},
836 {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}},
837
838@@ -4552,6 +4628,8 @@
839
840 {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}},
841
842+{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
843+
844 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
845
846 {"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}},
847@@ -4601,6 +4679,8 @@
848
849 {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
850
851+{"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
852+
853 {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
854 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
855
856@@ -4613,6 +4693,8 @@
857
858 {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
859
860+{"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
861+
862 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
863
864 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}},
865@@ -4645,6 +4727,8 @@
866
867 {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}},
868
869+{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
870+
871 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
872
873 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
874@@ -4673,6 +4757,8 @@
875 {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}},
876 {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}},
877
878+{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
879+{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
880 {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
881 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
882
883@@ -4705,6 +4791,8 @@
884
885 {"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}},
886
887+{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
888+{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
889 {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}},
890
891 {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}},
892@@ -4725,6 +4813,8 @@
893 {"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
894 {"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}},
895
896+{"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
897+
898 {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
899 {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
900
901@@ -4743,6 +4833,8 @@
902
903 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}},
904
905+{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
906+
907 {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},
908 {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}},
909
910@@ -4788,6 +4880,8 @@
911
912 {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}},
913
914+{"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
915+
916 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}},
917 {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}},
918 {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}},
919@@ -4816,6 +4910,8 @@
920 {"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}},
921 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}},
922
923+{"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
924+
925 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
926 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}},
927
928@@ -4843,6 +4939,8 @@
929
930 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}},
931
932+{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}},
933+
934 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
935
936 {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}},