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-rw-r--r--meta/recipes-kernel/oprofile/oprofile.inc2
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch219
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/0001-Add-rmb-definition-for-AArch64-architecture.patch31
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/0001-Tidy-powerpc64-bfd-target-check.patch123
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/0002-Add-freescale-e6500-support.patch364
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/filemode-fix.patch41
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/opstart.patch245
-rw-r--r--meta/recipes-kernel/oprofile/oprofile/root-home-dir.patch134
-rw-r--r--meta/recipes-kernel/oprofile/oprofile_0.9.9.bb17
-rw-r--r--meta/recipes-kernel/oprofile/oprofile_1.0.0.bb12
10 files changed, 83 insertions, 1105 deletions
diff --git a/meta/recipes-kernel/oprofile/oprofile.inc b/meta/recipes-kernel/oprofile/oprofile.inc
index 69582039e8..509640c806 100644
--- a/meta/recipes-kernel/oprofile/oprofile.inc
+++ b/meta/recipes-kernel/oprofile/oprofile.inc
@@ -18,7 +18,7 @@ FILES_${PN} = "${bindir} ${libdir}/${BPN}/lib*${SOLIBS} ${datadir}/${BPN}"
18FILES_${PN}-dev += "${libdir}/${BPN}/lib*${SOLIBSDEV} ${libdir}/${BPN}/lib*.la" 18FILES_${PN}-dev += "${libdir}/${BPN}/lib*${SOLIBSDEV} ${libdir}/${BPN}/lib*.la"
19FILES_${PN}-staticdev += "${libdir}/${BPN}/lib*.a" 19FILES_${PN}-staticdev += "${libdir}/${BPN}/lib*.a"
20 20
21SRC_URI = "file://opstart.patch \ 21SRC_URI = "file://filemode-fix.patch \
22 file://acinclude.m4 \ 22 file://acinclude.m4 \
23 file://automake-foreign.patch \ 23 file://automake-foreign.patch \
24 file://oprofile-cross-compile-tests.patch \ 24 file://oprofile-cross-compile-tests.patch \
diff --git a/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch b/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch
deleted file mode 100644
index 077da4bf2b..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile/0001-Add-freescale-e500mc-support.patch
+++ /dev/null
@@ -1,219 +0,0 @@
1From ca3f796b3a7742215ed35b56fc072595174c410e Mon Sep 17 00:00:00 2001
2From: Ting Liu <b28495@freescale.com>
3Date: Thu, 5 Sep 2013 07:43:55 -0500
4Subject: [PATCH 1/2] Add freescale e500mc support
5
6Upstream-Status: Backport
7
8Signed-off-by: George Stephen <Stephen.George@freescale.com>
9Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com>
10Signed-off-by: Ting Liu <b28495@freescale.com>
11---
12 events/Makefile.am | 1 +
13 events/ppc/e500mc/events | 120 ++++++++++++++++++++++++++++++++++++++++++
14 events/ppc/e500mc/unit_masks | 4 ++
15 libop/op_cpu_type.c | 1 +
16 libop/op_cpu_type.h | 1 +
17 libop/op_events.c | 1 +
18 utils/ophelp.c | 1 +
19 7 files changed, 129 insertions(+), 0 deletions(-)
20 create mode 100644 events/ppc/e500mc/events
21 create mode 100644 events/ppc/e500mc/unit_masks
22
23diff --git a/events/Makefile.am b/events/Makefile.am
24index be87781..e496f98 100644
25--- a/events/Makefile.am
26+++ b/events/Makefile.am
27@@ -76,6 +76,7 @@ event_files = \
28 ppc/7450/events ppc/7450/unit_masks \
29 ppc/e500/events ppc/e500/unit_masks \
30 ppc/e500v2/events ppc/e500v2/unit_masks \
31+ ppc/e500mc/events ppc/e500mc/unit_masks \
32 ppc/e300/events ppc/e300/unit_masks \
33 tile/tile64/events tile/tile64/unit_masks \
34 tile/tilepro/events tile/tilepro/unit_masks \
35diff --git a/events/ppc/e500mc/events b/events/ppc/e500mc/events
36new file mode 100644
37index 0000000..8197a7d
38--- /dev/null
39+++ b/events/ppc/e500mc/events
40@@ -0,0 +1,120 @@
41+# e500mc Events
42+#
43+# Copyright (C) 2010 Freescale Semiconductor, Inc.
44+#
45+event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles
46+event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
47+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
48+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
49+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
50+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
51+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
52+event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
53+event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
54+event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
55+event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
56+event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished
57+event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
58+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction
59+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken
60+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
61+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
62+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
63+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
64+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
65+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
66+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
67+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
68+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated.
69+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.)
70+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.)
71+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.)
72+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)
73+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
74+event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated
75+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated
76+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated.
77+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB
78+event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.)
79+event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.)
80+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.)
81+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.)
82+event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.)
83+event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.
84+event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF.
85+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full.
86+event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full.
87+event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer.
88+event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full.
89+event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision.
90+event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss.
91+event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy.
92+event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache.
93+event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full.
94+event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full.
95+event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer.
96+event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full.
97+event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision.
98+event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss.
99+event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy.
100+event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache.
101+event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.)
102+event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.
103+event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
104+event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads
105+event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads
106+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads
107+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads
108+event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt
109+event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.)
110+event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.)
111+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.)
112+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.)
113+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.)
114+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared)
115+event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)
116+event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
117+event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
118+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
119+event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
120+event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
121+event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
122+event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
123+event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
124+event:0x5b counters:0,1,2,3 um:zero minimum:500 name:L2_LINEFILL_REQ : Number L2 Linefill requests
125+event:0x5c counters:0,1,2,3 um:zero minimum:500 name:L2_VICTIM_SELECT : Number L2 Victim selects
126+event:0x6e counters:0,1,2,3 um:zero minimum:500 name:L2_ACCESS : Number L2 cache accesses
127+event:0x6f counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_ACCESS : Number L2 hit cache accesses
128+event:0x70 counters:0,1,2,3 um:zero minimum:500 name:L2_DATA_ACCESS : Number L2 data cache accesses
129+event:0x71 counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_DATA_ACCESS : Number L2 hit data cache accesses
130+event:0x72 counters:0,1,2,3 um:zero minimum:500 name:L2_INST_ACCESS : Number L2 instruction cache accesses
131+event:0x73 counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_INST_ACCESS : Number L2 hit instruction cache accesses
132+event:0x74 counters:0,1,2,3 um:zero minimum:500 name:L2_ALLOC : Number L2 cache allocations
133+event:0x75 counters:0,1,2,3 um:zero minimum:500 name:L2_DATA_ALLOC : Number L2 data cache allocations
134+event:0x76 counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_DATA_ALLOC : Number L2 dirty data cache allocations
135+event:0x77 counters:0,1,2,3 um:zero minimum:500 name:L2_INST_ALLOC : Number L2 instruction cache allocations
136+event:0x78 counters:0,1,2,3 um:zero minimum:500 name:L2_UPDATE : Number L2 cache updates
137+event:0x79 counters:0,1,2,3 um:zero minimum:500 name:L2_CLEAN_UPDATE : Number L2 cache clean updates
138+event:0x7a counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_UPDATE : Number L2 cache dirty updates
139+event:0x7b counters:0,1,2,3 um:zero minimum:500 name:L2_CLEAN_REDU_UPDATE : Number L2 cache clean redundant updates
140+event:0x7c counters:0,1,2,3 um:zero minimum:500 name:L2_DIRTY_REDU_UPDATE : Number L2 cache dirty redundant updates
141+event:0x7d counters:0,1,2,3 um:zero minimum:500 name:L2_LOCKS : Number L2 cache locks
142+event:0x7e counters:0,1,2,3 um:zero minimum:500 name:L2_CASTOUT : Number L2 cache castouts
143+event:0x7f counters:0,1,2,3 um:zero minimum:500 name:L2_HIT_DATA_DIRTY : Number L2 cache data dirty hits
144+event:0x82 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_CLEAN : Number L2 cache invalidation of clean lines
145+event:0x83 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_INCOHER : Number L2 cache invalidation of incoherent lines
146+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L2_INV_COHER : Number L2 cache invalidation of coherent lines
147+event:0x94 counters:0,1,2,3 um:zero minimum:500 name:DVT0 : Detection of write to DEVENT with DVT0 set
148+event:0x95 counters:0,1,2,3 um:zero minimum:500 name:DVT1 : Detection of write to DEVENT with DVT1 set
149+event:0x96 counters:0,1,2,3 um:zero minimum:500 name:DVT2 : Detection of write to DEVENT with DVT2 set
150+event:0x97 counters:0,1,2,3 um:zero minimum:500 name:DVT3 : Detection of write to DEVENT with DVT3 set
151+event:0x98 counters:0,1,2,3 um:zero minimum:500 name:DVT4 : Detection of write to DEVENT with DVT4 set
152+event:0x99 counters:0,1,2,3 um:zero minimum:500 name:DVT5 : Detection of write to DEVENT with DVT5 set
153+event:0x9a counters:0,1,2,3 um:zero minimum:500 name:DVT6 : Detection of write to DEVENT with DVT6 set
154+event:0x9b counters:0,1,2,3 um:zero minimum:500 name:DVT7 : Detection of write to DEVENT with DVT7 set
155+event:0x9c counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NEXUS_STALLED : Number of completion cycles stalled due to Nexus FIFO full
156+event:0xb0 counters:0,1,2,3 um:zero minimum:500 name:DECORATED_LOAD : Number of decorated loads.
157+event:0xb1 counters:0,1,2,3 um:zero minimum:500 name:DECORATED_STORE : Number of decorated stores
158+event:0xb2 counters:0,1,2,3 um:zero minimum:500 name:LOAD_RETRY : Number of load retries
159+event:0xb3 counters:0,1,2,3 um:zero minimum:500 name:STWCX_SUCCESS : Number of successful stwcx. instructions
160+event:0xb4 counters:0,1,2,3 um:zero minimum:500 name:STWCX_UNSUCCESS : Number of unsuccessful stwcx. instructions
161diff --git a/events/ppc/e500mc/unit_masks b/events/ppc/e500mc/unit_masks
162new file mode 100644
163index 0000000..395c653
164--- /dev/null
165+++ b/events/ppc/e500mc/unit_masks
166@@ -0,0 +1,4 @@
167+# e500 possible unit masks
168+#
169+name:zero type:mandatory default:0x0
170+ 0x0 No unit mask
171diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c
172index 89d5a92..7d50a2d 100644
173--- a/libop/op_cpu_type.c
174+++ b/libop/op_cpu_type.c
175@@ -125,6 +125,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
176 { "AMD64 generic", "x86-64/generic", CPU_AMD64_GENERIC, 4 },
177 { "IBM Power Architected Events V1", "ppc64/architected_events_v1", CPU_PPC64_ARCH_V1, 6 },
178 { "ppc64 POWER8", "ppc64/power8", CPU_PPC64_POWER8, 6 },
179+ { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 },
180 };
181
182 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
183diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h
184index aeb6bb2..10f000b 100644
185--- a/libop/op_cpu_type.h
186+++ b/libop/op_cpu_type.h
187@@ -105,6 +105,7 @@ typedef enum {
188 CPU_AMD64_GENERIC, /**< AMD64 Generic */
189 CPU_PPC64_ARCH_V1, /** < IBM Power architected events version 1 */
190 CPU_PPC64_POWER8, /**< ppc64 POWER8 family */
191+ CPU_PPC_E500MC, /**< e500mc */
192 MAX_CPU_TYPE
193 } op_cpu;
194
195diff --git a/libop/op_events.c b/libop/op_events.c
196index bb86833..638dc5c 100644
197--- a/libop/op_events.c
198+++ b/libop/op_events.c
199@@ -1308,6 +1308,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
200
201 case CPU_PPC_E500:
202 case CPU_PPC_E500_2:
203+ case CPU_PPC_E500MC:
204 case CPU_PPC_E300:
205 descr->name = "CPU_CLK";
206 break;
207diff --git a/utils/ophelp.c b/utils/ophelp.c
208index 1b913ca..0647360 100644
209--- a/utils/ophelp.c
210+++ b/utils/ophelp.c
211@@ -753,6 +753,7 @@ int main(int argc, char const * argv[])
212
213 case CPU_PPC_E500:
214 case CPU_PPC_E500_2:
215+ case CPU_PPC_E500MC:
216 event_doc =
217 "See PowerPC e500 Core Complex Reference Manual\n"
218 "Chapter 7: Performance Monitor\n"
219--
diff --git a/meta/recipes-kernel/oprofile/oprofile/0001-Add-rmb-definition-for-AArch64-architecture.patch b/meta/recipes-kernel/oprofile/oprofile/0001-Add-rmb-definition-for-AArch64-architecture.patch
deleted file mode 100644
index a2385cd2b2..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile/0001-Add-rmb-definition-for-AArch64-architecture.patch
+++ /dev/null
@@ -1,31 +0,0 @@
1From 27edaef9c6d66dfc324630ef40cb27e78031eeeb Mon Sep 17 00:00:00 2001
2From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
3Date: Tue, 15 Jan 2013 07:37:33 +0100
4Subject: [PATCH] Add rmb() definition for AArch64 architecture
5
6Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
7
8Upstream-Status: backport
9---
10 libperf_events/operf_utils.h | 5 +++++
11 1 file changed, 5 insertions(+)
12
13diff --git a/libperf_events/operf_utils.h b/libperf_events/operf_utils.h
14index 815d51d..2df00b7 100644
15--- a/libperf_events/operf_utils.h
16+++ b/libperf_events/operf_utils.h
17@@ -148,6 +148,11 @@ void op_release_resources(void);
18 #define cpu_relax() asm volatile("":::"memory")
19 #endif
20
21+#ifdef __aarch64__
22+#define rmb() asm volatile("dmb ld" ::: "memory")
23+#define cpu_relax() asm volatile("yield" ::: "memory")
24+#endif
25+
26 #ifdef __mips__
27 #include <asm/unistd.h>
28 #define rmb() asm volatile( \
29--
301.8.0
31
diff --git a/meta/recipes-kernel/oprofile/oprofile/0001-Tidy-powerpc64-bfd-target-check.patch b/meta/recipes-kernel/oprofile/oprofile/0001-Tidy-powerpc64-bfd-target-check.patch
deleted file mode 100644
index 93c62400cf..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile/0001-Tidy-powerpc64-bfd-target-check.patch
+++ /dev/null
@@ -1,123 +0,0 @@
1Upstream-Status: Backport
2
3From 63b5692aace5ff6022f892822b4bfdc51ed25bfb Mon Sep 17 00:00:00 2001
4From: Alan Modra <amodra@gmail.com>
5Date: Fri, 2 May 2014 07:54:08 -0500
6Subject: [PATCH] Tidy powerpc64 bfd target check
7
8Testing for a bfd_target vector might (will!) break. See
9https://sourceware.org/ml/binutils/2014-04/msg00283.html
10
11It's safer to ask BFD for the target name. I left the direct target
12vector checks in configure tests, and updated them, even though the
13target vector is no longer used in oprofile code, because a run-time
14configure test for powerpc64 support in bfd:
15 #include <bfd.h>
16 int main(void)
17 { return !bfd_find_target("elf64-powerpc", (void *)0); }
18unfortunately isn't possible when cross-compiling.
19
20The bfd_target vector tests could be omitted if we aren't bothered by
21the small runtime overhead of a strncmp on targets other than
22powerpc64.
23
24 * libutil++/bfd_support.cpp (get_synth_symbols): Don't check for
25 ppc64 target vector, use bfd_get_target to return the target
26 name instead.
27 * m4/binutils.m4: Modernize bfd_get_synthetic_symtab checks to
28 use AC_LINK_IFELSE. Check for either powerpc_elf64_vec or
29 bfd_elf64_powerpc_vec.
30
31Signed-off-by: Alan Modra <amodra@gmail.com>
32---
33 libutil++/bfd_support.cpp | 10 +++++++--
34 m4/binutils.m4 | 50 ++++++++++++++++++++++-----------------------
35 2 files changed, 33 insertions(+), 27 deletions(-)
36
37Index: oprofile-0.9.9/libutil++/bfd_support.cpp
38===================================================================
39--- oprofile-0.9.9.orig/libutil++/bfd_support.cpp 2013-07-29 08:55:06.000000000 -0700
40+++ oprofile-0.9.9/libutil++/bfd_support.cpp 2014-05-02 09:12:05.761146347 -0700
41@@ -633,10 +633,16 @@
42
43 bool bfd_info::get_synth_symbols()
44 {
45- extern const bfd_target bfd_elf64_powerpc_vec;
46- extern const bfd_target bfd_elf64_powerpcle_vec;
47- bool is_elf64_powerpc_target = (abfd->xvec == &bfd_elf64_powerpc_vec)
48- || (abfd->xvec == &bfd_elf64_powerpcle_vec);
49+ const char* targname = bfd_get_target(abfd);
50+ // Match elf64-powerpc and elf64-powerpc-freebsd, but not
51+ // elf64-powerpcle. elf64-powerpcle is a different ABI without
52+ // function descriptors, so we don't need the synthetic
53+ // symbols to have function code marked by a symbol.
54+ bool is_elf64_powerpc_target = (!strncmp(targname, "elf64-powerpc", 13)
55+ && (targname[13] == 0
56+ || targname[13] == '-'));
57+
58+
59
60 if (!is_elf64_powerpc_target)
61 return false;
62Index: oprofile-0.9.9/m4/binutils.m4
63===================================================================
64--- oprofile-0.9.9.orig/m4/binutils.m4 2013-07-29 08:55:07.000000000 -0700
65+++ oprofile-0.9.9/m4/binutils.m4 2014-05-02 09:07:32.471148147 -0700
66@@ -22,32 +22,32 @@
67
68 AC_LANG_PUSH(C)
69 # Determine if bfd_get_synthetic_symtab macro is available
70-OS="`uname`"
71-if test "$OS" = "Linux"; then
72- AC_MSG_CHECKING([whether bfd_get_synthetic_symtab() exists in BFD library])
73- rm -f test-for-synth
74- AC_LANG_CONFTEST(
75- [AC_LANG_PROGRAM([[#include <bfd.h>]],
76- [[asymbol * synthsyms; bfd * ibfd = 0;
77- long synth_count = bfd_get_synthetic_symtab(ibfd, 0, 0, 0, 0, &synthsyms);
78- extern const bfd_target bfd_elf64_powerpc_vec;
79- extern const bfd_target bfd_elf64_powerpcle_vec;
80- char * ppc_name = bfd_elf64_powerpc_vec.name;
81- char * ppcle_name = bfd_elf64_powerpcle_vec.name;
82- printf("%s %s\n", ppc_name, ppcle_name);]])
83- ])
84- $CC conftest.$ac_ext $CFLAGS $LDFLAGS $LIBS -o test-for-synth > /dev/null 2>&1
85- if test -f test-for-synth; then
86- echo "yes"
87- SYNTHESIZE_SYMBOLS='1'
88- else
89- echo "no"
90- SYNTHESIZE_SYMBOLS='0'
91- fi
92- AC_DEFINE_UNQUOTED(SYNTHESIZE_SYMBOLS, $SYNTHESIZE_SYMBOLS, [Synthesize special symbols when needed])
93- rm -f test-for-synth*
94+AC_MSG_CHECKING([whether bfd_get_synthetic_symtab() exists in BFD library])
95+AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include <bfd.h>
96+ ]],
97+ [[asymbol * synthsyms; bfd * ibfd = 0;
98+ long synth_count = bfd_get_synthetic_symtab(ibfd, 0, 0, 0, 0, &synthsyms);
99+ extern const bfd_target powerpc_elf64_vec;
100+ char *ppc_name = powerpc_elf64_vec.name;
101+ printf("%s\n", ppc_name);
102+ ]])],
103+ [AC_MSG_RESULT([yes])
104+ SYNTHESIZE_SYMBOLS=2],
105+ [AC_LINK_IFELSE([AC_LANG_PROGRAM([[#include <bfd.h>
106+ ]],
107+ [[asymbol * synthsyms; bfd * ibfd = 0;
108+ long synth_count = bfd_get_synthetic_symtab(ibfd, 0, 0, 0, 0, &synthsyms);
109+ extern const bfd_target bfd_elf64_powerpc_vec;
110+ char *ppc_name = bfd_elf64_powerpc_vec.name;
111+ printf("%s\n", ppc_name);
112+ ]])],
113+ [AC_MSG_RESULT([yes])
114+ SYNTHESIZE_SYMBOLS=1],
115+ [AC_MSG_RESULT([no])
116+ SYNTHESIZE_SYMBOLS=0])
117+ ])
118+AC_DEFINE_UNQUOTED(SYNTHESIZE_SYMBOLS, $SYNTHESIZE_SYMBOLS, [Synthesize special symbols when needed])
119
120-fi
121 AC_LANG_POP(C)
122 ]
123 )
diff --git a/meta/recipes-kernel/oprofile/oprofile/0002-Add-freescale-e6500-support.patch b/meta/recipes-kernel/oprofile/oprofile/0002-Add-freescale-e6500-support.patch
deleted file mode 100644
index 9b2ae042c6..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile/0002-Add-freescale-e6500-support.patch
+++ /dev/null
@@ -1,364 +0,0 @@
1From b91794fd855177946719b34ea5cd3822c7993caa Mon Sep 17 00:00:00 2001
2From: Ting Liu <b28495@freescale.com>
3Date: Thu, 5 Sep 2013 07:45:52 -0500
4Subject: [PATCH 2/2] Add freescale e6500 support
5
6Upstream-Status: Backport
7
8Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com>
9Signed-off-by: Ting Liu <b28495@freescale.com>
10---
11 events/Makefile.am | 1 +
12 events/ppc/e6500/events | 266 +++++++++++++++++++++++++++++++++++++++++++
13 events/ppc/e6500/unit_masks | 4 +
14 libop/op_cpu_type.c | 1 +
15 libop/op_cpu_type.h | 1 +
16 libop/op_events.c | 1 +
17 utils/ophelp.c | 1 +
18 7 files changed, 275 insertions(+), 0 deletions(-)
19 create mode 100644 events/ppc/e6500/events
20 create mode 100644 events/ppc/e6500/unit_masks
21
22diff --git a/events/Makefile.am b/events/Makefile.am
23index e496f98..d91d44b 100644
24--- a/events/Makefile.am
25+++ b/events/Makefile.am
26@@ -77,6 +77,7 @@ event_files = \
27 ppc/e500/events ppc/e500/unit_masks \
28 ppc/e500v2/events ppc/e500v2/unit_masks \
29 ppc/e500mc/events ppc/e500mc/unit_masks \
30+ ppc/e6500/events ppc/e6500/unit_masks \
31 ppc/e300/events ppc/e300/unit_masks \
32 tile/tile64/events tile/tile64/unit_masks \
33 tile/tilepro/events tile/tilepro/unit_masks \
34diff --git a/events/ppc/e6500/events b/events/ppc/e6500/events
35new file mode 100644
36index 0000000..f34f82d
37--- /dev/null
38+++ b/events/ppc/e6500/events
39@@ -0,0 +1,266 @@
40+# e6500 Events
41+#
42+# Copyright (C) 2012 Freescale Semiconductor, Inc.
43+#
44+event:0x1 counters:0,1,2,3,4,5 um:zero minimum:100 name:CPU_CLK : Cycles
45+event:0x2 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
46+event:0x3 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops
47+event:0x5 counters:0,1,2,3,4,5 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
48+event:0x6 counters:0,1,2,3,4,5 um:zero minimum:500 name:TRANSITIONS_PM_EVENT : 0 to 1 transitions on the pm_event input
49+event:0x7 counters:0,1,2,3,4,5 um:zero minimum:500 name:CPU_CLK_PM_EVENT : Processor cycles that occur when the pm_event input is asserted
50+event:0x8 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
51+event:0x9 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
52+event:0xa counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
53+event:0xb counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
54+event:0xc counters:0,1,2,3,4,5 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
55+event:0xd counters:0,1,2,3,4,5 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
56+event:0xe counters:0,1,2,3,4,5 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED_NOT_BTB : Finished unconditional branches that miss the BTB
57+event:0xf counters:0,1,2,3,4,5 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
58+event:0x10 counters:0,1,2,3,4,5 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction
59+event:0x11 counters:0,1,2,3,4,5 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken
60+event:0x12 counters:0,1,2,3,4,5 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
61+event:0x13 counters:0,1,2,3,4,5 um:zero minimum:500 name:ISSUE_STALLED : Cycles the SFX/CFX issue queue is not empty but 0 instructions issued
62+event:0x14 counters:0,1,2,3,4,5 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
63+event:0x15 counters:0,1,2,3,4,5 um:zero minimum:500 name:SFX0_SCHEDULE_STALLED : Cycles SFX0 is not empty but 0 instructions scheduled
64+event:0x16 counters:0,1,2,3,4,5 um:zero minimum:500 name:SFX1_SCHEDULE_STALLED : Cycles SFX1 is not empty but 0 instructions scheduled
65+event:0x17 counters:0,1,2,3,4,5 um:zero minimum:500 name:CFX_SCHEDULE_STALLED : Cycles CFX is not empty but 0 instructions scheduled
66+event:0x18 counters:0,1,2,3,4,5 um:zero minimum:500 name:LSU_SCHEDULE_STALLED : Cycles LSU is not empty but 0 instructions scheduled
67+event:0x19 counters:0,1,2,3,4,5 um:zero minimum:500 name:BU_SCHEDULE_STALLED : Cycles BU is not empty but 0 instructions scheduled
68+event:0x1a counters:0,1,2,3,4,5 um:zero minimum:500 name:TOTAL_TRANSLATED : Total LSU micro-ops that reach the second stage of the LSU
69+event:0x1b counters:0,1,2,3,4,5 um:zero minimum:500 name:LOADS_TRANSLATED : Cacheable load micro-ops translated.1 (Does not include WT)
70+event:0x1c counters:0,1,2,3,4,5 um:zero minimum:500 name:STORES_TRANSLATED : Cacheable store micro-ops translated.1 (Does not include WT)
71+event:0x1d counters:0,1,2,3,4,5 um:zero minimum:500 name:TOUCHES_TRANSLATED : Cacheable touch instructions translated. Includes: dcbt / dcbtep dcbtst / dcbtstep icbt ct=2
72+event:0x1e counters:0,1,2,3,4,5 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)
73+event:0x1f counters:0,1,2,3,4,5 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
74+event:0x20 counters:0,1,2,3,4,5 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated
75+event:0x21 counters:0,1,2,3,4,5 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated
76+event:0x22 counters:0,1,2,3,4,5 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated.
77+event:0x23 counters:0,1,2,3,4,5 um:zero minimum:500 name:FETCH_2X4_HITS : Each fetch retrieves up to 8 instructions, but only the first 4 are required. This event increments if at least one instruction of the second 4 are actually used.
78+event:0x24 counters:0,1,2,3,4,5 um:zero minimum:500 name:FETCH_HITS_ON_PREFETCHES : Fetch hits on instruction prefetch when the data is still in the ILFB.
79+event:0x25 counters:0,1,2,3,4,5 um:zero minimum:500 name:GENERATED_FETCH_PREFETCHES : Number of prefetches generated.
80+event:0x29 counters:0,1,2,3,4,5 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.
81+event:0x2c counters:0,1,2,3,4,5 um:zero minimum:500 name:LOAD_MISS_WITH_LOAD_QUEUE_FULL : Counts number of stalls; Com:52 counts cycles stalled. Includes: cacheable loads, CI loads, loadec, larx, touches, ibll, ibsl,ibllsl
82+event:0x2d counters:0,1,2,3,4,5 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer.
83+event:0x2e counters:0,1,2,3,4,5 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full.
84+event:0x2f counters:0,1,2,3,4,5 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision.
85+event:0x30 counters:0,1,2,3,4,5 um:zero minimum:500 name:DTLB_MISS_REPLAYS : Counts number of stalls; Com:56 counts cycles stalled.
86+event:0x31 counters:0,1,2,3,4,5 um:zero minimum:500 name:DTLB_BUSY_REPLAYS : Counts number of stalls; Com:57 counts cycles stalled.
87+event:0x32 counters:0,1,2,3,4,5 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache.
88+event:0x34 counters:0,1,2,3,4,5 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full.
89+event:0x35 counters:0,1,2,3,4,5 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer.
90+event:0x36 counters:0,1,2,3,4,5 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full.
91+event:0x37 counters:0,1,2,3,4,5 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision.
92+event:0x38 counters:0,1,2,3,4,5 um:zero minimum:500 name:DTLB_MISS_CYCLES : Cycles stalled on replay condition - DTLB miss.
93+event:0x39 counters:0,1,2,3,4,5 um:zero minimum:500 name:DTLB_BUSY_CYCLES : Cycles stalled on replay condition - DTLB busy.
94+event:0x3a counters:0,1,2,3,4,5 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache.
95+event:0x3c counters:0,1,2,3,4,5 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.
96+event:0x3d counters:0,1,2,3,4,5 um:zero minimum:500 name:FETCHES : Counts fetches that write at least one instruction to the Instruction Buffer.
97+event:0x3e counters:0,1,2,3,4,5 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads
98+event:0x3f counters:0,1,2,3,4,5 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads
99+event:0x40 counters:0,1,2,3,4,5 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads
100+event:0x41 counters:0,1,2,3,4,5 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads
101+event:0x42 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt
102+event:0x43 counters:0,1,2,3,4,5 um:zero minimum:500 name:TAKEN_BRANCHES : Completed branch instructions that were taken.
103+event:0x44 counters:0,1,2,3,4,5 um:zero minimum:500 name:TAKEN_BLR : Completed blr instructions that were taken.
104+event:0x45 counters:0,1,2,3,4,5 um:zero minimum:500 name:BTB_TARGET_MISPREDICT : Number of target mispredicts (BTB).
105+event:0x46 counters:0,1,2,3,4,5 um:zero minimum:500 name:MISPREDICT_TARGET_BLR : Number of link stack mispredicts (LS).
106+event:0x47 counters:0,1,2,3,4,5 um:zero minimum:500 name:TAKEN_BTB_BUT_MISS : Number of BTB misses, but taken (BTB allocates).
107+event:0x52 counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
108+event:0x53 counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
109+event:0x54 counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
110+event:0x55 counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
111+event:0x56 counters:0,1,2,3,4,5 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
112+event:0x57 counters:0,1,2,3,4,5 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
113+event:0x58 counters:0,1,2,3,4,5 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
114+event:0x59 counters:0,1,2,3,4,5 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
115+event:0x5a counters:0,1,2,3,4,5 um:zero minimum:500 name:TBL_BIT_TRANS_PMGC0 : Counts transitions of the TBL bit selected by PMGC0[TBSEL].
116+event:0x5b counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC4_OVERFLOW : Counts the number of times PMC4[32] transitioned from 1 to 0.
117+event:0x5c counters:0,1,2,3,4,5 um:zero minimum:500 name:PMC5_OVERFLOW : Counts the number of times PMC5[32] transitioned from 1 to 0.
118+event:0x61 counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_STASH_HIT : Stash hits in L1 Data Cache.
119+event:0x63 counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_STASH_REQ : Stash requests to L1 Data Cache.
120+event:0x64 counters:0,1,2,3,4,5 um:zero minimum:500 name:TIMES_LSU_THREAD_PRIO_SWTICHED : Number of times the Load Store Unit thread priority switched based on resource collisions.
121+event:0x65 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_REQ_FPU_DENIED : Number of cycles both threads had Floating Point Unit requests and one was denied.
122+event:0x66 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_REQ_VPERM_DENIED : Number of cycles both threads had Altivec Permute requests and one was denied.
123+event:0x67 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_REQ_VGEN_DENIED : Number of cycles both threads had Altivec General requests and one was denied.
124+event:0x68 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_REQ_CFX_DENIED : Number of cycles both threads had Complex Fixed-Point Unit requests and one was denied.
125+event:0x69 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_REQ_FETCH_DENIED : Number of cycles both threads both threads made a Fetch request to the L1 Instruction Cache and one thread wins arbitration.
126+event:0x6e counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_LSU_ISSUE_STALLED : Cycles the LSU issue queue is not empty but 0 instructions issued.
127+event:0x6f counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_FPU_ISSUE_STALLED : Cycles the FPU issue queue is not empty but 0 instructions issued.
128+event:0x70 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_ALTIVEC_ISSUE_STALLED : Cycles the AltiVec issue queue is not empty but 0 instructions issued.
129+event:0x71 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_FPU_SCHEDULE_STALLED : Cycles FPU is not empty but 0 instructions scheduled.
130+event:0x72 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VPERM_SCHEDULE_STALLED : Cycles VPERM is not empty but 0 instructions scheduled.
131+event:0x73 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VGEN_SCHEDULE_STALLED : Cycles VGEN is not empty but 0 instructions scheduled.
132+event:0x74 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VPU_INSTRUCTION_WAIT_FOR_OPERA : Cycles VPU instruction waits for operands.
133+event:0x75 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VFPU_INSTRUCTION_WAIT_FOR_OPERA : Cycles VFPU instruction waits for operands.
134+event:0x76 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VSFX_INSTRUCTION_WAIT_FOR_OPERA : Cycles VSFX instruction waits for operands
135+event:0x77 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VCFX_INSTRUCTION_WAIT_FOR_OPERA : Cycles VCFX instruction waits for operands.
136+event:0x7a counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_IB_EMPT : Number of cycles the Instruction Buffer is empty
137+event:0x7b counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_IB_FULL : Number of cycles the Instruction Buffer is full enough such that fetch stops fetching.
138+event:0x7c counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_CB_EMPT : Number of cycles the Completion Buffer is empty.
139+event:0x7d counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_CB_FULL : Number of cycles the Completion Buffer is full enough such that decode stops.
140+event:0x7e counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_PRESYNC_SI_IB : Number of cycles a pre-sync serialized instruction holds in the Instruction Buffer and is not decoded.
141+event:0x7f counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_CLK_0_INSTRUCTIONS : Increments if 0 instructions (micro-ops) completed.
142+event:0x80 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_CLK_1_INSTRUCTIONS : Increments if 1 instruction (micro-op) completed.
143+event:0x80 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_CLK_2_INSTRUCTIONS : Increments if 2 instructions (micro-op) completed.
144+event:0x88 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC5S : Every valid IAC5 detection.
145+event:0x89 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC6S : Every valid IAC6 detection.
146+event:0x8a counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC7S : Every valid IAC7 detection.
147+event:0x8b counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC8S : Every valid IAC8 detection.
148+event:0x8c counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC1S : Every valid IAC1 detection.
149+event:0x8d counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC2S : Every valid IAC2 detection.
150+event:0x8e counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC3S : Every valid IAC3 detection.
151+event:0x8f counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_IAC4S : Every valid IAC4 detection.
152+event:0x90 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DAC1S : Every valid DAC1 detection.
153+event:0x91 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DAC2S : Every valid DAC2 detection.
154+event:0x94 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT0 : Detection of a write to DEVENT SPR with DVT0 set.
155+event:0x95 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT1 : Detection of a write to DEVENT SPR with DVT1 set.
156+event:0x96 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT2 : Detection of a write to DEVENT SPR with DVT2 set.
157+event:0x97 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT3 : Detection of a write to DEVENT SPR with DVT3 set.
158+event:0x98 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT4 : Detection of a write to DEVENT SPR with DVT4 set.
159+event:0x99 counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT5 : Detection of a write to DEVENT SPR with DVT5 set.
160+event:0x9a counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT6 : Detection of a write to DEVENT SPR with DVT6 set.
161+event:0x9b counters:0,1,2,3,4,5 um:zero minimum:500 name:DETECTED_DVT7 : Detection of a write to DEVENT SPR with DVT7 set.
162+event:0x9c counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_COMPLETION_STALLED : Number of completion cycles stalled due to Nexus FIFO full.
163+event:0xa1 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_FINISH : FPU finish.
164+event:0xa2 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_FPU_DIV : Counts once for every cycle of divide execution. (fdivs and fdiv).
165+event:0xa3 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_DENORM_INPUT : Counts extra cycles delay due to denormalized inputs. If there is one, this is incremented 4 times, Two operands increments it 5 times. This shows the real penalty due to denorms, not just how often they occur.
166+event:0xa4 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_DENORM_OUTPUT : FPU denorm output.
167+event:0xa5 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_FPSCR_FULL_STALL : FPU FPSCR stall.
168+event:0xa6 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_PIPE_SYNC_STALL : Synchronization-op stalls: count once for each cycle that a ��break-before�� FPU is in the RS/issue stage but cannotissue. Also count once for each cycle that an FPU op is in the RS/issue stage but cannot issue due to ��break-after��: of an FPU op currently in progress.
169+event:0xa7 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_INPUT_DATA_STALL : FPU data-ready stall: cycles in which there is an op in the RS/issue stage that cannot issue because one or more of its operands is not yet available.
170+event:0xa8 counters:0,1,2,3,4,5 um:zero minimum:500 name:FPU_INSTRUCTIONS_GEN_FLAG : FPU instruction sets FPSCR[FEX].
171+event:0xac counters:0,1,2,3,4,5 um:zero minimum:500 name:PW20_CNT : Number of times the core enters the PW20 power management state.
172+event:0xb0 counters:0,1,2,3,4,5 um:zero minimum:500 name:DECORATED_LOADS : Number of decorated loads to cache inhibited memory performed.
173+event:0xb1 counters:0,1,2,3,4,5 um:zero minimum:500 name:DECORATED_STORES : Number of decorated stores to cache inhibited memory performed.
174+event:0xb3 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_INSTRUCTIONS_SUCC : Number of successful stbcx., sthcx., stwcx., or stdcx. instructions.
175+event:0xb4 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_INSTRUCTIONS_UNSUCC : Number of unsuccessful stbcx., sthcx., stwcx., or stdcx. instructions.
176+event:0xb5 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_LSU_MICROOPS : Completed Load Store Unit micro-ops. Every micro-op that goes down the LSU pipe. Includes: GPR loads / GPR stores, FPR loads / FPR stores, VR loads / VR stores, Cache ops. Memory barriers Other LSU ops (dsn, msgsnd, mvidsplt, mviwsplt, tlbilx, tlbivax, tlbsync)
177+event:0xb6 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_GPR_LOADS : GPR load micro-ops completed. This event only counts once for misaligns. Note that lmw that causes a fault may end up double-counting micro-ops -- once for first pass, once for second pass.
178+event:0xb7 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_GPR_STORES : GPR store micro-ops completed. This event only counts once for misaligns. Note that stmw that causes a fault may end up double-counting micro-ops -- once for first pass, once for second pass.
179+event:0xb8 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_CACHEOPS : Cache ops completed. Includes: dcba / dcbal, dcbf / dcbfep, dcbi, dcblc / dcblq, dcbst / dcbstep, dcbt / dcbtep / dcbtls, dcbtst / dcbtstep / dcbtstls, dcbz / dcbzep / dcbzl / dcbzlep, icbi / icbiep, icblc / icblq., icbt / icbtls
180+event:0xb9 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_MEM_BARRIERS : Memory barriers completed. Includes: msync (sync, lwsync, elemental barriers) mbar (eieio) miso.
181+event:0xba counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_SFX_MICROOPS : SFX micro-ops completed.
182+event:0xbb counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_SINCLK_SFX_MICROOPS : SFX single-cycle micro-ops completed.
183+event:0xbc counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_DBLCLK_SFX_MICROOPS : SFX double-cycle micro-ops completed.
184+event:0xbe counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_CFX_INSTRUCTIONS : CFX instructions completed.
185+event:0xbf counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_SFX_CFX_INSTRUCTIONS : SFX or CFX instructions completed.
186+event:0xc0 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPU_INSTRUCTIONS : FPU instructions completed.
187+event:0xc1 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPR_MICROOPS_LOADS : FPR load micro-ops completed.
188+event:0xc2 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPR_MICROOPS_STORES : FPR store micro-ops completed.
189+event:0xc3 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPR_MICROOPS_LOADS_STORES : FPR load and store micro-ops completed.
190+event:0xc4 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPR_SINPRECISE_LOADS_STORES : FPR single-precision load and store micro-ops completed.
191+event:0xc5 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_FPR_DBLPRECISE_LOADS_STORES : FPR double-precision load and store micro-ops completed.
192+event:0xc6 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_ALTIVEC_INSTRUCTIONS : AltiVec instructions completed. (non-LSU).
193+event:0xc7 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_ALTIVEC_VSFX_INSTRUCTIONS : AltiVec VSFX instructions completed.
194+event:0xc8 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_ALTIVEC_VCFX_INSTRUCTIONS : AltiVec VCFX instructions completed.
195+event:0xc9 counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_ALTIVEC_VPU_INSTRUCTIONS : AltiVec VPU instructions completed.
196+event:0xca counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_ALTIVEC_VFPU_INSTRUCTIONS : AltiVec VFPU instructions completed.
197+event:0xcb counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_VR_LOADS_MICROOPS : VR load micro-ops completed.
198+event:0xcc counters:0,1,2,3,4,5 um:zero minimum:500 name:COMPLETED_VR_STORES_MICROOPS : VR store micro-ops completed.
199+event:0xcd counters:0,1,2,3,4,5 um:zero minimum:500 name:VSCR_SAT_SET : Number of times the saturate bit flips from 0 to 1.
200+event:0xd2 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_SFX0_IDLE : Cycles Simple Fixed Point Unit 0 is idle.
201+event:0xd3 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_SFX1_IDLE : Cycles Simple Fixed Point Unit 1 is idle.
202+event:0xd4 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_CFX_IDLE : Cycles Complex Fixed Point Unit is idle.
203+event:0xd5 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_LSU_IDLE : Cycles Load Store Unit is idle.
204+event:0xd6 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_BU_IDLE : Cycles Branch Unit is idle.
205+event:0xd7 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_FPU_IDLE : Cycles Floating Point Unit is idle.
206+event:0xd8 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VPU_IDLE : Cycles AltiVec Permute Unit is idle.
207+event:0xd9 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VFPU_IDLE : Cycles AltiVec Floating Point Unit is idle.
208+event:0xda counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VSFX_IDLE : Cycles AltiVec Simple Fixed Point Unit is idle.
209+event:0xdb counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_VCFX_IDLE : Cycles AltiVec Complex Fixed Point Unit is idle.
210+event:0xdd counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_CACHE_MISSES : Data L1 cache misses. (Includes load, store, cache ops).
211+event:0xde counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_CACHE_LOAD_MISSES : Data L1 cache load misses.
212+event:0xdf counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_CACHE_STORE_MISSES : Data L1 cache store misses.
213+event:0xe0 counters:0,1,2,3,4,5 um:zero minimum:500 name:LMQ_ALLOCATED_LOADS : Loads that allocate into Load Miss Queue. (Data L1 cache misses, but may not be to different cache lines).
214+event:0xe1 counters:0,1,2,3,4,5 um:zero minimum:500 name:LOAD_THREAD_MISS_COLLISION : Number of times that this thread��s load hits a line that is valid for the other thread but not this thread.
215+event:0xe2 counters:0,1,2,3,4,5 um:zero minimum:500 name:INTERTHREAD_STATUS_ARRAY_COLLISION : Number of times that two threads collide on status array access.
216+event:0xe3 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_ALLOC : Number of Store Gather Buffer allocates.
217+event:0xe4 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_GATHERS : Number of Store Gather Buffer gathers.
218+event:0xe5 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_OVERFLOWS : Number of Store Gather Buffer overflows. (Causes SGB full condition when additional store request is made).
219+event:0xe6 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_PROMOTIONS : Number of Store Gather Buffer promotions.
220+event:0xe7 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_INORDER_PROMOTIONS : Number of Store Gather Buffer in-order promotions. (Also includes oldest-entry timeout condition).
221+event:0xe8 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_OUTOFORDER_PROMOTIONS : Number of Store Gather Buffer out-of-order promotions.
222+event:0xe9 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_HP_PROMOTIONS : Number of Store Gather Buffer high-priority promotions. (Load hits on pending store).
223+event:0xea counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_MISO_PROMOTIONS : Number of Store Gather Buffer miso promotions. promotions. (Load hits on pending store).
224+event:0xeb counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_WATERMARK_PROMOTIONS : Number of Store Gather Buffer watermark promotions.
225+event:0xec counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_SGB_OVERFLOW_PROMOTIONS : Number of Store Gather Buffer overflow promotions.
226+event:0xed counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_DLAQ_FULL : Number of cycles the DLink Age Queue is full.
227+event:0xee counters:0,1,2,3,4,5 um:zero minimum:500 name:TIMES_DLAQ_FULL : Number of times the DLink Age Queue is full.
228+event:0xef counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_LRSAQ_FULL : Number of cycles the Load Reservation Set Age Queue is full.
229+event:0xf0 counters:0,1,2,3,4,5 um:zero minimum:500 name:TIMES_LRSAQ_FULL : Number of times the Load Reservation Set Age Queue is full.
230+event:0xf1 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_FWDAQ_FULL : Number of cycles the Forward Age Queue is full.
231+event:0xf2 counters:0,1,2,3,4,5 um:zero minimum:500 name:TIMES_FWDAQ_FULL : Number of times the Forward Age Queue is full.
232+event:0xf3 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_TIMES : Number of times a Store Queue collision is forwardable. The following cases are not forwardable: store address + size does not contain the load, cache-inhibited store, denormalized, floating point store, stcx, guarded load.
233+event:0xf4 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_TIMES_DATA_RDY : Number of times a Store Queue collision is forwardable and is ready with data to forward.
234+event:0xf5 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_TIMES_DATA_NORDY : Number of times a Store Queue collision is forwardable but is not ready with data to forward.
235+event:0xf6 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_NOFWD_STQ_COLLISION_TIMES : Number of times a Store Queue collision is not forwardable and must wait until the store leaves the Store Queue.
236+event:0xf7 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_CLK : Number of cycles a Store Queue collision is forwardable. (Number of cycles from the detection of a forwardable Store Queue entry until the load is replayed in stg1).
237+event:0xf8 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_CLK_DATA_RDY : Number of cycles a Store Queue collision is forwardable and is ready with data to forward. (Number of cycles from the detection of a forwardable Store Queue entry with valid data until the load is replayed in stg1).
238+event:0xf9 counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FWD_STQ_COLLISION_CLK_DATA_NORDY : Number of cycles a Store Queue collision is forwardable but is not ready with data to forward. (Number of cycles from the detection of a forwardable Store Queue entry without valid data until the load is replayed in stg1).
239+event:0xfa counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_NOFWD_STQ_COLLISION_CLK : Number of cycles a Store Queue collision is not forwardable and has to wait until the store leaves the Store Queue. (Number of cycles from the detection of a non-forwardable Store Queue entry until the load is replayed in stg1).
240+event:0xfb counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_FALSE_EA_COLLISION : Number of times the lower 12-bits of EA matched but the upper bits did not, leading to a false load-on-store replay. Cycle penalty is 4x the number of times.
241+event:0xfc counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_LSO_BUS_COLLISION : Number of LS0 result bus collisions. Cycle penalty is 3x this measurement.
242+event:0xfd counters:0,1,2,3,4,5 um:zero minimum:500 name:NUM_INTERTHREAD_DBLWORKD_BANK_COLLISION : Number of inter-thread double-word bank collisions. Measures when both threads attempt to access the same double-word bank. Cycle penalty is 3x this measurement.
243+event:0xfe counters:0,1,2,3,4,5 um:zero minimum:500 name:L1_CACHE_IM : Instruction L1 cache demand fetch misses. (Includes icbtls. Does not include prefetch).
244+event:0x100 counters:0,1,2,3,4,5 um:zero minimum:500 name:IMMU_MISSES : Counts misses in the level 1 Instruction MMU.
245+event:0x101 counters:0,1,2,3,4,5 um:zero minimum:500 name:IMMU_TLB4K_HITS : Counts hits in the level 1 Instruction MMU TLB-4K.
246+event:0x102 counters:0,1,2,3,4,5 um:zero minimum:500 name:IMMU_VSP_HITS : Counts hits in the level 1 Instruction MMU VSP.
247+event:0x103 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_IMMU_HW_TABLEWALK : Counts IMMU cycles spent in hardware tablewalk. This represents the cycles from the point where the L2 MMU miss occurs to when the page table walk completes with a valid translation or exception.
248+event:0x104 counters:0,1,2,3,4,5 um:zero minimum:500 name:DMMU_MISSES : Counts misses in the level 1 Data MMU. (Does not count replayed operations).
249+event:0x105 counters:0,1,2,3,4,5 um:zero minimum:500 name:DMMU_TLB4K_HITS : Counts hits in the level 1 Data MMU TLB-4K. (Does not count replayed operations).
250+event:0x106 counters:0,1,2,3,4,5 um:zero minimum:500 name:DMMU_VSP_HITS : Counts hits in the level 1 Data MMU VSP. (Does not count replayed operations).
251+event:0x107 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_DMMU_HW_TABLEWALK : Counts DMMU cycles spent in hardware tablewalk. This represents the cycles from the point where the L2 MMU miss occurs to when the page table walk completes with a valid translation or exception.
252+event:0x108 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_MISSES : Counts level 2 MMU misses. (Does not count misses that occur due to dcbt / dcbtst / dcba / dcbal instructions that fail translation and are no-oped. Does not count misses in L2MMU-VSP when looking up an indirect entry).
253+event:0x109 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_4K_HITS : Counts level 2 MMU hits in L2MMU-4K.
254+event:0x10a counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_VSP_HITS : Counts level 2 MMU hits in L2MMU-VSP. (Does not count indirect lookups).
255+event:0x10b counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_INDIRECT_MISSES : Counts level 2 MMU indirect misses. This represents indirect entry lookups that do not have a matching indirect entry.
256+event:0x10c counters:0,1,2,3,4,5 um:zero minimum:500 name:L2MMU_INDIRECT_VALID_MISSES : Counts level 2 MMU indirect valid misses. This occurts when the indirect entry is valid, but the corresponding PTE[V] = 0 or the premissions in the PTE are not sufficient for the requested access.
257+event:0x10d counters:0,1,2,3,4,5 um:zero minimum:500 name:LRAT_MISSES : Counts Logical to Real Address Translation misses. This includes LRAT misses from tlbwe instructions or from page table translations.
258+event:0x110 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_LMQ_LOSE_DLINK_DUE_SGB : Cycles the Load Miss Queue loses DLINK arbitration due to the Store Gather Buffer.
259+event:0x111 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_SGB_LOSE_DLINK_DUE_LMQ : Cycles the Store Gather Buffer loses DLINK arbitration due to the Load Miss Queue.
260+event:0x112 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_THREAD_LOSE_DLINK_DUE_OTHER_THREAD : Cycles thread loses DLINK arbitration due to other thread: Cycles thread loses DLINK arbitration due to other thread.
261+event:0x116 counters:0,1,2,3,4,5 um:zero minimum:500 name:DECODE_MASK_VALUE : One mask/value pair that allows instructions to be counted in Decode.
262+event:0x1bb counters:0,1,2,3,4,5 um:zero minimum:500 name:SHR_L2_DLINK_REQ : Number of DLINK requests made from core to Shared L2.
263+event:0x1bc counters:0,1,2,3,4,5 um:zero minimum:500 name:SHR_L2_ILINK_REQ : Number of ILINK requests made from core to Shared L2. (Includes instruction fetches and L2MMU hardware tablewalk requests).
264+event:0x1bd counters:0,1,2,3,4,5 um:zero minimum:500 name:SHR_L2_RLINK_REQ : Number of RLINK requests made from Shared L2 to core. (back invalidates, stashes, barriers).
265+event:0x1be counters:0,1,2,3,4,5 um:zero minimum:500 name:SHR_L2_BLINK_REQ : Number of BLINK requests made from Shared L2 to core. (back invalidates, stashes, barriers).
266+event:0x1bf counters:0,1,2,3,4,5 um:zero minimum:500 name:SHR_L2_CLINK_REQ : Number of CLINK requests made from Shared L2 to core. (back invalidates, stashes, barriers).
267+event:0x1c8 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_HITS : Number of L2 Cache hits. Counts 0, 1, 2, 3, or 4 per cycle.
268+event:0x1c9 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_MISSES : Number of L2 Cache hits. Counts 0, 1, 2, 3, or 4 per cycle.
269+event:0x1ca counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DEMAND_ACCESS : Number of L2 Cache demand accesses. Counts 0, 1, 2, 3, or 4 per cycle.
270+event:0x1cb counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_ACCESSES : Number of L2 Cache accesses from all sources (demand, reload, snoop, etc). Counts 0, 1, 2, 3, or 4 per cycle.
271+event:0x1cc counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_STORE_ALLOCATE : Number of L2 Cache store allocates. Counts 0, 1, 2, 3, or 4 per cycle.
272+event:0x1cd counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_INSTRUCTIONS_ACCESS : Number of L2 Cache instruction accesses. Counts 0, 1, 2, 3, or 4 per cycle.
273+event:0x1ce counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DATA_ACCESS : Number of L2 Cache data accesses. Counts 0, 1, 2, 3, or 4 per cycle.
274+event:0x1cf counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_INSTRUCTIONS_MISSES : Number of L2 Cache instruction misses. Counts 0, 1, 2, 3, or 4 per cycle.
275+event:0x1d0 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DATA_MISSES : Number of L2 Cache data misses. Counts 0, 1, 2, 3, or 4 per cycle.
276+event:0x1d1 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_HITS_PER_THREAD : Number of times this core/thread hits in the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
277+event:0x1d2 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_MISSES_PER_THREAD : Number of times this core/thread misses in the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
278+event:0x1d3 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DEMAND_ACCESS_PER_THREAD : Number of times this core/thread makes a demand access to the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
279+event:0x1d4 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_STORE_ALLOC_PER_THREAD : Number of times a store from this core/thread allocates in the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
280+event:0x1d5 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_INSTRUCTIONS_ACCESS_PER_THREAD : Number of times an instruction from this core/thread accesses the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
281+event:0x1d6 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DATA_ACCESS_PER_THREAD : Number of times a data operation from this core/thread accesses the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
282+event:0x1d7 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_INSTRUCTION_MISSES_PER_THREAD : Number of times an instruction from this core/thread misses in the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
283+event:0x1d8 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_DATA_MISSES_PER_THREAD : Number of times a data operation from this core/thread misses in the L2 Cache. Counts 0, 1, 2, 3, or 4 per cycle.
284+event:0x1d9 counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_RELOAD_FROM_CORENET : Number of L2 Cache reloads from CoreNet. Counts 0, 1, 2, 3, or 4 per cycle.
285+event:0x1da counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_IN_STASH_REQ : Number of incoming L2 Cache stash requests. Counts 0, 1, 2, 3, or 4 per cycle.
286+event:0x1db counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_STASH_REQ_DOWNGRD_TO_SNOOPS : Number of incoming L2 Cache stash requests downgraded to snoops. Counts 0, 1, 2, 3, or 4 per cycle.
287+event:0x1dc counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_SNOOPS_HITS : Number of L2 Cache snoop hits. Counts 0, 1, 2, 3, or 4 per cycle.
288+event:0x1dd counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_SNOOPS_MINT : Number of L2 Cache snoops causing MINT.
289+event:0x1de counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_SNOOPS_SINT : Number of L2 Cache snoops causing SINT.
290+event:0x1df counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_SNOOPS_PUSHES : Number of L2 Cache snoop pushes.
291+event:0x1e0 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_BIB_STALL : Stall for Back Invalidate Buffer entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
292+event:0x1e2 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_RLT_STALL : Stall for Reload Table entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
293+event:0x1e4 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_RLFQ_STALL : Stall for Reload Fold Queue entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
294+event:0x1e6 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_DTQ_STALL : Stall for Data Transaction Queue entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
295+event:0x1e8 counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_COB_STALL : Stall for Castout Buffer entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
296+event:0x1ea counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_WDB_STALL : Stall for Write Data Buffer entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
297+event:0x1ec counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_RLDB_STALL : Stall for Reload Data Buffer entry (cycles). Counts 0, 1, 2, 3, or 4 per cycle.
298+event:0x1ee counters:0,1,2,3,4,5 um:zero minimum:500 name:CLK_SNPQ_STALL : Stall for Snoop Queue entry (cycles).
299+event:0x1fa counters:0,1,2,3,4,5 um:zero minimum:500 name:BIU_MASTER_REQ : Master transaction starts. (Number of AOut sent to CoreNet).
300+event:0x1fb counters:0,1,2,3,4,5 um:zero minimum:500 name:BIU_MASTER_GLOBAL_REQ : Master transaction starts that are global. (Number of AOut with M=1 sent to CoreNet).
301+event:0x1fc counters:0,1,2,3,4,5 um:zero minimum:500 name:BIU_MASTER_DATA_SIDE_REQ : Master transaction starts that are global. (Number of AOut with M=1 sent to CoreNet).
302+event:0x1fd counters:0,1,2,3,4,5 um:zero minimum:500 name:BIU_MASTER_INSTRUCTION_SIDE_REQ : Master instruction-side transaction starts. (Number of I-side AOut sent to CoreNet).
303+event:0x1fe counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_STASH_REQ : Stash request on AIn matches stash IDs for core or L2.
304+event:0x1ff counters:0,1,2,3,4,5 um:zero minimum:500 name:L2_SNOOP_REQ : Externally generated snoop requests. (Number of AIn from CoreNet not from self).
305+
306diff --git a/events/ppc/e6500/unit_masks b/events/ppc/e6500/unit_masks
307new file mode 100644
308index 0000000..b7e7a23
309--- /dev/null
310+++ b/events/ppc/e6500/unit_masks
311@@ -0,0 +1,4 @@
312+# e6500 possible unit masks
313+#
314+name:zero type:mandatory default:0x0
315+ 0x0 no unit mask
316diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c
317index 7d50a2d..badb7ba 100644
318--- a/libop/op_cpu_type.c
319+++ b/libop/op_cpu_type.c
320@@ -126,6 +126,7 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
321 { "IBM Power Architected Events V1", "ppc64/architected_events_v1", CPU_PPC64_ARCH_V1, 6 },
322 { "ppc64 POWER8", "ppc64/power8", CPU_PPC64_POWER8, 6 },
323 { "e500mc", "ppc/e500mc", CPU_PPC_E500MC, 4 },
324+ { "e6500", "ppc/e6500", CPU_PPC_E6500, 6 },
325 };
326
327 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
328diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h
329index 10f000b..934fe9e 100644
330--- a/libop/op_cpu_type.h
331+++ b/libop/op_cpu_type.h
332@@ -106,6 +106,7 @@ typedef enum {
333 CPU_PPC64_ARCH_V1, /** < IBM Power architected events version 1 */
334 CPU_PPC64_POWER8, /**< ppc64 POWER8 family */
335 CPU_PPC_E500MC, /**< e500mc */
336+ CPU_PPC_E6500, /**< e6500 */
337 MAX_CPU_TYPE
338 } op_cpu;
339
340diff --git a/libop/op_events.c b/libop/op_events.c
341index 638dc5c..9d2aa5e 100644
342--- a/libop/op_events.c
343+++ b/libop/op_events.c
344@@ -1309,6 +1309,7 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
345 case CPU_PPC_E500:
346 case CPU_PPC_E500_2:
347 case CPU_PPC_E500MC:
348+ case CPU_PPC_E6500:
349 case CPU_PPC_E300:
350 descr->name = "CPU_CLK";
351 break;
352diff --git a/utils/ophelp.c b/utils/ophelp.c
353index 0647360..3b2896a 100644
354--- a/utils/ophelp.c
355+++ b/utils/ophelp.c
356@@ -754,6 +754,7 @@ int main(int argc, char const * argv[])
357 case CPU_PPC_E500:
358 case CPU_PPC_E500_2:
359 case CPU_PPC_E500MC:
360+ case CPU_PPC_E6500:
361 event_doc =
362 "See PowerPC e500 Core Complex Reference Manual\n"
363 "Chapter 7: Performance Monitor\n"
364--
diff --git a/meta/recipes-kernel/oprofile/oprofile/filemode-fix.patch b/meta/recipes-kernel/oprofile/oprofile/filemode-fix.patch
new file mode 100644
index 0000000000..f7ebe24691
--- /dev/null
+++ b/meta/recipes-kernel/oprofile/oprofile/filemode-fix.patch
@@ -0,0 +1,41 @@
1With security_flags.inc:
2
3| In file included from /media/build1/poky/build/tmp/sysroots/qemumips/usr/include/fcntl.h:302:0,
4| from opjitconv.c:25:
5| In function 'open',
6| inlined from 'copy_dumpfile' at opjitconv.c:219:6:
7| /media/build1/poky/build/tmp/sysroots/qemumips/usr/include/bits/fcntl2.h:50:4: error: call to '__open_missing_mode' declared with attribute error: open with O_CREAT in second argument needs 3 arguments
8| __open_missing_mode ();
9| ^
10| Makefile:440: recipe for target 'opjitconv.o' failed
11
12Why does this only happen on mips? mips has:
13
14O_CREAT = 0x100
15and
16S_IRUSR = 0400
17
18and these (in hex and otcal) are equivalent. Most other platforms
19have O_CREAT = 0100.
20
21http://sourceforge.net/p/oprofile/oprofile/ci/4598ca73b0a367ca46d4a2843261e20e1896773b
22
23The file should not be created, only opened if its present, therefore use O_RDONLY instead.
24
25RP 2014/11/6
26
27Upstream-Status: Backport
28
29Index: oprofile-1.0.0/opjitconv/opjitconv.c
30===================================================================
31--- oprofile-1.0.0.orig/opjitconv/opjitconv.c 2014-09-12 14:39:47.000000000 +0000
32+++ oprofile-1.0.0/opjitconv/opjitconv.c 2014-11-06 13:14:25.941639003 +0000
33@@ -216,7 +216,7 @@
34 int file_locked = 0;
35 unsigned int usecs_waited = 0;
36 int rc = OP_JIT_CONV_OK;
37- int fd = open(dumpfile, S_IRUSR);
38+ int fd = open(dumpfile, O_RDONLY);
39 if (fd < 0) {
40 perror("opjitconv failed to open JIT dumpfile");
41 return OP_JIT_CONV_FAIL;
diff --git a/meta/recipes-kernel/oprofile/oprofile/opstart.patch b/meta/recipes-kernel/oprofile/oprofile/opstart.patch
deleted file mode 100644
index 8696f4ef4d..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile/opstart.patch
+++ /dev/null
@@ -1,245 +0,0 @@
1Upstream-Status: Pending
2
3The patch gives a low overhead way of starting/stopping oprofile which
4doesn't involve script exection.
5
6(written by RP in OpenedHand days)
7
8diff --git a/utils/Makefile.am b/utils/Makefile.am
9index d34b060..dff15f9 100644
10--- oprofile.orig/utils/Makefile.am
11+++ oprofile/utils/Makefile.am
12@@ -7,7 +7,7 @@ AM_LDFLAGS = @OP_LDFLAGS@
13
14 LIBS=@POPT_LIBS@ @LIBERTY_LIBS@
15
16-bin_PROGRAMS = ophelp op-check-perfevents
17+bin_PROGRAMS = ophelp op-check-perfevents opstart
18 dist_bin_SCRIPTS = opcontrol
19
20 op_check_perfevents_SOURCES = op_perf_events_checker.c
21@@ -15,3 +15,10 @@ op_check_perfevents_CPPFLAGS = ${AM_CFLAGS} @PERF_EVENT_FLAGS@
22
23 ophelp_SOURCES = ophelp.c
24 ophelp_LDADD = ../libop/libop.a ../libutil/libutil.a
25+
26+opstart_SOURCES = opstart.c
27+
28+install-exec-local:
29+ cd $(DESTDIR)/$(bindir) && \
30+ rm -f opstop && \
31+ $(LN_S) opstart opstop
32Index: oprofile/utils/opstart.c
33===================================================================
34--- /dev/null 1970-01-01 00:00:00.000000000 +0000
35+++ oprofile/utils/opstart.c 2008-07-02 15:14:07.000000000 +0100
36@@ -0,0 +1,110 @@
37+/**
38+ * @file opstart.c
39+ * Start/Stop oprofile
40+ *
41+ * @remark Copyright 2007 Openedhand Ltd.
42+ * @remark Read the file COPYING
43+ *
44+ * @author Richard Purdie
45+ */
46+
47+#include <signal.h>
48+#include <stdio.h>
49+#include <stdlib.h>
50+#include <string.h>
51+#include <unistd.h>
52+#include <sys/types.h>
53+#include <sys/stat.h>
54+
55+int main(const int argc, const char* argv[])
56+{
57+ const char *enable = "/dev/oprofile/enable";
58+ const char *lockfile;
59+ unsigned long dpid;
60+ struct stat sbuf;
61+ FILE *lfile, *efile;
62+ int sig, enb, err;
63+
64+ if (argc >= 2) {
65+ printf("Error: Invalid options.\n");
66+ return 1;
67+ }
68+
69+ lockfile = getenv("LOCK_FILE");
70+ if (!lockfile)
71+ lockfile = "/var/lib/oprofile/lock";
72+
73+ /* Add SESSION_DIR support? */
74+
75+ if (geteuid()) {
76+ printf("Error: This program must be run as root.\n");
77+ return 1;
78+ }
79+
80+ if (stat(enable, &sbuf)) {
81+ printf("Error: Could not find /dev/oprofile/enable, the"
82+ " kernel module probably isn't loaded.\n");
83+ printf("This binary only works with 2.6 kernels and oprofile"
84+ " must have been initialised with 'opcontrol --start-daemon'.\n");
85+ return 1;
86+ }
87+
88+ if (stat(lockfile, &sbuf)) {
89+ printf("Error: Could not find lockfile %s.\n", lockfile);
90+ printf("The oprofile daemon must be running (oprofile must"
91+ " have been initialised with 'opcontrol --start-daemon').\n");
92+ return 1;
93+ }
94+
95+ lfile = fopen(lockfile, "r");
96+ if (!lfile) {
97+ printf("Error opening lockfile %s.\n", lockfile);
98+ return 1;
99+ }
100+
101+ err = fscanf(lfile, "%lud", (unsigned long *) &dpid);
102+ if (err != 1) {
103+ printf("Error reading pid from lockfile %s.\n", lockfile);
104+ return 1;
105+ }
106+ fclose(lfile);
107+
108+ efile = fopen(enable, "r");
109+ if (!efile) {
110+ printf("Error opening %s.\n", enable);
111+ return 1;
112+ }
113+
114+ if (strstr(argv[0], "opstart")) {
115+ printf("Starting Profiler\n");
116+ sig = SIGUSR1;
117+ enb = 1;
118+ } else if (strstr(argv[0], "opstop")) {
119+ printf("Stopping Oprofile.\n");
120+ printf("You need to run 'opcontrol --dump' when the session"
121+ " is finished.\n");
122+ sig = SIGUSR2;
123+ enb = 0;
124+ } else {
125+ printf("Error: Please call as 'opstart' or 'opstop'\n");
126+ return 1;
127+ }
128+
129+ err = kill(dpid, 0);
130+ if (err) {
131+ printf("Error sending signal to oprofiled. Stale lockfile"
132+ " (%s) ?\n", lockfile);
133+ return 1;
134+ }
135+
136+ fprintf(efile, "%d\n", enb);
137+ err = kill(dpid, sig);
138+ if (err) {
139+ printf("Error sending signal to oprofiled. Stale lockfile"
140+ " (%s) ?\n", lockfile);
141+ return 1;
142+ }
143+
144+ return 0;
145+}
146+
147Index: oprofile/configure.ac
148===================================================================
149--- oprofile.orig/configure.ac 2008-07-02 15:13:58.000000000 +0100
150+++ oprofile/configure.ac 2008-07-02 15:17:37.000000000 +0100
151@@ -16,6 +16,7 @@
152 AM_CONFIG_HEADER(config.h)
153
154 AC_PROG_RANLIB
155+AC_PROG_LN_S
156 AC_PROG_LIBTOOL
157
158 dnl for the man page
159@@ -241,6 +242,8 @@
160 doc/xsl/catalog-1.xml \
161 doc/oprofile.1 \
162 doc/opcontrol.1 \
163+ doc/opstart.1 \
164+ doc/opstop.1 \
165 doc/ophelp.1 \
166 doc/opreport.1 \
167 doc/opannotate.1 \
168Index: oprofile/doc/Makefile.am
169===================================================================
170--- oprofile.orig/doc/Makefile.am 2008-07-02 15:13:59.000000000 +0100
171+++ oprofile/doc/Makefile.am 2008-07-02 15:14:07.000000000 +0100
172@@ -11,6 +11,8 @@
173 man_MANS = \
174 oprofile.1 \
175 opcontrol.1 \
176+ opstart.1 \
177+ opstop.1 \
178 opreport.1 \
179 opannotate.1 \
180 opgprof.1 \
181Index: oprofile/doc/opstart.1.in
182===================================================================
183--- /dev/null 1970-01-01 00:00:00.000000000 +0000
184+++ oprofile/doc/opstart.1.in 2008-07-02 15:14:07.000000000 +0100
185@@ -0,0 +1,27 @@
186+.TH OPSTART 1 "@DATE@" "oprofile @VERSION@"
187+.UC 4
188+.SH NAME
189+opstart \- start OProfile profiling
190+.SH SYNOPSIS
191+.br
192+.B opstart
193+.SH DESCRIPTION
194+.B opstart
195+is a simple optimised command to start profiling with 2.6 Linux kernels.
196+OProfile should have already been initialised by calling "opcontrol --start-daemon".
197+
198+.SH ENVIRONMENT
199+No special environment variables are recognised by opstart.
200+
201+.SH FILES
202+.TP
203+.I /var/lib/oprofile/samples/
204+The location of the generated sample files.
205+
206+.SH VERSION
207+.TP
208+This man page is current for @PACKAGE@-@VERSION@.
209+
210+.SH SEE ALSO
211+.BR @OP_DOCDIR@,
212+.BR oprofile(1)
213Index: oprofile/doc/opstop.1.in
214===================================================================
215--- /dev/null 1970-01-01 00:00:00.000000000 +0000
216+++ oprofile/doc/opstop.1.in 2008-07-02 15:14:07.000000000 +0100
217@@ -0,0 +1,28 @@
218+.TH OPSTOP 1 "@DATE@" "oprofile @VERSION@"
219+.UC 4
220+.SH NAME
221+opstop \- stop OProfile profiling
222+.SH SYNOPSIS
223+.br
224+.B opstop
225+.SH DESCRIPTION
226+.B opstop
227+is a simple optimsed command to stop profiling with 2.6 Linux kernels.
228+You need to run "opcontrol --dump" before being able to view a profile
229+with opreport.
230+
231+.SH ENVIRONMENT
232+No special environment variables are recognised by opstop.
233+
234+.SH FILES
235+.TP
236+.I /var/lib/oprofile/samples/
237+The location of the generated sample files.
238+
239+.SH VERSION
240+.TP
241+This man page is current for @PACKAGE@-@VERSION@.
242+
243+.SH SEE ALSO
244+.BR @OP_DOCDIR@,
245+.BR oprofile(1)
diff --git a/meta/recipes-kernel/oprofile/oprofile/root-home-dir.patch b/meta/recipes-kernel/oprofile/oprofile/root-home-dir.patch
index 45cab7d3d8..20fc5e503b 100644
--- a/meta/recipes-kernel/oprofile/oprofile/root-home-dir.patch
+++ b/meta/recipes-kernel/oprofile/oprofile/root-home-dir.patch
@@ -1,7 +1,7 @@
1oprofile: Determine the root home directory dynamically 1oprofile: Determine the root home directory dynamically
2 2
3This commit detects the root home directory dynamically with changes to 3This commit detects the root home directory dynamically with changes to
4the opcontrol script and the oprofile gui app source. 4the oprofile gui app source.
5 5
6The commit replaces an earlier fix that detected and adjusted a 6The commit replaces an earlier fix that detected and adjusted a
7'non-standard' root home directory at build time. The advantage of this 7'non-standard' root home directory at build time. The advantage of this
@@ -12,109 +12,33 @@ Upstream-Status: inappropriate [OE specific]
12 12
13Signed-off-by: Dave Lerner <dave.lerner@windriver.com> 13Signed-off-by: Dave Lerner <dave.lerner@windriver.com>
14 14
15diff --git a/doc/opcontrol.1.in b/doc/opcontrol.1.in 15Index: oprofile-1.0.0/doc/oprofile.html
16index c434704..f57eb76 100644 16===================================================================
17--- a/doc/opcontrol.1.in 17--- oprofile-1.0.0.orig/doc/oprofile.html 2014-11-03 17:55:31.511034857 +0000
18+++ b/doc/opcontrol.1.in 18+++ oprofile-1.0.0/doc/oprofile.html 2014-11-03 17:57:26.415037988 +0000
19@@ -171,7 +171,7 @@ No special environment variables are recognised by opcontrol. 19@@ -1563,8 +1563,8 @@
20 20 <span class="emphasis"><em>must</em></span> stop it in a controlled manner in order to process
21 .SH FILES 21 the profile data it has collected. Use <code class="code">kill -SIGINT &lt;operf-PID&gt;</code>
22 .TP 22 for this purpose. It is recommended that when running <span class="command"><strong>operf</strong></span>
23-.I /root/.oprofile/daemonrc 23- with this option, your current working directory should be <code class="filename">/root</code> or a subdirectory
24+.I ~root/.oprofile/daemonrc 24- of <code class="filename">/root</code> to avoid storing sample data files in locations accessible by regular users.
25 Configuration file for opcontrol 25+ with this option, your current working directory should be <code class="filename">~root</code> or a subdirectory
26 .TP 26+ of <code class="filename">~root</code> to avoid storing sample data files in locations accessible by regular users.
27 .I /var/lib/oprofile/samples/
28diff --git a/doc/oprofile.1.in b/doc/oprofile.1.in
29index 3d0f0ed..5c623e1 100644
30--- a/doc/oprofile.1.in
31+++ b/doc/oprofile.1.in
32@@ -150,7 +150,7 @@ No special environment variables are recognised by oprofile.
33 .I $HOME/.oprofile/
34 Configuration files
35 .TP
36-.I /root/.oprofile/daemonrc
37+.I ~root/.oprofile/daemonrc
38 Configuration file for opcontrol
39 .TP
40 .I @prefix@/share/oprofile/
41diff --git a/doc/oprofile.html b/doc/oprofile.html
42index 128d9f7..d7e4dea 100644
43--- a/doc/oprofile.html
44+++ b/doc/oprofile.html
45@@ -1394,7 +1394,7 @@ The <span class="command"><strong>opcontrol</strong></span> script provides the
46 <dd>
47 <p>
48 Followed by list arguments for profiling set up. List of arguments
49- saved in <code class="filename">/root/.oprofile/daemonrc</code>.
50+ saved in <code class="filename">~root/.oprofile/daemonrc</code>.
51 Giving this option is not necessary; you can just directly pass one
52 of the setup options, e.g. <span class="command"><strong>opcontrol --no-vmlinux</strong></span>.
53 </p>
54@@ -1430,7 +1430,7 @@ The <span class="command"><strong>opcontrol</strong></span> script provides the
55 <dd>
56 <p>
57 Start data collection with either arguments provided by <code class="option">--setup</code>
58- or information saved in <code class="filename">/root/.oprofile/daemonrc</code>. Specifying
59+ or information saved in <code class="filename">~root/.oprofile/daemonrc</code>. Specifying
60 the addition <code class="option">--verbose</code> makes the daemon generate lots of debug data
61 whilst it is running.
62 </p> 27 </p>
63diff --git a/doc/oprofile.xml b/doc/oprofile.xml 28 </dd>
64index 6a17c6d..0968d76 100644 29 <dt>
65--- a/doc/oprofile.xml 30Index: oprofile-1.0.0/doc/oprofile.xml
66+++ b/doc/oprofile.xml 31===================================================================
67@@ -568,7 +568,7 @@ The <command>opcontrol</command> script provides the following actions : 32--- oprofile-1.0.0.orig/doc/oprofile.xml 2014-11-03 17:55:31.515034857 +0000
68 <term><option>--setup</option></term> 33+++ oprofile-1.0.0/doc/oprofile.xml 2014-11-03 17:58:03.719039005 +0000
69 <listitem><para> 34@@ -654,8 +654,8 @@
70 Followed by list arguments for profiling set up. List of arguments 35 <emphasis>must</emphasis> stop it in a controlled manner in order to process
71- saved in <filename>/root/.oprofile/daemonrc</filename>. 36 the profile data it has collected. Use <code>kill -SIGINT &lt;operf-PID&gt;</code>
72+ saved in <filename>~root/.oprofile/daemonrc</filename>. 37 for this purpose. It is recommended that when running <command>operf</command>
73 Giving this option is not necessary; you can just directly pass one 38- with this option, your current working directory should be <filename>/root</filename> or a subdirectory
74 of the setup options, e.g. <command>opcontrol --no-vmlinux</command>. 39- of <filename>/root</filename> to avoid storing sample data files in locations accessible by regular users.
75 </para></listitem> 40+ with this option, your current working directory should be <filename>~root</filename> or a subdirectory
76@@ -592,7 +592,7 @@ The <command>opcontrol</command> script provides the following actions : 41+ of <filename>~root</filename> to avoid storing sample data files in locations accessible by regular users.
77 <term><option>--start</option></term>
78 <listitem><para>
79 Start data collection with either arguments provided by <option>--setup</option>
80- or information saved in <filename>/root/.oprofile/daemonrc</filename>. Specifying
81+ or information saved in <filename>~root/.oprofile/daemonrc</filename>. Specifying
82 the addition <option>--verbose</option> makes the daemon generate lots of debug data
83 whilst it is running.
84 </para></listitem> 42 </para></listitem>
85diff --git a/gui/oprof_start_util.cpp b/gui/oprof_start_util.cpp 43 </varlistentry>
86index d293431..d13fa8f 100644 44 <varlistentry>
87--- a/gui/oprof_start_util.cpp
88+++ b/gui/oprof_start_util.cpp
89@@ -20,6 +20,8 @@
90 #include <iostream>
91 #include <fstream>
92 #include <cstdlib>
93+#include <sys/types.h>
94+#include <pwd.h>
95
96 #include <qfiledialog.h>
97 #include <qmessagebox.h>
98@@ -39,7 +41,8 @@ namespace {
99 // return the ~ expansion suffixed with a '/'
100 string const get_config_dir()
101 {
102- return "/root";
103+ struct *pw = getpwnam("root");
104+ return pw->pw_dir;
105 }
106
107 string daemon_pid;
108diff --git a/utils/opcontrol b/utils/opcontrol
109index 09fa5a7..a8acdae 100644
110--- a/utils/opcontrol
111+++ b/utils/opcontrol
112@@ -385,7 +385,7 @@ do_init()
113 OPROFILED="$OPDIR/oprofiled"
114
115 # location for daemon setup information
116- SETUP_DIR="/root/.oprofile"
117+ SETUP_DIR="`grep root /etc/passwd | cut -d: -f6`/.oprofile"
118 SETUP_FILE="$SETUP_DIR/daemonrc"
119 SEC_SETUP_FILE="$SETUP_DIR/daemonrc_new"
120
diff --git a/meta/recipes-kernel/oprofile/oprofile_0.9.9.bb b/meta/recipes-kernel/oprofile/oprofile_0.9.9.bb
deleted file mode 100644
index 63ef6af0e9..0000000000
--- a/meta/recipes-kernel/oprofile/oprofile_0.9.9.bb
+++ /dev/null
@@ -1,17 +0,0 @@
1require oprofile.inc
2
3DEPENDS += "virtual/kernel"
4DEPENDS_append_powerpc64 = " libpfm4"
5
6SRC_URI += "${SOURCEFORGE_MIRROR}/${BPN}/${BPN}-${PV}.tar.gz \
7 file://0001-Add-rmb-definition-for-AArch64-architecture.patch \
8 file://0001-Tidy-powerpc64-bfd-target-check.patch \
9 file://0001-Add-freescale-e500mc-support.patch \
10 file://0002-Add-freescale-e6500-support.patch \
11 "
12SRC_URI[md5sum] = "00aec1287da2dfffda17a9b1c0a01868"
13SRC_URI[sha256sum] = "1e523400daaba7b8d0d15269e977a08b40edfea53970774b69ae130e25117597"
14
15
16S = "${WORKDIR}/oprofile-${PV}"
17
diff --git a/meta/recipes-kernel/oprofile/oprofile_1.0.0.bb b/meta/recipes-kernel/oprofile/oprofile_1.0.0.bb
new file mode 100644
index 0000000000..ad48ab377c
--- /dev/null
+++ b/meta/recipes-kernel/oprofile/oprofile_1.0.0.bb
@@ -0,0 +1,12 @@
1require oprofile.inc
2
3DEPENDS += "virtual/kernel"
4DEPENDS_append_powerpc64 = " libpfm4"
5
6SRC_URI += "${SOURCEFORGE_MIRROR}/${BPN}/${BPN}-${PV}.tar.gz"
7
8SRC_URI[md5sum] = "ba0b340e5c421a93959776c836ed35b3"
9SRC_URI[sha256sum] = "847110b4ecdcf8c8353cd38f94c1b704aad4bfcd9453e38b88d112cfb7e3c45a"
10
11S = "${WORKDIR}/oprofile-${PV}"
12
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-19 02:47:52 +0000