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-rw-r--r--meta/recipes-devtools/gcc/gcc-7.3.inc1
-rw-r--r--meta/recipes-devtools/gcc/gcc-7.3/0001-PR-rtl-optimization-83030.patch272
2 files changed, 273 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-7.3.inc b/meta/recipes-devtools/gcc/gcc-7.3.inc
index d56d2c5e06..b0cba27df2 100644
--- a/meta/recipes-devtools/gcc/gcc-7.3.inc
+++ b/meta/recipes-devtools/gcc/gcc-7.3.inc
@@ -78,6 +78,7 @@ SRC_URI = "\
78" 78"
79BACKPORTS = "\ 79BACKPORTS = "\
80 file://0001-Fix-internal-compiler-error-in-testcase.patch \ 80 file://0001-Fix-internal-compiler-error-in-testcase.patch \
81 file://0001-PR-rtl-optimization-83030.patch \
81" 82"
82 83
83SRC_URI[md5sum] = "be2da21680f27624f3a87055c4ba5af2" 84SRC_URI[md5sum] = "be2da21680f27624f3a87055c4ba5af2"
diff --git a/meta/recipes-devtools/gcc/gcc-7.3/0001-PR-rtl-optimization-83030.patch b/meta/recipes-devtools/gcc/gcc-7.3/0001-PR-rtl-optimization-83030.patch
new file mode 100644
index 0000000000..71f7988eaa
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-7.3/0001-PR-rtl-optimization-83030.patch
@@ -0,0 +1,272 @@
1From f5c4a9440f15ccf6775659910a2014a5494ee86e Mon Sep 17 00:00:00 2001
2From: ebotcazou <ebotcazou@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Wed, 22 Nov 2017 21:43:22 +0000
4Subject: [PATCH] PR rtl-optimization/83030 * doc/rtl.texi (Flags
5 in an RTL Expression): Alphabetize, add entry for CROSSING_JUMP_P and
6 mention usage of 'jump' for JUMP_INSNs. (Insns): Delete entry for
7 REG_CROSSING_JUMP in register notes. * bb-reorder.c
8 (update_crossing_jump_flags): Do not test whether the CROSSING_JUMP_P flag
9 is already set before setting it. * cfgrtl.c (fixup_partition_crossing):
10 Likewise. * reorg.c (relax_delay_slots): Do not consider a
11 CROSSING_JUMP_P insn as useless.
12
13git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@255083 138bc75d-0d04-0410-961f-82ee72b054a4
14
15Upstream-Status: Backport
16
17This patch removes changes to Changelog from the original upstream patch.
18This will help us avoid conflicts.
19
20Original backport to GCC 7.x by Amruta Pawar <Amruta.Pawar@kpit.com>
21
22Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
23
24---
25 gcc/bb-reorder.c | 5 +--
26 gcc/cfgrtl.c | 3 +-
27 gcc/doc/rtl.texi | 129 ++++++++++++++++++++++++++++---------------------------
28 gcc/reorg.c | 7 +--
29 5 files changed, 84 insertions(+), 72 deletions(-)
30
31diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c
32index 55e6dc6..794283c 100644
33--- a/gcc/bb-reorder.c
34+++ b/gcc/bb-reorder.c
35@@ -2236,10 +2236,7 @@ update_crossing_jump_flags (void)
36 FOR_EACH_EDGE (e, ei, bb->succs)
37 if (e->flags & EDGE_CROSSING)
38 {
39- if (JUMP_P (BB_END (bb))
40- /* Some flags were added during fix_up_fall_thru_edges, via
41- force_nonfallthru_and_redirect. */
42- && !CROSSING_JUMP_P (BB_END (bb)))
43+ if (JUMP_P (BB_END (bb)))
44 CROSSING_JUMP_P (BB_END (bb)) = 1;
45 break;
46 }
47diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
48index d6e5ac0..a2ad075 100644
49--- a/gcc/cfgrtl.c
50+++ b/gcc/cfgrtl.c
51@@ -1334,8 +1334,7 @@ fixup_partition_crossing (edge e)
52 if (BB_PARTITION (e->src) != BB_PARTITION (e->dest))
53 {
54 e->flags |= EDGE_CROSSING;
55- if (JUMP_P (BB_END (e->src))
56- && !CROSSING_JUMP_P (BB_END (e->src)))
57+ if (JUMP_P (BB_END (e->src)))
58 CROSSING_JUMP_P (BB_END (e->src)) = 1;
59 }
60 else if (BB_PARTITION (e->src) == BB_PARTITION (e->dest))
61diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
62index 21524f5..a58eedc 100644
63--- a/gcc/doc/rtl.texi
64+++ b/gcc/doc/rtl.texi
65@@ -565,6 +565,16 @@ that are used in certain types of expression. Most often they
66 are accessed with the following macros, which expand into lvalues.
67
68 @table @code
69+@findex CROSSING_JUMP_P
70+@cindex @code{jump_insn} and @samp{/j}
71+@item CROSSING_JUMP_P (@var{x})
72+Nonzero in a @code{jump_insn} if it crosses between hot and cold sections,
73+which could potentially be very far apart in the executable. The presence
74+of this flag indicates to other optimizations that this branching instruction
75+should not be ``collapsed'' into a simpler branching construct. It is used
76+when the optimization to partition basic blocks into hot and cold sections
77+is turned on.
78+
79 @findex CONSTANT_POOL_ADDRESS_P
80 @cindex @code{symbol_ref} and @samp{/u}
81 @cindex @code{unchanging}, in @code{symbol_ref}
82@@ -577,37 +587,6 @@ In either case GCC assumes these addresses can be addressed directly,
83 perhaps with the help of base registers.
84 Stored in the @code{unchanging} field and printed as @samp{/u}.
85
86-@findex RTL_CONST_CALL_P
87-@cindex @code{call_insn} and @samp{/u}
88-@cindex @code{unchanging}, in @code{call_insn}
89-@item RTL_CONST_CALL_P (@var{x})
90-In a @code{call_insn} indicates that the insn represents a call to a
91-const function. Stored in the @code{unchanging} field and printed as
92-@samp{/u}.
93-
94-@findex RTL_PURE_CALL_P
95-@cindex @code{call_insn} and @samp{/i}
96-@cindex @code{return_val}, in @code{call_insn}
97-@item RTL_PURE_CALL_P (@var{x})
98-In a @code{call_insn} indicates that the insn represents a call to a
99-pure function. Stored in the @code{return_val} field and printed as
100-@samp{/i}.
101-
102-@findex RTL_CONST_OR_PURE_CALL_P
103-@cindex @code{call_insn} and @samp{/u} or @samp{/i}
104-@item RTL_CONST_OR_PURE_CALL_P (@var{x})
105-In a @code{call_insn}, true if @code{RTL_CONST_CALL_P} or
106-@code{RTL_PURE_CALL_P} is true.
107-
108-@findex RTL_LOOPING_CONST_OR_PURE_CALL_P
109-@cindex @code{call_insn} and @samp{/c}
110-@cindex @code{call}, in @code{call_insn}
111-@item RTL_LOOPING_CONST_OR_PURE_CALL_P (@var{x})
112-In a @code{call_insn} indicates that the insn represents a possibly
113-infinite looping call to a const or pure function. Stored in the
114-@code{call} field and printed as @samp{/c}. Only true if one of
115-@code{RTL_CONST_CALL_P} or @code{RTL_PURE_CALL_P} is true.
116-
117 @findex INSN_ANNULLED_BRANCH_P
118 @cindex @code{jump_insn} and @samp{/u}
119 @cindex @code{call_insn} and @samp{/u}
120@@ -702,6 +681,29 @@ Stored in the @code{call} field and printed as @samp{/c}.
121 Nonzero in a @code{mem} if the memory reference holds a pointer.
122 Stored in the @code{frame_related} field and printed as @samp{/f}.
123
124+@findex MEM_READONLY_P
125+@cindex @code{mem} and @samp{/u}
126+@cindex @code{unchanging}, in @code{mem}
127+@item MEM_READONLY_P (@var{x})
128+Nonzero in a @code{mem}, if the memory is statically allocated and read-only.
129+
130+Read-only in this context means never modified during the lifetime of the
131+program, not necessarily in ROM or in write-disabled pages. A common
132+example of the later is a shared library's global offset table. This
133+table is initialized by the runtime loader, so the memory is technically
134+writable, but after control is transferred from the runtime loader to the
135+application, this memory will never be subsequently modified.
136+
137+Stored in the @code{unchanging} field and printed as @samp{/u}.
138+
139+@findex PREFETCH_SCHEDULE_BARRIER_P
140+@cindex @code{prefetch} and @samp{/v}
141+@cindex @code{volatile}, in @code{prefetch}
142+@item PREFETCH_SCHEDULE_BARRIER_P (@var{x})
143+In a @code{prefetch}, indicates that the prefetch is a scheduling barrier.
144+No other INSNs will be moved over it.
145+Stored in the @code{volatil} field and printed as @samp{/v}.
146+
147 @findex REG_FUNCTION_VALUE_P
148 @cindex @code{reg} and @samp{/i}
149 @cindex @code{return_val}, in @code{reg}
150@@ -731,6 +733,37 @@ The same hard register may be used also for collecting the values of
151 functions called by this one, but @code{REG_FUNCTION_VALUE_P} is zero
152 in this kind of use.
153
154+@findex RTL_CONST_CALL_P
155+@cindex @code{call_insn} and @samp{/u}
156+@cindex @code{unchanging}, in @code{call_insn}
157+@item RTL_CONST_CALL_P (@var{x})
158+In a @code{call_insn} indicates that the insn represents a call to a
159+const function. Stored in the @code{unchanging} field and printed as
160+@samp{/u}.
161+
162+@findex RTL_PURE_CALL_P
163+@cindex @code{call_insn} and @samp{/i}
164+@cindex @code{return_val}, in @code{call_insn}
165+@item RTL_PURE_CALL_P (@var{x})
166+In a @code{call_insn} indicates that the insn represents a call to a
167+pure function. Stored in the @code{return_val} field and printed as
168+@samp{/i}.
169+
170+@findex RTL_CONST_OR_PURE_CALL_P
171+@cindex @code{call_insn} and @samp{/u} or @samp{/i}
172+@item RTL_CONST_OR_PURE_CALL_P (@var{x})
173+In a @code{call_insn}, true if @code{RTL_CONST_CALL_P} or
174+@code{RTL_PURE_CALL_P} is true.
175+
176+@findex RTL_LOOPING_CONST_OR_PURE_CALL_P
177+@cindex @code{call_insn} and @samp{/c}
178+@cindex @code{call}, in @code{call_insn}
179+@item RTL_LOOPING_CONST_OR_PURE_CALL_P (@var{x})
180+In a @code{call_insn} indicates that the insn represents a possibly
181+infinite looping call to a const or pure function. Stored in the
182+@code{call} field and printed as @samp{/c}. Only true if one of
183+@code{RTL_CONST_CALL_P} or @code{RTL_PURE_CALL_P} is true.
184+
185 @findex RTX_FRAME_RELATED_P
186 @cindex @code{insn} and @samp{/f}
187 @cindex @code{call_insn} and @samp{/f}
188@@ -765,21 +798,6 @@ computation performed by this instruction, i.e., one that
189 This flag is required for exception handling support on targets with RTL
190 prologues.
191
192-@findex MEM_READONLY_P
193-@cindex @code{mem} and @samp{/u}
194-@cindex @code{unchanging}, in @code{mem}
195-@item MEM_READONLY_P (@var{x})
196-Nonzero in a @code{mem}, if the memory is statically allocated and read-only.
197-
198-Read-only in this context means never modified during the lifetime of the
199-program, not necessarily in ROM or in write-disabled pages. A common
200-example of the later is a shared library's global offset table. This
201-table is initialized by the runtime loader, so the memory is technically
202-writable, but after control is transferred from the runtime loader to the
203-application, this memory will never be subsequently modified.
204-
205-Stored in the @code{unchanging} field and printed as @samp{/u}.
206-
207 @findex SCHED_GROUP_P
208 @cindex @code{insn} and @samp{/s}
209 @cindex @code{call_insn} and @samp{/s}
210@@ -879,14 +897,6 @@ Stored in the @code{volatil} field and printed as @samp{/v}.
211 Most uses of @code{SYMBOL_REF_FLAG} are historic and may be subsumed
212 by @code{SYMBOL_REF_FLAGS}. Certainly use of @code{SYMBOL_REF_FLAGS}
213 is mandatory if the target requires more than one bit of storage.
214-
215-@findex PREFETCH_SCHEDULE_BARRIER_P
216-@cindex @code{prefetch} and @samp{/v}
217-@cindex @code{volatile}, in @code{prefetch}
218-@item PREFETCH_SCHEDULE_BARRIER_P (@var{x})
219-In a @code{prefetch}, indicates that the prefetch is a scheduling barrier.
220-No other INSNs will be moved over it.
221-Stored in the @code{volatil} field and printed as @samp{/v}.
222 @end table
223
224 These are the fields to which the above macros refer:
225@@ -974,6 +985,8 @@ In a @code{set}, 1 means it is for a return.
226
227 In a @code{call_insn}, 1 means it is a sibling call.
228
229+In a @code{jump_insn}, 1 means it is a crossing jump.
230+
231 In an RTL dump, this flag is represented as @samp{/j}.
232
233 @findex unchanging
234@@ -3887,16 +3900,6 @@ multiple targets; the last label in the insn (in the highest numbered
235 insn-field) goes into the @code{JUMP_LABEL} field and does not have a
236 @code{REG_LABEL_TARGET} note. @xref{Insns, JUMP_LABEL}.
237
238-@findex REG_CROSSING_JUMP
239-@item REG_CROSSING_JUMP
240-This insn is a branching instruction (either an unconditional jump or
241-an indirect jump) which crosses between hot and cold sections, which
242-could potentially be very far apart in the executable. The presence
243-of this note indicates to other optimizations that this branching
244-instruction should not be ``collapsed'' into a simpler branching
245-construct. It is used when the optimization to partition basic blocks
246-into hot and cold sections is turned on.
247-
248 @findex REG_SETJMP
249 @item REG_SETJMP
250 Appears attached to each @code{CALL_INSN} to @code{setjmp} or a
251diff --git a/gcc/reorg.c b/gcc/reorg.c
252index 5914af6..77f3fe7 100644
253--- a/gcc/reorg.c
254+++ b/gcc/reorg.c
255@@ -3360,10 +3360,11 @@ relax_delay_slots (rtx_insn *first)
256 }
257
258 /* See if we have a simple (conditional) jump that is useless. */
259- if (! INSN_ANNULLED_BRANCH_P (delay_jump_insn)
260- && ! condjump_in_parallel_p (delay_jump_insn)
261+ if (!CROSSING_JUMP_P (delay_jump_insn)
262+ && !INSN_ANNULLED_BRANCH_P (delay_jump_insn)
263+ && !condjump_in_parallel_p (delay_jump_insn)
264 && prev_active_insn (as_a<rtx_insn *> (target_label)) == insn
265- && ! BARRIER_P (prev_nonnote_insn (as_a<rtx_insn *> (target_label)))
266+ && !BARRIER_P (prev_nonnote_insn (as_a<rtx_insn *> (target_label)))
267 /* If the last insn in the delay slot sets CC0 for some insn,
268 various code assumes that it is in a delay slot. We could
269 put it back where it belonged and delete the register notes,
270--
2711.8.5.6
272