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-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6.inc3
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch49
2 files changed, 51 insertions, 1 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-4.6.inc b/meta/recipes-devtools/gcc/gcc-4.6.inc
index 380f9f7dae..f7bcf30f1b 100644
--- a/meta/recipes-devtools/gcc/gcc-4.6.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.6.inc
@@ -1,6 +1,6 @@
1require gcc-common.inc 1require gcc-common.inc
2 2
3PR = "r9" 3PR = "r10"
4 4
5# Third digit in PV should be incremented after a minor release 5# Third digit in PV should be incremented after a minor release
6# happens from this branch on gcc e.g. currently its 4.6.0 6# happens from this branch on gcc e.g. currently its 4.6.0
@@ -67,6 +67,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
67 file://volatile_access_backport.patch \ 67 file://volatile_access_backport.patch \
68 file://use-defaults.h-and-t-oe-in-B.patch \ 68 file://use-defaults.h-and-t-oe-in-B.patch \
69 file://powerpc-e5500.patch \ 69 file://powerpc-e5500.patch \
70 file://fix-for-ice-50099.patch \
70 " 71 "
71 72
72SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch " 73SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch "
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch b/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
new file mode 100644
index 0000000000..57b03d2bfb
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
@@ -0,0 +1,49 @@
1
2This patch address an issue with the compiler generating an ICE
3during compliation of lttng-ust.
4
5http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50099
6
7Upstream-Status: Pending
8
9Signed-off-by: Khem Raj <khem.raj@gmail.com>
10Signed-off-by: Saul Wold <sgw@linux.intel.com>
11
12Index: gcc/config/arm/arm.md
13===================================================================
14--- gcc-4.6.0/gcc/config/arm/arm.md (revision 178135)
15+++ gcc-4.6.0/gcc/config/arm/arm.md (working copy)
16@@ -4217,6 +4217,7 @@ (define_split
17 "TARGET_32BIT"
18 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
19 {
20+ rtx srcop = operands[1];
21 rtx lo_part = gen_lowpart (SImode, operands[0]);
22 enum machine_mode src_mode = GET_MODE (operands[1]);
23
24@@ -4224,14 +4225,21 @@ (define_split
25 && !reg_overlap_mentioned_p (operands[0], operands[1]))
26 emit_clobber (operands[0]);
27
28+ if (TARGET_ARM && src_mode == QImode
29+ && !arm_reg_or_extendqisi_mem_op (srcop, QImode))
30+ {
31+ rtx dest = gen_lowpart (QImode, lo_part);
32+ emit_move_insn (dest, srcop);
33+ srcop = dest;
34+ }
35 if (!REG_P (lo_part) || src_mode != SImode
36- || !rtx_equal_p (lo_part, operands[1]))
37+ || !rtx_equal_p (lo_part, srcop))
38 {
39 if (src_mode == SImode)
40- emit_move_insn (lo_part, operands[1]);
41+ emit_move_insn (lo_part, srcop);
42 else
43 emit_insn (gen_rtx_SET (VOIDmode, lo_part,
44- gen_rtx_SIGN_EXTEND (SImode, operands[1])));
45+ gen_rtx_SIGN_EXTEND (SImode, srcop)));
46 operands[1] = lo_part;
47 }
48 operands[0] = gen_highpart (SImode, operands[0]);
49