diff options
author | Richard Purdie <rpurdie@linux.intel.com> | 2010-09-07 22:28:15 +0100 |
---|---|---|
committer | Richard Purdie <rpurdie@linux.intel.com> | 2010-09-07 22:29:28 +0100 |
commit | 7ef65593aa45da08cb15e8fa76491de4aba5b4b3 (patch) | |
tree | 791604031a1c1e743cbfddeb420672810ab00f1a /meta | |
parent | 51dd0269bcaf22bb3c1b3b2e877896d104168ee8 (diff) | |
download | poky-7ef65593aa45da08cb15e8fa76491de4aba5b4b3.tar.gz |
qemu: Apply fix for armv6 locale generation using TLS registers
Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
Diffstat (limited to 'meta')
-rw-r--r-- | meta/recipes-devtools/qemu/qemu-0.12.4/arm-cp15-fix.patch | 131 | ||||
-rw-r--r-- | meta/recipes-devtools/qemu/qemu_0.12.4.bb | 3 |
2 files changed, 133 insertions, 1 deletions
diff --git a/meta/recipes-devtools/qemu/qemu-0.12.4/arm-cp15-fix.patch b/meta/recipes-devtools/qemu/qemu-0.12.4/arm-cp15-fix.patch new file mode 100644 index 0000000000..1e0ea43083 --- /dev/null +++ b/meta/recipes-devtools/qemu/qemu-0.12.4/arm-cp15-fix.patch | |||
@@ -0,0 +1,131 @@ | |||
1 | From: Riku Voipio <riku.voipio@nokia.com> | ||
2 | |||
3 | Access the cp15.c13 TLS registers directly with TCG ops instead of with | ||
4 | a slow helper. If the the cp15 read/write was not TLS register access, | ||
5 | fall back to the cp15 helper. | ||
6 | |||
7 | This makes accessing __thread variables in linux-user when apps are compiled | ||
8 | with -mtp=cp15 possible. legal cp15 register to acces from linux-user are | ||
9 | already checked in cp15_user_ok. | ||
10 | |||
11 | While at it, make the cp15.c13 Thread ID registers available only on | ||
12 | ARMv6K and newer. | ||
13 | |||
14 | Signed-off-by: Riku Voipio <riku.voipio@nokia.com> | ||
15 | Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
16 | |||
17 | diff --git a/target-arm/helper.c b/target-arm/helper.c | ||
18 | index b3aec99..27001e8 100644 | ||
19 | --- a/target-arm/helper.c | ||
20 | +++ b/target-arm/helper.c | ||
21 | @@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) | ||
22 | uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) | ||
23 | { | ||
24 | cpu_abort(env, "cp15 insn %08x\n", insn); | ||
25 | - return 0; | ||
26 | } | ||
27 | |||
28 | /* These should probably raise undefined insn exceptions. */ | ||
29 | @@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) | ||
30 | tlb_flush(env, 0); | ||
31 | env->cp15.c13_context = val; | ||
32 | break; | ||
33 | - case 2: | ||
34 | - env->cp15.c13_tls1 = val; | ||
35 | - break; | ||
36 | - case 3: | ||
37 | - env->cp15.c13_tls2 = val; | ||
38 | - break; | ||
39 | - case 4: | ||
40 | - env->cp15.c13_tls3 = val; | ||
41 | - break; | ||
42 | default: | ||
43 | goto bad_reg; | ||
44 | } | ||
45 | @@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) | ||
46 | return env->cp15.c13_fcse; | ||
47 | case 1: | ||
48 | return env->cp15.c13_context; | ||
49 | - case 2: | ||
50 | - return env->cp15.c13_tls1; | ||
51 | - case 3: | ||
52 | - return env->cp15.c13_tls2; | ||
53 | - case 4: | ||
54 | - return env->cp15.c13_tls3; | ||
55 | default: | ||
56 | goto bad_reg; | ||
57 | } | ||
58 | diff --git a/target-arm/translate.c b/target-arm/translate.c | ||
59 | index 5cf3e06..786c329 100644 | ||
60 | --- a/target-arm/translate.c | ||
61 | +++ b/target-arm/translate.c | ||
62 | @@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn) | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | +static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd) | ||
67 | +{ | ||
68 | + TCGv tmp; | ||
69 | + int cpn = (insn >> 16) & 0xf; | ||
70 | + int cpm = insn & 0xf; | ||
71 | + int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); | ||
72 | + | ||
73 | + if (!arm_feature(env, ARM_FEATURE_V6K)) | ||
74 | + return 0; | ||
75 | + | ||
76 | + if (!(cpn == 13 && cpm == 0)) | ||
77 | + return 0; | ||
78 | + | ||
79 | + if (insn & ARM_CP_RW_BIT) { | ||
80 | + tmp = new_tmp(); | ||
81 | + switch (op) { | ||
82 | + case 2: | ||
83 | + tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1)); | ||
84 | + break; | ||
85 | + case 3: | ||
86 | + tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2)); | ||
87 | + break; | ||
88 | + case 4: | ||
89 | + tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3)); | ||
90 | + break; | ||
91 | + default: | ||
92 | + dead_tmp(tmp); | ||
93 | + return 0; | ||
94 | + } | ||
95 | + store_reg(s, rd, tmp); | ||
96 | + | ||
97 | + } else { | ||
98 | + tmp = load_reg(s, rd); | ||
99 | + switch (op) { | ||
100 | + case 2: | ||
101 | + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls1)); | ||
102 | + break; | ||
103 | + case 3: | ||
104 | + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls2)); | ||
105 | + break; | ||
106 | + case 4: | ||
107 | + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, cp15.c13_tls3)); | ||
108 | + break; | ||
109 | + default: | ||
110 | + return 0; | ||
111 | + } | ||
112 | + dead_tmp(tmp); | ||
113 | + } | ||
114 | + return 1; | ||
115 | +} | ||
116 | + | ||
117 | /* Disassemble system coprocessor (cp15) instruction. Return nonzero if | ||
118 | instruction is not defined. */ | ||
119 | static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) | ||
120 | @@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) | ||
121 | return 0; | ||
122 | } | ||
123 | rd = (insn >> 12) & 0xf; | ||
124 | + | ||
125 | + if (cp15_tls_load_store(env, s, insn, rd)) | ||
126 | + return 0; | ||
127 | + | ||
128 | tmp2 = tcg_const_i32(insn); | ||
129 | if (insn & ARM_CP_RW_BIT) { | ||
130 | tmp = new_tmp(); | ||
131 | |||
diff --git a/meta/recipes-devtools/qemu/qemu_0.12.4.bb b/meta/recipes-devtools/qemu/qemu_0.12.4.bb index ac197d756a..e448eb9b17 100644 --- a/meta/recipes-devtools/qemu/qemu_0.12.4.bb +++ b/meta/recipes-devtools/qemu/qemu_0.12.4.bb | |||
@@ -1,6 +1,6 @@ | |||
1 | require qemu.inc | 1 | require qemu.inc |
2 | 2 | ||
3 | PR = "r19" | 3 | PR = "r20" |
4 | 4 | ||
5 | FILESPATH = "${FILE_DIRNAME}/qemu-${PV}" | 5 | FILESPATH = "${FILE_DIRNAME}/qemu-${PV}" |
6 | FILESDIR = "${WORKDIR}" | 6 | FILESDIR = "${WORKDIR}" |
@@ -18,6 +18,7 @@ SRC_URI = "\ | |||
18 | file://qemu-vmware-vga-depth.patch \ | 18 | file://qemu-vmware-vga-depth.patch \ |
19 | file://qemu-ppc-hack.patch \ | 19 | file://qemu-ppc-hack.patch \ |
20 | file://enable-i386-linux-user.patch \ | 20 | file://enable-i386-linux-user.patch \ |
21 | file://arm-cp15-fix.patch \ | ||
21 | file://powerpc_rom.bin" | 22 | file://powerpc_rom.bin" |
22 | 23 | ||
23 | do_install_append () { | 24 | do_install_append () { |