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authorRichard Purdie <rpurdie@linux.intel.com>2010-08-27 15:14:24 +0100
committerRichard Purdie <rpurdie@linux.intel.com>2010-08-27 15:29:45 +0100
commit29d6678fd546377459ef75cf54abeef5b969b5cf (patch)
tree8edd65790e37a00d01c3f203f773fe4b5012db18 /meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch
parentda49de6885ee1bc424e70bc02f21f6ab920efb55 (diff)
downloadpoky-29d6678fd546377459ef75cf54abeef5b969b5cf.tar.gz
Major layout change to the packages directory
Having one monolithic packages directory makes it hard to find things and is generally overwhelming. This commit splits it into several logical sections roughly based on function, recipes.txt gives more information about the classifications used. The opportunity is also used to switch from "packages" to "recipes" as used in OpenEmbedded as the term "packages" can be confusing to people and has many different meanings. Not all recipes have been classified yet, this is just a first pass at separating things out. Some packages are moved to meta-extras as they're no longer actively used or maintained. Signed-off-by: Richard Purdie <rpurdie@linux.intel.com>
Diffstat (limited to 'meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch')
-rw-r--r--meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch5877
1 files changed, 5877 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch b/meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch
new file mode 100644
index 0000000000..ad4ce996df
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-rp-2.6.23/arm_pxa_20070923.patch
@@ -0,0 +1,5877 @@
1# Base git commit: da8f153e51290e7438ba7da66234a864e5d3e1c1
2# (Revert "x86_64: Quicklist support for x86_64")
3#
4# Author: eric miao (Wed Sep 12 03:13:17 BST 2007)
5# Committer: Russell King (Sun Sep 23 14:18:19 BST 2007)
6#
7# [ARM] pxa: PXA3xx base support
8#
9# Signed-off-by: eric miao
10# Signed-off-by: Russell King
11#
12# arch/arm/Kconfig | 6
13# arch/arm/boot/compressed/head-xscale.S | 4
14# arch/arm/mach-pxa/Kconfig | 30 +
15# arch/arm/mach-pxa/Makefile | 9
16# arch/arm/mach-pxa/clock.c | 79 ++--
17# arch/arm/mach-pxa/clock.h | 43 ++
18# arch/arm/mach-pxa/devices.h | 3
19# arch/arm/mach-pxa/generic.c | 146 ++++---
20# arch/arm/mach-pxa/generic.h | 26 +
21# arch/arm/mach-pxa/irq.c | 80 ----
22# arch/arm/mach-pxa/mfp.c | 235 ++++++++++++
23# arch/arm/mach-pxa/pxa25x.c | 90 ++++
24# arch/arm/mach-pxa/pxa27x.c | 127 ++++++
25# arch/arm/mach-pxa/pxa300.c | 93 +++++
26# arch/arm/mach-pxa/pxa320.c | 88 ++++
27# arch/arm/mach-pxa/pxa3xx.c | 216 +++++++++++
28# arch/arm/mach-pxa/time.c | 53 ++
29# arch/arm/mach-pxa/zylonite.c | 184 +++++++++
30# arch/arm/mach-pxa/zylonite_pxa300.c | 188 ++++++++++
31# arch/arm/mach-pxa/zylonite_pxa320.c | 173 +++++++++
32# arch/arm/mm/Kconfig | 4
33# drivers/i2c/busses/i2c-pxa.c | 45 +-
34# drivers/input/keyboard/pxa27x_keyboard.c | 25 +
35# drivers/mmc/host/pxamci.c | 43 +-
36# drivers/mmc/host/pxamci.h | 14
37# drivers/mtd/maps/lubbock-flash.c | 9
38# drivers/mtd/maps/mainstone-flash.c | 5
39# drivers/net/irda/pxaficp_ir.c | 51 ++
40# drivers/net/smc91x.c | 62 ---
41# drivers/net/smc91x.h | 71 +++
42# drivers/serial/pxa.c | 163 ++++----
43# drivers/serial/serial_core.c | 18
44# drivers/usb/gadget/pxa2xx_udc.c | 68 ++-
45# drivers/usb/gadget/pxa2xx_udc.h | 1
46# drivers/video/pxafb.c | 36 +
47# drivers/video/pxafb.h | 1
48# include/asm-arm/arch-pxa/hardware.h | 72 +++
49# include/asm-arm/arch-pxa/irqs.h | 6
50# include/asm-arm/arch-pxa/mfp-pxa300.h | 574 ++++++++++++++++++++++++++++++
51# include/asm-arm/arch-pxa/mfp-pxa320.h | 446 ++++++++++++++++++++++++
52# include/asm-arm/arch-pxa/mfp.h | 576 +++++++++++++++++++++++++++++++
53# include/asm-arm/arch-pxa/pxa-regs.h | 2
54# include/asm-arm/arch-pxa/pxa3xx-regs.h | 75 ++++
55# include/asm-arm/arch-pxa/timex.h | 2
56# include/asm-arm/arch-pxa/zylonite.h | 35 +
57# 45 files changed, 3825 insertions(+), 452 deletions(-)
58# create mode 100644 arch/arm/mach-pxa/mfp.c
59# create mode 100644 arch/arm/mach-pxa/pxa300.c
60# create mode 100644 arch/arm/mach-pxa/pxa320.c
61# create mode 100644 arch/arm/mach-pxa/pxa3xx.c
62# create mode 100644 arch/arm/mach-pxa/zylonite.c
63# create mode 100644 arch/arm/mach-pxa/zylonite_pxa300.c
64# create mode 100644 arch/arm/mach-pxa/zylonite_pxa320.c
65# create mode 100644 include/asm-arm/arch-pxa/mfp-pxa300.h
66# create mode 100644 include/asm-arm/arch-pxa/mfp-pxa320.h
67# create mode 100644 include/asm-arm/arch-pxa/mfp.h
68# create mode 100644 include/asm-arm/arch-pxa/pxa3xx-regs.h
69# create mode 100644 include/asm-arm/arch-pxa/zylonite.h
70#
71# Author: Russell King (Sat Sep 1 21:27:18 BST 2007)
72# Committer: Russell King (Sun Sep 23 14:18:17 BST 2007)
73#
74# [NET] smc91x: fix PXA DMA support code
75#
76# The PXA DMA support code for smc91x doesn't pass a struct device to
77# the dma_*map_single() functions, which leads to an oops in the dma
78# bounce code. We have a struct device which was used to probe the
79# SMC chip. Use it.
80#
81# (This patch is slightly larger because it requires struct smc_local
82# to move into the header file.)
83#
84# Signed-off-by: Russell King
85#
86#
87# Author: Russell King (Sat Sep 1 21:25:09 BST 2007)
88# Committer: Russell King (Sun Sep 23 14:18:12 BST 2007)
89#
90# [SERIAL] Fix console initialisation ordering
91#
92# Ensure pm callback is called upon initialisation to place port in
93# correct power saving state. Ensure console is initialised prior
94# to deciding whether to power down the port.
95#
96# Signed-off-by: Russell King
97#
98#
99# Author: Russell King (Wed Sep 19 09:21:51 BST 2007)
100# Committer: Russell King (Sun Sep 23 14:18:07 BST 2007)
101#
102# [ARM] pxa: tidy up arch/arm/mach-pxa/Makefile
103#
104# Signed-off-by: Russell King
105#
106#
107# Author: Russell King (Sat Sep 1 21:28:55 BST 2007)
108# Committer: Russell King (Sun Sep 23 14:18:03 BST 2007)
109#
110# [ARM] lubbock, mainstone: only initialise if running on that platform
111#
112# Signed-off-by: Russell King
113#
114#
115# Author: eric miao (Wed Aug 29 10:22:17 BST 2007)
116# Committer: Russell King (Sun Sep 23 14:18:01 BST 2007)
117#
118# [ARM] 4560/1: pxa: move processor specific set_wake logic out of irq.c
119#
120# a function pxa_init_irq_set_wake() was introduced, so that
121# processor specific code could install their own version
122#
123# code setting PFER and PRER registers within pxa_gpio_irq_type
124# are removed, and the edge configuration is postponed to the
125# (*set_wake) and copies the GRER and GFER register, which will
126# always be set up correctly by pxa_gpio_irq_type()
127#
128# Signed-off-by: eric miao
129# Signed-off-by: Russell King
130#
131#
132# Author: eric miao (Wed Aug 29 10:18:47 BST 2007)
133# Committer: Russell King (Sun Sep 23 14:17:59 BST 2007)
134#
135# [ARM] 4559/1: pxa: make PXA_LAST_GPIO a run-time variable
136#
137# This definition produces processor specific code in generic function
138# pxa_gpio_mode(), thus creating inconsistencies for support of pxa25x
139# and pxa27x in a single zImage.
140#
141# As David Brownell suggests, make it a run-time variable and initialize
142# at run-time according to the number of GPIOs on the processor. For now
143# the initialization happens in pxa_init_irq_gpio(), since there is
144# already a parameter for that, besides, this is and MUST be earlier
145# than any subsequent calls to pxa_gpio_mode().
146#
147# Signed-off-by: eric miao
148# Signed-off-by: Russell King
149#
150#
151# Author: eric miao (Wed Aug 29 10:15:41 BST 2007)
152# Committer: Russell King (Sun Sep 23 14:17:57 BST 2007)
153#
154# [ARM] 4558/1: pxa: remove MACH_TYPE_LUBBOCK assignment and leave it to boot loader
155#
156# since both u-boot and blob support passing MACH_TYPE_LUBBOCK to the
157# kernel, it should be quite safe to remove this
158#
159# Signed-off-by: eric miao
160# Acked-by: Nicolas Pitre
161# Signed-off-by: Russell King
162#
163#
164# Author: eric miao (Wed Sep 12 03:13:17 BST 2007)
165# Committer: Russell King (Sun Sep 23 14:17:55 BST 2007)
166#
167# [ARM] pxa: add PXA3 cpu_is_xxx() macros
168#
169# Extracted from patch by Eric Miao, this adds the cpu_is_xxx() macros
170# for identifying PXA3 SoCs.
171#
172# Signed-off-by: eric miao
173# Signed-off-by: Russell King
174#
175#
176# Author: Russell King (Wed Sep 19 09:38:32 BST 2007)
177# Committer: Russell King (Sun Sep 23 14:17:51 BST 2007)
178#
179# [ARM] pxa: Make CPU_XSCALE depend on PXA25x or PXA27x
180#
181# PXA3 SoCs are supported by the Xscale3 CPU code rather than the
182# Xscale CPU code.
183#
184# Signed-off-by: Russell King
185#
186#
187# Author: Russell King (Wed Sep 19 09:33:55 BST 2007)
188# Committer: Russell King (Sun Sep 23 14:17:48 BST 2007)
189#
190# [ARM] pxa: mark pxa_set_cken deprecated
191#
192# Allow the generic clock support code to fiddle with the CKEN register
193# and mark pxa_set_cken() deprecated.
194#
195# Signed-off-by: Russell King
196#
197#
198# Author: Russell King (Mon Aug 20 10:34:37 BST 2007)
199# Committer: Russell King (Sun Sep 23 14:17:43 BST 2007)
200#
201# [ARM] pxa: remove get_lcdclk_frequency_10khz()
202#
203# get_lcdclk_frequency_10khz() is now redundant, remove it. Hide
204# pxa27x_get_lcdclk_frequency_10khz() from public view.
205#
206# Signed-off-by: Russell King
207#
208#
209# Author: Russell King (Sun Sep 2 17:09:23 BST 2007)
210# Committer: Russell King (Sun Sep 23 14:17:39 BST 2007)
211#
212# [ARM] pxa: update pxa irda driver to use clk support
213#
214# Signed-off-by: Russell King
215#
216#
217# Author: Russell King (Sun Sep 2 17:08:42 BST 2007)
218# Committer: Russell King (Sun Sep 23 14:17:36 BST 2007)
219#
220# [ARM] pxa: Make STUART and FICP clocks available
221#
222# Signed-off-by: Russell King
223#
224#
225# Author: Russell King (Mon Aug 20 10:33:35 BST 2007)
226# Committer: Russell King (Sun Sep 23 14:17:34 BST 2007)
227#
228# [ARM] pxa: update PXA UDC driver to use clk support
229#
230# Note: this produces a WARN() dump.
231#
232# Signed-off-by: Russell King
233#
234#
235# Author: Russell King (Mon Aug 20 10:28:15 BST 2007)
236# Committer: Russell King (Sun Sep 23 14:17:31 BST 2007)
237#
238# [ARM] pxa: update pxa serial driver to use clk support
239#
240# Signed-off-by: Russell King
241#
242#
243# Author: Russell King (Mon Aug 20 10:20:03 BST 2007)
244# Committer: Russell King (Sun Sep 23 14:17:27 BST 2007)
245#
246# [ARM] pxa: update PXA MMC interface driver to use clk support
247#
248# Signed-off-by: Russell King
249#
250#
251# Author: Russell King (Mon Aug 20 10:19:39 BST 2007)
252# Committer: Russell King (Sun Sep 23 14:17:23 BST 2007)
253#
254# [ARM] pxa: update pxa27x keypad driver to use clk support
255#
256# Signed-off-by: Russell King
257#
258#
259# Author: Russell King (Mon Aug 20 10:19:10 BST 2007)
260# Committer: Russell King (Sun Sep 23 14:17:19 BST 2007)
261#
262# [ARM] pxa: update pxa i2c driver to use clk support
263#
264# Signed-off-by: Russell King
265#
266#
267# Author: Russell King (Mon Aug 20 10:18:42 BST 2007)
268# Committer: Russell King (Sun Sep 23 14:16:50 BST 2007)
269#
270# [ARM] pxa: update pxafb to use clk support
271#
272# Signed-off-by: Russell King
273#
274#
275# Author: Russell King (Mon Aug 20 10:18:02 BST 2007)
276# Committer: Russell King (Sat Sep 22 20:48:09 BST 2007)
277#
278# [ARM] pxa: introduce clk support for PXA SoC clocks
279#
280# Signed-off-by: Russell King
281#
282# create mode 100644 arch/arm/mach-pxa/clock.h
283#
284# Author: Russell King (Mon Aug 20 10:09:18 BST 2007)
285# Committer: Russell King (Sat Sep 22 20:48:09 BST 2007)
286#
287# [ARM] pxa: make pxa27x devices globally visible
288#
289# Signed-off-by: Russell King
290#
291#
292# Author: Russell King (Mon Aug 20 10:07:44 BST 2007)
293# Committer: Russell King (Sat Sep 22 20:48:08 BST 2007)
294#
295# [ARM] pxa: fix naming of memory/lcd/core clock functions
296#
297# Rename pxa25x and pxa27x memory/lcd/core clock functions, and
298# select the correct version at run time.
299#
300# Signed-off-by: Russell King
301#
302#
303# Author: Russell King (Mon Aug 20 09:47:41 BST 2007)
304# Committer: Russell King (Sat Sep 22 20:48:08 BST 2007)
305#
306# [ARM] pxa: convert PXA serial drivers to use platform resources
307#
308# Signed-off-by: Russell King
309#
310#
311# Author: Russell King (Sat Sep 1 21:12:50 BST 2007)
312# Committer: Russell King (Sat Sep 22 20:48:07 BST 2007)
313#
314# [ARM] pxa: make pxa timer initialisation select clock rate at runtime
315#
316# Rather than using the compile-time constant CLOCK_TICK_RATE, select
317# the clock tick rate at run time. We organise the selection so that
318# PXA3 automatically falls out with the right tick rate.
319#
320# Signed-off-by: Russell King
321#
322#
323# Author: Nicolas Pitre (Fri Aug 17 16:55:22 BST 2007)
324# Committer: Russell King (Sat Sep 22 20:48:05 BST 2007)
325#
326# [ARM] 4550/1: sched_clock on PXA should cope with run time clock rate selection
327#
328# The previous implementation was relying on compile time optimizations
329# based on a constant clock rate. However, support for different PXA
330# flavors in the same kernel binary requires that the clock be selected at
331# run time, so here it is.
332#
333# Let's move this code to a more appropriate location while at it.
334#
335# Signed-off-by: Nicolas Pitre
336# Signed-off-by: Russell King
337#
338#
339--- linux-2.6.23.orig/arch/arm/Kconfig
340+++ linux-2.6.23/arch/arm/Kconfig
341@@ -336,14 +336,14 @@
342 This enables support for Philips PNX4008 mobile platform.
343
344 config ARCH_PXA
345- bool "PXA2xx-based"
346+ bool "PXA2xx/PXA3xx-based"
347 depends on MMU
348 select ARCH_MTD_XIP
349 select GENERIC_GPIO
350 select GENERIC_TIME
351 select GENERIC_CLOCKEVENTS
352 help
353- Support for Intel's PXA2XX processor line.
354+ Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
355
356 config ARCH_RPC
357 bool "RiscPC"
358@@ -486,7 +486,7 @@
359 config IWMMXT
360 bool "Enable iWMMXt support"
361 depends on CPU_XSCALE || CPU_XSC3
362- default y if PXA27x
363+ default y if PXA27x || PXA3xx
364 help
365 Enable support for iWMMXt context switching at run time if
366 running on a CPU that supports it.
367--- linux-2.6.23.orig/arch/arm/boot/compressed/head-xscale.S
368+++ linux-2.6.23/arch/arm/boot/compressed/head-xscale.S
369@@ -33,10 +33,6 @@
370 bic r0, r0, #0x1000 @ clear Icache
371 mcr p15, 0, r0, c1, c0, 0
372
373-#ifdef CONFIG_ARCH_LUBBOCK
374- mov r7, #MACH_TYPE_LUBBOCK
375-#endif
376-
377 #ifdef CONFIG_ARCH_COTULLA_IDP
378 mov r7, #MACH_TYPE_COTULLA_IDP
379 #endif
380--- linux-2.6.23.orig/arch/arm/mach-pxa/Kconfig
381+++ linux-2.6.23/arch/arm/mach-pxa/Kconfig
382@@ -1,6 +1,24 @@
383 if ARCH_PXA
384
385-menu "Intel PXA2xx Implementations"
386+menu "Intel PXA2xx/PXA3xx Implementations"
387+
388+if PXA3xx
389+
390+menu "Supported PXA3xx Processor Variants"
391+
392+config CPU_PXA300
393+ bool "PXA300 (codename Monahans-L)"
394+
395+config CPU_PXA310
396+ bool "PXA310 (codename Monahans-LV)"
397+ select CPU_PXA300
398+
399+config CPU_PXA320
400+ bool "PXA320 (codename Monahans-P)"
401+
402+endmenu
403+
404+endif
405
406 choice
407 prompt "Select target board"
408@@ -41,6 +59,11 @@
409 bool "CompuLab EM-x270 platform"
410 select PXA27x
411
412+
413+config MACH_ZYLONITE
414+ bool "PXA3xx Development Platform"
415+ select PXA3xx
416+
417 config MACH_HX2750
418 bool "HP iPAQ hx2750"
419 select PXA27x
420@@ -228,6 +251,11 @@
421 help
422 Select code specific to PXA27x variants
423
424+config PXA3xx
425+ bool
426+ help
427+ Select code specific to PXA3xx variants
428+
429 config PXA_SHARP_C7xx
430 bool
431 select PXA_SSP
432--- linux-2.6.23.orig/arch/arm/mach-pxa/Makefile
433+++ linux-2.6.23/arch/arm/mach-pxa/Makefile
434@@ -6,6 +6,9 @@
435 obj-y += clock.o generic.o irq.o dma.o time.o
436 obj-$(CONFIG_PXA25x) += pxa25x.o
437 obj-$(CONFIG_PXA27x) += pxa27x.o
438+obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
439+obj-$(CONFIG_CPU_PXA300) += pxa300.o
440+obj-$(CONFIG_CPU_PXA320) += pxa320.o
441
442 # Specific board support
443 obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
444@@ -19,6 +22,12 @@
445 obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o sharpsl_pm.o poodle_pm.o
446 obj-$(CONFIG_MACH_TOSA) += tosa.o
447 obj-$(CONFIG_MACH_EM_X270) += em-x270.o
448+ifeq ($(CONFIG_MACH_ZYLONITE),y)
449+ obj-y += zylonite.o
450+ obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
451+ obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
452+endif
453+
454 obj-$(CONFIG_MACH_HX2750) += hx2750.o hx2750_test.o
455 obj-$(CONFIG_MACH_HTCUNIVERSAL) += htcuniversal/
456
457--- linux-2.6.23.orig/arch/arm/mach-pxa/clock.c
458+++ linux-2.6.23/arch/arm/mach-pxa/clock.c
459@@ -9,19 +9,15 @@
460 #include <linux/string.h>
461 #include <linux/clk.h>
462 #include <linux/spinlock.h>
463+#include <linux/platform_device.h>
464+#include <linux/delay.h>
465
466 #include <asm/arch/pxa-regs.h>
467 #include <asm/hardware.h>
468
469-struct clk {
470- struct list_head node;
471- unsigned long rate;
472- struct module *owner;
473- const char *name;
474- unsigned int enabled;
475- void (*enable)(void);
476- void (*disable)(void);
477-};
478+#include "devices.h"
479+#include "generic.h"
480+#include "clock.h"
481
482 static LIST_HEAD(clocks);
483 static DEFINE_MUTEX(clocks_mutex);
484@@ -33,7 +29,8 @@
485
486 mutex_lock(&clocks_mutex);
487 list_for_each_entry(p, &clocks, node) {
488- if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
489+ if (strcmp(id, p->name) == 0 &&
490+ (p->dev == NULL || p->dev == dev)) {
491 clk = p;
492 break;
493 }
494@@ -46,7 +43,6 @@
495
496 void clk_put(struct clk *clk)
497 {
498- module_put(clk->owner);
499 }
500 EXPORT_SYMBOL(clk_put);
501
502@@ -56,8 +52,12 @@
503
504 spin_lock_irqsave(&clocks_lock, flags);
505 if (clk->enabled++ == 0)
506- clk->enable();
507+ clk->ops->enable(clk);
508 spin_unlock_irqrestore(&clocks_lock, flags);
509+
510+ if (clk->delay)
511+ udelay(clk->delay);
512+
513 return 0;
514 }
515 EXPORT_SYMBOL(clk_enable);
516@@ -70,54 +70,75 @@
517
518 spin_lock_irqsave(&clocks_lock, flags);
519 if (--clk->enabled == 0)
520- clk->disable();
521+ clk->ops->disable(clk);
522 spin_unlock_irqrestore(&clocks_lock, flags);
523 }
524 EXPORT_SYMBOL(clk_disable);
525
526 unsigned long clk_get_rate(struct clk *clk)
527 {
528- return clk->rate;
529+ unsigned long rate;
530+
531+ rate = clk->rate;
532+ if (clk->ops->getrate)
533+ rate = clk->ops->getrate(clk);
534+
535+ return rate;
536 }
537 EXPORT_SYMBOL(clk_get_rate);
538
539
540-static void clk_gpio27_enable(void)
541+static void clk_gpio27_enable(struct clk *clk)
542 {
543 pxa_gpio_mode(GPIO11_3_6MHz_MD);
544 }
545
546-static void clk_gpio27_disable(void)
547+static void clk_gpio27_disable(struct clk *clk)
548 {
549 }
550
551-static struct clk clk_gpio27 = {
552- .name = "GPIO27_CLK",
553- .rate = 3686400,
554+static const struct clkops clk_gpio27_ops = {
555 .enable = clk_gpio27_enable,
556 .disable = clk_gpio27_disable,
557 };
558
559-int clk_register(struct clk *clk)
560+
561+void clk_cken_enable(struct clk *clk)
562 {
563- mutex_lock(&clocks_mutex);
564- list_add(&clk->node, &clocks);
565- mutex_unlock(&clocks_mutex);
566- return 0;
567+ CKEN |= 1 << clk->cken;
568 }
569-EXPORT_SYMBOL(clk_register);
570
571-void clk_unregister(struct clk *clk)
572+void clk_cken_disable(struct clk *clk)
573 {
574+ CKEN &= ~(1 << clk->cken);
575+}
576+
577+const struct clkops clk_cken_ops = {
578+ .enable = clk_cken_enable,
579+ .disable = clk_cken_disable,
580+};
581+
582+static struct clk common_clks[] = {
583+ {
584+ .name = "GPIO27_CLK",
585+ .ops = &clk_gpio27_ops,
586+ .rate = 3686400,
587+ },
588+};
589+
590+void clks_register(struct clk *clks, size_t num)
591+{
592+ int i;
593+
594 mutex_lock(&clocks_mutex);
595- list_del(&clk->node);
596+ for (i = 0; i < num; i++)
597+ list_add(&clks[i].node, &clocks);
598 mutex_unlock(&clocks_mutex);
599 }
600-EXPORT_SYMBOL(clk_unregister);
601
602 static int __init clk_init(void)
603 {
604- clk_register(&clk_gpio27);
605+ clks_register(common_clks, ARRAY_SIZE(common_clks));
606 return 0;
607 }
608 arch_initcall(clk_init);
609--- /dev/null
610+++ linux-2.6.23/arch/arm/mach-pxa/clock.h
611@@ -0,0 +1,43 @@
612+struct clk;
613+
614+struct clkops {
615+ void (*enable)(struct clk *);
616+ void (*disable)(struct clk *);
617+ unsigned long (*getrate)(struct clk *);
618+};
619+
620+struct clk {
621+ struct list_head node;
622+ const char *name;
623+ struct device *dev;
624+ const struct clkops *ops;
625+ unsigned long rate;
626+ unsigned int cken;
627+ unsigned int delay;
628+ unsigned int enabled;
629+};
630+
631+#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \
632+ { \
633+ .name = _name, \
634+ .dev = _dev, \
635+ .ops = &clk_cken_ops, \
636+ .rate = _rate, \
637+ .cken = CKEN_##_cken, \
638+ .delay = _delay, \
639+ }
640+
641+#define INIT_CK(_name, _cken, _ops, _dev) \
642+ { \
643+ .name = _name, \
644+ .dev = _dev, \
645+ .ops = _ops, \
646+ .cken = CKEN_##_cken, \
647+ }
648+
649+extern const struct clkops clk_cken_ops;
650+
651+void clk_cken_enable(struct clk *clk);
652+void clk_cken_disable(struct clk *clk);
653+
654+void clks_register(struct clk *clks, size_t num);
655--- linux-2.6.23.orig/arch/arm/mach-pxa/devices.h
656+++ linux-2.6.23/arch/arm/mach-pxa/devices.h
657@@ -9,3 +9,6 @@
658 extern struct platform_device pxa_device_i2s;
659 extern struct platform_device pxa_device_ficp;
660 extern struct platform_device pxa_device_rtc;
661+
662+extern struct platform_device pxa27x_device_i2c_power;
663+extern struct platform_device pxa27x_device_ohci;
664--- linux-2.6.23.orig/arch/arm/mach-pxa/generic.c
665+++ linux-2.6.23/arch/arm/mach-pxa/generic.c
666@@ -25,10 +25,6 @@
667 #include <linux/pm.h>
668 #include <linux/string.h>
669
670-#include <linux/sched.h>
671-#include <asm/cnt32_to_63.h>
672-#include <asm/div64.h>
673-
674 #include <asm/hardware.h>
675 #include <asm/irq.h>
676 #include <asm/system.h>
677@@ -48,66 +44,39 @@
678 #include "generic.h"
679
680 /*
681- * This is the PXA2xx sched_clock implementation. This has a resolution
682- * of at least 308ns and a maximum value that depends on the value of
683- * CLOCK_TICK_RATE.
684- *
685- * The return value is guaranteed to be monotonic in that range as
686- * long as there is always less than 582 seconds between successive
687- * calls to this function.
688+ * Get the clock frequency as reflected by CCCR and the turbo flag.
689+ * We assume these values have been applied via a fcs.
690+ * If info is not 0 we also display the current settings.
691 */
692-unsigned long long sched_clock(void)
693+unsigned int get_clk_frequency_khz(int info)
694 {
695- unsigned long long v = cnt32_to_63(OSCR);
696- /* Note: top bit ov v needs cleared unless multiplier is even. */
697-
698-#if CLOCK_TICK_RATE == 3686400
699- /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */
700- /* The <<1 is used to get rid of tick.hi top bit */
701- v *= 78125<<1;
702- do_div(v, 288<<1);
703-#elif CLOCK_TICK_RATE == 3250000
704- /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
705- v *= 4000;
706- do_div(v, 13);
707-#elif CLOCK_TICK_RATE == 3249600
708- /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
709- v *= 625000;
710- do_div(v, 2031);
711-#else
712-#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
713- /*
714- * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
715- * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
716- * years range and truncation to unsigned long long limits it to
717- * sched_clock's max range of ~584 years. This is nice but with
718- * higher computation cost.
719- */
720- {
721- union {
722- unsigned long long val;
723- struct { unsigned long lo, hi; };
724- } x;
725- unsigned long long y;
726-
727- x.val = v;
728- x.hi &= 0x7fffffff;
729- y = (unsigned long long)x.lo * NSEC_PER_SEC;
730- x.lo = y;
731- y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
732- x.hi = do_div(y, CLOCK_TICK_RATE);
733- do_div(x.val, CLOCK_TICK_RATE);
734- x.hi += y;
735- v = x.val;
736- }
737-#endif
738+ if (cpu_is_pxa21x() || cpu_is_pxa25x())
739+ return pxa25x_get_clk_frequency_khz(info);
740+ else if (cpu_is_pxa27x())
741+ return pxa27x_get_clk_frequency_khz(info);
742+ else
743+ return pxa3xx_get_clk_frequency_khz(info);
744+}
745+EXPORT_SYMBOL(get_clk_frequency_khz);
746
747- return v;
748+/*
749+ * Return the current memory clock frequency in units of 10kHz
750+ */
751+unsigned int get_memclk_frequency_10khz(void)
752+{
753+ if (cpu_is_pxa21x() || cpu_is_pxa25x())
754+ return pxa25x_get_memclk_frequency_10khz();
755+ else if (cpu_is_pxa27x())
756+ return pxa27x_get_memclk_frequency_10khz();
757+ else
758+ return pxa3xx_get_memclk_frequency_10khz();
759 }
760+EXPORT_SYMBOL(get_memclk_frequency_10khz);
761
762 /*
763 * Handy function to set GPIO alternate functions
764 */
765+int pxa_last_gpio;
766
767 int pxa_gpio_mode(int gpio_mode)
768 {
769@@ -116,7 +85,7 @@
770 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
771 int gafr;
772
773- if (gpio > PXA_LAST_GPIO)
774+ if (gpio > pxa_last_gpio)
775 return -EINVAL;
776
777 local_irq_save(flags);
778@@ -160,7 +129,7 @@
779 /*
780 * Routine to safely enable or disable a clock in the CKEN
781 */
782-void pxa_set_cken(int clock, int enable)
783+void __pxa_set_cken(int clock, int enable)
784 {
785 unsigned long flags;
786 local_irq_save(flags);
787@@ -173,7 +142,7 @@
788 local_irq_restore(flags);
789 }
790
791-EXPORT_SYMBOL(pxa_set_cken);
792+EXPORT_SYMBOL(__pxa_set_cken);
793
794 /*
795 * Intel PXA2xx internal register mapping.
796@@ -330,21 +299,80 @@
797 pxa_device_fb.dev.parent = parent_dev;
798 }
799
800+static struct resource pxa_resource_ffuart[] = {
801+ {
802+ .start = __PREG(FFUART),
803+ .end = __PREG(FFUART) + 35,
804+ .flags = IORESOURCE_MEM,
805+ }, {
806+ .start = IRQ_FFUART,
807+ .end = IRQ_FFUART,
808+ .flags = IORESOURCE_IRQ,
809+ }
810+};
811+
812 struct platform_device pxa_device_ffuart= {
813 .name = "pxa2xx-uart",
814 .id = 0,
815+ .resource = pxa_resource_ffuart,
816+ .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
817+};
818+
819+static struct resource pxa_resource_btuart[] = {
820+ {
821+ .start = __PREG(BTUART),
822+ .end = __PREG(BTUART) + 35,
823+ .flags = IORESOURCE_MEM,
824+ }, {
825+ .start = IRQ_BTUART,
826+ .end = IRQ_BTUART,
827+ .flags = IORESOURCE_IRQ,
828+ }
829 };
830+
831 struct platform_device pxa_device_btuart = {
832 .name = "pxa2xx-uart",
833 .id = 1,
834+ .resource = pxa_resource_btuart,
835+ .num_resources = ARRAY_SIZE(pxa_resource_btuart),
836 };
837+
838+static struct resource pxa_resource_stuart[] = {
839+ {
840+ .start = __PREG(STUART),
841+ .end = __PREG(STUART) + 35,
842+ .flags = IORESOURCE_MEM,
843+ }, {
844+ .start = IRQ_STUART,
845+ .end = IRQ_STUART,
846+ .flags = IORESOURCE_IRQ,
847+ }
848+};
849+
850 struct platform_device pxa_device_stuart = {
851 .name = "pxa2xx-uart",
852 .id = 2,
853+ .resource = pxa_resource_stuart,
854+ .num_resources = ARRAY_SIZE(pxa_resource_stuart),
855+};
856+
857+static struct resource pxa_resource_hwuart[] = {
858+ {
859+ .start = __PREG(HWUART),
860+ .end = __PREG(HWUART) + 47,
861+ .flags = IORESOURCE_MEM,
862+ }, {
863+ .start = IRQ_HWUART,
864+ .end = IRQ_HWUART,
865+ .flags = IORESOURCE_IRQ,
866+ }
867 };
868+
869 struct platform_device pxa_device_hwuart = {
870 .name = "pxa2xx-uart",
871 .id = 3,
872+ .resource = pxa_resource_hwuart,
873+ .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
874 };
875
876 void __init pxa_set_ffuart_info(struct platform_pxa_serial_funcs *info)
877--- linux-2.6.23.orig/arch/arm/mach-pxa/generic.h
878+++ linux-2.6.23/arch/arm/mach-pxa/generic.h
879@@ -15,14 +15,40 @@
880 extern void __init pxa_init_irq_low(void);
881 extern void __init pxa_init_irq_high(void);
882 extern void __init pxa_init_irq_gpio(int gpio_nr);
883+extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
884 extern void __init pxa25x_init_irq(void);
885 extern void __init pxa27x_init_irq(void);
886+extern void __init pxa3xx_init_irq(void);
887 extern void __init pxa_map_io(void);
888
889 extern unsigned int get_clk_frequency_khz(int info);
890+extern int pxa_last_gpio;
891
892 #define SET_BANK(__nr,__start,__size) \
893 mi->bank[__nr].start = (__start), \
894 mi->bank[__nr].size = (__size), \
895 mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
896
897+#ifdef CONFIG_PXA25x
898+extern unsigned pxa25x_get_clk_frequency_khz(int);
899+extern unsigned pxa25x_get_memclk_frequency_10khz(void);
900+#else
901+#define pxa25x_get_clk_frequency_khz(x) (0)
902+#define pxa25x_get_memclk_frequency_10khz() (0)
903+#endif
904+
905+#ifdef CONFIG_PXA27x
906+extern unsigned pxa27x_get_clk_frequency_khz(int);
907+extern unsigned pxa27x_get_memclk_frequency_10khz(void);
908+#else
909+#define pxa27x_get_clk_frequency_khz(x) (0)
910+#define pxa27x_get_memclk_frequency_10khz() (0)
911+#endif
912+
913+#ifdef CONFIG_PXA3xx
914+extern unsigned pxa3xx_get_clk_frequency_khz(int);
915+extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
916+#else
917+#define pxa3xx_get_clk_frequency_khz(x) (0)
918+#define pxa3xx_get_memclk_frequency_10khz() (0)
919+#endif
920--- linux-2.6.23.orig/arch/arm/mach-pxa/irq.c
921+++ linux-2.6.23/arch/arm/mach-pxa/irq.c
922@@ -38,33 +38,11 @@
923 ICMR |= (1 << irq);
924 }
925
926-static int pxa_set_wake(unsigned int irq, unsigned int on)
927-{
928- u32 mask;
929-
930- switch (irq) {
931- case IRQ_RTCAlrm:
932- mask = PWER_RTC;
933- break;
934-#ifdef CONFIG_PXA27x
935- /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
936-#endif
937- default:
938- return -EINVAL;
939- }
940- if (on)
941- PWER |= mask;
942- else
943- PWER &= ~mask;
944- return 0;
945-}
946-
947 static struct irq_chip pxa_internal_chip_low = {
948 .name = "SC",
949 .ack = pxa_mask_low_irq,
950 .mask = pxa_mask_low_irq,
951 .unmask = pxa_unmask_low_irq,
952- .set_wake = pxa_set_wake,
953 };
954
955 void __init pxa_init_irq_low(void)
956@@ -87,7 +65,7 @@
957 }
958 }
959
960-#ifdef CONFIG_PXA27x
961+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
962
963 /*
964 * This is for the second set of internal IRQs as found on the PXA27x.
965@@ -125,26 +103,6 @@
966 }
967 #endif
968
969-/* Note that if an input/irq line ever gets changed to an output during
970- * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
971- */
972-#ifdef CONFIG_PXA27x
973-
974-/* PXA27x: Various gpios can issue wakeup events. This logic only
975- * handles the simple cases, not the WEMUX2 and WEMUX3 options
976- */
977-#define PXA27x_GPIO_NOWAKE_MASK \
978- ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
979-#define WAKEMASK(gpio) \
980- (((gpio) <= 15) \
981- ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
982- : ((gpio == 35) ? (1 << 24) : 0))
983-#else
984-
985-/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
986-#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
987-#endif
988-
989 /*
990 * PXA GPIO edge detection for IRQs:
991 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
992@@ -158,11 +116,9 @@
993 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
994 {
995 int gpio, idx;
996- u32 mask;
997
998 gpio = IRQ_TO_GPIO(irq);
999 idx = gpio >> 5;
1000- mask = WAKEMASK(gpio);
1001
1002 if (type == IRQT_PROBE) {
1003 /* Don't mess with enabled GPIOs using preconfigured edges or
1004@@ -182,19 +138,15 @@
1005 if (type & __IRQT_RISEDGE) {
1006 /* printk("rising "); */
1007 __set_bit (gpio, GPIO_IRQ_rising_edge);
1008- PRER |= mask;
1009 } else {
1010 __clear_bit (gpio, GPIO_IRQ_rising_edge);
1011- PRER &= ~mask;
1012 }
1013
1014 if (type & __IRQT_FALEDGE) {
1015 /* printk("falling "); */
1016 __set_bit (gpio, GPIO_IRQ_falling_edge);
1017- PFER |= mask;
1018 } else {
1019 __clear_bit (gpio, GPIO_IRQ_falling_edge);
1020- PFER &= ~mask;
1021 }
1022
1023 /* printk("edges\n"); */
1024@@ -213,29 +165,12 @@
1025 GEDR0 = (1 << (irq - IRQ_GPIO0));
1026 }
1027
1028-static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
1029-{
1030- int gpio = IRQ_TO_GPIO(irq);
1031- u32 mask = WAKEMASK(gpio);
1032-
1033- if (!mask)
1034- return -EINVAL;
1035-
1036- if (on)
1037- PWER |= mask;
1038- else
1039- PWER &= ~mask;
1040- return 0;
1041-}
1042-
1043-
1044 static struct irq_chip pxa_low_gpio_chip = {
1045 .name = "GPIO-l",
1046 .ack = pxa_ack_low_gpio,
1047 .mask = pxa_mask_low_irq,
1048 .unmask = pxa_unmask_low_irq,
1049 .set_type = pxa_gpio_irq_type,
1050- .set_wake = pxa_set_gpio_wake,
1051 };
1052
1053 /*
1054@@ -342,13 +277,14 @@
1055 .mask = pxa_mask_muxed_gpio,
1056 .unmask = pxa_unmask_muxed_gpio,
1057 .set_type = pxa_gpio_irq_type,
1058- .set_wake = pxa_set_gpio_wake,
1059 };
1060
1061 void __init pxa_init_irq_gpio(int gpio_nr)
1062 {
1063 int irq, i;
1064
1065+ pxa_last_gpio = gpio_nr - 1;
1066+
1067 /* clear all GPIO edge detects */
1068 for (i = 0; i < gpio_nr; i += 32) {
1069 GFER(i) = 0;
1070@@ -375,3 +311,13 @@
1071 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
1072 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
1073 }
1074+
1075+void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
1076+{
1077+ pxa_internal_chip_low.set_wake = set_wake;
1078+#ifdef CONFIG_PXA27x
1079+ pxa_internal_chip_high.set_wake = set_wake;
1080+#endif
1081+ pxa_low_gpio_chip.set_wake = set_wake;
1082+ pxa_muxed_gpio_chip.set_wake = set_wake;
1083+}
1084--- /dev/null
1085+++ linux-2.6.23/arch/arm/mach-pxa/mfp.c
1086@@ -0,0 +1,235 @@
1087+/*
1088+ * linux/arch/arm/mach-pxa/mfp.c
1089+ *
1090+ * PXA3xx Multi-Function Pin Support
1091+ *
1092+ * Copyright (C) 2007 Marvell Internation Ltd.
1093+ *
1094+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
1095+ * initial version
1096+ *
1097+ * This program is free software; you can redistribute it and/or modify
1098+ * it under the terms of the GNU General Public License version 2 as
1099+ * published by the Free Software Foundation.
1100+ */
1101+
1102+#include <linux/module.h>
1103+#include <linux/kernel.h>
1104+#include <linux/init.h>
1105+#include <linux/io.h>
1106+
1107+#include <asm/hardware.h>
1108+#include <asm/arch/mfp.h>
1109+
1110+/* mfp_spin_lock is used to ensure that MFP register configuration
1111+ * (most likely a read-modify-write operation) is atomic, and that
1112+ * mfp_table[] is consistent
1113+ */
1114+static DEFINE_SPINLOCK(mfp_spin_lock);
1115+
1116+static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
1117+static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
1118+
1119+#define mfpr_readl(off) \
1120+ __raw_readl(mfpr_mmio_base + (off))
1121+
1122+#define mfpr_writel(off, val) \
1123+ __raw_writel(val, mfpr_mmio_base + (off))
1124+
1125+/*
1126+ * perform a read-back of any MFPR register to make sure the
1127+ * previous writings are finished
1128+ */
1129+#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
1130+
1131+static inline void __mfp_config(int pin, unsigned long val)
1132+{
1133+ unsigned long off = mfp_table[pin].mfpr_off;
1134+
1135+ mfp_table[pin].mfpr_val = val;
1136+ mfpr_writel(off, val);
1137+}
1138+
1139+void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num)
1140+{
1141+ int i, pin;
1142+ unsigned long val, flags;
1143+ mfp_cfg_t *mfp_cfg = mfp_cfgs;
1144+
1145+ spin_lock_irqsave(&mfp_spin_lock, flags);
1146+
1147+ for (i = 0; i < num; i++, mfp_cfg++) {
1148+ pin = MFP_CFG_PIN(*mfp_cfg);
1149+ val = MFP_CFG_VAL(*mfp_cfg);
1150+
1151+ BUG_ON(pin >= MFP_PIN_MAX);
1152+
1153+ __mfp_config(pin, val);
1154+ }
1155+
1156+ mfpr_sync();
1157+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1158+}
1159+
1160+unsigned long pxa3xx_mfp_read(int mfp)
1161+{
1162+ unsigned long val, flags;
1163+
1164+ BUG_ON(mfp >= MFP_PIN_MAX);
1165+
1166+ spin_lock_irqsave(&mfp_spin_lock, flags);
1167+ val = mfpr_readl(mfp_table[mfp].mfpr_off);
1168+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1169+
1170+ return val;
1171+}
1172+
1173+void pxa3xx_mfp_write(int mfp, unsigned long val)
1174+{
1175+ unsigned long flags;
1176+
1177+ BUG_ON(mfp >= MFP_PIN_MAX);
1178+
1179+ spin_lock_irqsave(&mfp_spin_lock, flags);
1180+ mfpr_writel(mfp_table[mfp].mfpr_off, val);
1181+ mfpr_sync();
1182+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1183+}
1184+
1185+void pxa3xx_mfp_set_afds(int mfp, int af, int ds)
1186+{
1187+ uint32_t mfpr_off, mfpr_val;
1188+ unsigned long flags;
1189+
1190+ BUG_ON(mfp >= MFP_PIN_MAX);
1191+
1192+ spin_lock_irqsave(&mfp_spin_lock, flags);
1193+ mfpr_off = mfp_table[mfp].mfpr_off;
1194+
1195+ mfpr_val = mfpr_readl(mfpr_off);
1196+ mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
1197+ mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
1198+ ((ds & 0x7) << MFPR_DRV_OFFSET));
1199+
1200+ mfpr_writel(mfpr_off, mfpr_val);
1201+ mfpr_sync();
1202+
1203+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1204+}
1205+
1206+void pxa3xx_mfp_set_rdh(int mfp, int rdh)
1207+{
1208+ uint32_t mfpr_off, mfpr_val;
1209+ unsigned long flags;
1210+
1211+ BUG_ON(mfp >= MFP_PIN_MAX);
1212+
1213+ spin_lock_irqsave(&mfp_spin_lock, flags);
1214+
1215+ mfpr_off = mfp_table[mfp].mfpr_off;
1216+
1217+ mfpr_val = mfpr_readl(mfpr_off);
1218+ mfpr_val &= ~MFPR_RDH_MASK;
1219+
1220+ if (likely(rdh))
1221+ mfpr_val |= (1u << MFPR_SS_OFFSET);
1222+
1223+ mfpr_writel(mfpr_off, mfpr_val);
1224+ mfpr_sync();
1225+
1226+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1227+}
1228+
1229+void pxa3xx_mfp_set_lpm(int mfp, int lpm)
1230+{
1231+ uint32_t mfpr_off, mfpr_val;
1232+ unsigned long flags;
1233+
1234+ BUG_ON(mfp >= MFP_PIN_MAX);
1235+
1236+ spin_lock_irqsave(&mfp_spin_lock, flags);
1237+
1238+ mfpr_off = mfp_table[mfp].mfpr_off;
1239+ mfpr_val = mfpr_readl(mfpr_off);
1240+ mfpr_val &= ~MFPR_LPM_MASK;
1241+
1242+ if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
1243+ if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
1244+ if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
1245+ if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
1246+ if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
1247+
1248+ mfpr_writel(mfpr_off, mfpr_val);
1249+ mfpr_sync();
1250+
1251+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1252+}
1253+
1254+void pxa3xx_mfp_set_pull(int mfp, int pull)
1255+{
1256+ uint32_t mfpr_off, mfpr_val;
1257+ unsigned long flags;
1258+
1259+ BUG_ON(mfp >= MFP_PIN_MAX);
1260+
1261+ spin_lock_irqsave(&mfp_spin_lock, flags);
1262+
1263+ mfpr_off = mfp_table[mfp].mfpr_off;
1264+ mfpr_val = mfpr_readl(mfpr_off);
1265+ mfpr_val &= ~MFPR_PULL_MASK;
1266+ mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET);
1267+
1268+ mfpr_writel(mfpr_off, mfpr_val);
1269+ mfpr_sync();
1270+
1271+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1272+}
1273+
1274+void pxa3xx_mfp_set_edge(int mfp, int edge)
1275+{
1276+ uint32_t mfpr_off, mfpr_val;
1277+ unsigned long flags;
1278+
1279+ BUG_ON(mfp >= MFP_PIN_MAX);
1280+
1281+ spin_lock_irqsave(&mfp_spin_lock, flags);
1282+
1283+ mfpr_off = mfp_table[mfp].mfpr_off;
1284+ mfpr_val = mfpr_readl(mfpr_off);
1285+
1286+ mfpr_val &= ~MFPR_EDGE_MASK;
1287+ mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
1288+ mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
1289+
1290+ mfpr_writel(mfpr_off, mfpr_val);
1291+ mfpr_sync();
1292+
1293+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1294+}
1295+
1296+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
1297+{
1298+ struct pxa3xx_mfp_addr_map *p;
1299+ unsigned long offset, flags;
1300+ int i;
1301+
1302+ spin_lock_irqsave(&mfp_spin_lock, flags);
1303+
1304+ for (p = map; p->start != MFP_PIN_INVALID; p++) {
1305+ offset = p->offset;
1306+ i = p->start;
1307+
1308+ do {
1309+ mfp_table[i].mfpr_off = offset;
1310+ mfp_table[i].mfpr_val = 0;
1311+ offset += 4; i++;
1312+ } while ((i <= p->end) && (p->end != -1));
1313+ }
1314+
1315+ spin_unlock_irqrestore(&mfp_spin_lock, flags);
1316+}
1317+
1318+void __init pxa3xx_init_mfp(void)
1319+{
1320+ memset(mfp_table, 0, sizeof(mfp_table));
1321+}
1322--- linux-2.6.23.orig/arch/arm/mach-pxa/pxa25x.c
1323+++ linux-2.6.23/arch/arm/mach-pxa/pxa25x.c
1324@@ -30,6 +30,7 @@
1325
1326 #include "generic.h"
1327 #include "devices.h"
1328+#include "clock.h"
1329
1330 /*
1331 * Various clock factors driven by the CCCR register.
1332@@ -53,7 +54,7 @@
1333 * We assume these values have been applied via a fcs.
1334 * If info is not 0 we also display the current settings.
1335 */
1336-unsigned int get_clk_frequency_khz(int info)
1337+unsigned int pxa25x_get_clk_frequency_khz(int info)
1338 {
1339 unsigned long cccr, turbo;
1340 unsigned int l, L, m, M, n2, N;
1341@@ -86,27 +87,48 @@
1342 return (turbo & 1) ? (N/1000) : (M/1000);
1343 }
1344
1345-EXPORT_SYMBOL(get_clk_frequency_khz);
1346-
1347 /*
1348 * Return the current memory clock frequency in units of 10kHz
1349 */
1350-unsigned int get_memclk_frequency_10khz(void)
1351+unsigned int pxa25x_get_memclk_frequency_10khz(void)
1352 {
1353 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
1354 }
1355
1356-EXPORT_SYMBOL(get_memclk_frequency_10khz);
1357-
1358-/*
1359- * Return the current LCD clock frequency in units of 10kHz
1360- */
1361-unsigned int get_lcdclk_frequency_10khz(void)
1362+static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
1363 {
1364- return get_memclk_frequency_10khz();
1365+ return pxa25x_get_memclk_frequency_10khz() * 10000;
1366 }
1367
1368-EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
1369+static const struct clkops clk_pxa25x_lcd_ops = {
1370+ .enable = clk_cken_enable,
1371+ .disable = clk_cken_disable,
1372+ .getrate = clk_pxa25x_lcd_getrate,
1373+};
1374+
1375+/*
1376+ * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
1377+ * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
1378+ * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
1379+ */
1380+static struct clk pxa25x_clks[] = {
1381+ INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
1382+ INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
1383+ INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
1384+ INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
1385+ INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
1386+ INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
1387+ INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
1388+ INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
1389+ /*
1390+ INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
1391+ INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
1392+ INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
1393+ INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
1394+ INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
1395+ */
1396+ INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
1397+};
1398
1399 #ifdef CONFIG_PM
1400
1401@@ -207,10 +229,52 @@
1402 }
1403 #endif
1404
1405+/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
1406+ */
1407+
1408+static int pxa25x_set_wake(unsigned int irq, unsigned int on)
1409+{
1410+ int gpio = IRQ_TO_GPIO(irq);
1411+ uint32_t gpio_bit, mask = 0;
1412+
1413+ if (gpio >= 0 && gpio <= 15) {
1414+ gpio_bit = GPIO_bit(gpio);
1415+ mask = gpio_bit;
1416+ if (on) {
1417+ if (GRER(gpio) | gpio_bit)
1418+ PRER |= gpio_bit;
1419+ else
1420+ PRER &= ~gpio_bit;
1421+
1422+ if (GFER(gpio) | gpio_bit)
1423+ PFER |= gpio_bit;
1424+ else
1425+ PFER &= ~gpio_bit;
1426+ }
1427+ goto set_pwer;
1428+ }
1429+
1430+ if (irq == IRQ_RTCAlrm) {
1431+ mask = PWER_RTC;
1432+ goto set_pwer;
1433+ }
1434+
1435+ return -EINVAL;
1436+
1437+set_pwer:
1438+ if (on)
1439+ PWER |= mask;
1440+ else
1441+ PWER &=~mask;
1442+
1443+ return 0;
1444+}
1445+
1446 void __init pxa25x_init_irq(void)
1447 {
1448 pxa_init_irq_low();
1449 pxa_init_irq_gpio(85);
1450+ pxa_init_irq_set_wake(pxa25x_set_wake);
1451 }
1452
1453 static struct platform_device *pxa25x_devices[] __initdata = {
1454@@ -231,6 +295,8 @@
1455 int ret = 0;
1456
1457 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
1458+ clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
1459+
1460 if ((ret = pxa_init_dma(16)))
1461 return ret;
1462 #ifdef CONFIG_PM
1463--- linux-2.6.23.orig/arch/arm/mach-pxa/pxa27x.c
1464+++ linux-2.6.23/arch/arm/mach-pxa/pxa27x.c
1465@@ -27,6 +27,7 @@
1466
1467 #include "generic.h"
1468 #include "devices.h"
1469+#include "clock.h"
1470
1471 /* Crystal clock: 13MHz */
1472 #define BASE_CLK 13000000
1473@@ -36,7 +37,7 @@
1474 * We assume these values have been applied via a fcs.
1475 * If info is not 0 we also display the current settings.
1476 */
1477-unsigned int get_clk_frequency_khz( int info)
1478+unsigned int pxa27x_get_clk_frequency_khz(int info)
1479 {
1480 unsigned long ccsr, clkcfg;
1481 unsigned int l, L, m, M, n2, N, S;
1482@@ -79,7 +80,7 @@
1483 * Return the current mem clock frequency in units of 10kHz as
1484 * reflected by CCCR[A], B, and L
1485 */
1486-unsigned int get_memclk_frequency_10khz(void)
1487+unsigned int pxa27x_get_memclk_frequency_10khz(void)
1488 {
1489 unsigned long ccsr, clkcfg;
1490 unsigned int l, L, m, M;
1491@@ -104,7 +105,7 @@
1492 /*
1493 * Return the current LCD clock frequency in units of 10kHz as
1494 */
1495-unsigned int get_lcdclk_frequency_10khz(void)
1496+static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
1497 {
1498 unsigned long ccsr;
1499 unsigned int l, L, k, K;
1500@@ -120,9 +121,47 @@
1501 return (K / 10000);
1502 }
1503
1504-EXPORT_SYMBOL(get_clk_frequency_khz);
1505-EXPORT_SYMBOL(get_memclk_frequency_10khz);
1506-EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
1507+static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
1508+{
1509+ return pxa27x_get_lcdclk_frequency_10khz() * 10000;
1510+}
1511+
1512+static const struct clkops clk_pxa27x_lcd_ops = {
1513+ .enable = clk_cken_enable,
1514+ .disable = clk_cken_disable,
1515+ .getrate = clk_pxa27x_lcd_getrate,
1516+};
1517+
1518+static struct clk pxa27x_clks[] = {
1519+ INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
1520+ INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
1521+
1522+ INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
1523+ INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
1524+ INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
1525+
1526+ INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
1527+ INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
1528+ INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
1529+ INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
1530+ INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
1531+
1532+ INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev),
1533+ INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
1534+ INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
1535+
1536+ /*
1537+ INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
1538+ INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL),
1539+ INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL),
1540+ INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL),
1541+ INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
1542+ INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
1543+ INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
1544+ INIT_CKEN("IMCLK", IM, 0, 0, NULL),
1545+ INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
1546+ */
1547+};
1548
1549 #ifdef CONFIG_PM
1550
1551@@ -269,6 +308,69 @@
1552 }
1553 #endif
1554
1555+/* PXA27x: Various gpios can issue wakeup events. This logic only
1556+ * handles the simple cases, not the WEMUX2 and WEMUX3 options
1557+ */
1558+#define PXA27x_GPIO_NOWAKE_MASK \
1559+ ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
1560+#define WAKEMASK(gpio) \
1561+ (((gpio) <= 15) \
1562+ ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
1563+ : ((gpio == 35) ? (1 << 24) : 0))
1564+
1565+static int pxa27x_set_wake(unsigned int irq, unsigned int on)
1566+{
1567+ int gpio = IRQ_TO_GPIO(irq);
1568+ uint32_t mask;
1569+
1570+ if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
1571+ if (WAKEMASK(gpio) == 0)
1572+ return -EINVAL;
1573+
1574+ mask = WAKEMASK(gpio);
1575+
1576+ if (on) {
1577+ if (GRER(gpio) | GPIO_bit(gpio))
1578+ PRER |= mask;
1579+ else
1580+ PRER &= ~mask;
1581+
1582+ if (GFER(gpio) | GPIO_bit(gpio))
1583+ PFER |= mask;
1584+ else
1585+ PFER &= ~mask;
1586+ }
1587+ goto set_pwer;
1588+ }
1589+
1590+ switch (irq) {
1591+ case IRQ_RTCAlrm:
1592+ mask = PWER_RTC;
1593+ break;
1594+ case IRQ_USB:
1595+ mask = 1u << 26;
1596+ break;
1597+ default:
1598+ return -EINVAL;
1599+ }
1600+
1601+set_pwer:
1602+ if (on)
1603+ PWER |= mask;
1604+ else
1605+ PWER &=~mask;
1606+
1607+ return 0;
1608+}
1609+
1610+void __init pxa27x_init_irq(void)
1611+{
1612+ pxa_init_irq_low();
1613+ pxa_init_irq_high();
1614+ pxa_init_irq_gpio(128);
1615+ pxa_init_irq_set_wake(pxa27x_set_wake);
1616+}
1617+
1618 /*
1619 * device registration specific to PXA27x.
1620 */
1621@@ -288,7 +390,7 @@
1622 },
1623 };
1624
1625-static struct platform_device pxa27x_device_ohci = {
1626+struct platform_device pxa27x_device_ohci = {
1627 .name = "pxa27x-ohci",
1628 .id = -1,
1629 .dev = {
1630@@ -316,7 +418,7 @@
1631 },
1632 };
1633
1634-static struct platform_device pxa27x_device_i2c_power = {
1635+struct platform_device pxa27x_device_i2c_power = {
1636 .name = "pxa2xx-i2c",
1637 .id = 1,
1638 .resource = i2c_power_resources,
1639@@ -338,17 +440,12 @@
1640 &pxa27x_device_ohci,
1641 };
1642
1643-void __init pxa27x_init_irq(void)
1644-{
1645- pxa_init_irq_low();
1646- pxa_init_irq_high();
1647- pxa_init_irq_gpio(128);
1648-}
1649-
1650 static int __init pxa27x_init(void)
1651 {
1652 int ret = 0;
1653 if (cpu_is_pxa27x()) {
1654+ clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
1655+
1656 if ((ret = pxa_init_dma(32)))
1657 return ret;
1658 #ifdef CONFIG_PM
1659--- /dev/null
1660+++ linux-2.6.23/arch/arm/mach-pxa/pxa300.c
1661@@ -0,0 +1,93 @@
1662+/*
1663+ * linux/arch/arm/mach-pxa/pxa300.c
1664+ *
1665+ * Code specific to PXA300/PXA310
1666+ *
1667+ * Copyright (C) 2007 Marvell Internation Ltd.
1668+ *
1669+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
1670+ * initial version
1671+ *
1672+ * This program is free software; you can redistribute it and/or modify
1673+ * it under the terms of the GNU General Public License version 2 as
1674+ * published by the Free Software Foundation.
1675+ */
1676+
1677+#include <linux/module.h>
1678+#include <linux/kernel.h>
1679+
1680+#include <asm/hardware.h>
1681+#include <asm/arch/mfp-pxa300.h>
1682+
1683+static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
1684+
1685+ MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
1686+ MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
1687+ MFP_ADDR_X(GPIO27, GPIO127, 0x0400),
1688+ MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec),
1689+
1690+ MFP_ADDR(nBE0, 0x0204),
1691+ MFP_ADDR(nBE1, 0x0208),
1692+
1693+ MFP_ADDR(nLUA, 0x0244),
1694+ MFP_ADDR(nLLA, 0x0254),
1695+
1696+ MFP_ADDR(DF_CLE_nOE, 0x0240),
1697+ MFP_ADDR(DF_nRE_nOE, 0x0200),
1698+ MFP_ADDR(DF_ALE_nWE, 0x020C),
1699+ MFP_ADDR(DF_INT_RnB, 0x00C8),
1700+ MFP_ADDR(DF_nCS0, 0x0248),
1701+ MFP_ADDR(DF_nCS1, 0x0278),
1702+ MFP_ADDR(DF_nWE, 0x00CC),
1703+
1704+ MFP_ADDR(DF_ADDR0, 0x0210),
1705+ MFP_ADDR(DF_ADDR1, 0x0214),
1706+ MFP_ADDR(DF_ADDR2, 0x0218),
1707+ MFP_ADDR(DF_ADDR3, 0x021C),
1708+
1709+ MFP_ADDR(DF_IO0, 0x0220),
1710+ MFP_ADDR(DF_IO1, 0x0228),
1711+ MFP_ADDR(DF_IO2, 0x0230),
1712+ MFP_ADDR(DF_IO3, 0x0238),
1713+ MFP_ADDR(DF_IO4, 0x0258),
1714+ MFP_ADDR(DF_IO5, 0x0260),
1715+ MFP_ADDR(DF_IO6, 0x0268),
1716+ MFP_ADDR(DF_IO7, 0x0270),
1717+ MFP_ADDR(DF_IO8, 0x0224),
1718+ MFP_ADDR(DF_IO9, 0x022C),
1719+ MFP_ADDR(DF_IO10, 0x0234),
1720+ MFP_ADDR(DF_IO11, 0x023C),
1721+ MFP_ADDR(DF_IO12, 0x025C),
1722+ MFP_ADDR(DF_IO13, 0x0264),
1723+ MFP_ADDR(DF_IO14, 0x026C),
1724+ MFP_ADDR(DF_IO15, 0x0274),
1725+
1726+ MFP_ADDR_END,
1727+};
1728+
1729+/* override pxa300 MFP register addresses */
1730+static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
1731+ MFP_ADDR_X(GPIO30, GPIO98, 0x0418),
1732+ MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
1733+
1734+ MFP_ADDR(ULPI_STP, 0x040C),
1735+ MFP_ADDR(ULPI_NXT, 0x0410),
1736+ MFP_ADDR(ULPI_DIR, 0x0414),
1737+
1738+ MFP_ADDR_END,
1739+};
1740+
1741+static int __init pxa300_init(void)
1742+{
1743+ if (cpu_is_pxa300() || cpu_is_pxa310()) {
1744+ pxa3xx_init_mfp();
1745+ pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
1746+ }
1747+
1748+ if (cpu_is_pxa310())
1749+ pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
1750+
1751+ return 0;
1752+}
1753+
1754+core_initcall(pxa300_init);
1755--- /dev/null
1756+++ linux-2.6.23/arch/arm/mach-pxa/pxa320.c
1757@@ -0,0 +1,88 @@
1758+/*
1759+ * linux/arch/arm/mach-pxa/pxa320.c
1760+ *
1761+ * Code specific to PXA320
1762+ *
1763+ * Copyright (C) 2007 Marvell Internation Ltd.
1764+ *
1765+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
1766+ * initial version
1767+ *
1768+ * This program is free software; you can redistribute it and/or modify
1769+ * it under the terms of the GNU General Public License version 2 as
1770+ * published by the Free Software Foundation.
1771+ */
1772+
1773+#include <linux/module.h>
1774+#include <linux/kernel.h>
1775+
1776+#include <asm/hardware.h>
1777+#include <asm/arch/mfp.h>
1778+#include <asm/arch/mfp-pxa320.h>
1779+
1780+static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
1781+
1782+ MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
1783+ MFP_ADDR_X(GPIO5, GPIO26, 0x028C),
1784+ MFP_ADDR_X(GPIO27, GPIO62, 0x0400),
1785+ MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
1786+ MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
1787+ MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
1788+ MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
1789+ MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494),
1790+ MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0),
1791+
1792+ MFP_ADDR(nXCVREN, 0x0138),
1793+ MFP_ADDR(DF_CLE_nOE, 0x0204),
1794+ MFP_ADDR(DF_nADV1_ALE, 0x0208),
1795+ MFP_ADDR(DF_SCLK_S, 0x020C),
1796+ MFP_ADDR(DF_SCLK_E, 0x0210),
1797+ MFP_ADDR(nBE0, 0x0214),
1798+ MFP_ADDR(nBE1, 0x0218),
1799+ MFP_ADDR(DF_nADV2_ALE, 0x021C),
1800+ MFP_ADDR(DF_INT_RnB, 0x0220),
1801+ MFP_ADDR(DF_nCS0, 0x0224),
1802+ MFP_ADDR(DF_nCS1, 0x0228),
1803+ MFP_ADDR(DF_nWE, 0x022C),
1804+ MFP_ADDR(DF_nRE_nOE, 0x0230),
1805+ MFP_ADDR(nLUA, 0x0234),
1806+ MFP_ADDR(nLLA, 0x0238),
1807+ MFP_ADDR(DF_ADDR0, 0x023C),
1808+ MFP_ADDR(DF_ADDR1, 0x0240),
1809+ MFP_ADDR(DF_ADDR2, 0x0244),
1810+ MFP_ADDR(DF_ADDR3, 0x0248),
1811+ MFP_ADDR(DF_IO0, 0x024C),
1812+ MFP_ADDR(DF_IO8, 0x0250),
1813+ MFP_ADDR(DF_IO1, 0x0254),
1814+ MFP_ADDR(DF_IO9, 0x0258),
1815+ MFP_ADDR(DF_IO2, 0x025C),
1816+ MFP_ADDR(DF_IO10, 0x0260),
1817+ MFP_ADDR(DF_IO3, 0x0264),
1818+ MFP_ADDR(DF_IO11, 0x0268),
1819+ MFP_ADDR(DF_IO4, 0x026C),
1820+ MFP_ADDR(DF_IO12, 0x0270),
1821+ MFP_ADDR(DF_IO5, 0x0274),
1822+ MFP_ADDR(DF_IO13, 0x0278),
1823+ MFP_ADDR(DF_IO6, 0x027C),
1824+ MFP_ADDR(DF_IO14, 0x0280),
1825+ MFP_ADDR(DF_IO7, 0x0284),
1826+ MFP_ADDR(DF_IO15, 0x0288),
1827+
1828+ MFP_ADDR_END,
1829+};
1830+
1831+static void __init pxa320_init_mfp(void)
1832+{
1833+ pxa3xx_init_mfp();
1834+ pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
1835+}
1836+
1837+static int __init pxa320_init(void)
1838+{
1839+ if (cpu_is_pxa320())
1840+ pxa320_init_mfp();
1841+
1842+ return 0;
1843+}
1844+
1845+core_initcall(pxa320_init);
1846--- /dev/null
1847+++ linux-2.6.23/arch/arm/mach-pxa/pxa3xx.c
1848@@ -0,0 +1,216 @@
1849+/*
1850+ * linux/arch/arm/mach-pxa/pxa3xx.c
1851+ *
1852+ * code specific to pxa3xx aka Monahans
1853+ *
1854+ * Copyright (C) 2006 Marvell International Ltd.
1855+ *
1856+ * 2007-09-02: eric miao <eric.y.miao@gmail.com>
1857+ * initial version
1858+ *
1859+ * This program is free software; you can redistribute it and/or modify
1860+ * it under the terms of the GNU General Public License version 2 as
1861+ * published by the Free Software Foundation.
1862+ */
1863+
1864+#include <linux/module.h>
1865+#include <linux/kernel.h>
1866+#include <linux/init.h>
1867+#include <linux/pm.h>
1868+#include <linux/platform_device.h>
1869+#include <linux/irq.h>
1870+
1871+#include <asm/hardware.h>
1872+#include <asm/arch/pxa3xx-regs.h>
1873+#include <asm/arch/ohci.h>
1874+#include <asm/arch/pm.h>
1875+#include <asm/arch/dma.h>
1876+#include <asm/arch/ssp.h>
1877+
1878+#include "generic.h"
1879+#include "devices.h"
1880+#include "clock.h"
1881+
1882+/* Crystal clock: 13MHz */
1883+#define BASE_CLK 13000000
1884+
1885+/* Ring Oscillator Clock: 60MHz */
1886+#define RO_CLK 60000000
1887+
1888+#define ACCR_D0CS (1 << 26)
1889+
1890+/* crystal frequency to static memory controller multiplier (SMCFS) */
1891+static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
1892+
1893+/* crystal frequency to HSIO bus frequency multiplier (HSS) */
1894+static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
1895+
1896+/*
1897+ * Get the clock frequency as reflected by CCSR and the turbo flag.
1898+ * We assume these values have been applied via a fcs.
1899+ * If info is not 0 we also display the current settings.
1900+ */
1901+unsigned int pxa3xx_get_clk_frequency_khz(int info)
1902+{
1903+ unsigned long acsr, xclkcfg;
1904+ unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
1905+
1906+ /* Read XCLKCFG register turbo bit */
1907+ __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
1908+ t = xclkcfg & 0x1;
1909+
1910+ acsr = ACSR;
1911+
1912+ xl = acsr & 0x1f;
1913+ xn = (acsr >> 8) & 0x7;
1914+ hss = (acsr >> 14) & 0x3;
1915+
1916+ XL = xl * BASE_CLK;
1917+ XN = xn * XL;
1918+
1919+ ro = acsr & ACCR_D0CS;
1920+
1921+ CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
1922+ HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
1923+
1924+ if (info) {
1925+ pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
1926+ RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
1927+ (ro) ? "" : "in");
1928+ pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
1929+ XL / 1000000, (XL % 1000000) / 10000, xl);
1930+ pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
1931+ XN / 1000000, (XN % 1000000) / 10000, xn,
1932+ (t) ? "" : "in");
1933+ pr_info("HSIO bus clock: %d.%02dMHz\n",
1934+ HSS / 1000000, (HSS % 1000000) / 10000);
1935+ }
1936+
1937+ return CLK;
1938+}
1939+
1940+/*
1941+ * Return the current static memory controller clock frequency
1942+ * in units of 10kHz
1943+ */
1944+unsigned int pxa3xx_get_memclk_frequency_10khz(void)
1945+{
1946+ unsigned long acsr;
1947+ unsigned int smcfs, clk = 0;
1948+
1949+ acsr = ACSR;
1950+
1951+ smcfs = (acsr >> 23) & 0x7;
1952+ clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
1953+
1954+ return (clk / 10000);
1955+}
1956+
1957+/*
1958+ * Return the current HSIO bus clock frequency
1959+ */
1960+static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
1961+{
1962+ unsigned long acsr;
1963+ unsigned int hss, hsio_clk;
1964+
1965+ acsr = ACSR;
1966+
1967+ hss = (acsr >> 14) & 0x3;
1968+ hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
1969+
1970+ return hsio_clk;
1971+}
1972+
1973+static void clk_pxa3xx_cken_enable(struct clk *clk)
1974+{
1975+ unsigned long mask = 1ul << (clk->cken & 0x1f);
1976+
1977+ local_irq_disable();
1978+
1979+ if (clk->cken < 32)
1980+ CKENA |= mask;
1981+ else
1982+ CKENB |= mask;
1983+
1984+ local_irq_enable();
1985+}
1986+
1987+static void clk_pxa3xx_cken_disable(struct clk *clk)
1988+{
1989+ unsigned long mask = 1ul << (clk->cken & 0x1f);
1990+
1991+ local_irq_disable();
1992+
1993+ if (clk->cken < 32)
1994+ CKENA &= ~mask;
1995+ else
1996+ CKENB &= ~mask;
1997+
1998+ local_irq_enable();
1999+}
2000+
2001+static const struct clkops clk_pxa3xx_hsio_ops = {
2002+ .enable = clk_pxa3xx_cken_enable,
2003+ .disable = clk_pxa3xx_cken_disable,
2004+ .getrate = clk_pxa3xx_hsio_getrate,
2005+};
2006+
2007+static struct clk pxa3xx_clks[] = {
2008+ INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
2009+ INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
2010+
2011+ INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
2012+ INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
2013+ INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
2014+
2015+ INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
2016+ INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
2017+};
2018+
2019+void __init pxa3xx_init_irq(void)
2020+{
2021+ /* enable CP6 access */
2022+ u32 value;
2023+ __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
2024+ value |= (1 << 6);
2025+ __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
2026+
2027+ pxa_init_irq_low();
2028+ pxa_init_irq_high();
2029+ pxa_init_irq_gpio(128);
2030+}
2031+
2032+/*
2033+ * device registration specific to PXA3xx.
2034+ */
2035+
2036+static struct platform_device *devices[] __initdata = {
2037+ &pxa_device_mci,
2038+ &pxa_device_udc,
2039+ &pxa_device_fb,
2040+ &pxa_device_ffuart,
2041+ &pxa_device_btuart,
2042+ &pxa_device_stuart,
2043+ &pxa_device_i2c,
2044+ &pxa_device_i2s,
2045+ &pxa_device_ficp,
2046+ &pxa_device_rtc,
2047+};
2048+
2049+static int __init pxa3xx_init(void)
2050+{
2051+ int ret = 0;
2052+
2053+ if (cpu_is_pxa3xx()) {
2054+ clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
2055+
2056+ if ((ret = pxa_init_dma(32)))
2057+ return ret;
2058+
2059+ return platform_add_devices(devices, ARRAY_SIZE(devices));
2060+ }
2061+ return 0;
2062+}
2063+
2064+subsys_initcall(pxa3xx_init);
2065--- linux-2.6.23.orig/arch/arm/mach-pxa/time.c
2066+++ linux-2.6.23/arch/arm/mach-pxa/time.c
2067@@ -16,10 +16,48 @@
2068 #include <linux/init.h>
2069 #include <linux/interrupt.h>
2070 #include <linux/clockchips.h>
2071+#include <linux/sched.h>
2072
2073+#include <asm/div64.h>
2074+#include <asm/cnt32_to_63.h>
2075 #include <asm/mach/irq.h>
2076 #include <asm/mach/time.h>
2077 #include <asm/arch/pxa-regs.h>
2078+#include <asm/mach-types.h>
2079+
2080+/*
2081+ * This is PXA's sched_clock implementation. This has a resolution
2082+ * of at least 308 ns and a maximum value of 208 days.
2083+ *
2084+ * The return value is guaranteed to be monotonic in that range as
2085+ * long as there is always less than 582 seconds between successive
2086+ * calls to sched_clock() which should always be the case in practice.
2087+ */
2088+
2089+#define OSCR2NS_SCALE_FACTOR 10
2090+
2091+static unsigned long oscr2ns_scale;
2092+
2093+static void __init set_oscr2ns_scale(unsigned long oscr_rate)
2094+{
2095+ unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
2096+ do_div(v, oscr_rate);
2097+ oscr2ns_scale = v;
2098+ /*
2099+ * We want an even value to automatically clear the top bit
2100+ * returned by cnt32_to_63() without an additional run time
2101+ * instruction. So if the LSB is 1 then round it up.
2102+ */
2103+ if (oscr2ns_scale & 1)
2104+ oscr2ns_scale++;
2105+}
2106+
2107+unsigned long long sched_clock(void)
2108+{
2109+ unsigned long long v = cnt32_to_63(OSCR);
2110+ return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
2111+}
2112+
2113
2114 static irqreturn_t
2115 pxa_ost0_interrupt(int irq, void *dev_id)
2116@@ -149,18 +187,29 @@
2117
2118 static void __init pxa_timer_init(void)
2119 {
2120+ unsigned long clock_tick_rate;
2121+
2122 OIER = 0;
2123 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
2124
2125+ if (cpu_is_pxa21x() || cpu_is_pxa25x())
2126+ clock_tick_rate = 3686400;
2127+ else if (machine_is_mainstone())
2128+ clock_tick_rate = 3249600;
2129+ else
2130+ clock_tick_rate = 3250000;
2131+
2132+ set_oscr2ns_scale(clock_tick_rate);
2133+
2134 ckevt_pxa_osmr0.mult =
2135- div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
2136+ div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
2137 ckevt_pxa_osmr0.max_delta_ns =
2138 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
2139 ckevt_pxa_osmr0.min_delta_ns =
2140 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
2141
2142 cksrc_pxa_oscr0.mult =
2143- clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
2144+ clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
2145
2146 setup_irq(IRQ_OST0, &pxa_ost0_irq);
2147
2148--- /dev/null
2149+++ linux-2.6.23/arch/arm/mach-pxa/zylonite.c
2150@@ -0,0 +1,184 @@
2151+/*
2152+ * linux/arch/arm/mach-pxa/zylonite.c
2153+ *
2154+ * Support for the PXA3xx Development Platform (aka Zylonite)
2155+ *
2156+ * Copyright (C) 2006 Marvell International Ltd.
2157+ *
2158+ * 2007-09-04: eric miao <eric.y.miao@gmail.com>
2159+ * rewrite to align with latest kernel
2160+ *
2161+ * This program is free software; you can redistribute it and/or modify
2162+ * it under the terms of the GNU General Public License version 2 as
2163+ * published by the Free Software Foundation.
2164+ */
2165+
2166+#include <linux/module.h>
2167+#include <linux/kernel.h>
2168+#include <linux/interrupt.h>
2169+#include <linux/init.h>
2170+#include <linux/platform_device.h>
2171+
2172+#include <asm/mach-types.h>
2173+#include <asm/mach/arch.h>
2174+#include <asm/hardware.h>
2175+#include <asm/arch/gpio.h>
2176+#include <asm/arch/pxafb.h>
2177+#include <asm/arch/zylonite.h>
2178+
2179+#include "generic.h"
2180+
2181+int gpio_backlight;
2182+int gpio_eth_irq;
2183+
2184+int lcd_id;
2185+int lcd_orientation;
2186+
2187+static struct resource smc91x_resources[] = {
2188+ [0] = {
2189+ .start = ZYLONITE_ETH_PHYS + 0x300,
2190+ .end = ZYLONITE_ETH_PHYS + 0xfffff,
2191+ .flags = IORESOURCE_MEM,
2192+ },
2193+ [1] = {
2194+ .start = -1, /* for run-time assignment */
2195+ .end = -1,
2196+ .flags = IORESOURCE_IRQ,
2197+ }
2198+};
2199+
2200+static struct platform_device smc91x_device = {
2201+ .name = "smc91x",
2202+ .id = 0,
2203+ .num_resources = ARRAY_SIZE(smc91x_resources),
2204+ .resource = smc91x_resources,
2205+};
2206+
2207+#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES)
2208+static void zylonite_backlight_power(int on)
2209+{
2210+ gpio_set_value(gpio_backlight, on);
2211+}
2212+
2213+static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
2214+ .pixclock = 110000,
2215+ .xres = 240,
2216+ .yres = 320,
2217+ .bpp = 16,
2218+ .hsync_len = 4,
2219+ .left_margin = 6,
2220+ .right_margin = 4,
2221+ .vsync_len = 2,
2222+ .upper_margin = 2,
2223+ .lower_margin = 3,
2224+ .sync = FB_SYNC_VERT_HIGH_ACT,
2225+};
2226+
2227+static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
2228+ .pixclock = 50000,
2229+ .xres = 640,
2230+ .yres = 480,
2231+ .bpp = 16,
2232+ .hsync_len = 1,
2233+ .left_margin = 0x9f,
2234+ .right_margin = 1,
2235+ .vsync_len = 44,
2236+ .upper_margin = 0,
2237+ .lower_margin = 0,
2238+ .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
2239+};
2240+
2241+static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
2242+ .num_modes = 1,
2243+ .lccr0 = LCCR0_Act,
2244+ .lccr3 = LCCR3_PCP,
2245+ .pxafb_backlight_power = zylonite_backlight_power,
2246+};
2247+
2248+static struct pxafb_mode_info sharp_ls037_modes[] = {
2249+ [0] = {
2250+ .pixclock = 158000,
2251+ .xres = 240,
2252+ .yres = 320,
2253+ .bpp = 16,
2254+ .hsync_len = 4,
2255+ .left_margin = 39,
2256+ .right_margin = 39,
2257+ .vsync_len = 1,
2258+ .upper_margin = 2,
2259+ .lower_margin = 3,
2260+ .sync = 0,
2261+ },
2262+ [1] = {
2263+ .pixclock = 39700,
2264+ .xres = 480,
2265+ .yres = 640,
2266+ .bpp = 16,
2267+ .hsync_len = 8,
2268+ .left_margin = 81,
2269+ .right_margin = 81,
2270+ .vsync_len = 1,
2271+ .upper_margin = 2,
2272+ .lower_margin = 7,
2273+ .sync = 0,
2274+ },
2275+};
2276+
2277+static struct pxafb_mach_info zylonite_sharp_lcd_info = {
2278+ .modes = sharp_ls037_modes,
2279+ .num_modes = 2,
2280+ .lccr0 = LCCR0_Act,
2281+ .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP,
2282+ .pxafb_backlight_power = zylonite_backlight_power,
2283+};
2284+
2285+static void __init zylonite_init_lcd(void)
2286+{
2287+ /* backlight GPIO: output, default on */
2288+ gpio_direction_output(gpio_backlight, 1);
2289+
2290+ if (lcd_id & 0x20) {
2291+ set_pxa_fb_info(&zylonite_sharp_lcd_info);
2292+ return;
2293+ }
2294+
2295+ /* legacy LCD panels, it would be handy here if LCD panel type can
2296+ * be decided at run-time
2297+ */
2298+ if (1)
2299+ zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode;
2300+ else
2301+ zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
2302+
2303+ set_pxa_fb_info(&zylonite_toshiba_lcd_info);
2304+}
2305+#else
2306+static inline void zylonite_init_lcd(void) {}
2307+#endif
2308+
2309+static void __init zylonite_init(void)
2310+{
2311+ /* board-processor specific initialization */
2312+ zylonite_pxa300_init();
2313+ zylonite_pxa320_init();
2314+
2315+ /*
2316+ * Note: We depend that the bootloader set
2317+ * the correct value to MSC register for SMC91x.
2318+ */
2319+ smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
2320+ smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq);
2321+ platform_device_register(&smc91x_device);
2322+
2323+ zylonite_init_lcd();
2324+}
2325+
2326+MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
2327+ .phys_io = 0x40000000,
2328+ .boot_params = 0xa0000100,
2329+ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
2330+ .map_io = pxa_map_io,
2331+ .init_irq = pxa3xx_init_irq,
2332+ .timer = &pxa_timer,
2333+ .init_machine = zylonite_init,
2334+MACHINE_END
2335--- /dev/null
2336+++ linux-2.6.23/arch/arm/mach-pxa/zylonite_pxa300.c
2337@@ -0,0 +1,188 @@
2338+/*
2339+ * linux/arch/arm/mach-pxa/zylonite_pxa300.c
2340+ *
2341+ * PXA300/PXA310 specific support code for the
2342+ * PXA3xx Development Platform (aka Zylonite)
2343+ *
2344+ * Copyright (C) 2007 Marvell Internation Ltd.
2345+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
2346+ * initial version
2347+ *
2348+ * This program is free software; you can redistribute it and/or modify
2349+ * it under the terms of the GNU General Public License version 2 as
2350+ * published by the Free Software Foundation.
2351+ */
2352+
2353+#include <linux/module.h>
2354+#include <linux/kernel.h>
2355+#include <linux/init.h>
2356+
2357+#include <asm/gpio.h>
2358+#include <asm/arch/mfp-pxa300.h>
2359+#include <asm/arch/zylonite.h>
2360+
2361+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
2362+
2363+/* PXA300/PXA310 common configurations */
2364+static mfp_cfg_t common_mfp_cfg[] __initdata = {
2365+ /* LCD */
2366+ GPIO54_LCD_LDD_0,
2367+ GPIO55_LCD_LDD_1,
2368+ GPIO56_LCD_LDD_2,
2369+ GPIO57_LCD_LDD_3,
2370+ GPIO58_LCD_LDD_4,
2371+ GPIO59_LCD_LDD_5,
2372+ GPIO60_LCD_LDD_6,
2373+ GPIO61_LCD_LDD_7,
2374+ GPIO62_LCD_LDD_8,
2375+ GPIO63_LCD_LDD_9,
2376+ GPIO64_LCD_LDD_10,
2377+ GPIO65_LCD_LDD_11,
2378+ GPIO66_LCD_LDD_12,
2379+ GPIO67_LCD_LDD_13,
2380+ GPIO68_LCD_LDD_14,
2381+ GPIO69_LCD_LDD_15,
2382+ GPIO70_LCD_LDD_16,
2383+ GPIO71_LCD_LDD_17,
2384+ GPIO72_LCD_FCLK,
2385+ GPIO73_LCD_LCLK,
2386+ GPIO74_LCD_PCLK,
2387+ GPIO75_LCD_BIAS,
2388+ GPIO76_LCD_VSYNC,
2389+ GPIO127_LCD_CS_N,
2390+
2391+ /* BTUART */
2392+ GPIO111_UART2_RTS,
2393+ GPIO112_UART2_RXD,
2394+ GPIO113_UART2_TXD,
2395+ GPIO114_UART2_CTS,
2396+
2397+ /* STUART */
2398+ GPIO109_UART3_TXD,
2399+ GPIO110_UART3_RXD,
2400+
2401+ /* AC97 */
2402+ GPIO23_AC97_nACRESET,
2403+ GPIO24_AC97_SYSCLK,
2404+ GPIO29_AC97_BITCLK,
2405+ GPIO25_AC97_SDATA_IN_0,
2406+ GPIO27_AC97_SDATA_OUT,
2407+ GPIO28_AC97_SYNC,
2408+
2409+ /* Keypad */
2410+ GPIO107_KP_DKIN_0,
2411+ GPIO108_KP_DKIN_1,
2412+ GPIO115_KP_MKIN_0,
2413+ GPIO116_KP_MKIN_1,
2414+ GPIO117_KP_MKIN_2,
2415+ GPIO118_KP_MKIN_3,
2416+ GPIO119_KP_MKIN_4,
2417+ GPIO120_KP_MKIN_5,
2418+ GPIO2_2_KP_MKIN_6,
2419+ GPIO3_2_KP_MKIN_7,
2420+ GPIO121_KP_MKOUT_0,
2421+ GPIO122_KP_MKOUT_1,
2422+ GPIO123_KP_MKOUT_2,
2423+ GPIO124_KP_MKOUT_3,
2424+ GPIO125_KP_MKOUT_4,
2425+ GPIO4_2_KP_MKOUT_5,
2426+ GPIO5_2_KP_MKOUT_6,
2427+ GPIO6_2_KP_MKOUT_7,
2428+};
2429+
2430+static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
2431+ /* FFUART */
2432+ GPIO30_UART1_RXD,
2433+ GPIO31_UART1_TXD,
2434+ GPIO32_UART1_CTS,
2435+ GPIO37_UART1_RTS,
2436+ GPIO33_UART1_DCD,
2437+ GPIO34_UART1_DSR,
2438+ GPIO35_UART1_RI,
2439+ GPIO36_UART1_DTR,
2440+
2441+ /* Ethernet */
2442+ GPIO2_nCS3,
2443+ GPIO99_GPIO,
2444+};
2445+
2446+static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
2447+ /* FFUART */
2448+ GPIO99_UART1_RXD,
2449+ GPIO100_UART1_TXD,
2450+ GPIO101_UART1_CTS,
2451+ GPIO106_UART1_RTS,
2452+
2453+ /* Ethernet */
2454+ GPIO2_nCS3,
2455+ GPIO102_GPIO,
2456+};
2457+
2458+#define NUM_LCD_DETECT_PINS 7
2459+
2460+static int lcd_detect_pins[] __initdata = {
2461+ MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */
2462+ MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */
2463+ MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */
2464+ MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */
2465+ MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */
2466+ MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */
2467+ MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */
2468+};
2469+
2470+static void __init zylonite_detect_lcd_panel(void)
2471+{
2472+ unsigned long mfpr_save[NUM_LCD_DETECT_PINS];
2473+ int i, gpio, id = 0;
2474+
2475+ /* save the original MFP settings of these pins and configure
2476+ * them as GPIO Input, DS01X, Pull Neither, Edge Clear
2477+ */
2478+ for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
2479+ mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
2480+ pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440);
2481+ }
2482+
2483+ for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
2484+ id = id << 1;
2485+ gpio = mfp_to_gpio(lcd_detect_pins[i]);
2486+ gpio_direction_input(gpio);
2487+
2488+ if (gpio_get_value(gpio))
2489+ id = id | 0x1;
2490+ }
2491+
2492+ /* lcd id, flush out bit 1 */
2493+ lcd_id = id & 0x3d;
2494+
2495+ /* lcd orientation, portrait or landscape */
2496+ lcd_orientation = (id >> 6) & 0x1;
2497+
2498+ /* restore the original MFP settings */
2499+ for (i = 0; i < NUM_LCD_DETECT_PINS; i++)
2500+ pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
2501+}
2502+
2503+void __init zylonite_pxa300_init(void)
2504+{
2505+ if (cpu_is_pxa300() || cpu_is_pxa310()) {
2506+ /* initialize MFP */
2507+ pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg));
2508+
2509+ /* detect LCD panel */
2510+ zylonite_detect_lcd_panel();
2511+
2512+ /* GPIO pin assignment */
2513+ gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
2514+ }
2515+
2516+ if (cpu_is_pxa300()) {
2517+ pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg));
2518+ gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99);
2519+ }
2520+
2521+ if (cpu_is_pxa310()) {
2522+ pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
2523+ gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
2524+ }
2525+}
2526--- /dev/null
2527+++ linux-2.6.23/arch/arm/mach-pxa/zylonite_pxa320.c
2528@@ -0,0 +1,173 @@
2529+/*
2530+ * linux/arch/arm/mach-pxa/zylonite_pxa320.c
2531+ *
2532+ * PXA320 specific support code for the
2533+ * PXA3xx Development Platform (aka Zylonite)
2534+ *
2535+ * Copyright (C) 2007 Marvell Internation Ltd.
2536+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
2537+ * initial version
2538+ *
2539+ * This program is free software; you can redistribute it and/or modify
2540+ * it under the terms of the GNU General Public License version 2 as
2541+ * published by the Free Software Foundation.
2542+ */
2543+
2544+#include <linux/module.h>
2545+#include <linux/kernel.h>
2546+#include <linux/init.h>
2547+
2548+#include <asm/arch/gpio.h>
2549+#include <asm/arch/mfp-pxa320.h>
2550+#include <asm/arch/zylonite.h>
2551+
2552+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
2553+
2554+static mfp_cfg_t mfp_cfg[] __initdata = {
2555+ /* LCD */
2556+ GPIO6_2_LCD_LDD_0,
2557+ GPIO7_2_LCD_LDD_1,
2558+ GPIO8_2_LCD_LDD_2,
2559+ GPIO9_2_LCD_LDD_3,
2560+ GPIO10_2_LCD_LDD_4,
2561+ GPIO11_2_LCD_LDD_5,
2562+ GPIO12_2_LCD_LDD_6,
2563+ GPIO13_2_LCD_LDD_7,
2564+ GPIO63_LCD_LDD_8,
2565+ GPIO64_LCD_LDD_9,
2566+ GPIO65_LCD_LDD_10,
2567+ GPIO66_LCD_LDD_11,
2568+ GPIO67_LCD_LDD_12,
2569+ GPIO68_LCD_LDD_13,
2570+ GPIO69_LCD_LDD_14,
2571+ GPIO70_LCD_LDD_15,
2572+ GPIO71_LCD_LDD_16,
2573+ GPIO72_LCD_LDD_17,
2574+ GPIO73_LCD_CS_N,
2575+ GPIO74_LCD_VSYNC,
2576+ GPIO14_2_LCD_FCLK,
2577+ GPIO15_2_LCD_LCLK,
2578+ GPIO16_2_LCD_PCLK,
2579+ GPIO17_2_LCD_BIAS,
2580+
2581+ /* FFUART */
2582+ GPIO41_UART1_RXD,
2583+ GPIO42_UART1_TXD,
2584+ GPIO43_UART1_CTS,
2585+ GPIO44_UART1_DCD,
2586+ GPIO45_UART1_DSR,
2587+ GPIO46_UART1_RI,
2588+ GPIO47_UART1_DTR,
2589+ GPIO48_UART1_RTS,
2590+
2591+ /* AC97 */
2592+ GPIO34_AC97_SYSCLK,
2593+ GPIO35_AC97_SDATA_IN_0,
2594+ GPIO37_AC97_SDATA_OUT,
2595+ GPIO38_AC97_SYNC,
2596+ GPIO39_AC97_BITCLK,
2597+ GPIO40_AC97_nACRESET,
2598+
2599+ /* I2C */
2600+ GPIO32_I2C_SCL,
2601+ GPIO33_I2C_SDA,
2602+
2603+ /* Keypad */
2604+ GPIO105_KP_DKIN_0,
2605+ GPIO106_KP_DKIN_1,
2606+ GPIO113_KP_MKIN_0,
2607+ GPIO114_KP_MKIN_1,
2608+ GPIO115_KP_MKIN_2,
2609+ GPIO116_KP_MKIN_3,
2610+ GPIO117_KP_MKIN_4,
2611+ GPIO118_KP_MKIN_5,
2612+ GPIO119_KP_MKIN_6,
2613+ GPIO120_KP_MKIN_7,
2614+ GPIO121_KP_MKOUT_0,
2615+ GPIO122_KP_MKOUT_1,
2616+ GPIO123_KP_MKOUT_2,
2617+ GPIO124_KP_MKOUT_3,
2618+ GPIO125_KP_MKOUT_4,
2619+ GPIO126_KP_MKOUT_5,
2620+ GPIO127_KP_MKOUT_6,
2621+ GPIO5_2_KP_MKOUT_7,
2622+
2623+ /* Ethernet */
2624+ GPIO4_nCS3,
2625+ GPIO90_GPIO,
2626+};
2627+
2628+#define NUM_LCD_DETECT_PINS 7
2629+
2630+static int lcd_detect_pins[] __initdata = {
2631+ MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */
2632+ MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */
2633+ MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */
2634+ MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */
2635+ MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */
2636+ MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */
2637+ MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */
2638+ /*
2639+ * set the MFP_PIN_GPIO 14/15/17 to alternate function other than
2640+ * GPIO to avoid input level confliction with 14_2, 15_2, 17_2
2641+ */
2642+ MFP_PIN_GPIO14,
2643+ MFP_PIN_GPIO15,
2644+ MFP_PIN_GPIO17,
2645+};
2646+
2647+static int lcd_detect_mfpr[] __initdata = {
2648+ /* AF0, DS 1X, Pull Neither, Edge Clear */
2649+ 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440,
2650+ 0xc442, /* Backlight, Pull-Up, AF2 */
2651+ 0x8445, /* AF5 */
2652+ 0x8445, /* AF5 */
2653+};
2654+
2655+static void __init zylonite_detect_lcd_panel(void)
2656+{
2657+ unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)];
2658+ int i, gpio, id = 0;
2659+
2660+ /* save the original MFP settings of these pins and configure them
2661+ * as GPIO Input, DS01X, Pull Neither, Edge Clear
2662+ */
2663+ for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) {
2664+ mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
2665+ pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]);
2666+ }
2667+
2668+ for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
2669+ id = id << 1;
2670+ gpio = mfp_to_gpio(lcd_detect_pins[i]);
2671+ gpio_direction_input(gpio);
2672+
2673+ if (gpio_get_value(gpio))
2674+ id = id | 0x1;
2675+ }
2676+
2677+ /* lcd id, flush out bit 1 */
2678+ lcd_id = id & 0x3d;
2679+
2680+ /* lcd orientation, portrait or landscape */
2681+ lcd_orientation = (id >> 6) & 0x1;
2682+
2683+ /* restore the original MFP settings */
2684+ for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++)
2685+ pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
2686+}
2687+
2688+void __init zylonite_pxa320_init(void)
2689+{
2690+ if (cpu_is_pxa320()) {
2691+ /* initialize MFP */
2692+ pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
2693+
2694+ /* detect LCD panel */
2695+ zylonite_detect_lcd_panel();
2696+
2697+ /* GPIO pin assignment */
2698+ gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
2699+ gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
2700+ }
2701+}
2702--- linux-2.6.23.orig/arch/arm/mm/Kconfig
2703+++ linux-2.6.23/arch/arm/mm/Kconfig
2704@@ -322,7 +322,7 @@
2705 # XScale
2706 config CPU_XSCALE
2707 bool
2708- depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
2709+ depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
2710 default y
2711 select CPU_32v5
2712 select CPU_ABRT_EV5T
2713@@ -333,7 +333,7 @@
2714 # XScale Core Version 3
2715 config CPU_XSC3
2716 bool
2717- depends on ARCH_IXP23XX || ARCH_IOP13XX
2718+ depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
2719 default y
2720 select CPU_32v5
2721 select CPU_ABRT_EV5T
2722--- linux-2.6.23.orig/drivers/i2c/busses/i2c-pxa.c
2723+++ linux-2.6.23/drivers/i2c/busses/i2c-pxa.c
2724@@ -31,6 +31,8 @@
2725 #include <linux/interrupt.h>
2726 #include <linux/i2c-pxa.h>
2727 #include <linux/platform_device.h>
2728+#include <linux/err.h>
2729+#include <linux/clk.h>
2730
2731 #include <asm/hardware.h>
2732 #include <asm/irq.h>
2733@@ -48,6 +50,7 @@
2734 unsigned int slave_addr;
2735
2736 struct i2c_adapter adap;
2737+ struct clk *clk;
2738 #ifdef CONFIG_I2C_PXA_SLAVE
2739 struct i2c_slave_client *slave;
2740 #endif
2741@@ -869,6 +872,12 @@
2742
2743 sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id);
2744
2745+ i2c->clk = clk_get(&dev->dev, "I2CCLK");
2746+ if (IS_ERR(i2c->clk)) {
2747+ ret = PTR_ERR(i2c->clk);
2748+ goto eclk;
2749+ }
2750+
2751 i2c->reg_base = ioremap(res->start, res_len(res));
2752 if (!i2c->reg_base) {
2753 ret = -EIO;
2754@@ -889,22 +898,19 @@
2755 }
2756 #endif
2757
2758+ clk_enable(i2c->clk);
2759+#ifdef CONFIG_PXA27x
2760 switch (dev->id) {
2761 case 0:
2762-#ifdef CONFIG_PXA27x
2763 pxa_gpio_mode(GPIO117_I2CSCL_MD);
2764 pxa_gpio_mode(GPIO118_I2CSDA_MD);
2765-#endif
2766- pxa_set_cken(CKEN_I2C, 1);
2767 break;
2768-#ifdef CONFIG_PXA27x
2769 case 1:
2770 local_irq_disable();
2771 PCFR |= PCFR_PI2CEN;
2772 local_irq_enable();
2773- pxa_set_cken(CKEN_PWRI2C, 1);
2774-#endif
2775 }
2776+#endif
2777
2778 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
2779 i2c->adap.name, i2c);
2780@@ -948,19 +954,18 @@
2781 eadapt:
2782 free_irq(irq, i2c);
2783 ereqirq:
2784- switch (dev->id) {
2785- case 0:
2786- pxa_set_cken(CKEN_I2C, 0);
2787- break;
2788+ clk_disable(i2c->clk);
2789+
2790 #ifdef CONFIG_PXA27x
2791- case 1:
2792- pxa_set_cken(CKEN_PWRI2C, 0);
2793+ if (dev->id == 1) {
2794 local_irq_disable();
2795 PCFR &= ~PCFR_PI2CEN;
2796 local_irq_enable();
2797-#endif
2798 }
2799+#endif
2800 eremap:
2801+ clk_put(i2c->clk);
2802+eclk:
2803 kfree(i2c);
2804 emalloc:
2805 release_mem_region(res->start, res_len(res));
2806@@ -975,18 +980,18 @@
2807
2808 i2c_del_adapter(&i2c->adap);
2809 free_irq(i2c->irq, i2c);
2810- switch (dev->id) {
2811- case 0:
2812- pxa_set_cken(CKEN_I2C, 0);
2813- break;
2814+
2815+ clk_disable(i2c->clk);
2816+ clk_put(i2c->clk);
2817+
2818 #ifdef CONFIG_PXA27x
2819- case 1:
2820- pxa_set_cken(CKEN_PWRI2C, 0);
2821+ if (dev->id == 1) {
2822 local_irq_disable();
2823 PCFR &= ~PCFR_PI2CEN;
2824 local_irq_enable();
2825-#endif
2826 }
2827+#endif
2828+
2829 release_mem_region(i2c->iobase, i2c->iosize);
2830 kfree(i2c);
2831
2832--- linux-2.6.23.orig/drivers/input/keyboard/pxa27x_keyboard.c
2833+++ linux-2.6.23/drivers/input/keyboard/pxa27x_keyboard.c
2834@@ -23,6 +23,8 @@
2835 #include <linux/input.h>
2836 #include <linux/device.h>
2837 #include <linux/platform_device.h>
2838+#include <linux/clk.h>
2839+#include <linux/err.h>
2840
2841 #include <asm/mach-types.h>
2842 #include <asm/mach/arch.h>
2843@@ -40,6 +42,8 @@
2844 col/2 == 2 ? KPASMKP2 : KPASMKP3)
2845 #define KPASMKPx_MKC(row, col) (1 << (row + 16 * (col % 2)))
2846
2847+static struct clk *pxakbd_clk;
2848+
2849 static irqreturn_t pxakbd_irq_handler(int irq, void *dev_id)
2850 {
2851 struct platform_device *pdev = dev_id;
2852@@ -104,7 +108,7 @@
2853 KPREC = 0x7F;
2854
2855 /* Enable unit clock */
2856- pxa_set_cken(CKEN_KEYPAD, 1);
2857+ clk_enable(pxakbd_clk);
2858
2859 return 0;
2860 }
2861@@ -112,7 +116,7 @@
2862 static void pxakbd_close(struct input_dev *dev)
2863 {
2864 /* Disable clock unit */
2865- pxa_set_cken(CKEN_KEYPAD, 0);
2866+ clk_disable(pxakbd_clk);
2867 }
2868
2869 #ifdef CONFIG_PM
2870@@ -140,7 +144,8 @@
2871 KPREC = pdata->reg_kprec;
2872
2873 /* Enable unit clock */
2874- pxa_set_cken(CKEN_KEYPAD, 1);
2875+ clk_disable(pxakbd_clk);
2876+ clk_enable(pxakbd_clk);
2877 }
2878
2879 mutex_unlock(&input_dev->mutex);
2880@@ -158,11 +163,18 @@
2881 struct input_dev *input_dev;
2882 int i, row, col, error;
2883
2884+ pxakbd_clk = clk_get(&pdev->dev, "KBDCLK");
2885+ if (IS_ERR(pxakbd_clk)) {
2886+ error = PTR_ERR(pxakbd_clk);
2887+ goto err_clk;
2888+ }
2889+
2890 /* Create and register the input driver. */
2891 input_dev = input_allocate_device();
2892 if (!input_dev) {
2893 printk(KERN_ERR "Cannot request keypad device\n");
2894- return -ENOMEM;
2895+ error = -ENOMEM;
2896+ goto err_alloc;
2897 }
2898
2899 input_dev->name = DRIVER_NAME;
2900@@ -185,7 +197,6 @@
2901 DRIVER_NAME, pdev);
2902 if (error) {
2903 printk(KERN_ERR "Cannot request keypad IRQ\n");
2904- pxa_set_cken(CKEN_KEYPAD, 0);
2905 goto err_free_dev;
2906 }
2907
2908@@ -217,6 +228,9 @@
2909 free_irq(IRQ_KEYPAD, pdev);
2910 err_free_dev:
2911 input_free_device(input_dev);
2912+ err_alloc:
2913+ clk_put(pxakbd_clk);
2914+ err_clk:
2915 return error;
2916 }
2917
2918@@ -226,6 +240,7 @@
2919
2920 input_unregister_device(input_dev);
2921 free_irq(IRQ_KEYPAD, pdev);
2922+ clk_put(pxakbd_clk);
2923 platform_set_drvdata(pdev, NULL);
2924
2925 return 0;
2926--- linux-2.6.23.orig/drivers/mmc/host/pxamci.c
2927+++ linux-2.6.23/drivers/mmc/host/pxamci.c
2928@@ -23,6 +23,8 @@
2929 #include <linux/delay.h>
2930 #include <linux/interrupt.h>
2931 #include <linux/dma-mapping.h>
2932+#include <linux/clk.h>
2933+#include <linux/err.h>
2934 #include <linux/mmc/host.h>
2935
2936 #include <asm/dma.h>
2937@@ -44,6 +46,8 @@
2938 spinlock_t lock;
2939 struct resource *res;
2940 void __iomem *base;
2941+ struct clk *clk;
2942+ unsigned long clkrate;
2943 int irq;
2944 int dma;
2945 unsigned int clkrt;
2946@@ -119,7 +123,7 @@
2947 writel(nob, host->base + MMC_NOB);
2948 writel(data->blksz, host->base + MMC_BLKLEN);
2949
2950- clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
2951+ clks = (unsigned long long)data->timeout_ns * host->clkrate;
2952 do_div(clks, 1000000000UL);
2953 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
2954 writel((timeout + 255) / 256, host->base + MMC_RDTO);
2955@@ -358,18 +362,25 @@
2956 struct pxamci_host *host = mmc_priv(mmc);
2957
2958 if (ios->clock) {
2959- unsigned int clk = CLOCKRATE / ios->clock;
2960- if (CLOCKRATE / clk > ios->clock)
2961+ unsigned long rate = host->clkrate;
2962+ unsigned int clk = rate / ios->clock;
2963+
2964+ /*
2965+ * clk might result in a lower divisor than we
2966+ * desire. check for that condition and adjust
2967+ * as appropriate.
2968+ */
2969+ if (rate / clk > ios->clock)
2970 clk <<= 1;
2971 host->clkrt = fls(clk) - 1;
2972- pxa_set_cken(CKEN_MMC, 1);
2973+ clk_enable(host->clk);
2974
2975 /*
2976 * we write clkrt on the next command
2977 */
2978 } else {
2979 pxamci_stop_clock(host);
2980- pxa_set_cken(CKEN_MMC, 0);
2981+ clk_disable(host->clk);
2982 }
2983
2984 if (host->power_mode != ios->power_mode) {
2985@@ -429,8 +440,6 @@
2986 }
2987
2988 mmc->ops = &pxamci_ops;
2989- mmc->f_min = CLOCKRATE_MIN;
2990- mmc->f_max = CLOCKRATE_MAX;
2991
2992 /*
2993 * We can do SG-DMA, but we don't because we never know how much
2994@@ -457,6 +466,22 @@
2995 host->mmc = mmc;
2996 host->dma = -1;
2997 host->pdata = pdev->dev.platform_data;
2998+
2999+ host->clk = clk_get(&pdev->dev, "MMCCLK");
3000+ if (IS_ERR(host->clk)) {
3001+ ret = PTR_ERR(host->clk);
3002+ host->clk = NULL;
3003+ goto out;
3004+ }
3005+
3006+ host->clkrate = clk_get_rate(host->clk);
3007+
3008+ /*
3009+ * Calculate minimum clock rate, rounding up.
3010+ */
3011+ mmc->f_min = (host->clkrate + 63) / 64;
3012+ mmc->f_max = host->clkrate;
3013+
3014 mmc->ocr_avail = host->pdata ?
3015 host->pdata->ocr_mask :
3016 MMC_VDD_32_33|MMC_VDD_33_34;
3017@@ -515,6 +540,8 @@
3018 iounmap(host->base);
3019 if (host->sg_cpu)
3020 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
3021+ if (host->clk)
3022+ clk_put(host->clk);
3023 }
3024 if (mmc)
3025 mmc_free_host(mmc);
3026@@ -549,6 +576,8 @@
3027 iounmap(host->base);
3028 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
3029
3030+ clk_put(host->clk);
3031+
3032 release_resource(host->res);
3033
3034 mmc_free_host(mmc);
3035--- linux-2.6.23.orig/drivers/mmc/host/pxamci.h
3036+++ linux-2.6.23/drivers/mmc/host/pxamci.h
3037@@ -86,17 +86,3 @@
3038 #define MMC_RXFIFO 0x0040 /* 8 bit */
3039
3040 #define MMC_TXFIFO 0x0044 /* 8 bit */
3041-
3042-/*
3043- * The base MMC clock rate
3044- */
3045-#ifdef CONFIG_PXA27x
3046-#define CLOCKRATE_MIN 304688
3047-#define CLOCKRATE_MAX 19500000
3048-#else
3049-#define CLOCKRATE_MIN 312500
3050-#define CLOCKRATE_MAX 20000000
3051-#endif
3052-
3053-#define CLOCKRATE CLOCKRATE_MAX
3054-
3055--- linux-2.6.23.orig/drivers/mtd/maps/lubbock-flash.c
3056+++ linux-2.6.23/drivers/mtd/maps/lubbock-flash.c
3057@@ -22,6 +22,7 @@
3058
3059 #include <asm/io.h>
3060 #include <asm/hardware.h>
3061+#include <asm/mach-types.h>
3062 #include <asm/arch/pxa-regs.h>
3063 #include <asm/arch/lubbock.h>
3064 #include <asm/cacheflush.h>
3065@@ -71,9 +72,14 @@
3066
3067 static int __init init_lubbock(void)
3068 {
3069- int flashboot = (LUB_CONF_SWITCHES & 1);
3070+ int flashboot;
3071 int ret = 0, i;
3072
3073+ if (!machine_is_lubbock())
3074+ return -ENODEV;
3075+
3076+ flashboot = (LUB_CONF_SWITCHES & 1);
3077+
3078 lubbock_maps[0].bankwidth = lubbock_maps[1].bankwidth =
3079 (BOOT_DEF & 1) ? 2 : 4;
3080
3081--- linux-2.6.23.orig/drivers/mtd/maps/mainstone-flash.c
3082+++ linux-2.6.23/drivers/mtd/maps/mainstone-flash.c
3083@@ -22,6 +22,7 @@
3084
3085 #include <asm/io.h>
3086 #include <asm/hardware.h>
3087+#include <asm/mach-types.h>
3088 #include <asm/arch/pxa-regs.h>
3089 #include <asm/arch/mainstone.h>
3090 #include <asm/cacheflush.h>
3091@@ -76,6 +77,9 @@
3092 int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
3093 int ret = 0, i;
3094
3095+ if (!machine_is_mainstone())
3096+ return -ENODEV;
3097+
3098 mainstone_maps[0].bankwidth = (BOOT_DEF & 1) ? 2 : 4;
3099 mainstone_maps[1].bankwidth = 4;
3100
3101--- linux-2.6.23.orig/drivers/net/irda/pxaficp_ir.c
3102+++ linux-2.6.23/drivers/net/irda/pxaficp_ir.c
3103@@ -23,6 +23,7 @@
3104 #include <linux/dma-mapping.h>
3105 #include <linux/platform_device.h>
3106 #include <linux/pm.h>
3107+#include <linux/clk.h>
3108
3109 #include <net/irda/irda.h>
3110 #include <net/irda/irmod.h>
3111@@ -87,8 +88,30 @@
3112
3113 struct device *dev;
3114 struct pxaficp_platform_data *pdata;
3115+ struct clk *fir_clk;
3116+ struct clk *sir_clk;
3117+ struct clk *cur_clk;
3118 };
3119
3120+static inline void pxa_irda_disable_clk(struct pxa_irda *si)
3121+{
3122+ if (si->cur_clk)
3123+ clk_disable(si->cur_clk);
3124+ si->cur_clk = NULL;
3125+}
3126+
3127+static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
3128+{
3129+ si->cur_clk = si->fir_clk;
3130+ clk_enable(si->fir_clk);
3131+}
3132+
3133+static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
3134+{
3135+ si->cur_clk = si->sir_clk;
3136+ clk_enable(si->sir_clk);
3137+}
3138+
3139
3140 #define IS_FIR(si) ((si)->speed >= 4000000)
3141 #define IRDA_FRAME_SIZE_LIMIT 2047
3142@@ -134,7 +157,7 @@
3143 DCSR(si->rxdma) &= ~DCSR_RUN;
3144 /* disable FICP */
3145 ICCR0 = 0;
3146- pxa_set_cken(CKEN_FICP, 0);
3147+ pxa_irda_disable_clk(si);
3148
3149 /* set board transceiver to SIR mode */
3150 si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
3151@@ -144,7 +167,7 @@
3152 pxa_gpio_mode(GPIO47_STTXD_MD);
3153
3154 /* enable the STUART clock */
3155- pxa_set_cken(CKEN_STUART, 1);
3156+ pxa_irda_enable_sirclk(si);
3157 }
3158
3159 /* disable STUART first */
3160@@ -169,7 +192,7 @@
3161 /* disable STUART */
3162 STIER = 0;
3163 STISR = 0;
3164- pxa_set_cken(CKEN_STUART, 0);
3165+ pxa_irda_disable_clk(si);
3166
3167 /* disable FICP first */
3168 ICCR0 = 0;
3169@@ -182,7 +205,7 @@
3170 pxa_gpio_mode(GPIO47_ICPTXD_MD);
3171
3172 /* enable the FICP clock */
3173- pxa_set_cken(CKEN_FICP, 1);
3174+ pxa_irda_enable_firclk(si);
3175
3176 si->speed = speed;
3177 pxa_irda_fir_dma_rx_start(si);
3178@@ -592,16 +615,15 @@
3179 STIER = 0;
3180 /* disable STUART SIR mode */
3181 STISR = 0;
3182- /* disable the STUART clock */
3183- pxa_set_cken(CKEN_STUART, 0);
3184
3185 /* disable DMA */
3186 DCSR(si->txdma) &= ~DCSR_RUN;
3187 DCSR(si->rxdma) &= ~DCSR_RUN;
3188 /* disable FICP */
3189 ICCR0 = 0;
3190- /* disable the FICP clock */
3191- pxa_set_cken(CKEN_FICP, 0);
3192+
3193+ /* disable the STUART or FICP clocks */
3194+ pxa_irda_disable_clk(si);
3195
3196 DRCMR17 = 0;
3197 DRCMR18 = 0;
3198@@ -792,6 +814,13 @@
3199 si->dev = &pdev->dev;
3200 si->pdata = pdev->dev.platform_data;
3201
3202+ si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
3203+ si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
3204+ if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
3205+ err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
3206+ goto err_mem_4;
3207+ }
3208+
3209 /*
3210 * Initialise the SIR buffers
3211 */
3212@@ -831,6 +860,10 @@
3213 err_mem_5:
3214 kfree(si->rx_buff.head);
3215 err_mem_4:
3216+ if (si->sir_clk && !IS_ERR(si->sir_clk))
3217+ clk_put(si->sir_clk);
3218+ if (si->fir_clk && !IS_ERR(si->fir_clk))
3219+ clk_put(si->fir_clk);
3220 free_netdev(dev);
3221 err_mem_3:
3222 release_mem_region(__PREG(FICP), 0x1c);
3223@@ -850,6 +883,8 @@
3224 unregister_netdev(dev);
3225 kfree(si->tx_buff.head);
3226 kfree(si->rx_buff.head);
3227+ clk_put(si->fir_clk);
3228+ clk_put(si->sir_clk);
3229 free_netdev(dev);
3230 }
3231
3232--- linux-2.6.23.orig/drivers/net/smc91x.c
3233+++ linux-2.6.23/drivers/net/smc91x.c
3234@@ -173,56 +173,6 @@
3235 */
3236 #define MII_DELAY 1
3237
3238-/* store this information for the driver.. */
3239-struct smc_local {
3240- /*
3241- * If I have to wait until memory is available to send a
3242- * packet, I will store the skbuff here, until I get the
3243- * desired memory. Then, I'll send it out and free it.
3244- */
3245- struct sk_buff *pending_tx_skb;
3246- struct tasklet_struct tx_task;
3247-
3248- /*
3249- * these are things that the kernel wants me to keep, so users
3250- * can find out semi-useless statistics of how well the card is
3251- * performing
3252- */
3253- struct net_device_stats stats;
3254-
3255- /* version/revision of the SMC91x chip */
3256- int version;
3257-
3258- /* Contains the current active transmission mode */
3259- int tcr_cur_mode;
3260-
3261- /* Contains the current active receive mode */
3262- int rcr_cur_mode;
3263-
3264- /* Contains the current active receive/phy mode */
3265- int rpc_cur_mode;
3266- int ctl_rfduplx;
3267- int ctl_rspeed;
3268-
3269- u32 msg_enable;
3270- u32 phy_type;
3271- struct mii_if_info mii;
3272-
3273- /* work queue */
3274- struct work_struct phy_configure;
3275- struct net_device *dev;
3276- int work_pending;
3277-
3278- spinlock_t lock;
3279-
3280-#ifdef SMC_USE_PXA_DMA
3281- /* DMA needs the physical address of the chip */
3282- u_long physaddr;
3283-#endif
3284- void __iomem *base;
3285- void __iomem *datacs;
3286-};
3287-
3288 #if SMC_DEBUG > 0
3289 #define DBG(n, args...) \
3290 do { \
3291@@ -2238,17 +2188,19 @@
3292 goto out_release_attrib;
3293 }
3294
3295- platform_set_drvdata(pdev, ndev);
3296- ret = smc_probe(ndev, addr);
3297- if (ret != 0)
3298- goto out_iounmap;
3299 #ifdef SMC_USE_PXA_DMA
3300- else {
3301+ {
3302 struct smc_local *lp = netdev_priv(ndev);
3303+ lp->device = &pdev->dev;
3304 lp->physaddr = res->start;
3305 }
3306 #endif
3307
3308+ platform_set_drvdata(pdev, ndev);
3309+ ret = smc_probe(ndev, addr);
3310+ if (ret != 0)
3311+ goto out_iounmap;
3312+
3313 smc_request_datacs(pdev, ndev);
3314
3315 return 0;
3316--- linux-2.6.23.orig/drivers/net/smc91x.h
3317+++ linux-2.6.23/drivers/net/smc91x.h
3318@@ -461,6 +461,59 @@
3319
3320 #endif
3321
3322+
3323+/* store this information for the driver.. */
3324+struct smc_local {
3325+ /*
3326+ * If I have to wait until memory is available to send a
3327+ * packet, I will store the skbuff here, until I get the
3328+ * desired memory. Then, I'll send it out and free it.
3329+ */
3330+ struct sk_buff *pending_tx_skb;
3331+ struct tasklet_struct tx_task;
3332+
3333+ /*
3334+ * these are things that the kernel wants me to keep, so users
3335+ * can find out semi-useless statistics of how well the card is
3336+ * performing
3337+ */
3338+ struct net_device_stats stats;
3339+
3340+ /* version/revision of the SMC91x chip */
3341+ int version;
3342+
3343+ /* Contains the current active transmission mode */
3344+ int tcr_cur_mode;
3345+
3346+ /* Contains the current active receive mode */
3347+ int rcr_cur_mode;
3348+
3349+ /* Contains the current active receive/phy mode */
3350+ int rpc_cur_mode;
3351+ int ctl_rfduplx;
3352+ int ctl_rspeed;
3353+
3354+ u32 msg_enable;
3355+ u32 phy_type;
3356+ struct mii_if_info mii;
3357+
3358+ /* work queue */
3359+ struct work_struct phy_configure;
3360+ struct net_device *dev;
3361+ int work_pending;
3362+
3363+ spinlock_t lock;
3364+
3365+#ifdef SMC_USE_PXA_DMA
3366+ /* DMA needs the physical address of the chip */
3367+ u_long physaddr;
3368+ struct device *device;
3369+#endif
3370+ void __iomem *base;
3371+ void __iomem *datacs;
3372+};
3373+
3374+
3375 #ifdef SMC_USE_PXA_DMA
3376 /*
3377 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
3378@@ -475,11 +528,12 @@
3379 #ifdef SMC_insl
3380 #undef SMC_insl
3381 #define SMC_insl(a, r, p, l) \
3382- smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
3383+ smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
3384 static inline void
3385-smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
3386+smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
3387 u_char *buf, int len)
3388 {
3389+ u_long physaddr = lp->physaddr;
3390 dma_addr_t dmabuf;
3391
3392 /* fallback if no DMA available */
3393@@ -496,7 +550,7 @@
3394 }
3395
3396 len *= 4;
3397- dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
3398+ dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
3399 DCSR(dma) = DCSR_NODESC;
3400 DTADR(dma) = dmabuf;
3401 DSADR(dma) = physaddr + reg;
3402@@ -506,18 +560,19 @@
3403 while (!(DCSR(dma) & DCSR_STOPSTATE))
3404 cpu_relax();
3405 DCSR(dma) = 0;
3406- dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
3407+ dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
3408 }
3409 #endif
3410
3411 #ifdef SMC_insw
3412 #undef SMC_insw
3413 #define SMC_insw(a, r, p, l) \
3414- smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
3415+ smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
3416 static inline void
3417-smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
3418+smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
3419 u_char *buf, int len)
3420 {
3421+ u_long physaddr = lp->physaddr;
3422 dma_addr_t dmabuf;
3423
3424 /* fallback if no DMA available */
3425@@ -534,7 +589,7 @@
3426 }
3427
3428 len *= 2;
3429- dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
3430+ dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
3431 DCSR(dma) = DCSR_NODESC;
3432 DTADR(dma) = dmabuf;
3433 DSADR(dma) = physaddr + reg;
3434@@ -544,7 +599,7 @@
3435 while (!(DCSR(dma) & DCSR_STOPSTATE))
3436 cpu_relax();
3437 DCSR(dma) = 0;
3438- dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
3439+ dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
3440 }
3441 #endif
3442
3443--- linux-2.6.23.orig/drivers/serial/pxa.c
3444+++ linux-2.6.23/drivers/serial/pxa.c
3445@@ -42,6 +42,7 @@
3446 #include <linux/tty.h>
3447 #include <linux/tty_flip.h>
3448 #include <linux/serial_core.h>
3449+#include <linux/clk.h>
3450
3451 #include <asm/io.h>
3452 #include <asm/hardware.h>
3453@@ -56,7 +57,7 @@
3454 unsigned char lcr;
3455 unsigned char mcr;
3456 unsigned int lsr_break_flag;
3457- unsigned int cken;
3458+ struct clk *clk;
3459 char *name;
3460 };
3461
3462@@ -363,6 +364,8 @@
3463 else
3464 up->mcr = 0;
3465
3466+ up->port.uartclk = clk_get_rate(up->clk);
3467+
3468 /*
3469 * Allocate the IRQ
3470 */
3471@@ -568,9 +571,11 @@
3472 unsigned int oldstate)
3473 {
3474 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
3475- pxa_set_cken(up->cken, !state);
3476+
3477 if (!state)
3478- udelay(1);
3479+ clk_enable(up->clk);
3480+ else
3481+ clk_disable(up->clk);
3482 }
3483
3484 static void serial_pxa_release_port(struct uart_port *port)
3485@@ -604,7 +609,7 @@
3486
3487 #ifdef CONFIG_SERIAL_PXA_CONSOLE
3488
3489-static struct uart_pxa_port serial_pxa_ports[];
3490+static struct uart_pxa_port *serial_pxa_ports[4];
3491 static struct uart_driver serial_pxa_reg;
3492
3493 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
3494@@ -654,9 +659,11 @@
3495 static void
3496 serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
3497 {
3498- struct uart_pxa_port *up = &serial_pxa_ports[co->index];
3499+ struct uart_pxa_port *up = serial_pxa_ports[co->index];
3500 unsigned int ier;
3501
3502+ clk_enable(up->clk);
3503+
3504 /*
3505 * First save the IER then disable the interrupts
3506 */
3507@@ -671,6 +678,8 @@
3508 */
3509 wait_for_xmitr(up);
3510 serial_out(up, UART_IER, ier);
3511+
3512+ clk_disable(up->clk);
3513 }
3514
3515 static int __init
3516@@ -684,7 +693,9 @@
3517
3518 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
3519 co->index = 0;
3520- up = &serial_pxa_ports[co->index];
3521+ up = serial_pxa_ports[co->index];
3522+ if (!up)
3523+ return -ENODEV;
3524
3525 if (options)
3526 uart_parse_options(options, &baud, &parity, &bits, &flow);
3527@@ -702,15 +713,6 @@
3528 .data = &serial_pxa_reg,
3529 };
3530
3531-static int __init
3532-serial_pxa_console_init(void)
3533-{
3534- register_console(&serial_pxa_console);
3535- return 0;
3536-}
3537-
3538-console_initcall(serial_pxa_console_init);
3539-
3540 #define PXA_CONSOLE &serial_pxa_console
3541 #else
3542 #define PXA_CONSOLE NULL
3543@@ -736,73 +738,13 @@
3544 .verify_port = serial_pxa_verify_port,
3545 };
3546
3547-static struct uart_pxa_port serial_pxa_ports[] = {
3548- { /* FFUART */
3549- .name = "FFUART",
3550- .cken = CKEN_FFUART,
3551- .port = {
3552- .type = PORT_PXA,
3553- .iotype = UPIO_MEM,
3554- .membase = (void *)&FFUART,
3555- .mapbase = __PREG(FFUART),
3556- .irq = IRQ_FFUART,
3557- .uartclk = 921600 * 16,
3558- .fifosize = 64,
3559- .ops = &serial_pxa_pops,
3560- .line = 0,
3561- },
3562- }, { /* BTUART */
3563- .name = "BTUART",
3564- .cken = CKEN_BTUART,
3565- .port = {
3566- .type = PORT_PXA,
3567- .iotype = UPIO_MEM,
3568- .membase = (void *)&BTUART,
3569- .mapbase = __PREG(BTUART),
3570- .irq = IRQ_BTUART,
3571- .uartclk = 921600 * 16,
3572- .fifosize = 64,
3573- .ops = &serial_pxa_pops,
3574- .line = 1,
3575- },
3576- }, { /* STUART */
3577- .name = "STUART",
3578- .cken = CKEN_STUART,
3579- .port = {
3580- .type = PORT_PXA,
3581- .iotype = UPIO_MEM,
3582- .membase = (void *)&STUART,
3583- .mapbase = __PREG(STUART),
3584- .irq = IRQ_STUART,
3585- .uartclk = 921600 * 16,
3586- .fifosize = 64,
3587- .ops = &serial_pxa_pops,
3588- .line = 2,
3589- },
3590- }, { /* HWUART */
3591- .name = "HWUART",
3592- .cken = CKEN_HWUART,
3593- .port = {
3594- .type = PORT_PXA,
3595- .iotype = UPIO_MEM,
3596- .membase = (void *)&HWUART,
3597- .mapbase = __PREG(HWUART),
3598- .irq = IRQ_HWUART,
3599- .uartclk = 921600 * 16,
3600- .fifosize = 64,
3601- .ops = &serial_pxa_pops,
3602- .line = 3,
3603- },
3604- }
3605-};
3606-
3607 static struct uart_driver serial_pxa_reg = {
3608 .owner = THIS_MODULE,
3609 .driver_name = "PXA serial",
3610 .dev_name = "ttyS",
3611 .major = TTY_MAJOR,
3612 .minor = 64,
3613- .nr = ARRAY_SIZE(serial_pxa_ports),
3614+ .nr = 4,
3615 .cons = PXA_CONSOLE,
3616 };
3617
3618@@ -828,10 +770,68 @@
3619
3620 static int serial_pxa_probe(struct platform_device *dev)
3621 {
3622- serial_pxa_ports[dev->id].port.dev = &dev->dev;
3623- uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port);
3624- platform_set_drvdata(dev, &serial_pxa_ports[dev->id]);
3625+ struct uart_pxa_port *sport;
3626+ struct resource *mmres, *irqres;
3627+ int ret;
3628+
3629+ mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
3630+ irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
3631+ if (!mmres || !irqres)
3632+ return -ENODEV;
3633+
3634+ sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
3635+ if (!sport)
3636+ return -ENOMEM;
3637+
3638+ sport->clk = clk_get(&dev->dev, "UARTCLK");
3639+ if (IS_ERR(sport->clk)) {
3640+ ret = PTR_ERR(sport->clk);
3641+ goto err_free;
3642+ }
3643+
3644+ sport->port.type = PORT_PXA;
3645+ sport->port.iotype = UPIO_MEM;
3646+ sport->port.mapbase = mmres->start;
3647+ sport->port.irq = irqres->start;
3648+ sport->port.fifosize = 64;
3649+ sport->port.ops = &serial_pxa_pops;
3650+ sport->port.line = dev->id;
3651+ sport->port.dev = &dev->dev;
3652+ sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
3653+ sport->port.uartclk = clk_get_rate(sport->clk);
3654+
3655+ /*
3656+ * Is it worth keeping this?
3657+ */
3658+ if (mmres->start == __PREG(FFUART))
3659+ sport->name = "FFUART";
3660+ else if (mmres->start == __PREG(BTUART))
3661+ sport->name = "BTUART";
3662+ else if (mmres->start == __PREG(STUART))
3663+ sport->name = "STUART";
3664+ else if (mmres->start == __PREG(HWUART))
3665+ sport->name = "HWUART";
3666+ else
3667+ sport->name = "???";
3668+
3669+ sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1);
3670+ if (!sport->port.membase) {
3671+ ret = -ENOMEM;
3672+ goto err_clk;
3673+ }
3674+
3675+ serial_pxa_ports[dev->id] = sport;
3676+
3677+ uart_add_one_port(&serial_pxa_reg, &sport->port);
3678+ platform_set_drvdata(dev, sport);
3679+
3680 return 0;
3681+
3682+ err_clk:
3683+ clk_put(sport->clk);
3684+ err_free:
3685+ kfree(sport);
3686+ return ret;
3687 }
3688
3689 static int serial_pxa_remove(struct platform_device *dev)
3690@@ -840,8 +840,9 @@
3691
3692 platform_set_drvdata(dev, NULL);
3693
3694- if (sport)
3695- uart_remove_one_port(&serial_pxa_reg, &sport->port);
3696+ uart_remove_one_port(&serial_pxa_reg, &sport->port);
3697+ clk_put(sport->clk);
3698+ kfree(sport);
3699
3700 return 0;
3701 }
3702--- linux-2.6.23.orig/drivers/serial/serial_core.c
3703+++ linux-2.6.23/drivers/serial/serial_core.c
3704@@ -2128,6 +2128,14 @@
3705 spin_unlock_irqrestore(&port->lock, flags);
3706
3707 /*
3708+ * If this driver supports console, and it hasn't been
3709+ * successfully registered yet, try to re-register it.
3710+ * It may be that the port was not available.
3711+ */
3712+ if (port->cons && !(port->cons->flags & CON_ENABLED))
3713+ register_console(port->cons);
3714+
3715+ /*
3716 * Power down all ports by default, except the
3717 * console if we have one.
3718 */
3719@@ -2288,6 +2296,7 @@
3720 }
3721
3722 state->port = port;
3723+ state->pm_state = -1;
3724
3725 port->cons = drv->cons;
3726 port->info = state->info;
3727@@ -2310,15 +2319,6 @@
3728 tty_register_device(drv->tty_driver, port->line, port->dev);
3729
3730 /*
3731- * If this driver supports console, and it hasn't been
3732- * successfully registered yet, try to re-register it.
3733- * It may be that the port was not available.
3734- */
3735- if (port->type != PORT_UNKNOWN &&
3736- port->cons && !(port->cons->flags & CON_ENABLED))
3737- register_console(port->cons);
3738-
3739- /*
3740 * Ensure UPF_DEAD is not set.
3741 */
3742 port->flags &= ~UPF_DEAD;
3743--- linux-2.6.23.orig/drivers/usb/gadget/pxa2xx_udc.c
3744+++ linux-2.6.23/drivers/usb/gadget/pxa2xx_udc.c
3745@@ -43,6 +43,8 @@
3746 #include <linux/platform_device.h>
3747 #include <linux/dma-mapping.h>
3748 #include <linux/irq.h>
3749+#include <linux/clk.h>
3750+#include <linux/err.h>
3751
3752 #include <asm/byteorder.h>
3753 #include <asm/dma.h>
3754@@ -1157,7 +1159,7 @@
3755
3756 #ifdef CONFIG_ARCH_PXA
3757 /* Disable clock for USB device */
3758- pxa_set_cken(CKEN_USB, 0);
3759+ clk_disable(dev->clk);
3760 #endif
3761
3762 ep0_idle (dev);
3763@@ -1202,8 +1204,7 @@
3764
3765 #ifdef CONFIG_ARCH_PXA
3766 /* Enable clock for USB device */
3767- pxa_set_cken(CKEN_USB, 1);
3768- udelay(5);
3769+ clk_enable(dev->clk);
3770 #endif
3771
3772 /* try to clear these bits before we enable the udc */
3773@@ -2137,6 +2138,14 @@
3774 if (irq < 0)
3775 return -ENODEV;
3776
3777+#ifdef CONFIG_ARCH_PXA
3778+ dev->clk = clk_get(&pdev->dev, "UDCCLK");
3779+ if (IS_ERR(dev->clk)) {
3780+ retval = PTR_ERR(dev->clk);
3781+ goto err_clk;
3782+ }
3783+#endif
3784+
3785 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
3786 dev->has_cfr ? "" : " (!cfr)",
3787 SIZE_STR "(pio)"
3788@@ -2152,11 +2161,10 @@
3789 dev_dbg(&pdev->dev,
3790 "can't get vbus gpio %d, err: %d\n",
3791 dev->mach->gpio_vbus, retval);
3792- return -EBUSY;
3793+ goto err_gpio_vbus;
3794 }
3795 gpio_direction_input(dev->mach->gpio_vbus);
3796 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus);
3797- set_irq_type(vbus_irq, IRQT_BOTHEDGE);
3798 } else
3799 vbus_irq = 0;
3800
3801@@ -2166,9 +2174,7 @@
3802 dev_dbg(&pdev->dev,
3803 "can't get pullup gpio %d, err: %d\n",
3804 dev->mach->gpio_pullup, retval);
3805- if (dev->mach->gpio_vbus)
3806- gpio_free(dev->mach->gpio_vbus);
3807- return -EBUSY;
3808+ goto err_gpio_pullup;
3809 }
3810 gpio_direction_output(dev->mach->gpio_pullup, 0);
3811 }
3812@@ -2195,11 +2201,7 @@
3813 if (retval != 0) {
3814 printk(KERN_ERR "%s: can't get irq %d, err %d\n",
3815 driver_name, irq, retval);
3816- if (dev->mach->gpio_pullup)
3817- gpio_free(dev->mach->gpio_pullup);
3818- if (dev->mach->gpio_vbus)
3819- gpio_free(dev->mach->gpio_vbus);
3820- return -EBUSY;
3821+ goto err_irq1;
3822 }
3823 dev->got_irq = 1;
3824
3825@@ -2213,12 +2215,7 @@
3826 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
3827 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
3828 lubbock_fail0:
3829- free_irq(irq, dev);
3830- if (dev->mach->gpio_pullup)
3831- gpio_free(dev->mach->gpio_pullup);
3832- if (dev->mach->gpio_vbus)
3833- gpio_free(dev->mach->gpio_vbus);
3834- return -EBUSY;
3835+ goto err_irq_lub;
3836 }
3837 retval = request_irq(LUBBOCK_USB_IRQ,
3838 lubbock_vbus_irq,
3839@@ -2234,22 +2231,37 @@
3840 #endif
3841 if (vbus_irq) {
3842 retval = request_irq(vbus_irq, udc_vbus_irq,
3843- IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
3844+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
3845+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
3846 driver_name, dev);
3847 if (retval != 0) {
3848 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
3849 driver_name, vbus_irq, retval);
3850- free_irq(irq, dev);
3851- if (dev->mach->gpio_pullup)
3852- gpio_free(dev->mach->gpio_pullup);
3853- if (dev->mach->gpio_vbus)
3854- gpio_free(dev->mach->gpio_vbus);
3855- return -EBUSY;
3856+ goto err_vbus_irq;
3857 }
3858 }
3859 create_proc_files();
3860
3861 return 0;
3862+
3863+ err_vbus_irq:
3864+#ifdef CONFIG_ARCH_LUBBOCK
3865+ free_irq(LUBBOCK_USB_DISC_IRQ, dev);
3866+ err_irq_lub:
3867+#endif
3868+ free_irq(irq, dev);
3869+ err_irq1:
3870+ if (dev->mach->gpio_pullup)
3871+ gpio_free(dev->mach->gpio_pullup);
3872+ err_gpio_pullup:
3873+ if (dev->mach->gpio_vbus)
3874+ gpio_free(dev->mach->gpio_vbus);
3875+ err_gpio_vbus:
3876+#ifdef CONFIG_ARCH_PXA
3877+ clk_put(dev->clk);
3878+ err_clk:
3879+#endif
3880+ return retval;
3881 }
3882
3883 static void pxa2xx_udc_shutdown(struct platform_device *_dev)
3884@@ -2284,6 +2296,10 @@
3885 if (dev->mach->gpio_pullup)
3886 gpio_free(dev->mach->gpio_pullup);
3887
3888+#ifdef CONFIG_ARCH_PXA
3889+ clk_put(dev->clk);
3890+#endif
3891+
3892 platform_set_drvdata(pdev, NULL);
3893 the_controller = NULL;
3894 return 0;
3895--- linux-2.6.23.orig/drivers/usb/gadget/pxa2xx_udc.h
3896+++ linux-2.6.23/drivers/usb/gadget/pxa2xx_udc.h
3897@@ -125,6 +125,7 @@
3898 struct timer_list timer;
3899
3900 struct device *dev;
3901+ struct clk *clk;
3902 struct pxa2xx_udc_mach_info *mach;
3903 u64 dma_mask;
3904 struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS];
3905--- linux-2.6.23.orig/drivers/video/pxafb.c
3906+++ linux-2.6.23/drivers/video/pxafb.c
3907@@ -37,6 +37,8 @@
3908 #include <linux/cpufreq.h>
3909 #include <linux/platform_device.h>
3910 #include <linux/dma-mapping.h>
3911+#include <linux/clk.h>
3912+#include <linux/err.h>
3913
3914 #include <asm/hardware.h>
3915 #include <asm/io.h>
3916@@ -574,15 +576,15 @@
3917 *
3918 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
3919 */
3920-static inline unsigned int get_pcd(unsigned int pixclock)
3921+static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock)
3922 {
3923 unsigned long long pcd;
3924
3925 /* FIXME: Need to take into account Double Pixel Clock mode
3926- * (DPC) bit? or perhaps set it based on the various clock
3927- * speeds */
3928-
3929- pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
3930+ * (DPC) bit? or perhaps set it based on the various clock
3931+ * speeds */
3932+ pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
3933+ pcd *= pixclock;
3934 do_div(pcd, 100000000 * 2);
3935 /* no need for this, since we should subtract 1 anyway. they cancel */
3936 /* pcd += 1; */ /* make up for integer math truncations */
3937@@ -591,19 +593,21 @@
3938
3939 /*
3940 * Some touchscreens need hsync information from the video driver to
3941- * function correctly. We export it here.
3942+ * function correctly. We export it here. Note that 'hsync_time' and
3943+ * the value returned from pxafb_get_hsync_time() is the *reciprocal*
3944+ * of the hsync period in seconds.
3945 */
3946 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
3947 {
3948- unsigned long long htime;
3949+ unsigned long htime;
3950
3951 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
3952 fbi->hsync_time=0;
3953 return;
3954 }
3955
3956- htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
3957- do_div(htime, pcd * fbi->fb.var.hsync_len);
3958+ htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
3959+
3960 fbi->hsync_time = htime;
3961 }
3962
3963@@ -628,7 +632,7 @@
3964 {
3965 struct pxafb_lcd_reg new_regs;
3966 u_long flags;
3967- u_int lines_per_panel, pcd = get_pcd(var->pixclock);
3968+ u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
3969
3970 pr_debug("pxafb: Configuring PXA LCD\n");
3971
3972@@ -908,7 +912,7 @@
3973 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
3974
3975 /* enable LCD controller clock */
3976- pxa_set_cken(CKEN_LCD, 1);
3977+ clk_enable(fbi->clk);
3978
3979 down(&fcs_lcd_sem);
3980 /* Sequence from 11.7.10 */
3981@@ -950,7 +954,7 @@
3982 up(&fcs_lcd_sem);
3983
3984 /* disable LCD controller clock */
3985- pxa_set_cken(CKEN_LCD, 0);
3986+ clk_disable(fbi->clk);
3987 }
3988
3989 /*
3990@@ -1161,7 +1165,7 @@
3991 if ((clkinfo->old == 13000))
3992 break;
3993
3994- pcd = get_pcd(fbi->fb.var.pixclock);
3995+ pcd = get_pcd(fbi, fbi->fb.var.pixclock);
3996 lccr3 = fbi->reg_lccr3;
3997 set_hsync_time(fbi, pcd);
3998 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
3999@@ -1293,6 +1297,12 @@
4000 memset(fbi, 0, sizeof(struct pxafb_info));
4001 fbi->dev = dev;
4002
4003+ fbi->clk = clk_get(dev, "LCDCLK");
4004+ if (IS_ERR(fbi->clk)) {
4005+ kfree(fbi);
4006+ return NULL;
4007+ }
4008+
4009 strcpy(fbi->fb.fix.id, PXA_NAME);
4010
4011 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
4012--- linux-2.6.23.orig/drivers/video/pxafb.h
4013+++ linux-2.6.23/drivers/video/pxafb.h
4014@@ -94,6 +94,7 @@
4015 struct pxafb_info {
4016 struct fb_info fb;
4017 struct device *dev;
4018+ struct clk *clk;
4019
4020 /*
4021 * These are the addresses we mapped
4022--- linux-2.6.23.orig/include/asm-arm/arch-pxa/hardware.h
4023+++ linux-2.6.23/include/asm-arm/arch-pxa/hardware.h
4024@@ -80,6 +80,24 @@
4025 _id == 0x411; \
4026 })
4027
4028+#define __cpu_is_pxa300(id) \
4029+ ({ \
4030+ unsigned int _id = (id) >> 4 & 0xfff; \
4031+ _id == 0x688; \
4032+ })
4033+
4034+#define __cpu_is_pxa310(id) \
4035+ ({ \
4036+ unsigned int _id = (id) >> 4 & 0xfff; \
4037+ _id == 0x689; \
4038+ })
4039+
4040+#define __cpu_is_pxa320(id) \
4041+ ({ \
4042+ unsigned int _id = (id) >> 4 & 0xfff; \
4043+ _id == 0x603 || _id == 0x682; \
4044+ })
4045+
4046 #define cpu_is_pxa21x() \
4047 ({ \
4048 unsigned int id = read_cpuid(CPUID_ID); \
4049@@ -98,6 +116,53 @@
4050 __cpu_is_pxa27x(id); \
4051 })
4052
4053+#define cpu_is_pxa300() \
4054+ ({ \
4055+ unsigned int id = read_cpuid(CPUID_ID); \
4056+ __cpu_is_pxa300(id); \
4057+ })
4058+
4059+#define cpu_is_pxa310() \
4060+ ({ \
4061+ unsigned int id = read_cpuid(CPUID_ID); \
4062+ __cpu_is_pxa310(id); \
4063+ })
4064+
4065+#define cpu_is_pxa320() \
4066+ ({ \
4067+ unsigned int id = read_cpuid(CPUID_ID); \
4068+ __cpu_is_pxa320(id); \
4069+ })
4070+
4071+/*
4072+ * CPUID Core Generation Bit
4073+ * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
4074+ * == 0x3 for pxa300/pxa310/pxa320
4075+ */
4076+#define __cpu_is_pxa2xx(id) \
4077+ ({ \
4078+ unsigned int _id = (id) >> 13 & 0x7; \
4079+ _id <= 0x2; \
4080+ })
4081+
4082+#define __cpu_is_pxa3xx(id) \
4083+ ({ \
4084+ unsigned int _id = (id) >> 13 & 0x7; \
4085+ _id == 0x3; \
4086+ })
4087+
4088+#define cpu_is_pxa2xx() \
4089+ ({ \
4090+ unsigned int id = read_cpuid(CPUID_ID); \
4091+ __cpu_is_pxa2xx(id); \
4092+ })
4093+
4094+#define cpu_is_pxa3xx() \
4095+ ({ \
4096+ unsigned int id = read_cpuid(CPUID_ID); \
4097+ __cpu_is_pxa3xx(id); \
4098+ })
4099+
4100 /*
4101 * Handy routine to set GPIO alternate functions
4102 */
4103@@ -116,13 +181,16 @@
4104 /*
4105 * Routine to enable or disable CKEN
4106 */
4107-extern void pxa_set_cken(int clock, int enable);
4108+static inline void __deprecated pxa_set_cken(int clock, int enable)
4109+{
4110+ extern void __pxa_set_cken(int clock, int enable);
4111+ __pxa_set_cken(clock, enable);
4112+}
4113
4114 /*
4115 * return current memory and LCD clock frequency in units of 10kHz
4116 */
4117 extern unsigned int get_memclk_frequency_10khz(void);
4118-extern unsigned int get_lcdclk_frequency_10khz(void);
4119
4120 #endif
4121
4122--- linux-2.6.23.orig/include/asm-arm/arch-pxa/irqs.h
4123+++ linux-2.6.23/include/asm-arm/arch-pxa/irqs.h
4124@@ -66,12 +66,6 @@
4125 #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
4126 #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
4127
4128-#if defined(CONFIG_PXA25x)
4129-#define PXA_LAST_GPIO 84
4130-#elif defined(CONFIG_PXA27x)
4131-#define PXA_LAST_GPIO 127
4132-#endif
4133-
4134 /*
4135 * The next 16 interrupts are for board specific purposes. Since
4136 * the kernel can only run on one machine at a time, we can re-use
4137--- /dev/null
4138+++ linux-2.6.23/include/asm-arm/arch-pxa/mfp-pxa300.h
4139@@ -0,0 +1,574 @@
4140+/*
4141+ * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
4142+ *
4143+ * PXA300/PXA310 specific MFP configuration definitions
4144+ *
4145+ * Copyright (C) 2007 Marvell International Ltd.
4146+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
4147+ * initial version
4148+ *
4149+ * This program is free software; you can redistribute it and/or modify
4150+ * it under the terms of the GNU General Public License version 2 as
4151+ * published by the Free Software Foundation.
4152+ */
4153+
4154+#ifndef __ASM_ARCH_MFP_PXA300_H
4155+#define __ASM_ARCH_MFP_PXA300_H
4156+
4157+#include <asm/arch/mfp.h>
4158+
4159+/* GPIO */
4160+#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
4161+#define GPIO49_GPIO MFP_CFG(GPIO49, AF3)
4162+#define GPIO50_GPIO MFP_CFG(GPIO50, AF2)
4163+#define GPIO51_GPIO MFP_CFG(GPIO51, AF3)
4164+#define GPIO52_GPIO MFP_CFG(GPIO52, AF3)
4165+#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
4166+#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
4167+#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
4168+#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
4169+#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
4170+#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
4171+
4172+#ifdef CONFIG_CPU_PXA310
4173+#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
4174+#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
4175+#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
4176+#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
4177+#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
4178+#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
4179+#endif
4180+
4181+/* Chip Select */
4182+#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
4183+
4184+/* AC97 */
4185+#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1)
4186+#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1)
4187+#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1)
4188+#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1)
4189+#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1)
4190+#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3)
4191+#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2)
4192+#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3)
4193+#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2)
4194+#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1)
4195+#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1)
4196+
4197+/* I2C */
4198+#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
4199+#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
4200+
4201+/* QCI */
4202+#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X)
4203+#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X)
4204+#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X)
4205+#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X)
4206+#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X)
4207+#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X)
4208+#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X)
4209+#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
4210+#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
4211+#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
4212+#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
4213+#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
4214+#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
4215+#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
4216+
4217+/* KEYPAD */
4218+#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)
4219+#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT)
4220+#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT)
4221+#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT)
4222+#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT)
4223+#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
4224+#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
4225+#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT)
4226+#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT)
4227+#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT)
4228+#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
4229+#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
4230+#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
4231+#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
4232+#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
4233+#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
4234+#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
4235+#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
4236+#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
4237+#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
4238+#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
4239+#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
4240+#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
4241+#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
4242+#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
4243+#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
4244+#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
4245+#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
4246+#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT)
4247+#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
4248+#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
4249+#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
4250+#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
4251+#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
4252+#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
4253+
4254+#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT)
4255+#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT)
4256+#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
4257+#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
4258+#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT)
4259+#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT)
4260+#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT)
4261+#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT)
4262+#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT)
4263+#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT)
4264+#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
4265+#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
4266+#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
4267+#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
4268+#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
4269+#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
4270+#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
4271+#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
4272+#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
4273+
4274+#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
4275+#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH)
4276+#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH)
4277+#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
4278+#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH)
4279+#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH)
4280+#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH)
4281+#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH)
4282+#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH)
4283+#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
4284+#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
4285+#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH)
4286+#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH)
4287+#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
4288+#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
4289+#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
4290+#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
4291+#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
4292+#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
4293+#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
4294+#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
4295+#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
4296+#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
4297+#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
4298+
4299+/* LCD */
4300+#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X)
4301+#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X)
4302+#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X)
4303+#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X)
4304+#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X)
4305+#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X)
4306+#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X)
4307+#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X)
4308+#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X)
4309+#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X)
4310+#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X)
4311+#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X)
4312+#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X)
4313+#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X)
4314+#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X)
4315+#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X)
4316+#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X)
4317+#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X)
4318+#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X)
4319+#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X)
4320+#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X)
4321+#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X)
4322+#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X)
4323+#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X)
4324+
4325+#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X)
4326+#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X)
4327+#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X)
4328+
4329+/* Mini-LCD */
4330+#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X)
4331+#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X)
4332+#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X)
4333+#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X)
4334+#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X)
4335+#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X)
4336+#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X)
4337+#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X)
4338+#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X)
4339+#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X)
4340+#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X)
4341+#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X)
4342+#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X)
4343+#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X)
4344+#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X)
4345+#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X)
4346+#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X)
4347+#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X)
4348+#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X)
4349+#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X)
4350+
4351+/* MMC1 */
4352+#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
4353+#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
4354+#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
4355+#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
4356+#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH)
4357+#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH)
4358+#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
4359+#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
4360+
4361+/* MMC2 */
4362+#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH)
4363+#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
4364+#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
4365+#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
4366+#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
4367+#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
4368+#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
4369+#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
4370+#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
4371+#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
4372+#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
4373+#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
4374+
4375+/* SSP1 */
4376+#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1)
4377+#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1)
4378+#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6)
4379+#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2)
4380+#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5)
4381+#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5)
4382+#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1)
4383+#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1)
4384+#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7)
4385+#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2)
4386+#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2)
4387+#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7)
4388+#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5)
4389+#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4)
4390+#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5)
4391+#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6)
4392+#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1)
4393+#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6)
4394+#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6)
4395+#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1)
4396+
4397+/* SSP2 */
4398+#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2)
4399+#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2)
4400+#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2)
4401+#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2)
4402+#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2)
4403+#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6)
4404+#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6)
4405+#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2)
4406+#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2)
4407+#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2)
4408+#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7)
4409+#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5)
4410+#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4)
4411+#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2)
4412+#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5)
4413+#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5)
4414+#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2)
4415+#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7)
4416+#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6)
4417+#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4)
4418+#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2)
4419+#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2)
4420+#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4)
4421+#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7)
4422+
4423+/* SSP3 */
4424+#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
4425+#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
4426+#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
4427+#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
4428+#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
4429+#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
4430+#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
4431+#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
4432+#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
4433+#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
4434+#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
4435+#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
4436+
4437+/* SSP4 */
4438+#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
4439+#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
4440+#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
4441+#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
4442+#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
4443+#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
4444+
4445+/* UART1 */
4446+#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT)
4447+#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT)
4448+#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT)
4449+#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT)
4450+#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT)
4451+#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT)
4452+
4453+#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT)
4454+#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT)
4455+#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT)
4456+#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT)
4457+#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT)
4458+#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
4459+
4460+#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT)
4461+#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT)
4462+#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT)
4463+#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT)
4464+#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
4465+#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT)
4466+
4467+#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT)
4468+#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT)
4469+#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT)
4470+#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT)
4471+#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
4472+#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT)
4473+
4474+#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT)
4475+#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT)
4476+#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT)
4477+
4478+#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT)
4479+#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT)
4480+#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT)
4481+
4482+#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
4483+#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT)
4484+#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT)
4485+#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT)
4486+#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT)
4487+#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT)
4488+#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT)
4489+#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT)
4490+
4491+#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT)
4492+#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
4493+#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT)
4494+#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT)
4495+#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT)
4496+#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
4497+#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT)
4498+
4499+/* UART2 */
4500+#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT)
4501+#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT)
4502+#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT)
4503+#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT)
4504+
4505+#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT)
4506+#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT)
4507+#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT)
4508+#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT)
4509+
4510+#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT)
4511+#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT)
4512+#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT)
4513+#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT)
4514+
4515+#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT)
4516+#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT)
4517+#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT)
4518+#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT)
4519+
4520+/* UART3 */
4521+#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT)
4522+#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT)
4523+#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT)
4524+#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT)
4525+
4526+#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT)
4527+#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT)
4528+#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT)
4529+#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT)
4530+
4531+#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT)
4532+#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT)
4533+#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT)
4534+#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT)
4535+#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT)
4536+#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
4537+
4538+#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT)
4539+#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT)
4540+#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT)
4541+#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT)
4542+#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT)
4543+#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
4544+
4545+/* USB Host */
4546+#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1)
4547+#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1)
4548+
4549+/* USB P3 */
4550+#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2)
4551+#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2)
4552+#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2)
4553+#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2)
4554+#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2)
4555+#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2)
4556+
4557+/* PWM */
4558+#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1)
4559+#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1)
4560+#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1)
4561+#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1)
4562+
4563+/* CIR */
4564+#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5)
4565+#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3)
4566+
4567+#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5)
4568+#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2)
4569+
4570+#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1)
4571+#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7)
4572+#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6)
4573+#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6)
4574+#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6)
4575+#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6)
4576+#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2)
4577+#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3)
4578+#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7)
4579+#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6)
4580+
4581+#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1)
4582+
4583+#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1)
4584+#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1)
4585+#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1)
4586+#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1)
4587+
4588+#define GPIO9_SCIO MFP_CFG(GPIO9, AF1)
4589+#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4)
4590+#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1)
4591+
4592+/*
4593+ * PXA300 specific MFP configurations
4594+ */
4595+#ifdef CONFIG_CPU_PXA300
4596+#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2)
4597+#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3)
4598+#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4)
4599+#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4)
4600+#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5)
4601+#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2)
4602+#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2)
4603+#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2)
4604+#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2)
4605+#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2)
4606+#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2)
4607+#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2)
4608+
4609+/* U2D UTMI */
4610+#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1)
4611+#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3)
4612+#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1)
4613+#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5)
4614+#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3)
4615+#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2)
4616+#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5)
4617+#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3)
4618+#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2)
4619+#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1)
4620+#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5)
4621+#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1)
4622+#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3)
4623+#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3)
4624+#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
4625+#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
4626+#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3)
4627+#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3)
4628+#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
4629+#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4)
4630+#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2)
4631+#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7)
4632+#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4)
4633+#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2)
4634+#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3)
4635+#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5)
4636+#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1)
4637+#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2)
4638+#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3)
4639+#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3)
4640+#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2)
4641+#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3)
4642+#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5)
4643+#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3)
4644+#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5)
4645+#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3)
4646+#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4)
4647+#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3)
4648+#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7)
4649+#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5)
4650+#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3)
4651+#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5)
4652+#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3)
4653+#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3)
4654+#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3)
4655+#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3)
4656+#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3)
4657+#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3)
4658+#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3)
4659+#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3)
4660+#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3)
4661+#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3)
4662+#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3)
4663+#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3)
4664+#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3)
4665+#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3)
4666+#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3)
4667+#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3)
4668+#endif /* CONFIG_CPU_PXA300 */
4669+
4670+/*
4671+ * PXA310 specific MFP configurations
4672+ */
4673+#ifdef CONFIG_CPU_PXA310
4674+/* USB P2 */
4675+#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1)
4676+#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1)
4677+#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1)
4678+#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1)
4679+#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1)
4680+#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1)
4681+
4682+/* MMC1 */
4683+#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3)
4684+#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3)
4685+
4686+/* MMC3 */
4687+#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2)
4688+#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2)
4689+#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1)
4690+#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1)
4691+#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1)
4692+#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1)
4693+#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1)
4694+#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1)
4695+
4696+/* ULPI */
4697+#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1)
4698+#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3)
4699+#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3)
4700+#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3)
4701+#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3)
4702+#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3)
4703+#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3)
4704+#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3)
4705+#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3)
4706+#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1)
4707+
4708+#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
4709+#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
4710+#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
4711+#endif /* CONFIG_CPU_PXA310 */
4712+
4713+#endif /* __ASM_ARCH_MFP_PXA300_H */
4714--- /dev/null
4715+++ linux-2.6.23/include/asm-arm/arch-pxa/mfp-pxa320.h
4716@@ -0,0 +1,446 @@
4717+/*
4718+ * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
4719+ *
4720+ * PXA320 specific MFP configuration definitions
4721+ *
4722+ * Copyright (C) 2007 Marvell International Ltd.
4723+ * 2007-08-21: eric miao <eric.y.miao@gmail.com>
4724+ * initial version
4725+ *
4726+ * This program is free software; you can redistribute it and/or modify
4727+ * it under the terms of the GNU General Public License version 2 as
4728+ * published by the Free Software Foundation.
4729+ */
4730+
4731+#ifndef __ASM_ARCH_MFP_PXA320_H
4732+#define __ASM_ARCH_MFP_PXA320_H
4733+
4734+#include <asm/arch/mfp.h>
4735+
4736+/* GPIO */
4737+#define GPIO46_GPIO MFP_CFG(GPIO6, AF0)
4738+#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
4739+#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
4740+#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
4741+#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
4742+
4743+#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
4744+#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
4745+#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
4746+#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
4747+#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
4748+#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
4749+#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0)
4750+#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0)
4751+#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0)
4752+#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0)
4753+#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
4754+
4755+/* Chip Select */
4756+#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
4757+
4758+/* AC97 */
4759+#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1)
4760+#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1)
4761+#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1)
4762+#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1)
4763+#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1)
4764+#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2)
4765+#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2)
4766+#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3)
4767+#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3)
4768+#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1)
4769+#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1)
4770+
4771+/* I2C */
4772+#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
4773+#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
4774+
4775+/* QCI */
4776+#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X)
4777+#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X)
4778+#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X)
4779+#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X)
4780+#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X)
4781+#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X)
4782+#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X)
4783+#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X)
4784+#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X)
4785+#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X)
4786+#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X)
4787+#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X)
4788+#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X)
4789+#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X)
4790+
4791+#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5)
4792+
4793+#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3)
4794+#define GPIO0_DRQ MFP_CFG(GPIO0, AF2)
4795+#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5)
4796+#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6)
4797+#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1)
4798+#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4)
4799+#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1)
4800+#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1)
4801+
4802+#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT)
4803+#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT)
4804+#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
4805+#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
4806+
4807+#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT)
4808+#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT)
4809+#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
4810+#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
4811+#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
4812+#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
4813+#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
4814+#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
4815+
4816+#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
4817+#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
4818+#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
4819+#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
4820+#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
4821+#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
4822+#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
4823+#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
4824+
4825+#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT)
4826+#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT)
4827+
4828+#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
4829+#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
4830+#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
4831+#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
4832+#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
4833+#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
4834+#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
4835+#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
4836+
4837+#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT)
4838+#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT)
4839+#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
4840+#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
4841+#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
4842+#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
4843+#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
4844+#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
4845+
4846+#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
4847+#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
4848+#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
4849+#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
4850+#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
4851+#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
4852+
4853+#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
4854+#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
4855+#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
4856+#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
4857+#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
4858+#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
4859+#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
4860+#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
4861+
4862+/* LCD */
4863+#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
4864+#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
4865+#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
4866+#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
4867+#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
4868+#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
4869+#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
4870+#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
4871+#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X)
4872+#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X)
4873+#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X)
4874+#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X)
4875+#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X)
4876+#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X)
4877+#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X)
4878+#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X)
4879+#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X)
4880+#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X)
4881+#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X)
4882+#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X)
4883+#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
4884+#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
4885+#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
4886+#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
4887+#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X)
4888+#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X)
4889+
4890+#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
4891+#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
4892+#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
4893+#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
4894+#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
4895+#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
4896+#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
4897+#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
4898+#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X)
4899+#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X)
4900+#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X)
4901+#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X)
4902+#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X)
4903+#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X)
4904+#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X)
4905+#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X)
4906+#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X)
4907+#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X)
4908+#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X)
4909+#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X)
4910+#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
4911+#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
4912+#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
4913+#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
4914+
4915+/* MMC1 */
4916+#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH)
4917+#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
4918+#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
4919+#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
4920+#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
4921+#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
4922+#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
4923+#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
4924+#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
4925+#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
4926+#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
4927+#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
4928+#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
4929+
4930+#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
4931+#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
4932+#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
4933+#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
4934+#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
4935+#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
4936+
4937+#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
4938+#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
4939+#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
4940+#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
4941+#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
4942+#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
4943+#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
4944+#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
4945+#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
4946+#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
4947+#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
4948+#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
4949+
4950+/* 1-Wire */
4951+#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT)
4952+#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
4953+
4954+/* SSP1 */
4955+#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1)
4956+#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1)
4957+#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1)
4958+#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1)
4959+#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6)
4960+#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1)
4961+#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1)
4962+#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6)
4963+
4964+/* SSP2 */
4965+#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2)
4966+#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2)
4967+#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2)
4968+#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2)
4969+#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2)
4970+#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5)
4971+#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2)
4972+#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
4973+#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
4974+
4975+#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
4976+#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
4977+#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
4978+#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
4979+#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
4980+#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
4981+#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
4982+#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
4983+#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
4984+#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
4985+#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
4986+#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
4987+
4988+#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
4989+#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
4990+#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
4991+#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
4992+#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
4993+#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
4994+#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
4995+
4996+/* UART1 */
4997+#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT)
4998+#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT)
4999+#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT)
5000+#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT)
5001+#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT)
5002+#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT)
5003+#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT)
5004+#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT)
5005+#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT)
5006+#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT)
5007+#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT)
5008+#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT)
5009+#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT)
5010+#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT)
5011+#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT)
5012+#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT)
5013+#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT)
5014+#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT)
5015+#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT)
5016+#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT)
5017+#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT)
5018+#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT)
5019+#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
5020+#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
5021+#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT)
5022+#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
5023+#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT)
5024+#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT)
5025+
5026+/* UART2 */
5027+#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT)
5028+#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT)
5029+#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT)
5030+#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT)
5031+#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
5032+#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
5033+#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT)
5034+#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT)
5035+
5036+/* UART3 */
5037+#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT)
5038+#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT)
5039+#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT)
5040+#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT)
5041+#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT)
5042+#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT)
5043+#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT)
5044+#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
5045+#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
5046+#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT)
5047+#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT)
5048+#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
5049+#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT)
5050+#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT)
5051+#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT)
5052+#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT)
5053+#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT)
5054+#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT)
5055+#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT)
5056+#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT)
5057+
5058+
5059+/* USB 2.0 UTMI */
5060+#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1)
5061+#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3)
5062+#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1)
5063+#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5)
5064+#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3)
5065+#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2)
5066+#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5)
5067+#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3)
5068+#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1)
5069+#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5)
5070+#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1)
5071+#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3)
5072+#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3)
5073+#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
5074+#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
5075+#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3)
5076+#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3)
5077+#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
5078+
5079+#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3)
5080+#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3)
5081+#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3)
5082+#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3)
5083+#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3)
5084+#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3)
5085+#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3)
5086+#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3)
5087+
5088+#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3)
5089+#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3)
5090+#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3)
5091+#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3)
5092+#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3)
5093+#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3)
5094+#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3)
5095+#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3)
5096+
5097+#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4)
5098+#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2)
5099+#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7)
5100+
5101+#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4)
5102+#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2)
5103+#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4)
5104+#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5)
5105+
5106+#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1)
5107+#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2)
5108+#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3)
5109+
5110+#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3)
5111+#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2)
5112+#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3)
5113+
5114+#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5)
5115+#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3)
5116+#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7)
5117+#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5)
5118+
5119+#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4)
5120+#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5)
5121+#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7)
5122+
5123+#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5)
5124+#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3)
5125+#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5)
5126+
5127+/* USB Host 1.1 */
5128+#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1)
5129+#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1)
5130+
5131+/* USB P2 */
5132+#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2)
5133+#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4)
5134+#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4)
5135+#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2)
5136+#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2)
5137+#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2)
5138+#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2)
5139+#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2)
5140+#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2)
5141+#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2)
5142+
5143+/* USB P3 */
5144+#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2)
5145+#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2)
5146+#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2)
5147+#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2)
5148+#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2)
5149+#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2)
5150+
5151+#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6)
5152+#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6)
5153+
5154+#define GPIO2_RDY MFP_CFG(GPIO2, AF1)
5155+#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3)
5156+
5157+#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1)
5158+#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1)
5159+#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1)
5160+#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1)
5161+
5162+#endif /* __ASM_ARCH_MFP_PXA320_H */
5163--- /dev/null
5164+++ linux-2.6.23/include/asm-arm/arch-pxa/mfp.h
5165@@ -0,0 +1,576 @@
5166+/*
5167+ * linux/include/asm-arm/arch-pxa/mfp.h
5168+ *
5169+ * Multi-Function Pin Definitions
5170+ *
5171+ * Copyright (C) 2007 Marvell International Ltd.
5172+ *
5173+ * 2007-8-21: eric miao <eric.y.miao@gmail.com>
5174+ * initial version
5175+ *
5176+ * This program is free software; you can redistribute it and/or modify
5177+ * it under the terms of the GNU General Public License version 2 as
5178+ * published by the Free Software Foundation.
5179+ */
5180+
5181+#ifndef __ASM_ARCH_MFP_H
5182+#define __ASM_ARCH_MFP_H
5183+
5184+#define MFPR_BASE (0x40e10000)
5185+#define MFPR_SIZE (PAGE_SIZE)
5186+
5187+#define mfp_to_gpio(m) ((m) % 128)
5188+
5189+/* list of all the configurable MFP pins */
5190+enum {
5191+ MFP_PIN_INVALID = -1,
5192+
5193+ MFP_PIN_GPIO0 = 0,
5194+ MFP_PIN_GPIO1,
5195+ MFP_PIN_GPIO2,
5196+ MFP_PIN_GPIO3,
5197+ MFP_PIN_GPIO4,
5198+ MFP_PIN_GPIO5,
5199+ MFP_PIN_GPIO6,
5200+ MFP_PIN_GPIO7,
5201+ MFP_PIN_GPIO8,
5202+ MFP_PIN_GPIO9,
5203+ MFP_PIN_GPIO10,
5204+ MFP_PIN_GPIO11,
5205+ MFP_PIN_GPIO12,
5206+ MFP_PIN_GPIO13,
5207+ MFP_PIN_GPIO14,
5208+ MFP_PIN_GPIO15,
5209+ MFP_PIN_GPIO16,
5210+ MFP_PIN_GPIO17,
5211+ MFP_PIN_GPIO18,
5212+ MFP_PIN_GPIO19,
5213+ MFP_PIN_GPIO20,
5214+ MFP_PIN_GPIO21,
5215+ MFP_PIN_GPIO22,
5216+ MFP_PIN_GPIO23,
5217+ MFP_PIN_GPIO24,
5218+ MFP_PIN_GPIO25,
5219+ MFP_PIN_GPIO26,
5220+ MFP_PIN_GPIO27,
5221+ MFP_PIN_GPIO28,
5222+ MFP_PIN_GPIO29,
5223+ MFP_PIN_GPIO30,
5224+ MFP_PIN_GPIO31,
5225+ MFP_PIN_GPIO32,
5226+ MFP_PIN_GPIO33,
5227+ MFP_PIN_GPIO34,
5228+ MFP_PIN_GPIO35,
5229+ MFP_PIN_GPIO36,
5230+ MFP_PIN_GPIO37,
5231+ MFP_PIN_GPIO38,
5232+ MFP_PIN_GPIO39,
5233+ MFP_PIN_GPIO40,
5234+ MFP_PIN_GPIO41,
5235+ MFP_PIN_GPIO42,
5236+ MFP_PIN_GPIO43,
5237+ MFP_PIN_GPIO44,
5238+ MFP_PIN_GPIO45,
5239+ MFP_PIN_GPIO46,
5240+ MFP_PIN_GPIO47,
5241+ MFP_PIN_GPIO48,
5242+ MFP_PIN_GPIO49,
5243+ MFP_PIN_GPIO50,
5244+ MFP_PIN_GPIO51,
5245+ MFP_PIN_GPIO52,
5246+ MFP_PIN_GPIO53,
5247+ MFP_PIN_GPIO54,
5248+ MFP_PIN_GPIO55,
5249+ MFP_PIN_GPIO56,
5250+ MFP_PIN_GPIO57,
5251+ MFP_PIN_GPIO58,
5252+ MFP_PIN_GPIO59,
5253+ MFP_PIN_GPIO60,
5254+ MFP_PIN_GPIO61,
5255+ MFP_PIN_GPIO62,
5256+ MFP_PIN_GPIO63,
5257+ MFP_PIN_GPIO64,
5258+ MFP_PIN_GPIO65,
5259+ MFP_PIN_GPIO66,
5260+ MFP_PIN_GPIO67,
5261+ MFP_PIN_GPIO68,
5262+ MFP_PIN_GPIO69,
5263+ MFP_PIN_GPIO70,
5264+ MFP_PIN_GPIO71,
5265+ MFP_PIN_GPIO72,
5266+ MFP_PIN_GPIO73,
5267+ MFP_PIN_GPIO74,
5268+ MFP_PIN_GPIO75,
5269+ MFP_PIN_GPIO76,
5270+ MFP_PIN_GPIO77,
5271+ MFP_PIN_GPIO78,
5272+ MFP_PIN_GPIO79,
5273+ MFP_PIN_GPIO80,
5274+ MFP_PIN_GPIO81,
5275+ MFP_PIN_GPIO82,
5276+ MFP_PIN_GPIO83,
5277+ MFP_PIN_GPIO84,
5278+ MFP_PIN_GPIO85,
5279+ MFP_PIN_GPIO86,
5280+ MFP_PIN_GPIO87,
5281+ MFP_PIN_GPIO88,
5282+ MFP_PIN_GPIO89,
5283+ MFP_PIN_GPIO90,
5284+ MFP_PIN_GPIO91,
5285+ MFP_PIN_GPIO92,
5286+ MFP_PIN_GPIO93,
5287+ MFP_PIN_GPIO94,
5288+ MFP_PIN_GPIO95,
5289+ MFP_PIN_GPIO96,
5290+ MFP_PIN_GPIO97,
5291+ MFP_PIN_GPIO98,
5292+ MFP_PIN_GPIO99,
5293+ MFP_PIN_GPIO100,
5294+ MFP_PIN_GPIO101,
5295+ MFP_PIN_GPIO102,
5296+ MFP_PIN_GPIO103,
5297+ MFP_PIN_GPIO104,
5298+ MFP_PIN_GPIO105,
5299+ MFP_PIN_GPIO106,
5300+ MFP_PIN_GPIO107,
5301+ MFP_PIN_GPIO108,
5302+ MFP_PIN_GPIO109,
5303+ MFP_PIN_GPIO110,
5304+ MFP_PIN_GPIO111,
5305+ MFP_PIN_GPIO112,
5306+ MFP_PIN_GPIO113,
5307+ MFP_PIN_GPIO114,
5308+ MFP_PIN_GPIO115,
5309+ MFP_PIN_GPIO116,
5310+ MFP_PIN_GPIO117,
5311+ MFP_PIN_GPIO118,
5312+ MFP_PIN_GPIO119,
5313+ MFP_PIN_GPIO120,
5314+ MFP_PIN_GPIO121,
5315+ MFP_PIN_GPIO122,
5316+ MFP_PIN_GPIO123,
5317+ MFP_PIN_GPIO124,
5318+ MFP_PIN_GPIO125,
5319+ MFP_PIN_GPIO126,
5320+ MFP_PIN_GPIO127,
5321+ MFP_PIN_GPIO0_2,
5322+ MFP_PIN_GPIO1_2,
5323+ MFP_PIN_GPIO2_2,
5324+ MFP_PIN_GPIO3_2,
5325+ MFP_PIN_GPIO4_2,
5326+ MFP_PIN_GPIO5_2,
5327+ MFP_PIN_GPIO6_2,
5328+ MFP_PIN_GPIO7_2,
5329+ MFP_PIN_GPIO8_2,
5330+ MFP_PIN_GPIO9_2,
5331+ MFP_PIN_GPIO10_2,
5332+ MFP_PIN_GPIO11_2,
5333+ MFP_PIN_GPIO12_2,
5334+ MFP_PIN_GPIO13_2,
5335+ MFP_PIN_GPIO14_2,
5336+ MFP_PIN_GPIO15_2,
5337+ MFP_PIN_GPIO16_2,
5338+ MFP_PIN_GPIO17_2,
5339+
5340+ MFP_PIN_ULPI_STP,
5341+ MFP_PIN_ULPI_NXT,
5342+ MFP_PIN_ULPI_DIR,
5343+
5344+ MFP_PIN_nXCVREN,
5345+ MFP_PIN_DF_CLE_nOE,
5346+ MFP_PIN_DF_nADV1_ALE,
5347+ MFP_PIN_DF_SCLK_E,
5348+ MFP_PIN_DF_SCLK_S,
5349+ MFP_PIN_nBE0,
5350+ MFP_PIN_nBE1,
5351+ MFP_PIN_DF_nADV2_ALE,
5352+ MFP_PIN_DF_INT_RnB,
5353+ MFP_PIN_DF_nCS0,
5354+ MFP_PIN_DF_nCS1,
5355+ MFP_PIN_nLUA,
5356+ MFP_PIN_nLLA,
5357+ MFP_PIN_DF_nWE,
5358+ MFP_PIN_DF_ALE_nWE,
5359+ MFP_PIN_DF_nRE_nOE,
5360+ MFP_PIN_DF_ADDR0,
5361+ MFP_PIN_DF_ADDR1,
5362+ MFP_PIN_DF_ADDR2,
5363+ MFP_PIN_DF_ADDR3,
5364+ MFP_PIN_DF_IO0,
5365+ MFP_PIN_DF_IO1,
5366+ MFP_PIN_DF_IO2,
5367+ MFP_PIN_DF_IO3,
5368+ MFP_PIN_DF_IO4,
5369+ MFP_PIN_DF_IO5,
5370+ MFP_PIN_DF_IO6,
5371+ MFP_PIN_DF_IO7,
5372+ MFP_PIN_DF_IO8,
5373+ MFP_PIN_DF_IO9,
5374+ MFP_PIN_DF_IO10,
5375+ MFP_PIN_DF_IO11,
5376+ MFP_PIN_DF_IO12,
5377+ MFP_PIN_DF_IO13,
5378+ MFP_PIN_DF_IO14,
5379+ MFP_PIN_DF_IO15,
5380+
5381+ MFP_PIN_MAX,
5382+};
5383+
5384+/*
5385+ * Table that determines the low power modes outputs, with actual settings
5386+ * used in parentheses for don't-care values. Except for the float output,
5387+ * the configured driven and pulled levels match, so if there is a need for
5388+ * non-LPM pulled output, the same configuration could probably be used.
5389+ *
5390+ * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
5391+ * (bit 7) (bit 8) (bit 14d) (bit 13d)
5392+ *
5393+ * Drive 0 0 0 0 X (1) 0
5394+ * Drive 1 0 1 X (1) 0 0
5395+ * Pull hi (1) 1 X(1) 1 0 0
5396+ * Pull lo (0) 1 X(0) 0 1 0
5397+ * Z (float) 1 X(0) 0 0 0
5398+ */
5399+#define MFP_LPM_DRIVE_LOW 0x8
5400+#define MFP_LPM_DRIVE_HIGH 0x6
5401+#define MFP_LPM_PULL_HIGH 0x7
5402+#define MFP_LPM_PULL_LOW 0x9
5403+#define MFP_LPM_FLOAT 0x1
5404+#define MFP_LPM_PULL_NEITHER 0x0
5405+
5406+/*
5407+ * The pullup and pulldown state of the MFP pin is by default determined by
5408+ * selected alternate function. In case some buggy devices need to override
5409+ * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
5410+ * the following definition as the parameter.
5411+ *
5412+ * Definition pull_sel pullup_en pulldown_en
5413+ * MFP_PULL_HIGH 1 1 0
5414+ * MFP_PULL_LOW 1 0 1
5415+ * MFP_PULL_BOTH 1 1 1
5416+ * MFP_PULL_NONE 1 0 0
5417+ * MFP_PULL_DEFAULT 0 X X
5418+ *
5419+ * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
5420+ * bits, which will cause potential conflicts with the low power mode
5421+ * setting, device drivers should take care of this
5422+ */
5423+#define MFP_PULL_BOTH (0x7u)
5424+#define MFP_PULL_HIGH (0x6u)
5425+#define MFP_PULL_LOW (0x5u)
5426+#define MFP_PULL_NONE (0x4u)
5427+#define MFP_PULL_DEFAULT (0x0u)
5428+
5429+#define MFP_AF0 (0)
5430+#define MFP_AF1 (1)
5431+#define MFP_AF2 (2)
5432+#define MFP_AF3 (3)
5433+#define MFP_AF4 (4)
5434+#define MFP_AF5 (5)
5435+#define MFP_AF6 (6)
5436+#define MFP_AF7 (7)
5437+
5438+#define MFP_DS01X (0)
5439+#define MFP_DS02X (1)
5440+#define MFP_DS03X (2)
5441+#define MFP_DS04X (3)
5442+#define MFP_DS06X (4)
5443+#define MFP_DS08X (5)
5444+#define MFP_DS10X (6)
5445+#define MFP_DS12X (7)
5446+
5447+#define MFP_EDGE_BOTH 0x3
5448+#define MFP_EDGE_RISE 0x2
5449+#define MFP_EDGE_FALL 0x1
5450+#define MFP_EDGE_NONE 0x0
5451+
5452+#define MFPR_AF_MASK 0x0007
5453+#define MFPR_DRV_MASK 0x1c00
5454+#define MFPR_RDH_MASK 0x0200
5455+#define MFPR_LPM_MASK 0xe180
5456+#define MFPR_PULL_MASK 0xe000
5457+#define MFPR_EDGE_MASK 0x0070
5458+
5459+#define MFPR_ALT_OFFSET 0
5460+#define MFPR_ERE_OFFSET 4
5461+#define MFPR_EFE_OFFSET 5
5462+#define MFPR_EC_OFFSET 6
5463+#define MFPR_SON_OFFSET 7
5464+#define MFPR_SD_OFFSET 8
5465+#define MFPR_SS_OFFSET 9
5466+#define MFPR_DRV_OFFSET 10
5467+#define MFPR_PD_OFFSET 13
5468+#define MFPR_PU_OFFSET 14
5469+#define MFPR_PS_OFFSET 15
5470+
5471+#define MFPR(af, drv, rdh, lpm, edge) \
5472+ (((af) & 0x7) | (((drv) & 0x7) << 10) |\
5473+ (((rdh) & 0x1) << 9) |\
5474+ (((lpm) & 0x3) << 7) |\
5475+ (((lpm) & 0x4) << 12)|\
5476+ (((lpm) & 0x8) << 10)|\
5477+ ((!(edge)) << 6) |\
5478+ (((edge) & 0x1) << 5) |\
5479+ (((edge) & 0x2) << 3))
5480+
5481+/*
5482+ * a possible MFP configuration is represented by a 32-bit integer
5483+ * bit 0..15 - MFPR value (16-bit)
5484+ * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
5485+ *
5486+ * to facilitate the definition, the following macros are provided
5487+ *
5488+ * MFPR_DEFAULT - default MFPR value, with
5489+ * alternate function = 0,
5490+ * drive strength = fast 1mA (MFP_DS01X)
5491+ * low power mode = default
5492+ * release dalay hold = false (RDH bit)
5493+ * edge detection = none
5494+ *
5495+ * MFP_CFG - default MFPR value with alternate function
5496+ * MFP_CFG_DRV - default MFPR value with alternate function and
5497+ * pin drive strength
5498+ * MFP_CFG_LPM - default MFPR value with alternate function and
5499+ * low power mode
5500+ * MFP_CFG_X - default MFPR value with alternate function,
5501+ * pin drive strength and low power mode
5502+ *
5503+ * use
5504+ *
5505+ * MFP_CFG_PIN - to get the MFP pin index
5506+ * MFP_CFG_VAL - to get the corresponding MFPR value
5507+ */
5508+
5509+typedef uint32_t mfp_cfg_t;
5510+
5511+#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
5512+#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
5513+
5514+#define MFPR_DEFAULT (0x0000)
5515+
5516+#define MFP_CFG(pin, af) \
5517+ ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
5518+
5519+#define MFP_CFG_DRV(pin, af, drv) \
5520+ ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
5521+ ((MFP_##drv) << 10) | (MFP_##af))
5522+
5523+#define MFP_CFG_LPM(pin, af, lpm) \
5524+ ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
5525+ (((MFP_LPM_##lpm) & 0x3) << 7) |\
5526+ (((MFP_LPM_##lpm) & 0x4) << 12) |\
5527+ (((MFP_LPM_##lpm) & 0x8) << 10))
5528+
5529+#define MFP_CFG_X(pin, af, drv, lpm) \
5530+ ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
5531+ ((MFP_##drv) << 10) | (MFP_##af) |\
5532+ (((MFP_LPM_##lpm) & 0x3) << 7) |\
5533+ (((MFP_LPM_##lpm) & 0x4) << 12) |\
5534+ (((MFP_LPM_##lpm) & 0x8) << 10))
5535+
5536+/* common MFP configurations - processor specific ones defined
5537+ * in mfp-pxa3xx.h
5538+ */
5539+#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
5540+#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
5541+#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
5542+#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
5543+#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
5544+#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
5545+#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
5546+#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
5547+#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
5548+#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
5549+#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
5550+#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
5551+#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
5552+#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
5553+#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
5554+#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
5555+#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
5556+#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
5557+#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
5558+#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
5559+#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
5560+#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
5561+#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
5562+#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
5563+#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
5564+#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
5565+#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
5566+#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
5567+#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
5568+#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
5569+#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
5570+#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
5571+#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
5572+#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
5573+#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
5574+#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
5575+#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
5576+#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
5577+#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
5578+#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
5579+#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
5580+#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
5581+#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
5582+#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
5583+#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
5584+#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
5585+
5586+#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
5587+#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
5588+
5589+#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
5590+#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
5591+#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
5592+
5593+#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
5594+
5595+#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
5596+#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
5597+#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
5598+#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
5599+#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
5600+#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
5601+#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
5602+#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
5603+#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
5604+#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
5605+#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
5606+#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
5607+#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
5608+#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
5609+#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
5610+#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
5611+#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
5612+#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
5613+#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
5614+#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
5615+#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
5616+#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
5617+#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
5618+#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
5619+#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
5620+#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
5621+#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
5622+#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
5623+#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
5624+#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
5625+#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
5626+#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
5627+#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
5628+#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
5629+#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
5630+#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
5631+#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
5632+#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
5633+#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
5634+#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
5635+#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
5636+#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
5637+#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
5638+#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
5639+#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
5640+#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
5641+#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
5642+#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
5643+#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
5644+#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
5645+#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
5646+#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
5647+#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
5648+#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
5649+#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
5650+#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
5651+#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
5652+#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
5653+#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
5654+#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
5655+#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
5656+#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
5657+#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
5658+#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
5659+#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
5660+
5661+#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
5662+#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
5663+#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
5664+#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
5665+#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
5666+#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
5667+#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
5668+
5669+/*
5670+ * each MFP pin will have a MFPR register, since the offset of the
5671+ * register varies between processors, the processor specific code
5672+ * should initialize the pin offsets by pxa3xx_mfp_init_addr()
5673+ *
5674+ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
5675+ * structure, which represents a range of MFP pins from "start" to
5676+ * "end", with the offset begining at "offset", to define a single
5677+ * pin, let "end" = -1
5678+ *
5679+ * use
5680+ *
5681+ * MFP_ADDR_X() to define a range of pins
5682+ * MFP_ADDR() to define a single pin
5683+ * MFP_ADDR_END to signal the end of pin offset definitions
5684+ */
5685+struct pxa3xx_mfp_addr_map {
5686+ unsigned int start;
5687+ unsigned int end;
5688+ unsigned long offset;
5689+};
5690+
5691+#define MFP_ADDR_X(start, end, offset) \
5692+ { MFP_PIN_##start, MFP_PIN_##end, offset }
5693+
5694+#define MFP_ADDR(pin, offset) \
5695+ { MFP_PIN_##pin, -1, offset }
5696+
5697+#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
5698+
5699+struct pxa3xx_mfp_pin {
5700+ unsigned long mfpr_off; /* MFPRxx register offset */
5701+ unsigned long mfpr_val; /* MFPRxx register value */
5702+};
5703+
5704+/*
5705+ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
5706+ * to the MFPR register
5707+ */
5708+unsigned long pxa3xx_mfp_read(int mfp);
5709+void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
5710+
5711+/*
5712+ * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
5713+ * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
5714+ * pxa3xx_mfp_set_lpm - set MFP low power mode state
5715+ * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
5716+ *
5717+ * use these functions to override/change the default configuration
5718+ * done by pxa3xx_mfp_set_config(s)
5719+ */
5720+void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
5721+void pxa3xx_mfp_set_rdh(int mfp, int rdh);
5722+void pxa3xx_mfp_set_lpm(int mfp, int lpm);
5723+void pxa3xx_mfp_set_edge(int mfp, int edge);
5724+
5725+/*
5726+ * pxa3xx_mfp_config - configure the MFPR registers
5727+ *
5728+ * used by board specific initialization code
5729+ */
5730+void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
5731+
5732+/*
5733+ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
5734+ * index and MFPR register offset
5735+ *
5736+ * used by processor specific code
5737+ */
5738+void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
5739+void __init pxa3xx_init_mfp(void);
5740+
5741+#endif /* __ASM_ARCH_MFP_H */
5742--- linux-2.6.23.orig/include/asm-arm/arch-pxa/pxa-regs.h
5743+++ linux-2.6.23/include/asm-arm/arch-pxa/pxa-regs.h
5744@@ -1184,7 +1184,7 @@
5745
5746 #define GPIO_bit(x) (1 << ((x) & 0x1f))
5747
5748-#ifdef CONFIG_PXA27x
5749+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
5750
5751 /* Interrupt Controller */
5752
5753--- /dev/null
5754+++ linux-2.6.23/include/asm-arm/arch-pxa/pxa3xx-regs.h
5755@@ -0,0 +1,75 @@
5756+/*
5757+ * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
5758+ *
5759+ * PXA3xx specific register definitions
5760+ *
5761+ * Copyright (C) 2007 Marvell International Ltd.
5762+ *
5763+ * This program is free software; you can redistribute it and/or modify
5764+ * it under the terms of the GNU General Public License version 2 as
5765+ * published by the Free Software Foundation.
5766+ */
5767+
5768+#ifndef __ASM_ARCH_PXA3XX_REGS_H
5769+#define __ASM_ARCH_PXA3XX_REGS_H
5770+
5771+/*
5772+ * Application Subsystem Clock
5773+ */
5774+#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
5775+#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
5776+#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
5777+#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
5778+#define CKENB __REG(0x41340010) /* B Clock Enable Register */
5779+#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
5780+
5781+/*
5782+ * Clock Enable Bit
5783+ */
5784+#define CKEN_LCD 1 /* < LCD Clock Enable */
5785+#define CKEN_USBH 2 /* < USB host clock enable */
5786+#define CKEN_CAMERA 3 /* < Camera interface clock enable */
5787+#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
5788+#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
5789+#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
5790+#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
5791+#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
5792+#define CKEN_BOOT 11 /* < Boot rom clock enable */
5793+#define CKEN_MMC1 12 /* < MMC1 Clock enable */
5794+#define CKEN_MMC2 13 /* < MMC2 clock enable */
5795+#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
5796+#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
5797+#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
5798+#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
5799+#define CKEN_TPM 19 /* < TPM clock enable */
5800+#define CKEN_UDC 20 /* < UDC clock enable */
5801+#define CKEN_BTUART 21 /* < BTUART clock enable */
5802+#define CKEN_FFUART 22 /* < FFUART clock enable */
5803+#define CKEN_STUART 23 /* < STUART clock enable */
5804+#define CKEN_AC97 24 /* < AC97 clock enable */
5805+#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
5806+#define CKEN_SSP1 26 /* < SSP1 clock enable */
5807+#define CKEN_SSP2 27 /* < SSP2 clock enable */
5808+#define CKEN_SSP3 28 /* < SSP3 clock enable */
5809+#define CKEN_SSP4 29 /* < SSP4 clock enable */
5810+#define CKEN_MSL0 30 /* < MSL0 clock enable */
5811+#define CKEN_PWM0 32 /* < PWM[0] clock enable */
5812+#define CKEN_PWM1 33 /* < PWM[1] clock enable */
5813+#define CKEN_I2C 36 /* < I2C clock enable */
5814+#define CKEN_INTC 38 /* < Interrupt controller clock enable */
5815+#define CKEN_GPIO 39 /* < GPIO clock enable */
5816+#define CKEN_1WIRE 40 /* < 1-wire clock enable */
5817+#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
5818+#define CKEN_MINI_IM 48 /* < Mini-IM */
5819+#define CKEN_MINI_LCD 49 /* < Mini LCD */
5820+
5821+#if defined(CONFIG_CPU_PXA310)
5822+#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
5823+#define CKEN_MVED 43 /* < MVED clock enable */
5824+#endif
5825+
5826+/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
5827+#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
5828+#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
5829+
5830+#endif /* __ASM_ARCH_PXA3XX_REGS_H */
5831--- linux-2.6.23.orig/include/asm-arm/arch-pxa/timex.h
5832+++ linux-2.6.23/include/asm-arm/arch-pxa/timex.h
5833@@ -21,4 +21,6 @@
5834 #else
5835 #define CLOCK_TICK_RATE 3250000
5836 #endif
5837+#else
5838+#define CLOCK_TICK_RATE 3250000
5839 #endif
5840--- /dev/null
5841+++ linux-2.6.23/include/asm-arm/arch-pxa/zylonite.h
5842@@ -0,0 +1,35 @@
5843+#ifndef __ASM_ARCH_ZYLONITE_H
5844+#define __ASM_ARCH_ZYLONITE_H
5845+
5846+#define ZYLONITE_ETH_PHYS 0x14000000
5847+
5848+/* the following variables are processor specific and initialized
5849+ * by the corresponding zylonite_pxa3xx_init()
5850+ */
5851+extern int gpio_backlight;
5852+extern int gpio_eth_irq;
5853+
5854+extern int lcd_id;
5855+extern int lcd_orientation;
5856+
5857+#ifdef CONFIG_CPU_PXA300
5858+extern void zylonite_pxa300_init(void);
5859+#else
5860+static inline void zylonite_pxa300_init(void)
5861+{
5862+ if (cpu_is_pxa300() || cpu_is_pxa310())
5863+ panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
5864+}
5865+#endif
5866+
5867+#ifdef CONFIG_CPU_PXA320
5868+extern void zylonite_pxa320_init(void);
5869+#else
5870+static inline void zylonite_pxa320_init(void)
5871+{
5872+ if (cpu_is_pxa320())
5873+ panic("%s: PXA320 not supported\n", __FUNCTION__);
5874+}
5875+#endif
5876+
5877+#endif /* __ASM_ARCH_ZYLONITE_H */
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-09 10:18:40 +0000