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author | Tudor Florea <tudor.florea@enea.com> | 2015-10-09 22:59:03 +0200 |
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committer | Tudor Florea <tudor.florea@enea.com> | 2015-10-09 22:59:03 +0200 |
commit | 972dcfcdbfe75dcfeb777150c136576cf1a71e99 (patch) | |
tree | 97a61cd7e293d7ae9d56ef7ed0f81253365bb026 /meta/recipes-extended/libaio/libaio/00_arches.patch | |
download | poky-972dcfcdbfe75dcfeb777150c136576cf1a71e99.tar.gz |
initial commit for Enea Linux 5.0 arm
Signed-off-by: Tudor Florea <tudor.florea@enea.com>
Diffstat (limited to 'meta/recipes-extended/libaio/libaio/00_arches.patch')
-rw-r--r-- | meta/recipes-extended/libaio/libaio/00_arches.patch | 779 |
1 files changed, 779 insertions, 0 deletions
diff --git a/meta/recipes-extended/libaio/libaio/00_arches.patch b/meta/recipes-extended/libaio/libaio/00_arches.patch new file mode 100644 index 0000000000..91f4588cc5 --- /dev/null +++ b/meta/recipes-extended/libaio/libaio/00_arches.patch | |||
@@ -0,0 +1,779 @@ | |||
1 | Upstream-Status: Inappropriate [embedded specific] | ||
2 | |||
3 | from openembedded, added by Qing He <qing.he@intel.com> | ||
4 | |||
5 | Index: libaio-0.3.109/src/syscall-m68k.h | ||
6 | =================================================================== | ||
7 | --- /dev/null | ||
8 | +++ libaio-0.3.109/src/syscall-m68k.h | ||
9 | @@ -0,0 +1,78 @@ | ||
10 | +#define __NR_io_setup 241 | ||
11 | +#define __NR_io_destroy 242 | ||
12 | +#define __NR_io_getevents 243 | ||
13 | +#define __NR_io_submit 244 | ||
14 | +#define __NR_io_cancel 245 | ||
15 | + | ||
16 | +#define io_syscall1(type,fname,sname,atype,a) \ | ||
17 | +type fname(atype a) \ | ||
18 | +{ \ | ||
19 | +register long __res __asm__ ("%d0") = __NR_##sname; \ | ||
20 | +register long __a __asm__ ("%d1") = (long)(a); \ | ||
21 | +__asm__ __volatile__ ("trap #0" \ | ||
22 | + : "+d" (__res) \ | ||
23 | + : "d" (__a) ); \ | ||
24 | +return (type) __res; \ | ||
25 | +} | ||
26 | + | ||
27 | +#define io_syscall2(type,fname,sname,atype,a,btype,b) \ | ||
28 | +type fname(atype a,btype b) \ | ||
29 | +{ \ | ||
30 | +register long __res __asm__ ("%d0") = __NR_##sname; \ | ||
31 | +register long __a __asm__ ("%d1") = (long)(a); \ | ||
32 | +register long __b __asm__ ("%d2") = (long)(b); \ | ||
33 | +__asm__ __volatile__ ("trap #0" \ | ||
34 | + : "+d" (__res) \ | ||
35 | + : "d" (__a), "d" (__b) \ | ||
36 | + ); \ | ||
37 | +return (type) __res; \ | ||
38 | +} | ||
39 | + | ||
40 | +#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \ | ||
41 | +type fname(atype a,btype b,ctype c) \ | ||
42 | +{ \ | ||
43 | +register long __res __asm__ ("%d0") = __NR_##sname; \ | ||
44 | +register long __a __asm__ ("%d1") = (long)(a); \ | ||
45 | +register long __b __asm__ ("%d2") = (long)(b); \ | ||
46 | +register long __c __asm__ ("%d3") = (long)(c); \ | ||
47 | +__asm__ __volatile__ ("trap #0" \ | ||
48 | + : "+d" (__res) \ | ||
49 | + : "d" (__a), "d" (__b), \ | ||
50 | + "d" (__c) \ | ||
51 | + ); \ | ||
52 | +return (type) __res; \ | ||
53 | +} | ||
54 | + | ||
55 | +#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \ | ||
56 | +type fname (atype a, btype b, ctype c, dtype d) \ | ||
57 | +{ \ | ||
58 | +register long __res __asm__ ("%d0") = __NR_##sname; \ | ||
59 | +register long __a __asm__ ("%d1") = (long)(a); \ | ||
60 | +register long __b __asm__ ("%d2") = (long)(b); \ | ||
61 | +register long __c __asm__ ("%d3") = (long)(c); \ | ||
62 | +register long __d __asm__ ("%d4") = (long)(d); \ | ||
63 | +__asm__ __volatile__ ("trap #0" \ | ||
64 | + : "+d" (__res) \ | ||
65 | + : "d" (__a), "d" (__b), \ | ||
66 | + "d" (__c), "d" (__d) \ | ||
67 | + ); \ | ||
68 | +return (type) __res; \ | ||
69 | +} | ||
70 | + | ||
71 | +#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ | ||
72 | +type fname (atype a,btype b,ctype c,dtype d,etype e) \ | ||
73 | +{ \ | ||
74 | +register long __res __asm__ ("%d0") = __NR_##sname; \ | ||
75 | +register long __a __asm__ ("%d1") = (long)(a); \ | ||
76 | +register long __b __asm__ ("%d2") = (long)(b); \ | ||
77 | +register long __c __asm__ ("%d3") = (long)(c); \ | ||
78 | +register long __d __asm__ ("%d4") = (long)(d); \ | ||
79 | +register long __e __asm__ ("%d5") = (long)(e); \ | ||
80 | +__asm__ __volatile__ ("trap #0" \ | ||
81 | + : "+d" (__res) \ | ||
82 | + : "d" (__a), "d" (__b), \ | ||
83 | + "d" (__c), "d" (__d), "d" (__e) \ | ||
84 | + ); \ | ||
85 | +return (type) __res; \ | ||
86 | +} | ||
87 | + | ||
88 | Index: libaio-0.3.109/src/syscall-sparc.h | ||
89 | =================================================================== | ||
90 | --- /dev/null | ||
91 | +++ libaio-0.3.109/src/syscall-sparc.h | ||
92 | @@ -0,0 +1,130 @@ | ||
93 | +/* $Id: unistd.h,v 1.74 2002/02/08 03:57:18 davem Exp $ */ | ||
94 | + | ||
95 | +/* | ||
96 | + * System calls under the Sparc. | ||
97 | + * | ||
98 | + * Don't be scared by the ugly clobbers, it is the only way I can | ||
99 | + * think of right now to force the arguments into fixed registers | ||
100 | + * before the trap into the system call with gcc 'asm' statements. | ||
101 | + * | ||
102 | + * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | ||
103 | + * | ||
104 | + * SunOS compatibility based upon preliminary work which is: | ||
105 | + * | ||
106 | + * Copyright (C) 1995 Adrian M. Rodriguez (adrian@remus.rutgers.edu) | ||
107 | + */ | ||
108 | + | ||
109 | + | ||
110 | +#define __NR_io_setup 268 | ||
111 | +#define __NR_io_destroy 269 | ||
112 | +#define __NR_io_submit 270 | ||
113 | +#define __NR_io_cancel 271 | ||
114 | +#define __NR_io_getevents 272 | ||
115 | + | ||
116 | + | ||
117 | +#define io_syscall1(type,fname,sname,type1,arg1) \ | ||
118 | +type fname(type1 arg1) \ | ||
119 | +{ \ | ||
120 | +long __res; \ | ||
121 | +register long __g1 __asm__ ("g1") = __NR_##sname; \ | ||
122 | +register long __o0 __asm__ ("o0") = (long)(arg1); \ | ||
123 | +__asm__ __volatile__ ("t 0x10\n\t" \ | ||
124 | + "bcc 1f\n\t" \ | ||
125 | + "mov %%o0, %0\n\t" \ | ||
126 | + "sub %%g0, %%o0, %0\n\t" \ | ||
127 | + "1:\n\t" \ | ||
128 | + : "=r" (__res), "=&r" (__o0) \ | ||
129 | + : "1" (__o0), "r" (__g1) \ | ||
130 | + : "cc"); \ | ||
131 | +if (__res < -255 || __res >= 0) \ | ||
132 | + return (type) __res; \ | ||
133 | +return -1; \ | ||
134 | +} | ||
135 | + | ||
136 | +#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \ | ||
137 | +type fname(type1 arg1,type2 arg2) \ | ||
138 | +{ \ | ||
139 | +long __res; \ | ||
140 | +register long __g1 __asm__ ("g1") = __NR_##sname; \ | ||
141 | +register long __o0 __asm__ ("o0") = (long)(arg1); \ | ||
142 | +register long __o1 __asm__ ("o1") = (long)(arg2); \ | ||
143 | +__asm__ __volatile__ ("t 0x10\n\t" \ | ||
144 | + "bcc 1f\n\t" \ | ||
145 | + "mov %%o0, %0\n\t" \ | ||
146 | + "sub %%g0, %%o0, %0\n\t" \ | ||
147 | + "1:\n\t" \ | ||
148 | + : "=r" (__res), "=&r" (__o0) \ | ||
149 | + : "1" (__o0), "r" (__o1), "r" (__g1) \ | ||
150 | + : "cc"); \ | ||
151 | +if (__res < -255 || __res >= 0) \ | ||
152 | + return (type) __res; \ | ||
153 | +return -1; \ | ||
154 | +} | ||
155 | + | ||
156 | +#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \ | ||
157 | +type fname(type1 arg1,type2 arg2,type3 arg3) \ | ||
158 | +{ \ | ||
159 | +long __res; \ | ||
160 | +register long __g1 __asm__ ("g1") = __NR_##sname; \ | ||
161 | +register long __o0 __asm__ ("o0") = (long)(arg1); \ | ||
162 | +register long __o1 __asm__ ("o1") = (long)(arg2); \ | ||
163 | +register long __o2 __asm__ ("o2") = (long)(arg3); \ | ||
164 | +__asm__ __volatile__ ("t 0x10\n\t" \ | ||
165 | + "bcc 1f\n\t" \ | ||
166 | + "mov %%o0, %0\n\t" \ | ||
167 | + "sub %%g0, %%o0, %0\n\t" \ | ||
168 | + "1:\n\t" \ | ||
169 | + : "=r" (__res), "=&r" (__o0) \ | ||
170 | + : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__g1) \ | ||
171 | + : "cc"); \ | ||
172 | +if (__res < -255 || __res>=0) \ | ||
173 | + return (type) __res; \ | ||
174 | +return -1; \ | ||
175 | +} | ||
176 | + | ||
177 | +#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
178 | +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
179 | +{ \ | ||
180 | +long __res; \ | ||
181 | +register long __g1 __asm__ ("g1") = __NR_##sname; \ | ||
182 | +register long __o0 __asm__ ("o0") = (long)(arg1); \ | ||
183 | +register long __o1 __asm__ ("o1") = (long)(arg2); \ | ||
184 | +register long __o2 __asm__ ("o2") = (long)(arg3); \ | ||
185 | +register long __o3 __asm__ ("o3") = (long)(arg4); \ | ||
186 | +__asm__ __volatile__ ("t 0x10\n\t" \ | ||
187 | + "bcc 1f\n\t" \ | ||
188 | + "mov %%o0, %0\n\t" \ | ||
189 | + "sub %%g0, %%o0, %0\n\t" \ | ||
190 | + "1:\n\t" \ | ||
191 | + : "=r" (__res), "=&r" (__o0) \ | ||
192 | + : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__g1) \ | ||
193 | + : "cc"); \ | ||
194 | +if (__res < -255 || __res>=0) \ | ||
195 | + return (type) __res; \ | ||
196 | +return -1; \ | ||
197 | +} | ||
198 | + | ||
199 | +#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ | ||
200 | + type5,arg5) \ | ||
201 | +type fname(type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ | ||
202 | +{ \ | ||
203 | +long __res; \ | ||
204 | +register long __g1 __asm__ ("g1") = __NR_##sname; \ | ||
205 | +register long __o0 __asm__ ("o0") = (long)(arg1); \ | ||
206 | +register long __o1 __asm__ ("o1") = (long)(arg2); \ | ||
207 | +register long __o2 __asm__ ("o2") = (long)(arg3); \ | ||
208 | +register long __o3 __asm__ ("o3") = (long)(arg4); \ | ||
209 | +register long __o4 __asm__ ("o4") = (long)(arg5); \ | ||
210 | +__asm__ __volatile__ ("t 0x10\n\t" \ | ||
211 | + "bcc 1f\n\t" \ | ||
212 | + "mov %%o0, %0\n\t" \ | ||
213 | + "sub %%g0, %%o0, %0\n\t" \ | ||
214 | + "1:\n\t" \ | ||
215 | + : "=r" (__res), "=&r" (__o0) \ | ||
216 | + : "1" (__o0), "r" (__o1), "r" (__o2), "r" (__o3), "r" (__o4), "r" (__g1) \ | ||
217 | + : "cc"); \ | ||
218 | +if (__res < -255 || __res>=0) \ | ||
219 | + return (type) __res; \ | ||
220 | +return -1; \ | ||
221 | +} | ||
222 | + | ||
223 | Index: libaio-0.3.109/src/syscall.h | ||
224 | =================================================================== | ||
225 | --- libaio-0.3.109.orig/src/syscall.h | ||
226 | +++ libaio-0.3.109/src/syscall.h | ||
227 | @@ -24,6 +24,14 @@ | ||
228 | #include "syscall-alpha.h" | ||
229 | #elif defined(__arm__) | ||
230 | #include "syscall-arm.h" | ||
231 | +#elif defined(__m68k__) | ||
232 | +#include "syscall-m68k.h" | ||
233 | +#elif defined(__sparc__) | ||
234 | +#include "syscall-sparc.h" | ||
235 | +#elif defined(__hppa__) | ||
236 | +#include "syscall-parisc.h" | ||
237 | +#elif defined(__mips__) | ||
238 | +#include "syscall-mips.h" | ||
239 | #else | ||
240 | #error "add syscall-arch.h" | ||
241 | #endif | ||
242 | Index: libaio-0.3.109/src/syscall-mips.h | ||
243 | =================================================================== | ||
244 | --- /dev/null | ||
245 | +++ libaio-0.3.109/src/syscall-mips.h | ||
246 | @@ -0,0 +1,223 @@ | ||
247 | +/* | ||
248 | + * This file is subject to the terms and conditions of the GNU General Public | ||
249 | + * License. See the file "COPYING" in the main directory of this archive | ||
250 | + * for more details. | ||
251 | + * | ||
252 | + * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle | ||
253 | + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | ||
254 | + * | ||
255 | + * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto | ||
256 | + * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A | ||
257 | + */ | ||
258 | + | ||
259 | +#ifndef _MIPS_SIM_ABI32 | ||
260 | +#define _MIPS_SIM_ABI32 1 | ||
261 | +#define _MIPS_SIM_NABI32 2 | ||
262 | +#define _MIPS_SIM_ABI64 3 | ||
263 | +#endif | ||
264 | + | ||
265 | +#if _MIPS_SIM == _MIPS_SIM_ABI32 | ||
266 | + | ||
267 | +/* | ||
268 | + * Linux o32 style syscalls are in the range from 4000 to 4999. | ||
269 | + */ | ||
270 | +#define __NR_Linux 4000 | ||
271 | +#define __NR_io_setup (__NR_Linux + 241) | ||
272 | +#define __NR_io_destroy (__NR_Linux + 242) | ||
273 | +#define __NR_io_getevents (__NR_Linux + 243) | ||
274 | +#define __NR_io_submit (__NR_Linux + 244) | ||
275 | +#define __NR_io_cancel (__NR_Linux + 245) | ||
276 | + | ||
277 | +#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ | ||
278 | + | ||
279 | +#if _MIPS_SIM == _MIPS_SIM_ABI64 | ||
280 | + | ||
281 | +/* | ||
282 | + * Linux 64-bit syscalls are in the range from 5000 to 5999. | ||
283 | + */ | ||
284 | +#define __NR_Linux 5000 | ||
285 | +#define __NR_io_setup (__NR_Linux + 200) | ||
286 | +#define __NR_io_destroy (__NR_Linux + 201) | ||
287 | +#define __NR_io_getevents (__NR_Linux + 202) | ||
288 | +#define __NR_io_submit (__NR_Linux + 203) | ||
289 | +#define __NR_io_cancel (__NR_Linux + 204) | ||
290 | +#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ | ||
291 | + | ||
292 | +#if _MIPS_SIM == _MIPS_SIM_NABI32 | ||
293 | + | ||
294 | +/* | ||
295 | + * Linux N32 syscalls are in the range from 6000 to 6999. | ||
296 | + */ | ||
297 | +#define __NR_Linux 6000 | ||
298 | +#define __NR_io_setup (__NR_Linux + 200) | ||
299 | +#define __NR_io_destroy (__NR_Linux + 201) | ||
300 | +#define __NR_io_getevents (__NR_Linux + 202) | ||
301 | +#define __NR_io_submit (__NR_Linux + 203) | ||
302 | +#define __NR_io_cancel (__NR_Linux + 204) | ||
303 | +#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ | ||
304 | + | ||
305 | +#define io_syscall1(type,fname,sname,atype,a) \ | ||
306 | +type fname(atype a) \ | ||
307 | +{ \ | ||
308 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
309 | + register unsigned long __a3 asm("$7"); \ | ||
310 | + unsigned long __v0; \ | ||
311 | + \ | ||
312 | + __asm__ volatile ( \ | ||
313 | + ".set\tnoreorder\n\t" \ | ||
314 | + "li\t$2, %3\t\t\t# " #fname "\n\t" \ | ||
315 | + "syscall\n\t" \ | ||
316 | + "move\t%0, $2\n\t" \ | ||
317 | + ".set\treorder" \ | ||
318 | + : "=&r" (__v0), "=r" (__a3) \ | ||
319 | + : "r" (__a0), "i" (__NR_##sname) \ | ||
320 | + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
321 | + "memory"); \ | ||
322 | + \ | ||
323 | + if (__a3 == 0) \ | ||
324 | + return (type) __v0; \ | ||
325 | + return (type) -1; \ | ||
326 | +} | ||
327 | + | ||
328 | +#define io_syscall2(type,fname,sname,atype,a,btype,b) \ | ||
329 | +type fname(atype a, btype b) \ | ||
330 | +{ \ | ||
331 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
332 | + register unsigned long __a1 asm("$5") = (unsigned long) b; \ | ||
333 | + register unsigned long __a3 asm("$7"); \ | ||
334 | + unsigned long __v0; \ | ||
335 | + \ | ||
336 | + __asm__ volatile ( \ | ||
337 | + ".set\tnoreorder\n\t" \ | ||
338 | + "li\t$2, %4\t\t\t# " #fname "\n\t" \ | ||
339 | + "syscall\n\t" \ | ||
340 | + "move\t%0, $2\n\t" \ | ||
341 | + ".set\treorder" \ | ||
342 | + : "=&r" (__v0), "=r" (__a3) \ | ||
343 | + : "r" (__a0), "r" (__a1), "i" (__NR_##sname) \ | ||
344 | + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
345 | + "memory"); \ | ||
346 | + \ | ||
347 | + if (__a3 == 0) \ | ||
348 | + return (type) __v0; \ | ||
349 | + return (type) -1; \ | ||
350 | +} | ||
351 | + | ||
352 | +#define io_syscall3(type,fname,sname,atype,a,btype,b,ctype,c) \ | ||
353 | +type fname(atype a, btype b, ctype c) \ | ||
354 | +{ \ | ||
355 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
356 | + register unsigned long __a1 asm("$5") = (unsigned long) b; \ | ||
357 | + register unsigned long __a2 asm("$6") = (unsigned long) c; \ | ||
358 | + register unsigned long __a3 asm("$7"); \ | ||
359 | + unsigned long __v0; \ | ||
360 | + \ | ||
361 | + __asm__ volatile ( \ | ||
362 | + ".set\tnoreorder\n\t" \ | ||
363 | + "li\t$2, %5\t\t\t# " #fname "\n\t" \ | ||
364 | + "syscall\n\t" \ | ||
365 | + "move\t%0, $2\n\t" \ | ||
366 | + ".set\treorder" \ | ||
367 | + : "=&r" (__v0), "=r" (__a3) \ | ||
368 | + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \ | ||
369 | + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
370 | + "memory"); \ | ||
371 | + \ | ||
372 | + if (__a3 == 0) \ | ||
373 | + return (type) __v0; \ | ||
374 | + return (type) -1; \ | ||
375 | +} | ||
376 | + | ||
377 | +#define io_syscall4(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d) \ | ||
378 | +type fname(atype a, btype b, ctype c, dtype d) \ | ||
379 | +{ \ | ||
380 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
381 | + register unsigned long __a1 asm("$5") = (unsigned long) b; \ | ||
382 | + register unsigned long __a2 asm("$6") = (unsigned long) c; \ | ||
383 | + register unsigned long __a3 asm("$7") = (unsigned long) d; \ | ||
384 | + unsigned long __v0; \ | ||
385 | + \ | ||
386 | + __asm__ volatile ( \ | ||
387 | + ".set\tnoreorder\n\t" \ | ||
388 | + "li\t$2, %5\t\t\t# " #fname "\n\t" \ | ||
389 | + "syscall\n\t" \ | ||
390 | + "move\t%0, $2\n\t" \ | ||
391 | + ".set\treorder" \ | ||
392 | + : "=&r" (__v0), "+r" (__a3) \ | ||
393 | + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname) \ | ||
394 | + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
395 | + "memory"); \ | ||
396 | + \ | ||
397 | + if (__a3 == 0) \ | ||
398 | + return (type) __v0; \ | ||
399 | + return (type) -1; \ | ||
400 | +} | ||
401 | + | ||
402 | +#if (_MIPS_SIM == _MIPS_SIM_ABI32) | ||
403 | + | ||
404 | +/* | ||
405 | + * Using those means your brain needs more than an oil change ;-) | ||
406 | + */ | ||
407 | + | ||
408 | +#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ | ||
409 | +type fname(atype a, btype b, ctype c, dtype d, etype e) \ | ||
410 | +{ \ | ||
411 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
412 | + register unsigned long __a1 asm("$5") = (unsigned long) b; \ | ||
413 | + register unsigned long __a2 asm("$6") = (unsigned long) c; \ | ||
414 | + register unsigned long __a3 asm("$7") = (unsigned long) d; \ | ||
415 | + unsigned long __v0; \ | ||
416 | + \ | ||
417 | + __asm__ volatile ( \ | ||
418 | + ".set\tnoreorder\n\t" \ | ||
419 | + "lw\t$2, %6\n\t" \ | ||
420 | + "subu\t$29, 32\n\t" \ | ||
421 | + "sw\t$2, 16($29)\n\t" \ | ||
422 | + "li\t$2, %5\t\t\t# " #fname "\n\t" \ | ||
423 | + "syscall\n\t" \ | ||
424 | + "move\t%0, $2\n\t" \ | ||
425 | + "addiu\t$29, 32\n\t" \ | ||
426 | + ".set\treorder" \ | ||
427 | + : "=&r" (__v0), "+r" (__a3) \ | ||
428 | + : "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##sname), \ | ||
429 | + "m" ((unsigned long)e) \ | ||
430 | + : "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
431 | + "memory"); \ | ||
432 | + \ | ||
433 | + if (__a3 == 0) \ | ||
434 | + return (type) __v0; \ | ||
435 | + return (type) -1; \ | ||
436 | +} | ||
437 | + | ||
438 | +#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */ | ||
439 | + | ||
440 | +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) | ||
441 | + | ||
442 | +#define io_syscall5(type,fname,sname,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ | ||
443 | +type fname (atype a,btype b,ctype c,dtype d,etype e) \ | ||
444 | +{ \ | ||
445 | + register unsigned long __a0 asm("$4") = (unsigned long) a; \ | ||
446 | + register unsigned long __a1 asm("$5") = (unsigned long) b; \ | ||
447 | + register unsigned long __a2 asm("$6") = (unsigned long) c; \ | ||
448 | + register unsigned long __a3 asm("$7") = (unsigned long) d; \ | ||
449 | + register unsigned long __a4 asm("$8") = (unsigned long) e; \ | ||
450 | + unsigned long __v0; \ | ||
451 | + \ | ||
452 | + __asm__ volatile ( \ | ||
453 | + ".set\tnoreorder\n\t" \ | ||
454 | + "li\t$2, %6\t\t\t# " #fname "\n\t" \ | ||
455 | + "syscall\n\t" \ | ||
456 | + "move\t%0, $2\n\t" \ | ||
457 | + ".set\treorder" \ | ||
458 | + : "=&r" (__v0), "+r" (__a3) \ | ||
459 | + : "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##sname) \ | ||
460 | + : "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \ | ||
461 | + "memory"); \ | ||
462 | + \ | ||
463 | + if (__a3 == 0) \ | ||
464 | + return (type) __v0; \ | ||
465 | + return (type) -1; \ | ||
466 | +} | ||
467 | + | ||
468 | +#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ | ||
469 | + | ||
470 | Index: libaio-0.3.109/src/libaio.h | ||
471 | =================================================================== | ||
472 | --- libaio-0.3.109.orig/src/libaio.h | ||
473 | +++ libaio-0.3.109/src/libaio.h | ||
474 | @@ -83,6 +83,30 @@ typedef enum io_iocb_cmd { | ||
475 | #define PADDEDptr(x, y) x; unsigned y | ||
476 | #define PADDEDul(x, y) unsigned long x; unsigned y | ||
477 | # endif | ||
478 | +#elif defined(__m68k__) /* big endian, 32 bits */ | ||
479 | +#define PADDED(x, y) unsigned y; x | ||
480 | +#define PADDEDptr(x, y) unsigned y; x | ||
481 | +#define PADDEDul(x, y) unsigned y; unsigned long x | ||
482 | +#elif defined(__sparc__) /* big endian, 32 bits */ | ||
483 | +#define PADDED(x, y) unsigned y; x | ||
484 | +#define PADDEDptr(x, y) unsigned y; x | ||
485 | +#define PADDEDul(x, y) unsigned y; unsigned long x | ||
486 | +#elif defined(__hppa__) /* big endian, 32 bits */ | ||
487 | +#define PADDED(x, y) unsigned y; x | ||
488 | +#define PADDEDptr(x, y) unsigned y; x | ||
489 | +#define PADDEDul(x, y) unsigned y; unsigned long x | ||
490 | +#elif defined(__mips__) | ||
491 | +# if defined (__MIPSEB__) /* big endian, 32 bits */ | ||
492 | +#define PADDED(x, y) unsigned y; x | ||
493 | +#define PADDEDptr(x, y) unsigned y; x | ||
494 | +#define PADDEDul(x, y) unsigned y; unsigned long x | ||
495 | +# elif defined(__MIPSEL__) /* little endian, 32 bits */ | ||
496 | +#define PADDED(x, y) x; unsigned y | ||
497 | +#define PADDEDptr(x, y) x; unsigned y | ||
498 | +#define PADDEDul(x, y) unsigned long x; unsigned y | ||
499 | +# else | ||
500 | +# error "neither mipseb nor mipsel?" | ||
501 | +# endif | ||
502 | #else | ||
503 | #error endian? | ||
504 | #endif | ||
505 | Index: libaio-0.3.109/src/syscall-parisc.h | ||
506 | =================================================================== | ||
507 | --- /dev/null | ||
508 | +++ libaio-0.3.109/src/syscall-parisc.h | ||
509 | @@ -0,0 +1,146 @@ | ||
510 | +/* | ||
511 | + * Linux system call numbers. | ||
512 | + * | ||
513 | + * Cary Coutant says that we should just use another syscall gateway | ||
514 | + * page to avoid clashing with the HPUX space, and I think he's right: | ||
515 | + * it will would keep a branch out of our syscall entry path, at the | ||
516 | + * very least. If we decide to change it later, we can ``just'' tweak | ||
517 | + * the LINUX_GATEWAY_ADDR define at the bottom and make __NR_Linux be | ||
518 | + * 1024 or something. Oh, and recompile libc. =) | ||
519 | + * | ||
520 | + * 64-bit HPUX binaries get the syscall gateway address passed in a register | ||
521 | + * from the kernel at startup, which seems a sane strategy. | ||
522 | + */ | ||
523 | + | ||
524 | +#define __NR_Linux 0 | ||
525 | +#define __NR_io_setup (__NR_Linux + 215) | ||
526 | +#define __NR_io_destroy (__NR_Linux + 216) | ||
527 | +#define __NR_io_getevents (__NR_Linux + 217) | ||
528 | +#define __NR_io_submit (__NR_Linux + 218) | ||
529 | +#define __NR_io_cancel (__NR_Linux + 219) | ||
530 | + | ||
531 | +#define SYS_ify(syscall_name) __NR_##syscall_name | ||
532 | + | ||
533 | +/* Assume all syscalls are done from PIC code just to be | ||
534 | + * safe. The worst case scenario is that you lose a register | ||
535 | + * and save/restore r19 across the syscall. */ | ||
536 | +#define PIC | ||
537 | + | ||
538 | +/* Definition taken from glibc 2.3.3 | ||
539 | + * sysdeps/unix/sysv/linux/hppa/sysdep.h | ||
540 | + */ | ||
541 | + | ||
542 | +#ifdef PIC | ||
543 | +/* WARNING: CANNOT BE USED IN A NOP! */ | ||
544 | +# define K_STW_ASM_PIC " copy %%r19, %%r4\n" | ||
545 | +# define K_LDW_ASM_PIC " copy %%r4, %%r19\n" | ||
546 | +# define K_USING_GR4 "%r4", | ||
547 | +#else | ||
548 | +# define K_STW_ASM_PIC " \n" | ||
549 | +# define K_LDW_ASM_PIC " \n" | ||
550 | +# define K_USING_GR4 | ||
551 | +#endif | ||
552 | + | ||
553 | +/* GCC has to be warned that a syscall may clobber all the ABI | ||
554 | + registers listed as "caller-saves", see page 8, Table 2 | ||
555 | + in section 2.2.6 of the PA-RISC RUN-TIME architecture | ||
556 | + document. However! r28 is the result and will conflict with | ||
557 | + the clobber list so it is left out. Also the input arguments | ||
558 | + registers r20 -> r26 will conflict with the list so they | ||
559 | + are treated specially. Although r19 is clobbered by the syscall | ||
560 | + we cannot say this because it would violate ABI, thus we say | ||
561 | + r4 is clobbered and use that register to save/restore r19 | ||
562 | + across the syscall. */ | ||
563 | + | ||
564 | +#define K_CALL_CLOB_REGS "%r1", "%r2", K_USING_GR4 \ | ||
565 | + "%r20", "%r29", "%r31" | ||
566 | + | ||
567 | +#undef K_INLINE_SYSCALL | ||
568 | +#define K_INLINE_SYSCALL(name, nr, args...) ({ \ | ||
569 | + long __sys_res; \ | ||
570 | + { \ | ||
571 | + register unsigned long __res __asm__("r28"); \ | ||
572 | + K_LOAD_ARGS_##nr(args) \ | ||
573 | + /* FIXME: HACK stw/ldw r19 around syscall */ \ | ||
574 | + __asm__ volatile( \ | ||
575 | + K_STW_ASM_PIC \ | ||
576 | + " ble 0x100(%%sr2, %%r0)\n" \ | ||
577 | + " ldi %1, %%r20\n" \ | ||
578 | + K_LDW_ASM_PIC \ | ||
579 | + : "=r" (__res) \ | ||
580 | + : "i" (SYS_ify(name)) K_ASM_ARGS_##nr \ | ||
581 | + : "memory", K_CALL_CLOB_REGS K_CLOB_ARGS_##nr \ | ||
582 | + ); \ | ||
583 | + __sys_res = (long)__res; \ | ||
584 | + } \ | ||
585 | + __sys_res; \ | ||
586 | +}) | ||
587 | + | ||
588 | +#define K_LOAD_ARGS_0() | ||
589 | +#define K_LOAD_ARGS_1(r26) \ | ||
590 | + register unsigned long __r26 __asm__("r26") = (unsigned long)(r26); \ | ||
591 | + K_LOAD_ARGS_0() | ||
592 | +#define K_LOAD_ARGS_2(r26,r25) \ | ||
593 | + register unsigned long __r25 __asm__("r25") = (unsigned long)(r25); \ | ||
594 | + K_LOAD_ARGS_1(r26) | ||
595 | +#define K_LOAD_ARGS_3(r26,r25,r24) \ | ||
596 | + register unsigned long __r24 __asm__("r24") = (unsigned long)(r24); \ | ||
597 | + K_LOAD_ARGS_2(r26,r25) | ||
598 | +#define K_LOAD_ARGS_4(r26,r25,r24,r23) \ | ||
599 | + register unsigned long __r23 __asm__("r23") = (unsigned long)(r23); \ | ||
600 | + K_LOAD_ARGS_3(r26,r25,r24) | ||
601 | +#define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \ | ||
602 | + register unsigned long __r22 __asm__("r22") = (unsigned long)(r22); \ | ||
603 | + K_LOAD_ARGS_4(r26,r25,r24,r23) | ||
604 | +#define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \ | ||
605 | + register unsigned long __r21 __asm__("r21") = (unsigned long)(r21); \ | ||
606 | + K_LOAD_ARGS_5(r26,r25,r24,r23,r22) | ||
607 | + | ||
608 | +/* Even with zero args we use r20 for the syscall number */ | ||
609 | +#define K_ASM_ARGS_0 | ||
610 | +#define K_ASM_ARGS_1 K_ASM_ARGS_0, "r" (__r26) | ||
611 | +#define K_ASM_ARGS_2 K_ASM_ARGS_1, "r" (__r25) | ||
612 | +#define K_ASM_ARGS_3 K_ASM_ARGS_2, "r" (__r24) | ||
613 | +#define K_ASM_ARGS_4 K_ASM_ARGS_3, "r" (__r23) | ||
614 | +#define K_ASM_ARGS_5 K_ASM_ARGS_4, "r" (__r22) | ||
615 | +#define K_ASM_ARGS_6 K_ASM_ARGS_5, "r" (__r21) | ||
616 | + | ||
617 | +/* The registers not listed as inputs but clobbered */ | ||
618 | +#define K_CLOB_ARGS_6 | ||
619 | +#define K_CLOB_ARGS_5 K_CLOB_ARGS_6, "%r21" | ||
620 | +#define K_CLOB_ARGS_4 K_CLOB_ARGS_5, "%r22" | ||
621 | +#define K_CLOB_ARGS_3 K_CLOB_ARGS_4, "%r23" | ||
622 | +#define K_CLOB_ARGS_2 K_CLOB_ARGS_3, "%r24" | ||
623 | +#define K_CLOB_ARGS_1 K_CLOB_ARGS_2, "%r25" | ||
624 | +#define K_CLOB_ARGS_0 K_CLOB_ARGS_1, "%r26" | ||
625 | + | ||
626 | +#define io_syscall1(type,fname,sname,type1,arg1) \ | ||
627 | +type fname(type1 arg1) \ | ||
628 | +{ \ | ||
629 | + return K_INLINE_SYSCALL(sname, 1, arg1); \ | ||
630 | +} | ||
631 | + | ||
632 | +#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \ | ||
633 | +type fname(type1 arg1, type2 arg2) \ | ||
634 | +{ \ | ||
635 | + return K_INLINE_SYSCALL(sname, 2, arg1, arg2); \ | ||
636 | +} | ||
637 | + | ||
638 | +#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \ | ||
639 | +type fname(type1 arg1, type2 arg2, type3 arg3) \ | ||
640 | +{ \ | ||
641 | + return K_INLINE_SYSCALL(sname, 3, arg1, arg2, arg3); \ | ||
642 | +} | ||
643 | + | ||
644 | +#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ | ||
645 | +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ | ||
646 | +{ \ | ||
647 | + return K_INLINE_SYSCALL(sname, 4, arg1, arg2, arg3, arg4); \ | ||
648 | +} | ||
649 | + | ||
650 | +#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ | ||
651 | +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ | ||
652 | +{ \ | ||
653 | + return K_INLINE_SYSCALL(sname, 5, arg1, arg2, arg3, arg4, arg5); \ | ||
654 | +} | ||
655 | + | ||
656 | Index: libaio-0.3.109/src/syscall-arm.h | ||
657 | =================================================================== | ||
658 | --- libaio-0.3.109.orig/src/syscall-arm.h | ||
659 | +++ libaio-0.3.109/src/syscall-arm.h | ||
660 | @@ -114,3 +114,119 @@ type fname(type1 arg1, type2 arg2, type3 | ||
661 | return (type) __res_r0; \ | ||
662 | } | ||
663 | |||
664 | +/* | ||
665 | + * linux/include/asm-arm/unistd.h | ||
666 | + * | ||
667 | + * Copyright (C) 2001-2005 Russell King | ||
668 | + * | ||
669 | + * This program is free software; you can redistribute it and/or modify | ||
670 | + * it under the terms of the GNU General Public License version 2 as | ||
671 | + * published by the Free Software Foundation. | ||
672 | + * | ||
673 | + * Please forward _all_ changes to this file to rmk@arm.linux.org.uk, | ||
674 | + * no matter what the change is. Thanks! | ||
675 | + */ | ||
676 | + | ||
677 | +#define __NR_OABI_SYSCALL_BASE 0x900000 | ||
678 | + | ||
679 | +#if defined(__thumb__) || defined(__ARM_EABI__) | ||
680 | +#define __NR_SYSCALL_BASE 0 | ||
681 | +#else | ||
682 | +#define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE | ||
683 | +#endif | ||
684 | + | ||
685 | +#define __NR_io_setup (__NR_SYSCALL_BASE+243) | ||
686 | +#define __NR_io_destroy (__NR_SYSCALL_BASE+244) | ||
687 | +#define __NR_io_getevents (__NR_SYSCALL_BASE+245) | ||
688 | +#define __NR_io_submit (__NR_SYSCALL_BASE+246) | ||
689 | +#define __NR_io_cancel (__NR_SYSCALL_BASE+247) | ||
690 | + | ||
691 | +#define __sys2(x) #x | ||
692 | +#define __sys1(x) __sys2(x) | ||
693 | + | ||
694 | +#if defined(__thumb__) || defined(__ARM_EABI__) | ||
695 | +#define __SYS_REG(name) register long __sysreg __asm__("r7") = __NR_##name; | ||
696 | +#define __SYS_REG_LIST(regs...) "r" (__sysreg) , ##regs | ||
697 | +#define __syscall(name) "swi\t0" | ||
698 | +#else | ||
699 | +#define __SYS_REG(name) | ||
700 | +#define __SYS_REG_LIST(regs...) regs | ||
701 | +#define __syscall(name) "swi\t" __sys1(__NR_##name) "" | ||
702 | +#endif | ||
703 | + | ||
704 | +#define io_syscall1(type,fname,sname,type1,arg1) \ | ||
705 | +type fname(type1 arg1) { \ | ||
706 | + __SYS_REG(sname) \ | ||
707 | + register long __r0 __asm__("r0") = (long)arg1; \ | ||
708 | + register long __res_r0 __asm__("r0"); \ | ||
709 | + __asm__ __volatile__ ( \ | ||
710 | + __syscall(sname) \ | ||
711 | + : "=r" (__res_r0) \ | ||
712 | + : __SYS_REG_LIST( "0" (__r0) ) \ | ||
713 | + : "memory" ); \ | ||
714 | + return (type) __res_r0; \ | ||
715 | +} | ||
716 | + | ||
717 | +#define io_syscall2(type,fname,sname,type1,arg1,type2,arg2) \ | ||
718 | +type fname(type1 arg1,type2 arg2) { \ | ||
719 | + __SYS_REG(sname) \ | ||
720 | + register long __r0 __asm__("r0") = (long)arg1; \ | ||
721 | + register long __r1 __asm__("r1") = (long)arg2; \ | ||
722 | + register long __res_r0 __asm__("r0"); \ | ||
723 | + __asm__ __volatile__ ( \ | ||
724 | + __syscall(sname) \ | ||
725 | + : "=r" (__res_r0) \ | ||
726 | + : __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) \ | ||
727 | + : "memory" ); \ | ||
728 | + return (type) __res_r0; \ | ||
729 | +} | ||
730 | + | ||
731 | +#define io_syscall3(type,fname,sname,type1,arg1,type2,arg2,type3,arg3) \ | ||
732 | +type fname(type1 arg1,type2 arg2,type3 arg3) { \ | ||
733 | + __SYS_REG(sname) \ | ||
734 | + register long __r0 __asm__("r0") = (long)arg1; \ | ||
735 | + register long __r1 __asm__("r1") = (long)arg2; \ | ||
736 | + register long __r2 __asm__("r2") = (long)arg3; \ | ||
737 | + register long __res_r0 __asm__("r0"); \ | ||
738 | + __asm__ __volatile__ ( \ | ||
739 | + __syscall(sname) \ | ||
740 | + : "=r" (__res_r0) \ | ||
741 | + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) \ | ||
742 | + : "memory" ); \ | ||
743 | + return (type) __res_r0; \ | ||
744 | +} | ||
745 | + | ||
746 | +#define io_syscall4(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4)\ | ||
747 | +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \ | ||
748 | + __SYS_REG(sname) \ | ||
749 | + register long __r0 __asm__("r0") = (long)arg1; \ | ||
750 | + register long __r1 __asm__("r1") = (long)arg2; \ | ||
751 | + register long __r2 __asm__("r2") = (long)arg3; \ | ||
752 | + register long __r3 __asm__("r3") = (long)arg4; \ | ||
753 | + register long __res_r0 __asm__("r0"); \ | ||
754 | + __asm__ __volatile__ ( \ | ||
755 | + __syscall(sname) \ | ||
756 | + : "=r" (__res_r0) \ | ||
757 | + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) \ | ||
758 | + : "memory" ); \ | ||
759 | + return (type) __res_r0; \ | ||
760 | +} | ||
761 | + | ||
762 | +#define io_syscall5(type,fname,sname,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ | ||
763 | +type fname(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) {\ | ||
764 | + __SYS_REG(sname) \ | ||
765 | + register long __r0 __asm__("r0") = (long)arg1; \ | ||
766 | + register long __r1 __asm__("r1") = (long)arg2; \ | ||
767 | + register long __r2 __asm__("r2") = (long)arg3; \ | ||
768 | + register long __r3 __asm__("r3") = (long)arg4; \ | ||
769 | + register long __r4 __asm__("r4") = (long)arg5; \ | ||
770 | + register long __res_r0 __asm__("r0"); \ | ||
771 | + __asm__ __volatile__ ( \ | ||
772 | + __syscall(sname) \ | ||
773 | + : "=r" (__res_r0) \ | ||
774 | + : __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \ | ||
775 | + "r" (__r3), "r" (__r4) ) \ | ||
776 | + : "memory" ); \ | ||
777 | + return (type) __res_r0; \ | ||
778 | +} | ||
779 | + | ||