gcc-4.8: fix ICE of cross-compile for PowerPC e500v2 targets

  * http://gcc.gnu.org/bugzilla//show_bug.cgi?id=57717#c7

  * fix the segfault issue of dd on e500v2 targets
    Since double-float is disabled for e500v2 targets build due to ICE of gcc-4.8.1,
    accordingly %Ld format of sprintf is disabled.
    Address Bug 4910 - [p1022ds]urandom: segmentation fault

(From OE-Core rev: a4fefac26d91bc56d5d28e1c9973a189d2509d45)

Signed-off-by: Chunrong Guo <B40290@freescale.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

2 files changed, 22 insertions, 0 deletions

diff --git a/meta/recipes-devtools/gcc/gcc-4.8.inc b/meta/recipes-devtools/gcc/gcc-4.8.inc
index 39f323d87e..0fbbc1d9bc 100644
--- a/meta/recipes-devtools/gcc/gcc-4.8.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.8.inc
@@ -74,6 +74,7 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
            file://0042-pr57748.patch \
            file://0043-cpp.patch \
            file://0044-gengtypes.patch \
+           file://0045-gcc-4.8-PR57717-PowerPC-E500v2.patch \
           "
 SRC_URI[md5sum] = "3b2386c114cd74185aa3754b58a79304"
 SRC_URI[sha256sum] = "545b44be3ad9f2c4e90e6880f5c9d4f0a8f0e5f67e1ffb0d45da9fa01bb05813"
diff --git a/meta/recipes-devtools/gcc/gcc-4.8/0045-gcc-4.8-PR57717-PowerPC-E500v2.patch b/meta/recipes-devtools/gcc/gcc-4.8/0045-gcc-4.8-PR57717-PowerPC-E500v2.patch
new file mode 100644
index 0000000000..96fa1da073
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.8/0045-gcc-4.8-PR57717-PowerPC-E500v2.patch
@@ -0,0 +1,21 @@
+This backports fix from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57717
+
+Upstream-Status: Backport
+Signed-off-by: Julian Brown <Julian_Brown@mentor.com>
+
+fix for PR57717 (PowerPC E500v2)
+http://gcc.gnu.org/ml/gcc-patches/2013-08/msg00668.html
+
+--- a/gcc/config/rs6000/rs6000.c        2013-05-09 20:54:06.000000000 -0500
++++ b/gcc/config/rs6000/rs6000.c        2013-08-28 01:25:24.865218744 -0500
+@@ -6337,9 +6337,7 @@
+       && GET_CODE (XEXP (x, 1)) == CONST_INT
+       && reg_offset_p
+       && !SPE_VECTOR_MODE (mode)
+-      && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
+-                                 || mode == DDmode || mode == TDmode
+-                                 || mode == DImode))
++      && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+       && VECTOR_MEM_NONE_P (mode))
+     {
+       HOST_WIDE_INT val = INTVAL (XEXP (x, 1));