gcc: add patch for ice 50099, which caused lttng-ust not to build

[YOCTO #1381]

This patch came from from GCC Bugzilla via Khem

Cc: Khem Raj <raj.khem@gmail.com>
(From OE-Core rev: 61dac2f6f68bc46d8f3f6f7a8757924f103c7c54)

Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

1 files changed, 49 insertions, 0 deletions

diff --git a/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch b/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
new file mode 100644
index 0000000000..57b03d2bfb
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6/fix-for-ice-50099.patch
@@ -0,0 +1,49 @@
+
+This patch address an issue with the compiler generating an ICE
+during compliation of lttng-ust.
+
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50099
+
+Upstream-Status: Pending
+
+Signed-off-by: Khem Raj <khem.raj@gmail.com>
+Signed-off-by: Saul Wold <sgw@linux.intel.com>
+
+Index: gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.6.0/gcc/config/arm/arm.md     (revision 178135)
++++ gcc-4.6.0/gcc/config/arm/arm.md     (working copy)
+@@ -4217,6 +4217,7 @@ (define_split
+   "TARGET_32BIT"
+   [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
+ {
++  rtx srcop = operands[1];
+   rtx lo_part = gen_lowpart (SImode, operands[0]);
+   enum machine_mode src_mode = GET_MODE (operands[1]);
+ 
+@@ -4224,14 +4225,21 @@ (define_split
+       && !reg_overlap_mentioned_p (operands[0], operands[1]))
+     emit_clobber (operands[0]);
+ 
++  if (TARGET_ARM && src_mode == QImode
++      && !arm_reg_or_extendqisi_mem_op (srcop, QImode))
++    {
++      rtx dest = gen_lowpart (QImode, lo_part);
++      emit_move_insn (dest, srcop);
++      srcop = dest;
++    }
+   if (!REG_P (lo_part) || src_mode != SImode
+-      || !rtx_equal_p (lo_part, operands[1]))
++      || !rtx_equal_p (lo_part, srcop))
+     {
+       if (src_mode == SImode)
+-        emit_move_insn (lo_part, operands[1]);
++        emit_move_insn (lo_part, srcop);
+       else
+         emit_insn (gen_rtx_SET (VOIDmode, lo_part,
+-                               gen_rtx_SIGN_EXTEND (SImode, operands[1])));
++                               gen_rtx_SIGN_EXTEND (SImode, srcop)));
+       operands[1] = lo_part;
+     }
+   operands[0] = gen_highpart (SImode, operands[0]);
+