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authorKhem Raj <raj.khem@gmail.com>2011-04-30 12:37:47 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2011-05-05 12:26:41 +0100
commit478deec11f3349d61b1a922f047dc958dc07262a (patch)
tree1843907b36de2bcb8f821d49d8c9a88014ef0dc7 /meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch
parentd42dccf886983ba14ccc868041d7bea0cf1a260e (diff)
downloadpoky-478deec11f3349d61b1a922f047dc958dc07262a.tar.gz
gcc-4.6.0: Backport FSF 4.6 branch patches
This is set of bugfixes that has been done on FSF gcc-4_2-branch since 4.6.0 was released They will roll into 4.6.1 release once that happens in coming approx 6 months time then we can simply remove them thats the reason so use a separate .inc file to define the SRC_URI additions (From OE-Core rev: b0d5b9f12adbce2c4a0df6059f5671188cd32293) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch')
-rw-r--r--meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch405
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diff --git a/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch
new file mode 100644
index 0000000000..ea74a0817e
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6.0/gcc-4_6-branch-backports/0020-config-rx-rx.h-LABEL_ALIGN_AFTER_BARRIER-Define.patch
@@ -0,0 +1,405 @@
1From 04688242805dcf2a1e9c8948a3d15611d88c1520 Mon Sep 17 00:00:00 2001
2From: nickc <nickc@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Tue, 29 Mar 2011 12:27:07 +0000
4Subject: [PATCH 020/200] * config/rx/rx.h (LABEL_ALIGN_AFTER_BARRIER): Define.
5 (ASM_OUTPUT_MAX_SKIP): Define.
6 * config/rx/predicates.md (rx_zs_comparison_operator): Do not
7 allow LT aor GE comparisons.
8 * config/rx/rx-protos.h (rx_align_for_label): Prototype.
9 * config/rx/rx.md: Add peepholes and patterns to combine extending
10 loads with simple arithmetic instructions.
11 * config/rx/rx.c (rx_is_legitimate_address): Allow QI and HI modes
12 to use pre-decrement and post-increment addressing.
13 (rx_is_restricted_memory_address): For REG+INT addressing, ensure
14 that the INT is a valid offset.
15 (rx_print_operand): Handle %R.
16 Fix %Q's handling of MEMs.
17 (rx_option_override): Set alignments.
18 (rx_align_for_label): New function.
19 (rx_max_skip_for_label): New function.
20 (TARGET_ASM_JUMP_ALIGN_MAX_SKIP): Define.
21 (TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Define.
22 (TARGET_ASM_LABEL_ALIGN_MAX_SKIP): Define.
23 (TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Define.
24
25git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@171659 138bc75d-0d04-0410-961f-82ee72b054a4
26
27index 77b3353..82cac42 100644
28--- a/gcc/config/rx/predicates.md
29+++ b/gcc/config/rx/predicates.md
30@@ -284,7 +284,7 @@
31 )
32
33 (define_predicate "rx_zs_comparison_operator"
34- (match_code "eq,ne,lt,ge")
35+ (match_code "eq,ne")
36 )
37
38 ;; GT and LE omitted due to operand swap required.
39diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h
40index a6ae416..e1ab9c2 100644
41--- a/gcc/config/rx/rx-protos.h
42+++ b/gcc/config/rx/rx-protos.h
43@@ -30,16 +30,17 @@ extern void rx_expand_prologue (void);
44 extern int rx_initial_elimination_offset (int, int);
45
46 #ifdef RTX_CODE
47+extern int rx_align_for_label (void);
48 extern void rx_emit_stack_popm (rtx *, bool);
49 extern void rx_emit_stack_pushm (rtx *);
50 extern void rx_expand_epilogue (bool);
51 extern char * rx_gen_move_template (rtx *, bool);
52 extern bool rx_is_legitimate_constant (rtx);
53 extern bool rx_is_restricted_memory_address (rtx, Mmode);
54+extern bool rx_match_ccmode (rtx, Mmode);
55 extern void rx_notice_update_cc (rtx body, rtx insn);
56 extern void rx_split_cbranch (Mmode, Rcode, rtx, rtx, rtx);
57 extern Mmode rx_select_cc_mode (Rcode, rtx, rtx);
58-extern bool rx_match_ccmode (rtx, Mmode);
59 #endif
60
61 #endif /* GCC_RX_PROTOS_H */
62diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
63index 6b179e7..ad8d0bb 100644
64--- a/gcc/config/rx/rx.c
65+++ b/gcc/config/rx/rx.c
66@@ -57,7 +57,7 @@ static void rx_print_operand (FILE *, rtx, int);
67 #define CC_FLAG_Z (1 << 1)
68 #define CC_FLAG_O (1 << 2)
69 #define CC_FLAG_C (1 << 3)
70-#define CC_FLAG_FP (1 << 4) /* fake, to differentiate CC_Fmode */
71+#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
72
73 static unsigned int flags_from_mode (enum machine_mode mode);
74 static unsigned int flags_from_code (enum rtx_code code);
75@@ -85,7 +85,9 @@ rx_is_legitimate_address (Mmode mode, rtx x, bool strict ATTRIBUTE_UNUSED)
76 /* Register Indirect. */
77 return true;
78
79- if (GET_MODE_SIZE (mode) == 4
80+ if ((GET_MODE_SIZE (mode) == 4
81+ || GET_MODE_SIZE (mode) == 2
82+ || GET_MODE_SIZE (mode) == 1)
83 && (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
84 /* Pre-decrement Register Indirect or
85 Post-increment Register Indirect. */
86@@ -187,7 +189,10 @@ rx_is_restricted_memory_address (rtx mem, enum machine_mode mode)
87 base = XEXP (mem, 0);
88 index = XEXP (mem, 1);
89
90- return RX_REG_P (base) && CONST_INT_P (index);
91+ if (! RX_REG_P (base) || ! CONST_INT_P (index))
92+ return false;
93+
94+ return IN_RANGE (INTVAL (index), 0, (0x10000 * GET_MODE_SIZE (mode)) - 1);
95
96 case SYMBOL_REF:
97 /* Can happen when small data is being supported.
98@@ -386,11 +391,14 @@ rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
99 %L Print low part of a DImode register, integer or address.
100 %N Print the negation of the immediate value.
101 %Q If the operand is a MEM, then correctly generate
102- register indirect or register relative addressing. */
103+ register indirect or register relative addressing.
104+ %R Like %Q but for zero-extending loads. */
105
106 static void
107 rx_print_operand (FILE * file, rtx op, int letter)
108 {
109+ bool unsigned_load = false;
110+
111 switch (letter)
112 {
113 case 'A':
114@@ -450,6 +458,7 @@ rx_print_operand (FILE * file, rtx op, int letter)
115 else
116 {
117 unsigned int flags = flags_from_mode (mode);
118+
119 switch (code)
120 {
121 case LT:
122@@ -588,10 +597,15 @@ rx_print_operand (FILE * file, rtx op, int letter)
123 rx_print_integer (file, - INTVAL (op));
124 break;
125
126+ case 'R':
127+ gcc_assert (GET_MODE_SIZE (GET_MODE (op)) < 4);
128+ unsigned_load = true;
129+ /* Fall through. */
130 case 'Q':
131 if (MEM_P (op))
132 {
133 HOST_WIDE_INT offset;
134+ rtx mem = op;
135
136 op = XEXP (op, 0);
137
138@@ -626,22 +640,24 @@ rx_print_operand (FILE * file, rtx op, int letter)
139 rx_print_operand (file, op, 0);
140 fprintf (file, "].");
141
142- switch (GET_MODE_SIZE (GET_MODE (op)))
143+ switch (GET_MODE_SIZE (GET_MODE (mem)))
144 {
145 case 1:
146- gcc_assert (offset < 65535 * 1);
147- fprintf (file, "B");
148+ gcc_assert (offset <= 65535 * 1);
149+ fprintf (file, unsigned_load ? "UB" : "B");
150 break;
151 case 2:
152 gcc_assert (offset % 2 == 0);
153- gcc_assert (offset < 65535 * 2);
154- fprintf (file, "W");
155+ gcc_assert (offset <= 65535 * 2);
156+ fprintf (file, unsigned_load ? "UW" : "W");
157 break;
158- default:
159+ case 4:
160 gcc_assert (offset % 4 == 0);
161- gcc_assert (offset < 65535 * 4);
162+ gcc_assert (offset <= 65535 * 4);
163 fprintf (file, "L");
164 break;
165+ default:
166+ gcc_unreachable ();
167 }
168 break;
169 }
170@@ -2336,6 +2352,13 @@ rx_option_override (void)
171 flag_strict_volatile_bitfields = 1;
172
173 rx_override_options_after_change ();
174+
175+ if (align_jumps == 0 && ! optimize_size)
176+ align_jumps = 3;
177+ if (align_loops == 0 && ! optimize_size)
178+ align_loops = 3;
179+ if (align_labels == 0 && ! optimize_size)
180+ align_labels = 3;
181 }
182
183 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
184@@ -2728,6 +2751,45 @@ rx_match_ccmode (rtx insn, enum machine_mode cc_mode)
185 }
186
187
188+int
189+rx_align_for_label (void)
190+{
191+ return optimize_size ? 1 : 3;
192+}
193+
194+static int
195+rx_max_skip_for_label (rtx lab)
196+{
197+ int opsize;
198+ rtx op;
199+
200+ if (lab == NULL_RTX)
201+ return 0;
202+ op = lab;
203+ do
204+ {
205+ op = next_nonnote_insn (op);
206+ }
207+ while (op && (LABEL_P (op)
208+ || (INSN_P (op) && GET_CODE (PATTERN (op)) == USE)));
209+ if (!op)
210+ return 0;
211+
212+ opsize = get_attr_length (op);
213+ if (opsize >= 0 && opsize < 8)
214+ return opsize - 1;
215+ return 0;
216+}
217+
218+#undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
219+#define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
220+#undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
221+#define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rx_max_skip_for_label
222+#undef TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
223+#define TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP rx_max_skip_for_label
224+#undef TARGET_ASM_LABEL_ALIGN_MAX_SKIP
225+#define TARGET_ASM_LABEL_ALIGN_MAX_SKIP rx_max_skip_for_label
226+
227 #undef TARGET_FUNCTION_VALUE
228 #define TARGET_FUNCTION_VALUE rx_function_value
229
230diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
231index e3966ed..01fc23b 100644
232--- a/gcc/config/rx/rx.h
233+++ b/gcc/config/rx/rx.h
234@@ -615,4 +615,23 @@ typedef unsigned int CUMULATIVE_ARGS;
235 #define BRANCH_COST(SPEED,PREDICT) 1
236 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
237
238-#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
239+#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode((OP), (X), (Y))
240+
241+#define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label ()
242+
243+#define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
244+ do \
245+ { \
246+ if ((LOG) == 0 || (MAX_SKIP) == 0) \
247+ break; \
248+ if (TARGET_AS100_SYNTAX) \
249+ { \
250+ if ((LOG) >= 2) \
251+ fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
252+ else \
253+ fprintf (STREAM, "\t.ALIGN 2\n"); \
254+ } \
255+ else \
256+ fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \
257+ } \
258+ while (0)
259diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
260index cd5b571..641f1d4 100644
261--- a/gcc/config/rx/rx.md
262+++ b/gcc/config/rx/rx.md
263@@ -1545,6 +1545,139 @@
264 (set_attr "length" "3,4,5,6,7,6")]
265 )
266
267+;; A set of peepholes to catch extending loads followed by arithmetic operations.
268+;; We use iterators where possible to reduce the amount of typing and hence the
269+;; possibilities for typos.
270+
271+(define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
272+(define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
273+
274+(define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
275+(define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
276+(define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
277+
278+(define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
279+
280+(define_peephole2
281+ [(set (match_operand:SI 0 "register_operand")
282+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
283+ (parallel [(set (match_operand:SI 2 "register_operand")
284+ (memex_commutative:SI (match_dup 0)
285+ (match_dup 2)))
286+ (clobber (reg:CC CC_REG))])]
287+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
288+ [(parallel [(set:SI (match_dup 2)
289+ (memex_commutative:SI (match_dup 2)
290+ (extend_types:SI (match_dup 1))))
291+ (clobber (reg:CC CC_REG))])]
292+)
293+
294+(define_peephole2
295+ [(set (match_operand:SI 0 "register_operand")
296+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
297+ (parallel [(set (match_operand:SI 2 "register_operand")
298+ (memex_commutative:SI (match_dup 2)
299+ (match_dup 0)))
300+ (clobber (reg:CC CC_REG))])]
301+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
302+ [(parallel [(set:SI (match_dup 2)
303+ (memex_commutative:SI (match_dup 2)
304+ (extend_types:SI (match_dup 1))))
305+ (clobber (reg:CC CC_REG))])]
306+)
307+
308+(define_peephole2
309+ [(set (match_operand:SI 0 "register_operand")
310+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
311+ (parallel [(set (match_operand:SI 2 "register_operand")
312+ (memex_noncomm:SI (match_dup 2)
313+ (match_dup 0)))
314+ (clobber (reg:CC CC_REG))])]
315+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
316+ [(parallel [(set:SI (match_dup 2)
317+ (memex_noncomm:SI (match_dup 2)
318+ (extend_types:SI (match_dup 1))))
319+ (clobber (reg:CC CC_REG))])]
320+)
321+
322+(define_peephole2
323+ [(set (match_operand:SI 0 "register_operand")
324+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
325+ (set (match_operand:SI 2 "register_operand")
326+ (memex_nocc:SI (match_dup 0)
327+ (match_dup 2)))]
328+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
329+ [(set:SI (match_dup 2)
330+ (memex_nocc:SI (match_dup 2)
331+ (extend_types:SI (match_dup 1))))]
332+)
333+
334+(define_peephole2
335+ [(set (match_operand:SI 0 "register_operand")
336+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
337+ (set (match_operand:SI 2 "register_operand")
338+ (memex_nocc:SI (match_dup 2)
339+ (match_dup 0)))]
340+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
341+ [(set:SI (match_dup 2)
342+ (memex_nocc:SI (match_dup 2)
343+ (extend_types:SI (match_dup 1))))]
344+)
345+
346+(define_insn "*<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
347+ [(set (match_operand:SI 0 "register_operand" "=r")
348+ (memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
349+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
350+ (clobber (reg:CC CC_REG))]
351+ ""
352+ "<memex_commutative:op>\t%<extend_types:letter>2, %0"
353+ [(set_attr "timings" "33")
354+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
355+) ;; rather than using iterators we could specify exact sizes.
356+
357+(define_insn "*<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
358+ [(set (match_operand:SI 0 "register_operand" "=r")
359+ (memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
360+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
361+ (clobber (reg:CC CC_REG))]
362+ ""
363+ "<memex_noncomm:op>\t%<extend_types:letter>2, %0"
364+ [(set_attr "timings" "33")
365+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
366+) ;; rather than using iterators we could specify exact sizes.
367+
368+(define_insn "*<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
369+ [(set (match_operand:SI 0 "register_operand" "=r")
370+ (memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
371+ (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
372+ ""
373+ "<memex_nocc:op>\t%<extend_types:letter>2, %0"
374+ [(set_attr "timings" "33")
375+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
376+) ;; rather than using iterators we could specify exact sizes.
377+
378+(define_peephole2
379+ [(set (match_operand:SI 0 "register_operand")
380+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
381+ (set (reg:CC CC_REG)
382+ (compare:CC (match_operand:SI 2 "register_operand")
383+ (match_dup 0)))]
384+ "peep2_regno_dead_p (2, REGNO (operands[0]))"
385+ [(set (reg:CC CC_REG)
386+ (compare:CC (match_dup 2)
387+ (extend_types:SI (match_dup 1))))]
388+)
389+
390+(define_insn "*comparesi3_<extend_types:code><small_int_modes:mode>"
391+ [(set (reg:CC CC_REG)
392+ (compare:CC (match_operand:SI 0 "register_operand" "=r")
393+ (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
394+ ""
395+ "cmp\t%<extend_types:letter>1, %0"
396+ [(set_attr "timings" "33")
397+ (set_attr "length" "5")] ;; Worst case sceanario. FIXME: If we defined separate patterns
398+) ;; rather than using iterators we could specify exact sizes.
399+
400 ;; Floating Point Instructions
401
402 (define_insn "addsf3"
403--
4041.7.0.4
405
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