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author | Andrei Gherzan <andrei.gherzan@huawei.com> | 2021-03-09 20:13:21 +0000 |
---|---|---|
committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2021-03-10 10:30:39 +0000 |
commit | 1d7e44d44383bb05285b754e51f649e6de6472c9 (patch) | |
tree | 61896b82d079576bba8d83e301b6f5e361704955 /meta/recipes-core | |
parent | c61948e9b80c664ea298b9f9e4daf3ccec145449 (diff) | |
download | poky-1d7e44d44383bb05285b754e51f649e6de6472c9.tar.gz |
glibc: Backport patch to fix _SC_LEVEL1_ICACHE_LINESIZE
(From OE-Core rev: 89b38e4e7be9e136c71d5860ddca5369f9628393)
Signed-off-by: Andrei Gherzan <andrei.gherzan@huawei.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-core')
-rw-r--r-- | meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch | 185 | ||||
-rw-r--r-- | meta/recipes-core/glibc/glibc_2.33.bb | 1 |
2 files changed, 186 insertions, 0 deletions
diff --git a/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch b/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch new file mode 100644 index 0000000000..3a004e227f --- /dev/null +++ b/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch | |||
@@ -0,0 +1,185 @@ | |||
1 | From 750b00a1ddae220403fd892a6fd4e0791ffd154a Mon Sep 17 00:00:00 2001 | ||
2 | From: "H.J. Lu" <hjl.tools@gmail.com> | ||
3 | Date: Fri, 18 Sep 2020 07:55:14 -0700 | ||
4 | Subject: [PATCH] x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] | ||
5 | |||
6 | x86: Move x86 processor cache info to cpu_features | ||
7 | |||
8 | missed _SC_LEVEL1_ICACHE_LINESIZE. | ||
9 | |||
10 | 1. Add level1_icache_linesize to struct cpu_features. | ||
11 | 2. Initialize level1_icache_linesize by calling handle_intel, | ||
12 | handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE. | ||
13 | 3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE. | ||
14 | |||
15 | Upstream-Status: Backport [https://sourceware.org/bugzilla/show_bug.cgi?id=27444] | ||
16 | Signed-off-by: Andrei Gherzan <andrei.gherzan@huawei.com> | ||
17 | --- | ||
18 | sysdeps/x86/Makefile | 8 +++ | ||
19 | sysdeps/x86/cacheinfo.c | 3 + | ||
20 | sysdeps/x86/dl-cacheinfo.h | 6 ++ | ||
21 | sysdeps/x86/include/cpu-features.h | 2 + | ||
22 | .../x86/tst-sysconf-cache-linesize-static.c | 1 + | ||
23 | sysdeps/x86/tst-sysconf-cache-linesize.c | 57 +++++++++++++++++++ | ||
24 | 6 files changed, 77 insertions(+) | ||
25 | create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize-static.c | ||
26 | create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize.c | ||
27 | |||
28 | diff --git a/sysdeps/x86/Makefile b/sysdeps/x86/Makefile | ||
29 | index dd82674342..d231263051 100644 | ||
30 | --- a/sysdeps/x86/Makefile | ||
31 | +++ b/sysdeps/x86/Makefile | ||
32 | @@ -208,3 +208,11 @@ $(objpfx)check-cet.out: $(..)sysdeps/x86/check-cet.awk \ | ||
33 | generated += check-cet.out | ||
34 | endif | ||
35 | endif | ||
36 | + | ||
37 | +ifeq ($(subdir),posix) | ||
38 | +tests += \ | ||
39 | + tst-sysconf-cache-linesize \ | ||
40 | + tst-sysconf-cache-linesize-static | ||
41 | +tests-static += \ | ||
42 | + tst-sysconf-cache-linesize-static | ||
43 | +endif | ||
44 | diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c | ||
45 | index 7b8df45e3b..5ea4723ca6 100644 | ||
46 | --- a/sysdeps/x86/cacheinfo.c | ||
47 | +++ b/sysdeps/x86/cacheinfo.c | ||
48 | @@ -32,6 +32,9 @@ __cache_sysconf (int name) | ||
49 | case _SC_LEVEL1_ICACHE_SIZE: | ||
50 | return cpu_features->level1_icache_size; | ||
51 | |||
52 | + case _SC_LEVEL1_ICACHE_LINESIZE: | ||
53 | + return cpu_features->level1_icache_linesize; | ||
54 | + | ||
55 | case _SC_LEVEL1_DCACHE_SIZE: | ||
56 | return cpu_features->level1_dcache_size; | ||
57 | |||
58 | diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h | ||
59 | index a31fa0783a..7cd00b92f1 100644 | ||
60 | --- a/sysdeps/x86/dl-cacheinfo.h | ||
61 | +++ b/sysdeps/x86/dl-cacheinfo.h | ||
62 | @@ -707,6 +707,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) | ||
63 | long int core; | ||
64 | unsigned int threads = 0; | ||
65 | unsigned long int level1_icache_size = -1; | ||
66 | + unsigned long int level1_icache_linesize = -1; | ||
67 | unsigned long int level1_dcache_size = -1; | ||
68 | unsigned long int level1_dcache_assoc = -1; | ||
69 | unsigned long int level1_dcache_linesize = -1; | ||
70 | @@ -726,6 +727,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) | ||
71 | |||
72 | level1_icache_size | ||
73 | = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features); | ||
74 | + level1_icache_linesize | ||
75 | + = handle_intel (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features); | ||
76 | level1_dcache_size = data; | ||
77 | level1_dcache_assoc | ||
78 | = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features); | ||
79 | @@ -753,6 +756,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) | ||
80 | shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE); | ||
81 | |||
82 | level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE); | ||
83 | + level1_icache_linesize = handle_zhaoxin (_SC_LEVEL1_ICACHE_LINESIZE); | ||
84 | level1_dcache_size = data; | ||
85 | level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC); | ||
86 | level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE); | ||
87 | @@ -772,6 +776,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) | ||
88 | shared = handle_amd (_SC_LEVEL3_CACHE_SIZE); | ||
89 | |||
90 | level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE); | ||
91 | + level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE); | ||
92 | level1_dcache_size = data; | ||
93 | level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC); | ||
94 | level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE); | ||
95 | @@ -833,6 +838,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) | ||
96 | } | ||
97 | |||
98 | cpu_features->level1_icache_size = level1_icache_size; | ||
99 | + cpu_features->level1_icache_linesize = level1_icache_linesize; | ||
100 | cpu_features->level1_dcache_size = level1_dcache_size; | ||
101 | cpu_features->level1_dcache_assoc = level1_dcache_assoc; | ||
102 | cpu_features->level1_dcache_linesize = level1_dcache_linesize; | ||
103 | diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h | ||
104 | index 624736b40e..39a3f4f311 100644 | ||
105 | --- a/sysdeps/x86/include/cpu-features.h | ||
106 | +++ b/sysdeps/x86/include/cpu-features.h | ||
107 | @@ -874,6 +874,8 @@ struct cpu_features | ||
108 | unsigned long int rep_stosb_threshold; | ||
109 | /* _SC_LEVEL1_ICACHE_SIZE. */ | ||
110 | unsigned long int level1_icache_size; | ||
111 | + /* _SC_LEVEL1_ICACHE_LINESIZE. */ | ||
112 | + unsigned long int level1_icache_linesize; | ||
113 | /* _SC_LEVEL1_DCACHE_SIZE. */ | ||
114 | unsigned long int level1_dcache_size; | ||
115 | /* _SC_LEVEL1_DCACHE_ASSOC. */ | ||
116 | diff --git a/sysdeps/x86/tst-sysconf-cache-linesize-static.c b/sysdeps/x86/tst-sysconf-cache-linesize-static.c | ||
117 | new file mode 100644 | ||
118 | index 0000000000..152ae68821 | ||
119 | --- /dev/null | ||
120 | +++ b/sysdeps/x86/tst-sysconf-cache-linesize-static.c | ||
121 | @@ -0,0 +1 @@ | ||
122 | +#include "tst-sysconf-cache-linesize.c" | ||
123 | diff --git a/sysdeps/x86/tst-sysconf-cache-linesize.c b/sysdeps/x86/tst-sysconf-cache-linesize.c | ||
124 | new file mode 100644 | ||
125 | index 0000000000..642dbde5d2 | ||
126 | --- /dev/null | ||
127 | +++ b/sysdeps/x86/tst-sysconf-cache-linesize.c | ||
128 | @@ -0,0 +1,57 @@ | ||
129 | +/* Test system cache line sizes. | ||
130 | + Copyright (C) 2021 Free Software Foundation, Inc. | ||
131 | + This file is part of the GNU C Library. | ||
132 | + | ||
133 | + The GNU C Library is free software; you can redistribute it and/or | ||
134 | + modify it under the terms of the GNU Lesser General Public | ||
135 | + License as published by the Free Software Foundation; either | ||
136 | + version 2.1 of the License, or (at your option) any later version. | ||
137 | + | ||
138 | + The GNU C Library is distributed in the hope that it will be useful, | ||
139 | + but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
140 | + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
141 | + Lesser General Public License for more details. | ||
142 | + | ||
143 | + You should have received a copy of the GNU Lesser General Public | ||
144 | + License along with the GNU C Library; if not, see | ||
145 | + <https://www.gnu.org/licenses/>. */ | ||
146 | + | ||
147 | +#include <stdio.h> | ||
148 | +#include <stdlib.h> | ||
149 | +#include <unistd.h> | ||
150 | +#include <array_length.h> | ||
151 | + | ||
152 | +static struct | ||
153 | +{ | ||
154 | + const char *name; | ||
155 | + int _SC_val; | ||
156 | +} sc_options[] = | ||
157 | + { | ||
158 | +#define N(name) { "_SC_"#name, _SC_##name } | ||
159 | + N (LEVEL1_ICACHE_LINESIZE), | ||
160 | + N (LEVEL1_DCACHE_LINESIZE), | ||
161 | + N (LEVEL2_CACHE_LINESIZE) | ||
162 | + }; | ||
163 | + | ||
164 | +static int | ||
165 | +do_test (void) | ||
166 | +{ | ||
167 | + int result = EXIT_SUCCESS; | ||
168 | + | ||
169 | + for (int i = 0; i < array_length (sc_options); ++i) | ||
170 | + { | ||
171 | + long int scret = sysconf (sc_options[i]._SC_val); | ||
172 | + if (scret < 0) | ||
173 | + { | ||
174 | + printf ("sysconf (%s) returned < 0 (%ld)\n", | ||
175 | + sc_options[i].name, scret); | ||
176 | + result = EXIT_FAILURE; | ||
177 | + } | ||
178 | + else | ||
179 | + printf ("sysconf (%s): %ld\n", sc_options[i].name, scret); | ||
180 | + } | ||
181 | + | ||
182 | + return result; | ||
183 | +} | ||
184 | + | ||
185 | +#include <support/test-driver.c> | ||
diff --git a/meta/recipes-core/glibc/glibc_2.33.bb b/meta/recipes-core/glibc/glibc_2.33.bb index c47826a51e..ac73bbeb7f 100644 --- a/meta/recipes-core/glibc/glibc_2.33.bb +++ b/meta/recipes-core/glibc/glibc_2.33.bb | |||
@@ -45,6 +45,7 @@ SRC_URI = "${GLIBC_GIT_URI};branch=${SRCBRANCH};name=glibc \ | |||
45 | file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch \ | 45 | file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch \ |
46 | file://0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch \ | 46 | file://0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch \ |
47 | file://0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch \ | 47 | file://0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch \ |
48 | file://0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch \ | ||
48 | " | 49 | " |
49 | S = "${WORKDIR}/git" | 50 | S = "${WORKDIR}/git" |
50 | B = "${WORKDIR}/build-${TARGET_SYS}" | 51 | B = "${WORKDIR}/build-${TARGET_SYS}" |