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authorNathan Rossi <nathan@nathanrossi.com>2017-12-07 19:52:24 +1000
committerRichard Purdie <richard.purdie@linuxfoundation.org>2017-12-18 18:03:57 +0000
commit291378cd00e4a4fb7e1743c44f2696ff0eebb46f (patch)
treeaced3dde775de960d84f8fd3f5a8d6c2c34123f1 /meta/recipes-core/dbus
parentcd92c99462540c9d2f51ec1405187f9a0f794c3a (diff)
downloadpoky-291378cd00e4a4fb7e1743c44f2696ff0eebb46f.tar.gz
conf/machine/include/microblaze: Add MicroBlaze architecture includes
Add architecture and tune includes for MicroBlaze. This covers architecture configuration as well as tune configuration and features. The Xilinx MicroBlaze architecture is a soft-core CPU architecture designed for implementation on Xilinx FPGAs. Because the CPU is a soft-core it can be configured differently depending on resource and performance constraints which affect the ABI and supported instructions. The architecture is also used in other Xilinx products where the core is implemented as part of fixed silicon (e.g. Xilinx ZynqMP). The default tune include 'tune-microblaze.inc' provides the baseline (no features enabled) tune configuration for a target machine. This is similar to other architectures such that the machine.conf includes a tune-*.inc. However due to the customizability configuration is specifically handled on a per machine basis. A machine should configure the available tune features by setting the available features directly by appending to the 'TUNE_FEATURES_tune-microblaze' variable. This tune configuration approach is preferred to avoid the definition of an otherwise large set of possible tune configurations for the available features (14 CPU versions and 11 feature configurations), which would otherwise require >1024 predefined tune configurations. (From OE-Core rev: 295a99a31ca147a271c0c76538c4fb27dbecab27) Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Ross Burton <ross.burton@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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