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authorRichard Purdie <richard@openedhand.com>2007-05-23 23:36:02 +0000
committerRichard Purdie <richard@openedhand.com>2007-05-23 23:36:02 +0000
commitb77dd1b8983ce5f3462a48b8e8d2ac84d2a21b2d (patch)
tree01669b5c1d1c2ea240f60147f3a17430fb975497 /meta/packages
parent765f6203e38fc16d03f24d9d83db3a0e9a805fdc (diff)
downloadpoky-b77dd1b8983ce5f3462a48b8e8d2ac84d2a21b2d.tar.gz
oprofile: Update to new SRCDATE
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@1776 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages')
-rw-r--r--meta/packages/oprofile/oprofile/armv6_events.patch142
1 files changed, 63 insertions, 79 deletions
diff --git a/meta/packages/oprofile/oprofile/armv6_events.patch b/meta/packages/oprofile/oprofile/armv6_events.patch
index 6384e38e55..cbe6efef8e 100644
--- a/meta/packages/oprofile/oprofile/armv6_events.patch
+++ b/meta/packages/oprofile/oprofile/armv6_events.patch
@@ -1,50 +1,28 @@
1--- 1---
2 events/Makefile.am | 1 + 2 events/arm/armv6/events | 9 ++++++---
3 events/arm/armv6/events | 25 +++++++++++++++++++++++++ 3 events/arm/armv6/unit_masks | 2 +-
4 events/arm/armv6/unit_masks | 4 ++++ 4 libop/op_cpu_type.c | 2 +-
5 libop/op_cpu_type.c | 1 + 5 libop/op_cpu_type.h | 2 +-
6 libop/op_cpu_type.h | 1 + 6 libop/op_events.c | 5 +----
7 libop/op_events.c | 1 + 7 utils/ophelp.c | 2 +-
8 utils/ophelp.c | 5 ++++- 8 6 files changed, 11 insertions(+), 11 deletions(-)
9 7 files changed, 37 insertions(+), 1 deletion(-)
10 9
11Index: oprofile/events/Makefile.am
12===================================================================
13--- oprofile.orig/events/Makefile.am 2007-05-23 11:32:24.000000000 +0100
14+++ oprofile/events/Makefile.am 2007-05-23 14:13:12.000000000 +0100
15@@ -29,6 +29,7 @@ event_files = \
16 x86-64/family10/events x86-64/family10/unit_masks \
17 arm/xscale1/events arm/xscale1/unit_masks \
18 arm/xscale2/events arm/xscale2/unit_masks \
19+ arm/armv6/events arm/armv6/unit_masks \
20 mips/20K/events mips/20K/unit_masks \
21 mips/24K/events mips/24K/unit_masks \
22 mips/25K/events mips/25K/unit_masks \
23Index: oprofile/events/arm/armv6/events 10Index: oprofile/events/arm/armv6/events
24=================================================================== 11===================================================================
25--- /dev/null 1970-01-01 00:00:00.000000000 +0000 12--- oprofile.orig/events/arm/armv6/events 2007-05-23 15:02:33.000000000 +0100
26+++ oprofile/events/arm/armv6/events 2007-05-23 14:13:12.000000000 +0100 13+++ oprofile/events/arm/armv6/events 2007-05-24 00:33:41.000000000 +0100
27@@ -0,0 +1,25 @@ 14@@ -1,4 +1,4 @@
15-# ARM11 events
28+# ARM V6 events 16+# ARM V6 events
29+# 17 #
30+event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses 18 event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
31+event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled 19 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
32+event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency 20@@ -17,5 +17,8 @@ event:0x0f counters:1,2 um:zero minimum:
33+event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses 21 event:0x10 counters:1,2 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
34+event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses 22 event:0x11 counters:1,2 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
35+event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change 23 event:0x12 counters:1,2 um:zero minimum:500 name:WRITE_DRAIN : Times write buffer was drained
36+event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted 24-event:0xff counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
37+event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instruction executed 25-#
38+event:0x08 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache
39+event:0x09 counters:1,1 um:zero minimum:500 name:DCACHE_FULL_STALL_CNT : number of stalls due to dcache full condition
40+event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access
41+event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss
42+event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
43+event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
44+event:0x0f counters:1,2 um:zero minimum:500 name:TLB_MISS : Main TLB miss
45+event:0x10 counters:1,2 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
46+event:0x11 counters:1,2 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
47+event:0x12 counters:1,2 um:zero minimum:500 name:WRITE_DRAIN : Time swrite buffer was drained
48+event:0x20 counters:1,2 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted 26+event:0x20 counters:1,2 um:zero minimum:500 name:ETMEXTOUT0 : nuber of cycles ETMEXTOUT[0] signal was asserted
49+event:0x21 counters:1,2 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted 27+event:0x21 counters:1,2 um:zero minimum:500 name:ETMEXTOUT1 : nuber of cycles ETMEXTOUT[1] signal was asserted
50+event:0x22 counters:1,2 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2 28+event:0x22 counters:1,2 um:zero minimum:500 name:ETMEXTOUT_BOTH : nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2
@@ -52,67 +30,73 @@ Index: oprofile/events/arm/armv6/events
52+event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter 30+event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
53Index: oprofile/events/arm/armv6/unit_masks 31Index: oprofile/events/arm/armv6/unit_masks
54=================================================================== 32===================================================================
55--- /dev/null 1970-01-01 00:00:00.000000000 +0000 33--- oprofile.orig/events/arm/armv6/unit_masks 2007-05-23 15:02:33.000000000 +0100
56+++ oprofile/events/arm/armv6/unit_masks 2007-05-23 14:13:12.000000000 +0100 34+++ oprofile/events/arm/armv6/unit_masks 2007-05-23 15:28:24.000000000 +0100
57@@ -0,0 +1,4 @@ 35@@ -1,4 +1,4 @@
36-# Arm11 possible unit masks
58+# ARM V6 PMU possible unit masks 37+# ARM V6 PMU possible unit masks
59+# 38 #
60+name:zero type:mandatory default:0x00 39 name:zero type:mandatory default:0x00
61+ 0x00 No unit mask 40 0x00 No unit mask
62Index: oprofile/libop/op_cpu_type.c 41Index: oprofile/libop/op_cpu_type.c
63=================================================================== 42===================================================================
64--- oprofile.orig/libop/op_cpu_type.c 2007-05-23 11:32:35.000000000 +0100 43--- oprofile.orig/libop/op_cpu_type.c 2007-05-24 00:17:01.000000000 +0100
65+++ oprofile/libop/op_cpu_type.c 2007-05-23 14:13:12.000000000 +0100 44+++ oprofile/libop/op_cpu_type.c 2007-05-24 00:26:34.000000000 +0100
66@@ -69,6 +69,7 @@ static struct cpu_descr const cpu_descrs 45@@ -70,7 +70,7 @@ static struct cpu_descr const cpu_descrs
67 { "ppc64 Cell Broadband Engine", "ppc64/cell-be", CPU_PPC64_CELL, 8 },
68 { "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 }, 46 { "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 },
69 { "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 }, 47 { "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 },
70+ { "ARM/V6 PMU", "arm/armv6", CPU_ARM_V6, 3 }, 48 { "ARM MPCore", "arm/mpcore", CPU_ARM_MPCORE, 2 },
49- { "ARM11 PMU", "arm/armv6", CPU_ARM_ARM11, 3 },
50+ { "ARM V6 PMU", "arm/armv6", CPU_ARM_V6, 3 },
71 }; 51 };
72 52
73 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr); 53 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
74Index: oprofile/libop/op_cpu_type.h 54Index: oprofile/libop/op_cpu_type.h
75=================================================================== 55===================================================================
76--- oprofile.orig/libop/op_cpu_type.h 2007-05-23 11:32:35.000000000 +0100 56--- oprofile.orig/libop/op_cpu_type.h 2007-05-24 00:17:01.000000000 +0100
77+++ oprofile/libop/op_cpu_type.h 2007-05-23 14:13:12.000000000 +0100 57+++ oprofile/libop/op_cpu_type.h 2007-05-24 00:26:50.000000000 +0100
78@@ -67,6 +67,7 @@ typedef enum { 58@@ -68,7 +68,7 @@ typedef enum {
79 CPU_PPC64_CELL, /**< ppc64 Cell Broadband Engine*/
80 CPU_FAMILY10, /**< AMD family 10 */ 59 CPU_FAMILY10, /**< AMD family 10 */
81 CPU_PPC64_PA6T, /**< ppc64 PA6T */ 60 CPU_PPC64_PA6T, /**< ppc64 PA6T */
82+ CPU_ARM_V6, /**< ARM V6 PMU */ 61 CPU_ARM_MPCORE, /**< ARM MPCore */
62- CPU_ARM_ARM11, /**< ARM11 */
63+ CPU_ARM_V6, /**< ARM V6 */
83 MAX_CPU_TYPE 64 MAX_CPU_TYPE
84 } op_cpu; 65 } op_cpu;
85 66
86Index: oprofile/libop/op_events.c 67Index: oprofile/libop/op_events.c
87=================================================================== 68===================================================================
88--- oprofile.orig/libop/op_events.c 2007-05-23 11:32:35.000000000 +0100 69--- oprofile.orig/libop/op_events.c 2007-05-24 00:17:01.000000000 +0100
89+++ oprofile/libop/op_events.c 2007-05-23 14:13:12.000000000 +0100 70+++ oprofile/libop/op_events.c 2007-05-24 00:27:49.000000000 +0100
90@@ -785,6 +785,7 @@ void op_default_event(op_cpu cpu_type, s 71@@ -786,6 +786,7 @@ void op_default_event(op_cpu cpu_type, s
91 // we could possibly use the CCNT
92 case CPU_ARM_XSCALE1: 72 case CPU_ARM_XSCALE1:
93 case CPU_ARM_XSCALE2: 73 case CPU_ARM_XSCALE2:
74 case CPU_ARM_MPCORE:
94+ case CPU_ARM_V6: 75+ case CPU_ARM_V6:
95 descr->name = "CPU_CYCLES"; 76 descr->name = "CPU_CYCLES";
96 break; 77 break;
97 78
79@@ -842,10 +843,6 @@ void op_default_event(op_cpu cpu_type, s
80 descr->name = "CPU_CLK";
81 break;
82
83- case CPU_ARM_ARM11:
84- descr->name = "CPU_CYCLES";
85- break;
86-
87 // don't use default, if someone add a cpu he wants a compiler
88 // warning if he forgets to handle it here.
89 case CPU_TIMER_INT:
98Index: oprofile/utils/ophelp.c 90Index: oprofile/utils/ophelp.c
99=================================================================== 91===================================================================
100--- oprofile.orig/utils/ophelp.c 2007-05-23 11:32:45.000000000 +0100 92--- oprofile.orig/utils/ophelp.c 2007-05-24 00:17:12.000000000 +0100
101+++ oprofile/utils/ophelp.c 2007-05-23 14:16:33.000000000 +0100 93+++ oprofile/utils/ophelp.c 2007-05-24 00:26:08.000000000 +0100
102@@ -424,12 +424,15 @@ int main(int argc, char const * argv[]) 94@@ -429,7 +429,7 @@ int main(int argc, char const * argv[])
103 printf("See Intel XScale Core Developer's Manual\n" 95 "Page 3-70, performance counters\n");
104 "Chapter 8 Performance Monitoring\n");
105 break;
106+
107+ case CPU_ARM_V6:
108+ printf("See ARM11 Technical Reference Manual\n");
109 break; 96 break;
110 97
111 case CPU_PPC64_PA6T: 98- case CPU_ARM_ARM11:
112 printf("See PA6T Power Implementation Features Book IV\n" 99+ case CPU_ARM_V6:
113 "Chapter 7 Performance Counters\n"); 100 printf("See ARM11 Technical Reference Manual\n");
114- break; 101 break;
115+ break;
116 102
117 case CPU_PPC64_POWER4:
118 case CPU_PPC64_POWER5:
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-17 11:43:52 +0000