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authorRichard Purdie <rpurdie@linux.intel.com>2009-04-14 15:30:24 +0100
committerRichard Purdie <rpurdie@linux.intel.com>2009-04-14 15:30:24 +0100
commitd620ad6a40daf00196d32f0931800fd23357364f (patch)
tree44b2f5d43bfdf35ba3a15ba86aa67f0a8568992e /meta/packages
parent1b4c8ad27e271a085672fd143bc2dac4f39f2754 (diff)
downloadpoky-d620ad6a40daf00196d32f0931800fd23357364f.tar.gz
libdrm: 2.4.4 -> 2.4.7
Diffstat (limited to 'meta/packages')
-rw-r--r--meta/packages/drm/files/poulsbo.patch2516
-rw-r--r--meta/packages/drm/libdrm_2.4.7.bb (renamed from meta/packages/drm/libdrm_2.4.4.bb)5
2 files changed, 2 insertions, 2519 deletions
diff --git a/meta/packages/drm/files/poulsbo.patch b/meta/packages/drm/files/poulsbo.patch
deleted file mode 100644
index 91f8975f50..0000000000
--- a/meta/packages/drm/files/poulsbo.patch
+++ /dev/null
@@ -1,2516 +0,0 @@
1Index: libdrm-2.4.4/libdrm/xf86drm.c
2===================================================================
3--- libdrm-2.4.4.orig/libdrm/xf86drm.c 2009-01-10 01:08:29.000000000 +0000
4+++ libdrm-2.4.4/libdrm/xf86drm.c 2009-02-05 12:23:22.000000000 +0000
5@@ -2402,6 +2402,569 @@
6 return 0;
7 }
8
9+
10+/*
11+ * Valid flags are
12+ * DRM_FENCE_FLAG_EMIT
13+ * DRM_FENCE_FLAG_SHAREABLE
14+ * DRM_FENCE_MASK_DRIVER
15+ */
16+
17+int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
18+ drmFence *fence)
19+{
20+ drm_fence_arg_t arg;
21+
22+ memset(&arg, 0, sizeof(arg));
23+ arg.flags = flags;
24+ arg.type = type;
25+ arg.fence_class = fence_class;
26+
27+ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
28+ return -errno;
29+ fence->handle = arg.handle;
30+ fence->fence_class = arg.fence_class;
31+ fence->type = arg.type;
32+ fence->flags = arg.flags;
33+ fence->signaled = 0;
34+ return 0;
35+}
36+
37+/*
38+ * Valid flags are
39+ * DRM_FENCE_FLAG_SHAREABLE
40+ * DRM_FENCE_MASK_DRIVER
41+ */
42+
43+int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
44+{
45+ drm_fence_arg_t arg;
46+
47+ memset(&arg, 0, sizeof(arg));
48+ arg.flags = flags;
49+ arg.fence_class = fence_class;
50+
51+ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
52+ return -errno;
53+ fence->handle = arg.handle;
54+ fence->fence_class = arg.fence_class;
55+ fence->type = arg.type;
56+ fence->flags = arg.flags;
57+ fence->sequence = arg.sequence;
58+ fence->signaled = 0;
59+ return 0;
60+}
61+
62+int drmFenceReference(int fd, unsigned handle, drmFence *fence)
63+{
64+ drm_fence_arg_t arg;
65+
66+ memset(&arg, 0, sizeof(arg));
67+ arg.handle = handle;
68+
69+ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
70+ return -errno;
71+ fence->handle = arg.handle;
72+ fence->fence_class = arg.fence_class;
73+ fence->type = arg.type;
74+ fence->flags = arg.flags;
75+ fence->signaled = arg.signaled;
76+ return 0;
77+}
78+
79+int drmFenceUnreference(int fd, const drmFence *fence)
80+{
81+ drm_fence_arg_t arg;
82+
83+ memset(&arg, 0, sizeof(arg));
84+ arg.handle = fence->handle;
85+
86+ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
87+ return -errno;
88+ return 0;
89+}
90+
91+int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
92+{
93+ drm_fence_arg_t arg;
94+
95+ memset(&arg, 0, sizeof(arg));
96+ arg.handle = fence->handle;
97+ arg.type = flush_type;
98+
99+ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
100+ return -errno;
101+ fence->fence_class = arg.fence_class;
102+ fence->type = arg.type;
103+ fence->signaled = arg.signaled;
104+ return arg.error;
105+}
106+
107+int drmFenceUpdate(int fd, drmFence *fence)
108+{
109+ drm_fence_arg_t arg;
110+
111+ memset(&arg, 0, sizeof(arg));
112+ arg.handle = fence->handle;
113+
114+ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
115+ return -errno;
116+ fence->fence_class = arg.fence_class;
117+ fence->type = arg.type;
118+ fence->signaled = arg.signaled;
119+ return 0;
120+}
121+
122+int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
123+ int *signaled)
124+{
125+ if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
126+ ((fenceType & fence->signaled) != fenceType)) {
127+ int ret = drmFenceFlush(fd, fence, fenceType);
128+ if (ret)
129+ return ret;
130+ }
131+
132+ *signaled = ((fenceType & fence->signaled) == fenceType);
133+
134+ return 0;
135+}
136+
137+/*
138+ * Valid flags are
139+ * DRM_FENCE_FLAG_SHAREABLE
140+ * DRM_FENCE_MASK_DRIVER
141+ */
142+
143+
144+int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
145+{
146+ drm_fence_arg_t arg;
147+
148+ memset(&arg, 0, sizeof(arg));
149+ arg.fence_class = fence->fence_class;
150+ arg.flags = flags;
151+ arg.handle = fence->handle;
152+ arg.type = emit_type;
153+
154+ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
155+ return -errno;
156+ fence->fence_class = arg.fence_class;
157+ fence->type = arg.type;
158+ fence->signaled = arg.signaled;
159+ fence->sequence = arg.sequence;
160+ return 0;
161+}
162+
163+/*
164+ * Valid flags are
165+ * DRM_FENCE_FLAG_WAIT_LAZY
166+ * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
167+ */
168+
169+#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
170+
171+static unsigned long
172+drmTimeDiff(struct timeval *now, struct timeval *then)
173+{
174+ uint64_t val;
175+
176+ val = now->tv_sec - then->tv_sec;
177+ val *= 1000000LL;
178+ val += now->tv_usec;
179+ val -= then->tv_usec;
180+
181+ return (unsigned long) val;
182+}
183+
184+static int
185+drmIoctlTimeout(int fd, unsigned long request, void *argp)
186+{
187+ int haveThen = 0;
188+ struct timeval then, now;
189+ int ret;
190+
191+ do {
192+ ret = ioctl(fd, request, argp);
193+ if (ret != 0 && errno == EAGAIN) {
194+ if (!haveThen) {
195+ gettimeofday(&then, NULL);
196+ haveThen = 1;
197+ }
198+ gettimeofday(&now, NULL);
199+ }
200+ } while (ret != 0 && errno == EAGAIN &&
201+ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
202+
203+ if (ret != 0)
204+ return ((errno == EAGAIN) ? -EBUSY : -errno);
205+
206+ return 0;
207+}
208+
209+
210+
211+
212+int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
213+{
214+ drm_fence_arg_t arg;
215+ int ret;
216+
217+ if (flush_type == 0) {
218+ flush_type = fence->type;
219+ }
220+
221+ if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) {
222+ if ((flush_type & fence->signaled) == flush_type) {
223+ return 0;
224+ }
225+ }
226+
227+ memset(&arg, 0, sizeof(arg));
228+ arg.handle = fence->handle;
229+ arg.type = flush_type;
230+ arg.flags = flags;
231+
232+
233+ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
234+ if (ret)
235+ return ret;
236+
237+ fence->fence_class = arg.fence_class;
238+ fence->type = arg.type;
239+ fence->signaled = arg.signaled;
240+ return arg.error;
241+}
242+
243+static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
244+{
245+ buf->handle = rep->handle;
246+ buf->flags = rep->flags;
247+ buf->size = rep->size;
248+ buf->offset = rep->offset;
249+ buf->mapHandle = rep->arg_handle;
250+ buf->mask = rep->proposed_flags;
251+ buf->start = rep->buffer_start;
252+ buf->fenceFlags = rep->fence_flags;
253+ buf->replyFlags = rep->rep_flags;
254+ buf->pageAlignment = rep->page_alignment;
255+ buf->tileInfo = rep->tile_info;
256+ buf->hwTileStride = rep->hw_tile_stride;
257+ buf->desiredTileStride = rep->desired_tile_stride;
258+}
259+
260+
261+
262+int drmBOCreate(int fd, unsigned long size,
263+ unsigned pageAlignment, void *user_buffer,
264+ uint64_t mask,
265+ unsigned hint, drmBO *buf)
266+{
267+ struct drm_bo_create_arg arg;
268+ struct drm_bo_create_req *req = &arg.d.req;
269+ struct drm_bo_info_rep *rep = &arg.d.rep;
270+ int ret;
271+
272+ memset(buf, 0, sizeof(*buf));
273+ memset(&arg, 0, sizeof(arg));
274+ req->flags = mask;
275+ req->hint = hint;
276+ req->size = size;
277+ req->page_alignment = pageAlignment;
278+ req->buffer_start = (unsigned long) user_buffer;
279+
280+ buf->virtual = NULL;
281+
282+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
283+ if (ret)
284+ return ret;
285+
286+ drmBOCopyReply(rep, buf);
287+ buf->virtual = user_buffer;
288+ buf->mapCount = 0;
289+
290+ return 0;
291+}
292+
293+int drmBOReference(int fd, unsigned handle, drmBO *buf)
294+{
295+ struct drm_bo_reference_info_arg arg;
296+ struct drm_bo_handle_arg *req = &arg.d.req;
297+ struct drm_bo_info_rep *rep = &arg.d.rep;
298+
299+ memset(&arg, 0, sizeof(arg));
300+ req->handle = handle;
301+
302+ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
303+ return -errno;
304+
305+ drmBOCopyReply(rep, buf);
306+ buf->mapVirtual = NULL;
307+ buf->mapCount = 0;
308+ buf->virtual = NULL;
309+
310+ return 0;
311+}
312+
313+int drmBOUnreference(int fd, drmBO *buf)
314+{
315+ struct drm_bo_handle_arg arg;
316+
317+ if (buf->mapVirtual && buf->mapHandle) {
318+ (void) munmap(buf->mapVirtual, buf->start + buf->size);
319+ buf->mapVirtual = NULL;
320+ buf->virtual = NULL;
321+ }
322+
323+ memset(&arg, 0, sizeof(arg));
324+ arg.handle = buf->handle;
325+
326+ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
327+ return -errno;
328+
329+ buf->handle = 0;
330+ return 0;
331+}
332+
333+
334+/*
335+ * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
336+ * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
337+ * call return an -EBUSY if it can' immediately honor the mapping request.
338+ */
339+
340+int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
341+ void **address)
342+{
343+ struct drm_bo_map_wait_idle_arg arg;
344+ struct drm_bo_info_req *req = &arg.d.req;
345+ struct drm_bo_info_rep *rep = &arg.d.rep;
346+ int ret = 0;
347+
348+ /*
349+ * Make sure we have a virtual address of the buffer.
350+ */
351+
352+ if (!buf->virtual) {
353+ drmAddress virtual;
354+ virtual = mmap(0, buf->size + buf->start,
355+ PROT_READ | PROT_WRITE, MAP_SHARED,
356+ fd, buf->mapHandle);
357+ if (virtual == MAP_FAILED) {
358+ ret = -errno;
359+ }
360+ if (ret)
361+ return ret;
362+ buf->mapVirtual = virtual;
363+ buf->virtual = ((char *) virtual) + buf->start;
364+ }
365+
366+ memset(&arg, 0, sizeof(arg));
367+ req->handle = buf->handle;
368+ req->mask = mapFlags;
369+ req->hint = mapHint;
370+
371+ /*
372+ * May hang if the buffer object is busy.
373+ * This IOCTL synchronizes the buffer.
374+ */
375+
376+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
377+ if (ret)
378+ return ret;
379+
380+ drmBOCopyReply(rep, buf);
381+ buf->mapFlags = mapFlags;
382+ ++buf->mapCount;
383+ *address = buf->virtual;
384+
385+ return 0;
386+}
387+
388+
389+int drmBOUnmap(int fd, drmBO *buf)
390+{
391+ struct drm_bo_handle_arg arg;
392+
393+ memset(&arg, 0, sizeof(arg));
394+ arg.handle = buf->handle;
395+
396+ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
397+ return -errno;
398+ }
399+ buf->mapCount--;
400+ return 0;
401+}
402+
403+int drmBOSetStatus(int fd, drmBO *buf,
404+ uint64_t flags, uint64_t mask,
405+ unsigned int hint,
406+ unsigned int desired_tile_stride,
407+ unsigned int tile_info)
408+{
409+
410+ struct drm_bo_map_wait_idle_arg arg;
411+ struct drm_bo_info_req *req = &arg.d.req;
412+ struct drm_bo_info_rep *rep = &arg.d.rep;
413+ int ret = 0;
414+
415+ memset(&arg, 0, sizeof(arg));
416+ req->mask = mask;
417+ req->flags = flags;
418+ req->handle = buf->handle;
419+ req->hint = hint;
420+ req->desired_tile_stride = desired_tile_stride;
421+ req->tile_info = tile_info;
422+
423+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
424+ if (ret)
425+ return ret;
426+
427+ drmBOCopyReply(rep, buf);
428+ return 0;
429+}
430+
431+
432+int drmBOInfo(int fd, drmBO *buf)
433+{
434+ struct drm_bo_reference_info_arg arg;
435+ struct drm_bo_handle_arg *req = &arg.d.req;
436+ struct drm_bo_info_rep *rep = &arg.d.rep;
437+ int ret = 0;
438+
439+ memset(&arg, 0, sizeof(arg));
440+ req->handle = buf->handle;
441+
442+ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
443+ if (ret)
444+ return -errno;
445+
446+ drmBOCopyReply(rep, buf);
447+ return 0;
448+}
449+
450+int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
451+{
452+ struct drm_bo_map_wait_idle_arg arg;
453+ struct drm_bo_info_req *req = &arg.d.req;
454+ struct drm_bo_info_rep *rep = &arg.d.rep;
455+ int ret = 0;
456+
457+ if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
458+ (buf->replyFlags & DRM_BO_REP_BUSY)) {
459+ memset(&arg, 0, sizeof(arg));
460+ req->handle = buf->handle;
461+ req->hint = hint;
462+
463+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
464+ if (ret)
465+ return ret;
466+
467+ drmBOCopyReply(rep, buf);
468+ }
469+ return 0;
470+}
471+
472+int drmBOBusy(int fd, drmBO *buf, int *busy)
473+{
474+ if (!(buf->flags & DRM_BO_FLAG_SHAREABLE) &&
475+ !(buf->replyFlags & DRM_BO_REP_BUSY)) {
476+ *busy = 0;
477+ return 0;
478+ }
479+ else {
480+ int ret = drmBOInfo(fd, buf);
481+ if (ret)
482+ return ret;
483+ *busy = (buf->replyFlags & DRM_BO_REP_BUSY);
484+ return 0;
485+ }
486+}
487+
488+int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
489+ unsigned memType)
490+{
491+ struct drm_mm_init_arg arg;
492+
493+ memset(&arg, 0, sizeof(arg));
494+
495+ arg.magic = DRM_BO_INIT_MAGIC;
496+ arg.major = DRM_BO_INIT_MAJOR;
497+ arg.minor = DRM_BO_INIT_MINOR;
498+ arg.p_offset = pOffset;
499+ arg.p_size = pSize;
500+ arg.mem_type = memType;
501+
502+ if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
503+ return -errno;
504+ return 0;
505+}
506+
507+int drmMMTakedown(int fd, unsigned memType)
508+{
509+ struct drm_mm_type_arg arg;
510+
511+ memset(&arg, 0, sizeof(arg));
512+ arg.mem_type = memType;
513+
514+ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
515+ return -errno;
516+ return 0;
517+}
518+
519+/*
520+ * If this function returns an error, and lockBM was set to 1,
521+ * the buffer manager is NOT locked.
522+ */
523+
524+int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
525+{
526+ struct drm_mm_type_arg arg;
527+
528+ memset(&arg, 0, sizeof(arg));
529+ arg.mem_type = memType;
530+ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
531+ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
532+
533+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
534+}
535+
536+int drmMMUnlock(int fd, unsigned memType, int unlockBM)
537+{
538+ struct drm_mm_type_arg arg;
539+
540+ memset(&arg, 0, sizeof(arg));
541+
542+ arg.mem_type = memType;
543+ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
544+
545+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
546+}
547+
548+int drmBOVersion(int fd, unsigned int *major,
549+ unsigned int *minor,
550+ unsigned int *patchlevel)
551+{
552+ struct drm_bo_version_arg arg;
553+ int ret;
554+
555+ memset(&arg, 0, sizeof(arg));
556+ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
557+ if (ret)
558+ return -errno;
559+
560+ if (major)
561+ *major = arg.major;
562+ if (minor)
563+ *minor = arg.minor;
564+ if (patchlevel)
565+ *patchlevel = arg.patchlevel;
566+
567+ return 0;
568+}
569+
570+
571+
572 #define DRM_MAX_FDS 16
573 static struct {
574 char *BusID;
575Index: libdrm-2.4.4/libdrm/xf86drm.h
576===================================================================
577--- libdrm-2.4.4.orig/libdrm/xf86drm.h 2008-12-17 18:28:24.000000000 +0000
578+++ libdrm-2.4.4/libdrm/xf86drm.h 2009-02-04 16:39:55.000000000 +0000
579@@ -665,4 +665,6 @@
580 extern int drmSetMaster(int fd);
581 extern int drmDropMaster(int fd);
582
583+#include "xf86mm.h"
584+
585 #endif
586Index: libdrm-2.4.4/libdrm/xf86mm.h
587===================================================================
588--- /dev/null 1970-01-01 00:00:00.000000000 +0000
589+++ libdrm-2.4.4/libdrm/xf86mm.h 2009-02-04 16:39:55.000000000 +0000
590@@ -0,0 +1,140 @@
591+/**************************************************************************
592+ *
593+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA.
594+ * All Rights Reserved.
595+ *
596+ * Permission is hereby granted, free of charge, to any person obtaining a
597+ * copy of this software and associated documentation files (the
598+ * "Software"), to deal in the Software without restriction, including
599+ * without limitation the rights to use, copy, modify, merge, publish,
600+ * distribute, sub license, and/or sell copies of the Software, and to
601+ * permit persons to whom the Software is furnished to do so, subject to
602+ * the following conditions:
603+ *
604+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
605+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
606+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
607+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
608+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
609+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
610+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
611+ *
612+ * The above copyright notice and this permission notice (including the
613+ * next paragraph) shall be included in all copies or substantial portions
614+ * of the Software.
615+ *
616+ *
617+ **************************************************************************/
618+
619+#ifndef _XF86MM_H_
620+#define _XF86MM_H_
621+#include <stddef.h>
622+#include <stdint.h>
623+#include "drm.h"
624+
625+/*
626+ * Note on multithreaded applications using this interface.
627+ * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to
628+ * be protected using an external mutex.
629+ *
630+ * Note: Don't protect the following functions, as it may lead to deadlocks:
631+ * drmBOUnmap().
632+ * The kernel is synchronizing and refcounting buffer maps.
633+ * User space only needs to refcount object usage within the same application.
634+ */
635+
636+
637+/*
638+ * List macros heavily inspired by the Linux kernel
639+ * list handling. No list looping yet.
640+ */
641+
642+typedef struct _drmFence
643+{
644+ unsigned handle;
645+ int fence_class;
646+ unsigned type;
647+ unsigned flags;
648+ unsigned signaled;
649+ uint32_t sequence;
650+ unsigned pad[4]; /* for future expansion */
651+} drmFence;
652+
653+typedef struct _drmBO
654+{
655+ unsigned handle;
656+ uint64_t mapHandle;
657+ uint64_t flags;
658+ uint64_t mask;
659+ unsigned mapFlags;
660+ unsigned long size;
661+ unsigned long offset;
662+ unsigned long start;
663+ unsigned replyFlags;
664+ unsigned fenceFlags;
665+ unsigned pageAlignment;
666+ unsigned tileInfo;
667+ unsigned hwTileStride;
668+ unsigned desiredTileStride;
669+ void *virtual;
670+ void *mapVirtual;
671+ int mapCount;
672+ unsigned pad[8]; /* for future expansion */
673+} drmBO;
674+
675+/*
676+ * Fence functions.
677+ */
678+
679+extern int drmFenceCreate(int fd, unsigned flags, int fence_class,
680+ unsigned type, drmFence *fence);
681+extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
682+extern int drmFenceUnreference(int fd, const drmFence *fence);
683+extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
684+extern int drmFenceSignaled(int fd, drmFence *fence,
685+ unsigned fenceType, int *signaled);
686+extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
687+ unsigned flush_type);
688+extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
689+ unsigned emit_type);
690+extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence);
691+
692+
693+/*
694+ * Buffer object functions.
695+ */
696+
697+extern int drmBOCreate(int fd, unsigned long size,
698+ unsigned pageAlignment, void *user_buffer,
699+ uint64_t mask, unsigned hint, drmBO *buf);
700+extern int drmBOReference(int fd, unsigned handle, drmBO *buf);
701+extern int drmBOUnreference(int fd, drmBO *buf);
702+extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
703+ void **address);
704+extern int drmBOUnmap(int fd, drmBO *buf);
705+extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle);
706+extern int drmBOInfo(int fd, drmBO *buf);
707+extern int drmBOBusy(int fd, drmBO *buf, int *busy);
708+
709+extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint);
710+
711+/*
712+ * Initialization functions.
713+ */
714+
715+extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
716+ unsigned memType);
717+extern int drmMMTakedown(int fd, unsigned memType);
718+extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict);
719+extern int drmMMUnlock(int fd, unsigned memType, int unlockBM);
720+extern int drmBOSetStatus(int fd, drmBO *buf,
721+ uint64_t flags, uint64_t mask,
722+ unsigned int hint,
723+ unsigned int desired_tile_stride,
724+ unsigned int tile_info);
725+extern int drmBOVersion(int fd, unsigned int *major,
726+ unsigned int *minor,
727+ unsigned int *patchlevel);
728+
729+
730+#endif
731Index: libdrm-2.4.4/shared-core/drm.h
732===================================================================
733--- libdrm-2.4.4.orig/shared-core/drm.h 2008-12-17 18:28:24.000000000 +0000
734+++ libdrm-2.4.4/shared-core/drm.h 2009-02-05 12:20:53.000000000 +0000
735@@ -632,6 +632,8 @@
736 unsigned long handle; /**< Used for mapping / unmapping */
737 };
738
739+
740+
741 /**
742 * DRM_IOCTL_SET_VERSION ioctl argument type.
743 */
744@@ -1109,6 +1111,32 @@
745 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t)
746 #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xB0, struct drm_mode_fb_cmd)
747
748+#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
749+#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
750+#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
751+#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
752+
753+#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
754+#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
755+#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
756+#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
757+#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
758+#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
759+#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
760+#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
761+
762+#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
763+#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
764+#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
765+#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
766+#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
767+#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
768+#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
769+#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
770+#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
771+
772+#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
773+#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
774 /*@}*/
775
776 /**
777Index: libdrm-2.4.4/shared-core/Makefile.am
778===================================================================
779--- libdrm-2.4.4.orig/shared-core/Makefile.am 2008-12-17 18:28:24.000000000 +0000
780+++ libdrm-2.4.4/shared-core/Makefile.am 2009-02-04 16:39:55.000000000 +0000
781@@ -31,6 +31,8 @@
782 mach64_drm.h \
783 mga_drm.h \
784 nouveau_drm.h \
785+ psb_drm.h \
786+ psb_reg.h \
787 r128_drm.h \
788 radeon_drm.h \
789 savage_drm.h \
790Index: libdrm-2.4.4/shared-core/psb_drm.h
791===================================================================
792--- /dev/null 1970-01-01 00:00:00.000000000 +0000
793+++ libdrm-2.4.4/shared-core/psb_drm.h 2009-02-04 16:39:55.000000000 +0000
794@@ -0,0 +1,359 @@
795+/**************************************************************************
796+ * Copyright (c) 2007, Intel Corporation.
797+ * All Rights Reserved.
798+ *
799+ * This program is free software; you can redistribute it and/or modify it
800+ * under the terms and conditions of the GNU General Public License,
801+ * version 2, as published by the Free Software Foundation.
802+ *
803+ * This program is distributed in the hope it will be useful, but WITHOUT
804+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
805+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
806+ * more details.
807+ *
808+ * You should have received a copy of the GNU General Public License along with
809+ * this program; if not, write to the Free Software Foundation, Inc.,
810+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
811+ *
812+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
813+ * develop this driver.
814+ *
815+ **************************************************************************/
816+/*
817+ */
818+
819+#ifndef _PSB_DRM_H_
820+#define _PSB_DRM_H_
821+
822+#if defined(__linux__) && !defined(__KERNEL__)
823+#include<stdint.h>
824+#endif
825+
826+/*
827+ * Intel Poulsbo driver package version.
828+ *
829+ */
830+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
831+#define PSB_PACKAGE_VERSION "2.0.0.32L.0007"
832+
833+#define DRM_PSB_SAREA_MAJOR 0
834+#define DRM_PSB_SAREA_MINOR 1
835+#define PSB_FIXED_SHIFT 16
836+
837+/*
838+ * Public memory types.
839+ */
840+
841+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
842+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
843+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
844+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
845+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
846+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
847+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
848+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
849+#define PSB_MEM_RASTGEOM_START 0x30000000
850+
851+typedef int32_t psb_fixed;
852+typedef uint32_t psb_ufixed;
853+
854+static inline psb_fixed psb_int_to_fixed(int a)
855+{
856+ return a * (1 << PSB_FIXED_SHIFT);
857+}
858+
859+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
860+{
861+ return a << PSB_FIXED_SHIFT;
862+}
863+
864+/*Status of the command sent to the gfx device.*/
865+typedef enum {
866+ DRM_CMD_SUCCESS,
867+ DRM_CMD_FAILED,
868+ DRM_CMD_HANG
869+} drm_cmd_status_t;
870+
871+struct drm_psb_scanout {
872+ uint32_t buffer_id; /* DRM buffer object ID */
873+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
874+ uint32_t stride; /* Buffer stride in bytes */
875+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
876+ uint32_t width; /* Buffer width in pixels */
877+ uint32_t height; /* Buffer height in lines */
878+ psb_fixed transform[3][3]; /* Buffer composite transform */
879+ /* (scaling, rot, reflect) */
880+};
881+
882+#define DRM_PSB_SAREA_OWNERS 16
883+#define DRM_PSB_SAREA_OWNER_2D 0
884+#define DRM_PSB_SAREA_OWNER_3D 1
885+
886+#define DRM_PSB_SAREA_SCANOUTS 3
887+
888+struct drm_psb_sarea {
889+ /* Track changes of this data structure */
890+
891+ uint32_t major;
892+ uint32_t minor;
893+
894+ /* Last context to touch part of hw */
895+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
896+
897+ /* Definition of front- and rotated buffers */
898+ uint32_t num_scanouts;
899+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
900+
901+ int planeA_x;
902+ int planeA_y;
903+ int planeA_w;
904+ int planeA_h;
905+ int planeB_x;
906+ int planeB_y;
907+ int planeB_w;
908+ int planeB_h;
909+ uint32_t msvdx_state;
910+ uint32_t msvdx_context;
911+};
912+
913+#define PSB_RELOC_MAGIC 0x67676767
914+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
915+#define PSB_RELOC_SHIFT_SHIFT 0
916+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
917+#define PSB_RELOC_ALSHIFT_SHIFT 16
918+
919+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
920+ * buffer
921+ */
922+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
923+ * buffer, relative to 2D
924+ * base address
925+ */
926+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
927+ * relative to PDS base address
928+ */
929+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
930+ * buffer (for tiling)
931+ */
932+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
933+ * relative to base reg
934+ */
935+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
936+
937+struct drm_psb_reloc {
938+ uint32_t reloc_op;
939+ uint32_t where; /* offset in destination buffer */
940+ uint32_t buffer; /* Buffer reloc applies to */
941+ uint32_t mask; /* Destination format: */
942+ uint32_t shift; /* Destination format: */
943+ uint32_t pre_add; /* Destination format: */
944+ uint32_t background; /* Destination add */
945+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
946+ uint32_t arg0; /* Reloc-op dependant */
947+ uint32_t arg1;
948+};
949+
950+#define PSB_BO_FLAG_TA (1ULL << 48)
951+#define PSB_BO_FLAG_SCENE (1ULL << 49)
952+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
953+#define PSB_BO_FLAG_USSE (1ULL << 51)
954+
955+#define PSB_ENGINE_2D 0
956+#define PSB_ENGINE_VIDEO 1
957+#define PSB_ENGINE_RASTERIZER 2
958+#define PSB_ENGINE_TA 3
959+#define PSB_ENGINE_HPRAST 4
960+
961+/*
962+ * For this fence class we have a couple of
963+ * fence types.
964+ */
965+
966+#define _PSB_FENCE_EXE_SHIFT 0
967+#define _PSB_FENCE_TA_DONE_SHIFT 1
968+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
969+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
970+#define _PSB_FENCE_FEEDBACK_SHIFT 4
971+
972+#define _PSB_ENGINE_TA_FENCE_TYPES 5
973+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
974+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
975+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
976+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
977+
978+#define PSB_ENGINE_HPRAST 4
979+#define PSB_NUM_ENGINES 5
980+
981+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
982+#define PSB_TA_FLAG_LASTPASS (1 << 1)
983+
984+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
985+
986+struct drm_psb_scene {
987+ int handle_valid;
988+ uint32_t handle;
989+ uint32_t w;
990+ uint32_t h;
991+ uint32_t num_buffers;
992+};
993+
994+typedef struct drm_psb_cmdbuf_arg {
995+ uint64_t buffer_list; /* List of buffers to validate */
996+ uint64_t clip_rects; /* See i915 counterpart */
997+ uint64_t scene_arg;
998+ uint64_t fence_arg;
999+
1000+ uint32_t ta_flags;
1001+
1002+ uint32_t ta_handle; /* TA reg-value pairs */
1003+ uint32_t ta_offset;
1004+ uint32_t ta_size;
1005+
1006+ uint32_t oom_handle;
1007+ uint32_t oom_offset;
1008+ uint32_t oom_size;
1009+
1010+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
1011+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
1012+ uint32_t cmdbuf_size;
1013+
1014+ uint32_t reloc_handle; /* Reloc buffer object */
1015+ uint32_t reloc_offset;
1016+ uint32_t num_relocs;
1017+
1018+ int32_t damage; /* Damage front buffer with cliprects */
1019+ /* Not implemented yet */
1020+ uint32_t fence_flags;
1021+ uint32_t engine;
1022+
1023+ /*
1024+ * Feedback;
1025+ */
1026+
1027+ uint32_t feedback_ops;
1028+ uint32_t feedback_handle;
1029+ uint32_t feedback_offset;
1030+ uint32_t feedback_breakpoints;
1031+ uint32_t feedback_size;
1032+} drm_psb_cmdbuf_arg_t;
1033+
1034+struct drm_psb_xhw_init_arg {
1035+ uint32_t operation;
1036+ uint32_t buffer_handle;
1037+};
1038+
1039+/*
1040+ * Feedback components:
1041+ */
1042+
1043+/*
1044+ * Vistest component. The number of these in the feedback buffer
1045+ * equals the number of vistest breakpoints + 1.
1046+ * This is currently the only feedback component.
1047+ */
1048+
1049+struct drm_psb_vistest {
1050+ uint32_t vt[8];
1051+};
1052+
1053+#define PSB_HW_COOKIE_SIZE 16
1054+#define PSB_HW_FEEDBACK_SIZE 8
1055+#define PSB_HW_OOM_CMD_SIZE 6
1056+
1057+struct drm_psb_xhw_arg {
1058+ uint32_t op;
1059+ int ret;
1060+ uint32_t irq_op;
1061+ uint32_t issue_irq;
1062+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
1063+ union {
1064+ struct {
1065+ uint32_t w;
1066+ uint32_t h;
1067+ uint32_t size;
1068+ uint32_t clear_p_start;
1069+ uint32_t clear_num_pages;
1070+ } si;
1071+ struct {
1072+ uint32_t fire_flags;
1073+ uint32_t hw_context;
1074+ uint32_t offset;
1075+ uint32_t engine;
1076+ uint32_t flags;
1077+ uint32_t rca;
1078+ uint32_t num_oom_cmds;
1079+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
1080+ } sb;
1081+ struct {
1082+ uint32_t pages;
1083+ uint32_t size;
1084+ } bi;
1085+ struct {
1086+ uint32_t bca;
1087+ uint32_t rca;
1088+ uint32_t flags;
1089+ } oom;
1090+ struct {
1091+ uint32_t pt_offset;
1092+ uint32_t param_offset;
1093+ uint32_t flags;
1094+ } bl;
1095+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
1096+ } arg;
1097+};
1098+
1099+#define DRM_PSB_CMDBUF 0x00
1100+#define DRM_PSB_XHW_INIT 0x01
1101+#define DRM_PSB_XHW 0x02
1102+#define DRM_PSB_SCENE_UNREF 0x03
1103+/* Controlling the kernel modesetting buffers */
1104+#define DRM_PSB_KMS_OFF 0x04
1105+#define DRM_PSB_KMS_ON 0x05
1106+
1107+#define PSB_XHW_INIT 0x00
1108+#define PSB_XHW_TAKEDOWN 0x01
1109+
1110+#define PSB_XHW_FIRE_RASTER 0x00
1111+#define PSB_XHW_SCENE_INFO 0x01
1112+#define PSB_XHW_SCENE_BIND_FIRE 0x02
1113+#define PSB_XHW_TA_MEM_INFO 0x03
1114+#define PSB_XHW_RESET_DPM 0x04
1115+#define PSB_XHW_OOM 0x05
1116+#define PSB_XHW_TERMINATE 0x06
1117+#define PSB_XHW_VISTEST 0x07
1118+#define PSB_XHW_RESUME 0x08
1119+#define PSB_XHW_TA_MEM_LOAD 0x09
1120+
1121+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
1122+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
1123+#define PSB_SCENE_FLAG_SETUP (1 << 2)
1124+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
1125+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
1126+
1127+#define PSB_TA_MEM_FLAG_TA (1 << 0)
1128+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
1129+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
1130+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
1131+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
1132+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
1133+
1134+/*Raster fire will deallocate memory */
1135+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
1136+/*Isp reset needed due to change in ZLS format */
1137+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
1138+/*These are set by Xpsb. */
1139+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
1140+/*The task has had at least one OOM and Xpsb will
1141+ send back messages on each fire. */
1142+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
1143+
1144+#define PSB_SCENE_ENGINE_TA 0
1145+#define PSB_SCENE_ENGINE_RASTER 1
1146+#define PSB_SCENE_NUM_ENGINES 2
1147+
1148+struct drm_psb_dev_info_arg {
1149+ uint32_t num_use_attribute_registers;
1150+};
1151+#define DRM_PSB_DEVINFO 0x01
1152+
1153+#endif
1154Index: libdrm-2.4.4/shared-core/psb_drv.h
1155===================================================================
1156--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1157+++ libdrm-2.4.4/shared-core/psb_drv.h 2009-02-04 16:39:55.000000000 +0000
1158@@ -0,0 +1,786 @@
1159+/**************************************************************************
1160+ * Copyright (c) 2007, Intel Corporation.
1161+ * All Rights Reserved.
1162+ *
1163+ * This program is free software; you can redistribute it and/or modify it
1164+ * under the terms and conditions of the GNU General Public License,
1165+ * version 2, as published by the Free Software Foundation.
1166+ *
1167+ * This program is distributed in the hope it will be useful, but WITHOUT
1168+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1169+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1170+ * more details.
1171+ *
1172+ * You should have received a copy of the GNU General Public License along with
1173+ * this program; if not, write to the Free Software Foundation, Inc.,
1174+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1175+ *
1176+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
1177+ * develop this driver.
1178+ *
1179+ **************************************************************************/
1180+/*
1181+ */
1182+#ifndef _PSB_DRV_H_
1183+#define _PSB_DRV_H_
1184+
1185+#include "drmP.h"
1186+#include "psb_drm.h"
1187+#include "psb_reg.h"
1188+#include "psb_schedule.h"
1189+#include "intel_drv.h"
1190+
1191+enum {
1192+ CHIP_PSB_8108 = 0,
1193+ CHIP_PSB_8109 = 1
1194+};
1195+
1196+#define DRIVER_NAME "psb"
1197+#define DRIVER_DESC "drm driver for the Intel GMA500"
1198+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
1199+
1200+#define PSB_DRM_DRIVER_DATE "20080107"
1201+#define PSB_DRM_DRIVER_MAJOR 4
1202+#define PSB_DRM_DRIVER_MINOR 1
1203+#define PSB_DRM_DRIVER_PATCHLEVEL 0
1204+
1205+#define PSB_VDC_OFFSET 0x00000000
1206+#define PSB_VDC_SIZE 0x000080000
1207+#define PSB_SGX_SIZE 0x8000
1208+#define PSB_SGX_OFFSET 0x00040000
1209+#define PSB_MMIO_RESOURCE 0
1210+#define PSB_GATT_RESOURCE 2
1211+#define PSB_GTT_RESOURCE 3
1212+#define PSB_GMCH_CTRL 0x52
1213+#define PSB_BSM 0x5C
1214+#define _PSB_GMCH_ENABLED 0x4
1215+#define PSB_PGETBL_CTL 0x2020
1216+#define _PSB_PGETBL_ENABLED 0x00000001
1217+#define PSB_SGX_2D_SLAVE_PORT 0x4000
1218+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
1219+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
1220+#define PSB_NUM_VALIDATE_BUFFERS 640
1221+#define PSB_MEM_KERNEL_START 0x10000000
1222+#define PSB_MEM_PDS_START 0x20000000
1223+#define PSB_MEM_MMU_START 0x40000000
1224+
1225+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
1226+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
1227+
1228+/*
1229+ * Flags for external memory type field.
1230+ */
1231+
1232+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
1233+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
1234+
1235+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
1236+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
1237+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
1238+
1239+/*
1240+ * PTE's and PDE's
1241+ */
1242+
1243+#define PSB_PDE_MASK 0x003FFFFF
1244+#define PSB_PDE_SHIFT 22
1245+#define PSB_PTE_SHIFT 12
1246+
1247+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
1248+#define PSB_PTE_WO 0x0002 /* Write only */
1249+#define PSB_PTE_RO 0x0004 /* Read only */
1250+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
1251+
1252+/*
1253+ * VDC registers and bits
1254+ */
1255+#define PSB_HWSTAM 0x2098
1256+#define PSB_INSTPM 0x20C0
1257+#define PSB_INT_IDENTITY_R 0x20A4
1258+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
1259+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
1260+#define _PSB_IRQ_SGX_FLAG (1<<18)
1261+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
1262+#define PSB_INT_MASK_R 0x20A8
1263+#define PSB_INT_ENABLE_R 0x20A0
1264+#define PSB_PIPEASTAT 0x70024
1265+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
1266+#define _PSB_VBLANK_CLEAR (1 << 1)
1267+#define PSB_PIPEBSTAT 0x71024
1268+
1269+#define _PSB_MMU_ER_MASK 0x0001FF00
1270+#define _PSB_MMU_ER_HOST (1 << 16)
1271+#define GPIOA 0x5010
1272+#define GPIOB 0x5014
1273+#define GPIOC 0x5018
1274+#define GPIOD 0x501c
1275+#define GPIOE 0x5020
1276+#define GPIOF 0x5024
1277+#define GPIOG 0x5028
1278+#define GPIOH 0x502c
1279+#define GPIO_CLOCK_DIR_MASK (1 << 0)
1280+#define GPIO_CLOCK_DIR_IN (0 << 1)
1281+#define GPIO_CLOCK_DIR_OUT (1 << 1)
1282+#define GPIO_CLOCK_VAL_MASK (1 << 2)
1283+#define GPIO_CLOCK_VAL_OUT (1 << 3)
1284+#define GPIO_CLOCK_VAL_IN (1 << 4)
1285+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1286+#define GPIO_DATA_DIR_MASK (1 << 8)
1287+#define GPIO_DATA_DIR_IN (0 << 9)
1288+#define GPIO_DATA_DIR_OUT (1 << 9)
1289+#define GPIO_DATA_VAL_MASK (1 << 10)
1290+#define GPIO_DATA_VAL_OUT (1 << 11)
1291+#define GPIO_DATA_VAL_IN (1 << 12)
1292+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1293+
1294+#define VCLK_DIVISOR_VGA0 0x6000
1295+#define VCLK_DIVISOR_VGA1 0x6004
1296+#define VCLK_POST_DIV 0x6010
1297+
1298+#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
1299+#define I915_WRITE(_offs, _val) \
1300+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
1301+#define I915_READ(_offs) \
1302+ ioread32(dev_priv->vdc_reg + (_offs))
1303+
1304+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
1305+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
1306+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
1307+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
1308+#define PSB_COMM_USER_IRQ (1024 >> 2)
1309+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
1310+#define PSB_COMM_FW (2048 >> 2)
1311+
1312+#define PSB_UIRQ_VISTEST 1
1313+#define PSB_UIRQ_OOM_REPLY 2
1314+#define PSB_UIRQ_FIRE_TA_REPLY 3
1315+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
1316+
1317+#define PSB_2D_SIZE (256*1024*1024)
1318+#define PSB_MAX_RELOC_PAGES 1024
1319+
1320+#define PSB_LOW_REG_OFFS 0x0204
1321+#define PSB_HIGH_REG_OFFS 0x0600
1322+
1323+#define PSB_NUM_VBLANKS 2
1324+
1325+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
1326+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
1327+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
1328+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
1329+#define PSB_COMM_FW (2048 >> 2)
1330+
1331+#define PSB_2D_SIZE (256*1024*1024)
1332+#define PSB_MAX_RELOC_PAGES 1024
1333+
1334+#define PSB_LOW_REG_OFFS 0x0204
1335+#define PSB_HIGH_REG_OFFS 0x0600
1336+
1337+#define PSB_NUM_VBLANKS 2
1338+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
1339+
1340+/*
1341+ * User options.
1342+ */
1343+
1344+struct drm_psb_uopt {
1345+ int disable_clock_gating;
1346+};
1347+
1348+struct psb_gtt {
1349+ struct drm_device *dev;
1350+ int initialized;
1351+ uint32_t gatt_start;
1352+ uint32_t gtt_start;
1353+ uint32_t gtt_phys_start;
1354+ unsigned gtt_pages;
1355+ unsigned gatt_pages;
1356+ uint32_t stolen_base;
1357+ uint32_t pge_ctl;
1358+ u16 gmch_ctrl;
1359+ unsigned long stolen_size;
1360+ uint32_t *gtt_map;
1361+ struct rw_semaphore sem;
1362+};
1363+
1364+struct psb_use_base {
1365+ struct list_head head;
1366+ struct drm_fence_object *fence;
1367+ unsigned int reg;
1368+ unsigned long offset;
1369+ unsigned int dm;
1370+};
1371+
1372+struct psb_buflist_item {
1373+ struct drm_buffer_object *bo;
1374+ void __user *data;
1375+ struct drm_bo_info_rep rep;
1376+ int ret;
1377+};
1378+
1379+struct psb_msvdx_cmd_queue {
1380+ struct list_head head;
1381+ void *cmd;
1382+ unsigned long cmd_size;
1383+ uint32_t sequence;
1384+};
1385+
1386+struct drm_psb_private {
1387+ unsigned long chipset;
1388+
1389+ struct psb_xhw_buf resume_buf;
1390+ struct drm_psb_dev_info_arg dev_info;
1391+ struct drm_psb_uopt uopt;
1392+
1393+ struct psb_gtt *pg;
1394+
1395+ struct page *scratch_page;
1396+ struct page *comm_page;
1397+
1398+ volatile uint32_t *comm;
1399+ uint32_t comm_mmu_offset;
1400+ uint32_t mmu_2d_offset;
1401+ uint32_t sequence[PSB_NUM_ENGINES];
1402+ uint32_t last_sequence[PSB_NUM_ENGINES];
1403+ int idle[PSB_NUM_ENGINES];
1404+ uint32_t last_submitted_seq[PSB_NUM_ENGINES];
1405+ int engine_lockup_2d;
1406+
1407+ struct psb_mmu_driver *mmu;
1408+ struct psb_mmu_pd *pf_pd;
1409+
1410+ uint8_t *sgx_reg;
1411+ uint8_t *vdc_reg;
1412+ uint8_t *msvdx_reg;
1413+ /*MSVDX*/ int msvdx_needs_reset;
1414+ int has_msvdx;
1415+ uint32_t gatt_free_offset;
1416+
1417+ /*
1418+ * Fencing / irq.
1419+ */
1420+
1421+ uint32_t sgx_irq_mask;
1422+ uint32_t vdc_irq_mask;
1423+
1424+ spinlock_t irqmask_lock;
1425+ spinlock_t sequence_lock;
1426+ int fence0_irq_on;
1427+ int irq_enabled;
1428+ unsigned int irqen_count_2d;
1429+ wait_queue_head_t event_2d_queue;
1430+
1431+ uint32_t msvdx_current_sequence;
1432+ uint32_t msvdx_last_sequence;
1433+ int fence2_irq_on;
1434+ struct mutex mutex_2d;
1435+
1436+ /*
1437+ * MSVDX Rendec Memory
1438+ */
1439+ struct drm_buffer_object *ccb0;
1440+ uint32_t base_addr0;
1441+ struct drm_buffer_object *ccb1;
1442+ uint32_t base_addr1;
1443+
1444+ /*
1445+ * Memory managers
1446+ */
1447+
1448+ int have_vram;
1449+ int have_tt;
1450+ int have_mem_mmu;
1451+ int have_mem_aper;
1452+ int have_mem_kernel;
1453+ int have_mem_pds;
1454+ int have_mem_rastgeom;
1455+ struct mutex temp_mem;
1456+
1457+ /*
1458+ * Relocation buffer mapping.
1459+ */
1460+
1461+ spinlock_t reloc_lock;
1462+ unsigned int rel_mapped_pages;
1463+ wait_queue_head_t rel_mapped_queue;
1464+
1465+ /*
1466+ * SAREA
1467+ */
1468+ struct drm_psb_sarea *sarea_priv;
1469+
1470+ /*
1471+ * LVDS info
1472+ */
1473+ uint8_t blc_type;
1474+ uint8_t blc_pol;
1475+ uint8_t blc_freq;
1476+ uint8_t blc_minbrightness;
1477+ uint8_t blc_i2caddr;
1478+ uint8_t blc_brightnesscmd;
1479+ int backlight; /* restore backlight to this value */
1480+
1481+ struct intel_i2c_chan *i2c_bus;
1482+ u32 CoreClock;
1483+ u32 PWMControlRegFreq;
1484+
1485+ unsigned char * OpRegion;
1486+ unsigned int OpRegionSize;
1487+
1488+ int backlight_duty_cycle; /* restore backlight to this value */
1489+ bool panel_wants_dither;
1490+ struct drm_display_mode *panel_fixed_mode;
1491+
1492+ /*
1493+ * Register state
1494+ */
1495+ uint32_t saveDSPACNTR;
1496+ uint32_t saveDSPBCNTR;
1497+ uint32_t savePIPEACONF;
1498+ uint32_t savePIPEBCONF;
1499+ uint32_t savePIPEASRC;
1500+ uint32_t savePIPEBSRC;
1501+ uint32_t saveFPA0;
1502+ uint32_t saveFPA1;
1503+ uint32_t saveDPLL_A;
1504+ uint32_t saveDPLL_A_MD;
1505+ uint32_t saveHTOTAL_A;
1506+ uint32_t saveHBLANK_A;
1507+ uint32_t saveHSYNC_A;
1508+ uint32_t saveVTOTAL_A;
1509+ uint32_t saveVBLANK_A;
1510+ uint32_t saveVSYNC_A;
1511+ uint32_t saveDSPASTRIDE;
1512+ uint32_t saveDSPASIZE;
1513+ uint32_t saveDSPAPOS;
1514+ uint32_t saveDSPABASE;
1515+ uint32_t saveDSPASURF;
1516+ uint32_t saveFPB0;
1517+ uint32_t saveFPB1;
1518+ uint32_t saveDPLL_B;
1519+ uint32_t saveDPLL_B_MD;
1520+ uint32_t saveHTOTAL_B;
1521+ uint32_t saveHBLANK_B;
1522+ uint32_t saveHSYNC_B;
1523+ uint32_t saveVTOTAL_B;
1524+ uint32_t saveVBLANK_B;
1525+ uint32_t saveVSYNC_B;
1526+ uint32_t saveDSPBSTRIDE;
1527+ uint32_t saveDSPBSIZE;
1528+ uint32_t saveDSPBPOS;
1529+ uint32_t saveDSPBBASE;
1530+ uint32_t saveDSPBSURF;
1531+ uint32_t saveVCLK_DIVISOR_VGA0;
1532+ uint32_t saveVCLK_DIVISOR_VGA1;
1533+ uint32_t saveVCLK_POST_DIV;
1534+ uint32_t saveVGACNTRL;
1535+ uint32_t saveADPA;
1536+ uint32_t saveLVDS;
1537+ uint32_t saveDVOA;
1538+ uint32_t saveDVOB;
1539+ uint32_t saveDVOC;
1540+ uint32_t savePP_ON;
1541+ uint32_t savePP_OFF;
1542+ uint32_t savePP_CONTROL;
1543+ uint32_t savePP_CYCLE;
1544+ uint32_t savePFIT_CONTROL;
1545+ uint32_t savePaletteA[256];
1546+ uint32_t savePaletteB[256];
1547+ uint32_t saveBLC_PWM_CTL;
1548+
1549+ /*
1550+ * USE code base register management.
1551+ */
1552+
1553+ struct drm_reg_manager use_manager;
1554+
1555+ /*
1556+ * Xhw
1557+ */
1558+
1559+ uint32_t *xhw;
1560+ struct drm_buffer_object *xhw_bo;
1561+ struct drm_bo_kmap_obj xhw_kmap;
1562+ struct list_head xhw_in;
1563+ spinlock_t xhw_lock;
1564+ atomic_t xhw_client;
1565+ struct drm_file *xhw_file;
1566+ wait_queue_head_t xhw_queue;
1567+ wait_queue_head_t xhw_caller_queue;
1568+ struct mutex xhw_mutex;
1569+ struct psb_xhw_buf *xhw_cur_buf;
1570+ int xhw_submit_ok;
1571+ int xhw_on;
1572+
1573+ /*
1574+ * Scheduling.
1575+ */
1576+
1577+ struct mutex reset_mutex;
1578+ struct mutex cmdbuf_mutex;
1579+ struct psb_scheduler scheduler;
1580+ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS];
1581+ uint32_t ta_mem_pages;
1582+ struct psb_ta_mem *ta_mem;
1583+ int force_ta_mem_load;
1584+
1585+ /*
1586+ * Watchdog
1587+ */
1588+
1589+ spinlock_t watchdog_lock;
1590+ struct timer_list watchdog_timer;
1591+ struct work_struct watchdog_wq;
1592+ struct work_struct msvdx_watchdog_wq;
1593+ int timer_available;
1594+
1595+ /*
1596+ * msvdx command queue
1597+ */
1598+ spinlock_t msvdx_lock;
1599+ struct mutex msvdx_mutex;
1600+ struct list_head msvdx_queue;
1601+ int msvdx_busy;
1602+};
1603+
1604+struct psb_mmu_driver;
1605+
1606+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
1607+ int trap_pagefaults,
1608+ int invalid_type);
1609+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
1610+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
1611+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
1612+ uint32_t gtt_start, uint32_t gtt_pages);
1613+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
1614+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
1615+ int trap_pagefaults,
1616+ int invalid_type);
1617+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
1618+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
1619+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
1620+ unsigned long address,
1621+ uint32_t num_pages);
1622+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
1623+ uint32_t start_pfn,
1624+ unsigned long address,
1625+ uint32_t num_pages, int type);
1626+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
1627+ unsigned long *pfn);
1628+
1629+/*
1630+ * Enable / disable MMU for different requestors.
1631+ */
1632+
1633+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
1634+ uint32_t mask);
1635+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
1636+ uint32_t mask);
1637+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
1638+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
1639+ unsigned long address, uint32_t num_pages,
1640+ uint32_t desired_tile_stride,
1641+ uint32_t hw_tile_stride, int type);
1642+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
1643+ uint32_t num_pages,
1644+ uint32_t desired_tile_stride,
1645+ uint32_t hw_tile_stride);
1646+/*
1647+ * psb_sgx.c
1648+ */
1649+
1650+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
1651+ uint32_t sequence);
1652+extern void psb_init_2d(struct drm_psb_private *dev_priv);
1653+extern int drm_psb_idle(struct drm_device *dev);
1654+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
1655+ uint32_t src_offset,
1656+ uint32_t dst_offset, uint32_t pages,
1657+ int direction);
1658+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
1659+ struct drm_file *file_priv);
1660+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
1661+ unsigned int cmds);
1662+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
1663+ struct drm_buffer_object *cmd_buffer,
1664+ unsigned long cmd_offset,
1665+ unsigned long cmd_size, int engine,
1666+ uint32_t * copy_buffer);
1667+
1668+extern int psb_fence_for_errors(struct drm_file *priv,
1669+ struct drm_psb_cmdbuf_arg *arg,
1670+ struct drm_fence_arg *fence_arg,
1671+ struct drm_fence_object **fence_p);
1672+
1673+/*
1674+ * psb_irq.c
1675+ */
1676+
1677+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
1678+extern void psb_irq_preinstall(struct drm_device *dev);
1679+extern void psb_irq_postinstall(struct drm_device *dev);
1680+extern void psb_irq_uninstall(struct drm_device *dev);
1681+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
1682+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
1683+
1684+/*
1685+ * psb_fence.c
1686+ */
1687+
1688+extern void psb_poke_flush(struct drm_device *dev, uint32_t class);
1689+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class,
1690+ uint32_t flags, uint32_t * sequence,
1691+ uint32_t * native_type);
1692+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
1693+extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class,
1694+ uint32_t flags);
1695+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
1696+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
1697+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
1698+ uint32_t class);
1699+extern void psb_fence_error(struct drm_device *dev,
1700+ uint32_t class,
1701+ uint32_t sequence, uint32_t type, int error);
1702+
1703+/*MSVDX stuff*/
1704+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
1705+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
1706+
1707+/*
1708+ * psb_buffer.c
1709+ */
1710+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
1711+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
1712+ uint32_t * type);
1713+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
1714+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
1715+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
1716+ struct drm_mem_type_manager *man);
1717+extern int psb_move(struct drm_buffer_object *bo,
1718+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
1719+
1720+/*
1721+ * psb_gtt.c
1722+ */
1723+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
1724+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
1725+ unsigned offset_pages, unsigned num_pages,
1726+ unsigned desired_tile_stride,
1727+ unsigned hw_tile_stride, int type);
1728+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
1729+ unsigned num_pages,
1730+ unsigned desired_tile_stride,
1731+ unsigned hw_tile_stride);
1732+
1733+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
1734+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
1735+
1736+/*
1737+ * psb_fb.c
1738+ */
1739+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
1740+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
1741+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
1742+ struct drm_file *file_priv);
1743+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
1744+ struct drm_file *file_priv);
1745+
1746+/*
1747+ * psb_reset.c
1748+ */
1749+
1750+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
1751+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
1752+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
1753+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
1754+
1755+/*
1756+ * psb_regman.c
1757+ */
1758+
1759+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
1760+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
1761+ unsigned long dev_virtual,
1762+ unsigned long size,
1763+ unsigned int data_master,
1764+ uint32_t fence_class,
1765+ uint32_t fence_type,
1766+ int no_wait,
1767+ int ignore_signals,
1768+ int *r_reg, uint32_t * r_offset);
1769+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
1770+ unsigned int reg_start, unsigned int reg_num);
1771+
1772+/*
1773+ * psb_xhw.c
1774+ */
1775+
1776+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
1777+ struct drm_file *file_priv);
1778+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
1779+ struct drm_file *file_priv);
1780+extern int psb_xhw_init(struct drm_device *dev);
1781+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
1782+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
1783+ struct drm_file *file_priv, int closing);
1784+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
1785+ struct psb_xhw_buf *buf,
1786+ uint32_t fire_flags,
1787+ uint32_t hw_context,
1788+ uint32_t * cookie,
1789+ uint32_t * oom_cmds,
1790+ uint32_t num_oom_cmds,
1791+ uint32_t offset,
1792+ uint32_t engine, uint32_t flags);
1793+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
1794+ struct psb_xhw_buf *buf, uint32_t fire_flags);
1795+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
1796+ struct psb_xhw_buf *buf,
1797+ uint32_t w,
1798+ uint32_t h,
1799+ uint32_t * hw_cookie,
1800+ uint32_t * bo_size,
1801+ uint32_t * clear_p_start,
1802+ uint32_t * clear_num_pages);
1803+
1804+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
1805+ struct psb_xhw_buf *buf);
1806+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
1807+ struct psb_xhw_buf *buf,
1808+ uint32_t pages,
1809+ uint32_t * hw_cookie, uint32_t * size);
1810+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
1811+ struct psb_xhw_buf *buf, uint32_t * cookie);
1812+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
1813+ struct psb_xhw_buf *buf,
1814+ uint32_t * cookie,
1815+ uint32_t * bca,
1816+ uint32_t * rca, uint32_t * flags);
1817+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
1818+ struct psb_xhw_buf *buf);
1819+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
1820+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
1821+ struct psb_xhw_buf *buf);
1822+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
1823+ struct psb_xhw_buf *buf, uint32_t * cookie);
1824+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
1825+ struct psb_xhw_buf *buf,
1826+ uint32_t flags,
1827+ uint32_t param_offset,
1828+ uint32_t pt_offset,
1829+ uint32_t *hw_cookie);
1830+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
1831+ struct psb_xhw_buf *buf);
1832+
1833+/*
1834+ * Utilities
1835+ */
1836+
1837+#define PSB_ALIGN_TO(_val, _align) \
1838+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
1839+#define PSB_WVDC32(_val, _offs) \
1840+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
1841+#define PSB_RVDC32(_offs) \
1842+ ioread32(dev_priv->vdc_reg + (_offs))
1843+#define PSB_WSGX32(_val, _offs) \
1844+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
1845+#define PSB_RSGX32(_offs) \
1846+ ioread32(dev_priv->sgx_reg + (_offs))
1847+#define PSB_WMSVDX32(_val, _offs) \
1848+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1849+#define PSB_RMSVDX32(_offs) \
1850+ ioread32(dev_priv->msvdx_reg + (_offs))
1851+
1852+#define PSB_ALPL(_val, _base) \
1853+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
1854+#define PSB_ALPLM(_val, _base) \
1855+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
1856+
1857+static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b)
1858+{
1859+ s64 tmp;
1860+ s64 a64 = (s64) a;
1861+ s64 b64 = (s64) b;
1862+
1863+ tmp = a64 * b64;
1864+ return tmp / (1ULL << PSB_FIXED_SHIFT) +
1865+ ((tmp & 0x80000000ULL) ? 1 : 0);
1866+}
1867+
1868+static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b)
1869+{
1870+ u64 tmp;
1871+ u64 a64 = (u64) a;
1872+ u64 b64 = (u64) b;
1873+
1874+ tmp = a64 * b64;
1875+ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0);
1876+}
1877+
1878+static inline uint32_t psb_ufixed_to_float32(psb_ufixed a)
1879+{
1880+ uint32_t exp = 0x7f + 7;
1881+ uint32_t mantissa = (uint32_t) a;
1882+
1883+ if (a == 0)
1884+ return 0;
1885+ while ((mantissa & 0xff800000) == 0) {
1886+ exp -= 1;
1887+ mantissa <<= 1;
1888+ }
1889+ while ((mantissa & 0xff800000) > 0x00800000) {
1890+ exp += 1;
1891+ mantissa >>= 1;
1892+ }
1893+ return (mantissa & ~0xff800000) | (exp << 23);
1894+}
1895+
1896+static inline uint32_t psb_fixed_to_float32(psb_fixed a)
1897+{
1898+ if (a < 0)
1899+ return psb_ufixed_to_float32(-a) | 0x80000000;
1900+ else
1901+ return psb_ufixed_to_float32(a);
1902+}
1903+
1904+#define PSB_D_RENDER (1 << 16)
1905+
1906+#define PSB_D_GENERAL (1 << 0)
1907+#define PSB_D_INIT (1 << 1)
1908+#define PSB_D_IRQ (1 << 2)
1909+#define PSB_D_FW (1 << 3)
1910+#define PSB_D_PERF (1 << 4)
1911+#define PSB_D_TMP (1 << 5)
1912+
1913+extern int drm_psb_debug;
1914+extern int drm_psb_no_fb;
1915+extern int drm_psb_disable_vsync;
1916+
1917+#define PSB_DEBUG_FW(_fmt, _arg...) \
1918+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
1919+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
1920+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
1921+#define PSB_DEBUG_INIT(_fmt, _arg...) \
1922+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
1923+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
1924+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
1925+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
1926+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
1927+#define PSB_DEBUG_PERF(_fmt, _arg...) \
1928+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
1929+#define PSB_DEBUG_TMP(_fmt, _arg...) \
1930+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
1931+
1932+#if DRM_DEBUG_CODE
1933+#define PSB_DEBUG(_flag, _fmt, _arg...) \
1934+ do { \
1935+ if ((_flag) & drm_psb_debug) \
1936+ printk(KERN_DEBUG \
1937+ "[psb:0x%02x:%s] " _fmt , _flag, \
1938+ __FUNCTION__ , ##_arg); \
1939+ } while (0)
1940+#else
1941+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
1942+#endif
1943+
1944+#endif
1945Index: libdrm-2.4.4/shared-core/psb_reg.h
1946===================================================================
1947--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1948+++ libdrm-2.4.4/shared-core/psb_reg.h 2009-02-04 16:39:55.000000000 +0000
1949@@ -0,0 +1,555 @@
1950+/**************************************************************************
1951+ *
1952+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
1953+ * Copyright (c) 2007, Intel Corporation.
1954+ * All Rights Reserved.
1955+ *
1956+ * This program is free software; you can redistribute it and/or modify it
1957+ * under the terms and conditions of the GNU General Public License,
1958+ * version 2, as published by the Free Software Foundation.
1959+ *
1960+ * This program is distributed in the hope it will be useful, but WITHOUT
1961+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1962+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1963+ * more details.
1964+ *
1965+ * You should have received a copy of the GNU General Public License along with
1966+ * this program; if not, write to the Free Software Foundation, Inc.,
1967+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
1968+ *
1969+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
1970+ * develop this driver.
1971+ *
1972+ **************************************************************************/
1973+/*
1974+ */
1975+#ifndef _PSB_REG_H_
1976+#define _PSB_REG_H_
1977+
1978+#define PSB_CR_CLKGATECTL 0x0000
1979+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
1980+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
1981+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
1982+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
1983+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
1984+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
1985+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
1986+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
1987+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
1988+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
1989+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
1990+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
1991+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
1992+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
1993+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
1994+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
1995+
1996+#define PSB_CR_CORE_ID 0x0010
1997+#define _PSB_CC_ID_ID_SHIFT (16)
1998+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
1999+#define _PSB_CC_ID_CONFIG_SHIFT (0)
2000+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
2001+
2002+#define PSB_CR_CORE_REVISION 0x0014
2003+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
2004+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
2005+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
2006+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
2007+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
2008+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
2009+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
2010+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
2011+
2012+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
2013+
2014+#define PSB_CR_SOFT_RESET 0x0080
2015+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
2016+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
2017+#define _PSB_CS_RESET_USE_RESET (1 << 4)
2018+#define _PSB_CS_RESET_TA_RESET (1 << 3)
2019+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
2020+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
2021+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
2022+
2023+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
2024+
2025+#define PSB_CR_EVENT_STATUS 0x012C
2026+
2027+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
2028+
2029+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
2030+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
2031+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
2032+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
2033+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
2034+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
2035+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
2036+#define _PSB_CE_SW_EVENT (1 << 14)
2037+#define _PSB_CE_TA_FINISHED (1 << 13)
2038+#define _PSB_CE_TA_TERMINATE (1 << 12)
2039+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
2040+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
2041+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
2042+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
2043+
2044+
2045+#define PSB_USE_OFFSET_MASK 0x0007FFFF
2046+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
2047+#define PSB_CR_USE_CODE_BASE0 0x0A0C
2048+#define PSB_CR_USE_CODE_BASE1 0x0A10
2049+#define PSB_CR_USE_CODE_BASE2 0x0A14
2050+#define PSB_CR_USE_CODE_BASE3 0x0A18
2051+#define PSB_CR_USE_CODE_BASE4 0x0A1C
2052+#define PSB_CR_USE_CODE_BASE5 0x0A20
2053+#define PSB_CR_USE_CODE_BASE6 0x0A24
2054+#define PSB_CR_USE_CODE_BASE7 0x0A28
2055+#define PSB_CR_USE_CODE_BASE8 0x0A2C
2056+#define PSB_CR_USE_CODE_BASE9 0x0A30
2057+#define PSB_CR_USE_CODE_BASE10 0x0A34
2058+#define PSB_CR_USE_CODE_BASE11 0x0A38
2059+#define PSB_CR_USE_CODE_BASE12 0x0A3C
2060+#define PSB_CR_USE_CODE_BASE13 0x0A40
2061+#define PSB_CR_USE_CODE_BASE14 0x0A44
2062+#define PSB_CR_USE_CODE_BASE15 0x0A48
2063+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
2064+#define _PSB_CUC_BASE_DM_SHIFT (25)
2065+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
2066+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
2067+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
2068+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
2069+#define _PSB_CUC_DM_VERTEX (0)
2070+#define _PSB_CUC_DM_PIXEL (1)
2071+#define _PSB_CUC_DM_RESERVED (2)
2072+#define _PSB_CUC_DM_EDM (3)
2073+
2074+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
2075+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
2076+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
2077+
2078+#define PSB_CR_EVENT_KICKER 0x0AC4
2079+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
2080+
2081+#define PSB_CR_EVENT_KICK 0x0AC8
2082+#define _PSB_CE_KICK_NOW (1 << 0)
2083+
2084+
2085+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
2086+
2087+#define PSB_CR_BIF_CTRL 0x0C00
2088+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
2089+#define _PSB_CB_CTRL_INVALDC (1 << 3)
2090+#define _PSB_CB_CTRL_FLUSH (1 << 2)
2091+
2092+#define PSB_CR_BIF_INT_STAT 0x0C04
2093+
2094+#define PSB_CR_BIF_FAULT 0x0C08
2095+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
2096+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
2097+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
2098+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
2099+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
2100+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
2101+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
2102+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
2103+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
2104+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
2105+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
2106+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
2107+
2108+#define PSB_CR_BIF_BANK0 0x0C78
2109+
2110+#define PSB_CR_BIF_BANK1 0x0C7C
2111+
2112+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
2113+
2114+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
2115+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
2116+
2117+#define PSB_CR_2D_SOCIF 0x0E18
2118+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
2119+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
2120+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
2121+
2122+#define PSB_CR_2D_BLIT_STATUS 0x0E04
2123+#define _PSB_C2B_STATUS_BUSY (1 << 24)
2124+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
2125+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
2126+
2127+/*
2128+ * 2D defs.
2129+ */
2130+
2131+/*
2132+ * 2D Slave Port Data : Block Header's Object Type
2133+ */
2134+
2135+#define PSB_2D_CLIP_BH (0x00000000)
2136+#define PSB_2D_PAT_BH (0x10000000)
2137+#define PSB_2D_CTRL_BH (0x20000000)
2138+#define PSB_2D_SRC_OFF_BH (0x30000000)
2139+#define PSB_2D_MASK_OFF_BH (0x40000000)
2140+#define PSB_2D_RESERVED1_BH (0x50000000)
2141+#define PSB_2D_RESERVED2_BH (0x60000000)
2142+#define PSB_2D_FENCE_BH (0x70000000)
2143+#define PSB_2D_BLIT_BH (0x80000000)
2144+#define PSB_2D_SRC_SURF_BH (0x90000000)
2145+#define PSB_2D_DST_SURF_BH (0xA0000000)
2146+#define PSB_2D_PAT_SURF_BH (0xB0000000)
2147+#define PSB_2D_SRC_PAL_BH (0xC0000000)
2148+#define PSB_2D_PAT_PAL_BH (0xD0000000)
2149+#define PSB_2D_MASK_SURF_BH (0xE0000000)
2150+#define PSB_2D_FLUSH_BH (0xF0000000)
2151+
2152+/*
2153+ * Clip Definition block (PSB_2D_CLIP_BH)
2154+ */
2155+#define PSB_2D_CLIPCOUNT_MAX (1)
2156+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
2157+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
2158+#define PSB_2D_CLIPCOUNT_SHIFT (0)
2159+// clip rectangle min & max
2160+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
2161+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
2162+#define PSB_2D_CLIP_XMAX_SHIFT (12)
2163+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
2164+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
2165+#define PSB_2D_CLIP_XMIN_SHIFT (0)
2166+// clip rectangle offset
2167+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
2168+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
2169+#define PSB_2D_CLIP_YMAX_SHIFT (12)
2170+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
2171+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
2172+#define PSB_2D_CLIP_YMIN_SHIFT (0)
2173+
2174+/*
2175+ * Pattern Control (PSB_2D_PAT_BH)
2176+ */
2177+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
2178+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
2179+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
2180+#define PSB_2D_PAT_WIDTH_SHIFT (5)
2181+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
2182+#define PSB_2D_PAT_YSTART_SHIFT (10)
2183+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
2184+#define PSB_2D_PAT_XSTART_SHIFT (15)
2185+
2186+/*
2187+ * 2D Control block (PSB_2D_CTRL_BH)
2188+ */
2189+// Present Flags
2190+#define PSB_2D_SRCCK_CTRL (0x00000001)
2191+#define PSB_2D_DSTCK_CTRL (0x00000002)
2192+#define PSB_2D_ALPHA_CTRL (0x00000004)
2193+// Colour Key Colour (SRC/DST)
2194+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
2195+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
2196+#define PSB_2D_CK_COL_SHIFT (0)
2197+// Colour Key Mask (SRC/DST)
2198+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
2199+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
2200+#define PSB_2D_CK_MASK_SHIFT (0)
2201+// Alpha Control (Alpha/RGB)
2202+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
2203+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
2204+#define PSB_2D_GBLALPHA_SHIFT (12)
2205+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
2206+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
2207+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
2208+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
2209+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
2210+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
2211+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
2212+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
2213+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
2214+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
2215+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
2216+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
2217+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
2218+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
2219+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
2220+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
2221+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
2222+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
2223+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
2224+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
2225+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
2226+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
2227+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
2228+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
2229+
2230+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
2231+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
2232+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
2233+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
2234+
2235+/*
2236+ *Source Offset (PSB_2D_SRC_OFF_BH)
2237+ */
2238+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
2239+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
2240+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
2241+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
2242+
2243+/*
2244+ * Mask Offset (PSB_2D_MASK_OFF_BH)
2245+ */
2246+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
2247+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
2248+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
2249+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
2250+
2251+/*
2252+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
2253+ */
2254+
2255+/*
2256+ *Blit Rectangle (PSB_2D_BLIT_BH)
2257+ */
2258+
2259+#define PSB_2D_ROT_MASK (3<<25)
2260+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
2261+#define PSB_2D_ROT_NONE (0<<25)
2262+#define PSB_2D_ROT_90DEGS (1<<25)
2263+#define PSB_2D_ROT_180DEGS (2<<25)
2264+#define PSB_2D_ROT_270DEGS (3<<25)
2265+
2266+#define PSB_2D_COPYORDER_MASK (3<<23)
2267+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
2268+#define PSB_2D_COPYORDER_TL2BR (0<<23)
2269+#define PSB_2D_COPYORDER_BR2TL (1<<23)
2270+#define PSB_2D_COPYORDER_TR2BL (2<<23)
2271+#define PSB_2D_COPYORDER_BL2TR (3<<23)
2272+
2273+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
2274+#define PSB_2D_DSTCK_DISABLE (0x00000000)
2275+#define PSB_2D_DSTCK_PASS (0x00200000)
2276+#define PSB_2D_DSTCK_REJECT (0x00400000)
2277+
2278+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
2279+#define PSB_2D_SRCCK_DISABLE (0x00000000)
2280+#define PSB_2D_SRCCK_PASS (0x00080000)
2281+#define PSB_2D_SRCCK_REJECT (0x00100000)
2282+
2283+#define PSB_2D_CLIP_ENABLE (0x00040000)
2284+
2285+#define PSB_2D_ALPHA_ENABLE (0x00020000)
2286+
2287+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
2288+#define PSB_2D_PAT_MASK (0x00010000)
2289+#define PSB_2D_USE_PAT (0x00010000)
2290+#define PSB_2D_USE_FILL (0x00000000)
2291+/*
2292+ * Tungsten Graphics note on rop codes: If rop A and rop B are
2293+ * identical, the mask surface will not be read and need not be
2294+ * set up.
2295+ */
2296+
2297+#define PSB_2D_ROP3B_MASK (0x0000FF00)
2298+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
2299+#define PSB_2D_ROP3B_SHIFT (8)
2300+// rop code A
2301+#define PSB_2D_ROP3A_MASK (0x000000FF)
2302+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
2303+#define PSB_2D_ROP3A_SHIFT (0)
2304+
2305+#define PSB_2D_ROP4_MASK (0x0000FFFF)
2306+/*
2307+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
2308+ * Fill Colour RGBA8888
2309+ */
2310+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
2311+#define PSB_2D_FILLCOLOUR_SHIFT (0)
2312+/*
2313+ * DWORD1: (Always Present)
2314+ * X Start (Dest)
2315+ * Y Start (Dest)
2316+ */
2317+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
2318+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
2319+#define PSB_2D_DST_XSTART_SHIFT (12)
2320+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
2321+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
2322+#define PSB_2D_DST_YSTART_SHIFT (0)
2323+/*
2324+ * DWORD2: (Always Present)
2325+ * X Size (Dest)
2326+ * Y Size (Dest)
2327+ */
2328+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
2329+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
2330+#define PSB_2D_DST_XSIZE_SHIFT (12)
2331+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
2332+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
2333+#define PSB_2D_DST_YSIZE_SHIFT (0)
2334+
2335+/*
2336+ * Source Surface (PSB_2D_SRC_SURF_BH)
2337+ */
2338+/*
2339+ * WORD 0
2340+ */
2341+
2342+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
2343+#define PSB_2D_SRC_1_PAL (0x00000000)
2344+#define PSB_2D_SRC_2_PAL (0x00008000)
2345+#define PSB_2D_SRC_4_PAL (0x00010000)
2346+#define PSB_2D_SRC_8_PAL (0x00018000)
2347+#define PSB_2D_SRC_8_ALPHA (0x00020000)
2348+#define PSB_2D_SRC_4_ALPHA (0x00028000)
2349+#define PSB_2D_SRC_332RGB (0x00030000)
2350+#define PSB_2D_SRC_4444ARGB (0x00038000)
2351+#define PSB_2D_SRC_555RGB (0x00040000)
2352+#define PSB_2D_SRC_1555ARGB (0x00048000)
2353+#define PSB_2D_SRC_565RGB (0x00050000)
2354+#define PSB_2D_SRC_0888ARGB (0x00058000)
2355+#define PSB_2D_SRC_8888ARGB (0x00060000)
2356+#define PSB_2D_SRC_8888UYVY (0x00068000)
2357+#define PSB_2D_SRC_RESERVED (0x00070000)
2358+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
2359+
2360+
2361+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
2362+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
2363+#define PSB_2D_SRC_STRIDE_SHIFT (0)
2364+/*
2365+ * WORD 1 - Base Address
2366+ */
2367+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
2368+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
2369+#define PSB_2D_SRC_ADDR_SHIFT (2)
2370+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
2371+
2372+/*
2373+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
2374+ */
2375+/*
2376+ * WORD 0
2377+ */
2378+
2379+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
2380+#define PSB_2D_PAT_1_PAL (0x00000000)
2381+#define PSB_2D_PAT_2_PAL (0x00008000)
2382+#define PSB_2D_PAT_4_PAL (0x00010000)
2383+#define PSB_2D_PAT_8_PAL (0x00018000)
2384+#define PSB_2D_PAT_8_ALPHA (0x00020000)
2385+#define PSB_2D_PAT_4_ALPHA (0x00028000)
2386+#define PSB_2D_PAT_332RGB (0x00030000)
2387+#define PSB_2D_PAT_4444ARGB (0x00038000)
2388+#define PSB_2D_PAT_555RGB (0x00040000)
2389+#define PSB_2D_PAT_1555ARGB (0x00048000)
2390+#define PSB_2D_PAT_565RGB (0x00050000)
2391+#define PSB_2D_PAT_0888ARGB (0x00058000)
2392+#define PSB_2D_PAT_8888ARGB (0x00060000)
2393+
2394+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
2395+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
2396+#define PSB_2D_PAT_STRIDE_SHIFT (0)
2397+/*
2398+ * WORD 1 - Base Address
2399+ */
2400+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
2401+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
2402+#define PSB_2D_PAT_ADDR_SHIFT (2)
2403+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
2404+
2405+/*
2406+ * Destination Surface (PSB_2D_DST_SURF_BH)
2407+ */
2408+/*
2409+ * WORD 0
2410+ */
2411+
2412+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
2413+#define PSB_2D_DST_332RGB (0x00030000)
2414+#define PSB_2D_DST_4444ARGB (0x00038000)
2415+#define PSB_2D_DST_555RGB (0x00040000)
2416+#define PSB_2D_DST_1555ARGB (0x00048000)
2417+#define PSB_2D_DST_565RGB (0x00050000)
2418+#define PSB_2D_DST_0888ARGB (0x00058000)
2419+#define PSB_2D_DST_8888ARGB (0x00060000)
2420+#define PSB_2D_DST_8888AYUV (0x00070000)
2421+
2422+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
2423+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
2424+#define PSB_2D_DST_STRIDE_SHIFT (0)
2425+/*
2426+ * WORD 1 - Base Address
2427+ */
2428+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
2429+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
2430+#define PSB_2D_DST_ADDR_SHIFT (2)
2431+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
2432+
2433+/*
2434+ * Mask Surface (PSB_2D_MASK_SURF_BH)
2435+ */
2436+/*
2437+ * WORD 0
2438+ */
2439+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
2440+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
2441+#define PSB_2D_MASK_STRIDE_SHIFT (0)
2442+/*
2443+ * WORD 1 - Base Address
2444+ */
2445+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
2446+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
2447+#define PSB_2D_MASK_ADDR_SHIFT (2)
2448+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
2449+
2450+/*
2451+ * Source Palette (PSB_2D_SRC_PAL_BH)
2452+ */
2453+
2454+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
2455+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
2456+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
2457+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
2458+
2459+/*
2460+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
2461+ */
2462+
2463+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
2464+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
2465+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
2466+#define PSB_2D_PATPAL_BYTEALIGN (1024)
2467+
2468+/*
2469+ * Rop3 Codes (2 LS bytes)
2470+ */
2471+
2472+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
2473+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
2474+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
2475+#define PSB_2D_ROP3_BLACKNESS (0x0000)
2476+#define PSB_2D_ROP3_SRC (0xCC)
2477+#define PSB_2D_ROP3_PAT (0xF0)
2478+#define PSB_2D_ROP3_DST (0xAA)
2479+
2480+
2481+/*
2482+ * Sizes.
2483+ */
2484+
2485+#define PSB_SCENE_HW_COOKIE_SIZE 16
2486+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
2487+
2488+/*
2489+ * Scene stuff.
2490+ */
2491+
2492+#define PSB_NUM_HW_SCENES 2
2493+
2494+/*
2495+ * Scheduler completion actions.
2496+ */
2497+
2498+#define PSB_RASTER_BLOCK 0
2499+#define PSB_RASTER 1
2500+#define PSB_RETURN 2
2501+#define PSB_TA 3
2502+
2503+
2504+#endif
2505Index: libdrm-2.4.4/libdrm/Makefile.am
2506===================================================================
2507--- libdrm-2.4.4.orig/libdrm/Makefile.am 2009-02-04 16:42:01.000000000 +0000
2508+++ libdrm-2.4.4/libdrm/Makefile.am 2009-02-04 16:45:06.000000000 +0000
2509@@ -31,6 +31,6 @@
2510 libdrm_lists.h
2511
2512 libdrmincludedir = ${includedir}
2513-libdrminclude_HEADERS = xf86drm.h xf86drmMode.h
2514+libdrminclude_HEADERS = xf86drm.h xf86drmMode.h xf86mm.h libdrm_lists.h
2515
2516 EXTRA_DIST = ChangeLog TODO
diff --git a/meta/packages/drm/libdrm_2.4.4.bb b/meta/packages/drm/libdrm_2.4.7.bb
index 8198592f8e..ee5643b420 100644
--- a/meta/packages/drm/libdrm_2.4.4.bb
+++ b/meta/packages/drm/libdrm_2.4.7.bb
@@ -1,8 +1,7 @@
1SECTION = "x11/base" 1SECTION = "x11/base"
2LICENSE = "MIT" 2LICENSE = "MIT"
3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2 \ 3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2"
4 file://poulsbo.patch;patch=1" 4PR = "r0"
5PR = "r3"
6PROVIDES = "drm" 5PROVIDES = "drm"
7DEPENDS = "libpthread-stubs" 6DEPENDS = "libpthread-stubs"
8 7
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 06:01:56 +0000