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authorRichard Purdie <richard@openedhand.com>2007-06-16 12:20:33 +0000
committerRichard Purdie <richard@openedhand.com>2007-06-16 12:20:33 +0000
commit1ee14413ed16ea65344c67d264cc1de4cde81a1a (patch)
tree635d7a0ae2e0b90c596a249e4432db9d45f80f17 /meta/packages/xorg-xserver/xserver-kdrive
parentac63e5a3413914d60ae58e6a60ef1ba66d078c3b (diff)
downloadpoky-1ee14413ed16ea65344c67d264cc1de4cde81a1a.tar.gz
xserver-kdrive: Drop unused patch
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@1957 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/xorg-xserver/xserver-kdrive')
-rw-r--r--meta/packages/xorg-xserver/xserver-kdrive/kdrive-imageon.patch8851
1 files changed, 0 insertions, 8851 deletions
diff --git a/meta/packages/xorg-xserver/xserver-kdrive/kdrive-imageon.patch b/meta/packages/xorg-xserver/xserver-kdrive/kdrive-imageon.patch
deleted file mode 100644
index f4272f80e0..0000000000
--- a/meta/packages/xorg-xserver/xserver-kdrive/kdrive-imageon.patch
+++ /dev/null
@@ -1,8851 +0,0 @@
1# Author: Manuel Teira <manuel.teira@telefonica.net> (sirfred in #oe)
2# Description: New driver for the Imageon ATI Card. Implementing:
3# -Hardware solid fills
4# -Hardware bitblt
5# -Hardware cursors
6# -XV Extension
7# -Internal and External Imageon offscreen memory support
8# -Hardware RandR rotation (without using a shadow framebuffer)
9# -Support for RandR mode changing
10
11#
12# Patch managed by http://www.holgerschurig.de/patcher.html
13#
14
15--- xorg-server-X11R7.1-1.1.0.work/configure.ac~kdrive-imageon
16+++ xorg-server-X11R7.1-1.1.0.work/configure.ac
17@@ -435,6 +435,7 @@
18 AC_ARG_ENABLE(kdrive, AS_HELP_STRING([--enable-kdrive], [Build kdrive servers (default: no)]), [KDRIVE=$enableval], [KDRIVE=no])
19 AC_ARG_ENABLE(xephyr, AS_HELP_STRING([--enable-xephyr], [Build the kdrive Xephyr server (default: auto)]), [XEPHYR=$enableval], [XEPHYR=auto])
20 AC_ARG_ENABLE(xsdl, AS_HELP_STRING([--enable-xsdl], [Build the kdrive Xsdl server (default: auto)]), [XSDL=$enableval], [XSDL=auto])
21+AC_ARG_ENABLE(imageon, AS_HELP_STRING([--enable-imageon], [Build the kdrive Ximageon server (default: no)]), [KDRIVEIMAGEON=$enableval], [KDRIVEIMAGEON=no])
22 dnl xprint
23 AC_ARG_ENABLE(freetype, AS_HELP_STRING([ --enable-freetype], [Build Xprint FreeType backend (default: yes)]), [XP_USE_FREETYPE=$enableval],[XP_USE_FREETYPE=no])
24 AC_ARG_WITH(freetype-config, AS_HELP_STRING([ --with-freetype-config=PROG], [Use FreeType configuration program PROG (default: auto)]), freetype_config=$withval, freetype_config=auto)
25@@ -1509,6 +1510,11 @@
26 AC_SUBST([XSDL_INCS])
27
28
29+AM_CONDITIONAL(KDRIVEIMAGEON, [test "x$KDRIVEIMAGEON" = xyes])
30+if test "x$KDRIVEIMAGEON" = xyes; then
31+ AC_DEFINE(KDRIVEIMAGEON, 1, [Build Ximageon server])
32+fi
33+
34 dnl these only go in xkb-config.h (which is shared by the Xorg and Xnest servers)
35 AC_DEFINE(__XKBDEFRULES__, "xorg", [Default XKB rules])
36 AC_DEFINE_DIR(XKB_BASE_DIRECTORY, XKBPATH, [Path to XKB data])
37@@ -1750,6 +1756,7 @@
38 hw/kdrive/epson/Makefile
39 hw/kdrive/fake/Makefile
40 hw/kdrive/fbdev/Makefile
41+hw/kdrive/imageon/Makefile
42 hw/kdrive/i810/Makefile
43 hw/kdrive/linux/Makefile
44 hw/kdrive/mach64/Makefile
45--- xorg-server-X11R7.1-1.1.0.work/hw/kdrive/Makefile.am~kdrive-imageon
46+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/Makefile.am
47@@ -1,18 +1,9 @@
48-if KDRIVEVESA
49-VESA_SUBDIRS = vesa ati chips epson i810 mach64 mga neomagic nvidia pm2 r128 \
50- smi via
51-endif
52-
53 if KDRIVEFBDEV
54 FBDEV_SUBDIRS = fbdev
55 endif
56
57-if XSDLSERVER
58-XSDL_SUBDIRS = sdl
59-endif
60-
61-if XEPHYR
62-XEPHYR_SUBDIRS = ephyr
63+if KDRIVEIMAGEON
64+IMAGEON_SUBDIRS = imageon
65 endif
66
67 SUBDIRS = \
68@@ -20,9 +11,9 @@
69 linux \
70 $(XSDL_SUBDIRS) \
71 $(FBDEV_SUBDIRS) \
72+ $(IMAGEON_SUBDIRS) \
73 $(VESA_SUBDIRS) \
74- $(XEPHYR_SUBDIRS) \
75- fake
76+ $(XEPHYR_SUBDIRS)
77
78 DIST_SUBDIRS = vesa ati chips epson i810 mach64 mga neomagic nvidia pm2 r128 \
79 smi via fbdev sdl ephyr src linux fake sis300
80--- /dev/null
81+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/Makefile.am
82@@ -0,0 +1,47 @@
83+if KDRIVEFBDEV
84+FBDEV_INCLUDES =-I$(top_srcdir)/hw/kdrive/fbdev
85+FBDEV_LIBS = $(top_builddir)/hw/kdrive/fbdev/libfbdev.a
86+endif
87+
88+INCLUDES = \
89+ @KDRIVE_INCS@ \
90+ $(FBDEV_INCLUDES) \
91+ @KDRIVE_CFLAGS@
92+
93+bin_PROGRAMS = Ximageon
94+
95+if TSLIB
96+TSLIB_FLAG = -lts
97+endif
98+
99+noinst_LIBRARIES = libimageon.a
100+
101+libimageon_a_SOURCES = \
102+ imageon.h \
103+ imageon_regs.h \
104+ imageon_const.h \
105+ imageon.c \
106+ imageon_cursor.c \
107+ imageon_draw.c \
108+ imageon_support.c \
109+ imageon_video.c
110+
111+
112+
113+Ximageon_SOURCES = \
114+ imageon_stub.c
115+
116+W100_LIBS = \
117+ libimageon.a \
118+ $(FBDEV_LIBS) \
119+ @KDRIVE_LIBS@
120+
121+Ximageon_LDADD = \
122+ $(W100_LIBS) \
123+ @XSERVER_LIBS@ \
124+ $(TSLIB_FLAG)
125+
126+
127+Ximageon_DEPENDENCIES = \
128+ libimageon.a \
129+ $(FBDEV_LIBS)
130--- /dev/null
131+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon.c
132@@ -0,0 +1,606 @@
133+/*
134+ * Copyright © 2007 Manuel Teira
135+ *
136+ * Permission to use, copy, modify, distribute, and sell this software and its
137+ * documentation for any purpose is hereby granted without fee, provided that
138+ * the above copyright notice appear in all copies and that both that
139+ * copyright notice and this permission notice appear in supporting
140+ * documentation, and that the name of Manuel Teira not be used in
141+ * advertising or publicity pertaining to distribution of the software without
142+ * specific, written prior permission. Manuel Teira makes no
143+ * representations about the suitability of this software for any purpose. It
144+ * is provided "as is" without express or implied warranty.
145+ *
146+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
147+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
148+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
149+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
150+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
151+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
152+ * PERFORMANCE OF THIS SOFTWARE.
153+ */
154+
155+#ifdef HAVE_CONFIG_H
156+#include <kdrive-config.h>
157+#endif
158+#include "imageon.h"
159+#include "imageon_regs.h"
160+#include "imageon_support.h"
161+
162+W100CardEntry w100_cards[] = {
163+ {0x1002, 0x5644, 0, "ATI Imageon 3200"},
164+ {0x1002, 0x5741, W100XVSupport, "ATI Imageon 100"},
165+ {0x1002, 0x5744, 0, "ATI Imageon 3220"},
166+ {0, 0, 0, NULL}
167+};
168+
169+W100ModeSpec w100_modes[] = {
170+ {800, 600, 16, W100_EXTMEM, FALSE},
171+ {640, 480, 16, W100_EXTMEM, FALSE},
172+ {320, 240, 16, W100_INTMEM, FALSE},
173+ { 0, 0, 0, 0, FALSE}
174+};
175+
176+W100StartupInfo w100StartupInfo;
177+
178+extern void (*tslib_transform_coords)(long *x, long *y, void *closure);
179+extern void *tslib_transform_closure;
180+
181+static void
182+W100Startup(W100CardInfo *w100c)
183+{
184+ int i;
185+ DBG_IMAGEON(("--W100Startup\n"));
186+ W100ModeSpec *modes;
187+ /* Take the current graphics mode */
188+ if (!W100GetFbMode(w100c, &w100StartupInfo.mode)) {
189+ ErrorF("(E) Unable to get current mode\n");
190+ }
191+ w100StartupInfo.randr = W100GetRotation(w100c);
192+ w100StartupInfo.portrait = w100StartupInfo.mode.width < w100StartupInfo.mode.height;
193+
194+ /* Test the valid modes */
195+ for (modes = w100_modes; modes->width; modes++) {
196+ modes->supported = W100CheckFbMode(w100c, modes);
197+ }
198+
199+ DBG_IMAGEON(("Startup Mode: %dx%d@%d, rot: %d, portrait: %s\n",
200+ w100StartupInfo.mode.width,
201+ w100StartupInfo.mode.height,
202+ w100StartupInfo.mode.bpp,
203+ w100StartupInfo.randr,
204+ w100StartupInfo.portrait ? "Yes" : "No"));
205+
206+ /* Tell the kernel to never switch off external memory */
207+ W100SysFsSet(w100c, W100_SYSFS_BASE "extmem", "1");
208+
209+ /* Disable framebuffer accel */
210+ W100SysFsSet(w100c, W100_SYSFS_BASE "accel", "0");
211+
212+ /* Enable fastsysclk */
213+ W100SysFsSet(w100c, W100_SYSFS_BASE "fastpllclk", "1");
214+
215+}
216+
217+
218+static Bool
219+W100Map(KdCardInfo * card, W100CardInfo *w100c)
220+{
221+ DBG_IMAGEON(("--W100Map\n"));
222+ w100c->mem_base = (CARD8 *) KdMapDevice(W100_MEM_BASE, W100_MEM_SIZE);
223+
224+ if (w100c->mem_base == NULL) {
225+ return FALSE;
226+ }
227+
228+ w100c->reg_base = w100c->mem_base + W100_REG_OFFSET;
229+
230+ /*
231+ * It doesn't matter mapping all the area as registers.
232+ * There's only difference when HAVE_ASM_MTRR_H is defined.
233+ * So, this call is doing nothing.
234+ */
235+ KdSetMappedMode(W100_MEM_BASE, W100_MEM_SIZE, KD_MAPPED_MODE_REGISTERS);
236+
237+ return TRUE;
238+}
239+
240+static void
241+W100Unmap(KdCardInfo * card, W100CardInfo *w100c)
242+{
243+ DBG_IMAGEON(("--W100Unmap\n"));
244+ if (w100c->mem_base) {
245+ KdResetMappedMode(W100_MEM_BASE, W100_MEM_SIZE,
246+ KD_MAPPED_MODE_REGISTERS);
247+ KdUnmapDevice((void *) w100c->mem_base, W100_MEM_SIZE);
248+ w100c->mem_base = w100c->reg_base = 0;
249+ }
250+}
251+
252+static void W100MemSetup(W100CardInfo *w100c)
253+{
254+ int reg_value;
255+ int int_start, int_size;
256+ int ext_start, ext_size;
257+ int i;
258+ DBG_IMAGEON(("--W100MemSetup\n"));
259+
260+ for (i = 0; i < w100c->num_memareas; i++) {
261+ xfree(w100c->memareas[i]);
262+ }
263+ xfree(w100c->memareas);
264+
265+ reg_value = MMIO_IN32(mmMC_FB_LOCATION);
266+ int_start = (reg_value & 0xffff) << 8;
267+ int_size = (((reg_value >> 16) & 0xffff) - (reg_value & 0xffff)) << 8;
268+ DBG_IMAGEON(("(I) MC_FB_LOCATION: 0x%08x. Start: 0x%08x, size: %d\n",
269+ reg_value, int_start, int_size));
270+
271+ reg_value = MMIO_IN32(mmMC_EXT_MEM_LOCATION);
272+ ext_start = (reg_value & 0xffff) << 8;
273+ ext_size = (((reg_value >> 16) & 0xffff) - (reg_value & 0xffff)) << 8;
274+ DBG_IMAGEON(("(I) MC_EXT_MEM_LOCATION: 0x%08x. Start: 0x%08x, size: %d\n",
275+ reg_value, ext_start, ext_size));
276+
277+ w100c->num_memareas = (ext_size > 0) ? 2 : 1;
278+ w100c->memareas = xcalloc(sizeof(W100MemArea *), w100c->num_memareas);
279+
280+ w100c->memareas[W100_INTMEM] = xcalloc(sizeof(W100MemArea), 1);
281+ w100c->memareas[W100_INTMEM]->priority = KD_VIDMEM_MAXPRIO;
282+ w100c->memareas[W100_INTMEM]->start = (CARD8 *) int_start;
283+ w100c->memareas[W100_INTMEM]->size = int_size;
284+
285+ if (w100c->num_memareas == 2) {
286+ w100c->memareas[W100_EXTMEM] = xcalloc(sizeof(W100MemArea), 1);
287+ w100c->memareas[W100_EXTMEM]->priority = KD_VIDMEM_MINPRIO;
288+ w100c->memareas[W100_EXTMEM]->start = (CARD8 *) ext_start;
289+ w100c->memareas[W100_EXTMEM]->size = ext_size;
290+ }
291+
292+ for (i = 0; i < w100c->num_memareas; i++) {
293+ DBG_IMAGEON(("(I) Memory mapped at 0x%08x(0x%08x), size %d bytes\n",
294+ W100_CARD2HOST(w100c->memareas[i]->start),
295+ w100c->memareas[i]->start,
296+ w100c->memareas[i]->size));
297+ }
298+
299+}
300+
301+static Bool
302+W100CardInit(KdCardInfo * card)
303+{
304+ W100CardInfo *w100c;
305+
306+ W100CardEntry *model = &w100_cards[0];
307+ static Bool initialized = FALSE;
308+
309+ DBG_IMAGEON(("--W100CardInit\n"));
310+
311+ w100c = xcalloc(sizeof(W100CardInfo), 1);
312+ if (w100c == NULL)
313+ return FALSE;
314+
315+ if (!fbdevInitialize(card, &w100c->fbdev)) {
316+ return FALSE;
317+ }
318+
319+ if (!W100Map(card, w100c)) {
320+ xfree(w100c);
321+ return FALSE;
322+ }
323+ card->driver = w100c;
324+
325+ while (model->name) {
326+ if (model->device == card->attr.deviceID) {
327+ w100c->card_id = model;
328+ break;
329+ }
330+ model++;
331+ }
332+
333+ ErrorF("(I) Using ATI card: %s\n", w100c->card_id->name);
334+
335+ if (!initialized) {
336+ initialized = TRUE;
337+ W100Startup(w100c);
338+ }
339+
340+ w100c->hw_window.mode = W100GetModeSpec(w100c, &w100StartupInfo.mode);
341+ w100c->hw_window.randr = w100StartupInfo.randr;
342+
343+ tslib_transform_closure = w100c;
344+ tslib_transform_coords = W100TransformTsLibCoordinates;
345+ return TRUE;
346+}
347+
348+
349+static void
350+W100CardFini(KdCardInfo * card)
351+{
352+ W100CardInfo *w100c = (W100CardInfo *) card->driver;
353+
354+ DBG_IMAGEON(("--W100CardFini\n"));
355+ W100Unmap(card, w100c);
356+ fbdevCardFini(card);
357+}
358+
359+static void
360+W100Setup(KdScreenInfo *screen)
361+{
362+ W100CardInfo(screen);
363+ W100MemArea *mem;
364+ KdMouseMatrix m;
365+ int fb_size, i;
366+
367+ DBG_IMAGEON(("--W100Setup\n"));
368+
369+ /* Adjust mode */
370+ w100c->hw_window.width = screen->width;
371+ w100c->hw_window.height = screen->height;
372+ w100c->hw_window.bpp = screen->fb[0].bitsPerPixel;
373+ W100SetupGraphicWindow(w100c);
374+
375+ /* Get some register values */
376+ w100c->regs.ENG_CNTL = MMIO_IN32(mmENG_CNTL);
377+ w100c->regs.VIDEO_CTRL = MMIO_IN32(mmVIDEO_CTRL);
378+ w100c->regs.GRAPHIC_H_DISP = MMIO_IN32(mmGRAPHIC_H_DISP);
379+ w100c->regs.GRAPHIC_V_DISP = MMIO_IN32(mmGRAPHIC_V_DISP);
380+ w100c->regs.DISP_DEBUG2 = MMIO_IN32(mmDISP_DEBUG2);
381+
382+ W100MemSetup(w100c);
383+
384+ /* Clear the VideoMemAreas set up by the framebuffer initialization */
385+ for (i = 0; i < screen->num_videomem_areas; i++) {
386+ xfree(screen->videomem_areas[i]);
387+ }
388+ xfree(screen->videomem_areas);
389+
390+ screen->videomem_areas = xcalloc(sizeof(KdVideoMemArea *),
391+ w100c->num_memareas);
392+ screen->num_videomem_areas = w100c->num_memareas;
393+
394+ screen->fb[0].byteStride = screen->width * screen->fb[0].bitsPerPixel / 8;
395+ fb_size = screen->fb[0].byteStride * screen->height;
396+
397+ DBG_IMAGEON(("(I) Framebuffer required size: %d bytes\n", fb_size));
398+
399+ for (i = 0; i < w100c->num_memareas; i++) {
400+ mem = w100c->memareas[i];
401+ screen->videomem_areas[i] = xcalloc(sizeof(KdVideoMemArea), 1);
402+ screen->videomem_areas[i]->priority = mem->priority;
403+ screen->videomem_areas[i]->base = W100_CARD2HOST(mem->start);
404+ screen->videomem_areas[i]->size = mem->size;
405+ if (w100c->hw_window.mode->fbpool == i) {
406+ DBG_IMAGEON(("(I) FrameBuffer in w100 memzone 0x%08x(0x%08x)\n",
407+ W100_CARD2HOST(mem->start), mem->start));
408+ screen->videomem_areas[i]->available_offset = fb_size;
409+ screen->fb[0].frameBuffer = W100_CARD2HOST(mem->start);
410+ } else {
411+ screen->videomem_areas[i]->available_offset = 0;
412+ }
413+ DBG_IMAGEON(("New videomem_area(priority:%d, start:0x%08x, size:%d, available_offset:%d\n",
414+ screen->videomem_areas[i]->priority,
415+ screen->videomem_areas[i]->base,
416+ screen->videomem_areas[i]->size,
417+ screen->videomem_areas[i]->available_offset));
418+ }
419+
420+
421+ w100c->hw_window.offset = W100_HOST2CARD(screen->fb[0].frameBuffer);
422+
423+ KdComputeMouseMatrix(&m, screen->randr,
424+ w100StartupInfo.portrait ?
425+ W100_MIN(screen->width, screen->height) :
426+ W100_MAX(screen->width, screen->height),
427+ w100StartupInfo.portrait ?
428+ W100_MAX(screen->width, screen->height) :
429+ W100_MIN(screen->width, screen->height));
430+
431+ KdSetMouseMatrix(&m);
432+
433+ DBG_IMAGEON(("Window(width:%d,height:%d,bpp:%d,offset:0x%08x"
434+ "(0x%08x), randr:%d)\n",
435+ w100c->hw_window.width,
436+ w100c->hw_window.height,
437+ w100c->hw_window.bpp,
438+ w100c->hw_window.offset,
439+ screen->fb[0].frameBuffer,
440+ w100c->hw_window.randr));
441+
442+}
443+
444+static Bool
445+W100ScreenInit(KdScreenInfo * screen)
446+{
447+ W100ScreenInfo *w100s;
448+ W100CardInfo(screen);
449+ Bool success = FALSE;
450+
451+ DBG_IMAGEON(("--W100ScreenInit\n"));
452+ w100s = xcalloc(sizeof(W100ScreenInfo), 1);
453+ if (w100s == NULL)
454+ return FALSE;
455+
456+ w100s->w100c = w100c;
457+ w100s->screen = screen;
458+ screen->driver = w100s;
459+
460+ success = fbdevScreenInitialize(screen, &w100s->fbdev);
461+
462+ if (!success) {
463+ screen->driver = NULL;
464+ xfree(w100s);
465+ return FALSE;
466+ }
467+
468+ W100Setup(screen);
469+
470+ return TRUE;
471+}
472+
473+static void
474+W100ScreenFini(KdScreenInfo * screen)
475+{
476+ W100ScreenInfo *w100s = (W100ScreenInfo *) screen->driver;
477+ DBG_IMAGEON(("--W100ScreenFini\n"));
478+ fbdevScreenFini(screen);
479+ xfree(w100s);
480+ screen->driver = 0;
481+}
482+
483+static Bool
484+W100InitScreen(ScreenPtr pScreen)
485+{
486+ KdScreenPriv(pScreen);
487+ W100CardInfo(pScreenPriv);
488+
489+ DBG_IMAGEON(("--W100InitScreen\n"));
490+ if (w100c->card_id->caps & W100XVSupport) {
491+ W100InitVideo(pScreen);
492+ }
493+ return fbdevInitScreen(pScreen);
494+}
495+
496+#ifdef RANDR
497+
498+static Bool W100RandRSetConfig(ScreenPtr pScreen,
499+ Rotation randr,
500+ int rate,
501+ RRScreenSizePtr pSize)
502+{
503+ KdScreenPriv(pScreen);
504+ KdScreenInfo *screen = pScreenPriv->screen;
505+ W100CardInfo(pScreenPriv);
506+ Bool screenEnabled = pScreenPriv->enabled;
507+
508+ DBG_IMAGEON(("--W100RandRSetConfig(randr:%d,pSize:%dx%d)\n",
509+ randr, pSize->width, pSize->height));
510+
511+ if (screenEnabled) {
512+ KdDisableScreen(pScreen);
513+ }
514+
515+ if (randr & (RR_Rotate_0|RR_Rotate_180)) {
516+ pScreen->mmWidth = screen->width_mm;
517+ pScreen->mmHeight = screen->height_mm;
518+ pScreen->width = pSize->width;
519+ pScreen->height = pSize->height;
520+ } else {
521+ pScreen->mmWidth = screen->height_mm;
522+ pScreen->mmHeight = screen->width_mm;
523+ pScreen->width = pSize->height;
524+ pScreen->height = pSize->width;
525+ }
526+
527+ screen->randr = randr;
528+ screen->width = pScreen->width;
529+ screen->height = pScreen->height;
530+ w100c->hw_window.randr = KdSubRotation(w100StartupInfo.randr, randr);
531+ w100c->hw_window.mode = W100GetBestMode(w100c, pScreen->width, pScreen->height);
532+
533+ KdOffscreenSwapOut(screen->pScreen);
534+
535+ W100Setup(screen);
536+
537+ DBG_IMAGEON(("ModifyPixMapHeader(width:%d,height:%d,depth:%d,bpp:%d,bs:%d,fb:0x%08x)\n", pScreen->width, pScreen->height,
538+ screen->fb[0].depth,
539+ screen->fb[0].bitsPerPixel,
540+ screen->fb[0].byteStride,
541+ screen->fb[0].frameBuffer));
542+
543+
544+ (*pScreen->ModifyPixmapHeader) (fbGetScreenPixmap(pScreen),
545+ pScreen->width,
546+ pScreen->height,
547+ screen->fb[0].depth,
548+ screen->fb[0].bitsPerPixel,
549+ screen->fb[0].byteStride,
550+ screen->fb[0].frameBuffer);
551+
552+
553+ if (screenEnabled) {
554+ KdEnableScreen(pScreen);
555+ }
556+ return TRUE;
557+}
558+
559+static Bool W100RandRGetInfo(ScreenPtr pScreen, Rotation *rotations)
560+{
561+ KdScreenPriv(pScreen);
562+ KdScreenInfo *screen = pScreenPriv->screen;
563+ W100CardInfo(pScreenPriv);
564+ RRScreenSizePtr pSize;
565+ Rotation randr;
566+ W100ModeSpec *modes;
567+ int i;
568+
569+ DBG_IMAGEON(("--W100RandRGetInfo\n"));
570+
571+ *rotations = RR_Rotate_All;
572+
573+ for (modes = w100_modes; modes->width; modes++) {
574+ if (modes->supported) {
575+ pSize = RRRegisterSize(pScreen,
576+ modes->width,
577+ modes->height,
578+ screen->width_mm,
579+ screen->height_mm);
580+ if (modes == w100c->hw_window.mode) {
581+ RRSetCurrentConfig(pScreen, screen->randr, 0, pSize);
582+ }
583+ }
584+ }
585+
586+ return TRUE;
587+}
588+
589+static Bool W100RandRInit(ScreenPtr pScreen)
590+{
591+ rrScrPrivPtr pScrPriv = rrGetScrPriv(pScreen);
592+ DBG_IMAGEON(("--W100RandRInit\n"));
593+ pScrPriv->rrSetConfig = W100RandRSetConfig;
594+ pScrPriv->rrGetInfo = W100RandRGetInfo;
595+ return TRUE;
596+}
597+
598+#endif
599+
600+static Bool
601+W100FinishInitScreen(ScreenPtr pScreen)
602+{
603+ KdScreenPriv(pScreen);
604+ W100CardInfo(pScreenPriv);
605+ DBG_IMAGEON(("--W100FinishInitScreen\n"));
606+ if (!fbdevFinishInitScreen(pScreen))
607+ return FALSE;
608+
609+#ifdef RANDR
610+ if (!W100RandRInit(pScreen))
611+ return FALSE;
612+#endif
613+ return TRUE;
614+}
615+
616+static Bool
617+W100CreateResources(ScreenPtr pScreen)
618+{
619+ KdScreenPriv(pScreen);
620+ W100CardInfo(pScreenPriv);
621+
622+ return fbdevCreateResources(pScreen);
623+}
624+
625+static void
626+W100Preserve(KdCardInfo * card)
627+{
628+ W100CardInfo *w100c = card->driver;
629+ DBG_IMAGEON(("--W100Preserve\n"));
630+
631+ fbdevPreserve(card);
632+}
633+
634+static void
635+W100Restore(KdCardInfo * card)
636+{
637+ W100CardInfo *w100c = card->driver;
638+ DBG_IMAGEON(("--W100Restore\n"));
639+ fbdevRestore(card);
640+}
641+
642+static Bool
643+W100DPMS(ScreenPtr pScreen, int mode)
644+{
645+ KdScreenPriv(pScreen);
646+ W100CardInfo(pScreenPriv);
647+ DBG_IMAGEON(("--W100DPMS\n"));
648+ return fbdevDPMS(pScreen, mode);
649+}
650+
651+static Bool
652+W100Enable(ScreenPtr pScreen)
653+{
654+ KdScreenPriv(pScreen);
655+ W100CardInfo(pScreenPriv);
656+
657+ DBG_IMAGEON(("--W100Enable\n"));
658+
659+ /*
660+ if (!fbdevEnable(pScreen))
661+ return FALSE;
662+ */
663+
664+ if (w100c->mem_base == NULL) {
665+ if (!W100Map(pScreenPriv->screen->card, w100c)) {
666+ return FALSE;
667+ }
668+ W100Setup(pScreenPriv->screen);
669+ }
670+ W100SetupGraphicEngine(w100c);
671+
672+ graphic_offset_u go;
673+ go.val = MMIO_IN32(mmGRAPHIC_OFFSET);
674+ DBG_IMAGEON(("Graphic offset is 0x%08x(0x%08x)\n",
675+ go.f.graphic_offset,
676+ W100_CARD2HOST(go.f.graphic_offset)));
677+
678+
679+ return TRUE;
680+}
681+
682+static void
683+W100Disable(ScreenPtr pScreen)
684+{
685+ KdScreenPriv(pScreen);
686+ W100CardInfo(pScreenPriv);
687+ DBG_IMAGEON(("--W100Disable\n"));
688+ //W100Unmap(pScreenPriv->card, w100c);
689+
690+ fbdevDisable(pScreen);
691+}
692+
693+static void
694+W100GetColors(ScreenPtr pScreen, int fb, int n, xColorItem * pdefs)
695+{
696+ KdScreenPriv(pScreen);
697+ W100CardInfo(pScreenPriv);
698+
699+ fbdevGetColors(pScreen, fb, n, pdefs);
700+}
701+
702+static void
703+W100PutColors(ScreenPtr pScreen, int fb, int n, xColorItem * pdefs)
704+{
705+ KdScreenPriv(pScreen);
706+ W100CardInfo(pScreenPriv);
707+
708+ fbdevPutColors(pScreen, fb, n, pdefs);
709+}
710+
711+KdCardFuncs W100Funcs = {
712+ W100CardInit, /* cardinit */
713+ W100ScreenInit, /* scrinit */
714+ W100InitScreen, /* initScreen */
715+ W100FinishInitScreen, /* finishInitScreen */
716+ W100CreateResources, /* createRes */
717+ W100Preserve, /* preserve */
718+ W100Enable, /* enable */
719+ W100DPMS, /* dpms */
720+ W100Disable, /* disable */
721+ W100Restore, /* restore */
722+ W100ScreenFini, /* scrfini */
723+ W100CardFini, /* cardfini */
724+
725+ W100CursorInit, /* initCursor */
726+ W100CursorEnable, /* enableCursor */
727+ W100CursorDisable, /* disableCursor */
728+ W100CursorFini, /* finiCursor */
729+ W100RecolorCursor, /* recolorCursor */
730+
731+ W100InitAccel, /* initAccel */
732+ W100EnableAccel, /* enableAccel */
733+ W100DisableAccel, /* disableAccel */
734+ W100FiniAccel, /* finiAccel */
735+
736+ W100GetColors, /* getColors */
737+ W100PutColors, /* putColors */
738+};
739--- /dev/null
740+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_const.h
741@@ -0,0 +1,161 @@
742+/*
743+ * Copyright © 2007 Manuel Teira
744+ *
745+ * Permission to use, copy, modify, distribute, and sell this software and its
746+ * documentation for any purpose is hereby granted without fee, provided that
747+ * the above copyright notice appear in all copies and that both that
748+ * copyright notice and this permission notice appear in supporting
749+ * documentation, and that the name of Manuel Teira not be used in
750+ * advertising or publicity pertaining to distribution of the software without
751+ * specific, written prior permission. Manuel Teira makes no
752+ * representations about the suitability of this software for any purpose. It
753+ * is provided "as is" without express or implied warranty.
754+ *
755+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
756+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
757+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
758+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
759+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
760+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
761+ * PERFORMANCE OF THIS SOFTWARE.
762+ */
763+
764+#ifndef __IMAGEON_CONST_H__
765+#define __IMAGEON_CONST_H__
766+
767+// DP_GUI_MASTER_CNTL.GMC_Brush_DataType
768+// DP_DATATYPE.Brush_DataType
769+#define DP_BRUSH_8x8MONOOPA 0 //8x8 mono pattern (expanded to frgd, bkgd)
770+#define DP_BRUSH_8x8MONOTRA 1 //8x8 mono pattern (expanded to frgd, leave_alone)
771+#define DP_PEN_32x1MONOOPA 6 //32x1 mono pattern (expanded to frgd, bkgd)
772+#define DP_PEN_32x1MONOTRA 7 //32x1 mono pattern (expanded to frgd, leave_alone)
773+#define DP_BRUSH_8x8COLOR 10 //8x8 color pattern
774+#define DP_BRUSH_SOLIDCOLOR 13 //solid color pattern (frgd)
775+#define DP_BRUSH_NONE 15 //no brush used
776+
777+#define SIZE_BRUSH_8x8MONO 2
778+#define SIZE_PEN_32x1MONO 1
779+#define SIZE_BRUSH_8x8COLOR_8 16
780+#define SIZE_BRUSH_8x8COLOR_16 32
781+#define MAX_BRUSH_SIZE SIZE_BRUSH_8x8COLOR_16
782+
783+// DP_GUI_MASTER_CNTL.GMC_Dst_DataType
784+// DP_DATATYPE.Dp_Dst_DataType
785+#define DP_DST_8BPP 2 // 8 bpp grey scale
786+#define DP_DST_16BPP_1555 3 //16 bpp aRGB 1555
787+#define DP_DST_16BPP_444 5 //16 bpp aRGB 4444
788+
789+// DP_GUI_MASTER_CNTL.GMC_Src_DataType
790+// DP_DATATYPE.Dp_Src_DataType
791+#define DP_SRC_1BPP_OPA 0 //mono (expanded to frgd, bkgd)
792+#define DP_SRC_1BPP_TRA 1 //mono (expanded to frgd, leave_alone)
793+#define DP_SRC_COLOR_SAME_AS_DST 3 //color (same as DST)
794+#define DP_SRC_SOLID_COLOR_BLT 4 //solid color for Blt (use frgd)
795+#define DP_SRC_4BPP 5 //4 bpp
796+#define DP_SRC_12BPP_PACKED 6 //12 bpp packed
797+
798+// DP_GUI_MASTER_CNTL.GMC_Byte_Pix_Order
799+// DP_DATATYPE.Dp_Byte_Pix_Order
800+#define DP_PIX_ORDER_MSB2LSB 0 //monochrome pixel order from MSBit to LSBit
801+#define DP_PIX_ORDER_LSB2MSB 1 //monochrome pixel order from LSBit to MSBit
802+
803+// DP_GUI_MASTER_CNTL.GMC_Dp_Src_Source
804+#define DP_SRC_MEM_LINEAR 1 //loaded from memory (linear trajectory)
805+#define DP_SRC_MEM_RECTANGULAR 2 //loaded from memory (rectangular trajectory)
806+#define DP_SRC_HOSTDATA_BIT 3 //loaded from hostdata (linear trajectory)
807+#define DP_SRC_HOSTDATA_BYTE 4 //loaded from hostdata (linear trajectory & byte-aligned)
808+
809+// DP_GUI_MASTER_CNTL.GMC_Dp_Op
810+#define DP_OP_ROP 0
811+#define DP_OP_ARITHMETIC 1
812+
813+// E2_ARITHMETIC_CNTL.opcode
814+#define E2_OPC_GLBALP_ADD_SRC2 0
815+#define E2_OPC_GLBALP_SUB_SRC2 1
816+#define E2_OPC_SRC1_ADD_SRC2 2
817+#define E2_OPC_SRC1_SUB_SRC2 3
818+#define E2_OPC_DST_SADDBLEND_SRC2 4
819+#define E2_OPC_DST_CADDBLEND_SRC2 5
820+#define E2_OPC_DST_CSUBBLEND_SRC2 6
821+#define E2_OPC_LF_SRC2 7
822+#define E2_OPC_SCALE_SRC2 8
823+#define E2_OPC_STRETCH_SRC2 9
824+#define E2_OPC_SRC1_4BPPCPYWEXP 10
825+#define E2_OPC_MC1 11
826+#define E2_OPC_MC2 12
827+#define E2_OPC_MC1_IDCT 13
828+#define E2_OPC_MC2_IDCT 14
829+#define E2_OPC_IDCT_ONLY_IFRAME 15
830+
831+// E2_ARITHMETIC_CNTL.clamp
832+#define E2_CLAMP_OFF 0
833+#define E2_CLAMP_ON 1
834+
835+// E2_ARITHMETIC_CNTL.rounding
836+#define E2_ROUNDING_TRUNCATE 0
837+#define E2_ROUNDING_TO_INFINITY 1
838+
839+// E2_ARITHMETIC_CNTL.srcblend
840+#define E2_SRCBLEND_GLOBALALPHA 0
841+#define E2_SRCBLEND_ZERO 1
842+#define E2_SRCBLEND_SRC2ALPHA 2
843+#define E2_SRCBLEND_DSTALPHA 3
844+#define E2_SRCBLEND_ALPHA1PLANE 4
845+
846+// E2_ARITHMETIC_CNTL.destblend
847+#define E2_DSTBLEND_GLOBALALPHA 0
848+#define E2_DSTBLEND_ZERO 1
849+#define E2_DSTBLEND_SRC2ALPHA 2
850+#define E2_DSTBLEND_DSTALPHA 3
851+#define E2_DSTBLEND_ALPHA1PLANE 4
852+
853+// LCD_FORMAT.lcd_type
854+#define LCDTYPE_TFT333 0
855+#define LCDTYPE_TFT444 1
856+#define LCDTYPE_TFT555 2
857+#define LCDTYPE_TFT666 3
858+#define LCDTYPE_COLSTNPACK4 4
859+#define LCDTYPE_COLSTNPACK8F1 5
860+#define LCDTYPE_COLSTNPACK8F2 6
861+#define LCDTYPE_COLSTNPACK16 7
862+#define LCDTYPE_MONSTNPACK4 8
863+#define LCDTYPE_MONSTNPACK8 9
864+
865+// CP_RB_CNTL.rb_bufsz
866+#define RB_SIZE_2K 8
867+#define RB_SIZE_4K 9
868+#define RB_SIZE_8K 10
869+#define RB_SIZE_16K 11
870+#define RB_SIZE_32K 12
871+#define RB_SIZE_64K 13
872+
873+// GRAPHIC_CTRL.color_depth
874+#define COLOR_DEPTH_1BPP 0
875+#define COLOR_DEPTH_2BPP 1
876+#define COLOR_DEPTH_4BPP 2
877+#define COLOR_DEPTH_8BPP 3
878+#define COLOR_DEPTH_332 4
879+#define COLOR_DEPTH_A444 5
880+#define COLOR_DEPTH_A555 6
881+
882+// VIDEO_CTRL.video_mode
883+#define VIDEO_MODE_422 0
884+#define VIDEO_MODE_420 1
885+
886+// CLR_CMP_CNTL.cmp_fcn_src
887+#define CMP_FCN_SRC_NEQ 4
888+#define CMP_FCN_SRC_EQ 5
889+
890+// CLR_CMP_CNTL.cmp_src
891+#define CMP_SRC_SRC 1
892+
893+// Overlay formats
894+#define OVLFORMAT_YUV422 (6)
895+#define OVLFORMAT_YUV420 (7)
896+#define OVLFORMAT_RGB565 (5)
897+#define OVLFORMAT_EQU_DISPLAY (8)
898+
899+#define W100_CLK_SRC_XTAL 0
900+#define W100_CLK_SRC_PLL 1
901+
902+#endif
903--- /dev/null
904+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_cursor.c
905@@ -0,0 +1,566 @@
906+/*
907+ * Copyright © 2007 Manuel Teira
908+ *
909+ * Permission to use, copy, modify, distribute, and sell this software and its
910+ * documentation for any purpose is hereby granted without fee, provided that
911+ * the above copyright notice appear in all copies and that both that
912+ * copyright notice and this permission notice appear in supporting
913+ * documentation, and that the name of Manuel Teira not be used in
914+ * advertising or publicity pertaining to distribution of the software without
915+ * specific, written prior permission. Manuel Teira makes no
916+ * representations about the suitability of this software for any purpose. It
917+ * is provided "as is" without express or implied warranty.
918+ *
919+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
920+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
921+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
922+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
923+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
924+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
925+ * PERFORMANCE OF THIS SOFTWARE.
926+ */
927+
928+#ifdef HAVE_CONFIG_H
929+#include <kdrive-config.h>
930+#endif
931+
932+#include "cursorstr.h"
933+#include "imageon.h"
934+#include "imageon_regs.h"
935+
936+#define W100_CURSOR_HEIGHT (16)
937+#define W100_CURSOR_PITCH (4)
938+#define W100_CURSOR_WIDTH (16)
939+#define W100_CURSOR_SIZE W100_CURSOR_PITCH * W100_CURSOR_WIDTH
940+
941+static CARD16 expand2bpp[256];
942+
943+static CARD16 spread_byte(CARD8 b)
944+{
945+ CARD16 s = b;
946+
947+ s = ((s & 0x00f0) << 4) | (s & 0x000f);
948+ s = ((s & 0x0c0c) << 2) | (s & 0x0303);
949+ s = ((s & 0x2222) << 1) | (s & 0x1111);
950+ return s;
951+}
952+
953+static void W100InitExpansionTable()
954+{
955+ int i;
956+ for (i = 0; i < 256; i++) {
957+ expand2bpp[i] = spread_byte(i);
958+ }
959+}
960+
961+#define BigEndian(v) \
962+ (((v & 0x000000ff) << 24) | \
963+ ((v & 0x0000ff00) << 8) | \
964+ ((v & 0x00ff0000) >> 8) | \
965+ ((v & 0xff000000) >> 24))
966+
967+#define PixelOffset(x, y) \
968+ (((y) * W100_CURSOR_PITCH + ((x) / 4)) >> 2)
969+
970+#define PixelShift(x, y) \
971+ (2 * ((x) % W100_CURSOR_WIDTH))
972+
973+#define PixelMask(x, y) \
974+ ((0xc0000000) >> PixelShift(x, y))
975+
976+#define PixelVal(src, x, y) \
977+ ((*(src + PixelOffset(x, y)) & PixelMask(x, y)) >> (30 - PixelShift(x, y)))
978+
979+#define SetPixelVal(ptr, x, y, val) \
980+ *(((CARD32 *)(ptr)) + PixelOffset(x, y)) = \
981+ *(((CARD32 *)(ptr)) + PixelOffset(x, y)) & ~PixelMask(x, y) | \
982+ ((val) & 0x03) << (30 - PixelShift(x2, y2))
983+
984+#define DUMP_CURSOR(src) do { \
985+ int x; \
986+ int y; \
987+ for (y = 0; y < W100_CURSOR_HEIGHT; y++) { \
988+ DBG_IMAGEON(("Line %02d: ", y)); \
989+ for (x = 0; x < W100_CURSOR_WIDTH; x++) { \
990+ DBG_IMAGEON(("%d", PixelVal(src,x,y))); \
991+ } \
992+ DBG_IMAGEON(("\n")); \
993+ } \
994+ DBG_IMAGEON((".\n")); \
995+} while (0)
996+
997+static void
998+W100RotateCursor(int randr, CARD32 *src, CARD32 *dst)
999+{
1000+ int x1, y1, x2, y2;
1001+
1002+ switch (randr & RR_Rotate_All) {
1003+ case RR_Rotate_0:
1004+ x1 = 0;
1005+ y1 = 0;
1006+ for (y2 = 0; y2 < W100_CURSOR_HEIGHT; y2++) {
1007+ for (x2 = W100_CURSOR_WIDTH - 1; x2 >= 0; --x2) {
1008+ SetPixelVal(dst, x2, y2, PixelVal(src, x1, y1));
1009+ ++x1;
1010+ if (x1 >= W100_CURSOR_WIDTH) {
1011+ x1 = 0;
1012+ ++y1;
1013+ }
1014+ }
1015+ }
1016+ break;
1017+ case RR_Rotate_90:
1018+ x1 = 0;
1019+ y1 = 0;
1020+ for (x2 = W100_CURSOR_WIDTH - 1; x2 >= 0; --x2) {
1021+ for (y2 = W100_CURSOR_HEIGHT - 1; y2 >=0; --y2) {
1022+ SetPixelVal(dst, x2, y2, PixelVal(src, x1, y1));
1023+ ++x1;
1024+ if (x1 >= W100_CURSOR_WIDTH) {
1025+ x1 = 0;
1026+ ++y1;
1027+ }
1028+ }
1029+ }
1030+ break;
1031+ case RR_Rotate_180:
1032+ x1 = 0;
1033+ y1 = 0;
1034+ for (y2 = W100_CURSOR_HEIGHT - 1; y2 >= 0; --y2) {
1035+ for (x2 = 0; x2 < W100_CURSOR_WIDTH; x2++) {
1036+ SetPixelVal(dst, x2, y2, PixelVal(src, x1, y1));
1037+ ++x1;
1038+ if (x1 >= W100_CURSOR_WIDTH) {
1039+ x1 = 0;
1040+ ++y1;
1041+ }
1042+ }
1043+ }
1044+ break;
1045+ case RR_Rotate_270:
1046+ x1 = 0;
1047+ y1 = 0;
1048+ for (x2 = 0; x2 < W100_CURSOR_WIDTH; x2++) {
1049+ for (y2 = 0; y2 < W100_CURSOR_HEIGHT; y2++) {
1050+ SetPixelVal(dst, x2, y2, PixelVal(src, x1, y1));
1051+ ++x1;
1052+ if (x1 >= W100_CURSOR_WIDTH) {
1053+ x1 = 0;
1054+ ++y1;
1055+ }
1056+ }
1057+ }
1058+ break;
1059+ }
1060+}
1061+
1062+static void
1063+W100SetCursorColors(ScreenPtr pScreen)
1064+{
1065+ KdScreenPriv(pScreen);
1066+ W100CardInfo(pScreenPriv);
1067+ W100ScreenInfo(pScreenPriv);
1068+ W100Cursor *pCurPriv = &w100s->cursor;
1069+ CursorPtr pCursor = pCurPriv->pCursor;
1070+ CursorBitsPtr bits = pCursor->bits;
1071+ cursor_color_u fgcolor;
1072+ cursor_color_u bgcolor;
1073+
1074+ fgcolor.f.cur_color_r = pCursor->foreRed >> 8;
1075+ fgcolor.f.cur_color_g = pCursor->foreGreen >> 8;
1076+ fgcolor.f.cur_color_b = pCursor->foreBlue >> 8;
1077+
1078+ bgcolor.f.cur_color_r = pCursor->backRed >> 8;
1079+ bgcolor.f.cur_color_g = pCursor->backGreen >> 8;
1080+ bgcolor.f.cur_color_b = pCursor->backBlue >> 8;
1081+
1082+ DBG_IMAGEON(("W100SetCursorColors fg(%02x,%02x,%02x), bg(%02x,%02x,%02x)\n",
1083+ fgcolor.f.cur_color_r,
1084+ fgcolor.f.cur_color_g,
1085+ fgcolor.f.cur_color_b,
1086+ bgcolor.f.cur_color_r,
1087+ bgcolor.f.cur_color_g,
1088+ bgcolor.f.cur_color_b));
1089+
1090+ W100DisableDisplayUpdate(w100c);
1091+ MMIO_OUT32(mmCURSOR1_COLOR0, bgcolor.val);
1092+ MMIO_OUT32(mmCURSOR1_COLOR1, fgcolor.val);
1093+ W100EnableDisplayUpdate(w100c);
1094+
1095+}
1096+
1097+static void
1098+W100LoadCursor(ScreenPtr pScreen)
1099+{
1100+ KdScreenPriv(pScreen);
1101+ W100CardInfo(pScreenPriv);
1102+ W100ScreenInfo(pScreenPriv);
1103+ W100Cursor *pCurPriv = &w100s->cursor;
1104+ CursorPtr pCursor = pCurPriv->pCursor;
1105+ CursorBitsPtr bits = pCursor->bits;
1106+ CARD32 *dst;
1107+ CARD8 tmpCursor0[W100_CURSOR_SIZE];
1108+ CARD8 tmpCursor1[W100_CURSOR_SIZE];
1109+ CARD32 expValue, expMask;
1110+ CARD32 *src;
1111+ CARD32 *mask;
1112+ int lwsrc;
1113+ int line, i;
1114+ int h, w;
1115+
1116+
1117+ pCurPriv->pCursor = pCursor;
1118+ pCurPriv->xhot = bits->xhot;
1119+ pCurPriv->yhot = bits->yhot;
1120+
1121+ memset(tmpCursor0, 0xaa, W100_CURSOR_SIZE);
1122+
1123+ h = bits->height;
1124+ w = bits->width;
1125+ if (h > W100_CURSOR_HEIGHT) {
1126+ h = W100_CURSOR_HEIGHT;
1127+ }
1128+
1129+ if (w > W100_CURSOR_WIDTH) {
1130+ w = W100_CURSOR_WIDTH;
1131+ }
1132+
1133+ src = (CARD32*) bits->source;
1134+ dst = (CARD32*) tmpCursor0;
1135+ mask = (CARD32*) bits->mask;
1136+
1137+ lwsrc = BitmapBytePad(bits->width) >> 2;
1138+
1139+ for (line = 0; line < h; line++) {
1140+ for (i = 0; i < lwsrc; i++) {
1141+ expValue =
1142+ (expand2bpp[src[i] & 0xff]) |
1143+ (expand2bpp[(src[i] >> 8) & 0xff] << 16);
1144+ expMask =
1145+ (expand2bpp[mask[i] & 0xff]) |
1146+ (expand2bpp[(mask[i] >> 8) & 0xff] << 16);
1147+ expMask |= (expMask << 1); /* Expand 01 -> 11, 00 -> 00 */
1148+ dst[i] = (0xaaaaaaaa & ~expMask) | (expValue & expMask);
1149+ }
1150+ src += lwsrc;
1151+ mask += lwsrc;
1152+ dst += lwsrc;
1153+ }
1154+
1155+ /* Rotate the pixmap to get the correct orientation */
1156+ W100RotateCursor(w100c->hw_window.randr,
1157+ (CARD32*) tmpCursor0,
1158+ (CARD32*) tmpCursor1);
1159+
1160+ DUMP_CURSOR((CARD32*)tmpCursor1);
1161+ /* Correct endianness */
1162+ src = (CARD32*) tmpCursor1;
1163+ dst = (CARD32*) (pCurPriv->area->vidmem->base + pCurPriv->area->offset);
1164+ DBG_IMAGEON(("W100LoadCursor(xhot:%d,yhot:%d,width:%d,height:%d) dst(0x%08x)\n",
1165+ bits->xhot, bits->yhot,
1166+ bits->width, bits->height,
1167+ dst));
1168+
1169+ for (line = 0; line < h; line++) {
1170+ for (i = 0; i < lwsrc; i++) {
1171+ dst[i] = BigEndian(src[i]);
1172+ }
1173+ src += lwsrc;
1174+ dst += lwsrc;
1175+ }
1176+
1177+ W100SetCursorColors(pScreen);
1178+}
1179+
1180+static void
1181+W100UnloadCursor(ScreenPtr pScreen)
1182+{
1183+ KdScreenPriv(pScreen);
1184+ W100CardInfo(pScreenPriv);
1185+ W100ScreenInfo(pScreenPriv);
1186+ cursor_h_pos_u hpos;
1187+ W100Cursor *pCurPriv = &w100s->cursor;
1188+
1189+ DBG_IMAGEON(("W100UnloadCursor pCurPriv:%p\n", pCurPriv));
1190+
1191+ hpos.val = pCurPriv->hpos;
1192+ hpos.f.cur_en = 0;
1193+
1194+ W100DisableDisplayUpdate(w100c);
1195+ MMIO_OUT32(mmCURSOR1_H_POS, hpos.val);
1196+ W100EnableDisplayUpdate(w100c);
1197+ pCurPriv->hpos = hpos.val;
1198+}
1199+
1200+static void
1201+W100MoveCursor(ScreenPtr pScreen, int x, int y)
1202+{
1203+ KdScreenPriv(pScreen);
1204+ W100CardInfo(pScreenPriv);
1205+ W100ScreenInfo(pScreenPriv);
1206+ W100Cursor *pCurPriv = &w100s->cursor;
1207+ int xoffs, yoffs;
1208+ cursor_offset_u cursor_offset;
1209+ cursor_h_pos_u hpos;
1210+ cursor_v_pos_u vpos;
1211+ graphic_h_disp_u graphic_hdisp;
1212+ graphic_v_disp_u graphic_vdisp;
1213+ int tx, ty, tw, th;
1214+
1215+
1216+ if (!pCurPriv->has_cursor) {
1217+ return;
1218+ }
1219+ if (!pScreenPriv->enabled) {
1220+ return;
1221+ }
1222+
1223+ graphic_hdisp.val = w100c->regs.GRAPHIC_H_DISP;
1224+ graphic_vdisp.val = w100c->regs.GRAPHIC_V_DISP;
1225+ xoffs = 0;
1226+ yoffs = 0;
1227+ x -= pCurPriv->xhot;
1228+ y -= pCurPriv->yhot;
1229+ tx = W100MapToHWX(w100c, x, y, pCurPriv->width, pCurPriv->height);
1230+ ty = W100MapToHWY(w100c, x, y, pCurPriv->width, pCurPriv->height);
1231+ tw = W100MapToHWW(w100c, x, y, pCurPriv->width, pCurPriv->height);
1232+ th = W100MapToHWH(w100c, x, y, pCurPriv->width, pCurPriv->height);
1233+
1234+ if (tx < 0) {
1235+ xoffs = -tx;
1236+ tw -= xoffs;
1237+ tx = 0;
1238+ }
1239+
1240+ if (ty < 0) {
1241+ yoffs = -ty;
1242+ th -= yoffs;
1243+ ty = 0;
1244+ }
1245+
1246+ hpos.f.cur_h_start = graphic_hdisp.f.graphic_h_start + tx;
1247+ hpos.f.cur_h_end = hpos.f.cur_h_start + tw;
1248+ hpos.f.cur_en = 1;
1249+ vpos.f.cur_v_start = graphic_vdisp.f.graphic_v_start + ty;
1250+ vpos.f.cur_v_end = vpos.f.cur_v_start + th;
1251+ cursor_offset.f.cur_x_offset = xoffs;
1252+ cursor_offset.f.cur_y_offset = yoffs;
1253+ cursor_offset.f.cur_offset = (CARD32)
1254+ W100_HOST2CARD(pCurPriv->area->vidmem->base
1255+ + pCurPriv->area->offset);
1256+ DBG_IMAGEON(("W100MoveCursor dst(x:%d,y:%d),"
1257+ "mapped(x:%d,y:%d,xoffs:%d,yoffs:%d)\n",
1258+ x, y, tx, ty, xoffs, yoffs));
1259+
1260+ W100DisableDisplayUpdate(w100c);
1261+ MMIO_OUT32(mmCURSOR1_OFFSET, cursor_offset.val);
1262+ MMIO_OUT32(mmCURSOR1_V_POS, vpos.val);
1263+ MMIO_OUT32(mmCURSOR1_H_POS, hpos.val);
1264+ W100EnableDisplayUpdate(w100c);
1265+
1266+ pCurPriv->hpos = hpos.val;
1267+ pCurPriv->vpos = vpos.val;
1268+ pCurPriv->coffset = cursor_offset.val;
1269+
1270+}
1271+
1272+static Bool
1273+W100RealizeCursor(ScreenPtr pScreen, CursorPtr pCursor)
1274+{
1275+ KdScreenPriv(pScreen);
1276+ W100CardInfo(pScreenPriv);
1277+ W100ScreenInfo(pScreenPriv);
1278+ W100Cursor *pCurPriv = &w100s->cursor;
1279+ DBG_IMAGEON(("W100RealizeCursor\n"));
1280+
1281+ if (!pScreenPriv->enabled) {
1282+ return TRUE;
1283+ }
1284+
1285+ if (pCursor && pCurPriv->pCursor == pCursor) {
1286+ int x, y;
1287+ miPointerPosition(&x, &y);
1288+ W100LoadCursor(pScreen);
1289+ W100MoveCursor(pScreen, x, y);
1290+ }
1291+ return TRUE;
1292+}
1293+
1294+
1295+static Bool
1296+W100UnrealizeCursor(ScreenPtr pScreen, CursorPtr pCursor)
1297+{
1298+ DBG_IMAGEON(("W100UnrealizeCursor\n"));
1299+ return TRUE;
1300+}
1301+
1302+
1303+static void
1304+W100SetCursor(ScreenPtr pScreen, CursorPtr pCursor, int x, int y)
1305+{
1306+ KdScreenPriv(pScreen);
1307+ W100CardInfo(pScreenPriv);
1308+ W100ScreenInfo(pScreenPriv);
1309+ W100Cursor *pCurPriv = &w100s->cursor;
1310+
1311+ pCurPriv->pCursor = pCursor;
1312+
1313+ if (!pScreenPriv->enabled) {
1314+ return;
1315+ }
1316+
1317+ if (pCursor) {
1318+ W100LoadCursor(pScreen);
1319+ W100MoveCursor(pScreen, x, y);
1320+ } else {
1321+ W100UnloadCursor(pScreen);
1322+ }
1323+}
1324+
1325+
1326+miPointerSpriteFuncRec W100PointerSpriteFuncs = {
1327+ W100RealizeCursor,
1328+ W100UnrealizeCursor,
1329+ W100SetCursor,
1330+ W100MoveCursor,
1331+};
1332+
1333+static void
1334+W100QueryBestSize(int class, unsigned short *pwidth, unsigned short *pheight,
1335+ ScreenPtr pScreen)
1336+{
1337+ KdScreenPriv(pScreen);
1338+ W100ScreenInfo(pScreenPriv);
1339+ W100Cursor *pCurPriv = &w100s->cursor;
1340+
1341+ switch (class) {
1342+ case CursorShape:
1343+ if (*pwidth > pCurPriv->width) {
1344+ *pwidth = pCurPriv->width;
1345+ }
1346+ if (*pheight > pCurPriv->height) {
1347+ *pheight = pCurPriv->height;
1348+ }
1349+ if (*pwidth > pScreen->width) {
1350+ *pwidth = pScreen->width;
1351+ }
1352+ if (*pheight > pScreen->height) {
1353+ *pheight = pScreen->height;
1354+ }
1355+ break;
1356+ default:
1357+ fbQueryBestSize(class, pwidth, pheight, pScreen);
1358+ break;
1359+ }
1360+}
1361+
1362+static void
1363+W100CursorSave(ScreenPtr pScreen, KdOffscreenArea *area)
1364+{
1365+ KdScreenPriv(pScreen);
1366+ W100ScreenInfo(pScreenPriv);
1367+ W100Cursor *pCurPriv = &w100s->cursor;
1368+ DBG_IMAGEON(("W100CursorSave\n"));
1369+
1370+ pCurPriv->area = NULL;
1371+}
1372+
1373+void
1374+W100CursorEnable(ScreenPtr pScreen)
1375+{
1376+ KdScreenPriv(pScreen);
1377+ W100CardInfo(pScreenPriv);
1378+ W100ScreenInfo(pScreenPriv);
1379+ W100Cursor *pCurPriv = &w100s->cursor;
1380+
1381+ if (!pCurPriv->has_cursor) {
1382+ return;
1383+ }
1384+
1385+ DBG_IMAGEON(("W100CursorEnable\n"));
1386+
1387+ if (pCurPriv->area == NULL) {
1388+ pCurPriv->area = KdOffscreenAlloc(pScreen,
1389+ W100_CURSOR_SIZE, 0, TRUE,
1390+ W100CursorSave, w100s);
1391+ }
1392+ if (pCurPriv->area == NULL) {
1393+ FatalError("Couldn't allocate offscreen memory for cursor.\n");
1394+ } else {
1395+ DBG_IMAGEON(("Cursor memory at 0x%08x(0x%08x)\n",
1396+ pCurPriv->area->vidmem->base + pCurPriv->area->offset,
1397+ W100_HOST2CARD(pCurPriv->area->vidmem->base
1398+ + pCurPriv->area->offset)));
1399+ }
1400+ if (pCurPriv->pCursor) {
1401+ int x, y;
1402+ miPointerPosition(&x, &y);
1403+ W100LoadCursor(pScreen);
1404+ W100MoveCursor(pScreen, x, y);
1405+ } else {
1406+ W100UnloadCursor(pScreen);
1407+ }
1408+}
1409+
1410+
1411+void
1412+W100CursorDisable(ScreenPtr pScreen)
1413+{
1414+ KdScreenPriv(pScreen);
1415+ W100CardInfo(pScreenPriv);
1416+ W100ScreenInfo(pScreenPriv);
1417+ W100Cursor *pCurPriv = &w100s->cursor;
1418+ DBG_IMAGEON(("W100CursorDisable\n"));
1419+
1420+ if (!pScreenPriv->enabled || !pCurPriv->has_cursor) {
1421+ return;
1422+ }
1423+
1424+ if (pCurPriv->pCursor) {
1425+ W100UnloadCursor(pScreen);
1426+ }
1427+
1428+ pCurPriv->area = NULL;
1429+}
1430+
1431+Bool
1432+W100CursorInit(ScreenPtr pScreen)
1433+{
1434+ KdScreenPriv(pScreen);
1435+ W100CardInfo(pScreenPriv);
1436+ W100ScreenInfo(pScreenPriv);
1437+ W100Cursor *pCurPriv = &w100s->cursor;
1438+
1439+ DBG_IMAGEON(("W100CursorInit\n"));
1440+
1441+ pCurPriv->width = W100_CURSOR_WIDTH;
1442+ pCurPriv->height = W100_CURSOR_HEIGHT;
1443+ pScreen->QueryBestSize = W100QueryBestSize;
1444+ miPointerInitialize(pScreen,
1445+ &W100PointerSpriteFuncs,
1446+ &kdPointerScreenFuncs,
1447+ FALSE);
1448+ pCurPriv->has_cursor = TRUE;
1449+ pCurPriv->pCursor = NULL;
1450+ W100InitExpansionTable();
1451+ return TRUE;
1452+}
1453+
1454+
1455+void
1456+W100RecolorCursor(ScreenPtr pScreen, int ndef, xColorItem *pdef)
1457+{
1458+ return;
1459+}
1460+
1461+
1462+void
1463+W100CursorFini(ScreenPtr pScreen)
1464+{
1465+ KdScreenPriv(pScreen);
1466+ W100ScreenInfo(pScreenPriv);
1467+ W100Cursor *pCurPriv = &w100s->cursor;
1468+
1469+ pCurPriv->has_cursor = FALSE;
1470+ pCurPriv->pCursor = NULL;
1471+}
1472--- /dev/null
1473+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_draw.c
1474@@ -0,0 +1,237 @@
1475+/*
1476+ * Copyright © 2007 Manuel Teira
1477+ *
1478+ * Permission to use, copy, modify, distribute, and sell this software and its
1479+ * documentation for any purpose is hereby granted without fee, provided that
1480+ * the above copyright notice appear in all copies and that both that
1481+ * copyright notice and this permission notice appear in supporting
1482+ * documentation, and that the name of Manuel Teira not be used in
1483+ * advertising or publicity pertaining to distribution of the software without
1484+ * specific, written prior permission. Manuel Teira makes no
1485+ * representations about the suitability of this software for any purpose. It
1486+ * is provided "as is" without express or implied warranty.
1487+ *
1488+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1489+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1490+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1491+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1492+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1493+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1494+ * PERFORMANCE OF THIS SOFTWARE.
1495+ */
1496+
1497+#ifdef HAVE_CONFIG_H
1498+#include <kdrive-config.h>
1499+#endif
1500+
1501+#include "imageon.h"
1502+#include "imageon_regs.h"
1503+#include "imageon_const.h"
1504+#include "imageon_support.h"
1505+#include "kaa.h"
1506+
1507+static W100CardInfo *currentCard;
1508+
1509+void
1510+W100WaitMarker(ScreenPtr pScreen, int marker)
1511+{
1512+ KdScreenPriv(pScreen);
1513+ W100CardInfo(pScreenPriv);
1514+ W100WaitIdle(w100c);
1515+}
1516+
1517+Bool
1518+W100PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
1519+{
1520+ KdScreenPriv(pPix->drawable.pScreen);
1521+ W100ScreenInfo(pScreenPriv);
1522+ W100CardInfo(pScreenPriv);
1523+ int fifoEntries = 4;
1524+
1525+ DBG_IMAGEON(("W100PrepareSolid(alu:%d, pm:0x%08x, fg:%d)\n",
1526+ alu, pm, fg));
1527+
1528+ W100ResetContext(w100c);
1529+ W100SetPixelMask(w100c, pm);
1530+
1531+ if (W100SetDestinationPixmap(pPix)) {
1532+ if (w100c->ctx.mask.enable) {
1533+ ++fifoEntries;
1534+ }
1535+ if (W100WaitCmdFifoEntries(w100c, fifoEntries)) {
1536+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, W100ComputeSolidGmc(w100c, alu));
1537+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
1538+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
1539+ MMIO_OUT32(mmDP_BRUSH_FRGD_CLR, fg);
1540+
1541+ if (w100c->ctx.mask.enable) {
1542+ MMIO_OUT32(mmDP_WRITE_MSK, pm);
1543+ }
1544+ currentCard = w100c;
1545+ return TRUE;
1546+ }
1547+ }
1548+ ErrorF("Error in W100PrepareSolid\n");
1549+ return FALSE;
1550+}
1551+
1552+void
1553+W100Solid(int x1, int y1, int x2, int y2)
1554+{
1555+ W100CardInfo *w100c = currentCard;
1556+ DBG_IMAGEON(("W100Solid(x1:%d,y1:%d,x2:%d,y2:%d)\n", x1, y1, x2, y2));
1557+
1558+ if (W100WaitCmdFifoEntries(w100c, 2)) {
1559+ MMIO_OUT32(mmDST_Y_X, (y1 << 16) | x1);
1560+ MMIO_OUT32(mmDST_HEIGHT_WIDTH, ((y2 - y1) << 16) | (x2 - x1));
1561+ } else {
1562+ ErrorF("Error in W100Solid\n");
1563+ }
1564+}
1565+
1566+void
1567+W100DoneSolid(void)
1568+{
1569+}
1570+
1571+
1572+Bool
1573+W100PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
1574+ int dx, int dy, int alu, Pixel pm)
1575+{
1576+ KdScreenPriv(pDst->drawable.pScreen);
1577+ W100ScreenInfo(pScreenPriv);
1578+ W100CardInfo(pScreenPriv);
1579+ dp_datatype_u datatype;
1580+
1581+ int fifoEntries = 6;
1582+
1583+ W100ResetContext(w100c);
1584+ W100SetPixelMask(w100c, pm);
1585+ W100SetXForm(w100c, dx, dy);
1586+
1587+ if (W100SetSourcePixmap(pSrc) && W100SetDestinationPixmap(pDst)) {
1588+ DBG_IMAGEON(("W100PrepareCopy(src(pitch:%d,offset:0x%08x),"
1589+ "dst(pitch:%d,offset:0x%08x))\n",
1590+ w100c->ctx.src.pitch,
1591+ w100c->ctx.src.offset,
1592+ w100c->ctx.dst.pitch,
1593+ w100c->ctx.dst.offset));
1594+ if (w100c->ctx.mask.enable) {
1595+ ++fifoEntries;
1596+ }
1597+
1598+ if (W100WaitCmdFifoEntries(w100c, fifoEntries)) {
1599+ MMIO_OUT32(mmSRC_PITCH, w100c->ctx.src.pitch);
1600+ MMIO_OUT32(mmSRC_OFFSET, w100c->ctx.src.offset);
1601+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
1602+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
1603+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, W100ComputeCopyGmc(w100c, alu));
1604+ if (w100c->ctx.mask.enable) {
1605+ MMIO_OUT32(mmDP_WRITE_MSK, pm);
1606+ }
1607+ MMIO_OUT32(mmDP_CNTL, w100c->ctx.xform.dataPath);
1608+ currentCard = w100c;
1609+ return TRUE;
1610+ }
1611+ }
1612+ ErrorF("Error in W100PrepareCopy\n");
1613+ return FALSE;
1614+}
1615+
1616+void
1617+W100Copy(int srcX, int srcY, int dstX, int dstY, int w, int h)
1618+{
1619+ W100CardInfo *w100c = currentCard;
1620+ DBG_IMAGEON(("W100Copy(src(x:%d,y:%d),dst(x:%d,y:%d),w:%d,h:%d)\n",
1621+ srcX, srcY,
1622+ dstX, dstY,
1623+ w, h));
1624+ if (w100c->ctx.xform.dx < 0) {
1625+ dstX += w - 1;
1626+ srcX += w - 1;
1627+ }
1628+
1629+ if (w100c->ctx.xform.dy < 0) {
1630+ dstY += h - 1;
1631+ srcY += h - 1;
1632+ }
1633+
1634+ if (W100WaitCmdFifoEntries(w100c, 3)) {
1635+ MMIO_OUT32(mmSRC_Y_X, (srcY << 16) | srcX);
1636+ MMIO_OUT32(mmDST_Y_X, (dstY << 16) | dstX);
1637+ MMIO_OUT32(mmDST_HEIGHT_WIDTH, (h << 16) | w);
1638+ } else {
1639+ ErrorF("Error in W100Copy\n");
1640+ }
1641+}
1642+
1643+void
1644+W100DoneCopy(void)
1645+{
1646+}
1647+
1648+Bool
1649+W100InitAccel(ScreenPtr pScreen)
1650+{
1651+ KdScreenPriv(pScreen);
1652+ W100ScreenInfo(pScreenPriv);
1653+
1654+
1655+ DBG_IMAGEON(("--W100InitAccel: %d/%d depth/bpp\n",
1656+ pScreenPriv->screen->fb[0].depth,
1657+ pScreenPriv->screen->fb[0].bitsPerPixel));
1658+
1659+ memset(&w100s->kaa, 0, sizeof(KaaScreenInfoRec));
1660+ w100s->kaa.waitMarker = W100WaitMarker;
1661+ w100s->kaa.PrepareSolid = W100PrepareSolid;
1662+ w100s->kaa.Solid = W100Solid;
1663+ w100s->kaa.DoneSolid = W100DoneSolid;
1664+ w100s->kaa.PrepareCopy = W100PrepareCopy;
1665+ w100s->kaa.Copy = W100Copy;
1666+ w100s->kaa.DoneCopy = W100DoneCopy;
1667+
1668+ w100s->kaa.flags |= KAA_OFFSCREEN_PIXMAPS;
1669+ /* Offset alignment, not sure if this is enought */
1670+ w100s->kaa.offsetAlign = 0;
1671+ w100s->kaa.pitchAlign = 16;
1672+
1673+ if (!kaaDrawInit(pScreen, &w100s->kaa)) {
1674+ return FALSE;
1675+ }
1676+ DBG_IMAGEON(("KAA flags: 0x%08x\n", w100s->kaa.flags));
1677+ return TRUE;
1678+}
1679+
1680+void
1681+W100EnableAccel(ScreenPtr pScreen)
1682+{
1683+ KdScreenPriv(pScreen);
1684+ W100ScreenInfo(pScreenPriv);
1685+ W100CardInfo(pScreenPriv);
1686+
1687+ DBG_IMAGEON(("--W100EnableAccel\n"));
1688+
1689+ w100s->kaa.PrepareBlend = NULL;
1690+ w100s->kaa.Blend = NULL;
1691+ w100s->kaa.DoneBlend = NULL;
1692+ w100s->kaa.CheckComposite = NULL;
1693+ w100s->kaa.PrepareComposite = NULL;
1694+ w100s->kaa.Composite = NULL;
1695+ w100s->kaa.DoneComposite = NULL;
1696+ w100s->kaa.UploadToScreen = NULL;
1697+ w100s->kaa.UploadToScratch = NULL;
1698+ kaaMarkSync(pScreen);
1699+}
1700+
1701+void
1702+W100DisableAccel(ScreenPtr pScreen)
1703+{
1704+ DBG_IMAGEON(("--W100DisableAccel\n"));
1705+}
1706+
1707+void
1708+W100FiniAccel(ScreenPtr pScreen)
1709+{
1710+ DBG_IMAGEON(("--W100FiniAccel\n"));
1711+}
1712--- /dev/null
1713+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon.h
1714@@ -0,0 +1,261 @@
1715+/*
1716+ * Copyright © 2007 Manuel Teira
1717+ *
1718+ * Permission to use, copy, modify, distribute, and sell this software and its
1719+ * documentation for any purpose is hereby granted without fee, provided that
1720+ * the above copyright notice appear in all copies and that both that
1721+ * copyright notice and this permission notice appear in supporting
1722+ * documentation, and that the name of Manuel Teira not be used in
1723+ * advertising or publicity pertaining to distribution of the software without
1724+ * specific, written prior permission. Manuel Teira makes no
1725+ * representations about the suitability of this software for any purpose. It
1726+ * is provided "as is" without express or implied warranty.
1727+ *
1728+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1729+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1730+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1731+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1732+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1733+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1734+ * PERFORMANCE OF THIS SOFTWARE.
1735+ */
1736+
1737+#ifndef _IMAGEON_H_
1738+#define _IMAGEON_H_
1739+
1740+#ifdef HAVE_CONFIG_H
1741+#include <kdrive-config.h>
1742+#endif
1743+
1744+#include <fbdev.h>
1745+
1746+#include <kxv.h>
1747+
1748+#define DEBUG_IMAGEON 0
1749+#if DEBUG_IMAGEON
1750+#define DBG_IMAGEON(a) ErrorF a
1751+#else
1752+#define DBG_IMAGEON(a)
1753+#endif
1754+
1755+
1756+#define W100_MEM_BASE (0x08000000)
1757+#define W100_REG_OFFSET (0x00010000)
1758+#define W100_REG_BASE (W100_MEM_BASE + W100_REG_OFFSET)
1759+#define W100_MEM_SIZE (0x01000000)
1760+#define W100_REG_SIZE (0x00002000)
1761+#define W100_CMDFIFO_SIZE (16)
1762+
1763+#define W100_CARD2HOST(x) (w100c->mem_base + (CARD32)(x))
1764+#define W100_HOST2CARD(x) ((x) - (CARD32)(w100c->mem_base))
1765+#define W100_MEMAREAS (2)
1766+#define W100_INTMEM (0)
1767+#define W100_EXTMEM (1)
1768+
1769+#define W100_SYSFS_BASE "/sys/bus/platform/devices/w100fb/"
1770+
1771+#define MMIO_OUT32(a, v) (*(VOL32 *)((w100c->reg_base) + (a)) = (v))
1772+#define MMIO_IN32(a) (*(VOL32 *)((w100c->reg_base) + (a)))
1773+
1774+#define W100_MAX(x, y) ((x) > (y) ? x : y)
1775+#define W100_MIN(x, y) ((x) < (y) ? x : y)
1776+
1777+#define W100_ALIGN(q, a) ((q + a - 1) & ~(a - 1))
1778+
1779+#define TIMEOUT_LOCALS struct timeval _target, _curtime;
1780+
1781+static inline Bool
1782+tv_le(struct timeval *tv1, struct timeval *tv2)
1783+{
1784+ if (tv1->tv_sec < tv2->tv_sec ||
1785+ (tv1->tv_sec == tv2->tv_sec &&
1786+ tv1->tv_usec < tv2->tv_usec))
1787+ return TRUE;
1788+ else
1789+ return FALSE;
1790+}
1791+
1792+#define WHILE_NOT_TIMEOUT(_timeout) \
1793+ gettimeofday(&_target, NULL); \
1794+ _target.tv_usec += ((_timeout) * 1000000); \
1795+ _target.tv_sec += _target.tv_usec / 1000000; \
1796+ _target.tv_usec = _target.tv_usec % 1000000; \
1797+ while (gettimeofday(&_curtime, NULL), tv_le(&_curtime, &_target))
1798+
1799+#define TIMEDOUT() (!tv_le(&_curtime, &_target))
1800+
1801+typedef volatile CARD8 VOL8;
1802+typedef volatile CARD16 VOL16;
1803+typedef volatile CARD32 VOL32;
1804+
1805+typedef struct _W100CardEntry {
1806+ CARD16 vendor;
1807+ CARD16 device;
1808+ CARD8 caps;
1809+ char *name;
1810+} W100CardEntry;
1811+
1812+
1813+typedef enum _W100Caps {
1814+ W100XVSupport = 1
1815+} W100Caps;
1816+
1817+typedef struct _W100ModeSpec {
1818+ CARD16 width;
1819+ CARD16 height;
1820+ CARD8 bpp;
1821+ CARD8 fbpool;
1822+ Bool supported;
1823+} W100ModeSpec;
1824+
1825+typedef struct _W100Mode {
1826+ CARD16 width;
1827+ CARD16 height;
1828+ CARD8 bpp;
1829+} W100Mode;
1830+
1831+typedef struct _W100MemArea {
1832+ CARD8 *start;
1833+ CARD32 size;
1834+ CARD8 priority;
1835+} W100MemArea;
1836+
1837+typedef struct _W100StartupInfo {
1838+ W100CardEntry *card_id;
1839+ W100Mode mode;
1840+ Bool portrait;
1841+ int randr;
1842+} W100StartupInfo;
1843+
1844+typedef struct _W100CardInfo {
1845+ FbdevPriv fbdev;
1846+ W100CardEntry *card_id;
1847+ CARD8 *mem_base;
1848+ CARD8 *reg_base;
1849+ W100MemArea **memareas;
1850+ int num_memareas;
1851+ int cmdfifo_entries;
1852+ struct {
1853+ CARD32 ENG_CNTL;
1854+ CARD32 VIDEO_CTRL;
1855+ CARD32 GRAPHIC_H_DISP;
1856+ CARD32 GRAPHIC_V_DISP;
1857+ CARD32 DISP_DEBUG2;
1858+ } regs;
1859+ struct {
1860+ CARD8 *offset;
1861+ CARD16 width;
1862+ CARD16 height;
1863+ int randr;
1864+ W100ModeSpec *mode;
1865+ CARD8 bpp;
1866+ } hw_window;
1867+ CARD8 last_dst_videomem;
1868+ CARD8 last_src_videomem;
1869+ struct {
1870+ struct {
1871+ CARD8 datatype;
1872+ CARD32 pitch;
1873+ CARD32 offset;
1874+ CARD8 videomem;
1875+ } dst;
1876+ struct {
1877+ CARD8 datatype;
1878+ CARD32 pitch;
1879+ CARD32 offset;
1880+ CARD8 videomem;
1881+ } src;
1882+ struct {
1883+ int dx;
1884+ int dy;
1885+ int randr;
1886+ Bool mirror;
1887+ CARD32 dataPath;
1888+ } xform;
1889+ struct {
1890+ Pixel pm;
1891+ Bool enable;
1892+ } mask;
1893+ } ctx;
1894+} W100CardInfo;
1895+
1896+#define W100GetCardInfo(kd) ((W100CardInfo *) ((kd)->card->driver))
1897+#define W100CardInfo(kd) W100CardInfo *w100c = W100GetCardInfo(kd)
1898+
1899+typedef struct _W100Cursor {
1900+ int width, height;
1901+ int xhot, yhot;
1902+ Bool has_cursor;
1903+ CursorPtr pCursor;
1904+ KdOffscreenArea *area;
1905+ CARD32 vpos;
1906+ CARD32 hpos;
1907+ CARD32 coffset;
1908+} W100Cursor;
1909+
1910+typedef struct _W100ScreenInfo {
1911+ FbdevScrPriv fbdev;
1912+ KaaScreenInfoRec kaa;
1913+ W100CardInfo *w100c;
1914+ KdScreenInfo *screen;
1915+ KdVideoAdaptorPtr pAdaptor;
1916+ W100Cursor cursor;
1917+} W100ScreenInfo;
1918+
1919+#define W100GetScreenInfo(kd) ((W100ScreenInfo *) ((kd)->screen->driver))
1920+#define W100ScreenInfo(kd) W100ScreenInfo *w100s = W100GetScreenInfo(kd)
1921+
1922+typedef enum _W100VideoStatus {
1923+ W100_OVERLAY_ON = 1,
1924+ W100_OVERLAY_CONFIGURED = 2
1925+} W100VideoStatus;
1926+
1927+
1928+typedef struct _W100PortPriv {
1929+ CARD32 videoStatus;
1930+ CARD32 videoCtrl;
1931+ RegionRec clip;
1932+ KdOffscreenArea *offSurface;
1933+ CARD32 offSize;
1934+ KdOffscreenArea *ovlSurface;
1935+ CARD32 ovlSize;
1936+ CARD32 YPlaneOffset;
1937+ CARD32 UPlaneOffset;
1938+ CARD32 VPlaneOffset;
1939+ CARD32 colorKey;
1940+ CARD8 brightness;
1941+ CARD32 maxOverlaySize;
1942+ CARD16 ovlX;
1943+ CARD16 ovlY;
1944+ CARD16 ovlWidth;
1945+ CARD16 ovlHeight;
1946+ CARD8 videoHorExp;
1947+ CARD8 videoVerExp;
1948+ int id;
1949+} W100PortPrivRec, *W100PortPrivPtr;
1950+
1951+extern KdCardFuncs W100Funcs;
1952+
1953+/* imageon_draw.c */
1954+void W100WaitMarker(ScreenPtr pScreen, int marker);
1955+Bool W100PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg);
1956+void W100Solid(int x1, int y1, int x2, int y2);
1957+Bool W100PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
1958+ int dx, int dy, int alu, Pixel pm);
1959+void W100Copy(int srcX, int srcY, int dstX, int dstY, int w, int h);
1960+void W100DoneCopy(void);
1961+Bool W100InitAccel(ScreenPtr pScreen);
1962+void W100EnableAccel(ScreenPtr pScreen);
1963+void W100DisableAccel(ScreenPtr pScreen);
1964+void W100FiniAccel(ScreenPtr pScreen);
1965+/* imageon_cursor.c */
1966+void W100CursorEnable(ScreenPtr pScreen);
1967+void W100CursorDisable(ScreenPtr pScreen);
1968+Bool W100CursorInit(ScreenPtr pScreen);
1969+void W100RecolorCursor(ScreenPtr pScreen, int ndef, xColorItem * pdef);
1970+void W100CursorFini(ScreenPtr pScreen);
1971+
1972+
1973+
1974+
1975+#endif /* _IMAGEON_H_ */
1976--- /dev/null
1977+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_regs.h
1978@@ -0,0 +1,4155 @@
1979+/*
1980+ * Copyright © 2007 Manuel Teira
1981+ *
1982+ * Permission to use, copy, modify, distribute, and sell this software and its
1983+ * documentation for any purpose is hereby granted without fee, provided that
1984+ * the above copyright notice appear in all copies and that both that
1985+ * copyright notice and this permission notice appear in supporting
1986+ * documentation, and that the name of Manuel Teira not be used in
1987+ * advertising or publicity pertaining to distribution of the software without
1988+ * specific, written prior permission. Manuel Teira makes no
1989+ * representations about the suitability of this software for any purpose. It
1990+ * is provided "as is" without express or implied warranty.
1991+ *
1992+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
1993+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
1994+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
1995+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
1996+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
1997+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1998+ * PERFORMANCE OF THIS SOFTWARE.
1999+ */
2000+
2001+#ifndef __IMAGEON_REGS_H__
2002+#define __IMAGEON_REGS_H__
2003+
2004+/* Block CIF Start: */
2005+#define mmCHIP_ID 0x0000
2006+#define mmREVISION_ID 0x0004
2007+#define mmWRAP_BUF_A 0x0008
2008+#define mmWRAP_BUF_B 0x000C
2009+#define mmWRAP_TOP_DIR 0x0010
2010+#define mmWRAP_START_DIR 0x0014
2011+#define mmCIF_CNTL 0x0018
2012+#define mmCFGREG_BASE 0x001C
2013+#define mmCIF_IO 0x0020
2014+#define mmCIF_READ_DBG 0x0024
2015+#define mmCIF_WRITE_DBG 0x0028
2016+#define cfgIND_ADDR_A_0 0x0000
2017+#define cfgIND_ADDR_A_1 0x0001
2018+#define cfgIND_ADDR_A_2 0x0002
2019+#define cfgIND_DATA_A 0x0003
2020+#define cfgREG_BASE 0x0004
2021+#define cfgINTF_CNTL 0x0005
2022+#define cfgSTATUS 0x0006
2023+#define cfgCPU_DEFAULTS 0x0007
2024+#define cfgIND_ADDR_B_0 0x0008
2025+#define cfgIND_ADDR_B_1 0x0009
2026+#define cfgIND_ADDR_B_2 0x000A
2027+#define cfgIND_DATA_B 0x000B
2028+#define cfgPM4_RPTR 0x000C
2029+#define cfgSCRATCH 0x000D
2030+#define cfgPM4_WRPTR_0 0x000E
2031+#define cfgPM4_WRPTR_1 0x000F
2032+/* Block CIF End: */
2033+
2034+/* Block CP Start: */
2035+#define mmCP_RB_CNTL 0x0210
2036+#define mmCP_RB_BASE 0x0214
2037+#define mmCP_RB_RPTR_ADDR 0x0218
2038+#define mmCP_RB_RPTR 0x021C
2039+#define mmCP_RB_RPTR_WR 0x02F8
2040+#define mmCP_RB_WPTR 0x0220
2041+#define mmCP_IB_BASE 0x0228
2042+#define mmCP_IB_BUFSZ 0x022C
2043+#define mmCP_CSQ_CNTL 0x0230
2044+#define mmCP_CSQ_APER_PRIMARY 0x0300
2045+#define mmCP_CSQ_APER_INDIRECT 0x0340
2046+#define mmCP_ME_CNTL 0x0240
2047+#define mmCP_ME_RAM_ADDR 0x0244
2048+#define mmCP_ME_RAM_RADDR 0x0248
2049+#define mmCP_ME_RAM_DATAH 0x024C
2050+#define mmCP_ME_RAM_DATAL 0x0250
2051+#define mmCP_DEBUG 0x025C
2052+#define mmSCRATCH_REG0 0x0260
2053+#define mmSCRATCH_REG1 0x0264
2054+#define mmSCRATCH_REG2 0x0268
2055+#define mmSCRATCH_REG3 0x026C
2056+#define mmSCRATCH_REG4 0x0270
2057+#define mmSCRATCH_REG5 0x0274
2058+#define mmSCRATCH_UMSK 0x0280
2059+#define mmSCRATCH_ADDR 0x0284
2060+#define mmCP_CSQ_ADDR 0x02E4
2061+#define mmCP_CSQ_DATA 0x02E8
2062+#define mmCP_CSQ_STAT 0x02EC
2063+#define mmCP_STAT 0x02F0
2064+#define mmGEN_INT_CNTL 0x0200
2065+#define mmGEN_INT_STATUS 0x0204
2066+/* Block CP End: */
2067+
2068+/* Block DISPLAY Start: */
2069+#define mmLCD_FORMAT 0x0410
2070+#define mmGRAPHIC_CTRL 0x0414
2071+#define mmGRAPHIC_OFFSET 0x0418
2072+#define mmGRAPHIC_PITCH 0x041C
2073+#define mmCRTC_TOTAL 0x0420
2074+#define mmACTIVE_H_DISP 0x0424
2075+#define mmACTIVE_V_DISP 0x0428
2076+#define mmGRAPHIC_H_DISP 0x042C
2077+#define mmGRAPHIC_V_DISP 0x0430
2078+#define mmVIDEO_CTRL 0x0434
2079+#define mmGRAPHIC_KEY 0x0438
2080+#define mmVIDEO_Y_OFFSET 0x043C
2081+#define mmVIDEO_Y_PITCH 0x0440
2082+#define mmVIDEO_U_OFFSET 0x0444
2083+#define mmVIDEO_U_PITCH 0x0448
2084+#define mmVIDEO_V_OFFSET 0x044C
2085+#define mmVIDEO_V_PITCH 0x0450
2086+#define mmVIDEO_H_POS 0x0454
2087+#define mmVIDEO_V_POS 0x0458
2088+#define mmBRIGHTNESS_CNTL 0x045C
2089+#define mmCURSOR1_OFFSET 0x0460
2090+#define mmCURSOR1_H_POS 0x0464
2091+#define mmCURSOR1_V_POS 0x0468
2092+#define mmCURSOR1_COLOR0 0x046C
2093+#define mmCURSOR1_COLOR1 0x0470
2094+#define mmCURSOR2_OFFSET 0x0474
2095+#define mmCURSOR2_H_POS 0x0478
2096+#define mmCURSOR2_V_POS 0x047C
2097+#define mmCURSOR2_COLOR0 0x0480
2098+#define mmCURSOR2_COLOR1 0x0484
2099+#define mmDISP_INT_CNTL 0x0488
2100+#define mmCRTC_SS 0x048C
2101+#define mmCRTC_LS 0x0490
2102+#define mmCRTC_REV 0x0494
2103+#define mmCRTC_DCLK 0x049C
2104+#define mmCRTC_GS 0x04A0
2105+#define mmCRTC_VPOS_GS 0x04A4
2106+#define mmCRTC_GCLK 0x04A8
2107+#define mmCRTC_GOE 0x04AC
2108+#define mmCRTC_FRAME 0x04B0
2109+#define mmCRTC_FRAME_VPOS 0x04B4
2110+#define mmGPIO_DATA 0x04B8
2111+#define mmGPIO_CNTL1 0x04BC
2112+#define mmGPIO_CNTL2 0x04C0
2113+#define mmLCDD_CNTL1 0x04C4
2114+#define mmLCDD_CNTL2 0x04C8
2115+#define mmGENLCD_CNTL1 0x04CC
2116+#define mmGENLCD_CNTL2 0x04D0
2117+#define mmDISP_DEBUG 0x04D4
2118+#define mmDISP_DB_BUF_CNTL 0x04D8
2119+#define mmDISP_CRC_SIG 0x04DC
2120+#define mmCRTC_DEFAULT_COUNT 0x04E0
2121+#define mmLCD_BACKGROUND_COLOR 0x04E4
2122+#define mmCRTC_PS2 0x04E8
2123+#define mmCRTC_PS2_VPOS 0x04EC
2124+#define mmCRTC_PS1_ACTIVE 0x04F0
2125+#define mmCRTC_PS1_NACTIVE 0x04F4
2126+#define mmCRTC_GCLK_EXT 0x04F8
2127+#define mmCRTC_ALW 0x04FC
2128+#define mmCRTC_ALW_VPOS 0x0500
2129+#define mmCRTC_PSK 0x0504
2130+#define mmCRTC_PSK_HPOS 0x0508
2131+#define mmCRTC_CV4_START 0x050C
2132+#define mmCRTC_CV4_END 0x0510
2133+#define mmCRTC_CV4_HPOS 0x0514
2134+#define mmCRTC_ECK 0x051C
2135+#define mmREFRESH_CNTL 0x0520
2136+#define mmGENLCD_CNTL3 0x0524
2137+#define mmGPIO_DATA2 0x0528
2138+#define mmGPIO_CNTL3 0x052C
2139+#define mmGPIO_CNTL4 0x0530
2140+#define mmCHIP_STRAP 0x0534
2141+#define mmDISP_DEBUG2 0x0538
2142+#define mmDEBUG_BUS_CNTL 0x053C
2143+#define mmGAMMA_VALUE1 0x0540
2144+#define mmGAMMA_VALUE2 0x0544
2145+#define mmGAMMA_SLOPE 0x0548
2146+#define mmGEN_STATUS 0x054C
2147+#define mmHW_INT 0x0550
2148+/* Block DISPLAY End: */
2149+
2150+/* Block GFX Start: */
2151+#define mmDST_OFFSET 0x1004
2152+#define mmDST_PITCH 0x1008
2153+#define mmDST_PITCH_OFFSET 0x102C
2154+#define mmDST_X 0x101C
2155+#define mmDST_Y 0x1020
2156+#define mmDST_X_Y 0x1194
2157+#define mmDST_Y_X 0x1038
2158+#define mmDST_WIDTH 0x100C
2159+#define mmDST_HEIGHT 0x1010
2160+#define mmDST_WIDTH_HEIGHT 0x1198
2161+#define mmDST_HEIGHT_WIDTH 0x103C
2162+#define mmDST_HEIGHT_WIDTH_8 0x118C
2163+#define mmDST_HEIGHT_Y 0x11A0
2164+#define mmDST_WIDTH_X 0x1188
2165+#define mmDST_WIDTH_X_INCY 0x119C
2166+#define mmDST_LINE_START 0x1090
2167+#define mmDST_LINE_END 0x1094
2168+#define mmBRUSH_OFFSET 0x108C
2169+#define mmBRUSH_Y_X 0x1074
2170+#define mmDP_BRUSH_FRGD_CLR 0x107C
2171+#define mmDP_BRUSH_BKGD_CLR 0x1078
2172+#define mmSRC2_OFFSET 0x1060
2173+#define mmSRC2_PITCH 0x1064
2174+#define mmSRC2_PITCH_OFFSET 0x1068
2175+#define mmSRC2_X 0x1050
2176+#define mmSRC2_Y 0x1054
2177+#define mmSRC2_X_Y 0x1058
2178+#define mmSRC2_WIDTH 0x1080
2179+#define mmSRC2_HEIGHT 0x1084
2180+#define mmSRC2_INC 0x1088
2181+#define mmSRC_OFFSET 0x11AC
2182+#define mmSRC_PITCH 0x11B0
2183+#define mmSRC_PITCH_OFFSET 0x1028
2184+#define mmSRC_X 0x1014
2185+#define mmSRC_Y 0x1018
2186+#define mmSRC_X_Y 0x1190
2187+#define mmSRC_Y_X 0x1034
2188+#define mmSRC_WIDTH 0x1040
2189+#define mmSRC_HEIGHT 0x1044
2190+#define mmSRC_INC 0x1048
2191+#define mmHOST_DATA0 0x13C0
2192+#define mmHOST_DATA1 0x13C4
2193+#define mmHOST_DATA2 0x13C8
2194+#define mmHOST_DATA3 0x13CC
2195+#define mmHOST_DATA4 0x13D0
2196+#define mmHOST_DATA5 0x13D4
2197+#define mmHOST_DATA6 0x13D8
2198+#define mmHOST_DATA7 0x13DC
2199+#define mmHOST_DATA_LAST 0x13E0
2200+#define mmDP_SRC_FRGD_CLR 0x1240
2201+#define mmDP_SRC_BKGD_CLR 0x1244
2202+#define mmSC_LEFT 0x1140
2203+#define mmSC_RIGHT 0x1144
2204+#define mmSC_TOP 0x1148
2205+#define mmSC_BOTTOM 0x114C
2206+#define mmSRC_SC_RIGHT 0x1154
2207+#define mmSRC_SC_BOTTOM 0x115C
2208+#define mmDP_CNTL 0x11C8
2209+#define mmDP_CNTL_DST_DIR 0x11CC
2210+#define mmDP_DATATYPE 0x12C4
2211+#define mmDP_MIX 0x12C8
2212+#define mmDP_WRITE_MSK 0x12CC
2213+#define mmCLR_CMP_CLR_SRC 0x1234
2214+#define mmCLR_CMP_CLR_DST 0x1238
2215+#define mmCLR_CMP_CNTL 0x1230
2216+#define mmCLR_CMP_MSK 0x123C
2217+#define mmDEFAULT_PITCH_OFFSET 0x10A0
2218+#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
2219+#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
2220+#define mmREF1_PITCH_OFFSET 0x10B8
2221+#define mmREF2_PITCH_OFFSET 0x10BC
2222+#define mmREF3_PITCH_OFFSET 0x10C0
2223+#define mmREF4_PITCH_OFFSET 0x10C4
2224+#define mmREF5_PITCH_OFFSET 0x10C8
2225+#define mmREF6_PITCH_OFFSET 0x10CC
2226+#define mmDP_GUI_MASTER_CNTL 0x106C
2227+#define mmSC_TOP_LEFT 0x11BC
2228+#define mmSC_BOTTOM_RIGHT 0x11C0
2229+#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
2230+#define mmGLOBAL_ALPHA 0x1210
2231+#define mmFILTER_COEF 0x1214
2232+#define mmMVC_CNTL_START 0x11E0
2233+#define mmE2_ARITHMETIC_CNTL 0x1220
2234+#define mmDEBUG0 0x1280
2235+#define mmDEBUG1 0x1284
2236+#define mmDEBUG2 0x1288
2237+#define mmDEBUG3 0x128C
2238+#define mmDEBUG4 0x1290
2239+#define mmDEBUG5 0x1294
2240+#define mmDEBUG6 0x1298
2241+#define mmDEBUG7 0x129C
2242+#define mmDEBUG8 0x12A0
2243+#define mmDEBUG9 0x12A4
2244+#define mmDEBUG10 0x12A8
2245+#define mmDEBUG11 0x12AC
2246+#define mmDEBUG12 0x12B0
2247+#define mmDEBUG13 0x12B4
2248+#define mmDEBUG14 0x12B8
2249+#define mmDEBUG15 0x12BC
2250+#define mmENG_CNTL 0x13E8
2251+#define mmENG_PERF_CNT 0x13F0
2252+/* Block GFX End: */
2253+
2254+/* Block IDCT Start: */
2255+#define mmIDCT_RUNS 0x0C00
2256+#define mmIDCT_LEVELS 0x0C04
2257+#define mmIDCT_CONTROL 0x0C3C
2258+#define mmIDCT_AUTH_CONTROL 0x0C08
2259+#define mmIDCT_AUTH 0x0C0C
2260+/* Block IDCT End: */
2261+
2262+/* Block MC Start: */
2263+#define mmMEM_CNTL 0x0180
2264+#define mmMEM_ARB 0x0184
2265+#define mmMC_FB_LOCATION 0x0188
2266+#define mmMEM_EXT_CNTL 0x018C
2267+#define mmMC_EXT_MEM_LOCATION 0x0190
2268+#define mmMEM_EXT_TIMING_CNTL 0x0194
2269+#define mmMEM_SDRAM_MODE_REG 0x0198
2270+#define mmMEM_IO_CNTL 0x019C
2271+#define mmMC_DEBUG 0x01A0
2272+#define mmMC_BIST_CTRL 0x01A4
2273+#define mmMC_BIST_COLLAR_READ 0x01A8
2274+#define mmTC_MISMATCH 0x01AC
2275+#define mmMC_PERF_MON_CNTL 0x01B0
2276+#define mmMC_PERF_COUNTERS 0x01B4
2277+/* Block MC End: */
2278+
2279+/* Block RBBM Start: */
2280+#define mmWAIT_UNTIL 0x1400
2281+#define mmISYNC_CNTL 0x1404
2282+#define mmRBBM_GUICNTL 0x1408
2283+#define mmRBBM_STATUS 0x0140
2284+#define mmRBBM_STATUS_alt_1 0x140C
2285+#define mmRBBM_CNTL 0x0144
2286+#define mmRBBM_SOFT_RESET 0x0148
2287+#define mmNQWAIT_UNTIL 0x0150
2288+#define mmRBBM_DEBUG 0x016C
2289+#define mmRBBM_CMDFIFO_ADDR 0x0170
2290+#define mmRBBM_CMDFIFO_DATAL 0x0174
2291+#define mmRBBM_CMDFIFO_DATAH 0x0178
2292+#define mmRBBM_CMDFIFO_STAT 0x017C
2293+/* Block RBBM End: */
2294+
2295+/* Block CG Start: */
2296+#define mmCLK_PIN_CNTL 0x0080
2297+#define mmPLL_REF_FB_DIV 0x0084
2298+#define mmPLL_CNTL 0x0088
2299+#define mmSCLK_CNTL 0x008C
2300+#define mmPCLK_CNTL 0x0090
2301+#define mmCLK_TEST_CNTL 0x0094
2302+#define mmPWRMGT_CNTL 0x0098
2303+#define mmPWRMGT_STATUS 0x009C
2304+/* Block CG End: */
2305+
2306+/* default value definitions */
2307+#define defCHIP_ID 0x00001002
2308+#define defREVISION_ID 0x00000000
2309+#define defWRAP_BUF_A 0x01000000
2310+#define defWRAP_BUF_B 0x01000000
2311+#define defWRAP_TOP_DIR 0x00000000
2312+#define defWRAP_START_DIR 0x00000000
2313+//#define defCIF_CNTL 0x00082900
2314+#define defCIF_CNTL 0x00182d00 //??updated by Tobey Z.for Sharp,Oct11,2002
2315+#define defCFGREG_BASE 0x00000000
2316+//#define defCIF_IO 0x000c0800
2317+#define defCIF_IO 0x000C0902 //??updated by Tobey Z.for Sharp,Oct11,2002
2318+#define defCIF_READ_DBG 0x00018223
2319+#define defCIF_WRITE_DBG 0x00002100
2320+#define defIND_ADDR_A_0 0x00000000
2321+#define defIND_ADDR_A_1 0x00000000
2322+#define defIND_ADDR_A_2 0x00000000
2323+#define defIND_DATA_A 0x00000000
2324+#define defREG_BASE 0x00000001
2325+#define defINTF_CNTL 0x00000011
2326+#define defSTATUS 0x00000000
2327+#define defCPU_DEFAULTS 0x00000006
2328+#define defIND_ADDR_B_0 0x00000000
2329+#define defIND_ADDR_B_1 0x00000000
2330+#define defIND_ADDR_B_2 0x00000000
2331+#define defIND_DATA_B 0x00000000
2332+#define defPM4_RPTR 0x00000000
2333+#define defSCRATCH 0x00000000
2334+#define defPM4_WRPTR_0 0x00000000
2335+#define defPM4_WRPTR_1 0x00000000
2336+#define defCP_RB_CNTL 0x00000000
2337+#define defCP_RB_BASE 0x00000000
2338+#define defCP_RB_RPTR_ADDR 0x00000000
2339+#define defCP_RB_RPTR 0x00000000
2340+#define defCP_RB_RPTR_WR 0x00000000
2341+#define defCP_RB_WPTR 0x00000000
2342+#define defCP_IB_BASE 0x00000000
2343+#define defCP_IB_BUFSZ 0x00000000
2344+#define defCP_CSQ_CNTL 0x00000000
2345+#define defCP_CSQ_APER_PRIMARY 0x00000000
2346+#define defCP_CSQ_APER_INDIRECT 0x00000000
2347+#define defCP_ME_CNTL 0x40000000
2348+#define defCP_ME_RAM_ADDR 0x00000000
2349+#define defCP_ME_RAM_RADDR 0x00000000
2350+#define defCP_ME_RAM_DATAH 0x00000000
2351+#define defCP_ME_RAM_DATAL 0x00000000
2352+#define defCP_DEBUG 0x00000000
2353+#define defSCRATCH_REG0 0x00000000
2354+#define defSCRATCH_REG1 0x00000000
2355+#define defSCRATCH_REG2 0x00000000
2356+#define defSCRATCH_REG3 0x00000000
2357+#define defSCRATCH_REG4 0x00000000
2358+#define defSCRATCH_REG5 0x00000000
2359+#define defSCRATCH_UMSK 0x00000000
2360+#define defSCRATCH_ADDR 0x00000000
2361+#define defCP_CSQ_ADDR 0x00000000
2362+#define defCP_CSQ_DATA 0x00000000
2363+#define defCP_CSQ_STAT 0x00000000
2364+#define defCP_STAT 0x00000000
2365+#define defGEN_INT_CNTL 0x00000000
2366+#define defGEN_INT_STATUS_rd 0x00080000
2367+#define defGEN_INT_STATUS_wr 0x00000000
2368+#define defLCD_FORMAT 0x00000000
2369+#define defGRAPHIC_CTRL 0x00000000
2370+#define defGRAPHIC_OFFSET 0x00000000
2371+#define defGRAPHIC_PITCH 0x00000000
2372+#define defCRTC_TOTAL 0x00000000
2373+#define defACTIVE_H_DISP 0x00000000
2374+#define defACTIVE_V_DISP 0x00000000
2375+#define defGRAPHIC_H_DISP 0x00000000
2376+#define defGRAPHIC_V_DISP 0x00000000
2377+#define defVIDEO_CTRL 0x00000000
2378+#define defGRAPHIC_KEY 0x00000000
2379+#define defVIDEO_Y_OFFSET 0x00000000
2380+#define defVIDEO_Y_PITCH 0x00000000
2381+#define defVIDEO_U_OFFSET 0x00000000
2382+#define defVIDEO_U_PITCH 0x00000000
2383+#define defVIDEO_V_OFFSET 0x00000000
2384+#define defVIDEO_V_PITCH 0x00000000
2385+#define defVIDEO_H_POS 0x00000000
2386+#define defVIDEO_V_POS 0x00000000
2387+#define defBRIGHTNESS_CNTL 0x00000000
2388+#define defCURSOR1_OFFSET 0x00000000
2389+#define defCURSOR1_H_POS 0x00000000
2390+#define defCURSOR1_V_POS 0x00000000
2391+#define defCURSOR1_COLOR0 0x00000000
2392+#define defCURSOR1_COLOR1 0x00000000
2393+#define defCURSOR2_OFFSET 0x00000000
2394+#define defCURSOR2_H_POS 0x00000000
2395+#define defCURSOR2_V_POS 0x00000000
2396+#define defCURSOR2_COLOR0 0x00000000
2397+#define defCURSOR2_COLOR1 0x00000000
2398+#define defDISP_INT_CNTL 0x00000000
2399+#define defCRTC_SS 0x00000000
2400+#define defCRTC_LS 0x00000000
2401+#define defCRTC_REV 0x00000000
2402+#define defCRTC_DCLK 0x00000000
2403+#define defCRTC_GS 0x00000000
2404+#define defCRTC_VPOS_GS 0x00000000
2405+#define defCRTC_GCLK 0x00000000
2406+#define defCRTC_GOE 0x00000000
2407+#define defCRTC_FRAME 0x00000000
2408+#define defCRTC_FRAME_VPOS 0x00000000
2409+#define defGPIO_DATA 0x00000000
2410+#define defGPIO_CNTL1 0xff00ff00
2411+#define defGPIO_CNTL2 0x00000000
2412+#define defLCDD_CNTL1 0x0000ffff
2413+#define defLCDD_CNTL2 0x00000000
2414+#define defGENLCD_CNTL1 0x00aaa002
2415+#define defGENLCD_CNTL2 0x00000002
2416+#define defDISP_DEBUG 0x00000000
2417+#define defDISP_DB_BUF_CNTL_rd 0x00000000
2418+#define defDISP_DB_BUF_CNTL_wr 0x00000000
2419+#define defDISP_CRC_SIG 0x00000000
2420+#define defCRTC_DEFAULT_COUNT 0x00000000
2421+#define defLCD_BACKGROUND_COLOR 0x00000000
2422+#define defCRTC_PS2 0x00000000
2423+#define defCRTC_PS2_VPOS 0x00000000
2424+#define defCRTC_PS1_ACTIVE 0x00000000
2425+#define defCRTC_PS1_NACTIVE 0x00000000
2426+#define defCRTC_GCLK_EXT 0x00000000
2427+#define defCRTC_ALW 0x00000000
2428+#define defCRTC_ALW_VPOS 0x00000000
2429+#define defCRTC_PSK 0x00000000
2430+#define defCRTC_PSK_HPOS 0x00000000
2431+#define defCRTC_CV4_START 0x00000000
2432+#define defCRTC_CV4_END 0x00000000
2433+#define defCRTC_CV4_HPOS 0x00000000
2434+#define defCRTC_ECK 0x00000000
2435+#define defREFRESH_CNTL 0x00000000
2436+#define defGENLCD_CNTL3 0x000002aa
2437+#define defGPIO_DATA2 0x00000000
2438+#define defGPIO_CNTL3 0x00000000
2439+#define defGPIO_CNTL4 0x00000000
2440+#define defCHIP_STRAP 0x00000000
2441+#define defDISP_DEBUG2 0x00000000
2442+#define defDEBUG_BUS_CNTL 0x00000000
2443+#define defGAMMA_VALUE1 0x00000000
2444+#define defGAMMA_VALUE2 0x00000000
2445+#define defGAMMA_SLOPE 0x00000000
2446+#define defGEN_STATUS 0x00000000
2447+#define defHW_INT 0x00000000
2448+#define defDST_OFFSET 0x00000000
2449+#define defDST_PITCH 0x00000000
2450+#define defDST_PITCH_OFFSET 0x00000000
2451+#define defDST_X 0x00000000
2452+#define defDST_Y 0x00000000
2453+#define defDST_X_Y 0x00000000
2454+#define defDST_Y_X 0x00000000
2455+#define defDST_WIDTH 0x00000000
2456+#define defDST_HEIGHT 0x00000000
2457+#define defDST_WIDTH_HEIGHT 0x00000000
2458+#define defDST_HEIGHT_WIDTH 0x00000000
2459+#define defDST_HEIGHT_WIDTH_8 0x00000000
2460+#define defDST_HEIGHT_Y 0x00000000
2461+#define defDST_WIDTH_X 0x00000000
2462+#define defDST_WIDTH_X_INCY 0x00000000
2463+#define defDST_LINE_START 0x00000000
2464+#define defDST_LINE_END 0x00000000
2465+#define defBRUSH_OFFSET 0x00000000
2466+#define defBRUSH_Y_X 0x00000000
2467+#define defDP_BRUSH_FRGD_CLR 0x00000000
2468+#define defDP_BRUSH_BKGD_CLR 0x00000000
2469+#define defSRC2_OFFSET 0x00000000
2470+#define defSRC2_PITCH 0x00000000
2471+#define defSRC2_PITCH_OFFSET 0x00000000
2472+#define defSRC2_X 0x00000000
2473+#define defSRC2_Y 0x00000000
2474+#define defSRC2_X_Y 0x00000000
2475+#define defSRC2_WIDTH 0x00000000
2476+#define defSRC2_HEIGHT 0x00000000
2477+#define defSRC2_INC 0x00000000
2478+#define defSRC_OFFSET 0x00000000
2479+#define defSRC_PITCH 0x00000000
2480+#define defSRC_PITCH_OFFSET 0x00000000
2481+#define defSRC_X 0x00000000
2482+#define defSRC_Y 0x00000000
2483+#define defSRC_X_Y 0x00000000
2484+#define defSRC_Y_X 0x00000000
2485+#define defSRC_WIDTH 0x00000000
2486+#define defSRC_HEIGHT 0x00000000
2487+#define defSRC_INC 0x00000000
2488+#define defHOST_DATA0 0x00000000
2489+#define defHOST_DATA1 0x00000000
2490+#define defHOST_DATA2 0x00000000
2491+#define defHOST_DATA3 0x00000000
2492+#define defHOST_DATA4 0x00000000
2493+#define defHOST_DATA5 0x00000000
2494+#define defHOST_DATA6 0x00000000
2495+#define defHOST_DATA7 0x00000000
2496+#define defHOST_DATA_LAST 0x00000000
2497+#define defDP_SRC_FRGD_CLR 0x00000000
2498+#define defDP_SRC_BKGD_CLR 0x00000000
2499+#define defSC_LEFT 0x00000000
2500+#define defSC_RIGHT 0x00000000
2501+#define defSC_TOP 0x00000000
2502+#define defSC_BOTTOM 0x00000000
2503+#define defSRC_SC_RIGHT 0x00000000
2504+#define defSRC_SC_BOTTOM 0x00000000
2505+#define defDP_CNTL 0x00000000
2506+#define defDP_CNTL_DST_DIR 0x00000000
2507+#define defDP_DATATYPE 0x00000000
2508+#define defDP_MIX 0x00000000
2509+#define defDP_WRITE_MSK 0x00000000
2510+#define defCLR_CMP_CLR_SRC 0x00000000
2511+#define defCLR_CMP_CLR_DST 0x00000000
2512+#define defCLR_CMP_CNTL 0x00000000
2513+#define defCLR_CMP_MSK 0x00000000
2514+#define defDEFAULT_PITCH_OFFSET 0x00000000
2515+#define defDEFAULT_SC_BOTTOM_RIGHT 0x00000000
2516+#define defDEFAULT2_SC_BOTTOM_RIGHT 0x00000000
2517+#define defREF1_PITCH_OFFSET 0x00000000
2518+#define defREF2_PITCH_OFFSET 0x00000000
2519+#define defREF3_PITCH_OFFSET 0x00000000
2520+#define defREF4_PITCH_OFFSET 0x00000000
2521+#define defREF5_PITCH_OFFSET 0x00000000
2522+#define defREF6_PITCH_OFFSET 0x00000000
2523+#define defDP_GUI_MASTER_CNTL 0x00000000
2524+#define defSC_TOP_LEFT 0x00000000
2525+#define defSC_BOTTOM_RIGHT 0x00000000
2526+#define defSRC_SC_BOTTOM_RIGHT 0x00000000
2527+#define defGLOBAL_ALPHA 0x00000000
2528+#define defFILTER_COEF 0x00000000
2529+#define defMVC_CNTL_START 0x00000000
2530+#define defE2_ARITHMETIC_CNTL 0x00000000
2531+#define defDEBUG0 0x00000000
2532+#define defDEBUG1 0x00000000
2533+#define defDEBUG2 0x00000000
2534+#define defDEBUG3 0x00000000
2535+#define defDEBUG4 0x00000000
2536+#define defDEBUG5 0x00000000
2537+#define defDEBUG6 0x00000000
2538+#define defDEBUG7 0x00000000
2539+#define defDEBUG8 0x00000000
2540+#define defDEBUG9 0x00000000
2541+#define defDEBUG10 0x00000000
2542+#define defDEBUG11 0x00000000
2543+#define defDEBUG12 0x00000000
2544+#define defDEBUG13 0x00000000
2545+#define defDEBUG14 0x00000000
2546+#define defDEBUG15 0x00000000
2547+#define defENG_CNTL 0x00000003
2548+#define defENG_PERF_CNT 0x00000000
2549+#define defIDCT_RUNS 0x00000000
2550+#define defIDCT_LEVELS 0x00000000
2551+#define defIDCT_CONTROL 0x00000000
2552+#define defIDCT_AUTH_CONTROL 0x00000000
2553+#define defIDCT_AUTH 0x00000000
2554+#define defMEM_CNTL 0x00000006
2555+#define defMEM_ARB 0x00000000
2556+#define defMC_FB_LOCATION 0x00ff0000
2557+#define defMEM_EXT_CNTL 0x00040010
2558+#define defMC_EXT_MEM_LOCATION 0x07ff0000
2559+#define defMEM_EXT_TIMING_CNTL 0x00140c73
2560+#define defMEM_SDRAM_MODE_REG 0x00050000
2561+#define defMEM_IO_CNTL 0x00ff00ff
2562+#define defMC_DEBUG 0x00000000
2563+#define defMC_BIST_CTRL 0x00000000
2564+#define defMC_BIST_COLLAR_READ 0x00000000
2565+#define defTC_MISMATCH 0x00000000
2566+#define defMC_PERF_MON_CNTL 0x00000000
2567+#define defMC_PERF_COUNTERS 0x00000000
2568+#define defWAIT_UNTIL 0xc5cdcdcd
2569+#define defISYNC_CNTL 0x00000000
2570+#define defRBBM_GUICNTL 0x00000000
2571+#define defRBBM_STATUS 0x81cdcd40
2572+#define defRBBM_CNTL 0x0000000f
2573+#define defRBBM_SOFT_RESET 0x00000000
2574+#define defNQWAIT_UNTIL 0x00000001
2575+#define defRBBM_DEBUG 0x00000000
2576+#define defRBBM_CMDFIFO_ADDR 0x0000000d
2577+#define defRBBM_CMDFIFO_DATAL 0xcdcdcdcd
2578+#define defRBBM_CMDFIFO_DATAH 0x00000dcd
2579+#define defRBBM_CMDFIFO_STAT 0x00000d0d
2580+#define defCLK_PIN_CNTL 0x0000003f
2581+#define defPLL_REF_FB_DIV 0x5a500000
2582+#define defPLL_CNTL 0x4b000203
2583+#define defSCLK_CNTL 0x00ff0300
2584+#define defPCLK_CNTL 0x00010000
2585+#define defCLK_TEST_CNTL 0x00000000
2586+#define defPWRMGT_CNTL 0x00000004
2587+#define defPWRMGT_STATUS 0x00000001
2588+
2589+#define CFG_BASE_BOOT_DEFAULT 0x0
2590+#define CFG_BASE_VALUE 0x0
2591+#define REG_BASE_BOOT_DEFAULT 0x01
2592+#define REG_BASE_VALUE 0x10000
2593+#define MEM_INT_BASE_VALUE 0x100000
2594+#define MEM_INT_TOP_VALUE_W100 0x15ffff
2595+#define MEM_EXT_BASE_VALUE 0x800000
2596+#define MEM_EXT_TOP_VALUE 0x9fffff
2597+#define WRAP_BUF_BASE_VALUE 0x80000
2598+#define WRAP_BUF_TOP_VALUE 0xbffff
2599+
2600+
2601+/* data structure definitions */
2602+
2603+typedef struct _chip_id_t {
2604+ unsigned long vendor_id : 16;
2605+ unsigned long device_id : 16;
2606+ } chip_id_t;
2607+
2608+typedef union {
2609+ unsigned long val : 32;
2610+ chip_id_t f;
2611+} chip_id_u;
2612+
2613+typedef struct _revision_id_t {
2614+ unsigned long minor_rev_id : 4;
2615+ unsigned long major_rev_id : 4;
2616+ unsigned long : 24;
2617+ } revision_id_t;
2618+
2619+typedef union {
2620+ unsigned long val : 32;
2621+ revision_id_t f;
2622+} revision_id_u;
2623+
2624+typedef struct _wrap_buf_a_t {
2625+ unsigned long offset_addr_a : 24;
2626+ unsigned long block_size_a : 3;
2627+ unsigned long : 5;
2628+ } wrap_buf_a_t;
2629+
2630+typedef union {
2631+ unsigned long val : 32;
2632+ wrap_buf_a_t f;
2633+} wrap_buf_a_u;
2634+
2635+typedef struct _wrap_buf_b_t {
2636+ unsigned long offset_addr_b : 24;
2637+ unsigned long block_size_b : 3;
2638+ unsigned long : 5;
2639+ } wrap_buf_b_t;
2640+
2641+typedef union {
2642+ unsigned long val : 32;
2643+ wrap_buf_b_t f;
2644+} wrap_buf_b_u;
2645+
2646+typedef struct _wrap_top_dir_t {
2647+ unsigned long top_addr : 23;
2648+ unsigned long : 9;
2649+ } wrap_top_dir_t;
2650+
2651+typedef union {
2652+ unsigned long val : 32;
2653+ wrap_top_dir_t f;
2654+} wrap_top_dir_u;
2655+
2656+typedef struct _wrap_start_dir_t {
2657+ unsigned long start_addr : 23;
2658+ unsigned long : 9;
2659+ } wrap_start_dir_t;
2660+
2661+typedef union {
2662+ unsigned long val : 32;
2663+ wrap_start_dir_t f;
2664+} wrap_start_dir_u;
2665+
2666+typedef struct _cif_cntl_t {
2667+ unsigned long swap_reg : 2;
2668+ unsigned long swap_fbuf_1 : 2;
2669+ unsigned long swap_fbuf_2 : 2;
2670+ unsigned long swap_fbuf_3 : 2;
2671+ unsigned long pmi_int_disable : 1;
2672+ unsigned long pmi_schmen_disable : 1;
2673+ unsigned long intb_oe : 1;
2674+ unsigned long en_wait_to_compensate_dq_prop_dly : 1;
2675+ unsigned long compensate_wait_rd_size : 2;
2676+ unsigned long wait_asserted_timeout_val : 2;
2677+ unsigned long wait_masked_val : 2;
2678+ unsigned long en_wait_timeout : 1;
2679+ unsigned long en_one_clk_setup_before_wait : 1;
2680+ unsigned long interrupt_active_high : 1;
2681+ unsigned long en_overwrite_straps : 1;
2682+ unsigned long strap_wait_active_hi : 1;
2683+ unsigned long lat_busy_count : 2;
2684+ unsigned long lat_rd_pm4_sclk_busy : 1;
2685+ unsigned long dis_system_bits : 1;
2686+ unsigned long dis_mr : 1;
2687+ unsigned long cif_spare_1 : 4;
2688+ } cif_cntl_t;
2689+
2690+typedef union {
2691+ unsigned long val : 32;
2692+ cif_cntl_t f;
2693+} cif_cntl_u;
2694+
2695+typedef struct _cfgreg_base_t {
2696+ unsigned long cfgreg_base : 24;
2697+ unsigned long : 8;
2698+ } cfgreg_base_t;
2699+
2700+typedef union {
2701+ unsigned long val : 32;
2702+ cfgreg_base_t f;
2703+} cfgreg_base_u;
2704+
2705+typedef struct _cif_io_t {
2706+ unsigned long dq_srp : 1;
2707+ unsigned long dq_srn : 1;
2708+ unsigned long dq_sp : 4;
2709+ unsigned long dq_sn : 4;
2710+ unsigned long waitb_srp : 1;
2711+ unsigned long waitb_srn : 1;
2712+ unsigned long waitb_sp : 4;
2713+ unsigned long waitb_sn : 4;
2714+ unsigned long intb_srp : 1;
2715+ unsigned long intb_srn : 1;
2716+ unsigned long intb_sp : 4;
2717+ unsigned long intb_sn : 4;
2718+ unsigned long : 2;
2719+ } cif_io_t;
2720+
2721+typedef union {
2722+ unsigned long val : 32;
2723+ cif_io_t f;
2724+} cif_io_u;
2725+
2726+typedef struct _cif_read_dbg_t {
2727+ unsigned long unpacker_pre_fetch_trig_gen : 2;
2728+ unsigned long dly_second_rd_fetch_trig : 1;
2729+ unsigned long rst_rd_burst_id : 1;
2730+ unsigned long dis_rd_burst_id : 1;
2731+ unsigned long en_block_rd_when_packer_is_not_emp : 1;
2732+ unsigned long dis_pre_fetch_cntl_sm : 1;
2733+ unsigned long rbbm_chrncy_dis : 1;
2734+ unsigned long rbbm_rd_after_wr_lat : 2;
2735+ unsigned long dis_be_during_rd : 1;
2736+ unsigned long one_clk_invalidate_pulse : 1;
2737+ unsigned long dis_chnl_priority : 1;
2738+ unsigned long rst_read_path_a_pls : 1;
2739+ unsigned long rst_read_path_b_pls : 1;
2740+ unsigned long dis_reg_rd_fetch_trig : 1;
2741+ unsigned long dis_rd_fetch_trig_from_ind_addr : 1;
2742+ unsigned long dis_rd_same_byte_to_trig_fetch : 1;
2743+ unsigned long dis_dir_wrap : 1;
2744+ unsigned long dis_ring_buf_to_force_dec : 1;
2745+ unsigned long dis_addr_comp_in_16bit : 1;
2746+ unsigned long clr_w : 1;
2747+ unsigned long err_rd_tag_is_3 : 1;
2748+ unsigned long err_load_when_ful_a : 1;
2749+ unsigned long err_load_when_ful_b : 1;
2750+ unsigned long : 7;
2751+ } cif_read_dbg_t;
2752+
2753+typedef union {
2754+ unsigned long val : 32;
2755+ cif_read_dbg_t f;
2756+} cif_read_dbg_u;
2757+
2758+typedef struct _cif_write_dbg_t {
2759+ unsigned long packer_timeout_count : 2;
2760+ unsigned long en_upper_load_cond : 1;
2761+ unsigned long en_chnl_change_cond : 1;
2762+ unsigned long dis_addr_comp_cond : 1;
2763+ unsigned long dis_load_same_byte_addr_cond : 1;
2764+ unsigned long dis_timeout_cond : 1;
2765+ unsigned long dis_timeout_during_rbbm : 1;
2766+ unsigned long dis_packer_ful_during_rbbm_timeout : 1;
2767+ unsigned long en_dword_split_to_rbbm : 1;
2768+ unsigned long en_dummy_val : 1;
2769+ unsigned long dummy_val_sel : 1;
2770+ unsigned long mask_pm4_wrptr_dec : 1;
2771+ unsigned long dis_mc_clean_cond : 1;
2772+ unsigned long err_two_reqi_during_ful : 1;
2773+ unsigned long err_reqi_during_idle_clk : 1;
2774+ unsigned long err_global : 1;
2775+ unsigned long en_wr_buf_dbg_load : 1;
2776+ unsigned long en_wr_buf_dbg_path : 1;
2777+ unsigned long sel_wr_buf_byte : 3;
2778+ unsigned long dis_rd_flush_wr : 1;
2779+ unsigned long dis_packer_ful_cond : 1;
2780+ unsigned long dis_invalidate_by_ops_chnl : 1;
2781+ unsigned long en_halt_when_reqi_err : 1;
2782+ unsigned long cif_spare_2 : 5;
2783+ unsigned long : 1;
2784+ } cif_write_dbg_t;
2785+
2786+typedef union {
2787+ unsigned long val : 32;
2788+ cif_write_dbg_t f;
2789+} cif_write_dbg_u;
2790+
2791+typedef struct _ind_addr_a_0_t {
2792+ unsigned char ind_addr_a_0 : 8;
2793+ } ind_addr_a_0_t;
2794+
2795+typedef union {
2796+ unsigned char val : 8;
2797+ ind_addr_a_0_t f;
2798+} ind_addr_a_0_u;
2799+
2800+typedef struct _ind_addr_a_1_t {
2801+ unsigned char ind_addr_a_1 : 8;
2802+ } ind_addr_a_1_t;
2803+
2804+typedef union {
2805+ unsigned char val : 8;
2806+ ind_addr_a_1_t f;
2807+} ind_addr_a_1_u;
2808+
2809+typedef struct _ind_addr_a_2_t {
2810+ unsigned char ind_addr_a_2 : 8;
2811+ } ind_addr_a_2_t;
2812+
2813+typedef union {
2814+ unsigned char val : 8;
2815+ ind_addr_a_2_t f;
2816+} ind_addr_a_2_u;
2817+
2818+typedef struct _ind_data_a_t {
2819+ unsigned char ind_data_a : 8;
2820+ } ind_data_a_t;
2821+
2822+typedef union {
2823+ unsigned char val : 8;
2824+ ind_data_a_t f;
2825+} ind_data_a_u;
2826+
2827+typedef struct _reg_base_t {
2828+ unsigned char reg_base : 8;
2829+ } reg_base_t;
2830+
2831+typedef union {
2832+ unsigned char val : 8;
2833+ reg_base_t f;
2834+} reg_base_u;
2835+
2836+typedef struct _intf_cntl_t {
2837+ unsigned char ad_inc_a : 1;
2838+ unsigned char ring_buf_a : 1;
2839+ unsigned char rd_fetch_trigger_a : 1;
2840+ unsigned char rd_data_rdy_a : 1;
2841+ unsigned char ad_inc_b : 1;
2842+ unsigned char ring_buf_b : 1;
2843+ unsigned char rd_fetch_trigger_b : 1;
2844+ unsigned char rd_data_rdy_b : 1;
2845+ } intf_cntl_t;
2846+
2847+typedef union {
2848+ unsigned char val : 8;
2849+ intf_cntl_t f;
2850+} intf_cntl_u;
2851+
2852+typedef struct _status_t {
2853+ unsigned char wr_fifo_available_space : 2;
2854+ unsigned char fbuf_wr_pipe_emp : 1;
2855+ unsigned char soft_reset : 1;
2856+ unsigned char system_pwm_mode : 2;
2857+ unsigned char mem_access_dis : 1;
2858+ unsigned char en_pre_fetch : 1;
2859+ } status_t;
2860+
2861+typedef union {
2862+ unsigned char val : 8;
2863+ status_t f;
2864+} status_u;
2865+
2866+typedef struct _cpu_defaults_t {
2867+ unsigned char unpack_rd_data : 1;
2868+ unsigned char access_ind_addr_a : 1;
2869+ unsigned char access_ind_addr_b : 1;
2870+ unsigned char access_scratch_reg : 1;
2871+ unsigned char pack_wr_data : 1;
2872+ unsigned char transition_size : 1;
2873+ unsigned char en_read_buf_mode : 1;
2874+ unsigned char rd_fetch_scratch : 1;
2875+ } cpu_defaults_t;
2876+
2877+typedef union {
2878+ unsigned char val : 8;
2879+ cpu_defaults_t f;
2880+} cpu_defaults_u;
2881+
2882+typedef struct _ind_addr_b_0_t {
2883+ unsigned char ind_addr_b_0 : 8;
2884+ } ind_addr_b_0_t;
2885+
2886+typedef union {
2887+ unsigned char val : 8;
2888+ ind_addr_b_0_t f;
2889+} ind_addr_b_0_u;
2890+
2891+typedef struct _ind_addr_b_1_t {
2892+ unsigned char ind_addr_b_1 : 8;
2893+ } ind_addr_b_1_t;
2894+
2895+typedef union {
2896+ unsigned char val : 8;
2897+ ind_addr_b_1_t f;
2898+} ind_addr_b_1_u;
2899+
2900+typedef struct _ind_addr_b_2_t {
2901+ unsigned char ind_addr_b_2 : 8;
2902+ } ind_addr_b_2_t;
2903+
2904+typedef union {
2905+ unsigned char val : 8;
2906+ ind_addr_b_2_t f;
2907+} ind_addr_b_2_u;
2908+
2909+typedef struct _ind_data_b_t {
2910+ unsigned char ind_data_b : 8;
2911+ } ind_data_b_t;
2912+
2913+typedef union {
2914+ unsigned char val : 8;
2915+ ind_data_b_t f;
2916+} ind_data_b_u;
2917+
2918+typedef struct _pm4_rptr_t {
2919+ unsigned char pm4_rptr : 8;
2920+ } pm4_rptr_t;
2921+
2922+typedef union {
2923+ unsigned char val : 8;
2924+ pm4_rptr_t f;
2925+} pm4_rptr_u;
2926+
2927+typedef struct _scratch_t {
2928+ unsigned char scratch : 8;
2929+ } scratch_t;
2930+
2931+typedef union {
2932+ unsigned char val : 8;
2933+ scratch_t f;
2934+} scratch_u;
2935+
2936+typedef struct _pm4_wrptr_0_t {
2937+ unsigned char pm4_wrptr_0 : 8;
2938+ } pm4_wrptr_0_t;
2939+
2940+typedef union {
2941+ unsigned char val : 8;
2942+ pm4_wrptr_0_t f;
2943+} pm4_wrptr_0_u;
2944+
2945+typedef struct _pm4_wrptr_1_t {
2946+ unsigned char pm4_wrptr_1 : 6;
2947+ unsigned char rd_fetch_pm4_rptr : 1;
2948+ unsigned char wrptr_atomic_update_w : 1;
2949+ } pm4_wrptr_1_t;
2950+
2951+typedef union {
2952+ unsigned char val : 8;
2953+ pm4_wrptr_1_t f;
2954+} pm4_wrptr_1_u;
2955+
2956+typedef struct _cp_rb_cntl_t {
2957+ unsigned long rb_bufsz : 6;
2958+ unsigned long : 2;
2959+ unsigned long rb_blksz : 6;
2960+ unsigned long : 2;
2961+ unsigned long buf_swap : 2;
2962+ unsigned long max_fetch : 2;
2963+ unsigned long : 7;
2964+ unsigned long rb_no_update : 1;
2965+ unsigned long : 3;
2966+ unsigned long rb_rptr_wr_ena : 1;
2967+ } cp_rb_cntl_t;
2968+
2969+typedef union {
2970+ unsigned long val : 32;
2971+ cp_rb_cntl_t f;
2972+} cp_rb_cntl_u;
2973+
2974+typedef struct _cp_rb_base_t {
2975+ unsigned long : 2;
2976+ unsigned long rb_base : 22;
2977+ unsigned long : 8;
2978+ } cp_rb_base_t;
2979+
2980+typedef union {
2981+ unsigned long val : 32;
2982+ cp_rb_base_t f;
2983+} cp_rb_base_u;
2984+
2985+typedef struct _cp_rb_rptr_addr_t {
2986+ unsigned long rb_rptr_swap : 2;
2987+ unsigned long rb_rptr_addr : 22;
2988+ unsigned long : 8;
2989+ } cp_rb_rptr_addr_t;
2990+
2991+typedef union {
2992+ unsigned long val : 32;
2993+ cp_rb_rptr_addr_t f;
2994+} cp_rb_rptr_addr_u;
2995+
2996+typedef struct _cp_rb_rptr_t {
2997+ unsigned long rb_rptr : 23;
2998+ unsigned long : 9;
2999+ } cp_rb_rptr_t;
3000+
3001+typedef union {
3002+ unsigned long val : 32;
3003+ cp_rb_rptr_t f;
3004+} cp_rb_rptr_u;
3005+
3006+typedef struct _cp_rb_rptr_wr_t {
3007+ unsigned long rb_rptr_wr : 23;
3008+ unsigned long : 9;
3009+ } cp_rb_rptr_wr_t;
3010+
3011+typedef union {
3012+ unsigned long val : 32;
3013+ cp_rb_rptr_wr_t f;
3014+} cp_rb_rptr_wr_u;
3015+
3016+typedef struct _cp_rb_wptr_t {
3017+ unsigned long rb_wptr : 23;
3018+ unsigned long : 9;
3019+ } cp_rb_wptr_t;
3020+
3021+typedef union {
3022+ unsigned long val : 32;
3023+ cp_rb_wptr_t f;
3024+} cp_rb_wptr_u;
3025+
3026+typedef struct _cp_ib_base_t {
3027+ unsigned long : 2;
3028+ unsigned long ib_base : 22;
3029+ unsigned long : 8;
3030+ } cp_ib_base_t;
3031+
3032+typedef union {
3033+ unsigned long val : 32;
3034+ cp_ib_base_t f;
3035+} cp_ib_base_u;
3036+
3037+typedef struct _cp_ib_bufsz_t {
3038+ unsigned long ib_bufsz : 23;
3039+ unsigned long : 9;
3040+ } cp_ib_bufsz_t;
3041+
3042+typedef union {
3043+ unsigned long val : 32;
3044+ cp_ib_bufsz_t f;
3045+} cp_ib_bufsz_u;
3046+
3047+typedef struct _cp_csq_cntl_t {
3048+ unsigned long csq_cnt_primary : 8;
3049+ unsigned long csq_cnt_indirect : 8;
3050+ unsigned long : 12;
3051+ unsigned long csq_mode : 4;
3052+ } cp_csq_cntl_t;
3053+
3054+typedef union {
3055+ unsigned long val : 32;
3056+ cp_csq_cntl_t f;
3057+} cp_csq_cntl_u;
3058+
3059+typedef struct _cp_csq_aper_primary_t {
3060+ unsigned long cp_csq_aper_primary : 32;
3061+ } cp_csq_aper_primary_t;
3062+
3063+typedef union {
3064+ unsigned long val : 32;
3065+ cp_csq_aper_primary_t f;
3066+} cp_csq_aper_primary_u;
3067+
3068+typedef struct _cp_csq_aper_indirect_t {
3069+ unsigned long cp_csq_aper_indirect : 32;
3070+ } cp_csq_aper_indirect_t;
3071+
3072+typedef union {
3073+ unsigned long val : 32;
3074+ cp_csq_aper_indirect_t f;
3075+} cp_csq_aper_indirect_u;
3076+
3077+typedef struct _cp_me_cntl_t {
3078+ unsigned long me_stat : 16;
3079+ unsigned long me_statmux : 5;
3080+ unsigned long : 8;
3081+ unsigned long me_busy : 1;
3082+ unsigned long me_mode : 1;
3083+ unsigned long me_step : 1;
3084+ } cp_me_cntl_t;
3085+
3086+typedef union {
3087+ unsigned long val : 32;
3088+ cp_me_cntl_t f;
3089+} cp_me_cntl_u;
3090+
3091+typedef struct _cp_me_ram_addr_t {
3092+ unsigned long me_ram_addr : 8;
3093+ unsigned long : 24;
3094+ } cp_me_ram_addr_t;
3095+
3096+typedef union {
3097+ unsigned long val : 32;
3098+ cp_me_ram_addr_t f;
3099+} cp_me_ram_addr_u;
3100+
3101+typedef struct _cp_me_ram_raddr_t {
3102+ unsigned long me_ram_raddr : 8;
3103+ unsigned long : 24;
3104+ } cp_me_ram_raddr_t;
3105+
3106+typedef union {
3107+ unsigned long val : 32;
3108+ cp_me_ram_raddr_t f;
3109+} cp_me_ram_raddr_u;
3110+
3111+typedef struct _cp_me_ram_datah_t {
3112+ unsigned long me_ram_datah : 6;
3113+ unsigned long : 26;
3114+ } cp_me_ram_datah_t;
3115+
3116+typedef union {
3117+ unsigned long val : 32;
3118+ cp_me_ram_datah_t f;
3119+} cp_me_ram_datah_u;
3120+
3121+typedef struct _cp_me_ram_datal_t {
3122+ unsigned long me_ram_datal : 32;
3123+ } cp_me_ram_datal_t;
3124+
3125+typedef union {
3126+ unsigned long val : 32;
3127+ cp_me_ram_datal_t f;
3128+} cp_me_ram_datal_u;
3129+
3130+typedef struct _cp_debug_t {
3131+ unsigned long cp_debug : 32;
3132+ } cp_debug_t;
3133+
3134+typedef union {
3135+ unsigned long val : 32;
3136+ cp_debug_t f;
3137+} cp_debug_u;
3138+
3139+typedef struct _scratch_reg0_t {
3140+ unsigned long scratch_reg0 : 32;
3141+ } scratch_reg0_t;
3142+
3143+typedef union {
3144+ unsigned long val : 32;
3145+ scratch_reg0_t f;
3146+} scratch_reg0_u;
3147+
3148+typedef struct _scratch_reg1_t {
3149+ unsigned long scratch_reg1 : 32;
3150+ } scratch_reg1_t;
3151+
3152+typedef union {
3153+ unsigned long val : 32;
3154+ scratch_reg1_t f;
3155+} scratch_reg1_u;
3156+
3157+typedef struct _scratch_reg2_t {
3158+ unsigned long scratch_reg2 : 32;
3159+ } scratch_reg2_t;
3160+
3161+typedef union {
3162+ unsigned long val : 32;
3163+ scratch_reg2_t f;
3164+} scratch_reg2_u;
3165+
3166+typedef struct _scratch_reg3_t {
3167+ unsigned long scratch_reg3 : 32;
3168+ } scratch_reg3_t;
3169+
3170+typedef union {
3171+ unsigned long val : 32;
3172+ scratch_reg3_t f;
3173+} scratch_reg3_u;
3174+
3175+typedef struct _scratch_reg4_t {
3176+ unsigned long scratch_reg4 : 32;
3177+ } scratch_reg4_t;
3178+
3179+typedef union {
3180+ unsigned long val : 32;
3181+ scratch_reg4_t f;
3182+} scratch_reg4_u;
3183+
3184+typedef struct _scratch_reg5_t {
3185+ unsigned long scratch_reg5 : 32;
3186+ } scratch_reg5_t;
3187+
3188+typedef union {
3189+ unsigned long val : 32;
3190+ scratch_reg5_t f;
3191+} scratch_reg5_u;
3192+
3193+typedef struct _scratch_umsk_t {
3194+ unsigned long scratch_umsk : 6;
3195+ unsigned long : 10;
3196+ unsigned long scratch_swap : 2;
3197+ unsigned long : 14;
3198+ } scratch_umsk_t;
3199+
3200+typedef union {
3201+ unsigned long val : 32;
3202+ scratch_umsk_t f;
3203+} scratch_umsk_u;
3204+
3205+typedef struct _scratch_addr_t {
3206+ unsigned long : 5;
3207+ unsigned long scratch_addr : 27;
3208+ } scratch_addr_t;
3209+
3210+typedef union {
3211+ unsigned long val : 32;
3212+ scratch_addr_t f;
3213+} scratch_addr_u;
3214+
3215+typedef struct _cp_csq_addr_t {
3216+ unsigned long : 2;
3217+ unsigned long csq_addr : 8;
3218+ unsigned long : 22;
3219+ } cp_csq_addr_t;
3220+
3221+typedef union {
3222+ unsigned long val : 32;
3223+ cp_csq_addr_t f;
3224+} cp_csq_addr_u;
3225+
3226+typedef struct _cp_csq_data_t {
3227+ unsigned long csq_data : 32;
3228+ } cp_csq_data_t;
3229+
3230+typedef union {
3231+ unsigned long val : 32;
3232+ cp_csq_data_t f;
3233+} cp_csq_data_u;
3234+
3235+typedef struct _cp_csq_stat_t {
3236+ unsigned long csq_rptr_primary : 8;
3237+ unsigned long csq_wptr_primary : 8;
3238+ unsigned long csq_rptr_indirect : 8;
3239+ unsigned long csq_wptr_indirect : 8;
3240+ } cp_csq_stat_t;
3241+
3242+typedef union {
3243+ unsigned long val : 32;
3244+ cp_csq_stat_t f;
3245+} cp_csq_stat_u;
3246+
3247+typedef struct _cp_stat_t {
3248+ unsigned long mru_busy : 1;
3249+ unsigned long mwu_busy : 1;
3250+ unsigned long rsiu_busy : 1;
3251+ unsigned long rciu_busy : 1;
3252+ unsigned long : 5;
3253+ unsigned long csf_primary_busy : 1;
3254+ unsigned long csf_indirect_busy : 1;
3255+ unsigned long csq_primary_busy : 1;
3256+ unsigned long csq_indirect_busy : 1;
3257+ unsigned long csi_busy : 1;
3258+ unsigned long : 14;
3259+ unsigned long guidma_busy : 1;
3260+ unsigned long viddma_busy : 1;
3261+ unsigned long cmdstrm_busy : 1;
3262+ unsigned long cp_busy : 1;
3263+ } cp_stat_t;
3264+
3265+typedef union {
3266+ unsigned long val : 32;
3267+ cp_stat_t f;
3268+} cp_stat_u;
3269+
3270+typedef struct _gen_int_cntl_t {
3271+ unsigned long crtc_vblank_mask : 1;
3272+ unsigned long crtc_vline_mask : 1;
3273+ unsigned long crtc_hwint1_mask : 1;
3274+ unsigned long crtc_hwint2_mask : 1;
3275+ unsigned long : 15;
3276+ unsigned long gui_idle_mask : 1;
3277+ unsigned long : 8;
3278+ unsigned long pm4_idle_int_mask : 1;
3279+ unsigned long dvi_i2c_int_mask : 1;
3280+ unsigned long : 2;
3281+ } gen_int_cntl_t;
3282+
3283+typedef union {
3284+ unsigned long val : 32;
3285+ gen_int_cntl_t f;
3286+} gen_int_cntl_u;
3287+
3288+typedef struct _gen_int_status_rd_t {
3289+ unsigned long crtc_vblank_stat : 1;
3290+ unsigned long crtc_vline_stat : 1;
3291+ unsigned long crtc_hwint1_stat : 1;
3292+ unsigned long crtc_hwint2_stat : 1;
3293+ unsigned long : 15;
3294+ unsigned long gui_idle_stat : 1;
3295+ unsigned long : 8;
3296+ unsigned long pm4_idle_int_stat : 1;
3297+ unsigned long dvi_i2c_int_stat : 1;
3298+ unsigned long : 2;
3299+ } gen_int_status_rd_t;
3300+
3301+typedef union {
3302+ unsigned long val : 32;
3303+ gen_int_status_rd_t f;
3304+} gen_int_status_rd_u;
3305+
3306+typedef struct _gen_int_status_wr_t {
3307+ unsigned long crtc_vblank_stat_ak : 1;
3308+ unsigned long crtc_vline_stat_ak : 1;
3309+ unsigned long crtc_hwint1_stat_ak : 1;
3310+ unsigned long crtc_hwint2_stat_ak : 1;
3311+ unsigned long : 15;
3312+ unsigned long gui_idle_stat_ak : 1;
3313+ unsigned long : 8;
3314+ unsigned long pm4_idle_int_ak : 1;
3315+ unsigned long dvi_i2c_int_ak : 1;
3316+ unsigned long : 2;
3317+ } gen_int_status_wr_t;
3318+
3319+typedef union {
3320+ unsigned long val : 32;
3321+ gen_int_status_wr_t f;
3322+} gen_int_status_wr_u;
3323+
3324+typedef struct _lcd_format_t {
3325+ unsigned long lcd_type : 4;
3326+ unsigned long color_to_mono : 1;
3327+ unsigned long data_inv : 1;
3328+ unsigned long stn_fm : 2;
3329+ unsigned long tft_fm : 2;
3330+ unsigned long scan_lr_en : 1;
3331+ unsigned long scan_ud_en : 1;
3332+ unsigned long pol_inv : 1;
3333+ unsigned long rst_fm : 1;
3334+ unsigned long yuv_to_rgb : 1;
3335+ unsigned long hr_tft : 1;
3336+ unsigned long ulc_panel : 1;
3337+ unsigned long : 15;
3338+ } lcd_format_t;
3339+
3340+typedef union {
3341+ unsigned long val : 32;
3342+ lcd_format_t f;
3343+} lcd_format_u;
3344+
3345+typedef struct _graphic_ctrl_t {
3346+ unsigned long color_depth : 3;
3347+ unsigned long portrait_mode : 2;
3348+ unsigned long low_power_on : 1;
3349+ unsigned long req_freq : 4;
3350+ unsigned long en_crtc : 1;
3351+ unsigned long en_graphic_req : 1;
3352+ unsigned long en_graphic_crtc : 1;
3353+ unsigned long total_req_graphic : 9;
3354+ unsigned long lcd_pclk_on : 1;
3355+ unsigned long lcd_sclk_on : 1;
3356+ unsigned long pclk_running : 1;
3357+ unsigned long sclk_running : 1;
3358+ unsigned long : 6;
3359+ } graphic_ctrl_t;
3360+
3361+typedef union {
3362+ unsigned long val : 32;
3363+ graphic_ctrl_t f;
3364+} graphic_ctrl_u;
3365+
3366+typedef struct _graphic_offset_t {
3367+ unsigned long graphic_offset : 24;
3368+ unsigned long : 8;
3369+ } graphic_offset_t;
3370+
3371+typedef union {
3372+ unsigned long val : 32;
3373+ graphic_offset_t f;
3374+} graphic_offset_u;
3375+
3376+typedef struct _graphic_pitch_t {
3377+ unsigned long graphic_pitch : 11;
3378+ unsigned long : 21;
3379+ } graphic_pitch_t;
3380+
3381+typedef union {
3382+ unsigned long val : 32;
3383+ graphic_pitch_t f;
3384+} graphic_pitch_u;
3385+
3386+typedef struct _crtc_total_t {
3387+ unsigned long crtc_h_total : 10;
3388+ unsigned long : 6;
3389+ unsigned long crtc_v_total : 10;
3390+ unsigned long : 6;
3391+ } crtc_total_t;
3392+
3393+typedef union {
3394+ unsigned long val : 32;
3395+ crtc_total_t f;
3396+} crtc_total_u;
3397+
3398+typedef struct _active_h_disp_t {
3399+ unsigned long active_h_start : 10;
3400+ unsigned long : 6;
3401+ unsigned long active_h_end : 10;
3402+ unsigned long : 6;
3403+ } active_h_disp_t;
3404+
3405+typedef union {
3406+ unsigned long val : 32;
3407+ active_h_disp_t f;
3408+} active_h_disp_u;
3409+
3410+typedef struct _active_v_disp_t {
3411+ unsigned long active_v_start : 10;
3412+ unsigned long : 6;
3413+ unsigned long active_v_end : 10;
3414+ unsigned long : 6;
3415+ } active_v_disp_t;
3416+
3417+typedef union {
3418+ unsigned long val : 32;
3419+ active_v_disp_t f;
3420+} active_v_disp_u;
3421+
3422+typedef struct _graphic_h_disp_t {
3423+ unsigned long graphic_h_start : 10;
3424+ unsigned long : 6;
3425+ unsigned long graphic_h_end : 10;
3426+ unsigned long : 6;
3427+ } graphic_h_disp_t;
3428+
3429+typedef union {
3430+ unsigned long val : 32;
3431+ graphic_h_disp_t f;
3432+} graphic_h_disp_u;
3433+
3434+typedef struct _graphic_v_disp_t {
3435+ unsigned long graphic_v_start : 10;
3436+ unsigned long : 6;
3437+ unsigned long graphic_v_end : 10;
3438+ unsigned long : 6;
3439+ } graphic_v_disp_t;
3440+
3441+typedef union {
3442+ unsigned long val : 32;
3443+ graphic_v_disp_t f;
3444+} graphic_v_disp_u;
3445+
3446+typedef struct _video_ctrl_t {
3447+ unsigned long video_mode : 1;
3448+ unsigned long keyer_en : 1;
3449+ unsigned long en_video_req : 1;
3450+ unsigned long en_graphic_req_video : 1;
3451+ unsigned long en_video_crtc : 1;
3452+ unsigned long video_hor_exp : 2;
3453+ unsigned long video_ver_exp : 2;
3454+ unsigned long uv_combine : 1;
3455+ unsigned long total_req_video : 9;
3456+ unsigned long video_ch_sel : 1;
3457+ unsigned long video_portrait : 2;
3458+ unsigned long yuv2rgb_en : 1;
3459+ unsigned long yuv2rgb_option : 1;
3460+ unsigned long video_inv_hor : 1;
3461+ unsigned long video_inv_ver : 1;
3462+ unsigned long gamma_sel : 2;
3463+ unsigned long dis_limit : 1;
3464+ unsigned long en_uv_hblend : 1;
3465+ unsigned long rgb_gamma_sel : 2;
3466+ } video_ctrl_t;
3467+
3468+typedef union {
3469+ unsigned long val : 32;
3470+ video_ctrl_t f;
3471+} video_ctrl_u;
3472+
3473+typedef struct _graphic_key_t {
3474+ unsigned long keyer_color : 16;
3475+ unsigned long keyer_mask : 16;
3476+ } graphic_key_t;
3477+
3478+typedef union {
3479+ unsigned long val : 32;
3480+ graphic_key_t f;
3481+} graphic_key_u;
3482+
3483+typedef struct _video_y_offset_t {
3484+ unsigned long y_offset : 24;
3485+ unsigned long : 8;
3486+ } video_y_offset_t;
3487+
3488+typedef union {
3489+ unsigned long val : 32;
3490+ video_y_offset_t f;
3491+} video_y_offset_u;
3492+
3493+typedef struct _video_y_pitch_t {
3494+ unsigned long y_pitch : 11;
3495+ unsigned long : 21;
3496+ } video_y_pitch_t;
3497+
3498+typedef union {
3499+ unsigned long val : 32;
3500+ video_y_pitch_t f;
3501+} video_y_pitch_u;
3502+
3503+typedef struct _video_u_offset_t {
3504+ unsigned long u_offset : 24;
3505+ unsigned long : 8;
3506+ } video_u_offset_t;
3507+
3508+typedef union {
3509+ unsigned long val : 32;
3510+ video_u_offset_t f;
3511+} video_u_offset_u;
3512+
3513+typedef struct _video_u_pitch_t {
3514+ unsigned long u_pitch : 11;
3515+ unsigned long : 21;
3516+ } video_u_pitch_t;
3517+
3518+typedef union {
3519+ unsigned long val : 32;
3520+ video_u_pitch_t f;
3521+} video_u_pitch_u;
3522+
3523+typedef struct _video_v_offset_t {
3524+ unsigned long v_offset : 24;
3525+ unsigned long : 8;
3526+ } video_v_offset_t;
3527+
3528+typedef union {
3529+ unsigned long val : 32;
3530+ video_v_offset_t f;
3531+} video_v_offset_u;
3532+
3533+typedef struct _video_v_pitch_t {
3534+ unsigned long v_pitch : 11;
3535+ unsigned long : 21;
3536+ } video_v_pitch_t;
3537+
3538+typedef union {
3539+ unsigned long val : 32;
3540+ video_v_pitch_t f;
3541+} video_v_pitch_u;
3542+
3543+typedef struct _video_h_pos_t {
3544+ unsigned long video_h_start : 10;
3545+ unsigned long : 6;
3546+ unsigned long video_h_end : 10;
3547+ unsigned long : 6;
3548+ } video_h_pos_t;
3549+
3550+typedef union {
3551+ unsigned long val : 32;
3552+ video_h_pos_t f;
3553+} video_h_pos_u;
3554+
3555+typedef struct _video_v_pos_t {
3556+ unsigned long video_v_start : 10;
3557+ unsigned long : 6;
3558+ unsigned long video_v_end : 10;
3559+ unsigned long : 6;
3560+ } video_v_pos_t;
3561+
3562+typedef union {
3563+ unsigned long val : 32;
3564+ video_v_pos_t f;
3565+} video_v_pos_u;
3566+
3567+typedef struct _brightness_cntl_t {
3568+ unsigned long brightness : 7;
3569+ unsigned long : 25;
3570+ } brightness_cntl_t;
3571+
3572+typedef union {
3573+ unsigned long val : 32;
3574+ brightness_cntl_t f;
3575+} brightness_cntl_u;
3576+
3577+typedef struct _cursor1_offset_t {
3578+ unsigned long cur1_offset : 24;
3579+ unsigned long cur1_x_offset : 4;
3580+ unsigned long cur1_y_offset : 4;
3581+ } cursor1_offset_t;
3582+
3583+typedef union {
3584+ unsigned long val : 32;
3585+ cursor1_offset_t f;
3586+} cursor1_offset_u;
3587+
3588+typedef struct _cursor1_h_pos_t {
3589+ unsigned long cur1_h_start : 10;
3590+ unsigned long : 6;
3591+ unsigned long cur1_h_end : 10;
3592+ unsigned long : 5;
3593+ unsigned long cur1_en : 1;
3594+ } cursor1_h_pos_t;
3595+
3596+typedef union {
3597+ unsigned long val : 32;
3598+ cursor1_h_pos_t f;
3599+} cursor1_h_pos_u;
3600+
3601+typedef struct _cursor1_v_pos_t {
3602+ unsigned long cur1_v_start : 10;
3603+ unsigned long : 6;
3604+ unsigned long cur1_v_end : 10;
3605+ unsigned long : 6;
3606+ } cursor1_v_pos_t;
3607+
3608+typedef union {
3609+ unsigned long val : 32;
3610+ cursor1_v_pos_t f;
3611+} cursor1_v_pos_u;
3612+
3613+typedef struct _cursor1_color0_t {
3614+ unsigned long cur1_color0_r : 8;
3615+ unsigned long cur1_color0_g : 8;
3616+ unsigned long cur1_color0_b : 8;
3617+ unsigned long : 8;
3618+ } cursor1_color0_t;
3619+
3620+typedef union {
3621+ unsigned long val : 32;
3622+ cursor1_color0_t f;
3623+} cursor1_color0_u;
3624+
3625+typedef struct _cursor1_color1_t {
3626+ unsigned long cur1_color1_r : 8;
3627+ unsigned long cur1_color1_g : 8;
3628+ unsigned long cur1_color1_b : 8;
3629+ unsigned long : 8;
3630+ } cursor1_color1_t;
3631+
3632+typedef union {
3633+ unsigned long val : 32;
3634+ cursor1_color1_t f;
3635+} cursor1_color1_u;
3636+
3637+typedef struct _cursor2_offset_t {
3638+ unsigned long cur2_offset : 24;
3639+ unsigned long cur2_x_offset : 4;
3640+ unsigned long cur2_y_offset : 4;
3641+ } cursor2_offset_t;
3642+
3643+typedef union {
3644+ unsigned long val : 32;
3645+ cursor2_offset_t f;
3646+} cursor2_offset_u;
3647+
3648+typedef struct _cursor2_h_pos_t {
3649+ unsigned long cur2_h_start : 10;
3650+ unsigned long : 6;
3651+ unsigned long cur2_h_end : 10;
3652+ unsigned long : 5;
3653+ unsigned long cur2_en : 1;
3654+ } cursor2_h_pos_t;
3655+
3656+typedef union {
3657+ unsigned long val : 32;
3658+ cursor2_h_pos_t f;
3659+} cursor2_h_pos_u;
3660+
3661+typedef struct _cursor2_v_pos_t {
3662+ unsigned long cur2_v_start : 10;
3663+ unsigned long : 6;
3664+ unsigned long cur2_v_end : 10;
3665+ unsigned long : 6;
3666+ } cursor2_v_pos_t;
3667+
3668+typedef union {
3669+ unsigned long val : 32;
3670+ cursor2_v_pos_t f;
3671+} cursor2_v_pos_u;
3672+
3673+typedef struct _cursor2_color0_t {
3674+ unsigned long cur2_color0_r : 8;
3675+ unsigned long cur2_color0_g : 8;
3676+ unsigned long cur2_color0_b : 8;
3677+ unsigned long : 8;
3678+ } cursor2_color0_t;
3679+
3680+typedef union {
3681+ unsigned long val : 32;
3682+ cursor2_color0_t f;
3683+} cursor2_color0_u;
3684+
3685+typedef struct _cursor2_color1_t {
3686+ unsigned long cur2_color1_r : 8;
3687+ unsigned long cur2_color1_g : 8;
3688+ unsigned long cur2_color1_b : 8;
3689+ unsigned long : 8;
3690+ } cursor2_color1_t;
3691+
3692+typedef union {
3693+ unsigned long val : 32;
3694+ cursor2_color1_t f;
3695+} cursor2_color1_u;
3696+
3697+typedef struct _disp_int_cntl_t {
3698+ unsigned long vline_int_pos : 10;
3699+ unsigned long : 6;
3700+ unsigned long hpos_int_pos : 10;
3701+ unsigned long : 4;
3702+ unsigned long vblank_int_pol : 1;
3703+ unsigned long frame_int_pol : 1;
3704+ } disp_int_cntl_t;
3705+
3706+typedef union {
3707+ unsigned long val : 32;
3708+ disp_int_cntl_t f;
3709+} disp_int_cntl_u;
3710+
3711+typedef struct _crtc_ss_t {
3712+ unsigned long ss_start : 10;
3713+ unsigned long : 6;
3714+ unsigned long ss_end : 10;
3715+ unsigned long : 2;
3716+ unsigned long ss_align : 1;
3717+ unsigned long ss_pol : 1;
3718+ unsigned long ss_run_mode : 1;
3719+ unsigned long ss_en : 1;
3720+ } crtc_ss_t;
3721+
3722+typedef union {
3723+ unsigned long val : 32;
3724+ crtc_ss_t f;
3725+} crtc_ss_u;
3726+
3727+typedef struct _crtc_ls_t {
3728+ unsigned long ls_start : 10;
3729+ unsigned long : 6;
3730+ unsigned long ls_end : 10;
3731+ unsigned long : 2;
3732+ unsigned long ls_align : 1;
3733+ unsigned long ls_pol : 1;
3734+ unsigned long ls_run_mode : 1;
3735+ unsigned long ls_en : 1;
3736+ } crtc_ls_t;
3737+
3738+typedef union {
3739+ unsigned long val : 32;
3740+ crtc_ls_t f;
3741+} crtc_ls_u;
3742+
3743+typedef struct _crtc_rev_t {
3744+ unsigned long rev_pos : 10;
3745+ unsigned long : 6;
3746+ unsigned long rev_align : 1;
3747+ unsigned long rev_freq_nref : 5;
3748+ unsigned long rev_en : 1;
3749+ unsigned long : 9;
3750+ } crtc_rev_t;
3751+
3752+typedef union {
3753+ unsigned long val : 32;
3754+ crtc_rev_t f;
3755+} crtc_rev_u;
3756+
3757+typedef struct _crtc_dclk_t {
3758+ unsigned long dclk_start : 10;
3759+ unsigned long : 6;
3760+ unsigned long dclk_end : 10;
3761+ unsigned long : 1;
3762+ unsigned long dclk_run_mode : 2;
3763+ unsigned long dclk_pol : 1;
3764+ unsigned long dclk_align : 1;
3765+ unsigned long dclk_en : 1;
3766+ } crtc_dclk_t;
3767+
3768+typedef union {
3769+ unsigned long val : 32;
3770+ crtc_dclk_t f;
3771+} crtc_dclk_u;
3772+
3773+typedef struct _crtc_gs_t {
3774+ unsigned long gs_start : 10;
3775+ unsigned long : 6;
3776+ unsigned long gs_end : 10;
3777+ unsigned long : 3;
3778+ unsigned long gs_align : 1;
3779+ unsigned long gs_pol : 1;
3780+ unsigned long gs_en : 1;
3781+ } crtc_gs_t;
3782+
3783+typedef union {
3784+ unsigned long val : 32;
3785+ crtc_gs_t f;
3786+} crtc_gs_u;
3787+
3788+typedef struct _crtc_vpos_gs_t {
3789+ unsigned long gs_vpos_start : 10;
3790+ unsigned long : 6;
3791+ unsigned long gs_vpos_end : 10;
3792+ unsigned long : 6;
3793+ } crtc_vpos_gs_t;
3794+
3795+typedef union {
3796+ unsigned long val : 32;
3797+ crtc_vpos_gs_t f;
3798+} crtc_vpos_gs_u;
3799+
3800+typedef struct _crtc_gclk_t {
3801+ unsigned long gclk_start : 10;
3802+ unsigned long : 6;
3803+ unsigned long gclk_end : 10;
3804+ unsigned long : 3;
3805+ unsigned long gclk_align : 1;
3806+ unsigned long gclk_pol : 1;
3807+ unsigned long gclk_en : 1;
3808+ } crtc_gclk_t;
3809+
3810+typedef union {
3811+ unsigned long val : 32;
3812+ crtc_gclk_t f;
3813+} crtc_gclk_u;
3814+
3815+typedef struct _crtc_goe_t {
3816+ unsigned long goe_start : 10;
3817+ unsigned long : 6;
3818+ unsigned long goe_end : 10;
3819+ unsigned long : 3;
3820+ unsigned long goe_align : 1;
3821+ unsigned long goe_pol : 1;
3822+ unsigned long goe_en : 1;
3823+ } crtc_goe_t;
3824+
3825+typedef union {
3826+ unsigned long val : 32;
3827+ crtc_goe_t f;
3828+} crtc_goe_u;
3829+
3830+typedef struct _crtc_frame_t {
3831+ unsigned long crtc_fr_start : 10;
3832+ unsigned long : 6;
3833+ unsigned long crtc_fr_end : 10;
3834+ unsigned long : 4;
3835+ unsigned long crtc_frame_en : 1;
3836+ unsigned long crtc_frame_align : 1;
3837+ } crtc_frame_t;
3838+
3839+typedef union {
3840+ unsigned long val : 32;
3841+ crtc_frame_t f;
3842+} crtc_frame_u;
3843+
3844+typedef struct _crtc_frame_vpos_t {
3845+ unsigned long crtc_fr_vpos : 10;
3846+ unsigned long : 22;
3847+ } crtc_frame_vpos_t;
3848+
3849+typedef union {
3850+ unsigned long val : 32;
3851+ crtc_frame_vpos_t f;
3852+} crtc_frame_vpos_u;
3853+
3854+typedef struct _gpio_data_t {
3855+ unsigned long gio_out : 16;
3856+ unsigned long gio_in : 16;
3857+ } gpio_data_t;
3858+
3859+typedef union {
3860+ unsigned long val : 32;
3861+ gpio_data_t f;
3862+} gpio_data_u;
3863+
3864+typedef struct _gpio_cntl1_t {
3865+ unsigned long gio_pd : 16;
3866+ unsigned long gio_schmen : 16;
3867+ } gpio_cntl1_t;
3868+
3869+typedef union {
3870+ unsigned long val : 32;
3871+ gpio_cntl1_t f;
3872+} gpio_cntl1_u;
3873+
3874+typedef struct _gpio_cntl2_t {
3875+ unsigned long gio_oe : 16;
3876+ unsigned long gio_srp : 1;
3877+ unsigned long gio_srn : 1;
3878+ unsigned long gio_sp : 4;
3879+ unsigned long gio_sn : 4;
3880+ unsigned long : 6;
3881+ } gpio_cntl2_t;
3882+
3883+typedef union {
3884+ unsigned long val : 32;
3885+ gpio_cntl2_t f;
3886+} gpio_cntl2_u;
3887+
3888+typedef struct _lcdd_cntl1_t {
3889+ unsigned long lcdd_pd : 18;
3890+ unsigned long lcdd_srp : 1;
3891+ unsigned long lcdd_srn : 1;
3892+ unsigned long lcdd_sp : 4;
3893+ unsigned long lcdd_sn : 4;
3894+ unsigned long lcdd_align : 1;
3895+ unsigned long : 3;
3896+ } lcdd_cntl1_t;
3897+
3898+typedef union {
3899+ unsigned long val : 32;
3900+ lcdd_cntl1_t f;
3901+} lcdd_cntl1_u;
3902+
3903+typedef struct _lcdd_cntl2_t {
3904+ unsigned long lcdd_oe : 18;
3905+ unsigned long : 14;
3906+ } lcdd_cntl2_t;
3907+
3908+typedef union {
3909+ unsigned long val : 32;
3910+ lcdd_cntl2_t f;
3911+} lcdd_cntl2_u;
3912+
3913+typedef struct _genlcd_cntl1_t {
3914+ unsigned long dclk_oe : 1;
3915+ unsigned long dclk_pd : 1;
3916+ unsigned long dclk_srp : 1;
3917+ unsigned long dclk_srn : 1;
3918+ unsigned long dclk_sp : 4;
3919+ unsigned long dclk_sn : 4;
3920+ unsigned long ss_oe : 1;
3921+ unsigned long ss_pd : 1;
3922+ unsigned long ls_oe : 1;
3923+ unsigned long ls_pd : 1;
3924+ unsigned long gs_oe : 1;
3925+ unsigned long gs_pd : 1;
3926+ unsigned long goe_oe : 1;
3927+ unsigned long goe_pd : 1;
3928+ unsigned long rev_oe : 1;
3929+ unsigned long rev_pd : 1;
3930+ unsigned long frame_oe : 1;
3931+ unsigned long frame_pd : 1;
3932+ unsigned long : 8;
3933+ } genlcd_cntl1_t;
3934+
3935+typedef union {
3936+ unsigned long val : 32;
3937+ genlcd_cntl1_t f;
3938+} genlcd_cntl1_u;
3939+
3940+typedef struct _genlcd_cntl2_t {
3941+ unsigned long gclk_oe : 1;
3942+ unsigned long gclk_pd : 1;
3943+ unsigned long gclk_srp : 1;
3944+ unsigned long gclk_srn : 1;
3945+ unsigned long gclk_sp : 4;
3946+ unsigned long gclk_sn : 4;
3947+ unsigned long genlcd_srp : 1;
3948+ unsigned long genlcd_srn : 1;
3949+ unsigned long genlcd_sp : 4;
3950+ unsigned long genlcd_sn : 4;
3951+ unsigned long : 10;
3952+ } genlcd_cntl2_t;
3953+
3954+typedef union {
3955+ unsigned long val : 32;
3956+ genlcd_cntl2_t f;
3957+} genlcd_cntl2_u;
3958+
3959+typedef struct _disp_debug_t {
3960+ unsigned long disp_debug : 32;
3961+ } disp_debug_t;
3962+
3963+typedef union {
3964+ unsigned long val : 32;
3965+ disp_debug_t f;
3966+} disp_debug_u;
3967+
3968+typedef struct _disp_db_buf_cntl_rd_t {
3969+ unsigned long en_db_buf : 1;
3970+ unsigned long update_db_buf_done : 1;
3971+ unsigned long db_buf_cntl : 6;
3972+ unsigned long : 24;
3973+ } disp_db_buf_cntl_rd_t;
3974+
3975+typedef union {
3976+ unsigned long val : 32;
3977+ disp_db_buf_cntl_rd_t f;
3978+} disp_db_buf_cntl_rd_u;
3979+
3980+typedef struct _disp_db_buf_cntl_wr_t {
3981+ unsigned long en_db_buf : 1;
3982+ unsigned long update_db_buf : 1;
3983+ unsigned long db_buf_cntl : 6;
3984+ unsigned long : 24;
3985+ } disp_db_buf_cntl_wr_t;
3986+
3987+typedef union {
3988+ unsigned long val : 32;
3989+ disp_db_buf_cntl_wr_t f;
3990+} disp_db_buf_cntl_wr_u;
3991+
3992+typedef struct _disp_crc_sig_t {
3993+ unsigned long crc_sig_r : 6;
3994+ unsigned long crc_sig_g : 6;
3995+ unsigned long crc_sig_b : 6;
3996+ unsigned long crc_cont_en : 1;
3997+ unsigned long crc_en : 1;
3998+ unsigned long crc_mask_en : 1;
3999+ unsigned long crc_sig_cntl : 6;
4000+ unsigned long : 5;
4001+ } disp_crc_sig_t;
4002+
4003+typedef union {
4004+ unsigned long val : 32;
4005+ disp_crc_sig_t f;
4006+} disp_crc_sig_u;
4007+
4008+typedef struct _crtc_default_count_t {
4009+ unsigned long crtc_hcount_def : 10;
4010+ unsigned long : 6;
4011+ unsigned long crtc_vcount_def : 10;
4012+ unsigned long : 6;
4013+ } crtc_default_count_t;
4014+
4015+typedef union {
4016+ unsigned long val : 32;
4017+ crtc_default_count_t f;
4018+} crtc_default_count_u;
4019+
4020+typedef struct _lcd_background_color_t {
4021+ unsigned long lcd_bg_red : 8;
4022+ unsigned long lcd_bg_green : 8;
4023+ unsigned long lcd_bg_blue : 8;
4024+ unsigned long : 8;
4025+ } lcd_background_color_t;
4026+
4027+typedef union {
4028+ unsigned long val : 32;
4029+ lcd_background_color_t f;
4030+} lcd_background_color_u;
4031+
4032+typedef struct _crtc_ps2_t {
4033+ unsigned long ps2_start : 10;
4034+ unsigned long : 6;
4035+ unsigned long ps2_end : 10;
4036+ unsigned long : 4;
4037+ unsigned long ps2_pol : 1;
4038+ unsigned long ps2_en : 1;
4039+ } crtc_ps2_t;
4040+
4041+typedef union {
4042+ unsigned long val : 32;
4043+ crtc_ps2_t f;
4044+} crtc_ps2_u;
4045+
4046+typedef struct _crtc_ps2_vpos_t {
4047+ unsigned long ps2_vpos_start : 10;
4048+ unsigned long : 6;
4049+ unsigned long ps2_vpos_end : 10;
4050+ unsigned long : 6;
4051+ } crtc_ps2_vpos_t;
4052+
4053+typedef union {
4054+ unsigned long val : 32;
4055+ crtc_ps2_vpos_t f;
4056+} crtc_ps2_vpos_u;
4057+
4058+typedef struct _crtc_ps1_active_t {
4059+ unsigned long ps1_h_start : 10;
4060+ unsigned long : 6;
4061+ unsigned long ps1_h_end : 10;
4062+ unsigned long : 3;
4063+ unsigned long ps1_pol : 1;
4064+ unsigned long ps1_en : 1;
4065+ unsigned long ps1_use_nactive : 1;
4066+ } crtc_ps1_active_t;
4067+
4068+typedef union {
4069+ unsigned long val : 32;
4070+ crtc_ps1_active_t f;
4071+} crtc_ps1_active_u;
4072+
4073+typedef struct _crtc_ps1_nactive_t {
4074+ unsigned long ps1_h_start_na : 10;
4075+ unsigned long : 6;
4076+ unsigned long ps1_h_end_na : 10;
4077+ unsigned long : 5;
4078+ unsigned long ps1_en_na : 1;
4079+ } crtc_ps1_nactive_t;
4080+
4081+typedef union {
4082+ unsigned long val : 32;
4083+ crtc_ps1_nactive_t f;
4084+} crtc_ps1_nactive_u;
4085+
4086+typedef struct _crtc_gclk_ext_t {
4087+ unsigned long gclk_alter_start : 10;
4088+ unsigned long : 6;
4089+ unsigned long gclk_alter_width : 2;
4090+ unsigned long gclk_en_alter : 1;
4091+ unsigned long gclk_db_width : 2;
4092+ unsigned long : 11;
4093+ } crtc_gclk_ext_t;
4094+
4095+typedef union {
4096+ unsigned long val : 32;
4097+ crtc_gclk_ext_t f;
4098+} crtc_gclk_ext_u;
4099+
4100+typedef struct _crtc_alw_t {
4101+ unsigned long alw_hstart : 10;
4102+ unsigned long : 6;
4103+ unsigned long alw_hend : 10;
4104+ unsigned long : 4;
4105+ unsigned long alw_delay : 1;
4106+ unsigned long alw_en : 1;
4107+ } crtc_alw_t;
4108+
4109+typedef union {
4110+ unsigned long val : 32;
4111+ crtc_alw_t f;
4112+} crtc_alw_u;
4113+
4114+typedef struct _crtc_alw_vpos_t {
4115+ unsigned long alw_vstart : 10;
4116+ unsigned long : 6;
4117+ unsigned long alw_vend : 10;
4118+ unsigned long : 6;
4119+ } crtc_alw_vpos_t;
4120+
4121+typedef union {
4122+ unsigned long val : 32;
4123+ crtc_alw_vpos_t f;
4124+} crtc_alw_vpos_u;
4125+
4126+typedef struct _crtc_psk_t {
4127+ unsigned long psk_vstart : 10;
4128+ unsigned long : 6;
4129+ unsigned long psk_vend : 10;
4130+ unsigned long : 4;
4131+ unsigned long psk_pol : 1;
4132+ unsigned long psk_en : 1;
4133+ } crtc_psk_t;
4134+
4135+typedef union {
4136+ unsigned long val : 32;
4137+ crtc_psk_t f;
4138+} crtc_psk_u;
4139+
4140+typedef struct _crtc_psk_hpos_t {
4141+ unsigned long psk_hstart : 10;
4142+ unsigned long : 6;
4143+ unsigned long psk_hend : 10;
4144+ unsigned long : 6;
4145+ } crtc_psk_hpos_t;
4146+
4147+typedef union {
4148+ unsigned long val : 32;
4149+ crtc_psk_hpos_t f;
4150+} crtc_psk_hpos_u;
4151+
4152+typedef struct _crtc_cv4_start_t {
4153+ unsigned long cv4_vstart : 10;
4154+ unsigned long : 20;
4155+ unsigned long cv4_pol : 1;
4156+ unsigned long cv4_en : 1;
4157+ } crtc_cv4_start_t;
4158+
4159+typedef union {
4160+ unsigned long val : 32;
4161+ crtc_cv4_start_t f;
4162+} crtc_cv4_start_u;
4163+
4164+typedef struct _crtc_cv4_end_t {
4165+ unsigned long cv4_vend1 : 10;
4166+ unsigned long : 6;
4167+ unsigned long cv4_vend2 : 10;
4168+ unsigned long : 6;
4169+ } crtc_cv4_end_t;
4170+
4171+typedef union {
4172+ unsigned long val : 32;
4173+ crtc_cv4_end_t f;
4174+} crtc_cv4_end_u;
4175+
4176+typedef struct _crtc_cv4_hpos_t {
4177+ unsigned long cv4_hstart : 10;
4178+ unsigned long : 6;
4179+ unsigned long cv4_hend : 10;
4180+ unsigned long : 6;
4181+ } crtc_cv4_hpos_t;
4182+
4183+typedef union {
4184+ unsigned long val : 32;
4185+ crtc_cv4_hpos_t f;
4186+} crtc_cv4_hpos_u;
4187+
4188+typedef struct _crtc_eck_t {
4189+ unsigned long eck_freq1 : 3;
4190+ unsigned long eck_en : 1;
4191+ unsigned long : 28;
4192+ } crtc_eck_t;
4193+
4194+typedef union {
4195+ unsigned long val : 32;
4196+ crtc_eck_t f;
4197+} crtc_eck_u;
4198+
4199+typedef struct _refresh_cntl_t {
4200+ unsigned long ref_frame : 3;
4201+ unsigned long nref_frame : 5;
4202+ unsigned long ref_cntl : 1;
4203+ unsigned long stop_sm_nref : 1;
4204+ unsigned long stop_req_nref : 1;
4205+ unsigned long : 21;
4206+ } refresh_cntl_t;
4207+
4208+typedef union {
4209+ unsigned long val : 32;
4210+ refresh_cntl_t f;
4211+} refresh_cntl_u;
4212+
4213+typedef struct _genlcd_cntl3_t {
4214+ unsigned long ps1_oe : 1;
4215+ unsigned long ps1_pd : 1;
4216+ unsigned long ps2_oe : 1;
4217+ unsigned long ps2_pd : 1;
4218+ unsigned long rev2_oe : 1;
4219+ unsigned long rev2_pd : 1;
4220+ unsigned long awl_oe : 1;
4221+ unsigned long awl_pd : 1;
4222+ unsigned long dinv_oe : 1;
4223+ unsigned long dinv_pd : 1;
4224+ unsigned long psk_out : 1;
4225+ unsigned long psd_out : 1;
4226+ unsigned long eck_out : 1;
4227+ unsigned long cv4_out : 1;
4228+ unsigned long ps1_out : 1;
4229+ unsigned long ps2_out : 1;
4230+ unsigned long rev_out : 1;
4231+ unsigned long rev2_out : 1;
4232+ unsigned long : 14;
4233+ } genlcd_cntl3_t;
4234+
4235+typedef union {
4236+ unsigned long val : 32;
4237+ genlcd_cntl3_t f;
4238+} genlcd_cntl3_u;
4239+
4240+typedef struct _gpio_data2_t {
4241+ unsigned long gio2_out : 16;
4242+ unsigned long gio2_in : 16;
4243+ } gpio_data2_t;
4244+
4245+typedef union {
4246+ unsigned long val : 32;
4247+ gpio_data2_t f;
4248+} gpio_data2_u;
4249+
4250+typedef struct _gpio_cntl3_t {
4251+ unsigned long gio2_pd : 16;
4252+ unsigned long gio2_schmen : 16;
4253+ } gpio_cntl3_t;
4254+
4255+typedef union {
4256+ unsigned long val : 32;
4257+ gpio_cntl3_t f;
4258+} gpio_cntl3_u;
4259+
4260+typedef struct _gpio_cntl4_t {
4261+ unsigned long gio2_oe : 16;
4262+ unsigned long : 16;
4263+ } gpio_cntl4_t;
4264+
4265+typedef union {
4266+ unsigned long val : 32;
4267+ gpio_cntl4_t f;
4268+} gpio_cntl4_u;
4269+
4270+typedef struct _chip_strap_t {
4271+ unsigned long config_strap : 8;
4272+ unsigned long pkg_strap : 1;
4273+ unsigned long : 23;
4274+ } chip_strap_t;
4275+
4276+typedef union {
4277+ unsigned long val : 32;
4278+ chip_strap_t f;
4279+} chip_strap_u;
4280+
4281+typedef struct _disp_debug2_t {
4282+ unsigned long disp_debug2 : 32;
4283+ } disp_debug2_t;
4284+
4285+typedef union {
4286+ unsigned long val : 32;
4287+ disp_debug2_t f;
4288+} disp_debug2_u;
4289+
4290+typedef struct _debug_bus_cntl_t {
4291+ unsigned long debug_testmux : 4;
4292+ unsigned long debug_testsel : 4;
4293+ unsigned long debug_gioa_sel : 2;
4294+ unsigned long debug_giob_sel : 2;
4295+ unsigned long debug_clk_sel : 1;
4296+ unsigned long debug_clk_inv : 1;
4297+ unsigned long : 2;
4298+ unsigned long debug_bus : 16;
4299+ } debug_bus_cntl_t;
4300+
4301+typedef union {
4302+ unsigned long val : 32;
4303+ debug_bus_cntl_t f;
4304+} debug_bus_cntl_u;
4305+
4306+typedef struct _gamma_value1_t {
4307+ unsigned long gamma1 : 8;
4308+ unsigned long gamma2 : 8;
4309+ unsigned long gamma3 : 8;
4310+ unsigned long gamma4 : 8;
4311+ } gamma_value1_t;
4312+
4313+typedef union {
4314+ unsigned long val : 32;
4315+ gamma_value1_t f;
4316+} gamma_value1_u;
4317+
4318+typedef struct _gamma_value2_t {
4319+ unsigned long gamma5 : 8;
4320+ unsigned long gamma6 : 8;
4321+ unsigned long gamma7 : 8;
4322+ unsigned long gamma8 : 8;
4323+ } gamma_value2_t;
4324+
4325+typedef union {
4326+ unsigned long val : 32;
4327+ gamma_value2_t f;
4328+} gamma_value2_u;
4329+
4330+typedef struct _gamma_slope_t {
4331+ unsigned long slope1 : 3;
4332+ unsigned long slope2 : 3;
4333+ unsigned long slope3 : 3;
4334+ unsigned long slope4 : 3;
4335+ unsigned long slope5 : 3;
4336+ unsigned long slope6 : 3;
4337+ unsigned long slope7 : 3;
4338+ unsigned long slope8 : 3;
4339+ unsigned long : 8;
4340+ } gamma_slope_t;
4341+
4342+typedef union {
4343+ unsigned long val : 32;
4344+ gamma_slope_t f;
4345+} gamma_slope_u;
4346+
4347+typedef struct _gen_status_t {
4348+ unsigned long status : 16;
4349+ unsigned long : 16;
4350+ } gen_status_t;
4351+
4352+typedef union {
4353+ unsigned long val : 32;
4354+ gen_status_t f;
4355+} gen_status_u;
4356+
4357+typedef struct _hw_int_t {
4358+ unsigned long hwint1_pos : 5;
4359+ unsigned long hwint2_pos : 5;
4360+ unsigned long hwint1_pol : 1;
4361+ unsigned long hwint2_pol : 1;
4362+ unsigned long hwint1_en_db : 1;
4363+ unsigned long hwint2_en_db : 1;
4364+ unsigned long : 18;
4365+ } hw_int_t;
4366+
4367+typedef union {
4368+ unsigned long val : 32;
4369+ hw_int_t f;
4370+} hw_int_u;
4371+
4372+typedef struct _dst_offset_t {
4373+ unsigned long dst_offset : 24;
4374+ unsigned long : 8;
4375+ } dst_offset_t;
4376+
4377+typedef union {
4378+ unsigned long val : 32;
4379+ dst_offset_t f;
4380+} dst_offset_u;
4381+
4382+typedef struct _dst_pitch_t {
4383+ unsigned long dst_pitch : 14;
4384+ unsigned long mc_dst_pitch_mul : 2;
4385+ unsigned long : 16;
4386+ } dst_pitch_t;
4387+
4388+typedef union {
4389+ unsigned long val : 32;
4390+ dst_pitch_t f;
4391+} dst_pitch_u;
4392+
4393+typedef struct _dst_pitch_offset_t {
4394+ unsigned long dst_offset : 20;
4395+ unsigned long dst_pitch : 10;
4396+ unsigned long mc_dst_pitch_mul : 2;
4397+ } dst_pitch_offset_t;
4398+
4399+typedef union {
4400+ unsigned long val : 32;
4401+ dst_pitch_offset_t f;
4402+} dst_pitch_offset_u;
4403+
4404+typedef struct _dst_x_t {
4405+ unsigned long dst_x : 14;
4406+ unsigned long : 18;
4407+ } dst_x_t;
4408+
4409+typedef union {
4410+ unsigned long val : 32;
4411+ dst_x_t f;
4412+} dst_x_u;
4413+
4414+typedef struct _dst_y_t {
4415+ unsigned long dst_y : 14;
4416+ unsigned long : 18;
4417+ } dst_y_t;
4418+
4419+typedef union {
4420+ unsigned long val : 32;
4421+ dst_y_t f;
4422+} dst_y_u;
4423+
4424+typedef struct _dst_x_y_t {
4425+ unsigned long dst_y : 14;
4426+ unsigned long : 2;
4427+ unsigned long dst_x : 14;
4428+ unsigned long : 2;
4429+ } dst_x_y_t;
4430+
4431+typedef union {
4432+ unsigned long val : 32;
4433+ dst_x_y_t f;
4434+} dst_x_y_u;
4435+
4436+typedef struct _dst_y_x_t {
4437+ unsigned long dst_x : 14;
4438+ unsigned long : 2;
4439+ unsigned long dst_y : 14;
4440+ unsigned long : 2;
4441+ } dst_y_x_t;
4442+
4443+typedef union {
4444+ unsigned long val : 32;
4445+ dst_y_x_t f;
4446+} dst_y_x_u;
4447+
4448+typedef struct _dst_width_t {
4449+ unsigned long dst_width_b0 : 8;
4450+ unsigned long dst_width_b1 : 6;
4451+ unsigned long : 18;
4452+ } dst_width_t;
4453+
4454+typedef union {
4455+ unsigned long val : 32;
4456+ dst_width_t f;
4457+} dst_width_u;
4458+
4459+typedef struct _dst_height_t {
4460+ unsigned long dst_height : 14;
4461+ unsigned long : 18;
4462+ } dst_height_t;
4463+
4464+typedef union {
4465+ unsigned long val : 32;
4466+ dst_height_t f;
4467+} dst_height_u;
4468+
4469+typedef struct _dst_width_height_t {
4470+ unsigned long dst_height : 14;
4471+ unsigned long : 2;
4472+ unsigned long dst_width_b0 : 8;
4473+ unsigned long dst_width_b1 : 6;
4474+ unsigned long : 2;
4475+ } dst_width_height_t;
4476+
4477+typedef union {
4478+ unsigned long val : 32;
4479+ dst_width_height_t f;
4480+} dst_width_height_u;
4481+
4482+typedef struct _dst_height_width_t {
4483+ unsigned long dst_width_b0 : 8;
4484+ unsigned long dst_width_b1 : 6;
4485+ unsigned long : 2;
4486+ unsigned long dst_height : 14;
4487+ unsigned long : 2;
4488+ } dst_height_width_t;
4489+
4490+typedef union {
4491+ unsigned long val : 32;
4492+ dst_height_width_t f;
4493+} dst_height_width_u;
4494+
4495+typedef struct _dst_height_width_8_t {
4496+ unsigned long : 16;
4497+ unsigned long dst_width_b0 : 8;
4498+ unsigned long dst_height : 8;
4499+ } dst_height_width_8_t;
4500+
4501+typedef union {
4502+ unsigned long val : 32;
4503+ dst_height_width_8_t f;
4504+} dst_height_width_8_u;
4505+
4506+typedef struct _dst_height_y_t {
4507+ unsigned long dst_y : 14;
4508+ unsigned long : 2;
4509+ unsigned long dst_height : 14;
4510+ unsigned long : 2;
4511+ } dst_height_y_t;
4512+
4513+typedef union {
4514+ unsigned long val : 32;
4515+ dst_height_y_t f;
4516+} dst_height_y_u;
4517+
4518+typedef struct _dst_width_x_t {
4519+ unsigned long dst_x : 14;
4520+ unsigned long : 2;
4521+ unsigned long dst_width_b0 : 8;
4522+ unsigned long dst_width_b1 : 6;
4523+ unsigned long : 2;
4524+ } dst_width_x_t;
4525+
4526+typedef union {
4527+ unsigned long val : 32;
4528+ dst_width_x_t f;
4529+} dst_width_x_u;
4530+
4531+typedef struct _dst_width_x_incy_t {
4532+ unsigned long dst_x : 14;
4533+ unsigned long : 2;
4534+ unsigned long dst_width_b0 : 8;
4535+ unsigned long dst_width_b1 : 6;
4536+ unsigned long : 2;
4537+ } dst_width_x_incy_t;
4538+
4539+typedef union {
4540+ unsigned long val : 32;
4541+ dst_width_x_incy_t f;
4542+} dst_width_x_incy_u;
4543+
4544+typedef struct _dst_line_start_t {
4545+ unsigned long dst_start_x : 14;
4546+ unsigned long : 2;
4547+ unsigned long dst_start_y : 14;
4548+ unsigned long : 2;
4549+ } dst_line_start_t;
4550+
4551+typedef union {
4552+ unsigned long val : 32;
4553+ dst_line_start_t f;
4554+} dst_line_start_u;
4555+
4556+typedef struct _dst_line_end_t {
4557+ unsigned long dst_end_x : 14;
4558+ unsigned long : 2;
4559+ unsigned long dst_end_y_b0 : 8;
4560+ unsigned long dst_end_y_b1 : 6;
4561+ unsigned long : 2;
4562+ } dst_line_end_t;
4563+
4564+typedef union {
4565+ unsigned long val : 32;
4566+ dst_line_end_t f;
4567+} dst_line_end_u;
4568+
4569+typedef struct _brush_offset_t {
4570+ unsigned long brush_offset : 24;
4571+ unsigned long : 8;
4572+ } brush_offset_t;
4573+
4574+typedef union {
4575+ unsigned long val : 32;
4576+ brush_offset_t f;
4577+} brush_offset_u;
4578+
4579+typedef struct _brush_y_x_t {
4580+ unsigned long brush_x : 5;
4581+ unsigned long : 3;
4582+ unsigned long brush_y : 3;
4583+ unsigned long : 21;
4584+ } brush_y_x_t;
4585+
4586+typedef union {
4587+ unsigned long val : 32;
4588+ brush_y_x_t f;
4589+} brush_y_x_u;
4590+
4591+typedef struct _dp_brush_frgd_clr_t {
4592+ unsigned long dp_brush_frgd_clr : 32;
4593+ } dp_brush_frgd_clr_t;
4594+
4595+typedef union {
4596+ unsigned long val : 32;
4597+ dp_brush_frgd_clr_t f;
4598+} dp_brush_frgd_clr_u;
4599+
4600+typedef struct _dp_brush_bkgd_clr_t {
4601+ unsigned long dp_brush_bkgd_clr : 32;
4602+ } dp_brush_bkgd_clr_t;
4603+
4604+typedef union {
4605+ unsigned long val : 32;
4606+ dp_brush_bkgd_clr_t f;
4607+} dp_brush_bkgd_clr_u;
4608+
4609+typedef struct _src2_offset_t {
4610+ unsigned long src2_offset : 24;
4611+ unsigned long : 8;
4612+ } src2_offset_t;
4613+
4614+typedef union {
4615+ unsigned long val : 32;
4616+ src2_offset_t f;
4617+} src2_offset_u;
4618+
4619+typedef struct _src2_pitch_t {
4620+ unsigned long src2_pitch : 14;
4621+ unsigned long src2_pitch_mul : 2;
4622+ unsigned long : 16;
4623+ } src2_pitch_t;
4624+
4625+typedef union {
4626+ unsigned long val : 32;
4627+ src2_pitch_t f;
4628+} src2_pitch_u;
4629+
4630+typedef struct _src2_pitch_offset_t {
4631+ unsigned long src2_offset : 20;
4632+ unsigned long : 2;
4633+ unsigned long src2_pitch : 8;
4634+ unsigned long src2_pitch_mul : 2;
4635+ } src2_pitch_offset_t;
4636+
4637+typedef union {
4638+ unsigned long val : 32;
4639+ src2_pitch_offset_t f;
4640+} src2_pitch_offset_u;
4641+
4642+typedef struct _src2_x_t {
4643+ unsigned long src_x : 14;
4644+ unsigned long : 18;
4645+ } src2_x_t;
4646+
4647+typedef union {
4648+ unsigned long val : 32;
4649+ src2_x_t f;
4650+} src2_x_u;
4651+
4652+typedef struct _src2_y_t {
4653+ unsigned long src_y : 14;
4654+ unsigned long : 18;
4655+ } src2_y_t;
4656+
4657+typedef union {
4658+ unsigned long val : 32;
4659+ src2_y_t f;
4660+} src2_y_u;
4661+
4662+typedef struct _src2_x_y_t {
4663+ unsigned long src_y : 14;
4664+ unsigned long : 2;
4665+ unsigned long src_x : 14;
4666+ unsigned long : 2;
4667+ } src2_x_y_t;
4668+
4669+typedef union {
4670+ unsigned long val : 32;
4671+ src2_x_y_t f;
4672+} src2_x_y_u;
4673+
4674+typedef struct _src2_width_t {
4675+ unsigned long src2_width : 14;
4676+ unsigned long : 18;
4677+ } src2_width_t;
4678+
4679+typedef union {
4680+ unsigned long val : 32;
4681+ src2_width_t f;
4682+} src2_width_u;
4683+
4684+typedef struct _src2_height_t {
4685+ unsigned long src2_height : 14;
4686+ unsigned long : 18;
4687+ } src2_height_t;
4688+
4689+typedef union {
4690+ unsigned long val : 32;
4691+ src2_height_t f;
4692+} src2_height_u;
4693+
4694+typedef struct _src2_inc_t {
4695+ unsigned long src2_xinc : 6;
4696+ unsigned long : 2;
4697+ unsigned long src2_yinc : 6;
4698+ unsigned long : 18;
4699+ } src2_inc_t;
4700+
4701+typedef union {
4702+ unsigned long val : 32;
4703+ src2_inc_t f;
4704+} src2_inc_u;
4705+
4706+typedef struct _src_offset_t {
4707+ unsigned long src_offset : 24;
4708+ unsigned long : 8;
4709+ } src_offset_t;
4710+
4711+typedef union {
4712+ unsigned long val : 32;
4713+ src_offset_t f;
4714+} src_offset_u;
4715+
4716+typedef struct _src_pitch_t {
4717+ unsigned long src_pitch : 14;
4718+ unsigned long src_pitch_mul : 2;
4719+ unsigned long : 16;
4720+ } src_pitch_t;
4721+
4722+typedef union {
4723+ unsigned long val : 32;
4724+ src_pitch_t f;
4725+} src_pitch_u;
4726+
4727+typedef struct _src_pitch_offset_t {
4728+ unsigned long src_offset : 20;
4729+ unsigned long src_pitch : 10;
4730+ unsigned long src_pitch_mul : 2;
4731+ } src_pitch_offset_t;
4732+
4733+typedef union {
4734+ unsigned long val : 32;
4735+ src_pitch_offset_t f;
4736+} src_pitch_offset_u;
4737+
4738+typedef struct _src_x_t {
4739+ unsigned long src_x : 14;
4740+ unsigned long : 18;
4741+ } src_x_t;
4742+
4743+typedef union {
4744+ unsigned long val : 32;
4745+ src_x_t f;
4746+} src_x_u;
4747+
4748+typedef struct _src_y_t {
4749+ unsigned long src_y : 14;
4750+ unsigned long : 18;
4751+ } src_y_t;
4752+
4753+typedef union {
4754+ unsigned long val : 32;
4755+ src_y_t f;
4756+} src_y_u;
4757+
4758+typedef struct _src_x_y_t {
4759+ unsigned long src_y : 14;
4760+ unsigned long : 2;
4761+ unsigned long src_x : 14;
4762+ unsigned long : 2;
4763+ } src_x_y_t;
4764+
4765+typedef union {
4766+ unsigned long val : 32;
4767+ src_x_y_t f;
4768+} src_x_y_u;
4769+
4770+typedef struct _src_y_x_t {
4771+ unsigned long src_x : 14;
4772+ unsigned long : 2;
4773+ unsigned long src_y : 14;
4774+ unsigned long : 2;
4775+ } src_y_x_t;
4776+
4777+typedef union {
4778+ unsigned long val : 32;
4779+ src_y_x_t f;
4780+} src_y_x_u;
4781+
4782+typedef struct _src_width_t {
4783+ unsigned long src_width : 14;
4784+ unsigned long : 18;
4785+ } src_width_t;
4786+
4787+typedef union {
4788+ unsigned long val : 32;
4789+ src_width_t f;
4790+} src_width_u;
4791+
4792+typedef struct _src_height_t {
4793+ unsigned long src_height : 14;
4794+ unsigned long : 18;
4795+ } src_height_t;
4796+
4797+typedef union {
4798+ unsigned long val : 32;
4799+ src_height_t f;
4800+} src_height_u;
4801+
4802+typedef struct _src_inc_t {
4803+ unsigned long src_xinc : 6;
4804+ unsigned long : 2;
4805+ unsigned long src_yinc : 6;
4806+ unsigned long : 18;
4807+ } src_inc_t;
4808+
4809+typedef union {
4810+ unsigned long val : 32;
4811+ src_inc_t f;
4812+} src_inc_u;
4813+
4814+typedef struct _host_data0_t {
4815+ unsigned long host_data : 32;
4816+ } host_data0_t;
4817+
4818+typedef union {
4819+ unsigned long val : 32;
4820+ host_data0_t f;
4821+} host_data0_u;
4822+
4823+typedef struct _host_data1_t {
4824+ unsigned long host_data : 32;
4825+ } host_data1_t;
4826+
4827+typedef union {
4828+ unsigned long val : 32;
4829+ host_data1_t f;
4830+} host_data1_u;
4831+
4832+typedef struct _host_data2_t {
4833+ unsigned long host_data : 32;
4834+ } host_data2_t;
4835+
4836+typedef union {
4837+ unsigned long val : 32;
4838+ host_data2_t f;
4839+} host_data2_u;
4840+
4841+typedef struct _host_data3_t {
4842+ unsigned long host_data : 32;
4843+ } host_data3_t;
4844+
4845+typedef union {
4846+ unsigned long val : 32;
4847+ host_data3_t f;
4848+} host_data3_u;
4849+
4850+typedef struct _host_data4_t {
4851+ unsigned long host_data : 32;
4852+ } host_data4_t;
4853+
4854+typedef union {
4855+ unsigned long val : 32;
4856+ host_data4_t f;
4857+} host_data4_u;
4858+
4859+typedef struct _host_data5_t {
4860+ unsigned long host_data : 32;
4861+ } host_data5_t;
4862+
4863+typedef union {
4864+ unsigned long val : 32;
4865+ host_data5_t f;
4866+} host_data5_u;
4867+
4868+typedef struct _host_data6_t {
4869+ unsigned long host_data : 32;
4870+ } host_data6_t;
4871+
4872+typedef union {
4873+ unsigned long val : 32;
4874+ host_data6_t f;
4875+} host_data6_u;
4876+
4877+typedef struct _host_data7_t {
4878+ unsigned long host_data : 32;
4879+ } host_data7_t;
4880+
4881+typedef union {
4882+ unsigned long val : 32;
4883+ host_data7_t f;
4884+} host_data7_u;
4885+
4886+typedef struct _host_data_last_t {
4887+ unsigned long host_data_last : 32;
4888+ } host_data_last_t;
4889+
4890+typedef union {
4891+ unsigned long val : 32;
4892+ host_data_last_t f;
4893+} host_data_last_u;
4894+
4895+typedef struct _dp_src_frgd_clr_t {
4896+ unsigned long dp_src_frgd_clr : 32;
4897+ } dp_src_frgd_clr_t;
4898+
4899+typedef union {
4900+ unsigned long val : 32;
4901+ dp_src_frgd_clr_t f;
4902+} dp_src_frgd_clr_u;
4903+
4904+typedef struct _dp_src_bkgd_clr_t {
4905+ unsigned long dp_src_bkgd_clr : 32;
4906+ } dp_src_bkgd_clr_t;
4907+
4908+typedef union {
4909+ unsigned long val : 32;
4910+ dp_src_bkgd_clr_t f;
4911+} dp_src_bkgd_clr_u;
4912+
4913+typedef struct _sc_left_t {
4914+ unsigned long sc_left : 14;
4915+ unsigned long : 18;
4916+ } sc_left_t;
4917+
4918+typedef union {
4919+ unsigned long val : 32;
4920+ sc_left_t f;
4921+} sc_left_u;
4922+
4923+typedef struct _sc_right_t {
4924+ unsigned long sc_right : 14;
4925+ unsigned long : 18;
4926+ } sc_right_t;
4927+
4928+typedef union {
4929+ unsigned long val : 32;
4930+ sc_right_t f;
4931+} sc_right_u;
4932+
4933+typedef struct _sc_top_t {
4934+ unsigned long sc_top : 14;
4935+ unsigned long : 18;
4936+ } sc_top_t;
4937+
4938+typedef union {
4939+ unsigned long val : 32;
4940+ sc_top_t f;
4941+} sc_top_u;
4942+
4943+typedef struct _sc_bottom_t {
4944+ unsigned long sc_bottom : 14;
4945+ unsigned long : 18;
4946+ } sc_bottom_t;
4947+
4948+typedef union {
4949+ unsigned long val : 32;
4950+ sc_bottom_t f;
4951+} sc_bottom_u;
4952+
4953+typedef struct _src_sc_right_t {
4954+ unsigned long sc_right : 14;
4955+ unsigned long : 18;
4956+ } src_sc_right_t;
4957+
4958+typedef union {
4959+ unsigned long val : 32;
4960+ src_sc_right_t f;
4961+} src_sc_right_u;
4962+
4963+typedef struct _src_sc_bottom_t {
4964+ unsigned long sc_bottom : 14;
4965+ unsigned long : 18;
4966+ } src_sc_bottom_t;
4967+
4968+typedef union {
4969+ unsigned long val : 32;
4970+ src_sc_bottom_t f;
4971+} src_sc_bottom_u;
4972+
4973+typedef struct _dp_cntl_t {
4974+ unsigned long dst_x_dir : 1;
4975+ unsigned long dst_y_dir : 1;
4976+ unsigned long src_x_dir : 1;
4977+ unsigned long src_y_dir : 1;
4978+ unsigned long dst_major_x : 1;
4979+ unsigned long src_major_x : 1;
4980+ unsigned long : 26;
4981+ } dp_cntl_t;
4982+
4983+typedef union {
4984+ unsigned long val : 32;
4985+ dp_cntl_t f;
4986+} dp_cntl_u;
4987+
4988+typedef struct _dp_cntl_dst_dir_t {
4989+ unsigned long : 15;
4990+ unsigned long dst_y_dir : 1;
4991+ unsigned long : 15;
4992+ unsigned long dst_x_dir : 1;
4993+ } dp_cntl_dst_dir_t;
4994+
4995+typedef union {
4996+ unsigned long val : 32;
4997+ dp_cntl_dst_dir_t f;
4998+} dp_cntl_dst_dir_u;
4999+
5000+typedef struct _dp_datatype_t {
5001+ unsigned long dp_dst_datatype : 4;
5002+ unsigned long : 4;
5003+ unsigned long dp_brush_datatype : 4;
5004+ unsigned long dp_src2_type : 1;
5005+ unsigned long dp_src2_datatype : 3;
5006+ unsigned long dp_src_datatype : 3;
5007+ unsigned long : 11;
5008+ unsigned long dp_byte_pix_order : 1;
5009+ unsigned long : 1;
5010+ } dp_datatype_t;
5011+
5012+typedef union {
5013+ unsigned long val : 32;
5014+ dp_datatype_t f;
5015+} dp_datatype_u;
5016+
5017+typedef struct _dp_mix_t {
5018+ unsigned long : 8;
5019+ unsigned long dp_src_source : 3;
5020+ unsigned long dp_src2_source : 3;
5021+ unsigned long : 2;
5022+ unsigned long dp_rop3 : 8;
5023+ unsigned long dp_op : 1;
5024+ unsigned long : 7;
5025+ } dp_mix_t;
5026+
5027+typedef union {
5028+ unsigned long val : 32;
5029+ dp_mix_t f;
5030+} dp_mix_u;
5031+
5032+typedef struct _dp_write_msk_t {
5033+ unsigned long dp_write_msk : 32;
5034+ } dp_write_msk_t;
5035+
5036+typedef union {
5037+ unsigned long val : 32;
5038+ dp_write_msk_t f;
5039+} dp_write_msk_u;
5040+
5041+typedef struct _clr_cmp_clr_src_t {
5042+ unsigned long clr_cmp_clr_src : 32;
5043+ } clr_cmp_clr_src_t;
5044+
5045+typedef union {
5046+ unsigned long val : 32;
5047+ clr_cmp_clr_src_t f;
5048+} clr_cmp_clr_src_u;
5049+
5050+typedef struct _clr_cmp_clr_dst_t {
5051+ unsigned long clr_cmp_clr_dst : 32;
5052+ } clr_cmp_clr_dst_t;
5053+
5054+typedef union {
5055+ unsigned long val : 32;
5056+ clr_cmp_clr_dst_t f;
5057+} clr_cmp_clr_dst_u;
5058+
5059+typedef struct _clr_cmp_cntl_t {
5060+ unsigned long clr_cmp_fcn_src : 3;
5061+ unsigned long : 5;
5062+ unsigned long clr_cmp_fcn_dst : 3;
5063+ unsigned long : 13;
5064+ unsigned long clr_cmp_src : 2;
5065+ unsigned long : 6;
5066+ } clr_cmp_cntl_t;
5067+
5068+typedef union {
5069+ unsigned long val : 32;
5070+ clr_cmp_cntl_t f;
5071+} clr_cmp_cntl_u;
5072+
5073+typedef struct _clr_cmp_msk_t {
5074+ unsigned long clr_cmp_msk : 32;
5075+ } clr_cmp_msk_t;
5076+
5077+typedef union {
5078+ unsigned long val : 32;
5079+ clr_cmp_msk_t f;
5080+} clr_cmp_msk_u;
5081+
5082+typedef struct _default_pitch_offset_t {
5083+ unsigned long default_offset : 20;
5084+ unsigned long default_pitch : 10;
5085+ unsigned long : 2;
5086+ } default_pitch_offset_t;
5087+
5088+typedef union {
5089+ unsigned long val : 32;
5090+ default_pitch_offset_t f;
5091+} default_pitch_offset_u;
5092+
5093+typedef struct _default_sc_bottom_right_t {
5094+ unsigned long default_sc_right : 14;
5095+ unsigned long : 2;
5096+ unsigned long default_sc_bottom : 14;
5097+ unsigned long : 2;
5098+ } default_sc_bottom_right_t;
5099+
5100+typedef union {
5101+ unsigned long val : 32;
5102+ default_sc_bottom_right_t f;
5103+} default_sc_bottom_right_u;
5104+
5105+typedef struct _default2_sc_bottom_right_t {
5106+ unsigned long default_sc_right : 14;
5107+ unsigned long : 2;
5108+ unsigned long default_sc_bottom : 14;
5109+ unsigned long : 2;
5110+ } default2_sc_bottom_right_t;
5111+
5112+typedef union {
5113+ unsigned long val : 32;
5114+ default2_sc_bottom_right_t f;
5115+} default2_sc_bottom_right_u;
5116+
5117+typedef struct _ref1_pitch_offset_t {
5118+ unsigned long offset : 20;
5119+ unsigned long : 2;
5120+ unsigned long pitch : 8;
5121+ unsigned long : 2;
5122+ } ref1_pitch_offset_t;
5123+
5124+typedef union {
5125+ unsigned long val : 32;
5126+ ref1_pitch_offset_t f;
5127+} ref1_pitch_offset_u;
5128+
5129+typedef struct _ref2_pitch_offset_t {
5130+ unsigned long offset : 20;
5131+ unsigned long : 2;
5132+ unsigned long pitch : 8;
5133+ unsigned long : 2;
5134+ } ref2_pitch_offset_t;
5135+
5136+typedef union {
5137+ unsigned long val : 32;
5138+ ref2_pitch_offset_t f;
5139+} ref2_pitch_offset_u;
5140+
5141+typedef struct _ref3_pitch_offset_t {
5142+ unsigned long offset : 20;
5143+ unsigned long : 2;
5144+ unsigned long pitch : 8;
5145+ unsigned long : 2;
5146+ } ref3_pitch_offset_t;
5147+
5148+typedef union {
5149+ unsigned long val : 32;
5150+ ref3_pitch_offset_t f;
5151+} ref3_pitch_offset_u;
5152+
5153+typedef struct _ref4_pitch_offset_t {
5154+ unsigned long offset : 20;
5155+ unsigned long : 2;
5156+ unsigned long pitch : 8;
5157+ unsigned long : 2;
5158+ } ref4_pitch_offset_t;
5159+
5160+typedef union {
5161+ unsigned long val : 32;
5162+ ref4_pitch_offset_t f;
5163+} ref4_pitch_offset_u;
5164+
5165+typedef struct _ref5_pitch_offset_t {
5166+ unsigned long offset : 20;
5167+ unsigned long : 2;
5168+ unsigned long pitch : 8;
5169+ unsigned long : 2;
5170+ } ref5_pitch_offset_t;
5171+
5172+typedef union {
5173+ unsigned long val : 32;
5174+ ref5_pitch_offset_t f;
5175+} ref5_pitch_offset_u;
5176+
5177+typedef struct _ref6_pitch_offset_t {
5178+ unsigned long offset : 20;
5179+ unsigned long : 2;
5180+ unsigned long pitch : 8;
5181+ unsigned long : 2;
5182+ } ref6_pitch_offset_t;
5183+
5184+typedef union {
5185+ unsigned long val : 32;
5186+ ref6_pitch_offset_t f;
5187+} ref6_pitch_offset_u;
5188+
5189+typedef struct _dp_gui_master_cntl_t {
5190+ unsigned long gmc_src_pitch_offset_cntl : 1;
5191+ unsigned long gmc_dst_pitch_offset_cntl : 1;
5192+ unsigned long gmc_src_clipping : 1;
5193+ unsigned long gmc_dst_clipping : 1;
5194+ unsigned long gmc_brush_datatype : 4;
5195+ unsigned long gmc_dst_datatype : 4;
5196+ unsigned long gmc_src_datatype : 3;
5197+ unsigned long gmc_byte_pix_order : 1;
5198+ unsigned long gmc_default_sel : 1;
5199+ unsigned long gmc_rop3 : 8;
5200+ unsigned long gmc_dp_src_source : 3;
5201+ unsigned long gmc_clr_cmp_fcn_dis : 1;
5202+ unsigned long : 1;
5203+ unsigned long gmc_wr_msk_dis : 1;
5204+ unsigned long gmc_dp_op : 1;
5205+ } dp_gui_master_cntl_t;
5206+
5207+typedef union {
5208+ unsigned long val : 32;
5209+ dp_gui_master_cntl_t f;
5210+} dp_gui_master_cntl_u;
5211+
5212+typedef struct _sc_top_left_t {
5213+ unsigned long sc_left : 14;
5214+ unsigned long : 2;
5215+ unsigned long sc_top : 14;
5216+ unsigned long : 2;
5217+ } sc_top_left_t;
5218+
5219+typedef union {
5220+ unsigned long val : 32;
5221+ sc_top_left_t f;
5222+} sc_top_left_u;
5223+
5224+typedef struct _sc_bottom_right_t {
5225+ unsigned long sc_right : 14;
5226+ unsigned long : 2;
5227+ unsigned long sc_bottom : 14;
5228+ unsigned long : 2;
5229+ } sc_bottom_right_t;
5230+
5231+typedef union {
5232+ unsigned long val : 32;
5233+ sc_bottom_right_t f;
5234+} sc_bottom_right_u;
5235+
5236+typedef struct _src_sc_bottom_right_t {
5237+ unsigned long sc_right : 14;
5238+ unsigned long : 2;
5239+ unsigned long sc_bottom : 14;
5240+ unsigned long : 2;
5241+ } src_sc_bottom_right_t;
5242+
5243+typedef union {
5244+ unsigned long val : 32;
5245+ src_sc_bottom_right_t f;
5246+} src_sc_bottom_right_u;
5247+
5248+typedef struct _global_alpha_t {
5249+ unsigned long alpha_r : 8;
5250+ unsigned long alpha_g : 8;
5251+ unsigned long alpha_b : 8;
5252+ unsigned long alpha_a : 8;
5253+ } global_alpha_t;
5254+
5255+typedef union {
5256+ unsigned long val : 32;
5257+ global_alpha_t f;
5258+} global_alpha_u;
5259+
5260+typedef struct _filter_coef_t {
5261+ unsigned long c_4 : 4;
5262+ unsigned long c_3 : 4;
5263+ unsigned long c_2 : 4;
5264+ unsigned long c_1 : 4;
5265+ unsigned long c1 : 4;
5266+ unsigned long c2 : 4;
5267+ unsigned long c3 : 4;
5268+ unsigned long c4 : 4;
5269+ } filter_coef_t;
5270+
5271+typedef union {
5272+ unsigned long val : 32;
5273+ filter_coef_t f;
5274+} filter_coef_u;
5275+
5276+typedef struct _mvc_cntl_start_t {
5277+ unsigned long mc_cntl_src_1_index : 4;
5278+ unsigned long mc_cntl_dst_offset : 20;
5279+ unsigned long mc_dst_pitch_mul : 2;
5280+ unsigned long mc_cntl_src_2_index : 3;
5281+ unsigned long mc_cntl_width_height_sel : 3;
5282+ } mvc_cntl_start_t;
5283+
5284+typedef union {
5285+ unsigned long val : 32;
5286+ mvc_cntl_start_t f;
5287+} mvc_cntl_start_u;
5288+
5289+typedef struct _e2_arithmetic_cntl_t {
5290+ unsigned long opcode : 5;
5291+ unsigned long shiftright : 4;
5292+ unsigned long clamp : 1;
5293+ unsigned long rounding : 2;
5294+ unsigned long filter_n : 3;
5295+ unsigned long : 1;
5296+ unsigned long srcblend_inv : 1;
5297+ unsigned long srcblend : 4;
5298+ unsigned long : 3;
5299+ unsigned long dstblend_inv : 1;
5300+ unsigned long dstblend : 4;
5301+ unsigned long dst_signed : 1;
5302+ unsigned long autoinc : 1;
5303+ unsigned long : 1;
5304+ } e2_arithmetic_cntl_t;
5305+
5306+typedef union {
5307+ unsigned long val : 32;
5308+ e2_arithmetic_cntl_t f;
5309+} e2_arithmetic_cntl_u;
5310+
5311+typedef struct _debug0_t {
5312+ unsigned long debug0_r : 8;
5313+ unsigned long : 8;
5314+ unsigned long debug0_rw : 8;
5315+ unsigned long : 8;
5316+ } debug0_t;
5317+
5318+typedef union {
5319+ unsigned long val : 32;
5320+ debug0_t f;
5321+} debug0_u;
5322+
5323+typedef struct _debug1_t {
5324+ unsigned long debug1_r : 8;
5325+ unsigned long : 8;
5326+ unsigned long debug1_rw : 8;
5327+ unsigned long : 8;
5328+ } debug1_t;
5329+
5330+typedef union {
5331+ unsigned long val : 32;
5332+ debug1_t f;
5333+} debug1_u;
5334+
5335+typedef struct _debug2_t {
5336+ unsigned long debug2_r : 8;
5337+ unsigned long : 8;
5338+ unsigned long debug2_rw : 8;
5339+ unsigned long : 8;
5340+ } debug2_t;
5341+
5342+typedef union {
5343+ unsigned long val : 32;
5344+ debug2_t f;
5345+} debug2_u;
5346+
5347+typedef struct _debug3_t {
5348+ unsigned long : 32;
5349+ } debug3_t;
5350+
5351+typedef union {
5352+ unsigned long val : 32;
5353+ debug3_t f;
5354+} debug3_u;
5355+
5356+typedef struct _debug4_t {
5357+ unsigned long : 32;
5358+ } debug4_t;
5359+
5360+typedef union {
5361+ unsigned long val : 32;
5362+ debug4_t f;
5363+} debug4_u;
5364+
5365+typedef struct _debug5_t {
5366+ unsigned long : 32;
5367+ } debug5_t;
5368+
5369+typedef union {
5370+ unsigned long val : 32;
5371+ debug5_t f;
5372+} debug5_u;
5373+
5374+typedef struct _debug6_t {
5375+ unsigned long : 32;
5376+ } debug6_t;
5377+
5378+typedef union {
5379+ unsigned long val : 32;
5380+ debug6_t f;
5381+} debug6_u;
5382+
5383+typedef struct _debug7_t {
5384+ unsigned long : 32;
5385+ } debug7_t;
5386+
5387+typedef union {
5388+ unsigned long val : 32;
5389+ debug7_t f;
5390+} debug7_u;
5391+
5392+typedef struct _debug8_t {
5393+ unsigned long : 32;
5394+ } debug8_t;
5395+
5396+typedef union {
5397+ unsigned long val : 32;
5398+ debug8_t f;
5399+} debug8_u;
5400+
5401+typedef struct _debug9_t {
5402+ unsigned long : 32;
5403+ } debug9_t;
5404+
5405+typedef union {
5406+ unsigned long val : 32;
5407+ debug9_t f;
5408+} debug9_u;
5409+
5410+typedef struct _debug10_t {
5411+ unsigned long : 32;
5412+ } debug10_t;
5413+
5414+typedef union {
5415+ unsigned long val : 32;
5416+ debug10_t f;
5417+} debug10_u;
5418+
5419+typedef struct _debug11_t {
5420+ unsigned long : 32;
5421+ } debug11_t;
5422+
5423+typedef union {
5424+ unsigned long val : 32;
5425+ debug11_t f;
5426+} debug11_u;
5427+
5428+typedef struct _debug12_t {
5429+ unsigned long : 32;
5430+ } debug12_t;
5431+
5432+typedef union {
5433+ unsigned long val : 32;
5434+ debug12_t f;
5435+} debug12_u;
5436+
5437+typedef struct _debug13_t {
5438+ unsigned long : 32;
5439+ } debug13_t;
5440+
5441+typedef union {
5442+ unsigned long val : 32;
5443+ debug13_t f;
5444+} debug13_u;
5445+
5446+typedef struct _debug14_t {
5447+ unsigned long : 32;
5448+ } debug14_t;
5449+
5450+typedef union {
5451+ unsigned long val : 32;
5452+ debug14_t f;
5453+} debug14_u;
5454+
5455+typedef struct _debug15_t {
5456+ unsigned long : 32;
5457+ } debug15_t;
5458+
5459+typedef union {
5460+ unsigned long val : 32;
5461+ debug15_t f;
5462+} debug15_u;
5463+
5464+typedef struct _eng_cntl_t {
5465+ unsigned long erc_reg_rd_ws : 1;
5466+ unsigned long erc_reg_wr_ws : 1;
5467+ unsigned long erc_idle_reg_wr : 1;
5468+ unsigned long dis_engine_triggers : 1;
5469+ unsigned long dis_rop_src_uses_dst_w_h : 1;
5470+ unsigned long dis_src_uses_dst_dirmaj : 1;
5471+ unsigned long : 6;
5472+ unsigned long force_3dclk_when_2dclk : 1;
5473+ unsigned long : 19;
5474+ } eng_cntl_t;
5475+
5476+typedef union {
5477+ unsigned long val : 32;
5478+ eng_cntl_t f;
5479+} eng_cntl_u;
5480+
5481+typedef struct _eng_perf_cnt_t {
5482+ unsigned long perf_cnt : 20;
5483+ unsigned long perf_sel : 4;
5484+ unsigned long perf_en : 1;
5485+ unsigned long : 3;
5486+ unsigned long perf_clr : 1;
5487+ unsigned long : 3;
5488+ } eng_perf_cnt_t;
5489+
5490+typedef union {
5491+ unsigned long val : 32;
5492+ eng_perf_cnt_t f;
5493+} eng_perf_cnt_u;
5494+
5495+typedef struct _idct_runs_t {
5496+ unsigned long idct_runs_3 : 8;
5497+ unsigned long idct_runs_2 : 8;
5498+ unsigned long idct_runs_1 : 8;
5499+ unsigned long idct_runs_0 : 8;
5500+ } idct_runs_t;
5501+
5502+typedef union {
5503+ unsigned long val : 32;
5504+ idct_runs_t f;
5505+} idct_runs_u;
5506+
5507+typedef struct _idct_levels_t {
5508+ unsigned long idct_level_hi : 16;
5509+ unsigned long idct_level_lo : 16;
5510+ } idct_levels_t;
5511+
5512+typedef union {
5513+ unsigned long val : 32;
5514+ idct_levels_t f;
5515+} idct_levels_u;
5516+
5517+typedef struct _idct_control_t {
5518+ unsigned long idct_ctl_luma_rd_format : 2;
5519+ unsigned long idct_ctl_chroma_rd_format : 2;
5520+ unsigned long idct_ctl_scan_pattern : 1;
5521+ unsigned long idct_ctl_intra : 1;
5522+ unsigned long idct_ctl_flush : 1;
5523+ unsigned long idct_ctl_passthru : 1;
5524+ unsigned long idct_ctl_sw_reset : 1;
5525+ unsigned long idct_ctl_constreq : 1;
5526+ unsigned long idct_ctl_scramble : 1;
5527+ unsigned long idct_ctl_alt_scan : 1;
5528+ unsigned long : 20;
5529+ } idct_control_t;
5530+
5531+typedef union {
5532+ unsigned long val : 32;
5533+ idct_control_t f;
5534+} idct_control_u;
5535+
5536+typedef struct _idct_auth_control_t {
5537+ unsigned long control_bits : 32;
5538+ } idct_auth_control_t;
5539+
5540+typedef union {
5541+ unsigned long val : 32;
5542+ idct_auth_control_t f;
5543+} idct_auth_control_u;
5544+
5545+typedef struct _idct_auth_t {
5546+ unsigned long auth : 32;
5547+ } idct_auth_t;
5548+
5549+typedef union {
5550+ unsigned long val : 32;
5551+ idct_auth_t f;
5552+} idct_auth_u;
5553+
5554+typedef struct _mem_cntl_t {
5555+ unsigned long : 1;
5556+ unsigned long en_mem_ch1 : 1;
5557+ unsigned long en_mem_ch2 : 1;
5558+ unsigned long int_mem_mapping : 1;
5559+ unsigned long : 28;
5560+ } mem_cntl_t;
5561+
5562+typedef union {
5563+ unsigned long val : 32;
5564+ mem_cntl_t f;
5565+} mem_cntl_u;
5566+
5567+typedef struct _mem_arb_t {
5568+ unsigned long disp_time_slot : 4;
5569+ unsigned long disp_timer : 4;
5570+ unsigned long arb_option : 1;
5571+ unsigned long : 23;
5572+ } mem_arb_t;
5573+
5574+typedef union {
5575+ unsigned long val : 32;
5576+ mem_arb_t f;
5577+} mem_arb_u;
5578+
5579+typedef struct _mc_fb_location_t {
5580+ unsigned long mc_fb_start : 16;
5581+ unsigned long mc_fb_top : 16;
5582+ } mc_fb_location_t;
5583+
5584+typedef union {
5585+ unsigned long val : 32;
5586+ mc_fb_location_t f;
5587+} mc_fb_location_u;
5588+
5589+typedef struct _mem_ext_cntl_t {
5590+ unsigned long mem_ext_enable : 1;
5591+ unsigned long mem_ap_enable : 1;
5592+ unsigned long mem_addr_mapping : 2;
5593+ unsigned long mem_wdoe_cntl : 2;
5594+ unsigned long mem_wdoe_extend : 1;
5595+ unsigned long : 1;
5596+ unsigned long mem_page_timer : 8;
5597+ unsigned long mem_dynamic_cke : 1;
5598+ unsigned long mem_sdram_tri_en : 1;
5599+ unsigned long mem_self_refresh_en : 1;
5600+ unsigned long mem_power_down : 1;
5601+ unsigned long mem_hw_power_down_en : 1;
5602+ unsigned long mem_power_down_stat : 1;
5603+ unsigned long : 3;
5604+ unsigned long mem_pd_mck : 1;
5605+ unsigned long mem_pd_ma : 1;
5606+ unsigned long mem_pd_mdq : 1;
5607+ unsigned long mem_tristate_mck : 1;
5608+ unsigned long mem_tristate_ma : 1;
5609+ unsigned long mem_tristate_mcke : 1;
5610+ unsigned long mem_invert_mck : 1;
5611+ } mem_ext_cntl_t;
5612+
5613+typedef union {
5614+ unsigned long val : 32;
5615+ mem_ext_cntl_t f;
5616+} mem_ext_cntl_u;
5617+
5618+typedef struct _mc_ext_mem_location_t {
5619+ unsigned long mc_ext_mem_start : 16;
5620+ unsigned long mc_ext_mem_top : 16;
5621+ } mc_ext_mem_location_t;
5622+
5623+typedef union {
5624+ unsigned long val : 32;
5625+ mc_ext_mem_location_t f;
5626+} mc_ext_mem_location_u;
5627+
5628+typedef struct _mem_ext_timing_cntl_t {
5629+ unsigned long mem_trp : 2;
5630+ unsigned long mem_trcd : 2;
5631+ unsigned long mem_tras : 3;
5632+ unsigned long : 1;
5633+ unsigned long mem_trrd : 2;
5634+ unsigned long mem_tr2w : 2;
5635+ unsigned long mem_twr : 2;
5636+ unsigned long : 4;
5637+ unsigned long mem_twr_mode : 1;
5638+ unsigned long : 1;
5639+ unsigned long mem_refresh_dis : 1;
5640+ unsigned long : 3;
5641+ unsigned long mem_refresh_rate : 8;
5642+ } mem_ext_timing_cntl_t;
5643+
5644+typedef union {
5645+ unsigned long val : 32;
5646+ mem_ext_timing_cntl_t f;
5647+} mem_ext_timing_cntl_u;
5648+
5649+typedef struct _mem_sdram_mode_reg_t {
5650+ unsigned long mem_mode_reg : 14;
5651+ unsigned long : 2;
5652+ unsigned long mem_read_latency : 2;
5653+ unsigned long mem_schmen_latency : 2;
5654+ unsigned long mem_cas_latency : 2;
5655+ unsigned long mem_schmen_extend : 1;
5656+ unsigned long : 8;
5657+ unsigned long mem_sdram_reset : 1;
5658+ } mem_sdram_mode_reg_t;
5659+
5660+typedef union {
5661+ unsigned long val : 32;
5662+ mem_sdram_mode_reg_t f;
5663+} mem_sdram_mode_reg_u;
5664+
5665+typedef struct _mem_io_cntl_t {
5666+ unsigned long mem_sn_mck : 4;
5667+ unsigned long mem_sn_ma : 4;
5668+ unsigned long mem_sn_mdq : 4;
5669+ unsigned long mem_srn_mck : 1;
5670+ unsigned long mem_srn_ma : 1;
5671+ unsigned long mem_srn_mdq : 1;
5672+ unsigned long : 1;
5673+ unsigned long mem_sp_mck : 4;
5674+ unsigned long mem_sp_ma : 4;
5675+ unsigned long mem_sp_mdq : 4;
5676+ unsigned long mem_srp_mck : 1;
5677+ unsigned long mem_srp_ma : 1;
5678+ unsigned long mem_srp_mdq : 1;
5679+ unsigned long : 1;
5680+ } mem_io_cntl_t;
5681+
5682+typedef union {
5683+ unsigned long val : 32;
5684+ mem_io_cntl_t f;
5685+} mem_io_cntl_u;
5686+
5687+typedef struct _mc_debug_t {
5688+ unsigned long mc_debug : 32;
5689+ } mc_debug_t;
5690+
5691+typedef union {
5692+ unsigned long val : 32;
5693+ mc_debug_t f;
5694+} mc_debug_u;
5695+
5696+typedef struct _mc_bist_ctrl_t {
5697+ unsigned long mc_bist_ctrl : 32;
5698+ } mc_bist_ctrl_t;
5699+
5700+typedef union {
5701+ unsigned long val : 32;
5702+ mc_bist_ctrl_t f;
5703+} mc_bist_ctrl_u;
5704+
5705+typedef struct _mc_bist_collar_read_t {
5706+ unsigned long mc_bist_collar_read : 32;
5707+ } mc_bist_collar_read_t;
5708+
5709+typedef union {
5710+ unsigned long val : 32;
5711+ mc_bist_collar_read_t f;
5712+} mc_bist_collar_read_u;
5713+
5714+typedef struct _tc_mismatch_t {
5715+ unsigned long tc_mismatch : 24;
5716+ unsigned long : 8;
5717+ } tc_mismatch_t;
5718+
5719+typedef union {
5720+ unsigned long val : 32;
5721+ tc_mismatch_t f;
5722+} tc_mismatch_u;
5723+
5724+typedef struct _mc_perf_mon_cntl_t {
5725+ unsigned long clr_perf : 1;
5726+ unsigned long en_perf : 1;
5727+ unsigned long : 2;
5728+ unsigned long perf_op_a : 2;
5729+ unsigned long perf_op_b : 2;
5730+ unsigned long : 8;
5731+ unsigned long monitor_period : 8;
5732+ unsigned long perf_count_a_overflow : 1;
5733+ unsigned long perf_count_b_overflow : 1;
5734+ unsigned long : 6;
5735+ } mc_perf_mon_cntl_t;
5736+
5737+typedef union {
5738+ unsigned long val : 32;
5739+ mc_perf_mon_cntl_t f;
5740+} mc_perf_mon_cntl_u;
5741+
5742+typedef struct _mc_perf_counters_t {
5743+ unsigned long mc_perf_counter_a : 16;
5744+ unsigned long mc_perf_counter_b : 16;
5745+ } mc_perf_counters_t;
5746+
5747+typedef union {
5748+ unsigned long val : 32;
5749+ mc_perf_counters_t f;
5750+} mc_perf_counters_u;
5751+
5752+typedef struct _wait_until_t {
5753+ unsigned long wait_crtc_pflip : 1;
5754+ unsigned long wait_re_crtc_vline : 1;
5755+ unsigned long wait_fe_crtc_vline : 1;
5756+ unsigned long wait_crtc_vline : 1;
5757+ unsigned long wait_dma_viph0_idle : 1;
5758+ unsigned long wait_dma_viph1_idle : 1;
5759+ unsigned long wait_dma_viph2_idle : 1;
5760+ unsigned long wait_dma_viph3_idle : 1;
5761+ unsigned long wait_dma_vid_idle : 1;
5762+ unsigned long wait_dma_gui_idle : 1;
5763+ unsigned long wait_cmdfifo : 1;
5764+ unsigned long wait_ov0_flip : 1;
5765+ unsigned long wait_ov0_slicedone : 1;
5766+ unsigned long : 1;
5767+ unsigned long wait_2d_idle : 1;
5768+ unsigned long wait_3d_idle : 1;
5769+ unsigned long wait_2d_idleclean : 1;
5770+ unsigned long wait_3d_idleclean : 1;
5771+ unsigned long wait_host_idleclean : 1;
5772+ unsigned long wait_extern_sig : 1;
5773+ unsigned long cmdfifo_entries : 7;
5774+ unsigned long : 3;
5775+ unsigned long wait_both_crtc_pflip : 1;
5776+ unsigned long eng_display_select : 1;
5777+ } wait_until_t;
5778+
5779+typedef union {
5780+ unsigned long val : 32;
5781+ wait_until_t f;
5782+} wait_until_u;
5783+
5784+typedef struct _isync_cntl_t {
5785+ unsigned long isync_any2d_idle3d : 1;
5786+ unsigned long isync_any3d_idle2d : 1;
5787+ unsigned long isync_trig2d_idle3d : 1;
5788+ unsigned long isync_trig3d_idle2d : 1;
5789+ unsigned long isync_wait_idlegui : 1;
5790+ unsigned long isync_cpscratch_idlegui : 1;
5791+ unsigned long : 26;
5792+ } isync_cntl_t;
5793+
5794+typedef union {
5795+ unsigned long val : 32;
5796+ isync_cntl_t f;
5797+} isync_cntl_u;
5798+
5799+typedef struct _rbbm_guicntl_t {
5800+ unsigned long host_data_swap : 2;
5801+ unsigned long : 30;
5802+ } rbbm_guicntl_t;
5803+
5804+typedef union {
5805+ unsigned long val : 32;
5806+ rbbm_guicntl_t f;
5807+} rbbm_guicntl_u;
5808+
5809+typedef struct _rbbm_status_t {
5810+ unsigned long cmdfifo_avail : 7;
5811+ unsigned long : 1;
5812+ unsigned long hirq_on_rbb : 1;
5813+ unsigned long cprq_on_rbb : 1;
5814+ unsigned long cfrq_on_rbb : 1;
5815+ unsigned long hirq_in_rtbuf : 1;
5816+ unsigned long cprq_in_rtbuf : 1;
5817+ unsigned long cfrq_in_rtbuf : 1;
5818+ unsigned long cf_pipe_busy : 1;
5819+ unsigned long eng_ev_busy : 1;
5820+ unsigned long cp_cmdstrm_busy : 1;
5821+ unsigned long e2_busy : 1;
5822+ unsigned long rb2d_busy : 1;
5823+ unsigned long rb3d_busy : 1;
5824+ unsigned long se_busy : 1;
5825+ unsigned long re_busy : 1;
5826+ unsigned long tam_busy : 1;
5827+ unsigned long tdm_busy : 1;
5828+ unsigned long pb_busy : 1;
5829+ unsigned long : 6;
5830+ unsigned long gui_active : 1;
5831+ } rbbm_status_t;
5832+
5833+typedef union {
5834+ unsigned long val : 32;
5835+ rbbm_status_t f;
5836+} rbbm_status_u;
5837+
5838+typedef struct _rbbm_cntl_t {
5839+ unsigned long rb_settle : 4;
5840+ unsigned long abortclks_hi : 3;
5841+ unsigned long : 1;
5842+ unsigned long abortclks_cp : 3;
5843+ unsigned long : 1;
5844+ unsigned long abortclks_cfifo : 3;
5845+ unsigned long : 2;
5846+ unsigned long cpq_data_swap : 1;
5847+ unsigned long : 3;
5848+ unsigned long no_abort_idct : 1;
5849+ unsigned long no_abort_bios : 1;
5850+ unsigned long no_abort_fb : 1;
5851+ unsigned long no_abort_cp : 1;
5852+ unsigned long no_abort_hi : 1;
5853+ unsigned long no_abort_hdp : 1;
5854+ unsigned long no_abort_mc : 1;
5855+ unsigned long no_abort_aic : 1;
5856+ unsigned long no_abort_vip : 1;
5857+ unsigned long no_abort_disp : 1;
5858+ unsigned long no_abort_cg : 1;
5859+ } rbbm_cntl_t;
5860+
5861+typedef union {
5862+ unsigned long val : 32;
5863+ rbbm_cntl_t f;
5864+} rbbm_cntl_u;
5865+
5866+typedef struct _rbbm_soft_reset_t {
5867+ unsigned long soft_reset_cp : 1;
5868+ unsigned long soft_reset_hi : 1;
5869+ unsigned long reserved3 : 3;
5870+ unsigned long soft_reset_e2 : 1;
5871+ unsigned long reserved2 : 2;
5872+ unsigned long soft_reset_mc : 1;
5873+ unsigned long reserved1 : 2;
5874+ unsigned long soft_reset_disp : 1;
5875+ unsigned long soft_reset_cg : 1;
5876+ unsigned long : 19;
5877+ } rbbm_soft_reset_t;
5878+
5879+typedef union {
5880+ unsigned long val : 32;
5881+ rbbm_soft_reset_t f;
5882+} rbbm_soft_reset_u;
5883+
5884+typedef struct _nqwait_until_t {
5885+ unsigned long wait_gui_idle : 1;
5886+ unsigned long : 31;
5887+ } nqwait_until_t;
5888+
5889+typedef union {
5890+ unsigned long val : 32;
5891+ nqwait_until_t f;
5892+} nqwait_until_u;
5893+
5894+typedef struct _rbbm_debug_t {
5895+ unsigned long rbbm_debug : 32;
5896+ } rbbm_debug_t;
5897+
5898+typedef union {
5899+ unsigned long val : 32;
5900+ rbbm_debug_t f;
5901+} rbbm_debug_u;
5902+
5903+typedef struct _rbbm_cmdfifo_addr_t {
5904+ unsigned long cmdfifo_addr : 6;
5905+ unsigned long : 26;
5906+ } rbbm_cmdfifo_addr_t;
5907+
5908+typedef union {
5909+ unsigned long val : 32;
5910+ rbbm_cmdfifo_addr_t f;
5911+} rbbm_cmdfifo_addr_u;
5912+
5913+typedef struct _rbbm_cmdfifo_datal_t {
5914+ unsigned long cmdfifo_datal : 32;
5915+ } rbbm_cmdfifo_datal_t;
5916+
5917+typedef union {
5918+ unsigned long val : 32;
5919+ rbbm_cmdfifo_datal_t f;
5920+} rbbm_cmdfifo_datal_u;
5921+
5922+typedef struct _rbbm_cmdfifo_datah_t {
5923+ unsigned long cmdfifo_datah : 12;
5924+ unsigned long : 20;
5925+ } rbbm_cmdfifo_datah_t;
5926+
5927+typedef union {
5928+ unsigned long val : 32;
5929+ rbbm_cmdfifo_datah_t f;
5930+} rbbm_cmdfifo_datah_u;
5931+
5932+typedef struct _rbbm_cmdfifo_stat_t {
5933+ unsigned long cmdfifo_rptr : 6;
5934+ unsigned long : 2;
5935+ unsigned long cmdfifo_wptr : 6;
5936+ unsigned long : 18;
5937+ } rbbm_cmdfifo_stat_t;
5938+
5939+typedef union {
5940+ unsigned long val : 32;
5941+ rbbm_cmdfifo_stat_t f;
5942+} rbbm_cmdfifo_stat_u;
5943+
5944+typedef struct _clk_pin_cntl_t {
5945+ unsigned long osc_en : 1;
5946+ unsigned long osc_gain : 5;
5947+ unsigned long dont_use_xtalin : 1;
5948+ unsigned long xtalin_pm_en : 1;
5949+ unsigned long xtalin_dbl_en : 1;
5950+ unsigned long : 7;
5951+ unsigned long cg_debug : 16;
5952+ } clk_pin_cntl_t;
5953+
5954+typedef union {
5955+ unsigned long val : 32;
5956+ clk_pin_cntl_t f;
5957+} clk_pin_cntl_u;
5958+
5959+typedef struct _pll_ref_fb_div_t {
5960+ unsigned long pll_ref_div : 4;
5961+ unsigned long : 4;
5962+ unsigned long pll_fb_div_int : 6;
5963+ unsigned long : 2;
5964+ unsigned long pll_fb_div_frac : 3;
5965+ unsigned long : 1;
5966+ unsigned long pll_reset_time : 4;
5967+ unsigned long pll_lock_time : 8;
5968+ } pll_ref_fb_div_t;
5969+
5970+typedef union {
5971+ unsigned long val : 32;
5972+ pll_ref_fb_div_t f;
5973+} pll_ref_fb_div_u;
5974+
5975+typedef struct _pll_cntl_t {
5976+ unsigned long pll_pwdn : 1;
5977+ unsigned long pll_reset : 1;
5978+ unsigned long pll_pm_en : 1;
5979+ unsigned long pll_mode : 1;
5980+ unsigned long pll_refclk_sel : 1;
5981+ unsigned long pll_fbclk_sel : 1;
5982+ unsigned long pll_tcpoff : 1;
5983+ unsigned long pll_pcp : 3;
5984+ unsigned long pll_pvg : 3;
5985+ unsigned long pll_vcofr : 1;
5986+ unsigned long pll_ioffset : 2;
5987+ unsigned long pll_pecc_mode : 2;
5988+ unsigned long pll_pecc_scon : 2;
5989+ unsigned long pll_dactal : 4;
5990+ unsigned long pll_cp_clip : 2;
5991+ unsigned long pll_conf : 3;
5992+ unsigned long pll_mbctrl : 2;
5993+ unsigned long pll_ring_off : 1;
5994+ } pll_cntl_t;
5995+
5996+typedef union {
5997+ unsigned long val : 32;
5998+ pll_cntl_t f;
5999+} pll_cntl_u;
6000+
6001+typedef struct _sclk_cntl_t {
6002+ unsigned long sclk_src_sel : 2;
6003+ unsigned long : 2;
6004+ unsigned long sclk_post_div_fast : 4;
6005+ unsigned long sclk_clkon_hys : 3;
6006+ unsigned long sclk_post_div_slow : 4;
6007+ unsigned long disp_cg_ok2switch_en : 1;
6008+ unsigned long sclk_force_reg : 1;
6009+ unsigned long sclk_force_disp : 1;
6010+ unsigned long sclk_force_mc : 1;
6011+ unsigned long sclk_force_extmc : 1;
6012+ unsigned long sclk_force_cp : 1;
6013+ unsigned long sclk_force_e2 : 1;
6014+ unsigned long sclk_force_e3 : 1;
6015+ unsigned long sclk_force_idct : 1;
6016+ unsigned long sclk_force_bist : 1;
6017+ unsigned long busy_extend_cp : 1;
6018+ unsigned long busy_extend_e2 : 1;
6019+ unsigned long busy_extend_e3 : 1;
6020+ unsigned long busy_extend_idct : 1;
6021+ unsigned long : 3;
6022+ } sclk_cntl_t;
6023+
6024+typedef union {
6025+ unsigned long val : 32;
6026+ sclk_cntl_t f;
6027+} sclk_cntl_u;
6028+
6029+typedef struct _pclk_cntl_t {
6030+ unsigned long pclk_src_sel : 2;
6031+ unsigned long : 2;
6032+ unsigned long pclk_post_div : 4;
6033+ unsigned long : 8;
6034+ unsigned long pclk_force_disp : 1;
6035+ unsigned long : 15;
6036+ } pclk_cntl_t;
6037+
6038+typedef union {
6039+ unsigned long val : 32;
6040+ pclk_cntl_t f;
6041+} pclk_cntl_u;
6042+
6043+typedef struct _clk_test_cntl_t {
6044+ unsigned long testclk_sel : 4;
6045+ unsigned long : 3;
6046+ unsigned long start_check_freq : 1;
6047+ unsigned long tstcount_rst : 1;
6048+ unsigned long : 15;
6049+ unsigned long test_count : 8;
6050+ } clk_test_cntl_t;
6051+
6052+typedef union {
6053+ unsigned long val : 32;
6054+ clk_test_cntl_t f;
6055+} clk_test_cntl_u;
6056+
6057+typedef struct _pwrmgt_cntl_t {
6058+ unsigned long pwm_enable : 1;
6059+ unsigned long : 1;
6060+ unsigned long pwm_mode_req : 2;
6061+ unsigned long pwm_wakeup_cond : 2;
6062+ unsigned long pwm_fast_noml_hw_en : 1;
6063+ unsigned long pwm_noml_fast_hw_en : 1;
6064+ unsigned long pwm_fast_noml_cond : 4;
6065+ unsigned long pwm_noml_fast_cond : 4;
6066+ unsigned long pwm_idle_timer : 8;
6067+ unsigned long pwm_busy_timer : 8;
6068+ } pwrmgt_cntl_t;
6069+
6070+typedef union {
6071+ unsigned long val : 32;
6072+ pwrmgt_cntl_t f;
6073+} pwrmgt_cntl_u;
6074+
6075+typedef struct _pwrmgt_status_t {
6076+ unsigned long pwm_mode : 2;
6077+ unsigned long : 30;
6078+ } pwrmgt_status_t;
6079+
6080+typedef union {
6081+ unsigned long val : 32;
6082+ pwrmgt_status_t f;
6083+} pwrmgt_status_u;
6084+
6085+typedef struct _cursor_offset_t {
6086+ unsigned long cur_offset : 24;
6087+ unsigned long cur_x_offset : 4;
6088+ unsigned long cur_y_offset : 4;
6089+} cursor_offset_t;
6090+
6091+typedef union {
6092+ unsigned long val : 32;
6093+ cursor_offset_t f;
6094+} cursor_offset_u;
6095+
6096+typedef struct _cursor_h_pos_t {
6097+ unsigned long cur_h_start : 10;
6098+ unsigned long : 6;
6099+ unsigned long cur_h_end : 10;
6100+ unsigned long : 5;
6101+ unsigned long cur_en : 1;
6102+} cursor_h_pos_t;
6103+
6104+typedef union {
6105+ unsigned long val : 32;
6106+ cursor_h_pos_t f;
6107+} cursor_h_pos_u;
6108+
6109+typedef struct _cursor_v_pos_t {
6110+ unsigned long cur_v_start : 10;
6111+ unsigned long : 6;
6112+ unsigned long cur_v_end : 10;
6113+ unsigned long : 6;
6114+} cursor_v_pos_t;
6115+
6116+typedef union {
6117+ unsigned long val : 32;
6118+ cursor_v_pos_t f;
6119+} cursor_v_pos_u;
6120+
6121+typedef struct _cursor_color_t {
6122+ unsigned long cur_color_r : 8;
6123+ unsigned long cur_color_g : 8;
6124+ unsigned long cur_color_b : 8;
6125+ unsigned long : 8;
6126+} cursor_color_t;
6127+
6128+typedef union {
6129+ unsigned long val : 32;
6130+ cursor_color_t f;
6131+} cursor_color_u;
6132+
6133+#endif
6134--- /dev/null
6135+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_stub.c
6136@@ -0,0 +1,95 @@
6137+/*
6138+ * Copyright © 2007 Manuel Teira
6139+ *
6140+ * Permission to use, copy, modify, distribute, and sell this software and its
6141+ * documentation for any purpose is hereby granted without fee, provided that
6142+ * the above copyright notice appear in all copies and that both that
6143+ * copyright notice and this permission notice appear in supporting
6144+ * documentation, and that the name of Manuel Teira not be used in
6145+ * advertising or publicity pertaining to distribution of the software without
6146+ * specific, written prior permission. Manuel Teira makes no
6147+ * representations about the suitability of this software for any purpose. It
6148+ * is provided "as is" without express or implied warranty.
6149+ *
6150+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
6151+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
6152+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
6153+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
6154+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
6155+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
6156+ * PERFORMANCE OF THIS SOFTWARE.
6157+ */
6158+
6159+#ifdef HAVE_CONFIG_H
6160+#include <kdrive-config.h>
6161+#endif
6162+#include "imageon.h"
6163+#include "imageon_regs.h"
6164+#include "klinux.h"
6165+
6166+extern W100CardEntry w100_cards[];
6167+
6168+static Bool
6169+FindW100(CARD16 vendor, CARD16 device, KdCardAttr * attr)
6170+{
6171+ CARD8 *mmio;
6172+ CARD32 chip_id;
6173+ Bool found = FALSE;
6174+
6175+ mmio = KdMapDevice(W100_REG_BASE, W100_REG_SIZE);
6176+ KdSetMappedMode((CARD32) mmio, W100_REG_SIZE,
6177+ KD_MAPPED_MODE_REGISTERS);
6178+
6179+ chip_id = (*(VOL32 *)(mmio + mmCHIP_ID));
6180+ if ((vendor | (device << 16)) == chip_id) {
6181+ ErrorF("(I) Found W100 Chip ID: %08x\n\n", chip_id);
6182+ attr->deviceID = device;
6183+ attr->vendorID = vendor;
6184+ found = TRUE;
6185+ }
6186+ KdUnmapDevice(mmio, W100_REG_SIZE);
6187+ return found;
6188+}
6189+
6190+
6191+void
6192+InitCard(char *name)
6193+{
6194+ int i;
6195+ W100CardEntry *entry;
6196+ KdCardAttr attr;
6197+
6198+ for (entry = w100_cards; entry->name; entry++) {
6199+ if (FindW100(entry->vendor, entry->device, &attr)) {
6200+ KdCardInfoAdd(&W100Funcs, &attr, 0);
6201+ break;
6202+ }
6203+ }
6204+}
6205+
6206+void
6207+InitOutput(ScreenInfo * pScreenInfo, int argc, char **argv)
6208+{
6209+ KdInitOutput(pScreenInfo, argc, argv);
6210+}
6211+
6212+void
6213+InitInput(int argc, char **argv)
6214+{
6215+ KdInitInput(&LinuxMouseFuncs, &LinuxKeyboardFuncs);
6216+#ifdef TOUCHSCREEN
6217+ KdAddMouseDriver(&TsFuncs);
6218+#endif
6219+}
6220+
6221+void
6222+ddxUseMsg(void)
6223+{
6224+ KdUseMsg();
6225+}
6226+
6227+int
6228+ddxProcessArgument(int argc, char **argv, int i)
6229+{
6230+ return KdProcessArgument(argc, argv, i);
6231+}
6232--- /dev/null
6233+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_support.c
6234@@ -0,0 +1,1438 @@
6235+/*
6236+ * Copyright © 2007 Manuel Teira
6237+ *
6238+ * Permission to use, copy, modify, distribute, and sell this software and its
6239+ * documentation for any purpose is hereby granted without fee, provided that
6240+ * the above copyright notice appear in all copies and that both that
6241+ * copyright notice and this permission notice appear in supporting
6242+ * documentation, and that the name of Manuel Teira not be used in
6243+ * advertising or publicity pertaining to distribution of the software without
6244+ * specific, written prior permission. Manuel Teira makes no
6245+ * representations about the suitability of this software for any purpose. It
6246+ * is provided "as is" without express or implied warranty.
6247+ *
6248+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
6249+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
6250+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
6251+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
6252+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
6253+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
6254+ * PERFORMANCE OF THIS SOFTWARE.
6255+ */
6256+
6257+#ifdef HAVE_CONFIG_H
6258+#include <kdrive-config.h>
6259+#endif
6260+
6261+#include <sys/time.h>
6262+
6263+#include "imageon.h"
6264+#include "imageon_regs.h"
6265+#include "imageon_const.h"
6266+
6267+CARD8 W100SolidRop[16] = {
6268+ /* GXclear */ 0x00, /* 0 */
6269+ /* GXand */ 0xa0, /* src AND dst */
6270+ /* GXandReverse */ 0x50, /* src AND NOT dst */
6271+ /* GXcopy */ 0xf0, /* src */
6272+ /* GXandInverted */ 0x0a, /* NOT src AND dst */
6273+ /* GXnoop */ 0xaa, /* dst */
6274+ /* GXxor */ 0x5a, /* src XOR dst */
6275+ /* GXor */ 0xfa, /* src OR dst */
6276+ /* GXnor */ 0x05, /* NOT src AND NOT dst */
6277+ /* GXequiv */ 0xa5, /* NOT src XOR dst */
6278+ /* GXinvert */ 0x55, /* NOT dst */
6279+ /* GXorReverse */ 0xf5, /* src OR NOT dst */
6280+ /* GXcopyInverted */ 0x0f, /* NOT src */
6281+ /* GXorInverted */ 0xaf, /* NOT src OR dst */
6282+ /* GXnand */ 0x5f, /* NOT src OR NOT dst */
6283+ /* GXset */ 0xff, /* 1 */
6284+};
6285+
6286+CARD8 W100BltRop[16] = {
6287+ /* GXclear */ 0x00, /* 0 */
6288+ /* GXand */ 0x88, /* src AND dst */
6289+ /* GXandReverse */ 0x44, /* src AND NOT dst */
6290+ /* GXcopy */ 0xcc, /* src */
6291+ /* GXandInverted */ 0x22, /* NOT src AND dst */
6292+ /* GXnoop */ 0xaa, /* dst */
6293+ /* GXxor */ 0x66, /* src XOR dst */
6294+ /* GXor */ 0xee, /* src OR dst */
6295+ /* GXnor */ 0x11, /* NOT src AND NOT dst */
6296+ /* GXequiv */ 0x99, /* NOT src XOR dst */
6297+ /* GXinvert */ 0x55, /* NOT dst */
6298+ /* GXorReverse */ 0xdd, /* src OR NOT dst */
6299+ /* GXcopyInverted */ 0x33, /* NOT src */
6300+ /* GXorInverted */ 0xbb, /* NOT src OR dst */
6301+ /* GXnand */ 0x77, /* NOT src OR NOT dst */
6302+ /* GXset */ 0xff, /* 1 */
6303+};
6304+
6305+extern W100ModeSpec w100_modes[];
6306+extern W100StartupInfo w100StartupInfo;
6307+
6308+void W100DisableDisplayUpdate(W100CardInfo *w100c)
6309+{
6310+ disp_db_buf_cntl_wr_u disp_db_buf_cntl;
6311+
6312+ disp_db_buf_cntl.f.db_buf_cntl = 30;
6313+ disp_db_buf_cntl.f.en_db_buf = 0;
6314+ disp_db_buf_cntl.f.update_db_buf = 0;
6315+ MMIO_OUT32(mmDISP_DB_BUF_CNTL, disp_db_buf_cntl.val);
6316+}
6317+
6318+void W100EnableDisplayUpdate(W100CardInfo *w100c)
6319+{
6320+ disp_db_buf_cntl_wr_u disp_db_buf_cntl;
6321+
6322+ disp_db_buf_cntl.f.db_buf_cntl = 30;
6323+ disp_db_buf_cntl.f.en_db_buf = 1;
6324+ disp_db_buf_cntl.f.update_db_buf = 1;
6325+ MMIO_OUT32(mmDISP_DB_BUF_CNTL, disp_db_buf_cntl.val);
6326+}
6327+
6328+void W100SetupGraphicEngine(W100CardInfo *w100c)
6329+{
6330+ eng_cntl_u eng_cntl;
6331+ sc_bottom_right_u bottomright;
6332+ rbbm_cntl_u rbbm_cntl;
6333+ dst_pitch_u dpitch;
6334+ dst_offset_u doffset;
6335+ src_pitch_u spitch;
6336+ src_offset_u soffset;
6337+ sc_top_left_u tl;
6338+ sc_bottom_right_u br;
6339+ src_sc_bottom_right_u srcbr;
6340+ dp_gui_master_cntl_u gmc;
6341+ dp_mix_u dp_mix;
6342+ dp_cntl_u dp_cntl;
6343+ dp_datatype_u dp_datatype;
6344+
6345+ DBG_IMAGEON(("W100SetupGraphicEngine(offset:%p, pitch:%d)\n",
6346+ w100c->hw_window.offset,
6347+ w100c->hw_window.width));
6348+
6349+ eng_cntl.val = MMIO_IN32(mmENG_CNTL);
6350+ eng_cntl.f.erc_reg_wr_ws = 0;
6351+ MMIO_OUT32(mmENG_CNTL, eng_cntl.val);
6352+
6353+ rbbm_cntl.val = 0;
6354+ rbbm_cntl.f.abortclks_hi = 4;
6355+ rbbm_cntl.f.abortclks_cp = 4;
6356+ rbbm_cntl.f.abortclks_cfifo = 2;
6357+ MMIO_OUT32(mmRBBM_CNTL, rbbm_cntl.val);
6358+
6359+ bottomright.val = 0;
6360+ bottomright.f.sc_bottom = 0x1fff;
6361+ bottomright.f.sc_right = 0x1fff;
6362+ MMIO_OUT32(mmDEFAULT_SC_BOTTOM_RIGHT, bottomright.val);
6363+
6364+ dpitch.val = 0;
6365+ dpitch.f.dst_pitch = w100c->hw_window.width;
6366+ MMIO_OUT32(mmDST_PITCH, dpitch.val);
6367+
6368+ doffset.val = 0;
6369+ doffset.f.dst_offset = (CARD32) w100c->hw_window.offset;
6370+ MMIO_OUT32(mmDST_OFFSET, doffset.val);
6371+
6372+ spitch.val = 0;
6373+ spitch.f.src_pitch = w100c->hw_window.width;
6374+ MMIO_OUT32(mmSRC_PITCH, spitch.val);
6375+ soffset.val = 0;
6376+ soffset.f.src_offset = (CARD32) w100c->hw_window.offset;
6377+ MMIO_OUT32(mmSRC_OFFSET, soffset.val);
6378+
6379+ tl.f.sc_left = tl.f.sc_top = 0;
6380+ br.f.sc_right = br.f.sc_bottom = 0x1fff;
6381+ MMIO_OUT32(mmSC_TOP_LEFT, tl.val);
6382+ MMIO_OUT32(mmSC_BOTTOM_RIGHT, br.val);
6383+
6384+ srcbr.f.sc_right = srcbr.f.sc_bottom = 0x1fff;
6385+ MMIO_OUT32(mmSRC_SC_BOTTOM_RIGHT, br.val);
6386+
6387+ gmc.val = dp_datatype.val = dp_mix.val = dp_cntl.val = 0;
6388+
6389+ dp_cntl.f.dst_x_dir = 1;
6390+ dp_cntl.f.dst_y_dir = 1;
6391+ dp_cntl.f.src_x_dir = 1;
6392+ dp_cntl.f.src_y_dir = 1;
6393+ dp_cntl.f.dst_major_x = 1;
6394+ dp_cntl.f.src_major_x = 1;
6395+ MMIO_OUT32(mmDP_CNTL, dp_cntl.val);
6396+
6397+ gmc.f.gmc_src_pitch_offset_cntl = 1;
6398+ gmc.f.gmc_dst_pitch_offset_cntl = 1;
6399+ gmc.f.gmc_src_clipping = 1;
6400+ gmc.f.gmc_dst_clipping = 1;
6401+ gmc.f.gmc_brush_datatype = DP_BRUSH_SOLIDCOLOR;
6402+ gmc.f.gmc_dst_datatype = DP_DST_16BPP_1555;
6403+ gmc.f.gmc_src_datatype = DP_SRC_SOLID_COLOR_BLT;
6404+ gmc.f.gmc_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
6405+ gmc.f.gmc_default_sel = 0;
6406+ gmc.f.gmc_rop3 = W100SolidRop[GXcopy];
6407+ gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
6408+ gmc.f.gmc_clr_cmp_fcn_dis = 1;
6409+ gmc.f.gmc_wr_msk_dis = 1;
6410+ gmc.f.gmc_dp_op = DP_OP_ROP;
6411+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, gmc.val);
6412+
6413+ dp_datatype.f.dp_dst_datatype = gmc.f.gmc_dst_datatype;
6414+ dp_datatype.f.dp_brush_datatype = gmc.f.gmc_brush_datatype;
6415+ dp_datatype.f.dp_src2_type = 0;
6416+ dp_datatype.f.dp_src2_datatype = gmc.f.gmc_src_datatype;
6417+ dp_datatype.f.dp_src_datatype = gmc.f.gmc_src_datatype;
6418+ dp_datatype.f.dp_byte_pix_order = gmc.f.gmc_byte_pix_order;
6419+ MMIO_OUT32(mmDP_DATATYPE, dp_datatype.val);
6420+
6421+ dp_mix.f.dp_src_source = gmc.f.gmc_dp_src_source;
6422+ dp_mix.f.dp_src2_source = gmc.f.gmc_dp_src_source;
6423+ dp_mix.f.dp_rop3 = gmc.f.gmc_rop3;
6424+ dp_mix.f.dp_op = gmc.f.gmc_dp_op;
6425+ MMIO_OUT32(mmDP_MIX, dp_mix.val);
6426+}
6427+
6428+void W100ResetGraphicEngine(W100CardInfo *w100c)
6429+{
6430+ rbbm_soft_reset_u sreset;
6431+ sclk_cntl_u sclk_cntl;
6432+ CARD32 restore_sclk;
6433+
6434+ ErrorF("->W100ResetGraphicEngine\n");
6435+ sclk_cntl.val = restore_sclk = MMIO_IN32(mmSCLK_CNTL);
6436+
6437+ sclk_cntl.f.sclk_force_e2 = 1;
6438+ sclk_cntl.f.sclk_force_e3 = 1;
6439+ sclk_cntl.f.sclk_force_idct = 1;
6440+ MMIO_OUT32(mmSCLK_CNTL, sclk_cntl.val);
6441+
6442+ sreset.val = 0;
6443+ sreset.f.soft_reset_e2 = 1;
6444+ MMIO_OUT32(mmRBBM_SOFT_RESET, sreset.val);
6445+ sreset.f.soft_reset_e2 = 0;
6446+ MMIO_OUT32(mmRBBM_SOFT_RESET, 0);
6447+
6448+ MMIO_OUT32(mmSCLK_CNTL, restore_sclk);
6449+ ErrorF("<-W100ResetGraphicEngine\n");
6450+}
6451+
6452+W100ModeSpec *W100GetModeSpec(W100CardInfo *w100c, W100Mode *mode)
6453+{
6454+ W100ModeSpec *modes;
6455+ for (modes = w100_modes; modes->width; modes++) {
6456+ if ((modes->bpp == mode->bpp) &&
6457+ (((modes->width == mode->width) &&
6458+ (modes->height == mode->height)) ||
6459+ ((modes->width == mode->height) &&
6460+ (modes->height == mode->width)))) {
6461+ return modes;
6462+ }
6463+ }
6464+ ErrorF("No matching mode spec for %dx%d@%d\n",
6465+ mode->width, mode->height, mode->bpp);
6466+ return NULL;
6467+}
6468+
6469+W100ModeSpec *W100GetBestMode(W100CardInfo *w100c, int width, int height)
6470+{
6471+ unsigned int best_x = 0xffffffff;
6472+ unsigned int best_y = 0xffffffff;
6473+ W100ModeSpec *modes, *best_mode = NULL;
6474+ for (modes = w100_modes; modes->width; modes++) {
6475+ if (modes->supported) {
6476+ if (((modes->width >= width) && (modes->width < best_x)) &&
6477+ ((modes->height >= height) && (modes->height < best_y))) {
6478+ best_mode = modes;
6479+ best_x = modes->width;
6480+ best_y = modes->height;
6481+ } else if (((modes->width >= height) && (modes->width < best_y)) &&
6482+ ((modes->height >= width) && (modes->height < best_x))) {
6483+ best_mode = modes;
6484+ best_x = modes->height;
6485+ best_y = modes->width;
6486+ }
6487+ }
6488+ }
6489+ if (!best_mode) {
6490+ ErrorF("No matching mode spec for %dx%d\n", width, height);
6491+ }
6492+ return best_mode;
6493+}
6494+
6495+Bool W100GetFbMode(W100CardInfo *w100c, W100Mode *mode)
6496+{
6497+ struct fb_var_screeninfo vinfo;
6498+ int i;
6499+
6500+ if (ioctl(w100c->fbdev.fd, FBIOGET_VSCREENINFO, &vinfo) != 0) {
6501+ ErrorF("Unable to get framebuffer mode\n");
6502+ return FALSE;
6503+ }
6504+
6505+ mode->width = vinfo.xres;
6506+ mode->height = vinfo.yres;
6507+ mode->bpp = vinfo.bits_per_pixel;
6508+}
6509+
6510+Bool W100CheckFbMode(W100CardInfo *w100c, W100ModeSpec *modes)
6511+{
6512+ struct fb_var_screeninfo vinfo;
6513+
6514+ vinfo.xres = vinfo.xres_virtual = modes->width;
6515+ vinfo.yres = vinfo.yres_virtual = modes->height;
6516+ vinfo.bits_per_pixel = modes->bpp;
6517+ vinfo.activate = FB_ACTIVATE_TEST;
6518+
6519+ if (ioctl(w100c->fbdev.fd, FBIOPUT_VSCREENINFO, &vinfo) != 0) {
6520+ ErrorF("(W) Mode %dx%d@%d not supported\n",
6521+ vinfo.xres,
6522+ vinfo.yres,
6523+ vinfo.bits_per_pixel);
6524+ return FALSE;
6525+ }
6526+ DBG_IMAGEON(("(I) Mode %dx%d@%d supported\n",
6527+ vinfo.xres,
6528+ vinfo.yres,
6529+ vinfo.bits_per_pixel));
6530+ return TRUE;
6531+}
6532+
6533+Bool W100SetFbMode(W100CardInfo *w100c)
6534+{
6535+ struct fb_var_screeninfo vinfo;
6536+ int randr = KdSubRotation(w100c->hw_window.randr, w100StartupInfo.randr);
6537+
6538+ if (randr & (RR_Rotate_0 | RR_Rotate_180)) {
6539+ vinfo.xres = vinfo.xres_virtual = w100c->hw_window.mode->width;
6540+ vinfo.yres = vinfo.yres_virtual = w100c->hw_window.mode->height;
6541+ } else {
6542+ vinfo.xres = vinfo.xres_virtual = w100c->hw_window.mode->height;
6543+ vinfo.yres = vinfo.yres_virtual = w100c->hw_window.mode->width;
6544+ }
6545+ vinfo.bits_per_pixel = w100c->hw_window.mode->bpp;
6546+ vinfo.activate = FB_ACTIVATE_NOW;
6547+ int flip = (w100c->hw_window.randr > RR_Rotate_90) ? 1 : 0;
6548+
6549+ DBG_IMAGEON(("Asking framebuffer for mode %dx%d@%d. Flipped:%d\n",
6550+ vinfo.xres, vinfo.yres, vinfo.bits_per_pixel, flip));
6551+ if (ioctl(w100c->fbdev.fd, FBIOPUT_VSCREENINFO, &vinfo) != 0) {
6552+ ErrorF("Error setting mode %dx%d@%d\n",
6553+ vinfo.xres,
6554+ vinfo.yres,
6555+ vinfo.bits_per_pixel);
6556+ return FALSE;
6557+ }
6558+ W100SysFsSet(w100c, W100_SYSFS_BASE "flip", flip ? "1" : "0");
6559+ return TRUE;
6560+}
6561+
6562+void W100SetupGraphicWindow(W100CardInfo *w100c)
6563+{
6564+ DBG_IMAGEON(("W100SetupGraphicWindow(width:%d,height:%d,randr:%d)\n",
6565+ w100c->hw_window.width,
6566+ w100c->hw_window.height,
6567+ w100c->hw_window.randr));
6568+
6569+ if (!W100SetFbMode(w100c)) {
6570+ ErrorF("Error Setting Graphic Window\n");
6571+ }
6572+}
6573+
6574+void W100EnableGraphicWindow(W100CardInfo *w100c)
6575+{
6576+ graphic_ctrl_u gc;
6577+
6578+ gc.val = MMIO_IN32(mmGRAPHIC_CTRL);
6579+ gc.f.en_graphic_crtc = 1;
6580+ gc.f.en_graphic_req = 1;
6581+ W100DisableDisplayUpdate(w100c);
6582+ MMIO_OUT32(mmGRAPHIC_CTRL, gc.val);
6583+ W100EnableDisplayUpdate(w100c);
6584+}
6585+
6586+void W100DisableGraphicWindow(W100CardInfo *w100c)
6587+{
6588+ graphic_ctrl_u gc;
6589+
6590+ gc.val = MMIO_IN32(mmGRAPHIC_CTRL);
6591+ gc.f.en_graphic_crtc = 0;
6592+ gc.f.en_graphic_req = 0;
6593+ W100DisableDisplayUpdate(w100c);
6594+ MMIO_OUT32(mmGRAPHIC_CTRL, gc.val);
6595+ W100EnableDisplayUpdate(w100c);
6596+}
6597+
6598+inline Bool W100WaitCmdFifoEntries(W100CardInfo *w100c, int entries)
6599+{
6600+ rbbm_status_u rbbmStatus;
6601+ TIMEOUT_LOCALS;
6602+
6603+ if (entries > W100_CMDFIFO_SIZE)
6604+ return FALSE;
6605+
6606+ if (entries <= w100c->cmdfifo_entries) {
6607+ w100c->cmdfifo_entries -= entries;
6608+ return TRUE;
6609+ }
6610+
6611+ WHILE_NOT_TIMEOUT(.2) {
6612+ rbbmStatus.val = MMIO_IN32(mmRBBM_STATUS);
6613+ w100c->cmdfifo_entries = rbbmStatus.f.cmdfifo_avail;
6614+ if (w100c->cmdfifo_entries >= entries) {
6615+ break;
6616+ }
6617+ }
6618+ if (TIMEDOUT()) {
6619+ ErrorF("Not enough CMDFIFO entries: %d (%d needed)\n",
6620+ w100c->cmdfifo_entries, entries);
6621+ return FALSE;
6622+ }
6623+ w100c->cmdfifo_entries -= entries;
6624+ return TRUE;
6625+}
6626+
6627+Bool W100WaitIdle(W100CardInfo *w100c)
6628+{
6629+ rbbm_status_u rbbm_status;
6630+ TIMEOUT_LOCALS;
6631+
6632+ DBG_IMAGEON(("W100WaitIdle\n"));
6633+ if (!W100WaitCmdFifoEntries(w100c, W100_CMDFIFO_SIZE)) {
6634+ return FALSE;
6635+ }
6636+
6637+ WHILE_NOT_TIMEOUT(.2) {
6638+ rbbm_status.val = MMIO_IN32(mmRBBM_STATUS);
6639+ if (rbbm_status.f.gui_active == 0) {
6640+ break;
6641+ }
6642+ }
6643+ if (TIMEDOUT()) {
6644+ ErrorF("Timeout waiting for idle. rbbm_status: 0x%08x\n"
6645+ " .cmdfifo_avail : %d\n"
6646+ " .cf_pipe_busy : %d\n"
6647+ " .eng_ev_busy : %d\n"
6648+ " .cp_cmdstrm_busy : %d\n"
6649+ " .e2_busy : %d\n"
6650+ " .rb2d_busy : %d\n"
6651+ " .rb3d_busy : %d\n"
6652+ " .se_busy : %d\n"
6653+ " .re_busy : %d\n"
6654+ " .tam_busy : %d\n"
6655+ " .tdm_busy : %d\n"
6656+ " .pb_busy : %d\n"
6657+ " .gui_active : %d\n",
6658+ rbbm_status.val,
6659+ rbbm_status.f.cmdfifo_avail,
6660+ rbbm_status.f.cf_pipe_busy,
6661+ rbbm_status.f.eng_ev_busy,
6662+ rbbm_status.f.cp_cmdstrm_busy,
6663+ rbbm_status.f.e2_busy,
6664+ rbbm_status.f.rb2d_busy,
6665+ rbbm_status.f.rb3d_busy,
6666+ rbbm_status.f.se_busy,
6667+ rbbm_status.f.re_busy,
6668+ rbbm_status.f.tam_busy,
6669+ rbbm_status.f.tdm_busy,
6670+ rbbm_status.f.pb_busy,
6671+ rbbm_status.f.gui_active);
6672+ ErrorF("Last context: src(datatype:%d,pitch:%d,offset:0x%08x)\n"
6673+ " dst(datatype:%d,pitch:%d,offset:0x%08x)\n"
6674+ " xform(dx:%d,dy:%d)\n"
6675+ " mask(pm:0x%08x,enable:%d)\n",
6676+ w100c->ctx.src.datatype,
6677+ w100c->ctx.src.pitch,
6678+ w100c->ctx.src.offset,
6679+ w100c->ctx.dst.datatype,
6680+ w100c->ctx.dst.pitch,
6681+ w100c->ctx.dst.offset,
6682+ w100c->ctx.xform.dx,
6683+ w100c->ctx.xform.dy,
6684+ w100c->ctx.mask.pm,
6685+ w100c->ctx.mask.enable);
6686+
6687+ return FALSE;
6688+ }
6689+
6690+ return TRUE;
6691+}
6692+
6693+void W100ResetContext(W100CardInfo *w100c)
6694+{
6695+ w100c->ctx.dst.datatype = DP_DST_16BPP_1555;
6696+ w100c->ctx.dst.pitch = 0;
6697+ w100c->ctx.dst.offset = 0;
6698+ w100c->ctx.dst.videomem = 0;
6699+
6700+ w100c->ctx.src.datatype = DP_SRC_COLOR_SAME_AS_DST;
6701+ w100c->ctx.src.pitch = 0;
6702+ w100c->ctx.src.offset = 0;
6703+ w100c->ctx.src.videomem = 0;
6704+
6705+ w100c->ctx.xform.dx = 0;
6706+ w100c->ctx.xform.dy = 0;
6707+ w100c->ctx.xform.randr = 0;
6708+ w100c->ctx.xform.mirror = FALSE;
6709+ w100c->ctx.xform.dataPath = 0x0000003f;
6710+
6711+ w100c->ctx.mask.pm = 0;
6712+ w100c->ctx.mask.enable = FALSE;
6713+}
6714+
6715+CARD32 W100ComputeSolidGmc(W100CardInfo *w100c, CARD8 alu)
6716+{
6717+ dp_gui_master_cntl_u gmc;
6718+
6719+ gmc.val = 0;
6720+ gmc.f.gmc_dst_pitch_offset_cntl = 1;
6721+ gmc.f.gmc_dst_clipping = 0;
6722+ gmc.f.gmc_brush_datatype = DP_BRUSH_SOLIDCOLOR;
6723+ gmc.f.gmc_dst_datatype = w100c->ctx.dst.datatype;
6724+ gmc.f.gmc_dp_op = DP_OP_ROP;
6725+ gmc.f.gmc_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
6726+ gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
6727+ gmc.f.gmc_rop3 = W100SolidRop[alu];
6728+ gmc.f.gmc_clr_cmp_fcn_dis = 1;
6729+ if (w100c->ctx.mask.enable) {
6730+ gmc.f.gmc_wr_msk_dis = 0;
6731+ } else {
6732+ gmc.f.gmc_wr_msk_dis = 1;
6733+ }
6734+ return gmc.val;
6735+}
6736+
6737+CARD32 W100ComputeCopyGmc(W100CardInfo *w100c, CARD8 alu)
6738+{
6739+ dp_gui_master_cntl_u gmc;
6740+
6741+ gmc.val = 0;
6742+ gmc.f.gmc_src_pitch_offset_cntl = 1;
6743+ gmc.f.gmc_dst_pitch_offset_cntl = 1;
6744+ gmc.f.gmc_dst_clipping = 0;
6745+ gmc.f.gmc_src_clipping = 0;
6746+ gmc.f.gmc_src_datatype = w100c->ctx.src.datatype;
6747+ gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
6748+ gmc.f.gmc_brush_datatype = DP_BRUSH_NONE;
6749+ gmc.f.gmc_dst_datatype = w100c->ctx.dst.datatype;
6750+ gmc.f.gmc_dp_op = DP_OP_ROP;
6751+ gmc.f.gmc_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
6752+ gmc.f.gmc_rop3 = W100BltRop[alu];
6753+ gmc.f.gmc_clr_cmp_fcn_dis = 1;
6754+ if (w100c->ctx.mask.enable) {
6755+ gmc.f.gmc_wr_msk_dis = 0;
6756+ } else {
6757+ gmc.f.gmc_wr_msk_dis = 1;
6758+ }
6759+ return gmc.val;
6760+}
6761+
6762+CARD32 W100ComputeAritGmc(W100CardInfo *w100c, CARD8 alu)
6763+{
6764+ dp_gui_master_cntl_u gmc;
6765+
6766+ gmc.val = 0;
6767+ gmc.f.gmc_src_pitch_offset_cntl = 1;
6768+ gmc.f.gmc_dst_pitch_offset_cntl = 1;
6769+ gmc.f.gmc_dst_clipping = 0;
6770+ gmc.f.gmc_src_clipping = 0;
6771+ gmc.f.gmc_src_datatype = w100c->ctx.src.datatype;
6772+ gmc.f.gmc_dst_datatype = w100c->ctx.dst.datatype;
6773+ gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
6774+ gmc.f.gmc_brush_datatype = DP_BRUSH_NONE;
6775+ gmc.f.gmc_dp_op = DP_OP_ARITHMETIC;
6776+ gmc.f.gmc_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
6777+ gmc.f.gmc_rop3 = W100BltRop[alu];
6778+ gmc.f.gmc_clr_cmp_fcn_dis = 1;
6779+ if (w100c->ctx.mask.enable) {
6780+ gmc.f.gmc_wr_msk_dis = 0;
6781+ } else {
6782+ gmc.f.gmc_wr_msk_dis = 1;
6783+ }
6784+ return gmc.val;
6785+}
6786+
6787+void W100SetXForm(W100CardInfo *w100c, int dx, int dy)
6788+{
6789+ dp_cntl_u dp_cntl;
6790+
6791+ w100c->ctx.xform.dx = dx;
6792+ w100c->ctx.xform.dy = dy;
6793+
6794+ dp_cntl.val = 0;
6795+ dp_cntl.f.src_x_dir = 1;
6796+ dp_cntl.f.src_y_dir = 1;
6797+ dp_cntl.f.src_major_x = 1;
6798+ dp_cntl.f.dst_major_x = 1;
6799+
6800+ if (dx >= 0) {
6801+ dp_cntl.f.dst_x_dir = 1;
6802+ } else {
6803+ dp_cntl.f.dst_x_dir = 0;
6804+ }
6805+ if (dy >= 0) {
6806+ dp_cntl.f.dst_y_dir = 1;
6807+ } else {
6808+ dp_cntl.f.dst_y_dir = 0;
6809+ }
6810+ w100c->ctx.xform.dataPath = dp_cntl.val;
6811+}
6812+
6813+void W100SetRotation(W100CardInfo *w100c,
6814+ int randr,
6815+ Bool mirror)
6816+{
6817+ dp_cntl_u dp_cntl;
6818+ w100c->ctx.xform.randr = randr;
6819+ w100c->ctx.xform.mirror = mirror;
6820+ dp_cntl.val = 0;
6821+ dp_cntl.f.src_x_dir = 1;
6822+ dp_cntl.f.src_y_dir = 1;
6823+ dp_cntl.f.src_major_x = 1;
6824+
6825+
6826+ switch (randr & RR_Rotate_All) {
6827+ case RR_Rotate_0:
6828+ dp_cntl.f.dst_x_dir = mirror ? 0 : 1;
6829+ dp_cntl.f.dst_y_dir = 1;
6830+ dp_cntl.f.dst_major_x = 1;
6831+ break;
6832+ case RR_Rotate_90:
6833+ dp_cntl.f.dst_x_dir = 0;
6834+ dp_cntl.f.dst_y_dir = mirror ? 0 : 1;
6835+ dp_cntl.f.dst_major_x = 0;
6836+ break;
6837+ case RR_Rotate_180:
6838+ dp_cntl.f.dst_x_dir = mirror ? 1 : 0;
6839+ dp_cntl.f.dst_y_dir = 0;
6840+ dp_cntl.f.dst_major_x = 1;
6841+ break;
6842+ case RR_Rotate_270:
6843+ dp_cntl.f.dst_x_dir = 1;
6844+ dp_cntl.f.dst_y_dir = mirror ? 1 : 0;
6845+ dp_cntl.f.dst_major_x = 0;
6846+ break;
6847+ }
6848+ w100c->ctx.xform.dataPath = dp_cntl.val;
6849+}
6850+
6851+void W100SetPixelMask(W100CardInfo *w100c, Pixel mask)
6852+{
6853+ if (mask != 0xffffffff) {
6854+ w100c->ctx.mask.enable = TRUE;
6855+ w100c->ctx.mask.pm = mask;
6856+ } else {
6857+ w100c->ctx.mask.enable = FALSE;
6858+ }
6859+
6860+}
6861+
6862+Bool W100SetSource(KdScreenInfo *screen,
6863+ CARD32 srcPitch,
6864+ CARD32 srcOffset,
6865+ CARD8 bpp)
6866+{
6867+ W100CardInfo(screen);
6868+ int i;
6869+ w100c->ctx.src.pitch = srcPitch * 8 / bpp;
6870+ switch (bpp) {
6871+ case 1:
6872+ w100c->ctx.src.datatype = DP_SRC_1BPP_OPA;
6873+ break;
6874+ case 4:
6875+ w100c->ctx.src.datatype = DP_SRC_4BPP;
6876+ break;
6877+ case 12:
6878+ w100c->ctx.src.datatype = DP_SRC_12BPP_PACKED;
6879+ break;
6880+ case 8:
6881+ case 16:
6882+ w100c->ctx.src.datatype = DP_SRC_COLOR_SAME_AS_DST;
6883+ break;
6884+ default:
6885+ return FALSE;
6886+ }
6887+
6888+ for (i = 0; i < screen->num_videomem_areas; i++) {
6889+ KdVideoMemArea *vidmem = screen->videomem_areas[i];
6890+ if ((((CARD8*)srcOffset) >= vidmem->base) &&
6891+ (((CARD8*)srcOffset) <= (vidmem->base + vidmem->size))) {
6892+ w100c->ctx.src.offset = (CARD32) W100_HOST2CARD(srcOffset);
6893+ if (w100c->last_src_videomem != i) {
6894+ W100WaitIdle(w100c);
6895+ }
6896+ w100c->last_src_videomem = i;
6897+ DBG_IMAGEON(("Setting src(pitch:%d,offset:0x%08x,type:%d)\n",
6898+ w100c->ctx.src.pitch,
6899+ w100c->ctx.src.offset,
6900+ w100c->ctx.src.datatype));
6901+ return TRUE;
6902+ }
6903+ }
6904+ return FALSE;
6905+}
6906+
6907+Bool W100SetDestination(KdScreenInfo *screen,
6908+ CARD32 dstPitch,
6909+ CARD32 dstOffset,
6910+ CARD8 bpp)
6911+{
6912+ W100CardInfo(screen);
6913+ int i;
6914+ w100c->ctx.dst.pitch = dstPitch * 8 / bpp;
6915+ switch (bpp) {
6916+ case 8:
6917+ w100c->ctx.dst.datatype = DP_DST_8BPP;
6918+ break;
6919+ case 16:
6920+ w100c->ctx.dst.datatype = DP_DST_16BPP_1555;
6921+ break;
6922+ default:
6923+ return FALSE;
6924+ }
6925+
6926+ for (i = 0; i < screen->num_videomem_areas; i++) {
6927+ KdVideoMemArea *vidmem = screen->videomem_areas[i];
6928+ if ((((CARD8*)dstOffset) >= vidmem->base) &&
6929+ (((CARD8*)dstOffset) <= (vidmem->base + vidmem->size))) {
6930+ w100c->ctx.dst.offset = (CARD32) W100_HOST2CARD(dstOffset);
6931+ if (w100c->last_dst_videomem != i) {
6932+ W100WaitIdle(w100c);
6933+ }
6934+ w100c->last_dst_videomem = i;
6935+ DBG_IMAGEON(("Setting dst(pitch:%d,offset:0x%08x,type:%d)\n",
6936+ w100c->ctx.dst.pitch,
6937+ w100c->ctx.dst.offset,
6938+ w100c->ctx.dst.datatype));
6939+ return TRUE;
6940+ }
6941+ }
6942+ return FALSE;
6943+}
6944+
6945+Bool W100SetSourcePixmap(PixmapPtr pPix)
6946+{
6947+ KdScreenPriv(pPix->drawable.pScreen);
6948+
6949+ return W100SetSource(pScreenPriv->screen,
6950+ pPix->devKind,
6951+ (CARD32) pPix->devPrivate.ptr,
6952+ pPix->drawable.bitsPerPixel);
6953+}
6954+
6955+Bool W100SetDestinationPixmap(PixmapPtr pPix)
6956+{
6957+ KdScreenPriv(pPix->drawable.pScreen);
6958+
6959+ return W100SetDestination(pScreenPriv->screen,
6960+ pPix->devKind,
6961+ (CARD32) pPix->devPrivate.ptr,
6962+ pPix->drawable.bitsPerPixel);
6963+}
6964+
6965+int W100MapToHWX(W100CardInfo *w100c,
6966+ int x, int y, int w, int h)
6967+{
6968+ int tx;
6969+ switch (w100c->hw_window.randr & RR_Rotate_All) {
6970+ case RR_Rotate_0:
6971+ tx = x;
6972+ break;
6973+ case RR_Rotate_90:
6974+ tx = w100c->hw_window.height - (y + h);
6975+ break;
6976+ case RR_Rotate_180:
6977+ tx = w100c->hw_window.width - (x + w);
6978+ break;
6979+ case RR_Rotate_270:
6980+ tx = y;
6981+ break;
6982+ default:
6983+ tx = x;
6984+ }
6985+ return tx;
6986+}
6987+
6988+int W100MapToHWY(W100CardInfo *w100c,
6989+ int x, int y, int w, int h)
6990+{
6991+ int ty;
6992+ switch (w100c->hw_window.randr & RR_Rotate_All) {
6993+ case RR_Rotate_0:
6994+ ty = y;
6995+ break;
6996+ case RR_Rotate_90:
6997+ ty = x;
6998+ break;
6999+ case RR_Rotate_180:
7000+ ty = w100c->hw_window.height - (y + h);
7001+ break;
7002+ case RR_Rotate_270:
7003+ ty = w100c->hw_window.width - (x + w);
7004+ break;
7005+ default:
7006+ ty = y;
7007+ }
7008+ return ty;
7009+}
7010+
7011+int W100MapToHWW(W100CardInfo *w100c,
7012+ int x, int y, int w, int h)
7013+{
7014+ int tw;
7015+ switch (w100c->hw_window.randr & RR_Rotate_All) {
7016+ case RR_Rotate_0:
7017+ case RR_Rotate_180:
7018+ tw = w;
7019+ break;
7020+ case RR_Rotate_90:
7021+ case RR_Rotate_270:
7022+ tw = h;
7023+ break;
7024+ }
7025+ return tw;
7026+}
7027+
7028+int W100MapToHWH(W100CardInfo *w100c,
7029+ int x, int y, int w, int h)
7030+{
7031+ int th;
7032+ switch (w100c->hw_window.randr & RR_Rotate_All) {
7033+ case RR_Rotate_0:
7034+ case RR_Rotate_180:
7035+ th = h;
7036+ break;
7037+ case RR_Rotate_90:
7038+ case RR_Rotate_270:
7039+ th = w;
7040+ break;
7041+ }
7042+ return th;
7043+}
7044+
7045+CARD16 W100XformX(W100CardInfo *w100c,
7046+ CARD16 x, CARD16 y, CARD16 w, CARD16 h)
7047+{
7048+ CARD16 tx;
7049+ switch (w100c->ctx.xform.randr & RR_Rotate_All) {
7050+ case RR_Rotate_0:
7051+ if (w100c->ctx.xform.mirror) {
7052+ tx = x + w - 1;
7053+ } else {
7054+ tx = x;
7055+ }
7056+ break;
7057+ case RR_Rotate_90:
7058+ tx = x + h - 1;
7059+ break;
7060+ case RR_Rotate_180:
7061+ if (w100c->ctx.xform.mirror) {
7062+ tx = x;
7063+ } else {
7064+ tx = x + w - 1;
7065+ }
7066+ break;
7067+ case RR_Rotate_270:
7068+ default:
7069+ tx = x;
7070+ break;
7071+ }
7072+ return tx;
7073+}
7074+
7075+CARD16 W100XformY(W100CardInfo *w100c,
7076+ CARD16 x, CARD16 y, CARD16 w, CARD16 h)
7077+{
7078+ CARD16 ty;
7079+ switch (w100c->ctx.xform.randr & RR_Rotate_All) {
7080+ case RR_Rotate_0:
7081+ ty = y;
7082+ break;
7083+ case RR_Rotate_90:
7084+ if (w100c->ctx.xform.mirror) {
7085+ ty = y + w - 1;
7086+ } else {
7087+ ty = y;
7088+ }
7089+ break;
7090+ case RR_Rotate_180:
7091+ ty = y + h - 1;
7092+ break;
7093+ case RR_Rotate_270:
7094+ default:
7095+ if (w100c->ctx.xform.mirror) {
7096+ ty = y;
7097+ } else {
7098+ ty = y + w - 1;
7099+ }
7100+ break;
7101+ }
7102+ return ty;
7103+}
7104+
7105+CARD16 W100XformW(W100CardInfo *w100c,
7106+ CARD16 x, CARD16 y, CARD16 w, CARD16 h)
7107+{
7108+ CARD16 tw;
7109+
7110+ switch (w100c->ctx.xform.randr & RR_Rotate_All) {
7111+ case RR_Rotate_0:
7112+ case RR_Rotate_180:
7113+ default:
7114+ tw = w;
7115+ break;
7116+ case RR_Rotate_90:
7117+ case RR_Rotate_270:
7118+ tw = h;
7119+ break;
7120+ }
7121+ return tw;
7122+}
7123+
7124+CARD16 W100XformH(W100CardInfo *w100c,
7125+ CARD16 x, CARD16 y, CARD16 w, CARD16 h)
7126+{
7127+ CARD16 th;
7128+
7129+ switch (w100c->ctx.xform.randr & RR_Rotate_All) {
7130+ case RR_Rotate_0:
7131+ case RR_Rotate_180:
7132+ default:
7133+ th = h;
7134+ break;
7135+ case RR_Rotate_90:
7136+ case RR_Rotate_270:
7137+ th = w;
7138+ break;
7139+ }
7140+ return th;
7141+}
7142+
7143+CARD8 W100GetScaler(CARD16 dstsize, CARD16 srcsize)
7144+{
7145+ return W100_MAX(1, W100_MIN(31, ((16 * srcsize) + dstsize - 1) / dstsize));
7146+
7147+}
7148+
7149+CARD16 W100ApplyScaler(CARD16 srcsize, CARD8 scaler)
7150+{
7151+ return ((srcsize * 16) + (scaler - 1)) / scaler;
7152+}
7153+
7154+
7155+static void W100Blt(KdScreenInfo *screen,
7156+ int randr,
7157+ int bpp,
7158+ CARD32 srcOffset,
7159+ CARD16 srcW,
7160+ CARD16 srcH,
7161+ CARD16 srcPitch,
7162+ CARD32 dstOffset,
7163+ CARD16 dstPitch,
7164+ CARD16 dstX,
7165+ CARD16 dstY)
7166+{
7167+ ScreenPtr pScreen = screen->pScreen;
7168+ KdScreenPriv(pScreen);
7169+ W100CardInfo(pScreenPriv);
7170+ CARD16 x, y, w, h;
7171+ int fifoEntries = 9;
7172+ Bool hasXForm = FALSE;
7173+ eng_cntl_u eng_cntl;
7174+ src_x_y_u src_x_y;
7175+ dst_x_y_u dst_x_y;
7176+ src_width_u src_width;
7177+ src_height_u src_height;
7178+ dst_width_height_u dst_width_height;
7179+
7180+ DBG_IMAGEON(("W100Blt(randr:%d,bpp:%d,srcOffset:0x%08x,"
7181+ "srcW:%d,srcH:%d,srcPitch:%d,dstOffset:0x%08x,"
7182+ "dstPitch:%d,dstX:%d,dstY:%d)\n",
7183+ randr, bpp, srcOffset, srcW, srcH,
7184+ srcPitch, dstOffset, dstPitch, dstX, dstY));
7185+
7186+ if (randr & (RR_Rotate_90|RR_Rotate_270)) {
7187+ hasXForm = TRUE;
7188+ eng_cntl.val = w100c->regs.ENG_CNTL;
7189+ eng_cntl.f.dis_rop_src_uses_dst_w_h = 1;
7190+ eng_cntl.f.dis_src_uses_dst_dirmaj = 1;
7191+ fifoEntries += 4;
7192+ }
7193+
7194+ W100ResetContext(w100c);
7195+ W100SetRotation(w100c, randr, FALSE);
7196+ W100SetSource(screen, srcPitch, srcOffset, bpp);
7197+ W100SetDestination(screen, dstPitch, dstOffset, bpp);
7198+
7199+ x = W100XformX(w100c, dstX, dstY, srcW, srcH);
7200+ y = W100XformY(w100c, dstX, dstY, srcW, srcH);
7201+ w = W100XformW(w100c, dstX, dstY, srcW, srcH);
7202+ h = W100XformH(w100c, dstX, dstY, srcW, srcH);
7203+
7204+ src_x_y.f.src_y = 0;
7205+ src_x_y.f.src_x = 0;
7206+ dst_x_y.f.dst_x = x;
7207+ dst_x_y.f.dst_y = y;
7208+ src_width.f.src_width = srcW;
7209+ src_height.f.src_height = srcH;
7210+ dst_width_height.f.dst_height = h;
7211+ dst_width_height.f.dst_width_b0 = w & 0xff;
7212+ dst_width_height.f.dst_width_b1 = (w >> 8) & 0x3f;
7213+
7214+ if (W100WaitCmdFifoEntries(w100c, fifoEntries)) {
7215+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
7216+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
7217+ MMIO_OUT32(mmSRC_PITCH, w100c->ctx.src.pitch);
7218+ MMIO_OUT32(mmSRC_OFFSET, w100c->ctx.src.offset);
7219+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, W100ComputeCopyGmc(w100c, GXcopy));
7220+ MMIO_OUT32(mmDP_CNTL, w100c->ctx.xform.dataPath);
7221+ if (hasXForm) {
7222+ MMIO_OUT32(mmENG_CNTL, eng_cntl.val);
7223+ MMIO_OUT32(mmSRC_WIDTH, src_width.val);
7224+ MMIO_OUT32(mmSRC_HEIGHT, src_height.val);
7225+ }
7226+ MMIO_OUT32(mmSRC_X_Y, src_x_y.val);
7227+ MMIO_OUT32(mmDST_X_Y, dst_x_y.val);
7228+ MMIO_OUT32(mmDST_WIDTH_HEIGHT, dst_width_height.val);
7229+ /* Restore state */
7230+ if (hasXForm) {
7231+ MMIO_OUT32(mmENG_CNTL, w100c->regs.ENG_CNTL);
7232+ }
7233+ } else {
7234+ ErrorF("Unable to perform Blitting\n");
7235+ }
7236+}
7237+
7238+static void W100StretchBlt(KdScreenInfo *screen,
7239+ int randr,
7240+ int bpp,
7241+ CARD32 srcOffset,
7242+ CARD16 srcW,
7243+ CARD16 srcH,
7244+ CARD16 srcPitch,
7245+ CARD32 dstOffset,
7246+ CARD16 dstPitch,
7247+ CARD16 dstX,
7248+ CARD16 dstY,
7249+ CARD8 xscaler,
7250+ CARD8 yscaler)
7251+{
7252+ ScreenPtr pScreen = screen->pScreen;
7253+ KdScreenPriv(pScreen);
7254+ W100CardInfo(pScreenPriv);
7255+ CARD16 x, y, w, h, sw, sh;
7256+ Bool hasXForm = FALSE;
7257+ dp_datatype_u dp_datatype;
7258+ dp_mix_u dp_mix;
7259+ eng_cntl_u eng_cntl;
7260+ e2_arithmetic_cntl_u e2;
7261+ src_inc_u src_inc;
7262+ src_x_y_u src_x_y;
7263+ dst_x_y_u dst_x_y;
7264+ src_width_u src_width;
7265+ src_height_u src_height;
7266+ dst_width_height_u dst_width_height;
7267+ int firstStage = 10;
7268+ int secondStage = 10;
7269+
7270+ DBG_IMAGEON(("W100StretchBlt(randr:%d,bpp:%d,srcOffset:0x%08x,"
7271+ "srcW:%d,srcH:%d,srcPitch:%d,dstOffset:0x%08x,"
7272+ "dstPitch:%d,dstX:%d,dstY:%d,xscaler:%d,yscaler:%d)\n",
7273+ randr, bpp, srcOffset, srcW, srcH,
7274+ srcPitch, dstOffset, dstPitch,
7275+ dstX, dstY, xscaler, yscaler));
7276+
7277+ if (randr & (RR_Rotate_90|RR_Rotate_270)) {
7278+ hasXForm = TRUE;
7279+ eng_cntl.val = w100c->regs.ENG_CNTL;
7280+ eng_cntl.f.dis_rop_src_uses_dst_w_h = 1;
7281+ eng_cntl.f.dis_src_uses_dst_dirmaj = 1;
7282+ ++firstStage;
7283+ ++secondStage;
7284+ }
7285+
7286+ W100ResetContext(w100c);
7287+ W100SetRotation(w100c, randr, FALSE);
7288+ W100SetSource(screen, srcPitch, srcOffset, bpp);
7289+ W100SetDestination(screen, dstPitch, dstOffset, bpp);
7290+
7291+ src_inc.val = 0;
7292+ src_inc.f.src_xinc = xscaler;
7293+ src_inc.f.src_yinc = yscaler;
7294+
7295+ dp_datatype.val = 0;
7296+ dp_datatype.f.dp_brush_datatype = DP_BRUSH_SOLIDCOLOR;
7297+ dp_datatype.f.dp_dst_datatype = w100c->ctx.dst.datatype;
7298+ dp_datatype.f.dp_src_datatype = w100c->ctx.src.datatype;
7299+ dp_datatype.f.dp_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
7300+
7301+ dp_mix.val = 0;
7302+ dp_mix.f.dp_op = DP_OP_ARITHMETIC;
7303+ dp_mix.f.dp_src_source = DP_SRC_MEM_RECTANGULAR;
7304+ dp_mix.f.dp_rop3 = W100BltRop[GXcopy];
7305+
7306+ e2.val = 0;
7307+ e2.f.opcode = E2_OPC_STRETCH_SRC2;
7308+ e2.f.srcblend = E2_SRCBLEND_ZERO;
7309+ e2.f.dstblend = E2_DSTBLEND_ZERO;
7310+
7311+ sw = W100ApplyScaler(srcW, xscaler);
7312+ sh = W100ApplyScaler(srcH, yscaler);
7313+
7314+ x = W100XformX(w100c, dstX, dstY, sw, sh);
7315+ y = W100XformY(w100c, dstX, dstY, sw, sh);
7316+ w = W100XformW(w100c, dstX, dstY, sw, sh);
7317+ h = W100XformH(w100c, dstX, dstY, sw, sh);
7318+
7319+ src_x_y.f.src_y = 0;
7320+ src_x_y.f.src_x = 0;
7321+ dst_x_y.f.dst_x = x;
7322+ dst_x_y.f.dst_y = y;
7323+ src_width.f.src_width = sw + 1;
7324+ src_height.f.src_height = sh;
7325+ dst_width_height.f.dst_height = h;
7326+ dst_width_height.f.dst_width_b0 = w & 0xff;
7327+ dst_width_height.f.dst_width_b1 = (w >> 8) & 0x3f;
7328+
7329+
7330+ if (W100WaitCmdFifoEntries(w100c, firstStage)) {
7331+ /* Set Source */
7332+ MMIO_OUT32(mmSRC_PITCH, w100c->ctx.src.pitch);
7333+ MMIO_OUT32(mmSRC_OFFSET, w100c->ctx.src.offset);
7334+
7335+ /* Set Destination */
7336+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
7337+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
7338+
7339+ /* Prepare for Stretch Operation */
7340+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, W100ComputeAritGmc(w100c, GXcopy));
7341+ MMIO_OUT32(mmDP_DATATYPE, dp_datatype.val);
7342+ MMIO_OUT32(mmDP_MIX, dp_mix.val);
7343+ MMIO_OUT32(mmE2_ARITHMETIC_CNTL, e2.val);
7344+
7345+ /* Set Data Trajectory */
7346+ if (hasXForm) {
7347+ MMIO_OUT32(mmENG_CNTL, eng_cntl.val);
7348+ }
7349+ MMIO_OUT32(mmDP_CNTL, w100c->ctx.xform.dataPath);
7350+ } else {
7351+ ErrorF("Error preparing for Stretch operation\n");
7352+ return;
7353+ }
7354+
7355+ if (W100WaitCmdFifoEntries(w100c, secondStage)) {
7356+ /* Perform blitting */
7357+ MMIO_OUT32(mmSRC_X_Y, src_x_y.val);
7358+ MMIO_OUT32(mmDST_X_Y, dst_x_y.val);
7359+ MMIO_OUT32(mmSRC_WIDTH, src_width.val);
7360+ MMIO_OUT32(mmSRC_HEIGHT, src_height.val);
7361+ MMIO_OUT32(mmSRC_INC, src_inc.val);
7362+ MMIO_OUT32(mmDST_WIDTH_HEIGHT, dst_width_height.val);
7363+ /* Restore state */
7364+ if (hasXForm) {
7365+ MMIO_OUT32(mmENG_CNTL, w100c->regs.ENG_CNTL);
7366+ }
7367+ } else {
7368+ ErrorF("Error performing Stretch operation\n");
7369+ }
7370+}
7371+
7372+static void W100ScaledBlt(KdScreenInfo *screen,
7373+ int randr,
7374+ int bpp,
7375+ CARD32 srcOffset,
7376+ CARD16 srcW,
7377+ CARD16 srcH,
7378+ CARD16 srcPitch,
7379+ CARD32 dstOffset,
7380+ CARD16 dstPitch,
7381+ CARD16 dstX,
7382+ CARD16 dstY,
7383+ CARD8 xscaler,
7384+ CARD8 yscaler)
7385+{
7386+ ScreenPtr pScreen = screen->pScreen;
7387+ KdScreenPriv(pScreen);
7388+ W100CardInfo(pScreenPriv);
7389+ CARD16 x, y, w, h, sw, sh;
7390+ Bool hasXForm = FALSE;
7391+ dp_datatype_u dp_datatype;
7392+ dp_mix_u dp_mix;
7393+ eng_cntl_u eng_cntl;
7394+ e2_arithmetic_cntl_u e2;
7395+ src_inc_u src_inc;
7396+ src_x_y_u src_x_y;
7397+ src2_x_y_u src2_x_y;
7398+ dst_x_y_u dst_x_y;
7399+ src_width_u src_width;
7400+ src_height_u src_height;
7401+ dst_width_height_u dst_width_height;
7402+ int firstStage = 11;
7403+ int secondStage = 11;
7404+
7405+ DBG_IMAGEON(("W100ScaledBlt(randr:%d,bpp:%d,srcOffset:0x%08x,"
7406+ "srcW:%d,srcH:%d,srcPitch:%d,dstOffset:0x%08x,"
7407+ "dstPitch:%d,dstX:%d,dstY:%d,xscaler:%d,yscaler:%d)\n",
7408+ randr, bpp, srcOffset, srcW, srcH,
7409+ srcPitch, dstOffset, dstPitch,
7410+ dstX, dstY, xscaler, yscaler));
7411+
7412+ if (randr & (RR_Rotate_90|RR_Rotate_270)) {
7413+ hasXForm = TRUE;
7414+ eng_cntl.val = w100c->regs.ENG_CNTL;
7415+ eng_cntl.f.dis_rop_src_uses_dst_w_h = 1;
7416+ eng_cntl.f.dis_src_uses_dst_dirmaj = 1;
7417+ ++firstStage;
7418+ ++secondStage;
7419+ }
7420+
7421+ W100ResetContext(w100c);
7422+ W100SetRotation(w100c, randr, FALSE);
7423+ W100SetSource(screen, srcPitch, srcOffset, bpp);
7424+ W100SetDestination(screen, dstPitch, dstOffset, bpp);
7425+
7426+ src_inc.val = 0;
7427+ src_inc.f.src_xinc = xscaler;
7428+ src_inc.f.src_yinc = yscaler;
7429+
7430+ dp_datatype.val = 0;
7431+ dp_datatype.f.dp_brush_datatype = DP_BRUSH_SOLIDCOLOR;
7432+ dp_datatype.f.dp_src2_type = 1;
7433+ dp_datatype.f.dp_dst_datatype = w100c->ctx.dst.datatype;
7434+ dp_datatype.f.dp_src2_datatype = w100c->ctx.src.datatype;
7435+ dp_datatype.f.dp_src_datatype = w100c->ctx.src.datatype;
7436+ dp_datatype.f.dp_byte_pix_order = DP_PIX_ORDER_LSB2MSB;
7437+
7438+ dp_mix.val = 0;
7439+ dp_mix.f.dp_op = DP_OP_ARITHMETIC;
7440+ dp_mix.f.dp_src_source = DP_SRC_MEM_RECTANGULAR;
7441+ dp_mix.f.dp_src2_source = DP_SRC_MEM_RECTANGULAR;
7442+ dp_mix.f.dp_rop3 = W100BltRop[GXcopy];
7443+
7444+ e2.val = 0;
7445+ e2.f.opcode = E2_OPC_SCALE_SRC2;
7446+ e2.f.srcblend = E2_SRCBLEND_ZERO;
7447+ e2.f.dstblend = E2_DSTBLEND_ZERO;
7448+
7449+ sw = W100ApplyScaler(srcW, xscaler);
7450+ sh = W100ApplyScaler(srcH, yscaler);
7451+
7452+ x = W100XformX(w100c, dstX, dstY, sw, sh);
7453+ y = W100XformY(w100c, dstX, dstY, sw, sh);
7454+ w = W100XformW(w100c, dstX, dstY, sw, sh);
7455+ h = W100XformH(w100c, dstX, dstY, sw, sh);
7456+
7457+ src_x_y.f.src_y = 0;
7458+ src_x_y.f.src_x = 0;
7459+ src2_x_y.f.src_y = 0 + 4;
7460+ src2_x_y.f.src_x = 0;
7461+ dst_x_y.f.dst_x = x;
7462+ dst_x_y.f.dst_y = y;
7463+ src_width.f.src_width = sw + 1;
7464+ src_height.f.src_height = sh;
7465+ dst_width_height.f.dst_height = h;
7466+ dst_width_height.f.dst_width_b0 = w & 0xff;
7467+ dst_width_height.f.dst_width_b1 = (w >> 8) & 0x3f;
7468+
7469+ if (W100WaitCmdFifoEntries(w100c, firstStage)) {
7470+ /* Set Source */
7471+ MMIO_OUT32(mmSRC_PITCH, w100c->ctx.src.pitch);
7472+ MMIO_OUT32(mmSRC_OFFSET, w100c->ctx.src.offset);
7473+
7474+ /* Set Destination */
7475+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
7476+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
7477+ /* Set second source */
7478+ MMIO_OUT32(mmSRC2_PITCH, w100c->ctx.src.pitch);
7479+ MMIO_OUT32(mmSRC2_OFFSET, w100c->ctx.src.offset);
7480+
7481+ /* Prepare for Stretch Operation */
7482+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL, W100ComputeAritGmc(w100c, GXcopy));
7483+ MMIO_OUT32(mmDP_DATATYPE, dp_datatype.val);
7484+ MMIO_OUT32(mmDP_MIX, dp_mix.val);
7485+ MMIO_OUT32(mmE2_ARITHMETIC_CNTL, e2.val);
7486+ /* Set Data Trajectory */
7487+ if (hasXForm) {
7488+ MMIO_OUT32(mmENG_CNTL, eng_cntl.val);
7489+ }
7490+ MMIO_OUT32(mmDP_CNTL, w100c->ctx.xform.dataPath);
7491+ } else {
7492+ ErrorF("Unable to prepare for Scaled Blitting\n");
7493+ return;
7494+ }
7495+ if (W100WaitCmdFifoEntries(w100c, secondStage)) {
7496+ /* Perform blitting */
7497+ MMIO_OUT32(mmSRC_X_Y, src_x_y.val);
7498+ MMIO_OUT32(mmSRC2_X_Y, src2_x_y.val);
7499+ MMIO_OUT32(mmSRC2_WIDTH, src_width.val);
7500+ MMIO_OUT32(mmSRC2_HEIGHT, src_height.val);
7501+ MMIO_OUT32(mmSRC_INC, src_inc.val);
7502+ MMIO_OUT32(mmSRC2_INC, src_inc.val);
7503+ MMIO_OUT32(mmDST_X_Y, dst_x_y.val);
7504+ MMIO_OUT32(mmSRC_WIDTH, src_width.val);
7505+ MMIO_OUT32(mmSRC_HEIGHT, src_height.val);
7506+ MMIO_OUT32(mmDST_WIDTH_HEIGHT, dst_width_height.val);
7507+ /* Restore state */
7508+ if (hasXForm) {
7509+ MMIO_OUT32(mmENG_CNTL, w100c->regs.ENG_CNTL);
7510+ }
7511+ /* Without this, solid blitting is no longer working correctly */
7512+ dp_datatype.f.dp_src2_type = 0;
7513+ MMIO_OUT32(mmDP_DATATYPE, dp_datatype.val);
7514+ } else {
7515+ ErrorF("Unable to perform Scaled Blitting\n");
7516+ }
7517+}
7518+
7519+void W100PlanarBlt(KdScreenInfo *screen,
7520+ int planes,
7521+ int bpp,
7522+ int randr,
7523+ KdOffscreenArea *src,
7524+ int srcW,
7525+ int srcPitch,
7526+ int srcH,
7527+ KdOffscreenArea *dst,
7528+ int planeOffsets[],
7529+ int dstW,
7530+ int dstPitch,
7531+ int dstH,
7532+ int dstX,
7533+ int dstY)
7534+{
7535+ ScreenPtr pScreen = screen->pScreen;
7536+ KdScreenPriv(pScreen);
7537+ W100CardInfo(pScreenPriv);
7538+ W100ScreenInfo(pScreenPriv);
7539+ CARD8 *srcOffset, *dstBase, *dstOffset;
7540+ int xoffs, yoffs;
7541+ unsigned int subsampling[] = {0, 1, 1};
7542+ int plane;
7543+ int stretch = ((srcW != dstW) || (srcH != dstH));
7544+ CARD8 xscaler, yscaler;
7545+
7546+ DBG_IMAGEON(("W100PlanarBlt(planes:%d,bpp:%d,randr:%d,"
7547+ "src(w:%d,pitch:%d,h:%d),"
7548+ "dst(w:%d,pitch:%d,h:%d,x:%d,y:%d)\n",
7549+ planes, bpp, randr,
7550+ srcW, srcPitch, srcH,
7551+ dstW, dstPitch, dstH, dstX, dstY));
7552+
7553+ if (stretch) {
7554+ xscaler = W100GetScaler(dstW, srcW);
7555+ yscaler = W100GetScaler(dstH, srcH);
7556+ xoffs = yoffs = 0;
7557+ if (xscaler != 16 || yscaler != 16) {
7558+ xoffs = (dstW - W100ApplyScaler(srcW, xscaler)) / 2;
7559+ yoffs = (dstH - W100ApplyScaler(srcH, yscaler)) / 2;
7560+ DBG_IMAGEON(("Stretching with xscaler:%d,yscaler:%d,"
7561+ "xoffs:%d,yoffs:%d\n",
7562+ xscaler, yscaler, xoffs, yoffs));
7563+ } else {
7564+ xoffs = yoffs = 0;
7565+ stretch = FALSE;
7566+ }
7567+ }
7568+
7569+ srcOffset = src->vidmem->base + src->offset;
7570+ dstBase = dst->vidmem->base + dst->offset;
7571+ for (plane = 0; plane < planes; plane++) {
7572+ dstOffset = dstBase + planeOffsets[plane];
7573+ if (stretch) {
7574+ W100ScaledBlt(screen, randr, bpp,
7575+ (CARD32) srcOffset,
7576+ srcW >> subsampling[plane],
7577+ srcH >> subsampling[plane],
7578+ srcPitch >> subsampling[plane],
7579+ (CARD32) dstOffset,
7580+ dstPitch >> subsampling[plane],
7581+ (dstX + xoffs) >> subsampling[plane],
7582+ (dstY + yoffs) >> subsampling[plane],
7583+ xscaler, yscaler);
7584+ } else {
7585+ W100Blt(screen, randr, bpp,
7586+ (CARD32) srcOffset,
7587+ srcW >> subsampling[plane],
7588+ srcH >> subsampling[plane],
7589+ srcPitch >> subsampling[plane],
7590+ (CARD32) dstOffset,
7591+ dstPitch >> subsampling[plane],
7592+ dstX >> subsampling[plane],
7593+ dstY >> subsampling[plane]);
7594+ }
7595+ srcOffset += (srcPitch * srcH) >> (subsampling[plane] * 2);
7596+ }
7597+}
7598+
7599+void W100SetBrightness(W100CardInfo *w100c, CARD8 value)
7600+{
7601+ brightness_cntl_u brightness;
7602+ brightness.val = 0;
7603+ brightness.f.brightness = value;
7604+ MMIO_OUT32(mmBRIGHTNESS_CNTL, brightness.val);
7605+}
7606+
7607+CARD8 W100GetBrightness(W100CardInfo *w100c)
7608+{
7609+ brightness_cntl_u brightness;
7610+ brightness.val = MMIO_IN32(mmBRIGHTNESS_CNTL);
7611+ return brightness.f.brightness;
7612+}
7613+
7614+int W100GetRotation(W100CardInfo *w100c)
7615+{
7616+ graphic_ctrl_u gc;
7617+ int randr;
7618+
7619+ gc.val = MMIO_IN32(mmGRAPHIC_CTRL);
7620+
7621+ switch (gc.f.portrait_mode) {
7622+ case 0:
7623+ randr = RR_Rotate_0;
7624+ break;
7625+ case 1:
7626+ randr = RR_Rotate_90;
7627+ break;
7628+ case 2:
7629+ randr = RR_Rotate_270;
7630+ break;
7631+ case 3:
7632+ randr = RR_Rotate_180;
7633+ break;
7634+ }
7635+ return randr;
7636+}
7637+
7638+Bool W100SysFsSet(W100CardInfo *w100c, const char *path, const char *value)
7639+{
7640+ FILE *fd;
7641+ if ((fd = fopen(path, "w")) == NULL) {
7642+ ErrorF("(E) Error in W100SysFsSet: Unable to open '%s'\n", path);
7643+ return FALSE;
7644+ }
7645+ fprintf(fd, "%s", value);
7646+ fclose(fd);
7647+ return TRUE;
7648+}
7649+
7650+Bool W100SysFsGet(W100CardInfo *w100c, const char *path, char *value)
7651+{
7652+ FILE *fd;
7653+ if ((fd = fopen(path, "r")) == NULL) {
7654+ ErrorF("(E) Error in W100SysFsGet: Unable to open '%s'\n", path);
7655+ return FALSE;
7656+ }
7657+ fscanf(fd, "%s", value);
7658+ fclose(fd);
7659+ return TRUE;
7660+}
7661+
7662+void W100TransformTsLibCoordinates(long *x, long *y, void *closure)
7663+{
7664+ W100CardInfo *w100c = closure;
7665+
7666+ if (w100c->hw_window.mode->width == 320) {
7667+ *x >>= 1;
7668+ *y >>= 1;
7669+ }
7670+}
7671+
7672+
7673--- /dev/null
7674+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_video.c
7675@@ -0,0 +1,1051 @@
7676+/*
7677+ * Copyright © 2007 Manuel Teira
7678+ *
7679+ * Permission to use, copy, modify, distribute, and sell this software and its
7680+ * documentation for any purpose is hereby granted without fee, provided that
7681+ * the above copyright notice appear in all copies and that both that
7682+ * copyright notice and this permission notice appear in supporting
7683+ * documentation, and that the name of Manuel Teira not be used in
7684+ * advertising or publicity pertaining to distribution of the software without
7685+ * specific, written prior permission. Manuel Teira makes no
7686+ * representations about the suitability of this software for any purpose. It
7687+ * is provided "as is" without express or implied warranty.
7688+ *
7689+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
7690+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
7691+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
7692+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
7693+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
7694+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
7695+ * PERFORMANCE OF THIS SOFTWARE.
7696+ */
7697+
7698+#ifdef HAVE_CONFIG_H
7699+#include <kdrive-config.h>
7700+#endif
7701+#include "imageon.h"
7702+#include "imageon_regs.h"
7703+#include "imageon_support.h"
7704+#include "imageon_const.h"
7705+#include "kaa.h"
7706+
7707+#include <X11/extensions/Xv.h>
7708+#include "fourcc.h"
7709+
7710+static Atom xvBrightness;
7711+static Atom xvMaxOverlaySize;
7712+static Atom xvColorKey;
7713+
7714+#define IMAGE_MAX_WIDTH 720
7715+#define IMAGE_MAX_HEIGHT 576
7716+
7717+#define W_ALIGN 0
7718+#define H_ALIGN 0
7719+
7720+#define OVL_W_ALIGN 16
7721+#define OVL_H_ALIGN 16
7722+
7723+#define OVL_MAX_SIZE 196608
7724+
7725+static KdVideoEncodingRec DummyEncoding[1] = {
7726+ {0, "XV_IMAGE", IMAGE_MAX_WIDTH, IMAGE_MAX_HEIGHT, {1, 1}}
7727+};
7728+
7729+#define NUM_IMAGES (4)
7730+static KdImageRec Images[NUM_IMAGES] = {
7731+ XVIMAGE_YUY2,
7732+ XVIMAGE_YV12,
7733+ XVIMAGE_I420,
7734+ XVIMAGE_UYVY
7735+};
7736+
7737+#define NUM_FORMATS (3)
7738+static KdVideoFormatRec Formats[NUM_FORMATS] = {
7739+ {15, TrueColor},
7740+ {16, TrueColor},
7741+ {24, TrueColor}
7742+};
7743+
7744+#define NUM_ATTRIBUTES (3)
7745+static KdAttributeRec Attributes[NUM_ATTRIBUTES] = {
7746+ {XvSettable | XvGettable, 0, (1 << 16) - 1, "XV_COLORKEY"},
7747+ {XvSettable | XvGettable, 0, 127, "XV_BRIGHTNESS"},
7748+ {XvSettable | XvGettable, 0, 392960, "XV_MAXOVERLAYSIZE"}
7749+};
7750+
7751+#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE)
7752+
7753+#define NUM_OVL_RESIZERS (10)
7754+static struct {
7755+ CARD8 xfactor;
7756+ CARD8 yfactor;
7757+} ovlResizers[10] = {
7758+ { 0, 0 },
7759+ { 1, 0 },
7760+ { 0, 1 },
7761+ { 1, 1 },
7762+ { 2, 1 },
7763+ { 1, 2 },
7764+ { 2, 2 },
7765+ { 3, 2 },
7766+ { 2, 3 },
7767+ { 3, 3 }
7768+};
7769+
7770+static void W100ClearSurface(KdScreenInfo *screen,
7771+ KdOffscreenArea *area,
7772+ CARD16 x,
7773+ CARD16 y,
7774+ CARD16 pitch,
7775+ CARD16 width,
7776+ CARD16 height,
7777+ int id)
7778+{
7779+ W100CardInfo(screen);
7780+ int nplanes;
7781+ unsigned int subsampling[] = {0, 1, 1};
7782+ unsigned int zero[] = {0, 0x80, 0x80};
7783+ int bpp;
7784+ int plane;
7785+ CARD8 *dstOffset = area->vidmem->base + area->offset;
7786+
7787+ switch (id) {
7788+ case FOURCC_UYVY:
7789+ case FOURCC_YUY2:
7790+ nplanes = 1;
7791+ bpp = 16;
7792+ break;
7793+ case FOURCC_YV12:
7794+ case FOURCC_I420:
7795+ nplanes = 3;
7796+ bpp = 8;
7797+ }
7798+
7799+ DBG_IMAGEON(("Clearing surface with planes:%d, bpp:%d, pitch:%d, height:%d\n",
7800+ nplanes, bpp, pitch, height));
7801+
7802+ W100ResetContext(w100c);
7803+ for (plane = 0; plane < nplanes; plane++) {
7804+ W100SetDestination(screen,
7805+ pitch >> subsampling[plane],
7806+ (CARD32) dstOffset,
7807+ bpp);
7808+ if (W100WaitCmdFifoEntries(w100c, 6)) {
7809+ MMIO_OUT32(mmDST_PITCH, w100c->ctx.dst.pitch);
7810+ MMIO_OUT32(mmDST_OFFSET, w100c->ctx.dst.offset);
7811+ MMIO_OUT32(mmDP_GUI_MASTER_CNTL,
7812+ W100ComputeSolidGmc(w100c, GXcopy));
7813+ MMIO_OUT32(mmDP_BRUSH_FRGD_CLR, zero[plane]);
7814+ MMIO_OUT32(mmDST_Y_X, 0);
7815+ MMIO_OUT32(mmDST_HEIGHT_WIDTH, (height << 16) | width);
7816+ } else {
7817+ ErrorF("Error clearing surface\n");
7818+ break;
7819+ }
7820+ dstOffset += (pitch * height) >> (subsampling[plane] * 2);
7821+ }
7822+}
7823+
7824+static void W100OverlaySetup(KdScreenInfo *screen)
7825+{
7826+ W100ScreenInfo *w100s = screen->driver;
7827+ W100CardInfo(screen);
7828+ W100PortPrivPtr pPortPriv = w100s->pAdaptor->pPortPrivates[0].ptr;
7829+
7830+ video_ctrl_u video_ctrl;
7831+ video_y_offset_u video_y_offset;
7832+ video_y_pitch_u video_y_pitch;
7833+ video_u_offset_u video_u_offset;
7834+ video_u_pitch_u video_u_pitch;
7835+ video_v_offset_u video_v_offset;
7836+ video_v_pitch_u video_v_pitch;
7837+ graphic_key_u graphic_key;
7838+ video_h_pos_u video_hpos;
7839+ video_v_pos_u video_vpos;
7840+ graphic_h_disp_u graphic_h_disp;
7841+ graphic_v_disp_u graphic_v_disp;
7842+
7843+ CARD16 w, h;
7844+
7845+ DBG_IMAGEON(("W100OverlaySetup(ovlX:%d,ovlY:%d,ovlWidth:%d,ovlHeight:%d,"
7846+ "videoHorExp:%d,videoVerExp:%d,YPlane:0x%08x,UPlane:0x%08x,"
7847+ "VPlane:0x%08x)\n",
7848+ pPortPriv->ovlX, pPortPriv->ovlY,
7849+ pPortPriv->ovlWidth, pPortPriv->ovlHeight,
7850+ pPortPriv->videoHorExp, pPortPriv->videoVerExp,
7851+ pPortPriv->YPlaneOffset, pPortPriv->UPlaneOffset,
7852+ pPortPriv->VPlaneOffset));
7853+
7854+ if (pPortPriv->videoStatus & W100_OVERLAY_CONFIGURED) {
7855+ return;
7856+ }
7857+
7858+ w = pPortPriv->ovlWidth << pPortPriv->videoHorExp;
7859+ h = pPortPriv->ovlHeight << pPortPriv->videoVerExp;
7860+
7861+ video_ctrl.val = w100c->regs.VIDEO_CTRL;
7862+
7863+ video_ctrl.f.video_inv_hor = 0;
7864+ video_ctrl.f.video_inv_ver = 0;
7865+ video_ctrl.f.yuv2rgb_option = 0;
7866+ video_ctrl.f.video_hor_exp = pPortPriv->videoHorExp;
7867+ video_ctrl.f.video_ver_exp = pPortPriv->videoVerExp;
7868+ video_ctrl.f.video_ch_sel = 0;
7869+
7870+ video_ctrl.f.yuv2rgb_en = 1;
7871+ //Only support this, by the moment
7872+ video_ctrl.f.video_mode = OVLFORMAT_YUV420;
7873+
7874+ video_y_pitch.f.y_pitch = pPortPriv->ovlWidth;
7875+ video_u_pitch.f.u_pitch = pPortPriv->ovlWidth >> 1;
7876+ video_v_pitch.f.v_pitch = pPortPriv->ovlWidth >> 1;
7877+
7878+ /*
7879+ video_y_offset.f.y_offset = pPortPriv->YPlaneOffset +
7880+ video_y_pitch.f.y_pitch * pPortPriv->ovlY + pPortPriv->ovlX;
7881+ video_u_offset.f.u_offset = pPortPriv->UPlaneOffset +
7882+ video_u_pitch.f.u_pitch * pPortPriv->ovlY + (pPortPriv->ovlX / 2);
7883+ video_v_offset.f.v_offset = pPortPriv->VPlaneOffset +
7884+ video_v_pitch.f.v_pitch * pPortPriv->ovlY + (pPortPriv->ovlX / 2);
7885+ */
7886+
7887+ video_y_offset.f.y_offset = pPortPriv->YPlaneOffset;
7888+ video_u_offset.f.u_offset = pPortPriv->UPlaneOffset;
7889+ video_v_offset.f.v_offset = pPortPriv->VPlaneOffset;
7890+
7891+ graphic_key.val = 0;
7892+ graphic_key.f.keyer_color = pPortPriv->colorKey;
7893+ graphic_key.f.keyer_mask = 0xffffUL;
7894+ video_ctrl.f.keyer_en = 1;
7895+
7896+ graphic_h_disp.val = w100c->regs.GRAPHIC_H_DISP;
7897+ graphic_v_disp.val = w100c->regs.GRAPHIC_V_DISP;
7898+
7899+ video_hpos.f.video_h_start = graphic_h_disp.f.graphic_h_start
7900+ + pPortPriv->ovlX;
7901+ video_hpos.f.video_h_end = video_hpos.f.video_h_start + w;
7902+ video_vpos.f.video_v_start = graphic_v_disp.f.graphic_v_start
7903+ + pPortPriv->ovlY;
7904+ video_vpos.f.video_v_end = video_vpos.f.video_v_start + h;
7905+ if (video_hpos.f.video_h_end > graphic_h_disp.f.graphic_h_end) {
7906+ w = graphic_h_disp.f.graphic_h_end - video_hpos.f.video_h_start;
7907+ }
7908+
7909+ //This is possibly not valid for non planar modes
7910+ video_ctrl.f.total_req_video = (w + 3) / 4;
7911+
7912+ W100DisableDisplayUpdate(w100c);
7913+ //This need to be tuned deeply, to get an stable
7914+ //overlay image
7915+ MMIO_OUT32(mmDISP_DEBUG2,
7916+ (w100c->regs.DISP_DEBUG2 & ~0xff000000) | 0x80000000 );
7917+ MMIO_OUT32(mmGRAPHIC_KEY, graphic_key.val);
7918+ MMIO_OUT32(mmVIDEO_Y_OFFSET, video_y_offset.val);
7919+ MMIO_OUT32(mmVIDEO_Y_PITCH, video_y_pitch.val);
7920+ MMIO_OUT32(mmVIDEO_U_OFFSET, video_u_offset.val);
7921+ MMIO_OUT32(mmVIDEO_U_PITCH, video_u_pitch.val);
7922+ MMIO_OUT32(mmVIDEO_V_OFFSET, video_v_offset.val);
7923+ MMIO_OUT32(mmVIDEO_V_PITCH, video_v_pitch.val);
7924+ MMIO_OUT32(mmVIDEO_CTRL, video_ctrl.val);
7925+ MMIO_OUT32(mmVIDEO_H_POS, video_hpos.val);
7926+ MMIO_OUT32(mmVIDEO_V_POS, video_vpos.val);
7927+ W100EnableDisplayUpdate(w100c);
7928+
7929+ pPortPriv->videoCtrl = video_ctrl.val;
7930+ pPortPriv->videoStatus |= W100_OVERLAY_CONFIGURED;
7931+}
7932+
7933+static void W100OverlayEnable(KdScreenInfo *screen)
7934+{
7935+ W100ScreenInfo *w100s = screen->driver;
7936+ W100CardInfo(screen);
7937+ W100PortPrivPtr pPortPriv = w100s->pAdaptor->pPortPrivates[0].ptr;
7938+ video_ctrl_u video_ctrl;
7939+
7940+ DBG_IMAGEON(("W100OverlayEnable()\n"));
7941+
7942+ if (!(pPortPriv->videoStatus & W100_OVERLAY_CONFIGURED)) {
7943+ W100OverlaySetup(screen);
7944+ }
7945+
7946+ video_ctrl.val = pPortPriv->videoCtrl;
7947+ video_ctrl.f.en_video_req = 1;
7948+ video_ctrl.f.en_video_crtc = 1;
7949+ video_ctrl.f.en_graphic_req_video = 1;
7950+ W100DisableDisplayUpdate(w100c);
7951+ MMIO_OUT32(mmVIDEO_CTRL, video_ctrl.val);
7952+ W100EnableDisplayUpdate(w100c);
7953+ pPortPriv->videoCtrl = video_ctrl.val;
7954+ pPortPriv->videoStatus |= W100_OVERLAY_ON;
7955+}
7956+
7957+static void W100OverlayDisable(KdScreenInfo *screen)
7958+{
7959+ DBG_IMAGEON(("W100OverlayDisable()\n"));
7960+ W100ScreenInfo *w100s = screen->driver;
7961+ W100CardInfo(screen);
7962+ W100PortPrivPtr pPortPriv = w100s->pAdaptor->pPortPrivates[0].ptr;
7963+
7964+ video_ctrl_u video_ctrl;
7965+
7966+ video_ctrl.val = pPortPriv->videoCtrl;
7967+ video_ctrl.f.en_video_req = 0;
7968+ video_ctrl.f.en_video_crtc = 0;
7969+ video_ctrl.f.en_graphic_req_video = 0;
7970+ W100DisableDisplayUpdate(w100c);
7971+ MMIO_OUT32(mmVIDEO_CTRL, video_ctrl.val);
7972+ W100EnableDisplayUpdate(w100c);
7973+ pPortPriv->videoCtrl = video_ctrl.val;
7974+ pPortPriv->videoStatus &= ~W100_OVERLAY_ON;
7975+}
7976+
7977+static void W100VideoSave(ScreenPtr pScreen, KdOffscreenArea *area)
7978+{
7979+ KdScreenPriv(pScreen);
7980+ W100CardInfo(pScreenPriv);
7981+ W100ScreenInfo(pScreenPriv);
7982+ W100PortPrivPtr pPortPriv = w100s->pAdaptor->pPortPrivates[0].ptr;
7983+
7984+ if (pPortPriv->offSurface == area) {
7985+ pPortPriv->offSurface = NULL;
7986+ pPortPriv->offSize = 0;
7987+ }
7988+ if (pPortPriv->ovlSurface == area) {
7989+ pPortPriv->ovlSurface = NULL;
7990+ pPortPriv->ovlSize = 0;
7991+ }
7992+}
7993+
7994+static void W100HostPlanarData(KdScreenInfo *screen,
7995+ int id,
7996+ CARD8 *src,
7997+ KdOffscreenArea *dst,
7998+ CARD32 srcPitch, CARD32 srcHeight,
7999+ CARD32 dstPitch, CARD32 dstHeight,
8000+ CARD16 srcX, CARD16 srcY,
8001+ CARD16 dstX, CARD16 dstY,
8002+ CARD16 w, CARD16 h)
8003+{
8004+ CARD8 *dstBase = dst->vidmem->base + dst->offset;
8005+ CARD8 *dstPtr;
8006+ CARD8 *srcPtr;
8007+ int i;
8008+
8009+ srcPtr = src + (srcY * srcPitch) + srcX;
8010+ dstPtr = dstBase + (dstY * dstPitch) + dstX;
8011+
8012+ DBG_IMAGEON(("W100HostPlanarData(src(pitch:%d,offset:0x%08x,x:%d,y:%d),"
8013+ "dst(pitch:%d,offset:0x%08x,x:%d,y:%d), w:%d,h:%d)\n",
8014+ srcPitch, srcPtr, srcX, srcY,
8015+ dstPitch, dstPtr, dstX, dstY,
8016+ w, h));
8017+
8018+ /* Copy Y plane */
8019+ for (i = 0; i < h; i++) {
8020+ memcpy(dstPtr, srcPtr, w);
8021+ dstPtr += dstPitch;
8022+ srcPtr += srcPitch;
8023+ }
8024+ /* Copy U plane */
8025+ dstPtr = dstBase + (dstHeight * dstPitch) //Start of U Plane
8026+ + (dstX >> 1) //X Offset
8027+ + ((dstY * dstPitch) >> 2); //Y Offset
8028+ if (id == FOURCC_I420) {
8029+ srcPtr = src + (srcHeight * srcPitch) //Start of U Plane
8030+ + (srcX >> 1) //X Offset
8031+ + ((srcY * srcPitch) >> 2); //Y Offset
8032+ } else {
8033+ srcPtr = src + ((5 * srcHeight * srcPitch) / 4) //Start of U Plane
8034+ + (srcX >> 1) //X Offset
8035+ + ((srcY * srcPitch) >> 2); //Y Offset
8036+ }
8037+ for (i = 0; i < (h >> 1); i++) {
8038+ memcpy(dstPtr, srcPtr, w >> 1); //U Plane scanline
8039+ srcPtr += srcPitch >> 1;
8040+ dstPtr += dstPitch >> 1;
8041+ }
8042+
8043+ /* Copy V plane */
8044+ dstPtr = dstBase + ((5 * dstHeight * dstPitch) / 4) //Start of V Plane
8045+ + (dstX >> 1) //X Offset
8046+ + ((dstY * dstPitch) >> 2); //Y Offset
8047+ if (id == FOURCC_I420) {
8048+ srcPtr = src + ((5 * srcHeight * srcPitch) / 4) //Start of V Plane
8049+ + (srcX >> 1) //X Offset
8050+ + ((srcY * srcPitch) >> 2); //Y Offset
8051+ } else {
8052+ srcPtr = src + (srcHeight * srcPitch) //Start of V Plane
8053+ + (srcX >> 1) //X Offset
8054+ + ((srcY * srcPitch) >> 2); //Y Offset
8055+ }
8056+ for (i = 0; i < (h >> 1); i++) {
8057+ memcpy(dstPtr, srcPtr, w >> 1); //V Plane scanline
8058+ srcPtr += srcPitch >> 1;
8059+ dstPtr += dstPitch >> 1;
8060+ }
8061+}
8062+
8063+static void W100HostPackedData(KdScreenInfo *screen,
8064+ int id,
8065+ CARD8 *src,
8066+ KdOffscreenArea *dst,
8067+ CARD32 srcPitch,
8068+ CARD32 dstPitch,
8069+ CARD16 srcX, CARD16 srcY,
8070+ CARD16 dstX, CARD16 dstY,
8071+ CARD16 w, CARD16 h)
8072+{
8073+ CARD8 *dstBase = dst->vidmem->base + dst->offset;
8074+ CARD8 *dstPtr = dstBase + (dstY * dstPitch) + (dstX << 1);
8075+ CARD8 *srcPtr = src + (srcY + srcPitch) + (srcX << 1);
8076+
8077+ DBG_IMAGEON(("W100HostPackedData(src(pitch:%d,offset:0x%08x,x:%d,y:%d),"
8078+ "dst(pitch:%d,offset:0x%08x,x:%d,y:%d), w:%d,h:%d)\n",
8079+ srcPitch, srcPtr, srcX, srcY,
8080+ dstPitch, dstPtr, dstX, dstY,
8081+ w, h));
8082+ while(h--) {
8083+ memcpy(dstPtr, srcPtr, (w << 1)); /* 16bpp assumed */
8084+ srcPtr += srcPitch;
8085+ dstPtr += dstPitch;
8086+ }
8087+}
8088+
8089+
8090+static void W100StopVideo(KdScreenInfo *screen, pointer data, Bool exit)
8091+{
8092+ W100CardInfo(screen);
8093+ W100PortPrivPtr pPriv = (W100PortPrivPtr)data;
8094+
8095+ DBG_IMAGEON(("W100StopVideo(exit:%d)\n", exit));
8096+
8097+ REGION_EMPTY(screen->pScreen, &pPriv->clip);
8098+
8099+ if (exit) {
8100+ if (pPriv->videoStatus & W100_OVERLAY_ON) {
8101+ W100OverlayDisable(screen);
8102+ }
8103+ if (pPriv->offSurface) {
8104+ KdOffscreenFree(screen->pScreen, pPriv->offSurface);
8105+ pPriv->offSurface = NULL;
8106+ pPriv->offSize = 0;
8107+ }
8108+ if (pPriv->ovlSurface) {
8109+ KdOffscreenFree(screen->pScreen, pPriv->ovlSurface);
8110+ pPriv->ovlSurface = NULL;
8111+ pPriv->ovlSize = 0;
8112+ }
8113+ pPriv->videoStatus &= ~W100_OVERLAY_ON;
8114+ } else {
8115+ if (pPriv->videoStatus & W100_OVERLAY_ON) {
8116+ W100OverlayDisable(screen);
8117+ pPriv->videoStatus &= ~W100_OVERLAY_ON;
8118+ }
8119+ }
8120+}
8121+
8122+static int W100SetPortAttribute(KdScreenInfo *screen,
8123+ Atom attribute,
8124+ int value,
8125+ pointer data)
8126+{
8127+ W100CardInfo(screen);
8128+ W100PortPrivPtr pPriv = (W100PortPrivPtr)data;
8129+
8130+ if (attribute == xvBrightness) {
8131+ DBG_IMAGEON(("Setting Brightness attribute to %d\n", value));
8132+ W100SetBrightness(w100c, value);
8133+ pPriv->brightness = value;
8134+ } else if (attribute == xvMaxOverlaySize) {
8135+ DBG_IMAGEON(("Setting MaxOverlaySize to %d\n", value));
8136+ pPriv->maxOverlaySize = value;
8137+ } else if (attribute == xvColorKey) {
8138+ DBG_IMAGEON(("Setting ColorKey attribute to %d\n", value));
8139+ pPriv->colorKey = value;
8140+ }
8141+ return Success;
8142+}
8143+
8144+static int W100GetPortAttribute(KdScreenInfo *screen,
8145+ Atom attribute,
8146+ int *value,
8147+ pointer data)
8148+{
8149+ W100CardInfo(screen);
8150+ W100PortPrivPtr pPriv = (W100PortPrivPtr)data;
8151+
8152+ if (attribute == xvBrightness) {
8153+ DBG_IMAGEON(("Getting Brightness attribute\n"));
8154+ *value = pPriv->brightness;
8155+ } else if (attribute == xvMaxOverlaySize) {
8156+ *value = pPriv->maxOverlaySize;
8157+ DBG_IMAGEON(("Getting Contrast attribute\n"));
8158+ } else if (attribute == xvColorKey) {
8159+ DBG_IMAGEON(("Getting ColorKey attribute\n"));
8160+ *value = pPriv->colorKey;
8161+ }
8162+ return Success;
8163+}
8164+
8165+static void W100QueryBestSize(KdScreenInfo *screen,
8166+ Bool motion,
8167+ short vid_w, short vid_h, /*Video dimensions */
8168+ short drw_w, short drw_h, /*Drawable dimensions */
8169+ unsigned int *p_w, unsigned int *p_h,
8170+ pointer data)
8171+{
8172+ DBG_IMAGEON(("W100QueryBestSize(vid_w:%d,vid_h:%d,drw_w:%d,drw_h:%d)\n",
8173+ vid_w, vid_h, drw_w, drw_h));
8174+ int xscaler = W100GetScaler(drw_w, vid_w);
8175+ int yscaler = W100GetScaler(drw_h, vid_h);
8176+ *p_w = W100ApplyScaler(vid_w, xscaler);
8177+ *p_h = W100ApplyScaler(vid_h, yscaler);
8178+}
8179+
8180+static int W100QueryImageAttributes(KdScreenInfo *screen,
8181+ int id,
8182+ unsigned short *w, unsigned short *h,
8183+ int *pitches, int *offsets)
8184+{
8185+ int size, tmp;
8186+
8187+ if (*w > IMAGE_MAX_WIDTH) {
8188+ *w = IMAGE_MAX_WIDTH;
8189+ }
8190+ if (*h > IMAGE_MAX_HEIGHT) {
8191+ *h = IMAGE_MAX_HEIGHT;
8192+ }
8193+
8194+ if (W_ALIGN) {
8195+ *w = (*w + (W_ALIGN - 1)) & ~(W_ALIGN - 1);
8196+ }
8197+ if (H_ALIGN) {
8198+ *h = (*h + (H_ALIGN - 1)) & ~(H_ALIGN - 1);
8199+ }
8200+
8201+ if (offsets) {
8202+ offsets[0] = 0;
8203+ }
8204+
8205+ switch (id) {
8206+ /* Planar formats */
8207+ case FOURCC_YV12:
8208+ case FOURCC_I420:
8209+ *h = (*h + 1) & ~1;
8210+ size = (*w + 3) & ~3;
8211+ if (pitches) pitches[0] = size;
8212+ size *= *h;
8213+ if (offsets) offsets[1] = size;
8214+ tmp = ((*w >> 1) + 3) & ~3;
8215+ if (pitches) pitches[1] = pitches[2] = tmp;
8216+ tmp *= (*h >> 1);
8217+ size += tmp;
8218+ if(offsets) offsets[2] = size;
8219+ size += tmp;
8220+ break;
8221+ /* Packed Formats */
8222+ case FOURCC_UYVY:
8223+ case FOURCC_YUY2:
8224+ default:
8225+ size = *w << 1;
8226+ if (pitches) pitches[0] = size;
8227+ size *= *h;
8228+ break;
8229+ }
8230+ return size;
8231+}
8232+
8233+
8234+static void W100ClipVideo(BoxPtr dst,
8235+ INT32 *x1,
8236+ INT32 *x2,
8237+ INT32 *y1,
8238+ INT32 *y2,
8239+ BoxPtr extents,
8240+ INT32 width,
8241+ INT32 height)
8242+{
8243+ INT32 vscale, hscale, delta;
8244+ int diff;
8245+
8246+ hscale = ((*x2 - *x1) << 16) / (dst->x2 - dst->x1);
8247+ vscale = ((*y2 - *y1) << 16) / (dst->y2 - dst->y1);
8248+
8249+ *x1 <<= 16; *x2 <<= 16;
8250+ *y1 <<= 16; *y2 <<= 16;
8251+
8252+ diff = extents->x1 - dst->x1;
8253+ if(diff > 0) {
8254+ dst->x1 = extents->x1;
8255+ *x1 += diff * hscale;
8256+ }
8257+ diff = dst->x2 - extents->x2;
8258+ if(diff > 0) {
8259+ dst->x2 = extents->x2;
8260+ *x2 -= diff * hscale;
8261+ }
8262+ diff = extents->y1 - dst->y1;
8263+ if(diff > 0) {
8264+ dst->y1 = extents->y1;
8265+ *y1 += diff * vscale;
8266+ }
8267+ diff = dst->y2 - extents->y2;
8268+ if(diff > 0) {
8269+ dst->y2 = extents->y2;
8270+ *y2 -= diff * vscale;
8271+ }
8272+
8273+ if(*x1 < 0) {
8274+ diff = (- *x1 + hscale - 1)/ hscale;
8275+ dst->x1 += diff;
8276+ *x1 += diff * hscale;
8277+ }
8278+ delta = *x2 - (width << 16);
8279+ if(delta > 0) {
8280+ diff = (delta + hscale - 1)/ hscale;
8281+ dst->x2 -= diff;
8282+ *x2 -= diff * hscale;
8283+ }
8284+ if(*y1 < 0) {
8285+ diff = (- *y1 + vscale - 1)/ vscale;
8286+ dst->y1 += diff;
8287+ *y1 += diff * vscale;
8288+ }
8289+ delta = *y2 - (height << 16);
8290+ if(delta > 0) {
8291+ diff = (delta + vscale - 1)/ vscale;
8292+ dst->y2 -= diff;
8293+ *y2 -= diff * vscale;
8294+ }
8295+}
8296+
8297+static int W100PutImage(KdScreenInfo *screen,
8298+ DrawablePtr pDraw, /* Destination drawable */
8299+ short src_x, short src_y, /* Source coordinates */
8300+ short drw_x, short drw_y, /* Destination coordinates */
8301+ short src_w, short src_h, /* Source rectangle to put */
8302+ short drw_w, short drw_h, /* Destination size */
8303+ int id, /* FOURCC id */
8304+ unsigned char *buf, /* Source data */
8305+ short width, /* Source width */
8306+ short height, /* Source height */
8307+ Bool sync, /* Sync before returning */
8308+ RegionPtr clipBoxes,
8309+ pointer data)
8310+{
8311+ ScreenPtr pScreen = screen->pScreen;
8312+ KdScreenPriv(pScreen);
8313+ W100CardInfo(pScreenPriv);
8314+ W100ScreenInfo(pScreenPriv);
8315+ W100PortPrivPtr pPortPriv = (W100PortPrivPtr)data;
8316+ CARD32 baseAddr;
8317+ int randr = w100c->hw_window.randr;
8318+ int offWidth, offHeight;
8319+ int ovlWidth, ovlHeight;
8320+ int ovlX, ovlY;
8321+ int dstX, dstY;
8322+ int offSize;
8323+ int ovlSize;
8324+ int planes;
8325+ int bpp;
8326+ int i;
8327+ INT32 x1, x2, y1, y2;
8328+ BoxRec dstBox;
8329+ int planeOffsets[3];
8330+
8331+
8332+ DBG_IMAGEON(("W100PutImage(src(x:%d,y:%d,w:%d,h:%d),"
8333+ "drw(x:%d,y:%d,w:%d,h:%d),"
8334+ "width:%d,height:%d)\n",
8335+ src_x,src_y,src_w,src_h,
8336+ drw_x,drw_y,drw_w,drw_h,
8337+ width, height));
8338+
8339+ /* Clip */
8340+ x1 = src_x;
8341+ x2 = src_x + src_w;
8342+ y1 = src_y;
8343+ y2 = src_y + src_h;
8344+
8345+ dstBox.x1 = drw_x;
8346+ dstBox.x2 = drw_x + drw_w;
8347+ dstBox.y1 = drw_y;
8348+ dstBox.y2 = drw_y + drw_h;
8349+
8350+ W100ClipVideo(&dstBox, &x1, &x2, &y1, &y2,
8351+ REGION_EXTENTS(pScreen, clipBoxes),
8352+ width, height);
8353+
8354+ if ((x1 >= x2) || (y1 >= y2)) {
8355+ return Success;
8356+ }
8357+
8358+ src_w = (x2 - x1) >> 16;
8359+ src_h = (y2 - y1) >> 16;
8360+ drw_w = dstBox.x2 - dstBox.x1;
8361+ drw_h = dstBox.y2 - dstBox.y1;
8362+ drw_x = dstBox.x1;
8363+ drw_y = dstBox.y1;
8364+ src_x = x1 >> 16;
8365+ src_y = y1 >> 16;
8366+
8367+ /* Calculate dimensions for offscren and overlay surfaces */
8368+ offWidth = src_w;
8369+ offHeight = src_h;
8370+
8371+ ovlX = W100MapToHWX(w100c, drw_x, drw_y, drw_w, drw_h);
8372+ ovlY = W100MapToHWY(w100c, drw_x, drw_y, drw_w, drw_h);
8373+
8374+ for (i = 0; i < NUM_OVL_RESIZERS; i++) {
8375+ CARD16 candidate_w = drw_w >> ovlResizers[i].xfactor;
8376+ CARD16 candidate_h = drw_h >> ovlResizers[i].yfactor;
8377+
8378+ switch (randr & RR_Rotate_All) {
8379+ case RR_Rotate_0:
8380+ ovlWidth = W100_ALIGN(candidate_w, OVL_W_ALIGN);
8381+ ovlHeight = W100_ALIGN(candidate_h, OVL_H_ALIGN);
8382+ dstX = 0;
8383+ dstY = 0;
8384+ pPortPriv->videoHorExp = ovlResizers[i].xfactor;
8385+ pPortPriv->videoVerExp = ovlResizers[i].yfactor;
8386+ break;
8387+ case RR_Rotate_180:
8388+ ovlWidth = W100_ALIGN(candidate_w, OVL_W_ALIGN);
8389+ ovlHeight = W100_ALIGN(candidate_h, OVL_H_ALIGN);
8390+ dstX = ovlWidth - candidate_w;
8391+ dstY = ovlHeight - candidate_h;
8392+ pPortPriv->videoHorExp = ovlResizers[i].xfactor;
8393+ pPortPriv->videoVerExp = ovlResizers[i].yfactor;
8394+ break;
8395+ case RR_Rotate_90:
8396+ ovlWidth = W100_ALIGN(candidate_h, OVL_W_ALIGN);
8397+ ovlHeight = W100_ALIGN(candidate_w, OVL_H_ALIGN);
8398+ dstX = (ovlWidth - candidate_h) / 2;
8399+ dstY = (ovlHeight - candidate_w) / 2;
8400+ pPortPriv->videoHorExp = ovlResizers[i].yfactor;
8401+ pPortPriv->videoVerExp = ovlResizers[i].xfactor;
8402+ break;
8403+ case RR_Rotate_270:
8404+ ovlWidth = W100_ALIGN(candidate_h, OVL_W_ALIGN);
8405+ ovlHeight = W100_ALIGN(candidate_w, OVL_H_ALIGN);
8406+ dstX = 0;
8407+ dstY = ovlHeight - candidate_w;
8408+ pPortPriv->videoHorExp = ovlResizers[i].yfactor;
8409+ pPortPriv->videoVerExp = ovlResizers[i].xfactor;
8410+ break;
8411+ }
8412+
8413+ /* Calculate sizes for the surfaces */
8414+ switch (id) {
8415+ case FOURCC_YV12:
8416+ case FOURCC_I420:
8417+ offSize = (3 * offWidth * offHeight) / 2;
8418+ ovlSize = (3 * ovlWidth * ovlHeight) / 2;
8419+ planes = 3;
8420+ planeOffsets[0] = 0;
8421+ planeOffsets[1] = ovlWidth * ovlHeight;
8422+ planeOffsets[2] = (5 * (ovlWidth * ovlHeight)) / 4;
8423+ bpp = 8;
8424+ break;
8425+ case FOURCC_UYVY:
8426+ case FOURCC_YUY2:
8427+ offSize = offWidth * offHeight * 2;
8428+ ovlSize = ovlWidth * ovlHeight * 2;
8429+ planes = 1;
8430+ planeOffsets[0] = 0;
8431+ bpp = 16;
8432+ break;
8433+ }
8434+ if (ovlSize <= pPortPriv->maxOverlaySize) {
8435+ DBG_IMAGEON(("Using %dx%d overlay surface (%d bytes). "
8436+ "Resizer(xfactor:%d,yfactor:%d)\n",
8437+ ovlWidth, ovlHeight, ovlSize,
8438+ ovlResizers[i].xfactor, ovlResizers[i].yfactor));
8439+ drw_w = candidate_w;
8440+ drw_h = candidate_h;
8441+ break;
8442+ }
8443+ }
8444+
8445+ /* Reallocate the surfaces, if existing ones are not valid.
8446+ * If overlay surface is not valid, dump both ones, to give
8447+ * ovlSurface more chances to get internal memory
8448+ */
8449+ if (pPortPriv->ovlSurface && ovlSize != pPortPriv->ovlSize) {
8450+ DBG_IMAGEON(("Freeing overlay and offscreen surfaces\n"));
8451+ KdOffscreenFree(screen->pScreen, pPortPriv->ovlSurface);
8452+ KdOffscreenFree(screen->pScreen, pPortPriv->offSurface);
8453+ pPortPriv->ovlSurface = NULL;
8454+ pPortPriv->offSurface = NULL;
8455+ }
8456+
8457+ if (pPortPriv->offSurface && offSize != pPortPriv->offSize) {
8458+ DBG_IMAGEON(("Freeing offscreen surface\n"));
8459+ KdOffscreenFree(screen->pScreen, pPortPriv->offSurface);
8460+ pPortPriv->offSurface = NULL;
8461+ }
8462+
8463+ if (!pPortPriv->ovlSurface) {
8464+ pPortPriv->ovlSurface = KdOffscreenAllocPrio(screen->pScreen,
8465+ ovlSize, 0, TRUE,
8466+ W100VideoSave,
8467+ pPortPriv,
8468+ KD_VIDMEM_MAXPRIO,
8469+ KD_VIDMEM_MAXPRIO,
8470+ TRUE);
8471+ if (!pPortPriv->ovlSurface) {
8472+ ErrorF("Using non internal memory to overlay. "
8473+ "Expected bad performance\n");
8474+ pPortPriv->ovlSurface = KdOffscreenAlloc(screen->pScreen,
8475+ ovlSize, 0, TRUE,
8476+ W100VideoSave,
8477+ pPortPriv);
8478+ }
8479+ if (!pPortPriv->ovlSurface) {
8480+ ErrorF("Unable to allocate %d bytes for overlay surface\n",
8481+ ovlSize);
8482+ return BadAlloc;
8483+ }
8484+
8485+ pPortPriv->ovlSize = ovlSize;
8486+ W100ClearSurface(screen, pPortPriv->ovlSurface,
8487+ 0, 0, (ovlWidth * bpp / 8),
8488+ ovlWidth, ovlHeight, id);
8489+ }
8490+
8491+ if (!pPortPriv->offSurface) {
8492+ pPortPriv->offSurface = KdOffscreenAlloc(screen->pScreen,
8493+ offSize, 0, TRUE,
8494+ W100VideoSave,
8495+ pPortPriv);
8496+ if (!pPortPriv->offSurface) {
8497+ ErrorF("Unable to allocate %d bytes for offscreen surface\n",
8498+ offSize);
8499+ return BadAlloc;
8500+ }
8501+ pPortPriv->offSize = offSize;
8502+ }
8503+
8504+ /* Copy the data into the offscreen surface */
8505+ W100WaitIdle(w100c);
8506+
8507+ switch (id) {
8508+ case FOURCC_YV12:
8509+ case FOURCC_I420:
8510+ W100HostPlanarData(screen, //screen
8511+ id, //id
8512+ buf, //src
8513+ pPortPriv->offSurface, //dst
8514+ width, //srcPitch
8515+ height, //srcHeight
8516+ offWidth, //dstPitch
8517+ offHeight, //dstHeight
8518+ src_x, //srcX
8519+ src_y, //srcY
8520+ 0, //dstX
8521+ 0, //dstY
8522+ src_w, //w
8523+ src_h); //h
8524+ break;
8525+ case FOURCC_UYVY:
8526+ case FOURCC_YUY2:
8527+ W100HostPackedData(screen, //screen
8528+ id, //id
8529+ buf, //src
8530+ pPortPriv->offSurface, //dst
8531+ width << 1, //srcPitch
8532+ offWidth << 1, //dstPitch
8533+ src_x, //srcX
8534+ src_y, //srcY
8535+ 0, //dstX
8536+ 0, //dstY
8537+ src_w, //w
8538+ src_h); //h
8539+ break;
8540+ }
8541+
8542+ /* Update cliplist */
8543+ if(!REGION_EQUAL(screen->pScreen, &pPortPriv->clip, clipBoxes)) {
8544+ REGION_COPY(screen->pScreen, &pPortPriv->clip, clipBoxes);
8545+ KXVPaintRegion(pDraw, &pPortPriv->clip, pPortPriv->colorKey);
8546+ }
8547+
8548+ /* Calculate the incard offsets for the different planes */
8549+ baseAddr = (CARD32) W100_HOST2CARD(pPortPriv->ovlSurface->vidmem->base +
8550+ pPortPriv->ovlSurface->offset);
8551+ switch (id) {
8552+ case FOURCC_YV12:
8553+ case FOURCC_I420:
8554+ pPortPriv->YPlaneOffset = baseAddr + planeOffsets[0];
8555+ pPortPriv->UPlaneOffset = baseAddr + planeOffsets[1];
8556+ pPortPriv->VPlaneOffset = baseAddr + planeOffsets[2];
8557+ break;
8558+ case FOURCC_UYVY:
8559+ case FOURCC_YUY2:
8560+ pPortPriv->YPlaneOffset = baseAddr + planeOffsets[0];
8561+ pPortPriv->UPlaneOffset = 0;
8562+ pPortPriv->VPlaneOffset = 0;
8563+ }
8564+
8565+ DBG_IMAGEON(("Offsets(Y:0x%08x,U:0x%08x,V:0x%08x)\n",
8566+ pPortPriv->YPlaneOffset,
8567+ pPortPriv->UPlaneOffset,
8568+ pPortPriv->VPlaneOffset));
8569+
8570+
8571+ /* Blit from offSurface to ovlSurface taking into account
8572+ * the randr needed transformation
8573+ */
8574+ W100DisableDisplayUpdate(w100c);
8575+ W100PlanarBlt(screen, planes, bpp, randr,
8576+ pPortPriv->offSurface,
8577+ src_w, offWidth * bpp / 8, src_h,
8578+ pPortPriv->ovlSurface, planeOffsets,
8579+ drw_w, ovlWidth * bpp / 8, drw_h,
8580+ dstX, dstY);
8581+ W100EnableDisplayUpdate(w100c);
8582+
8583+
8584+ if ((pPortPriv->ovlWidth != ovlWidth) ||
8585+ (pPortPriv->ovlHeight != ovlHeight) ||
8586+ (pPortPriv->ovlX != ovlX) ||
8587+ (pPortPriv->ovlY != ovlY) ||
8588+ (pPortPriv->id != id)) {
8589+ pPortPriv->videoStatus &= ~W100_OVERLAY_CONFIGURED;
8590+ W100OverlayDisable(screen);
8591+ }
8592+ /* Enable overlay */
8593+ pPortPriv->ovlWidth = ovlWidth;
8594+ pPortPriv->ovlHeight = ovlHeight;
8595+ pPortPriv->ovlX = ovlX;
8596+ pPortPriv->ovlY = ovlY;
8597+ pPortPriv->id = id;
8598+ W100OverlayEnable(screen);
8599+
8600+ return Success;
8601+}
8602+
8603+static KdVideoAdaptorPtr
8604+W100SetupImageVideo(ScreenPtr pScreen)
8605+{
8606+ KdScreenPriv(pScreen);
8607+ W100ScreenInfo(pScreenPriv);
8608+ W100CardInfo(pScreenPriv);
8609+ KdVideoAdaptorPtr adaptor;
8610+ W100PortPrivPtr pPortPriv;
8611+
8612+ adaptor = xcalloc(1, sizeof(KdVideoAdaptorRec)
8613+ + sizeof(W100PortPrivRec)
8614+ + sizeof(DevUnion));
8615+ if (adaptor == NULL) {
8616+ return NULL;
8617+ }
8618+
8619+ adaptor->type = XvWindowMask | XvInputMask | XvImageMask;
8620+ adaptor->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT;
8621+ adaptor->name = "ATI (C) Imageon Video Overlay";
8622+ adaptor->nEncodings = 1;
8623+ adaptor->pEncodings = DummyEncoding;
8624+ adaptor->nFormats = NUM_FORMATS;
8625+ adaptor->pFormats = Formats;
8626+ adaptor->nPorts = 1;
8627+ adaptor->pPortPrivates = (DevUnion*)(&adaptor[1]);
8628+
8629+ pPortPriv = (W100PortPrivPtr)(&adaptor->pPortPrivates[1]);
8630+
8631+ adaptor->pPortPrivates[0].ptr = (pointer)(pPortPriv);
8632+
8633+ adaptor->nAttributes = NUM_ATTRIBUTES;
8634+ adaptor->pAttributes = Attributes;
8635+ adaptor->pImages = Images;
8636+ adaptor->nImages = NUM_IMAGES;
8637+ adaptor->PutVideo = NULL;
8638+ adaptor->PutStill = NULL;
8639+ adaptor->GetVideo = NULL;
8640+ adaptor->GetStill = NULL;
8641+ adaptor->StopVideo = W100StopVideo;
8642+ adaptor->SetPortAttribute = W100SetPortAttribute;
8643+ adaptor->GetPortAttribute = W100GetPortAttribute;
8644+ adaptor->QueryBestSize = W100QueryBestSize;
8645+ adaptor->PutImage = W100PutImage;
8646+ adaptor->ReputImage = NULL;
8647+ adaptor->QueryImageAttributes = W100QueryImageAttributes;
8648+
8649+ REGION_INIT(pScreen, &pPortPriv->clip, NullBox, 0);
8650+
8651+ w100s->pAdaptor = adaptor;
8652+
8653+ xvBrightness = MAKE_ATOM("XV_BRIGHTNESS");
8654+ xvColorKey = MAKE_ATOM("XV_COLORKEY");
8655+ xvMaxOverlaySize = MAKE_ATOM("XV_MAXOVERLAYSIZE");
8656+
8657+ pPortPriv->maxOverlaySize = OVL_MAX_SIZE;
8658+ pPortPriv->colorKey = 0xff00;
8659+ pPortPriv->brightness = W100GetBrightness(w100c);
8660+ return adaptor;
8661+}
8662+
8663+Bool W100InitVideo(ScreenPtr pScreen)
8664+{
8665+ KdScreenPriv(pScreen);
8666+ W100ScreenInfo(pScreenPriv);
8667+ W100CardInfo(pScreenPriv);
8668+ KdScreenInfo *screen = pScreenPriv->screen;
8669+ KdVideoAdaptorPtr *adaptors, *newAdaptors = NULL;
8670+ KdVideoAdaptorPtr newAdaptor = NULL;
8671+ int num_adaptors;
8672+
8673+ w100s->pAdaptor = NULL;
8674+
8675+ if (w100c->reg_base == NULL)
8676+ return FALSE;
8677+
8678+ num_adaptors = KdXVListGenericAdaptors(screen, &adaptors);
8679+
8680+ newAdaptor = W100SetupImageVideo(pScreen);
8681+
8682+ if (newAdaptor) {
8683+ if (!num_adaptors) {
8684+ num_adaptors = 1;
8685+ adaptors = &newAdaptor;
8686+ } else {
8687+ newAdaptors = xalloc((num_adaptors + 1) *
8688+ sizeof(KdVideoAdaptorPtr *));
8689+ if (newAdaptors) {
8690+ memcpy(newAdaptors, adaptors, num_adaptors *
8691+ sizeof(KdVideoAdaptorPtr));
8692+ newAdaptors[num_adaptors] = newAdaptor;
8693+ adaptors = newAdaptors;
8694+ num_adaptors++;
8695+ }
8696+ }
8697+ }
8698+
8699+ if (num_adaptors)
8700+ KdXVScreenInit(pScreen, adaptors, num_adaptors);
8701+
8702+ if (newAdaptors)
8703+ xfree(newAdaptors);
8704+
8705+ return TRUE;
8706+}
8707+
8708+void
8709+W100FiniVideo(ScreenPtr pScreen)
8710+{
8711+ KdScreenPriv(pScreen);
8712+ W100ScreenInfo(pScreenPriv);
8713+ KdVideoAdaptorPtr adaptor = w100s->pAdaptor;
8714+ W100PortPrivPtr pPortPriv;
8715+ int i;
8716+
8717+ if (!adaptor)
8718+ return;
8719+
8720+ pPortPriv = (W100PortPrivPtr)(&adaptor->pPortPrivates[0].ptr);
8721+ REGION_UNINIT(pScreen, &pPortPriv->clip);
8722+
8723+ xfree(adaptor);
8724+ w100s->pAdaptor = NULL;
8725+}
8726+
8727--- /dev/null
8728+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/imageon/imageon_support.h
8729@@ -0,0 +1,98 @@
8730+/*
8731+ * Copyright © 2007 Manuel Teira
8732+ *
8733+ * Permission to use, copy, modify, distribute, and sell this software and its
8734+ * documentation for any purpose is hereby granted without fee, provided that
8735+ * the above copyright notice appear in all copies and that both that
8736+ * copyright notice and this permission notice appear in supporting
8737+ * documentation, and that the name of Manuel Teira not be used in
8738+ * advertising or publicity pertaining to distribution of the software without
8739+ * specific, written prior permission. Manuel Teira makes no
8740+ * representations about the suitability of this software for any purpose. It
8741+ * is provided "as is" without express or implied warranty.
8742+ *
8743+ * MANUEL TEIRA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
8744+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
8745+ * EVENT SHALL MANUEL TEIRA BE LIABLE FOR ANY SPECIAL, INDIRECT OR
8746+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
8747+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
8748+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
8749+ * PERFORMANCE OF THIS SOFTWARE.
8750+ */
8751+
8752+#ifndef _IMAGEON_SUPPORT_H_
8753+#define _IMAGEON_SUPPORT_H
8754+
8755+#include "imageon.h"
8756+
8757+extern CARD8 W100SolidRop[16];
8758+extern CARD8 W100BltRop[16];
8759+
8760+void W100DisableDisplayUpdate(W100CardInfo *w100c);
8761+void W100EnableDisplayUpdate(W100CardInfo *w100c);
8762+void W100SetupGraphicEngine(W100CardInfo *w100c);
8763+void W100ResetGraphicEngine(W100CardInfo *w100c);
8764+void W100SetupGraphicWindow(W100CardInfo *w100c);
8765+void W100EnableGraphicWindow(W100CardInfo *w100c);
8766+void W100DisableGraphicWindow(W100CardInfo *w100c);
8767+inline Bool W100WaitCmdFifoEntries(W100CardInfo *w100c, int entries);
8768+Bool W100WaitIdle(W100CardInfo *w100c);
8769+void W100ResetContext(W100CardInfo *w100c);
8770+CARD32 W100ComputeSolidGmc(W100CardInfo *w100c, CARD8 alu);
8771+CARD32 W100ComputeCopyGmc(W100CardInfo *w100c, CARD8 alu);
8772+CARD32 W100ComputeAritGmc(W100CardInfo *w100c, CARD8 alu);
8773+void W100SetXForm(W100CardInfo *w100c, int dx, int dy);
8774+void W100SetRotation(W100CardInfo *w100c, int randr, Bool mirror);
8775+void W100SetPixelMask(W100CardInfo *w100c, Pixel mask);
8776+Bool W100SetSource(KdScreenInfo *screen, CARD32 srcPitch,
8777+ CARD32 srcOffset, CARD8 bpp);
8778+Bool W100SetDestination(KdScreenInfo *screen, CARD32 dstPitch,
8779+ CARD32 dstOffset, CARD8 bpp);
8780+Bool W100SetSourcePixmap(PixmapPtr pPix);
8781+Bool W100SetDestinationPixmap(PixmapPtr pPix);
8782+int W100MapToHWX(W100CardInfo *w100c,
8783+ int x, int y, int w, int h);
8784+int W100MapToHWY(W100CardInfo *w100c,
8785+ int x, int y, int w, int h);
8786+int W100MapToHWW(W100CardInfo *w100c,
8787+ int x, int y, int w, int h);
8788+int W100MapToHWH(W100CardInfo *w100c,
8789+ int x, int y, int w, int h);
8790+CARD16 W100XformX(W100CardInfo *w100c, CARD16 x, CARD16 y, CARD16 w, CARD16 h);
8791+CARD16 W100XformY(W100CardInfo *w100c, CARD16 x, CARD16 y, CARD16 w, CARD16 h);
8792+CARD16 W100XformW(W100CardInfo *w100c, CARD16 x, CARD16 y, CARD16 w, CARD16 h);
8793+CARD16 W100XformH(W100CardInfo *w100c, CARD16 x, CARD16 y, CARD16 w, CARD16 h);
8794+CARD8 W100GetScaler(CARD16 dstsize, CARD16 srcsize);
8795+CARD16 W100ApplyScaler(CARD16 srcsize, CARD8 scaler);
8796+static void W100Blt(KdScreenInfo *screen, int randr, int bpp,
8797+ CARD32 srcOffset, CARD16 srcW, CARD16 srcH, CARD16 srcPitch,
8798+ CARD32 dstOffset, CARD16 dstPitch,
8799+ CARD16 dstX, CARD16 dstY);
8800+static void W100StretchBlt(KdScreenInfo *screen, int randr, int bpp,
8801+ CARD32 srcOffset, CARD16 srcW, CARD16 srcH,
8802+ CARD16 srcPitch,
8803+ CARD32 dstOffset, CARD16 dstPitch,
8804+ CARD16 dstX, CARD16 dstY,
8805+ CARD8 xscaler, CARD8 yscaler);
8806+static void W100ScaledBlt(KdScreenInfo *screen, int randr, int bpp,
8807+ CARD32 srcOffset, CARD16 srcW, CARD16 srcH,
8808+ CARD16 srcPitch,
8809+ CARD32 dstOffset, CARD16 dstPitch,
8810+ CARD16 dstX, CARD16 dstY,
8811+ CARD8 xscaler, CARD8 yscaler);
8812+void W100PlanarBlt(KdScreenInfo *screen, int planes, int bpp, int randr,
8813+ KdOffscreenArea *src, int srcW, int srcPitch, int srcH,
8814+ KdOffscreenArea *dst, int planeOffsets[],
8815+ int dstW, int dstPitch, int dstH,
8816+ int dstX, int dstY);
8817+CARD8 W100GetBrightness(W100CardInfo *w100c);
8818+void W100SetBrightness(W100CardInfo *w100c, CARD8 value);
8819+int W100GetRotation(W100CardInfo *w100c);
8820+W100ModeSpec *W100GetModeSpec(W100CardInfo *w100c, W100Mode *mode);
8821+Bool W100GetFbMode(W100CardInfo *w100c, W100Mode *mode);
8822+Bool W100CheckFbMode(W100CardInfo *w100c, W100ModeSpec *modes);
8823+W100ModeSpec *W100GetBestMode(W100CardInfo *w100c, int width, int height);
8824+void W100TransformTsLibCoordinates(long *x, long *y, void *closure);
8825+Bool W100SysFsGet(W100CardInfo *w100c, const char *path, char *value);
8826+Bool W100SysFsSet(W100CardInfo *w100c, const char *path, const char *value);
8827+#endif
8828--- xorg-server-X11R7.1-1.1.0.work/hw/kdrive/linux/tslib.c~kdrive-imageon
8829+++ xorg-server-X11R7.1-1.1.0.work/hw/kdrive/linux/tslib.c
8830@@ -92,6 +92,10 @@
8831 void (*tslib_raw_event_hook)(int x, int y, int pressure, void *closure);
8832 void *tslib_raw_event_closure;
8833
8834+/* To support randr hot resolution change */
8835+void (*tslib_transform_coords)(long *x, long *y, void *closure);
8836+void *tslib_transform_closure;
8837+
8838 int TsInputType = 0;
8839 int KdTsPhyScreen = 0; /* XXX Togo .. */
8840
8841@@ -121,7 +125,9 @@
8842 flags = (event.pressure) ? KD_BUTTON_1 : 0;
8843 x = event.x;
8844 y = event.y;
8845-
8846+ if (tslib_transform_coords) {
8847+ tslib_transform_coords(&x, &y, tslib_transform_closure);
8848+ }
8849 KdEnqueueMouseEvent (mi, flags, x, y);
8850 }
8851 }
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-16 12:31:42 +0000