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authorMarcin Juszkiewicz <hrw@openedhand.com>2007-10-29 11:00:19 +0000
committerMarcin Juszkiewicz <hrw@openedhand.com>2007-10-29 11:00:19 +0000
commit70abc059ebae6bd18399c0361d348f415a3f631a (patch)
tree86ae8bf44d64d40603b5bca6774eac7f1aaa3ce5 /meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch
parentce1e498f5d3a46642b6bb14c14ebae2a52f732a4 (diff)
downloadpoky-70abc059ebae6bd18399c0361d348f415a3f631a.tar.gz
u-boot: import OpenMoko uboot from OE
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@3014 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch')
-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch1411
1 files changed, 1411 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch
new file mode 100644
index 0000000000..5757cc078b
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch
@@ -0,0 +1,1411 @@
1Index: u-boot/Makefile
2===================================================================
3--- u-boot.orig/Makefile
4+++ u-boot/Makefile
5@@ -2045,6 +2045,9 @@
6 smdk2440_config : unconfig
7 @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0
8
9+smdk2443_config : unconfig
10+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2443 NULL s3c24x0
11+
12 SX1_config : unconfig
13 @$(MKCONFIG) $(@:_config=) arm arm925t sx1
14
15Index: u-boot/board/smdk2443/Makefile
16===================================================================
17--- /dev/null
18+++ u-boot/board/smdk2443/Makefile
19@@ -0,0 +1,67 @@
20+#
21+# (C) Copyright 2000-2006
22+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
23+#
24+# See file CREDITS for list of people who contributed to this
25+# project.
26+#
27+# This program is free software; you can redistribute it and/or
28+# modify it under the terms of the GNU General Public License as
29+# published by the Free Software Foundation; either version 2 of
30+# the License, or (at your option) any later version.
31+#
32+# This program is distributed in the hope that it will be useful,
33+# but WITHOUT ANY WARRANTY; without even the implied warranty of
34+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35+# GNU General Public License for more details.
36+#
37+# You should have received a copy of the GNU General Public License
38+# along with this program; if not, write to the Free Software
39+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40+# MA 02111-1307 USA
41+#
42+
43+include $(TOPDIR)/config.mk
44+
45+LIB = $(obj)lib$(BOARD).a
46+
47+COBJS := smdk2443.o flash.o udc.o
48+SOBJS := lowlevel_init.o
49+
50+.PHONY: all
51+
52+all: $(LIB) lowlevel_foo.bin
53+
54+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
55+OBJS := $(addprefix $(obj),$(COBJS))
56+SOBJS := $(addprefix $(obj),$(SOBJS))
57+
58+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
59+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
60+
61+lowlevel_foo.o: lowlevel_foo.S
62+ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \
63+ -o lowlevel_foo.o lowlevel_foo.S
64+
65+lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds
66+ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \
67+ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo
68+
69+lowlevel_foo.bin: lowlevel_foo
70+ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \
71+ lowlevel_foo lowlevel_foo.bin
72+
73+clean:
74+ rm -f $(SOBJS) $(OBJS)
75+
76+distclean: clean
77+ rm -f $(LIB) core *.bak .depend
78+
79+#########################################################################
80+
81+# defines $(obj).depend target
82+include $(SRCTREE)/rules.mk
83+
84+sinclude $(obj).depend
85+
86+#########################################################################
87Index: u-boot/board/smdk2443/smdk2443.c
88===================================================================
89--- /dev/null
90+++ u-boot/board/smdk2443/smdk2443.c
91@@ -0,0 +1,147 @@
92+/*
93+ * (C) Copyright 2006 OpenMoko, Inc.
94+ * Author: Harald Welte <laforge@openmoko.org>
95+ *
96+ * See file CREDITS for list of people who contributed to this
97+ * project.
98+ *
99+ * This program is free software; you can redistribute it and/or
100+ * modify it under the terms of the GNU General Public License as
101+ * published by the Free Software Foundation; either version 2 of
102+ * the License, or (at your option) any later version.
103+ *
104+ * This program is distributed in the hope that it will be useful,
105+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
106+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
107+ * GNU General Public License for more details.
108+ *
109+ * You should have received a copy of the GNU General Public License
110+ * along with this program; if not, write to the Free Software
111+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
112+ * MA 02111-1307 USA
113+ */
114+
115+#include <common.h>
116+#include <s3c2440.h>
117+
118+DECLARE_GLOBAL_DATA_PTR;
119+
120+#define FCLK_SPEED 1
121+
122+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
123+#define M_MDIV 0xC3
124+#define M_PDIV 0x4
125+#define M_SDIV 0x1
126+#elif FCLK_SPEED==1 /* Fout = 399.65MHz */
127+#define M_MDIV 0x6e
128+#define M_PDIV 0x3
129+#define M_SDIV 0x1
130+#endif
131+
132+#define USB_CLOCK 1
133+
134+#if USB_CLOCK==0
135+#define U_M_MDIV 0xA1
136+#define U_M_PDIV 0x3
137+#define U_M_SDIV 0x1
138+#elif USB_CLOCK==1
139+#define U_M_MDIV 0x3c
140+#define U_M_PDIV 0x4
141+#define U_M_SDIV 0x2
142+#endif
143+
144+static inline void delay (unsigned long loops)
145+{
146+ __asm__ volatile ("1:\n"
147+ "subs %0, %1, #1\n"
148+ "bne 1b":"=r" (loops):"0" (loops));
149+}
150+
151+/*
152+ * Miscellaneous platform dependent initialisations
153+ */
154+
155+int board_init (void)
156+{
157+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
158+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
159+
160+ /* to reduce PLL lock time, adjust the LOCKTIME register */
161+ clk_power->LOCKTIME = 0xFFFFFF;
162+
163+ /* configure MPLL */
164+ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
165+
166+ /* some delay between MPLL and UPLL */
167+ delay (4000);
168+
169+ /* configure UPLL */
170+ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
171+
172+ /* some delay between MPLL and UPLL */
173+ delay (8000);
174+
175+ /* set up the I/O ports */
176+ gpio->GPACON = 0x007FFFFF;
177+ gpio->GPBCON = 0x00044555;
178+ gpio->GPBUP = 0x000007FF;
179+ gpio->GPCCON = 0xAAAAAAAA;
180+ gpio->GPCUP = 0x0000FFFF;
181+ gpio->GPDCON = 0xAAAAAAAA;
182+ gpio->GPDUP = 0x0000FFFF;
183+ gpio->GPECON = 0xAAAAAAAA;
184+ gpio->GPEUP = 0x0000FFFF;
185+ gpio->GPFCON = 0x000055AA;
186+ gpio->GPFUP = 0x000000FF;
187+ gpio->GPGCON = 0xFD95FFBA;
188+ gpio->GPGUP = 0x0000FFFF;
189+#ifdef CONFIG_SERIAL3
190+ gpio->GPHCON = 0x002AAAAA;
191+#else
192+ gpio->GPHCON = 0x002AFAAA;
193+#endif
194+ gpio->GPHUP = 0x000007FF;
195+
196+#if 0
197+ /* USB Device Part */
198+ /*GPGCON is reset for USB Device */
199+ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
200+ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */
201+
202+ gpio->GPGDAT |= ( 1 << 12) ;
203+ gpio->GPGDAT &= ~( 1 << 12) ;
204+ udelay(20000);
205+ gpio->GPGDAT |= ( 1 << 12) ;
206+#endif
207+
208+ /* arch number of SMDK2440-Board */
209+ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
210+
211+ /* adress of boot parameters */
212+ gd->bd->bi_boot_params = 0x30000100;
213+
214+ icache_enable();
215+ dcache_enable();
216+
217+ return 0;
218+}
219+
220+int dram_init (void)
221+{
222+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
223+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
224+
225+ return 0;
226+}
227+
228+/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
229+ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
230+ images: 640*480*2*2 = 1228800 < 1245184. */
231+
232+unsigned int dynpart_size[] = {
233+ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 };
234+
235+char *dynpart_names[] = {
236+ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
237+
238+
239Index: u-boot/board/smdk2443/u-boot.lds
240===================================================================
241--- /dev/null
242+++ u-boot/board/smdk2443/u-boot.lds
243@@ -0,0 +1,58 @@
244+/*
245+ * (C) Copyright 2002
246+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
247+ *
248+ * See file CREDITS for list of people who contributed to this
249+ * project.
250+ *
251+ * This program is free software; you can redistribute it and/or
252+ * modify it under the terms of the GNU General Public License as
253+ * published by the Free Software Foundation; either version 2 of
254+ * the License, or (at your option) any later version.
255+ *
256+ * This program is distributed in the hope that it will be useful,
257+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
258+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
259+ * GNU General Public License for more details.
260+ *
261+ * You should have received a copy of the GNU General Public License
262+ * along with this program; if not, write to the Free Software
263+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
264+ * MA 02111-1307 USA
265+ */
266+
267+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
268+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
269+OUTPUT_ARCH(arm)
270+ENTRY(_start)
271+SECTIONS
272+{
273+ . = 0x00000000;
274+
275+ . = ALIGN(4);
276+ .text :
277+ {
278+ cpu/arm920t/start.o (.text)
279+ cpu/arm920t/s3c24x0/nand_read.o (.text)
280+ *(.text)
281+ }
282+
283+ . = ALIGN(4);
284+ .rodata : { *(.rodata) }
285+
286+ . = ALIGN(4);
287+ .data : { *(.data) }
288+
289+ . = ALIGN(4);
290+ .got : { *(.got) }
291+
292+ . = .;
293+ __u_boot_cmd_start = .;
294+ .u_boot_cmd : { *(.u_boot_cmd) }
295+ __u_boot_cmd_end = .;
296+
297+ . = ALIGN(4);
298+ __bss_start = .;
299+ .bss : { *(.bss) }
300+ _end = .;
301+}
302Index: u-boot/include/configs/smdk2443.h
303===================================================================
304--- /dev/null
305+++ u-boot/include/configs/smdk2443.h
306@@ -0,0 +1,289 @@
307+/*
308+ * (C) Copyright 2007 OpenMoko, Inc.
309+ * Author: Harald Welte <laforge@openmoko.org>
310+ *
311+ * Configuation settings for the SAMSUNG SMDK2443 board.
312+ *
313+ * See file CREDITS for list of people who contributed to this
314+ * project.
315+ *
316+ * This program is free software; you can redistribute it and/or
317+ * modify it under the terms of the GNU General Public License as
318+ * published by the Free Software Foundation; either version 2 of
319+ * the License, or (at your option) any later version.
320+ *
321+ * This program is distributed in the hope that it will be useful,
322+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
323+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
324+ * GNU General Public License for more details.
325+ *
326+ * You should have received a copy of the GNU General Public License
327+ * along with this program; if not, write to the Free Software
328+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
329+ * MA 02111-1307 USA
330+ */
331+
332+#ifndef __CONFIG_H
333+#define __CONFIG_H
334+
335+#if 0
336+/* If we want to start u-boot from usb bootloader in NOR flash */
337+#define CONFIG_SKIP_RELOCATE_UBOOT 1
338+#define CONFIG_SKIP_LOWLEVEL_INIT 1
339+#else
340+/* If we want to start u-boot directly from within NAND flash */
341+#define CONFIG_LL_INIT_NAND_ONLY
342+#define CONFIG_S3C2410_NAND_BOOT 1
343+#define CONFIG_S3C2410_NAND_SKIP_BAD 1
344+#endif
345+
346+#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
347+
348+/*
349+ * High Level Configuration Options
350+ * (easy to change)
351+ */
352+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
353+#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */
354+#define CONFIG_SMDK2443 1 /* on a SAMSUNG SMDK2440 Board */
355+
356+/* input clock of PLL */
357+#define CONFIG_SYS_CLK_FREQ 16934400/* SMDK2440 has 16.9344MHz input clock */
358+
359+
360+#define USE_920T_MMU 1
361+#define CONFIG_USE_IRQ 1
362+
363+/*
364+ * Size of malloc() pool
365+ */
366+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024)
367+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
368+
369+/*
370+ * Hardware drivers
371+ */
372+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
373+#define CS8900_BASE 0x19000300
374+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
375+
376+/*
377+ * select serial console configuration
378+ */
379+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */
380+#define CONFIG_HWFLOW 1
381+
382+/************************************************************
383+ * RTC
384+ ************************************************************/
385+#define CONFIG_RTC_S3C24X0 1
386+
387+/* allow to overwrite serial and ethaddr */
388+#define CONFIG_ENV_OVERWRITE
389+
390+#define CONFIG_BAUDRATE 115200
391+
392+/***********************************************************
393+ * Command definition
394+ ***********************************************************/
395+#define CONFIG_COMMANDS \
396+ (CONFIG_CMD_DFL | \
397+ /*CFG_CMD_BSP | */ \
398+ CFG_CMD_CACHE | \
399+ CFG_CMD_DATE | \
400+ /*CFG_CMD_DHCP | */ \
401+ CFG_CMD_DIAG | \
402+ CFG_CMD_ELF | \
403+ CFG_CMD_EXT2 | \
404+ CFG_CMD_FAT | \
405+ /*CFG_CMD_HWFLOW | */ \
406+ /* CFG_CMD_IDE | */ \
407+ /* CFG_CMD_IRQ | */ \
408+ CFG_CMD_JFFS2 | \
409+ CFG_CMD_MMC | \
410+ CFG_CMD_NAND | \
411+ CFG_CMD_PING | \
412+ CFG_CMD_PORTIO | \
413+ CFG_CMD_REGINFO | \
414+ CFG_CMD_SAVES | \
415+ CFG_CMD_LICENSE | \
416+ CFG_CMD_USB)
417+
418+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
419+#include <cmd_confdefs.h>
420+
421+#define CONFIG_BOOTDELAY 3
422+#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8"
423+#define CONFIG_ETHADDR 00:0c:20:02:0a:5b
424+#define CONFIG_NETMASK 255.255.255.0
425+#define CONFIG_IPADDR 192.168.1.100
426+#define CONFIG_SERVERIP 192.168.1.21
427+#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm"
428+
429+#define CONFIG_DOS_PARTITION 1
430+
431+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
432+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
433+/* what's this ? it's not used anywhere */
434+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
435+#endif
436+
437+/*
438+ * Miscellaneous configurable options
439+ */
440+#define CFG_LONGHELP /* undef to save memory */
441+#define CFG_PROMPT "SMDK2443 # " /* Monitor Command Prompt */
442+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
443+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
444+#define CFG_MAXARGS 32 /* max number of command args */
445+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
446+
447+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
448+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
449+
450+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
451+
452+#define CFG_LOAD_ADDR 0x32000000 /* default load address */
453+
454+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
455+/* it to wrap 100 times (total 1562500) to get 1 sec. */
456+#define CFG_HZ 1562500
457+
458+/* valid baudrates */
459+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
460+
461+/*-----------------------------------------------------------------------
462+ * Stack sizes
463+ *
464+ * The stack sizes are set up in start.S using the settings below
465+ */
466+#define CONFIG_STACKSIZE (512*1024) /* regular stack */
467+#ifdef CONFIG_USE_IRQ
468+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
469+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
470+#endif
471+
472+/* IDE/ATA config */
473+
474+#if 0
475+#define CFG_IDE_MAXBUS 1
476+#define CFG_IDE_MAXDEVICE 2
477+#define CFG_IDE_PREINIT 0
478+
479+#define CFG_ATA_BASE_ADDR
480+#endif
481+
482+#define CONFIG_USB_OHCI 1
483+
484+#define CONFIG_USB_DEVICE 1
485+#define CONFIG_USB_TTY 1
486+#define CFG_CONSOLE_IS_IN_ENV 1
487+#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */
488+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
489+#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
490+#define CONFIG_USBD_MANUFACTURER "FiWin"
491+#define CONFIG_USBD_PRODUCT_NAME "S3C2443 Bootloader " U_BOOT_VERSION
492+#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0"
493+#define CONFIG_USBD_DFU 1
494+#define CONFIG_USBD_DFU_XFER_SIZE 4096
495+#define CONFIG_USBD_DFU_INTERFACE 2
496+
497+/*-----------------------------------------------------------------------
498+ * Physical Memory Map
499+ */
500+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
501+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
502+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
503+
504+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
505+
506+#define CFG_FLASH_BASE PHYS_FLASH_1
507+
508+/*-----------------------------------------------------------------------
509+ * FLASH and environment organization
510+ */
511+
512+#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
513+#if 0
514+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
515+#endif
516+
517+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
518+#ifdef CONFIG_AMD_LV800
519+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
520+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
521+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
522+#endif
523+#ifdef CONFIG_AMD_LV400
524+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
525+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
526+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
527+#endif
528+
529+/* timeout values are in ticks */
530+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
531+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
532+
533+#define CFG_ENV_IS_IN_NAND 1
534+#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */
535+#define CFG_ENV_OFFSET_OOB 1
536+#define CFG_PREBOOT_OVERRIDE 1
537+
538+#define NAND_MAX_CHIPS 1
539+#define CFG_NAND_BASE 0x4e000000
540+#define CFG_MAX_NAND_DEVICE 1
541+
542+#define CONFIG_MMC 1
543+#define CFG_MMC_BASE 0xff000000
544+
545+#define CONFIG_EXT2 1
546+
547+/* FAT driver in u-boot is broken currently */
548+#define CONFIG_FAT 1
549+#define CONFIG_SUPPORT_VFAT
550+
551+#if 1
552+/* JFFS2 driver */
553+#define CONFIG_JFFS2_CMDLINE 1
554+#define CONFIG_JFFS2_NAND 1
555+#define CONFIG_JFFS2_NAND_DEV 0
556+//#define CONFIG_JFFS2_NAND_OFF 0x634000
557+//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
558+#endif
559+
560+/* ATAG configuration */
561+#define CONFIG_INITRD_TAG 1
562+#define CONFIG_SETUP_MEMORY_TAGS 1
563+#define CONFIG_CMDLINE_TAG 1
564+#if 0
565+#define CONFIG_SERIAL_TAG 1
566+#define CONFIG_REVISION_TAG 1
567+#endif
568+
569+
570+#if 0
571+#define CONFIG_VIDEO
572+#define CONFIG_VIDEO_S3C2410
573+#define CONFIG_CFB_CONSOLE
574+#define CONFIG_VIDEO_LOGO
575+#define CONFIG_VGA_AS_SINGLE_DEVICE
576+
577+#define VIDEO_KBD_INIT_FCT 0
578+#define VIDEO_TSTC_FCT serial_tstc
579+#define VIDEO_GETC_FCT serial_getc
580+
581+#define LCD_VIDEO_ADDR 0x33d00000
582+#endif
583+
584+#define CONFIG_S3C2410_NAND_BBT 1
585+//#define CONFIG_S3C2410_NAND_HWECC 1
586+
587+#define CFG_NAND_YAFFS_WRITE
588+#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT
589+
590+#define MTDIDS_DEFAULT "nand0=smdk2443-nand"
591+#define MTPARTS_DEFAULT "smdk2443-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)"
592+#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2443-nand"
593+#define CONFIG_NAND_DYNPART
594+
595+#endif /* __CONFIG_H */
596Index: u-boot/board/smdk2443/lowlevel_foo.S
597===================================================================
598--- /dev/null
599+++ u-boot/board/smdk2443/lowlevel_foo.S
600@@ -0,0 +1,82 @@
601+
602+_start:
603+ b reset
604+undefvec:
605+ b undefvec
606+swivec:
607+ b swivec
608+pabtvec:
609+ b pabtvec
610+dabtvec:
611+ b dabtvec
612+rsvdvec:
613+ b rsvdvec
614+irqvec:
615+ b irqvec
616+fiqvec:
617+ b fiqvec
618+
619+reset:
620+ /*
621+ * set the cpu to SVC32 mode
622+ */
623+ mrs r0,cpsr
624+ bic r0,r0,#0x1f
625+ orr r0,r0,#0xd3
626+ msr cpsr,r0
627+
628+/* turn off the watchdog */
629+#define pWTCON 0x53000000
630+#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
631+#define INTSUBMSK 0x4A00001C
632+#define CLKDIVN 0x4C000014 /* clock divisor register */
633+
634+ ldr r0, =pWTCON
635+ mov r1, #0x0
636+ str r1, [r0]
637+
638+ mov r1, #0xffffffff
639+ ldr r0, =INTMSK
640+ str r1, [r0]
641+ ldr r1, =0x3ff
642+ ldr r0, =INTSUBMSK
643+ str r1, [r0]
644+
645+ /* FCLK:HCLK:PCLK = 1:2:4 */
646+ /* default FCLK is 120 MHz ! */
647+ ldr r0, =CLKDIVN
648+ mov r1, #3
649+ str r1, [r0]
650+
651+ bl cpu_init_crit
652+ ldr r0,=TEXT_BASE
653+ mov pc, r0
654+
655+cpu_init_crit:
656+ /*
657+ * flush v4 I/D caches
658+ */
659+ mov r0, #0
660+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
661+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
662+
663+ /*
664+ * disable MMU stuff and caches
665+ */
666+ mrc p15, 0, r0, c1, c0, 0
667+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
668+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
669+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
670+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
671+ mcr p15, 0, r0, c1, c0, 0
672+
673+ /*
674+ * before relocating, we have to setup RAM timing
675+ * because memory timing is board-dependend, you will
676+ * find a lowlevel_init.S in your board directory.
677+ */
678+ mov ip, lr
679+ bl lowlevel_init
680+ mov lr, ip
681+ mov pc, lr
682+
683Index: u-boot/board/smdk2443/lowlevel_init.S
684===================================================================
685--- /dev/null
686+++ u-boot/board/smdk2443/lowlevel_init.S
687@@ -0,0 +1,163 @@
688+/*
689+ * SMDK2443 Memory Setup
690+ *
691+ * Copyright (C) 2007 by OpenMoko, Inc.
692+ * Author: Harald Welte <laforge@openmoko.org>
693+ *
694+ * See file CREDITS for list of people who contributed to this
695+ * project.
696+ *
697+ * This program is free software; you can redistribute it and/or
698+ * modify it under the terms of the GNU General Public License as
699+ * published by the Free Software Foundation; either version 2 of
700+ * the License, or (at your option) any later version.
701+ *
702+ * This program is distributed in the hope that it will be useful,
703+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
704+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
705+ * GNU General Public License for more details.
706+ *
707+ * You should have received a copy of the GNU General Public License
708+ * along with this program; if not, write to the Free Software
709+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
710+ * MA 02111-1307 USA
711+ */
712+
713+
714+#include <config.h>
715+#include <version.h>
716+
717+
718+/* some parameters for the board */
719+
720+/*
721+ *
722+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
723+ *
724+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
725+ *
726+ */
727+
728+#define BWSCON 0x48000000
729+
730+/* BWSCON */
731+#define DW8 (0x0)
732+#define DW16 (0x1)
733+#define DW32 (0x2)
734+#define WAIT (0x1<<2)
735+#define UBLB (0x1<<3)
736+
737+#define B1_BWSCON (DW32)
738+#define B2_BWSCON (DW16)
739+#define B3_BWSCON (DW16 + WAIT + UBLB)
740+#define B4_BWSCON (DW16)
741+#define B5_BWSCON (DW16)
742+#define B6_BWSCON (DW32)
743+#define B7_BWSCON (DW32)
744+
745+/* BANK0CON */
746+#define B0_Tacs 0x0 /* 0clk */
747+#define B0_Tcos 0x0 /* 0clk */
748+#define B0_Tacc 0x7 /* 14clk */
749+#define B0_Tcoh 0x0 /* 0clk */
750+#define B0_Tah 0x0 /* 0clk */
751+#define B0_Tacp 0x0
752+#define B0_PMC 0x0 /* normal */
753+
754+/* BANK1CON */
755+#define B1_Tacs 0x0 /* 0clk */
756+#define B1_Tcos 0x0 /* 0clk */
757+#define B1_Tacc 0x7 /* 14clk */
758+#define B1_Tcoh 0x0 /* 0clk */
759+#define B1_Tah 0x0 /* 0clk */
760+#define B1_Tacp 0x0
761+#define B1_PMC 0x0
762+
763+#define B2_Tacs 0x0
764+#define B2_Tcos 0x0
765+#define B2_Tacc 0x7
766+#define B2_Tcoh 0x0
767+#define B2_Tah 0x0
768+#define B2_Tacp 0x0
769+#define B2_PMC 0x0
770+
771+#define B3_Tacs 0x0 /* 0clk */
772+#define B3_Tcos 0x3 /* 4clk */
773+#define B3_Tacc 0x7 /* 14clk */
774+#define B3_Tcoh 0x1 /* 1clk */
775+#define B3_Tah 0x0 /* 0clk */
776+#define B3_Tacp 0x3 /* 6clk */
777+#define B3_PMC 0x0 /* normal */
778+
779+#define B4_Tacs 0x0 /* 0clk */
780+#define B4_Tcos 0x0 /* 0clk */
781+#define B4_Tacc 0x7 /* 14clk */
782+#define B4_Tcoh 0x0 /* 0clk */
783+#define B4_Tah 0x0 /* 0clk */
784+#define B4_Tacp 0x0
785+#define B4_PMC 0x0 /* normal */
786+
787+#define B5_Tacs 0x0 /* 0clk */
788+#define B5_Tcos 0x0 /* 0clk */
789+#define B5_Tacc 0x7 /* 14clk */
790+#define B5_Tcoh 0x0 /* 0clk */
791+#define B5_Tah 0x0 /* 0clk */
792+#define B5_Tacp 0x0
793+#define B5_PMC 0x0 /* normal */
794+
795+#define B6_MT 0x3 /* SDRAM */
796+#define B6_Trcd 0x1
797+#define B6_SCAN 0x1 /* 9bit */
798+
799+#define B7_MT 0x3 /* SDRAM */
800+#define B7_Trcd 0x1 /* 3clk */
801+#define B7_SCAN 0x1 /* 9bit */
802+
803+/* REFRESH parameter */
804+#define REFEN 0x1 /* Refresh enable */
805+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
806+#define Trp 0x0 /* 2clk */
807+#define Trc 0x3 /* 7clk */
808+#define Tchr 0x2 /* 3clk */
809+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
810+/**************************************/
811+
812+_TEXT_BASE:
813+ .word TEXT_BASE
814+
815+.globl lowlevel_init
816+lowlevel_init:
817+ /* memory control configuration */
818+ /* make r0 relative the current location so that it */
819+ /* reads SMRDATA out of FLASH rather than memory ! */
820+ ldr r0, =SMRDATA
821+ ldr r1, _TEXT_BASE
822+ sub r0, r0, r1
823+ ldr r1, =BWSCON /* Bus Width Status Controller */
824+ add r2, r0, #13*4
825+0:
826+ ldr r3, [r0], #4
827+ str r3, [r1], #4
828+ cmp r2, r0
829+ bne 0b
830+
831+ /* everything is fine now */
832+ mov pc, lr
833+
834+ .ltorg
835+/* the literal pools origin */
836+
837+SMRDATA:
838+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
839+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
840+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
841+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
842+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
843+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
844+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
845+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
846+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
847+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
848+ .word 0x32
849+ .word 0x30
850+ .word 0x30
851Index: u-boot/board/smdk2443/config.mk
852===================================================================
853--- /dev/null
854+++ u-boot/board/smdk2443/config.mk
855@@ -0,0 +1,29 @@
856+#
857+# (C) Copyright 2002
858+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
859+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
860+#
861+# SAMSUNG SMDK2443 board with S3C2443 (ARM920T) cpu
862+#
863+# see http://www.samsung.com/ for more information on SAMSUNG
864+#
865+
866+CONFIG_USB_DFU_VENDOR=0x1457
867+CONFIG_USB_DFU_PRODUCT=0x511c
868+CONFIG_USB_DFU_REVISION=0x0100
869+
870+#
871+# SMDK2443 has 1 bank of 64 MB DRAM
872+#
873+# 3000'0000 to 3400'0000
874+#
875+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
876+# optionally with a ramdisk at 3080'0000
877+#
878+# we load ourself to 33F8'0000
879+#
880+# download area is 3300'0000
881+#
882+
883+
884+TEXT_BASE = 0x33F80000
885Index: u-boot/board/smdk2443/lowlevel_foo.lds
886===================================================================
887--- /dev/null
888+++ u-boot/board/smdk2443/lowlevel_foo.lds
889@@ -0,0 +1,56 @@
890+/*
891+ * (C) Copyright 2002
892+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
893+ *
894+ * See file CREDITS for list of people who contributed to this
895+ * project.
896+ *
897+ * This program is free software; you can redistribute it and/or
898+ * modify it under the terms of the GNU General Public License as
899+ * published by the Free Software Foundation; either version 2 of
900+ * the License, or (at your option) any later version.
901+ *
902+ * This program is distributed in the hope that it will be useful,
903+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
904+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
905+ * GNU General Public License for more details.
906+ *
907+ * You should have received a copy of the GNU General Public License
908+ * along with this program; if not, write to the Free Software
909+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
910+ * MA 02111-1307 USA
911+ */
912+
913+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
914+OUTPUT_ARCH(arm)
915+ENTRY(_start)
916+SECTIONS
917+{
918+ . = 0x00000000;
919+
920+ . = ALIGN(4);
921+ .text :
922+ {
923+ lowlevel_foo.o (.text)
924+ *(.text)
925+ }
926+
927+ . = ALIGN(4);
928+ .rodata : { *(.rodata) }
929+
930+ . = ALIGN(4);
931+ .data : { *(.data) }
932+
933+ . = ALIGN(4);
934+ .got : { *(.got) }
935+
936+ . = .;
937+ __u_boot_cmd_start = .;
938+ .u_boot_cmd : { *(.u_boot_cmd) }
939+ __u_boot_cmd_end = .;
940+
941+ . = ALIGN(4);
942+ __bss_start = .;
943+ .bss : { *(.bss) }
944+ _end = .;
945+}
946Index: u-boot/board/smdk2443/flash.c
947===================================================================
948--- /dev/null
949+++ u-boot/board/smdk2443/flash.c
950@@ -0,0 +1,433 @@
951+/*
952+ * (C) Copyright 2002
953+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
954+ * Alex Zuepke <azu@sysgo.de>
955+ *
956+ * See file CREDITS for list of people who contributed to this
957+ * project.
958+ *
959+ * This program is free software; you can redistribute it and/or
960+ * modify it under the terms of the GNU General Public License as
961+ * published by the Free Software Foundation; either version 2 of
962+ * the License, or (at your option) any later version.
963+ *
964+ * This program is distributed in the hope that it will be useful,
965+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
966+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
967+ * GNU General Public License for more details.
968+ *
969+ * You should have received a copy of the GNU General Public License
970+ * along with this program; if not, write to the Free Software
971+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
972+ * MA 02111-1307 USA
973+ */
974+
975+#include <common.h>
976+
977+ulong myflush (void);
978+
979+
980+#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
981+#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
982+
983+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
984+
985+
986+#define CMD_READ_ARRAY 0x000000F0
987+#define CMD_UNLOCK1 0x000000AA
988+#define CMD_UNLOCK2 0x00000055
989+#define CMD_ERASE_SETUP 0x00000080
990+#define CMD_ERASE_CONFIRM 0x00000030
991+#define CMD_PROGRAM 0x000000A0
992+#define CMD_UNLOCK_BYPASS 0x00000020
993+
994+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
995+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
996+
997+#define BIT_ERASE_DONE 0x00000080
998+#define BIT_RDY_MASK 0x00000080
999+#define BIT_PROGRAM_ERROR 0x00000020
1000+#define BIT_TIMEOUT 0x80000000 /* our flag */
1001+
1002+#define READY 1
1003+#define ERR 2
1004+#define TMO 4
1005+
1006+/*-----------------------------------------------------------------------
1007+ */
1008+
1009+ulong flash_init (void)
1010+{
1011+ int i, j;
1012+ ulong size = 0;
1013+
1014+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
1015+ ulong flashbase = 0;
1016+
1017+ flash_info[i].flash_id =
1018+#if defined(CONFIG_AMD_LV400)
1019+ (AMD_MANUFACT & FLASH_VENDMASK) |
1020+ (AMD_ID_LV400B & FLASH_TYPEMASK);
1021+#elif defined(CONFIG_AMD_LV800)
1022+ (AMD_MANUFACT & FLASH_VENDMASK) |
1023+ (AMD_ID_LV800B & FLASH_TYPEMASK);
1024+#else
1025+#error "Unknown flash configured"
1026+#endif
1027+ flash_info[i].size = FLASH_BANK_SIZE;
1028+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
1029+ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
1030+ if (i == 0)
1031+ flashbase = PHYS_FLASH_1;
1032+ else
1033+ panic ("configured too many flash banks!\n");
1034+ for (j = 0; j < flash_info[i].sector_count; j++) {
1035+ if (j <= 3) {
1036+ /* 1st one is 16 KB */
1037+ if (j == 0) {
1038+ flash_info[i].start[j] =
1039+ flashbase + 0;
1040+ }
1041+
1042+ /* 2nd and 3rd are both 8 KB */
1043+ if ((j == 1) || (j == 2)) {
1044+ flash_info[i].start[j] =
1045+ flashbase + 0x4000 + (j -
1046+ 1) *
1047+ 0x2000;
1048+ }
1049+
1050+ /* 4th 32 KB */
1051+ if (j == 3) {
1052+ flash_info[i].start[j] =
1053+ flashbase + 0x8000;
1054+ }
1055+ } else {
1056+ flash_info[i].start[j] =
1057+ flashbase + (j - 3) * MAIN_SECT_SIZE;
1058+ }
1059+ }
1060+ size += flash_info[i].size;
1061+ }
1062+
1063+ flash_protect (FLAG_PROTECT_SET,
1064+ CFG_FLASH_BASE,
1065+ CFG_FLASH_BASE + monitor_flash_len - 1,
1066+ &flash_info[0]);
1067+
1068+ flash_protect (FLAG_PROTECT_SET,
1069+ CFG_ENV_ADDR,
1070+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
1071+
1072+ return size;
1073+}
1074+
1075+/*-----------------------------------------------------------------------
1076+ */
1077+void flash_print_info (flash_info_t * info)
1078+{
1079+ int i;
1080+
1081+ switch (info->flash_id & FLASH_VENDMASK) {
1082+ case (AMD_MANUFACT & FLASH_VENDMASK):
1083+ printf ("AMD: ");
1084+ break;
1085+ default:
1086+ printf ("Unknown Vendor ");
1087+ break;
1088+ }
1089+
1090+ switch (info->flash_id & FLASH_TYPEMASK) {
1091+ case (AMD_ID_LV400B & FLASH_TYPEMASK):
1092+ printf ("1x Amd29LV400BB (4Mbit)\n");
1093+ break;
1094+ case (AMD_ID_LV800B & FLASH_TYPEMASK):
1095+ printf ("1x Amd29LV800BB (8Mbit)\n");
1096+ break;
1097+ default:
1098+ printf ("Unknown Chip Type\n");
1099+ goto Done;
1100+ break;
1101+ }
1102+
1103+ printf (" Size: %ld MB in %d Sectors\n",
1104+ info->size >> 20, info->sector_count);
1105+
1106+ printf (" Sector Start Addresses:");
1107+ for (i = 0; i < info->sector_count; i++) {
1108+ if ((i % 5) == 0) {
1109+ printf ("\n ");
1110+ }
1111+ printf (" %08lX%s", info->start[i],
1112+ info->protect[i] ? " (RO)" : " ");
1113+ }
1114+ printf ("\n");
1115+
1116+ Done:;
1117+}
1118+
1119+/*-----------------------------------------------------------------------
1120+ */
1121+
1122+int flash_erase (flash_info_t * info, int s_first, int s_last)
1123+{
1124+ ushort result;
1125+ int iflag, cflag, prot, sect;
1126+ int rc = ERR_OK;
1127+ int chip;
1128+
1129+ /* first look for protection bits */
1130+
1131+ if (info->flash_id == FLASH_UNKNOWN)
1132+ return ERR_UNKNOWN_FLASH_TYPE;
1133+
1134+ if ((s_first < 0) || (s_first > s_last)) {
1135+ return ERR_INVAL;
1136+ }
1137+
1138+ if ((info->flash_id & FLASH_VENDMASK) !=
1139+ (AMD_MANUFACT & FLASH_VENDMASK)) {
1140+ return ERR_UNKNOWN_FLASH_VENDOR;
1141+ }
1142+
1143+ prot = 0;
1144+ for (sect = s_first; sect <= s_last; ++sect) {
1145+ if (info->protect[sect]) {
1146+ prot++;
1147+ }
1148+ }
1149+ if (prot)
1150+ return ERR_PROTECTED;
1151+
1152+ /*
1153+ * Disable interrupts which might cause a timeout
1154+ * here. Remember that our exception vectors are
1155+ * at address 0 in the flash, and we don't want a
1156+ * (ticker) exception to happen while the flash
1157+ * chip is in programming mode.
1158+ */
1159+ cflag = icache_status ();
1160+ icache_disable ();
1161+ iflag = disable_interrupts ();
1162+
1163+ /* Start erase on unprotected sectors */
1164+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
1165+ printf ("Erasing sector %2d ... ", sect);
1166+
1167+ /* arm simple, non interrupt dependent timer */
1168+ reset_timer_masked ();
1169+
1170+ if (info->protect[sect] == 0) { /* not protected */
1171+ vu_short *addr = (vu_short *) (info->start[sect]);
1172+
1173+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
1174+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
1175+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
1176+
1177+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
1178+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
1179+ *addr = CMD_ERASE_CONFIRM;
1180+
1181+ /* wait until flash is ready */
1182+ chip = 0;
1183+
1184+ do {
1185+ result = *addr;
1186+
1187+ /* check timeout */
1188+ if (get_timer_masked () >
1189+ CFG_FLASH_ERASE_TOUT) {
1190+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
1191+ chip = TMO;
1192+ break;
1193+ }
1194+
1195+ if (!chip
1196+ && (result & 0xFFFF) & BIT_ERASE_DONE)
1197+ chip = READY;
1198+
1199+ if (!chip
1200+ && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
1201+ chip = ERR;
1202+
1203+ } while (!chip);
1204+
1205+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
1206+
1207+ if (chip == ERR) {
1208+ rc = ERR_PROG_ERROR;
1209+ goto outahere;
1210+ }
1211+ if (chip == TMO) {
1212+ rc = ERR_TIMOUT;
1213+ goto outahere;
1214+ }
1215+
1216+ printf ("ok.\n");
1217+ } else { /* it was protected */
1218+
1219+ printf ("protected!\n");
1220+ }
1221+ }
1222+
1223+ if (ctrlc ())
1224+ printf ("User Interrupt!\n");
1225+
1226+ outahere:
1227+ /* allow flash to settle - wait 10 ms */
1228+ udelay_masked (10000);
1229+
1230+ if (iflag)
1231+ enable_interrupts ();
1232+
1233+ if (cflag)
1234+ icache_enable ();
1235+
1236+ return rc;
1237+}
1238+
1239+/*-----------------------------------------------------------------------
1240+ * Copy memory to flash
1241+ */
1242+
1243+volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
1244+{
1245+ vu_short *addr = (vu_short *) dest;
1246+ ushort result;
1247+ int rc = ERR_OK;
1248+ int cflag, iflag;
1249+ int chip;
1250+
1251+ /*
1252+ * Check if Flash is (sufficiently) erased
1253+ */
1254+ result = *addr;
1255+ if ((result & data) != data)
1256+ return ERR_NOT_ERASED;
1257+
1258+
1259+ /*
1260+ * Disable interrupts which might cause a timeout
1261+ * here. Remember that our exception vectors are
1262+ * at address 0 in the flash, and we don't want a
1263+ * (ticker) exception to happen while the flash
1264+ * chip is in programming mode.
1265+ */
1266+ cflag = icache_status ();
1267+ icache_disable ();
1268+ iflag = disable_interrupts ();
1269+
1270+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
1271+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
1272+ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
1273+ *addr = CMD_PROGRAM;
1274+ *addr = data;
1275+
1276+ /* arm simple, non interrupt dependent timer */
1277+ reset_timer_masked ();
1278+
1279+ /* wait until flash is ready */
1280+ chip = 0;
1281+ do {
1282+ result = *addr;
1283+
1284+ /* check timeout */
1285+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
1286+ chip = ERR | TMO;
1287+ break;
1288+ }
1289+ if (!chip && ((result & 0x80) == (data & 0x80)))
1290+ chip = READY;
1291+
1292+ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
1293+ result = *addr;
1294+
1295+ if ((result & 0x80) == (data & 0x80))
1296+ chip = READY;
1297+ else
1298+ chip = ERR;
1299+ }
1300+
1301+ } while (!chip);
1302+
1303+ *addr = CMD_READ_ARRAY;
1304+
1305+ if (chip == ERR || *addr != data)
1306+ rc = ERR_PROG_ERROR;
1307+
1308+ if (iflag)
1309+ enable_interrupts ();
1310+
1311+ if (cflag)
1312+ icache_enable ();
1313+
1314+ return rc;
1315+}
1316+
1317+/*-----------------------------------------------------------------------
1318+ * Copy memory to flash.
1319+ */
1320+
1321+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
1322+{
1323+ ulong cp, wp;
1324+ int l;
1325+ int i, rc;
1326+ ushort data;
1327+
1328+ wp = (addr & ~1); /* get lower word aligned address */
1329+
1330+ /*
1331+ * handle unaligned start bytes
1332+ */
1333+ if ((l = addr - wp) != 0) {
1334+ data = 0;
1335+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
1336+ data = (data >> 8) | (*(uchar *) cp << 8);
1337+ }
1338+ for (; i < 2 && cnt > 0; ++i) {
1339+ data = (data >> 8) | (*src++ << 8);
1340+ --cnt;
1341+ ++cp;
1342+ }
1343+ for (; cnt == 0 && i < 2; ++i, ++cp) {
1344+ data = (data >> 8) | (*(uchar *) cp << 8);
1345+ }
1346+
1347+ if ((rc = write_hword (info, wp, data)) != 0) {
1348+ return (rc);
1349+ }
1350+ wp += 2;
1351+ }
1352+
1353+ /*
1354+ * handle word aligned part
1355+ */
1356+ while (cnt >= 2) {
1357+ data = *((vu_short *) src);
1358+ if ((rc = write_hword (info, wp, data)) != 0) {
1359+ return (rc);
1360+ }
1361+ src += 2;
1362+ wp += 2;
1363+ cnt -= 2;
1364+ }
1365+
1366+ if (cnt == 0) {
1367+ return ERR_OK;
1368+ }
1369+
1370+ /*
1371+ * handle unaligned tail bytes
1372+ */
1373+ data = 0;
1374+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
1375+ data = (data >> 8) | (*src++ << 8);
1376+ --cnt;
1377+ }
1378+ for (; i < 2; ++i, ++cp) {
1379+ data = (data >> 8) | (*(uchar *) cp << 8);
1380+ }
1381+
1382+ return write_hword (info, wp, data);
1383+}
1384Index: u-boot/board/smdk2443/udc.c
1385===================================================================
1386--- /dev/null
1387+++ u-boot/board/smdk2443/udc.c
1388@@ -0,0 +1,23 @@
1389+
1390+#include <common.h>
1391+#include <usbdcore.h>
1392+#include <s3c2440.h>
1393+
1394+void udc_ctrl(enum usbd_event event, int param)
1395+{
1396+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1397+
1398+ switch (event) {
1399+ case UDC_CTRL_PULLUP_ENABLE:
1400+ if (param)
1401+ gpio->GPGDAT |= (1 << 12);
1402+ else
1403+ gpio->GPGDAT &= ~(1 << 12);
1404+ break;
1405+ case UDC_CTRL_500mA_ENABLE:
1406+ /* IGNORE */
1407+ break;
1408+ default:
1409+ break;
1410+ }
1411+}
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-17 03:43:09 +0000