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author | Richard Purdie <richard@openedhand.com> | 2007-12-04 13:58:45 +0000 |
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committer | Richard Purdie <richard@openedhand.com> | 2007-12-04 13:58:45 +0000 |
commit | d0b4968cd24a0152e88396d40310cdbae9555a1f (patch) | |
tree | 0ec4da2bbbbfcc7300780589135c01a3430ff774 /meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch | |
parent | 1fbde4b0c426c59695eb19e3785718dddf62632c (diff) | |
download | poky-d0b4968cd24a0152e88396d40310cdbae9555a1f.tar.gz |
qemu: Make 20071121 the default version and cleanup various file locations and recipes
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@3305 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch')
-rw-r--r-- | meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch b/meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch new file mode 100644 index 0000000000..d579dbc66e --- /dev/null +++ b/meta/packages/qemu/qemu-0.9.0+cvs20070613/41_arm_fpa_sigfpe.patch | |||
@@ -0,0 +1,105 @@ | |||
1 | #DPATCHLEVEL=0 | ||
2 | --- | ||
3 | # linux-user/main.c | 53 +++++++++++++++++++++++++++++++++++++++++++++-- | ||
4 | # target-arm/nwfpe/fpa11.c | 7 ++++++ | ||
5 | # 2 files changed, 58 insertions(+), 2 deletions(-) | ||
6 | # | ||
7 | Index: linux-user/main.c | ||
8 | =================================================================== | ||
9 | --- linux-user/main.c.orig 2007-06-13 11:51:53.000000000 +0100 | ||
10 | +++ linux-user/main.c 2007-06-13 11:52:07.000000000 +0100 | ||
11 | @@ -339,18 +339,67 @@ void cpu_loop(CPUARMState *env) | ||
12 | { | ||
13 | TaskState *ts = env->opaque; | ||
14 | uint32_t opcode; | ||
15 | + int rc; | ||
16 | |||
17 | /* we handle the FPU emulation here, as Linux */ | ||
18 | /* we get the opcode */ | ||
19 | opcode = tget32(env->regs[15]); | ||
20 | |||
21 | - if (EmulateAll(opcode, &ts->fpa, env) == 0) { | ||
22 | + rc = EmulateAll(opcode, &ts->fpa, env); | ||
23 | + if (rc == 0) { /* illegal instruction */ | ||
24 | info.si_signo = SIGILL; | ||
25 | info.si_errno = 0; | ||
26 | info.si_code = TARGET_ILL_ILLOPN; | ||
27 | info._sifields._sigfault._addr = env->regs[15]; | ||
28 | queue_signal(info.si_signo, &info); | ||
29 | - } else { | ||
30 | + } else if (rc < 0) { /* FP exception */ | ||
31 | + int arm_fpe=0; | ||
32 | + | ||
33 | + /* translate softfloat flags to FPSR flags */ | ||
34 | + if (-rc & float_flag_invalid) | ||
35 | + arm_fpe |= BIT_IOC; | ||
36 | + if (-rc & float_flag_divbyzero) | ||
37 | + arm_fpe |= BIT_DZC; | ||
38 | + if (-rc & float_flag_overflow) | ||
39 | + arm_fpe |= BIT_OFC; | ||
40 | + if (-rc & float_flag_underflow) | ||
41 | + arm_fpe |= BIT_UFC; | ||
42 | + if (-rc & float_flag_inexact) | ||
43 | + arm_fpe |= BIT_IXC; | ||
44 | + | ||
45 | + FPSR fpsr = ts->fpa.fpsr; | ||
46 | + //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); | ||
47 | + | ||
48 | + if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ | ||
49 | + info.si_signo = SIGFPE; | ||
50 | + info.si_errno = 0; | ||
51 | + | ||
52 | + /* ordered by priority, least first */ | ||
53 | + if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; | ||
54 | + if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; | ||
55 | + if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; | ||
56 | + if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; | ||
57 | + if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; | ||
58 | + | ||
59 | + info._sifields._sigfault._addr = env->regs[15]; | ||
60 | + queue_signal(info.si_signo, &info); | ||
61 | + } else { | ||
62 | + env->regs[15] += 4; | ||
63 | + } | ||
64 | + | ||
65 | + /* accumulate unenabled exceptions */ | ||
66 | + if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) | ||
67 | + fpsr |= BIT_IXC; | ||
68 | + if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) | ||
69 | + fpsr |= BIT_UFC; | ||
70 | + if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) | ||
71 | + fpsr |= BIT_OFC; | ||
72 | + if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) | ||
73 | + fpsr |= BIT_DZC; | ||
74 | + if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) | ||
75 | + fpsr |= BIT_IOC; | ||
76 | + ts->fpa.fpsr=fpsr; | ||
77 | + } else { /* everything OK */ | ||
78 | /* increment PC */ | ||
79 | env->regs[15] += 4; | ||
80 | } | ||
81 | Index: target-arm/nwfpe/fpa11.c | ||
82 | =================================================================== | ||
83 | --- target-arm/nwfpe/fpa11.c.orig 2007-06-13 11:51:52.000000000 +0100 | ||
84 | +++ target-arm/nwfpe/fpa11.c 2007-06-13 11:51:55.000000000 +0100 | ||
85 | @@ -162,6 +162,8 @@ unsigned int EmulateAll(unsigned int opc | ||
86 | fpa11->initflag = 1; | ||
87 | } | ||
88 | |||
89 | + set_float_exception_flags(0, &fpa11->fp_status); | ||
90 | + | ||
91 | if (TEST_OPCODE(opcode,MASK_CPRT)) | ||
92 | { | ||
93 | //fprintf(stderr,"emulating CPRT\n"); | ||
94 | @@ -191,6 +193,11 @@ unsigned int EmulateAll(unsigned int opc | ||
95 | } | ||
96 | |||
97 | // restore_flags(flags); | ||
98 | + if(nRc == 1 && get_float_exception_flags(&fpa11->fp_status)) | ||
99 | + { | ||
100 | + //printf("fef 0x%x\n",float_exception_flags); | ||
101 | + nRc=-get_float_exception_flags(&fpa11->fp_status); | ||
102 | + } | ||
103 | |||
104 | //printf("returning %d\n",nRc); | ||
105 | return(nRc); | ||