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authorRichard Purdie <richard@openedhand.com>2008-08-03 11:21:36 +0000
committerRichard Purdie <richard@openedhand.com>2008-08-03 11:21:36 +0000
commit5e4da782189840fb87bf4ff2ff689a7278cd75c1 (patch)
treef707818d7bb3e96031876c651411feb12fa632f9 /meta/packages/linux
parent6dda6e3c3e1413e08364fdca7496435a894abe5f (diff)
downloadpoky-5e4da782189840fb87bf4ff2ff689a7278cd75c1.tar.gz
linux-omap2-git: Sync with OE.dev, add fixes to compile correctly with gcc 4.3.1
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@5009 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/linux')
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff23
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff22
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff27
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff28
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff45
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff31
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff21
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch134
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/400khz-i2c.diff22
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/4bitmmc.diff38
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-01.patch43
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-02.patch71
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-03.patch82
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-04.patch38
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch303
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-06.patch179
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-07.patch274
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-08.patch278
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-09.patch341
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch238
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/defconfig53
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff118
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks1.diff25
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks2.diff62
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks3.diff94
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/serialfix.diff18
-rw-r--r--meta/packages/linux/linux-omap2-git/beagleboard/soc.patch233
-rw-r--r--meta/packages/linux/linux-omap2-git/fixes.patch25
-rw-r--r--meta/packages/linux/linux-omap2_git.bb33
29 files changed, 2747 insertions, 152 deletions
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff b/meta/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff
new file mode 100644
index 0000000000..89fbe3a836
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff
@@ -0,0 +1,23 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Sat, 5 Jul 2008 20:31:56 +0000 (+0100)
3Subject: omapfb: fix video timings message
4X-Git-Tag: beagle-5~3
5X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2929b75035ebe8702ba2ff2c81b654c487701f64
6
7omapfb: fix video timings message
8---
9
10diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
11index 418ed9f..1166a01 100644
12--- a/drivers/video/omap/omapfb_main.c
13+++ b/drivers/video/omap/omapfb_main.c
14@@ -1789,7 +1789,8 @@ static int omapfb_do_probe(struct platform_device *pdev,
15 vram, fbdev->mem_desc.region_cnt);
16 pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz "
17 "vfreq %lu.%lu Hz\n",
18- phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10);
19+ phz / 1000, hhz / 10000, hhz % 10000,
20+ vhz / 10, vhz % 10);
21
22 return 0;
23
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff b/meta/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff
new file mode 100644
index 0000000000..c437f145d3
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff
@@ -0,0 +1,22 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Sat, 5 Jul 2008 20:32:38 +0000 (+0100)
3Subject: omap: set CLKSEL_DSS1 to 2
4X-Git-Tag: beagle-5~2
5X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=d23f9c3c5c6243b626f7ec4c255469de2536e488
6
7omap: set CLKSEL_DSS1 to 2
8---
9
10diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
11index 8fdf8f3..04dedec 100644
12--- a/arch/arm/mach-omap2/clock34xx.c
13+++ b/arch/arm/mach-omap2/clock34xx.c
14@@ -596,6 +596,8 @@ int __init omap2_clk_init(void)
15 /* u32 clkrate; */
16 u32 cpu_clkflg;
17
18+ __raw_writel(0x1002, io_p2v(0x48004e40));
19+
20 /* REVISIT: Ultimately this will be used for multiboot */
21 #if 0
22 if (cpu_is_omap242x()) {
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff b/meta/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff
new file mode 100644
index 0000000000..9fa749f5fc
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff
@@ -0,0 +1,27 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Sun, 6 Jul 2008 13:15:36 +0000 (+0100)
3Subject: omapfb: enable overlay optimisation when possible
4X-Git-Tag: beagle-5~1
5X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=a63ac3abdf6781f863112321260fe7a5da757802
6
7omapfb: enable overlay optimisation when possible
8---
9
10diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
11index 6aff476..3b36227 100644
12--- a/drivers/video/omap/dispc.c
13+++ b/drivers/video/omap/dispc.c
14@@ -582,11 +582,13 @@ static int omap_dispc_enable_plane(int plane, int enable)
15 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
16 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
17 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
18+ unsigned overlay_opt = plane & !!enable & !dispc.color_key.key_type;
19 if ((unsigned int)plane > dispc.mem_desc.region_cnt)
20 return -EINVAL;
21
22 enable_lcd_clocks(1);
23 MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
24+ MOD_REG_FLD(DISPC_CONTROL, 1<<12 | 1<<5, overlay_opt<<12 | 1<<5);
25 enable_lcd_clocks(0);
26
27 return 0;
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff b/meta/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff
new file mode 100644
index 0000000000..bdf8ab5f0b
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff
@@ -0,0 +1,28 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Sun, 6 Jul 2008 13:22:54 +0000 (+0100)
3Subject: omapfb: use PCD if set in panel config
4X-Git-Tag: beagle-5
5X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=c8060d36ae156771f00a7a27cabf1b4435c378bd
6
7omapfb: use PCD if set in panel config
8---
9
10diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
11index 3b36227..4e1a8e3 100644
12--- a/drivers/video/omap/dispc.c
13+++ b/drivers/video/omap/dispc.c
14@@ -798,7 +798,13 @@ static void set_lcd_timings(void)
15 l |= panel->acb & 0xff;
16 dispc_write_reg(DISPC_POL_FREQ, l);
17
18- calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
19+ if (panel->pcd) {
20+ pck_div = panel->pcd;
21+ lck_div = 1;
22+ } else {
23+ calc_ck_div(is_tft, panel->pixel_clock * 1000,
24+ &lck_div, &pck_div);
25+ }
26
27 l = dispc_read_reg(DISPC_DIVISOR);
28 l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff b/meta/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff
new file mode 100644
index 0000000000..d3c9fffcda
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff
@@ -0,0 +1,45 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Mon, 7 Jul 2008 00:13:00 +0000 (+0100)
3Subject: omapfb: fix display panning
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=9fec252c96b0e69bcef0afd9cb9dd72b7179c239
5
6omapfb: fix display panning
7---
8
9diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
10index 4e1a8e3..c17371c 100644
11--- a/drivers/video/omap/dispc.c
12+++ b/drivers/video/omap/dispc.c
13@@ -435,6 +435,8 @@ static inline int _setup_plane(int plane, int channel_out,
14
15 dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
16
17+ MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5);
18+
19 return height * screen_width * bpp / 8;
20 }
21
22diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
23index 1166a01..3e4959e 100644
24--- a/drivers/video/omap/omapfb_main.c
25+++ b/drivers/video/omap/omapfb_main.c
26@@ -206,8 +206,8 @@ static int ctrl_change_mode(struct fb_info *fbi)
27 struct omapfb_device *fbdev = plane->fbdev;
28 struct fb_var_screeninfo *var = &fbi->var;
29
30- offset = var->yoffset * fbi->fix.line_length +
31- var->xoffset * var->bits_per_pixel / 8;
32+ offset = (var->yoffset * var->xres_virtual + var->xoffset) *
33+ var->bits_per_pixel / 8;
34
35 if (fbdev->ctrl->sync)
36 fbdev->ctrl->sync();
37@@ -423,6 +423,8 @@ static void set_fb_fix(struct fb_info *fbi)
38 }
39 fix->accel = FB_ACCEL_OMAP1610;
40 fix->line_length = var->xres_virtual * bpp / 8;
41+ fix->xpanstep = 1;
42+ fix->ypanstep = 1;
43 }
44
45 static int set_color_mode(struct omapfb_plane_struct *plane,
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff b/meta/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff
new file mode 100644
index 0000000000..79871a7208
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff
@@ -0,0 +1,31 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Mon, 7 Jul 2008 23:59:08 +0000 (+0100)
3Subject: omapfb: ensure fck/lcd < 173MHz
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=0523ece1bad659c48c66aea364d83f7490e7e5ae
5
6omapfb: ensure fck/lcd < 173MHz
7---
8
9diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
10index c17371c..85d6cad 100644
11--- a/drivers/video/omap/dispc.c
12+++ b/drivers/video/omap/dispc.c
13@@ -738,14 +738,16 @@ static void setup_color_conv_coef(void)
14 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
15 }
16
17+#define MAX_FCK_LCD 173000000
18+
19 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
20 {
21 unsigned long fck, lck;
22
23- *lck_div = 1;
24 pck = max(1, pck);
25 fck = clk_get_rate(dispc.dss1_fck);
26- lck = fck;
27+ *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD;
28+ lck = fck / *lck_div;
29 *pck_div = (lck + pck - 1) / pck;
30 if (is_tft)
31 *pck_div = max(2, *pck_div);
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff b/meta/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff
new file mode 100644
index 0000000000..99bd80eae0
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff
@@ -0,0 +1,21 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Tue, 8 Jul 2008 18:26:43 +0000 (+0100)
3Subject: omapfb: set graphics burst size to 16x32
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=4f9e415dfcd5613a8de973f6c9878cab959c5869
5
6omapfb: set graphics burst size to 16x32
7---
8
9diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
10index 85d6cad..fd06ca2 100644
11--- a/drivers/video/omap/dispc.c
12+++ b/drivers/video/omap/dispc.c
13@@ -409,7 +409,7 @@ static inline int _setup_plane(int plane, int channel_out,
14 l |= cconv_en << 9;
15
16 l &= ~(0x03 << burst_shift);
17- l |= DISPC_BURST_8x32 << burst_shift;
18+ l |= DISPC_BURST_16x32 << burst_shift;
19
20 l &= ~(1 << chout_shift);
21 l |= chout_val << chout_shift;
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch b/meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch
index f1e2181c82..d2bff4b018 100644
--- a/meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/16bpp.patch
@@ -1,13 +1,137 @@
1diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
2index bdeb8fb..bf256f3 100644
3--- a/drivers/video/omap/Kconfig
4+++ b/drivers/video/omap/Kconfig
5@@ -7,6 +7,27 @@ config FB_OMAP
6 help
7 Frame buffer driver for OMAP based boards.
8
9+choice
10+ depends on FB_OMAP && MACH_OMAP3_BEAGLE
11+ prompt "Screen resolution"
12+ default FB_OMAP_079M3R
13+ help
14+ Selected desired screen resolution
15+
16+config FB_OMAP_031M3R
17+ boolean "640 x 480 @ 60 Hz Reduced blanking"
18+
19+config FB_OMAP_048M3R
20+ boolean "800 x 600 @ 60 Hz Reduced blanking"
21+
22+config FB_OMAP_079M3R
23+ boolean "1024 x 768 @ 60 Hz Reduced blanking"
24+
25+config FB_OMAP_092M9R
26+ boolean "1280 x 720 @ 60 Hz Reduced blanking"
27+
28+endchoice
29+
30 config FB_OMAP_LCDC_EXTERNAL
31 bool "External LCD controller support"
32 depends on FB_OMAP
1diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c 33diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
2index 69d4e06..c1c4f4c 100644 34index 69d4e06..5e098c2 100644
3--- a/drivers/video/omap/lcd_omap3beagle.c 35--- a/drivers/video/omap/lcd_omap3beagle.c
4+++ b/drivers/video/omap/lcd_omap3beagle.c 36+++ b/drivers/video/omap/lcd_omap3beagle.c
5@@ -66,7 +66,7 @@ struct lcd_panel omap3beagle_panel = { 37@@ -31,10 +31,6 @@
38
39 #define LCD_PANEL_ENABLE_GPIO 170
40
41-#define LCD_XRES 1024
42-#define LCD_YRES 768
43-#define LCD_PIXCLOCK 64000 /* in kHz */
44-
45 static int omap3beagle_panel_init(struct lcd_panel *panel,
46 struct omapfb_device *fbdev)
47 {
48@@ -65,19 +61,76 @@ static unsigned long omap3beagle_panel_get_caps(struct lcd_panel *panel)
49 struct lcd_panel omap3beagle_panel = {
6 .name = "omap3beagle", 50 .name = "omap3beagle",
7 .config = OMAP_LCDC_PANEL_TFT, 51 .config = OMAP_LCDC_PANEL_TFT,
8 52-
9- .bpp = 24, 53- .bpp = 24,
10+ .bpp = 16, 54+ .bpp = 16,
11 .data_lines = 24, 55 .data_lines = 24,
12 .x_res = LCD_XRES, 56- .x_res = LCD_XRES,
13 .y_res = LCD_YRES, 57- .y_res = LCD_YRES,
58- .hsw = 3, /* hsync_len (4) - 1 */
59- .hfp = 3, /* right_margin (4) - 1 */
60- .hbp = 39, /* left_margin (40) - 1 */
61- .vsw = 1, /* vsync_len (2) - 1 */
62- .vfp = 2, /* lower_margin */
63- .vbp = 7, /* upper_margin (8) - 1 */
64-
65- .pixel_clock = LCD_PIXCLOCK,
66+
67+#if defined CONFIG_FB_OMAP_031M3R
68+
69+ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
70+ .x_res = 640,
71+ .y_res = 480,
72+ .hfp = 48,
73+ .hsw = 32,
74+ .hbp = 80,
75+ .vfp = 3,
76+ .vsw = 4,
77+ .vbp = 7,
78+ .pixel_clock = 23500,
79+
80+#elif defined CONFIG_FB_OMAP_048M3R
81+
82+ /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */
83+ .x_res = 800,
84+ .y_res = 600,
85+ .hfp = 48,
86+ .hsw = 32,
87+ .hbp = 80,
88+ .vfp = 3,
89+ .vsw = 4,
90+ .vbp = 11,
91+ .pixel_clock = 35500,
92+
93+#elif defined CONFIG_FB_OMAP_079M3R
94+
95+ /* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */
96+ .x_res = 1024,
97+ .y_res = 768,
98+ .hfp = 48,
99+ .hsw = 32,
100+ .hbp = 80,
101+ .vfp = 3,
102+ .vsw = 4,
103+ .vbp = 15,
104+ .pixel_clock = 56000,
105+
106+#elif defined CONFIG_FB_OMAP_092M9R
107+
108+ /* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */
109+ .x_res = 1280,
110+ .y_res = 720,
111+ .hfp = 48,
112+ .hsw = 32,
113+ .hbp = 80,
114+ .vfp = 3,
115+ .vsw = 5,
116+ .vbp = 13,
117+ .pixel_clock = 64000,
118+
119+#else
120+
121+ /* use 640 x 480 if no config option */
122+ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
123+ .x_res = 640,
124+ .y_res = 480,
125+ .hfp = 48,
126+ .hsw = 32,
127+ .hbp = 80,
128+ .vfp = 3,
129+ .vsw = 4,
130+ .vbp = 7,
131+ .pixel_clock = 23500,
132+
133+#endif
134
135 .init = omap3beagle_panel_init,
136 .cleanup = omap3beagle_panel_cleanup,
137
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/400khz-i2c.diff b/meta/packages/linux/linux-omap2-git/beagleboard/400khz-i2c.diff
new file mode 100644
index 0000000000..f749dbcf5b
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/400khz-i2c.diff
@@ -0,0 +1,22 @@
1From: Steve Sakoman <steve@sakoman.com>
2Date: Wed, 16 Jul 2008 19:38:43 +0000 (-0700)
3Subject: omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be
4X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=12d6504334a830774ff1d42cee4b7296ac9fb7d2
5
6omap3beagle: set data rate on i2c-1 to 400, since 2600 seems to be
7flakey
8---
9
10diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
11index fdce787..938ad73 100644
12--- a/arch/arm/mach-omap2/board-omap3beagle.c
13+++ b/arch/arm/mach-omap2/board-omap3beagle.c
14@@ -39,7 +39,7 @@ static struct omap_uart_config omap3_beagle_uart_config __initdata = {
15
16 static int __init omap3_beagle_i2c_init(void)
17 {
18- omap_register_i2c_bus(1, 2600, NULL, 0);
19+ omap_register_i2c_bus(1, 400, NULL, 0);
20 omap_register_i2c_bus(2, 400, NULL, 0);
21 omap_register_i2c_bus(3, 400, NULL, 0);
22 return 0;
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/4bitmmc.diff b/meta/packages/linux/linux-omap2-git/beagleboard/4bitmmc.diff
new file mode 100644
index 0000000000..5cd120c544
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/4bitmmc.diff
@@ -0,0 +1,38 @@
1From: Purushotam Kumar <purushotam@ti.com>
2Date: Fri, 18 Jul 2008 23:28:57 +0000 (-0700)
3Subject: OMAP3:devices.c:Enabling 4-bit for SD card
4X-Git-Url: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=linux-omap-2.6.git;a=commitdiff_plain;h=6c4d34031c80ca4b50ffe73a4ef7fe197a760a60
5
6OMAP3:devices.c:Enabling 4-bit for SD card
7
8SD card was working in 1-bit mode.This patch will configure SD card in
94-bit mode and hence performance will increase.
10
11Signed-off-by: Purushotam Kumar <purushotam@ti.com>
12Acked-by: Madhusudhan Chikkature Rajashekar <madhu.cr@ti.com>
13---
14
15diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
16index b83f9a6..d0cfceb 100644
17--- a/arch/arm/plat-omap/devices.c
18+++ b/arch/arm/plat-omap/devices.c
19@@ -296,13 +296,17 @@ static void __init omap_init_mmc(void)
20 mmc = &mmc_conf->mmc[0];
21
22 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
23- if (mmc->enabled)
24+ if (mmc->enabled) {
25+ mmc1_data.conf = *mmc;
26 (void) platform_device_register(&mmc_omap_device1);
27+ }
28
29 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
30 mmc = &mmc_conf->mmc[1];
31- if (mmc->enabled)
32+ if (mmc->enabled) {
33+ mmc2_data.conf = *mmc;
34 (void) platform_device_register(&mmc_omap_device2);
35+ }
36 #endif
37
38 return;
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-01.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-01.patch
new file mode 100644
index 0000000000..c361c33d61
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-01.patch
@@ -0,0 +1,43 @@
1TWL4030: remove superfluous PWR interrupt status clear before masking
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_irq_init() clears PWR interrupt status bits, then masks the interrupts
6off, then clears the PWR interrupt status bits again. The first clear
7seems unnecessary, so, remove it.
8
9Signed-off-by: Paul Walmsley <paul@pwsan.com>
10---
11
12 drivers/i2c/chips/twl4030-core.c | 18 ------------------
13 1 files changed, 0 insertions(+), 18 deletions(-)
14
15diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
16index adc45d4..ff662bc 100644
17--- a/drivers/i2c/chips/twl4030-core.c
18+++ b/drivers/i2c/chips/twl4030-core.c
19@@ -719,24 +719,6 @@ static void twl_init_irq(void)
20 char *msg = "Unable to register interrupt subsystem";
21 unsigned int irq_num;
22
23- /*
24- * We end up with interrupts from other modules before
25- * they get a chance to handle them...
26- */
27- /* PWR_ISR1 */
28- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00);
29- if (res < 0) {
30- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
31- return;
32- }
33-
34- /* PWR_ISR2 */
35- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02);
36- if (res < 0) {
37- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
38- return;
39- }
40-
41 /* PWR_IMR1 */
42 res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1);
43 if (res < 0) {
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-02.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-02.patch
new file mode 100644
index 0000000000..48a59b945b
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-02.patch
@@ -0,0 +1,71 @@
1TWL4030: clear TWL GPIO interrupt status registers
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() does not clear the TWL GPIO ISR registers, but the PIH
6ISR thinks that it has. This causes any previously-latched GPIO interrupts
7to be stuck on until twl4030-gpio.c initializes, often drowning the console in
8
9 TWL4030 module irq 368 is disabled but can't be masked!
10
11messages. This seems to be a particular problem when booting on Beagle.
12
13Signed-off-by: Paul Walmsley <paul@pwsan.com>
14---
15
16 drivers/i2c/chips/twl4030-core.c | 42 ++++++++++++++++++++++++++++++++++++++
17 1 files changed, 42 insertions(+), 0 deletions(-)
18
19diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
20index ff662bc..dfc3805 100644
21--- a/drivers/i2c/chips/twl4030-core.c
22+++ b/drivers/i2c/chips/twl4030-core.c
23@@ -857,6 +857,48 @@ static void twl_init_irq(void)
24 return;
25 }
26
27+ /* GPIO_ISR1A */
28+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19);
29+ if (res < 0) {
30+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
31+ return;
32+ }
33+
34+ /* GPIO_ISR2A */
35+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a);
36+ if (res < 0) {
37+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
38+ return;
39+ }
40+
41+ /* GPIO_ISR3A */
42+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b);
43+ if (res < 0) {
44+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
45+ return;
46+ }
47+
48+ /* GPIO_ISR1B */
49+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f);
50+ if (res < 0) {
51+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
52+ return;
53+ }
54+
55+ /* GPIO_ISR2B */
56+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20);
57+ if (res < 0) {
58+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
59+ return;
60+ }
61+
62+ /* GPIO_ISR3B */
63+ res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21);
64+ if (res < 0) {
65+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
66+ return;
67+ }
68+
69 /* install an irq handler for each of the PIH modules */
70 for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
71 set_irq_chip(i, &twl4030_irq_chip);
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-03.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-03.patch
new file mode 100644
index 0000000000..fe1bea5398
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-03.patch
@@ -0,0 +1,82 @@
1TWL4030: use correct register addresses for BCI IMR registers
2
3From: Paul Walmsley <paul@pwsan.com>
4
5The existing code to mask and clear BCI interrupts in twl_init_irq() is
6wrong. It uses the wrong register offsets, it does not mask all of the
7BCI IMR registers, and it does not clear all of the BCI ISR registers.
8
9Signed-off-by: Paul Walmsley <paul@pwsan.com>
10---
11
12 drivers/i2c/chips/twl4030-core.c | 40 ++++++++++++++++++++++++++++++++------
13 1 files changed, 34 insertions(+), 6 deletions(-)
14
15diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
16index dfc3805..bb0732c 100644
17--- a/drivers/i2c/chips/twl4030-core.c
18+++ b/drivers/i2c/chips/twl4030-core.c
19@@ -750,29 +750,57 @@ static void twl_init_irq(void)
20 /* POWER HACK (END) */
21 /* Slave address 0x4A */
22
23- /* BCIIMR1_1 */
24+ /* BCIIMR1A */
25+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x2);
26+ if (res < 0) {
27+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
28+ return;
29+ }
30+
31+ /* BCIIMR2A */
32 res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x3);
33 if (res < 0) {
34 pr_err("%s[%d][%d]\n", msg, res, __LINE__);
35 return;
36 }
37
38- /* BCIIMR1_2 */
39- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4);
40+ /* BCIIMR1B */
41+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x6);
42 if (res < 0) {
43 pr_err("%s[%d][%d]\n", msg, res, __LINE__);
44 return;
45 }
46
47- /* BCIIMR2_1 */
48+ /* BCIIMR2B */
49 res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x7);
50 if (res < 0) {
51 pr_err("%s[%d][%d]\n", msg, res, __LINE__);
52 return;
53 }
54
55- /* BCIIMR2_2 */
56- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x8);
57+ /* BCIISR1A */
58+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0);
59+ if (res < 0) {
60+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
61+ return;
62+ }
63+
64+ /* BCIISR2A */
65+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1);
66+ if (res < 0) {
67+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
68+ return;
69+ }
70+
71+ /* BCIISR1B */
72+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4);
73+ if (res < 0) {
74+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
75+ return;
76+ }
77+
78+ /* BCIISR2B */
79+ res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5);
80 if (res < 0) {
81 pr_err("%s[%d][%d]\n", msg, res, __LINE__);
82 return;
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-04.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-04.patch
new file mode 100644
index 0000000000..fb65ac98bb
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-04.patch
@@ -0,0 +1,38 @@
1TWL4030: clear MADC interrupt status registers upon init
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() does not clear MADC interrupt status registers upon init -
6fix.
7
8Signed-off-by: Paul Walmsley <paul@pwsan.com>
9---
10
11 drivers/i2c/chips/twl4030-core.c | 14 ++++++++++++++
12 1 files changed, 14 insertions(+), 0 deletions(-)
13
14diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
15index bb0732c..9d93524 100644
16--- a/drivers/i2c/chips/twl4030-core.c
17+++ b/drivers/i2c/chips/twl4030-core.c
18@@ -821,6 +821,20 @@ static void twl_init_irq(void)
19 return;
20 }
21
22+ /* MADC_ISR1 */
23+ res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61);
24+ if (res < 0) {
25+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
26+ return;
27+ }
28+
29+ /* MADC_ISR2 */
30+ res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63);
31+ if (res < 0) {
32+ pr_err("%s[%d][%d]\n", msg, res, __LINE__);
33+ return;
34+ }
35+
36 /* key Pad */
37 /* KEYPAD - IMR1 */
38 res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x12));
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch
new file mode 100644
index 0000000000..02a72ed9df
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-05.patch
@@ -0,0 +1,303 @@
1TWL4030: use *_SIH_CTRL.COR bit to determine whether to read or write ISR to clear
2
3From: Paul Walmsley <paul@pwsan.com>
4
5TWL4030 interrupt status register bits can be cleared in one of two ways:
6either by reading from the register, or by writing a 1 to the
7appropriate bit(s) in the register. This behavior can be altered at any
8time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read").
9
10The TWL4030 TRM is deeply confused as to whether COR=1 means that the
11registers are cleared on reads, or cleared on writes. Peter De
12Schrijver <peter.de-schrijver> confirms that COR=1 means that the registers
13are cleared on read.
14
15So, for each TWL4030 SIH, check the value of the *_SIH_CTRL.COR bit, and if
16it is 1, use reads to clear the ISRs; if it is 0, use writes.
17
18Also, use WARN_ON() to warn if the read/write failed, and don't skip
19the rest of the initialization on failure either.
20
21Thanks to Peter for his help with this patch.
22
23
24Signed-off-by: Paul Walmsley <paul@pwsan.com>
25---
26
27 drivers/i2c/chips/twl4030-core.c | 183 ++++++++++++++++++++++----------------
28 1 files changed, 106 insertions(+), 77 deletions(-)
29
30diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
31index 9d93524..eae0634 100644
32--- a/drivers/i2c/chips/twl4030-core.c
33+++ b/drivers/i2c/chips/twl4030-core.c
34@@ -133,6 +133,16 @@
35 /* on I2C-1 for 2430SDP */
36 #define CONFIG_I2C_TWL4030_ID 1
37
38+/* SIH_CTRL registers */
39+#define TWL4030_INT_PWR_SIH_CTRL 0x07
40+#define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
41+#define TWL4030_MADC_MADC_SIH_CTRL 0x67
42+#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
43+#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
44+
45+#define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
46+
47+
48 /* Helper functions */
49 static int
50 twl4030_detect_client(struct i2c_adapter *adapter, unsigned char sid);
51@@ -712,13 +722,61 @@ static int power_companion_init(void)
52 return e;
53 }
54
55+/**
56+ * twl4030_i2c_clear_isr - clear TWL4030 SIH ISR regs via read + write
57+ * @mod_no: TWL4030 module number
58+ * @reg: register index to clear
59+ * @cor: value of the <module>_SIH_CTRL.COR bit (1 or 0)
60+ *
61+ * Either reads (cor == 1) or writes (cor == 0) to a TWL4030 interrupt
62+ * status register to ensure that any prior interrupts are cleared.
63+ * Returns the status from the I2C read operation.
64+ */
65+static int twl4030_i2c_clear_isr(u8 mod_no, u8 reg, u8 cor)
66+{
67+ u8 tmp;
68+
69+ return (cor) ? twl4030_i2c_read_u8(mod_no, &tmp, reg) :
70+ twl4030_i2c_write_u8(mod_no, 0xff, reg);
71+}
72+
73+/**
74+ * twl4030_read_cor_bit - are TWL module ISRs cleared by reads or writes?
75+ * @mod_no: TWL4030 module number
76+ * @reg: register index to clear
77+ *
78+ * Returns 1 if the TWL4030 SIH interrupt status registers (ISRs) for
79+ * the specified TWL module are cleared by reads, or 0 if cleared by
80+ * writes.
81+ */
82+static int twl4030_read_cor_bit(u8 mod_no, u8 reg)
83+{
84+ u8 tmp = 0;
85+
86+ WARN_ON(twl4030_i2c_read_u8(mod_no, &tmp, reg) < 0);
87+
88+ tmp &= TWL4030_SIH_CTRL_COR_MASK;
89+ tmp >>= __ffs(TWL4030_SIH_CTRL_COR_MASK);
90+
91+ return tmp;
92+}
93+
94 static void twl_init_irq(void)
95 {
96 int i = 0;
97 int res = 0;
98+ int cor;
99 char *msg = "Unable to register interrupt subsystem";
100 unsigned int irq_num;
101
102+ /*
103+ * For each TWL4030 module with ISR/IMR registers, mask all
104+ * interrupts and then clear any existing interrupt status bits,
105+ * since we initially do not have any TWL4030 module interrupt
106+ * handlers present.
107+ */
108+
109+
110 /* PWR_IMR1 */
111 res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1);
112 if (res < 0) {
113@@ -734,20 +792,18 @@ static void twl_init_irq(void)
114 }
115
116 /* Clear off any other pending interrupts on power */
117+
118+ /* Are PWR interrupt status bits cleared by reads or writes? */
119+ cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
120+ TWL4030_INT_PWR_SIH_CTRL);
121+ WARN_ON(cor < 0);
122+
123 /* PWR_ISR1 */
124- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x00);
125- if (res < 0) {
126- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
127- return;
128- }
129+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
130
131 /* PWR_ISR2 */
132- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x02);
133- if (res < 0) {
134- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
135- return;
136- }
137- /* POWER HACK (END) */
138+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
139+
140 /* Slave address 0x4A */
141
142 /* BCIIMR1A */
143@@ -778,33 +834,22 @@ static void twl_init_irq(void)
144 return;
145 }
146
147+ /* Are BCI interrupt status bits cleared by reads or writes? */
148+ cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
149+ TWL4030_INTERRUPTS_BCISIHCTRL);
150+ WARN_ON(cor < 0);
151+
152 /* BCIISR1A */
153- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x0);
154- if (res < 0) {
155- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
156- return;
157- }
158+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
159
160 /* BCIISR2A */
161- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x1);
162- if (res < 0) {
163- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
164- return;
165- }
166+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
167
168 /* BCIISR1B */
169- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x4);
170- if (res < 0) {
171- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
172- return;
173- }
174+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
175
176 /* BCIISR2B */
177- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x5);
178- if (res < 0) {
179- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
180- return;
181- }
182+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
183
184 /* MAD C */
185 /* MADC_IMR1 */
186@@ -821,19 +866,16 @@ static void twl_init_irq(void)
187 return;
188 }
189
190+ /* Are MADC interrupt status bits cleared by reads or writes? */
191+ cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
192+ TWL4030_MADC_MADC_SIH_CTRL);
193+ WARN_ON(cor < 0);
194+
195 /* MADC_ISR1 */
196- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x61);
197- if (res < 0) {
198- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
199- return;
200- }
201+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
202
203 /* MADC_ISR2 */
204- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x63);
205- if (res < 0) {
206- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
207- return;
208- }
209+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
210
211 /* key Pad */
212 /* KEYPAD - IMR1 */
213@@ -842,12 +884,15 @@ static void twl_init_irq(void)
214 pr_err("%s[%d][%d]\n", msg, res, __LINE__);
215 return;
216 }
217- {
218- u8 clear;
219- /* Clear ISR */
220- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11);
221- twl4030_i2c_read_u8(TWL4030_MODULE_KEYPAD, &clear, 0x11);
222- }
223+
224+ /* Are keypad interrupt status bits cleared by reads or writes? */
225+ cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
226+ TWL4030_KEYPAD_KEYP_SIH_CTRL);
227+ WARN_ON(cor < 0);
228+
229+ /* KEYPAD - ISR1 */
230+ /* XXX does this still need to be done twice for some reason? */
231+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
232
233 /* KEYPAD - IMR2 */
234 res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14));
235@@ -856,6 +901,9 @@ static void twl_init_irq(void)
236 return;
237 }
238
239+ /* KEYPAD - ISR2 */
240+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
241+
242 /* Slave address 0x49 */
243 /* GPIO_IMR1A */
244 res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C));
245@@ -899,47 +947,28 @@ static void twl_init_irq(void)
246 return;
247 }
248
249+ /* Are GPIO interrupt status bits cleared by reads or writes? */
250+ cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
251+ TWL4030_GPIO_GPIO_SIH_CTRL);
252+ WARN_ON(cor < 0);
253+
254 /* GPIO_ISR1A */
255- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x19);
256- if (res < 0) {
257- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
258- return;
259- }
260+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
261
262 /* GPIO_ISR2A */
263- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1a);
264- if (res < 0) {
265- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
266- return;
267- }
268+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
269
270 /* GPIO_ISR3A */
271- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1b);
272- if (res < 0) {
273- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
274- return;
275- }
276+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
277
278 /* GPIO_ISR1B */
279- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1f);
280- if (res < 0) {
281- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
282- return;
283- }
284+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
285
286 /* GPIO_ISR2B */
287- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x20);
288- if (res < 0) {
289- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
290- return;
291- }
292+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
293
294 /* GPIO_ISR3B */
295- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x21);
296- if (res < 0) {
297- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
298- return;
299- }
300+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
301
302 /* install an irq handler for each of the PIH modules */
303 for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-06.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-06.patch
new file mode 100644
index 0000000000..67b837c454
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-06.patch
@@ -0,0 +1,179 @@
1TWL4030: change init-time IMR mask code to WARN if error
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() prints error messages and returns if any interrupt mask
6register writes fail. Change this to generate a warning traceback and
7to continue execution rather than skipping TWL init. (These mask
8writes should not fail at all unless either the I2C bus or the TWL4030
9is somehow wedged.)
10
11Signed-off-by: Paul Walmsley <paul@pwsan.com>
12---
13
14 drivers/i2c/chips/twl4030-core.c | 100 +++++++-------------------------------
15 1 files changed, 18 insertions(+), 82 deletions(-)
16
17diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
18index eae0634..99cc143 100644
19--- a/drivers/i2c/chips/twl4030-core.c
20+++ b/drivers/i2c/chips/twl4030-core.c
21@@ -778,18 +778,10 @@ static void twl_init_irq(void)
22
23
24 /* PWR_IMR1 */
25- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x1);
26- if (res < 0) {
27- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
28- return;
29- }
30+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0);
31
32 /* PWR_IMR2 */
33- res = twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xFF, 0x3);
34- if (res < 0) {
35- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
36- return;
37- }
38+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0);
39
40 /* Clear off any other pending interrupts on power */
41
42@@ -807,32 +799,16 @@ static void twl_init_irq(void)
43 /* Slave address 0x4A */
44
45 /* BCIIMR1A */
46- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x2);
47- if (res < 0) {
48- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
49- return;
50- }
51+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0);
52
53- /* BCIIMR2A */
54- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x3);
55- if (res < 0) {
56- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
57- return;
58- }
59+ /* BCIIMR2A */
60+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0);
61
62- /* BCIIMR1B */
63- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x6);
64- if (res < 0) {
65- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
66- return;
67- }
68+ /* BCIIMR2A */
69+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0);
70
71 /* BCIIMR2B */
72- res = twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xFF, 0x7);
73- if (res < 0) {
74- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
75- return;
76- }
77+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0);
78
79 /* Are BCI interrupt status bits cleared by reads or writes? */
80 cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
81@@ -853,18 +829,10 @@ static void twl_init_irq(void)
82
83 /* MAD C */
84 /* MADC_IMR1 */
85- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x62);
86- if (res < 0) {
87- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
88- return;
89- }
90+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0);
91
92 /* MADC_IMR2 */
93- res = twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xFF, 0x64);
94- if (res < 0) {
95- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
96- return;
97- }
98+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0);
99
100 /* Are MADC interrupt status bits cleared by reads or writes? */
101 cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
102@@ -879,11 +847,7 @@ static void twl_init_irq(void)
103
104 /* key Pad */
105 /* KEYPAD - IMR1 */
106- res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x12));
107- if (res < 0) {
108- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
109- return;
110- }
111+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0);
112
113 /* Are keypad interrupt status bits cleared by reads or writes? */
114 cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
115@@ -895,57 +859,29 @@ static void twl_init_irq(void)
116 WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
117
118 /* KEYPAD - IMR2 */
119- res = twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xFF, (0x14));
120- if (res < 0) {
121- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
122- return;
123- }
124+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0);
125
126 /* KEYPAD - ISR2 */
127 WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
128
129 /* Slave address 0x49 */
130 /* GPIO_IMR1A */
131- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1C));
132- if (res < 0) {
133- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
134- return;
135- }
136+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0);
137
138 /* GPIO_IMR2A */
139- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1D));
140- if (res < 0) {
141- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
142- return;
143- }
144+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0);
145
146 /* GPIO_IMR3A */
147- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x1E));
148- if (res < 0) {
149- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
150- return;
151- }
152+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0);
153
154 /* GPIO_IMR1B */
155- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x22));
156- if (res < 0) {
157- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
158- return;
159- }
160+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0);
161
162 /* GPIO_IMR2B */
163- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x23));
164- if (res < 0) {
165- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
166- return;
167- }
168+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0);
169
170 /* GPIO_IMR3B */
171- res = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xFF, (0x24));
172- if (res < 0) {
173- pr_err("%s[%d][%d]\n", msg, res, __LINE__);
174- return;
175- }
176+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0);
177
178 /* Are GPIO interrupt status bits cleared by reads or writes? */
179 cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-07.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-07.patch
new file mode 100644
index 0000000000..8e4c4d6be4
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-07.patch
@@ -0,0 +1,274 @@
1TWL4030: move TWL module register defs into separate include files
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() uses "magic numbers" to access TWL module IMR and ISR
6registers. Symbolic constants are definitely preferred.
7
8Rather than duplicating already existing symbolic constants in
9twl4030-gpio.c and twl4030-pwrirq.c, move the existing constants out
10into include files. This patch should not change kernel behavior.
11
12Signed-off-by: Paul Walmsley <paul@pwsan.com>
13---
14
15 drivers/i2c/chips/twl4030-gpio.c | 48 -----------------------
16 drivers/i2c/chips/twl4030-pwrirq.c | 15 +++----
17 include/linux/i2c/twl4030-gpio.h | 76 ++++++++++++++++++++++++++++++++++++
18 include/linux/i2c/twl4030-pwrirq.h | 37 ++++++++++++++++++
19 4 files changed, 121 insertions(+), 55 deletions(-)
20 create mode 100644 include/linux/i2c/twl4030-gpio.h
21 create mode 100644 include/linux/i2c/twl4030-pwrirq.h
22
23diff --git a/drivers/i2c/chips/twl4030-gpio.c b/drivers/i2c/chips/twl4030-gpio.c
24index f16a48b..9d17f45 100644
25--- a/drivers/i2c/chips/twl4030-gpio.c
26+++ b/drivers/i2c/chips/twl4030-gpio.c
27@@ -38,6 +38,7 @@
28
29 #include <linux/i2c.h>
30 #include <linux/i2c/twl4030.h>
31+#include <linux/i2c/twl4030-gpio.h>
32 #include <linux/slab.h>
33
34 #include <asm/arch/irqs.h>
35@@ -47,53 +48,6 @@
36
37 #include <linux/device.h>
38
39-/*
40- * GPIO Block Register definitions
41- */
42-
43-#define REG_GPIODATAIN1 0x0
44-#define REG_GPIODATAIN2 0x1
45-#define REG_GPIODATAIN3 0x2
46-#define REG_GPIODATADIR1 0x3
47-#define REG_GPIODATADIR2 0x4
48-#define REG_GPIODATADIR3 0x5
49-#define REG_GPIODATAOUT1 0x6
50-#define REG_GPIODATAOUT2 0x7
51-#define REG_GPIODATAOUT3 0x8
52-#define REG_CLEARGPIODATAOUT1 0x9
53-#define REG_CLEARGPIODATAOUT2 0xA
54-#define REG_CLEARGPIODATAOUT3 0xB
55-#define REG_SETGPIODATAOUT1 0xC
56-#define REG_SETGPIODATAOUT2 0xD
57-#define REG_SETGPIODATAOUT3 0xE
58-#define REG_GPIO_DEBEN1 0xF
59-#define REG_GPIO_DEBEN2 0x10
60-#define REG_GPIO_DEBEN3 0x11
61-#define REG_GPIO_CTRL 0x12
62-#define REG_GPIOPUPDCTR1 0x13
63-#define REG_GPIOPUPDCTR2 0x14
64-#define REG_GPIOPUPDCTR3 0x15
65-#define REG_GPIOPUPDCTR4 0x16
66-#define REG_GPIOPUPDCTR5 0x17
67-#define REG_GPIO_ISR1A 0x19
68-#define REG_GPIO_ISR2A 0x1A
69-#define REG_GPIO_ISR3A 0x1B
70-#define REG_GPIO_IMR1A 0x1C
71-#define REG_GPIO_IMR2A 0x1D
72-#define REG_GPIO_IMR3A 0x1E
73-#define REG_GPIO_ISR1B 0x1F
74-#define REG_GPIO_ISR2B 0x20
75-#define REG_GPIO_ISR3B 0x21
76-#define REG_GPIO_IMR1B 0x22
77-#define REG_GPIO_IMR2B 0x23
78-#define REG_GPIO_IMR3B 0x24
79-#define REG_GPIO_EDR1 0x28
80-#define REG_GPIO_EDR2 0x29
81-#define REG_GPIO_EDR3 0x2A
82-#define REG_GPIO_EDR4 0x2B
83-#define REG_GPIO_EDR5 0x2C
84-#define REG_GPIO_SIH_CTRL 0x2D
85-
86 /* BitField Definitions */
87
88 /* Data banks : 3 banks for 8 gpios each */
89diff --git a/drivers/i2c/chips/twl4030-pwrirq.c b/drivers/i2c/chips/twl4030-pwrirq.c
90index a4d2e92..1afdb65 100644
91--- a/drivers/i2c/chips/twl4030-pwrirq.c
92+++ b/drivers/i2c/chips/twl4030-pwrirq.c
93@@ -27,10 +27,8 @@
94 #include <linux/random.h>
95 #include <linux/kthread.h>
96 #include <linux/i2c/twl4030.h>
97+#include <linux/i2c/twl4030-pwrirq.h>
98
99-#define PWR_ISR1 0
100-#define PWR_IMR1 1
101-#define PWR_SIH_CTRL 7
102 #define PWR_SIH_CTRL_COR (1<<2)
103
104 static u8 twl4030_pwrirq_mask;
105@@ -93,7 +91,8 @@ static void do_twl4030_pwrmodule_irq(unsigned int irq, irq_desc_t *desc)
106 twl4030_pwrirq_mask |= 1 << (irq - TWL4030_PWR_IRQ_BASE);
107 local_irq_enable();
108 twl4030_i2c_write_u8(TWL4030_MODULE_INT,
109- twl4030_pwrirq_mask, PWR_IMR1);
110+ twl4030_pwrirq_mask,
111+ TWL4030_INT_PWR_IMR1);
112 }
113 }
114 }
115@@ -115,7 +114,7 @@ static void do_twl4030_pwrirq(unsigned int irq, irq_desc_t *desc)
116
117 local_irq_enable();
118 ret = twl4030_i2c_read_u8(TWL4030_MODULE_INT, &pwr_isr,
119- PWR_ISR1);
120+ TWL4030_INT_PWR_ISR1);
121 if (ret) {
122 printk(KERN_WARNING
123 "I2C error %d while reading TWL4030"
124@@ -151,7 +150,7 @@ static int twl4030_pwrirq_thread(void *data)
125 twl4030_pwrirq_mask &= ~local_unmask;
126
127 twl4030_i2c_write_u8(TWL4030_MODULE_INT, twl4030_pwrirq_mask,
128- PWR_IMR1);
129+ TWL4030_INT_PWR_IMR1);
130
131 local_irq_disable();
132 if (!twl4030_pwrirq_pending_unmask)
133@@ -172,14 +171,14 @@ static int __init twl4030_pwrirq_init(void)
134 twl4030_pwrirq_pending_unmask = 0;
135
136 err = twl4030_i2c_write_u8(TWL4030_MODULE_INT, twl4030_pwrirq_mask,
137- PWR_IMR1);
138+ TWL4030_INT_PWR_IMR1);
139 if (err)
140 return err;
141
142 /* Enable clear on read */
143
144 err = twl4030_i2c_write_u8(TWL4030_MODULE_INT, PWR_SIH_CTRL_COR,
145- PWR_SIH_CTRL);
146+ TWL4030_INT_PWR_SIH_CTRL);
147 if (err)
148 return err;
149
150diff --git a/include/linux/i2c/twl4030-gpio.h b/include/linux/i2c/twl4030-gpio.h
151new file mode 100644
152index 0000000..7cbf610
153--- /dev/null
154+++ b/include/linux/i2c/twl4030-gpio.h
155@@ -0,0 +1,76 @@
156+/*
157+ * twl4030-gpio.h - header for TWL4030 GPIO module
158+ *
159+ * Copyright (C) 2005-2006, 2008 Texas Instruments, Inc.
160+ * Copyright (C) 2008 Nokia Corporation
161+ *
162+ * Based on tlv320aic23.c:
163+ * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
164+ *
165+ * This program is free software; you can redistribute it and/or modify
166+ * it under the terms of the GNU General Public License as published by
167+ * the Free Software Foundation; either version 2 of the License, or
168+ * (at your option) any later version.
169+ *
170+ * This program is distributed in the hope that it will be useful,
171+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
172+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
173+ * GNU General Public License for more details.
174+ *
175+ * You should have received a copy of the GNU General Public License
176+ * along with this program; if not, write to the Free Software
177+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
178+ *
179+ */
180+
181+#ifndef __TWL4030_GPIO_H_
182+#define __TWL4030_GPIO_H_
183+
184+/*
185+ * GPIO Block Register definitions
186+ */
187+
188+#define REG_GPIODATAIN1 0x0
189+#define REG_GPIODATAIN2 0x1
190+#define REG_GPIODATAIN3 0x2
191+#define REG_GPIODATADIR1 0x3
192+#define REG_GPIODATADIR2 0x4
193+#define REG_GPIODATADIR3 0x5
194+#define REG_GPIODATAOUT1 0x6
195+#define REG_GPIODATAOUT2 0x7
196+#define REG_GPIODATAOUT3 0x8
197+#define REG_CLEARGPIODATAOUT1 0x9
198+#define REG_CLEARGPIODATAOUT2 0xA
199+#define REG_CLEARGPIODATAOUT3 0xB
200+#define REG_SETGPIODATAOUT1 0xC
201+#define REG_SETGPIODATAOUT2 0xD
202+#define REG_SETGPIODATAOUT3 0xE
203+#define REG_GPIO_DEBEN1 0xF
204+#define REG_GPIO_DEBEN2 0x10
205+#define REG_GPIO_DEBEN3 0x11
206+#define REG_GPIO_CTRL 0x12
207+#define REG_GPIOPUPDCTR1 0x13
208+#define REG_GPIOPUPDCTR2 0x14
209+#define REG_GPIOPUPDCTR3 0x15
210+#define REG_GPIOPUPDCTR4 0x16
211+#define REG_GPIOPUPDCTR5 0x17
212+#define REG_GPIO_ISR1A 0x19
213+#define REG_GPIO_ISR2A 0x1A
214+#define REG_GPIO_ISR3A 0x1B
215+#define REG_GPIO_IMR1A 0x1C
216+#define REG_GPIO_IMR2A 0x1D
217+#define REG_GPIO_IMR3A 0x1E
218+#define REG_GPIO_ISR1B 0x1F
219+#define REG_GPIO_ISR2B 0x20
220+#define REG_GPIO_ISR3B 0x21
221+#define REG_GPIO_IMR1B 0x22
222+#define REG_GPIO_IMR2B 0x23
223+#define REG_GPIO_IMR3B 0x24
224+#define REG_GPIO_EDR1 0x28
225+#define REG_GPIO_EDR2 0x29
226+#define REG_GPIO_EDR3 0x2A
227+#define REG_GPIO_EDR4 0x2B
228+#define REG_GPIO_EDR5 0x2C
229+#define REG_GPIO_SIH_CTRL 0x2D
230+
231+#endif /* End of __TWL4030_GPIO_H */
232diff --git a/include/linux/i2c/twl4030-pwrirq.h b/include/linux/i2c/twl4030-pwrirq.h
233new file mode 100644
234index 0000000..7a13368
235--- /dev/null
236+++ b/include/linux/i2c/twl4030-pwrirq.h
237@@ -0,0 +1,37 @@
238+/*
239+ * twl4030-gpio.h - header for TWL4030 GPIO module
240+ *
241+ * Copyright (C) 2008 Texas Instruments, Inc.
242+ * Copyright (C) 2008 Nokia Corporation
243+ *
244+ * This program is free software; you can redistribute it and/or modify
245+ * it under the terms of the GNU General Public License as published by
246+ * the Free Software Foundation; either version 2 of the License, or
247+ * (at your option) any later version.
248+ *
249+ * This program is distributed in the hope that it will be useful,
250+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
251+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
252+ * GNU General Public License for more details.
253+ *
254+ * You should have received a copy of the GNU General Public License
255+ * along with this program; if not, write to the Free Software
256+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
257+ *
258+ */
259+
260+#ifndef __TWL4030_PWRIRQ_H_
261+#define __TWL4030_PWRIRQ_H_
262+
263+/*
264+ * INT Module Register definitions
265+ * (not all registers are defined below)
266+ */
267+
268+#define TWL4030_INT_PWR_ISR1 0x0
269+#define TWL4030_INT_PWR_IMR1 0x1
270+#define TWL4030_INT_PWR_ISR2 0x2
271+#define TWL4030_INT_PWR_IMR2 0x3
272+#define TWL4030_INT_PWR_SIH_CTRL 0x7
273+
274+#endif /* End of __TWL4030_PWRIRQ_H */
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-08.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-08.patch
new file mode 100644
index 0000000000..9af25a762d
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-08.patch
@@ -0,0 +1,278 @@
1TWL4030: use symbolic ISR/IMR register names during twl_init_irq()
2
3From: Paul Walmsley <paul@pwsan.com>
4
5twl_init_irq() uses a bunch of magic numbers as register indices; this
6has already led to several errors, fixed earlier in this patch series.
7Now use descriptive macros instead of magic numbers. This patch should
8not change kernel behavior.
9
10Signed-off-by: Paul Walmsley <paul@pwsan.com>
11---
12
13 drivers/i2c/chips/twl4030-core.c | 188 +++++++++++++++++++-------------------
14 1 files changed, 96 insertions(+), 92 deletions(-)
15
16diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
17index 99cc143..38c227a 100644
18--- a/drivers/i2c/chips/twl4030-core.c
19+++ b/drivers/i2c/chips/twl4030-core.c
20@@ -40,6 +40,9 @@
21
22 #include <linux/i2c.h>
23 #include <linux/i2c/twl4030.h>
24+#include <linux/i2c/twl4030-gpio.h>
25+#include <linux/i2c/twl4030-madc.h>
26+#include <linux/i2c/twl4030-pwrirq.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/device.h>
30@@ -114,6 +117,23 @@
31 #define TWL4030_BASEADD_RTC 0x001C
32 #define TWL4030_BASEADD_SECURED_REG 0x0000
33
34+/* TWL4030 BCI registers */
35+#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
36+#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
37+#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
38+#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
39+#define TWL4030_INTERRUPTS_BCIISR1A 0x0
40+#define TWL4030_INTERRUPTS_BCIISR2A 0x1
41+#define TWL4030_INTERRUPTS_BCIISR1B 0x4
42+#define TWL4030_INTERRUPTS_BCIISR2B 0x5
43+
44+/* TWL4030 keypad registers */
45+#define TWL4030_KEYPAD_KEYP_IMR1 0x12
46+#define TWL4030_KEYPAD_KEYP_IMR2 0x14
47+#define TWL4030_KEYPAD_KEYP_ISR1 0x11
48+#define TWL4030_KEYPAD_KEYP_ISR2 0x13
49+
50+
51 /* Triton Core internal information (END) */
52
53 /* Few power values */
54@@ -133,12 +153,10 @@
55 /* on I2C-1 for 2430SDP */
56 #define CONFIG_I2C_TWL4030_ID 1
57
58-/* SIH_CTRL registers */
59-#define TWL4030_INT_PWR_SIH_CTRL 0x07
60+/* SIH_CTRL registers that aren't defined elsewhere */
61 #define TWL4030_INTERRUPTS_BCISIHCTRL 0x0d
62 #define TWL4030_MADC_MADC_SIH_CTRL 0x67
63 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
64-#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2d
65
66 #define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
67
68@@ -776,135 +794,121 @@ static void twl_init_irq(void)
69 * handlers present.
70 */
71
72-
73- /* PWR_IMR1 */
74- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x1) < 0);
75-
76- /* PWR_IMR2 */
77- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff, 0x3) < 0);
78-
79- /* Clear off any other pending interrupts on power */
80+ /* Mask INT (PWR) interrupts at TWL4030 */
81+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
82+ TWL4030_INT_PWR_IMR1) < 0);
83+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
84+ TWL4030_INT_PWR_IMR2) < 0);
85
86 /* Are PWR interrupt status bits cleared by reads or writes? */
87 cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
88 TWL4030_INT_PWR_SIH_CTRL);
89 WARN_ON(cor < 0);
90
91- /* PWR_ISR1 */
92- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x00, cor) < 0);
93-
94- /* PWR_ISR2 */
95- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT, 0x02, cor) < 0);
96+ /* Clear TWL4030 INT (PWR) ISRs */
97+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
98+ TWL4030_INT_PWR_ISR1, cor) < 0);
99+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
100+ TWL4030_INT_PWR_ISR2, cor) < 0);
101
102 /* Slave address 0x4A */
103
104- /* BCIIMR1A */
105- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x2) < 0);
106-
107- /* BCIIMR2A */
108- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x3) < 0);
109-
110- /* BCIIMR2A */
111- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x6) < 0);
112-
113- /* BCIIMR2B */
114- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff, 0x7) < 0);
115+ /* Mask BCI interrupts at TWL4030 */
116+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
117+ TWL4030_INTERRUPTS_BCIIMR1A) < 0);
118+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
119+ TWL4030_INTERRUPTS_BCIIMR2A) < 0);
120+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
121+ TWL4030_INTERRUPTS_BCIIMR1B) < 0);
122+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
123+ TWL4030_INTERRUPTS_BCIIMR2B) < 0);
124
125 /* Are BCI interrupt status bits cleared by reads or writes? */
126 cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
127 TWL4030_INTERRUPTS_BCISIHCTRL);
128 WARN_ON(cor < 0);
129
130- /* BCIISR1A */
131- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x0, cor) < 0);
132-
133- /* BCIISR2A */
134- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x1, cor) < 0);
135-
136- /* BCIISR1B */
137- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x4, cor) < 0);
138-
139- /* BCIISR2B */
140- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS, 0x5, cor) < 0);
141+ /* Clear TWL4030 BCI ISRs */
142+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
143+ TWL4030_INTERRUPTS_BCIISR1A, cor) < 0);
144+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
145+ TWL4030_INTERRUPTS_BCIISR2A, cor) < 0);
146+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
147+ TWL4030_INTERRUPTS_BCIISR1B, cor) < 0);
148+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
149+ TWL4030_INTERRUPTS_BCIISR2B, cor) < 0);
150
151 /* MAD C */
152- /* MADC_IMR1 */
153- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x62) < 0);
154-
155- /* MADC_IMR2 */
156- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff, 0x64) < 0);
157+ /* Mask MADC interrupts at TWL4030 */
158+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
159+ TWL4030_MADC_IMR1) < 0);
160+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
161+ TWL4030_MADC_IMR2) < 0);
162
163 /* Are MADC interrupt status bits cleared by reads or writes? */
164 cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
165 TWL4030_MADC_MADC_SIH_CTRL);
166 WARN_ON(cor < 0);
167
168- /* MADC_ISR1 */
169- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x61, cor) < 0);
170-
171- /* MADC_ISR2 */
172- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC, 0x63, cor) < 0);
173+ /* Clear TWL4030 MADC ISRs */
174+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
175+ TWL4030_MADC_ISR1, cor) < 0);
176+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
177+ TWL4030_MADC_ISR2, cor) < 0);
178
179 /* key Pad */
180- /* KEYPAD - IMR1 */
181- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x12) < 0);
182+ /* Mask keypad interrupts at TWL4030 */
183+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
184+ TWL4030_KEYPAD_KEYP_IMR1) < 0);
185+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
186+ TWL4030_KEYPAD_KEYP_IMR2) < 0);
187
188 /* Are keypad interrupt status bits cleared by reads or writes? */
189 cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
190 TWL4030_KEYPAD_KEYP_SIH_CTRL);
191 WARN_ON(cor < 0);
192
193- /* KEYPAD - ISR1 */
194+ /* Clear TWL4030 keypad ISRs */
195 /* XXX does this still need to be done twice for some reason? */
196- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x11, cor) < 0);
197-
198- /* KEYPAD - IMR2 */
199- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff, 0x14) < 0);
200-
201- /* KEYPAD - ISR2 */
202- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD, 0x13, cor) < 0);
203+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
204+ TWL4030_KEYPAD_KEYP_ISR1, cor) < 0);
205+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
206+ TWL4030_KEYPAD_KEYP_ISR2, cor) < 0);
207
208 /* Slave address 0x49 */
209- /* GPIO_IMR1A */
210- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1c) < 0);
211-
212- /* GPIO_IMR2A */
213- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1d) < 0);
214-
215- /* GPIO_IMR3A */
216- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x1e) < 0);
217-
218- /* GPIO_IMR1B */
219- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x22) < 0);
220
221- /* GPIO_IMR2B */
222- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x23) < 0);
223-
224- /* GPIO_IMR3B */
225- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff, 0x24) < 0);
226+ /* Mask GPIO interrupts at TWL4030 */
227+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
228+ REG_GPIO_IMR1A) < 0);
229+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
230+ REG_GPIO_IMR2A) < 0);
231+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
232+ REG_GPIO_IMR3A) < 0);
233+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
234+ REG_GPIO_IMR1B) < 0);
235+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
236+ REG_GPIO_IMR2B) < 0);
237+ WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
238+ REG_GPIO_IMR3B) < 0);
239
240 /* Are GPIO interrupt status bits cleared by reads or writes? */
241 cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
242- TWL4030_GPIO_GPIO_SIH_CTRL);
243+ REG_GPIO_SIH_CTRL);
244 WARN_ON(cor < 0);
245
246- /* GPIO_ISR1A */
247- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x19, cor) < 0);
248-
249- /* GPIO_ISR2A */
250- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1a, cor) < 0);
251-
252- /* GPIO_ISR3A */
253- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1b, cor) < 0);
254-
255- /* GPIO_ISR1B */
256- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x1f, cor) < 0);
257-
258- /* GPIO_ISR2B */
259- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x20, cor) < 0);
260-
261- /* GPIO_ISR3B */
262- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, 0x21, cor) < 0);
263+ /* Clear TWL4030 GPIO ISRs */
264+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A,
265+ cor) < 0);
266+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A,
267+ cor) < 0);
268+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A,
269+ cor) < 0);
270+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B,
271+ cor) < 0);
272+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B,
273+ cor) < 0);
274+ WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B,
275+ cor) < 0);
276
277 /* install an irq handler for each of the PIH modules */
278 for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-09.patch b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-09.patch
new file mode 100644
index 0000000000..ab6cc6d87b
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/TWL4030-09.patch
@@ -0,0 +1,341 @@
1TWL4030: convert early interrupt mask/clear funcs to use array
2
3From: Paul Walmsley <paul@pwsan.com>
4
5Mask/clear TWL module IMRs/ISRs by iterating through arrays rather than
6using a block of cut-and-pasted commands. Removes 1056 bytes of bloat.
7
8Signed-off-by: Paul Walmsley <paul@pwsan.com>
9---
10
11 drivers/i2c/chips/twl4030-core.c | 302 +++++++++++++++++++++++---------------
12 1 files changed, 180 insertions(+), 122 deletions(-)
13
14diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
15index 38c227a..776b1dd 100644
16--- a/drivers/i2c/chips/twl4030-core.c
17+++ b/drivers/i2c/chips/twl4030-core.c
18@@ -160,6 +160,136 @@
19
20 #define TWL4030_SIH_CTRL_COR_MASK (1 << 2)
21
22+/**
23+ * struct twl4030_mod_iregs - TWL module IMR/ISR regs to mask/clear at init
24+ * @mod_no: TWL4030 module number (e.g., TWL4030_MODULE_GPIO)
25+ * @sih_ctrl: address of module SIH_CTRL register
26+ * @reg_cnt: number of IMR/ISR regs
27+ * @imrs: pointer to array of TWL module interrupt mask register indices
28+ * @isrs: pointer to array of TWL module interrupt status register indices
29+ *
30+ * Ties together TWL4030 modules and lists of IMR/ISR registers to mask/clear
31+ * during twl_init_irq().
32+ */
33+struct twl4030_mod_iregs {
34+ const u8 mod_no;
35+ const u8 sih_ctrl;
36+ const u8 reg_cnt;
37+ const u8 *imrs;
38+ const u8 *isrs;
39+};
40+
41+/* TWL4030 INT module interrupt mask registers */
42+static const u8 __initconst twl4030_int_imr_regs[] = {
43+ TWL4030_INT_PWR_IMR1,
44+ TWL4030_INT_PWR_IMR2,
45+};
46+
47+/* TWL4030 INT module interrupt status registers */
48+static const u8 __initconst twl4030_int_isr_regs[] = {
49+ TWL4030_INT_PWR_ISR1,
50+ TWL4030_INT_PWR_ISR2,
51+};
52+
53+/* TWL4030 INTERRUPTS module interrupt mask registers */
54+static const u8 __initconst twl4030_interrupts_imr_regs[] = {
55+ TWL4030_INTERRUPTS_BCIIMR1A,
56+ TWL4030_INTERRUPTS_BCIIMR1B,
57+ TWL4030_INTERRUPTS_BCIIMR2A,
58+ TWL4030_INTERRUPTS_BCIIMR2B,
59+};
60+
61+/* TWL4030 INTERRUPTS module interrupt status registers */
62+static const u8 __initconst twl4030_interrupts_isr_regs[] = {
63+ TWL4030_INTERRUPTS_BCIISR1A,
64+ TWL4030_INTERRUPTS_BCIISR1B,
65+ TWL4030_INTERRUPTS_BCIISR2A,
66+ TWL4030_INTERRUPTS_BCIISR2B,
67+};
68+
69+/* TWL4030 MADC module interrupt mask registers */
70+static const u8 __initconst twl4030_madc_imr_regs[] = {
71+ TWL4030_MADC_IMR1,
72+ TWL4030_MADC_IMR2,
73+};
74+
75+/* TWL4030 MADC module interrupt status registers */
76+static const u8 __initconst twl4030_madc_isr_regs[] = {
77+ TWL4030_MADC_ISR1,
78+ TWL4030_MADC_ISR2,
79+};
80+
81+/* TWL4030 keypad module interrupt mask registers */
82+static const u8 __initconst twl4030_keypad_imr_regs[] = {
83+ TWL4030_KEYPAD_KEYP_IMR1,
84+ TWL4030_KEYPAD_KEYP_IMR2,
85+};
86+
87+/* TWL4030 keypad module interrupt status registers */
88+static const u8 __initconst twl4030_keypad_isr_regs[] = {
89+ TWL4030_KEYPAD_KEYP_ISR1,
90+ TWL4030_KEYPAD_KEYP_ISR2,
91+};
92+
93+/* TWL4030 GPIO module interrupt mask registers */
94+static const u8 __initconst twl4030_gpio_imr_regs[] = {
95+ REG_GPIO_IMR1A,
96+ REG_GPIO_IMR1B,
97+ REG_GPIO_IMR2A,
98+ REG_GPIO_IMR2B,
99+ REG_GPIO_IMR3A,
100+ REG_GPIO_IMR3B,
101+};
102+
103+/* TWL4030 GPIO module interrupt status registers */
104+static const u8 __initconst twl4030_gpio_isr_regs[] = {
105+ REG_GPIO_ISR1A,
106+ REG_GPIO_ISR1B,
107+ REG_GPIO_ISR2A,
108+ REG_GPIO_ISR2B,
109+ REG_GPIO_ISR3A,
110+ REG_GPIO_ISR3B,
111+};
112+
113+/* TWL4030 modules that have IMR/ISR registers that must be masked/cleared */
114+static const struct twl4030_mod_iregs __initconst twl4030_mod_regs[] = {
115+ {
116+ .mod_no = TWL4030_MODULE_INT,
117+ .sih_ctrl = TWL4030_INT_PWR_SIH_CTRL,
118+ .reg_cnt = ARRAY_SIZE(twl4030_int_imr_regs),
119+ .imrs = twl4030_int_imr_regs,
120+ .isrs = twl4030_int_isr_regs,
121+ },
122+ {
123+ .mod_no = TWL4030_MODULE_INTERRUPTS,
124+ .sih_ctrl = TWL4030_INTERRUPTS_BCISIHCTRL,
125+ .reg_cnt = ARRAY_SIZE(twl4030_interrupts_imr_regs),
126+ .imrs = twl4030_interrupts_imr_regs,
127+ .isrs = twl4030_interrupts_isr_regs,
128+ },
129+ {
130+ .mod_no = TWL4030_MODULE_MADC,
131+ .sih_ctrl = TWL4030_MADC_MADC_SIH_CTRL,
132+ .reg_cnt = ARRAY_SIZE(twl4030_madc_imr_regs),
133+ .imrs = twl4030_madc_imr_regs,
134+ .isrs = twl4030_madc_isr_regs,
135+ },
136+ {
137+ .mod_no = TWL4030_MODULE_KEYPAD,
138+ .sih_ctrl = TWL4030_KEYPAD_KEYP_SIH_CTRL,
139+ .reg_cnt = ARRAY_SIZE(twl4030_keypad_imr_regs),
140+ .imrs = twl4030_keypad_imr_regs,
141+ .isrs = twl4030_keypad_isr_regs,
142+ },
143+ {
144+ .mod_no = TWL4030_MODULE_GPIO,
145+ .sih_ctrl = REG_GPIO_SIH_CTRL,
146+ .reg_cnt = ARRAY_SIZE(twl4030_gpio_imr_regs),
147+ .imrs = twl4030_gpio_imr_regs,
148+ .isrs = twl4030_gpio_isr_regs,
149+ },
150+};
151+
152
153 /* Helper functions */
154 static int
155@@ -779,136 +909,64 @@ static int twl4030_read_cor_bit(u8 mod_no, u8 reg)
156 return tmp;
157 }
158
159+/**
160+ * twl4030_mask_clear_intrs - mask and clear all TWL4030 interrupts
161+ * @t: pointer to twl4030_mod_iregs array
162+ * @t_sz: ARRAY_SIZE(t) (starting at 1)
163+ *
164+ * Mask all TWL4030 interrupt mask registers (IMRs) and clear all
165+ * interrupt status registers (ISRs). No return value, but will WARN if
166+ * any I2C operations fail.
167+ */
168+static void __init twl4030_mask_clear_intrs(const struct twl4030_mod_iregs *t,
169+ const u8 t_sz)
170+{
171+ int i, j;
172+
173+ /*
174+ * N.B. - further efficiency is possible here. Eight I2C
175+ * operations on BCI and GPIO modules are avoidable if I2C
176+ * burst read/write transactions were implemented. Would
177+ * probably save about 1ms of boot time and a small amount of
178+ * power.
179+ */
180+ for (i = 0; i < t_sz; i++) {
181+ const struct twl4030_mod_iregs tmr = t[i];
182+
183+ for (j = 0; j < tmr.reg_cnt; j++) {
184+ int cor;
185+
186+ /* Mask interrupts at the TWL4030 */
187+ WARN_ON(twl4030_i2c_write_u8(tmr.mod_no, 0xff,
188+ tmr.imrs[j]) < 0);
189+
190+ /* Are ISRs cleared by reads or writes? */
191+ cor = twl4030_read_cor_bit(tmr.mod_no, tmr.sih_ctrl);
192+ WARN_ON(cor < 0);
193+
194+ /* Clear TWL4030 ISRs */
195+ WARN_ON(twl4030_i2c_clear_isr(tmr.mod_no,
196+ tmr.isrs[j], cor) < 0);
197+ }
198+ }
199+
200+ return;
201+}
202+
203+
204 static void twl_init_irq(void)
205 {
206- int i = 0;
207+ int i;
208 int res = 0;
209- int cor;
210 char *msg = "Unable to register interrupt subsystem";
211 unsigned int irq_num;
212
213 /*
214- * For each TWL4030 module with ISR/IMR registers, mask all
215- * interrupts and then clear any existing interrupt status bits,
216- * since we initially do not have any TWL4030 module interrupt
217- * handlers present.
218+ * Mask and clear all TWL4030 interrupts since initially we do
219+ * not have any TWL4030 module interrupt handlers present
220 */
221-
222- /* Mask INT (PWR) interrupts at TWL4030 */
223- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
224- TWL4030_INT_PWR_IMR1) < 0);
225- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INT, 0xff,
226- TWL4030_INT_PWR_IMR2) < 0);
227-
228- /* Are PWR interrupt status bits cleared by reads or writes? */
229- cor = twl4030_read_cor_bit(TWL4030_MODULE_INT,
230- TWL4030_INT_PWR_SIH_CTRL);
231- WARN_ON(cor < 0);
232-
233- /* Clear TWL4030 INT (PWR) ISRs */
234- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
235- TWL4030_INT_PWR_ISR1, cor) < 0);
236- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INT,
237- TWL4030_INT_PWR_ISR2, cor) < 0);
238-
239- /* Slave address 0x4A */
240-
241- /* Mask BCI interrupts at TWL4030 */
242- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
243- TWL4030_INTERRUPTS_BCIIMR1A) < 0);
244- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
245- TWL4030_INTERRUPTS_BCIIMR2A) < 0);
246- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
247- TWL4030_INTERRUPTS_BCIIMR1B) < 0);
248- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, 0xff,
249- TWL4030_INTERRUPTS_BCIIMR2B) < 0);
250-
251- /* Are BCI interrupt status bits cleared by reads or writes? */
252- cor = twl4030_read_cor_bit(TWL4030_MODULE_INTERRUPTS,
253- TWL4030_INTERRUPTS_BCISIHCTRL);
254- WARN_ON(cor < 0);
255-
256- /* Clear TWL4030 BCI ISRs */
257- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
258- TWL4030_INTERRUPTS_BCIISR1A, cor) < 0);
259- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
260- TWL4030_INTERRUPTS_BCIISR2A, cor) < 0);
261- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
262- TWL4030_INTERRUPTS_BCIISR1B, cor) < 0);
263- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_INTERRUPTS,
264- TWL4030_INTERRUPTS_BCIISR2B, cor) < 0);
265-
266- /* MAD C */
267- /* Mask MADC interrupts at TWL4030 */
268- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
269- TWL4030_MADC_IMR1) < 0);
270- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_MADC, 0xff,
271- TWL4030_MADC_IMR2) < 0);
272-
273- /* Are MADC interrupt status bits cleared by reads or writes? */
274- cor = twl4030_read_cor_bit(TWL4030_MODULE_MADC,
275- TWL4030_MADC_MADC_SIH_CTRL);
276- WARN_ON(cor < 0);
277-
278- /* Clear TWL4030 MADC ISRs */
279- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
280- TWL4030_MADC_ISR1, cor) < 0);
281- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_MADC,
282- TWL4030_MADC_ISR2, cor) < 0);
283-
284- /* key Pad */
285- /* Mask keypad interrupts at TWL4030 */
286- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
287- TWL4030_KEYPAD_KEYP_IMR1) < 0);
288- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_KEYPAD, 0xff,
289- TWL4030_KEYPAD_KEYP_IMR2) < 0);
290-
291- /* Are keypad interrupt status bits cleared by reads or writes? */
292- cor = twl4030_read_cor_bit(TWL4030_MODULE_KEYPAD,
293- TWL4030_KEYPAD_KEYP_SIH_CTRL);
294- WARN_ON(cor < 0);
295-
296- /* Clear TWL4030 keypad ISRs */
297- /* XXX does this still need to be done twice for some reason? */
298- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
299- TWL4030_KEYPAD_KEYP_ISR1, cor) < 0);
300- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_KEYPAD,
301- TWL4030_KEYPAD_KEYP_ISR2, cor) < 0);
302-
303- /* Slave address 0x49 */
304-
305- /* Mask GPIO interrupts at TWL4030 */
306- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
307- REG_GPIO_IMR1A) < 0);
308- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
309- REG_GPIO_IMR2A) < 0);
310- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
311- REG_GPIO_IMR3A) < 0);
312- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
313- REG_GPIO_IMR1B) < 0);
314- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
315- REG_GPIO_IMR2B) < 0);
316- WARN_ON(twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, 0xff,
317- REG_GPIO_IMR3B) < 0);
318-
319- /* Are GPIO interrupt status bits cleared by reads or writes? */
320- cor = twl4030_read_cor_bit(TWL4030_MODULE_GPIO,
321- REG_GPIO_SIH_CTRL);
322- WARN_ON(cor < 0);
323-
324- /* Clear TWL4030 GPIO ISRs */
325- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1A,
326- cor) < 0);
327- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2A,
328- cor) < 0);
329- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3A,
330- cor) < 0);
331- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR1B,
332- cor) < 0);
333- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR2B,
334- cor) < 0);
335- WARN_ON(twl4030_i2c_clear_isr(TWL4030_MODULE_GPIO, REG_GPIO_ISR3B,
336- cor) < 0);
337+ twl4030_mask_clear_intrs(twl4030_mod_regs,
338+ ARRAY_SIZE(twl4030_mod_regs));
339
340 /* install an irq handler for each of the PIH modules */
341 for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch b/meta/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch
new file mode 100644
index 0000000000..c96b95f2f4
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch
@@ -0,0 +1,238 @@
1On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote:
2> Catalin Marinas wrote:
3> > But, anyway, if you want a patch, Harry is updating it to a recent
4> > kernel.
5>
6> Any news on this? I think there are some people wanting a patch ;)
7
8See below for a preliminary patch updated to 2.6.26-rc8. Note that I
9don't plan to submit it in its current form but clean it up a bit first.
10
11
12Show the cache type of ARMv7 CPUs
13
14From: Catalin Marinas <catalin.marinas@arm.com>
15
16Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
17---
18
19 arch/arm/kernel/setup.c | 137 +++++++++++++++++++++++++++++++++++++++++++++-
20 include/asm-arm/system.h | 18 ++++++
21 2 files changed, 153 insertions(+), 2 deletions(-)
22
23
24diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
25index 5ae0eb2..0cd238d 100644
26--- a/arch/arm/kernel/setup.c
27+++ b/arch/arm/kernel/setup.c
28@@ -256,6 +256,24 @@ static const char *proc_arch[] = {
29 "?(17)",
30 };
31
32+static const char *v7_cache_policy[4] = {
33+ "reserved",
34+ "AVIVT",
35+ "VIPT",
36+ "PIPT",
37+};
38+
39+static const char *v7_cache_type[8] = {
40+ "none",
41+ "instruction only",
42+ "data only",
43+ "separate instruction and data",
44+ "unified",
45+ "unknown type",
46+ "unknown type",
47+ "unknown type",
48+};
49+
50 #define CACHE_TYPE(x) (((x) >> 25) & 15)
51 #define CACHE_S(x) ((x) & (1 << 24))
52 #define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */
53@@ -266,6 +284,22 @@ static const char *proc_arch[] = {
54 #define CACHE_M(y) ((y) & (1 << 2))
55 #define CACHE_LINE(y) ((y) & 3)
56
57+#define CACHE_TYPE_V7(x) (((x) >> 14) & 3)
58+#define CACHE_UNIFIED(x) ((((x) >> 27) & 7)+1)
59+#define CACHE_COHERENT(x) ((((x) >> 24) & 7)+1)
60+
61+#define CACHE_ID_LEVEL_MASK 7
62+#define CACHE_ID_LEVEL_BITS 3
63+
64+#define CACHE_LINE_V7(v) ((1 << (((v) & 7)+4)))
65+#define CACHE_ASSOC_V7(v) ((((v) >> 3) & ((1<<10)-1))+1)
66+#define CACHE_SETS_V7(v) ((((v) >> 13) & ((1<<15)-1))+1)
67+#define CACHE_SIZE_V7(v) (CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v))
68+#define CACHE_WA_V7(v) (((v) & (1<<28)) != 0)
69+#define CACHE_RA_V7(v) (((v) & (1<<29)) != 0)
70+#define CACHE_WB_V7(v) (((v) & (1<<30)) != 0)
71+#define CACHE_WT_V7(v) (((v) & (1<<31)) != 0)
72+
73 static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
74 {
75 unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0);
76@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
77 CACHE_LINE(cache)));
78 }
79
80+static void dump_v7_cache(const char *type, int cpu, unsigned int level)
81+{
82+ unsigned int cachesize;
83+
84+ write_extended_cpuid(2,0,0,0,level); /* Set the cache size selection register */
85+ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */
86+ cachesize = read_extended_cpuid(1,0,0,0);
87+
88+ printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n supports%s%s%s%s\n",
89+ cpu, type,
90+ CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize),
91+ CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize),
92+ CACHE_WA_V7(cachesize) ? " WA" : "",
93+ CACHE_RA_V7(cachesize) ? " RA" : "",
94+ CACHE_WB_V7(cachesize) ? " WB" : "",
95+ CACHE_WT_V7(cachesize) ? " WT" : "");
96+}
97+
98 static void __init dump_cpu_info(int cpu)
99 {
100 unsigned int info = read_cpuid(CPUID_CACHETYPE);
101
102- if (info != processor_id) {
103+ if (info != processor_id && (info & (1 << 31))) {
104+ /* ARMv7 style of cache info register */
105+ unsigned int id = read_extended_cpuid(1,0,0,1);
106+ unsigned int level = 0;
107+ printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n",
108+ cpu,
109+ v7_cache_policy[CACHE_TYPE_V7(info)],
110+ CACHE_UNIFIED(id),
111+ CACHE_COHERENT(id));
112+
113+ while (id & CACHE_ID_LEVEL_MASK) {
114+ printk("CPU%u: Level %u cache is %s\n",
115+ cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
116+
117+ if (id & 1) {
118+ /* Dump I at this level */
119+ dump_v7_cache("I", cpu, level | 1);
120+ }
121+
122+ if (id & (4 | 2)) {
123+ /* Dump D or unified at this level */
124+ dump_v7_cache((id & 4) ? "unified" : "D", cpu, level);
125+ }
126+
127+ /* Next level out */
128+ level += 2;
129+ id >>= CACHE_ID_LEVEL_BITS;
130+ }
131+ } else if (info != processor_id) {
132 printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
133 cache_types[CACHE_TYPE(info)]);
134 if (CACHE_S(info)) {
135@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache)
136 CACHE_LINE(cache)));
137 }
138
139+static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect)
140+{
141+ unsigned int cachesize;
142+ unsigned int level = (levelselect >> 1) + 1;
143+
144+ write_extended_cpuid(2,0,0,0,levelselect); /* Set the cache size selection register */
145+ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */
146+ cachesize = read_extended_cpuid(1,0,0,0);
147+
148+ seq_printf(m, "L%u %s size\t\t: %d bytes\n"
149+ "L%u %s assoc\t\t: %d\n"
150+ "L%u %s line length\t: %d\n"
151+ "L%u %s sets\t\t: %d\n"
152+ "L%u %s supports\t\t:%s%s%s%s\n",
153+ level, type, CACHE_SIZE_V7(cachesize),
154+ level, type, CACHE_ASSOC_V7(cachesize),
155+ level, type, CACHE_LINE_V7(cachesize),
156+ level, type, CACHE_SETS_V7(cachesize),
157+ level, type, CACHE_WA_V7(cachesize) ? " WA" : "",
158+ CACHE_RA_V7(cachesize) ? " RA" : "",
159+ CACHE_WB_V7(cachesize) ? " WB" : "",
160+ CACHE_WT_V7(cachesize) ? " WT" : "");
161+}
162+
163 static int c_show(struct seq_file *m, void *v)
164 {
165 int i;
166@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v)
167
168 {
169 unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
170- if (cache_info != processor_id) {
171+ if (cache_info != processor_id && (cache_info & (1<<31))) {
172+ /* V7 style of cache info register */
173+ unsigned int id = read_extended_cpuid(1,0,0,1);
174+ unsigned int levelselect = 0;
175+ seq_printf(m, "L1 I cache\t:%s\n"
176+ "Cache unification level\t: %u\n"
177+ "Cache coherency level\t: %u\n",
178+ v7_cache_policy[CACHE_TYPE_V7(cache_info)],
179+ CACHE_UNIFIED(id),
180+ CACHE_COHERENT(id));
181+
182+ while (id & CACHE_ID_LEVEL_MASK) {
183+ seq_printf(m, "Level %u cache\t\t: %s\n",
184+ (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]);
185+
186+ if (id & 1) {
187+ /* Dump I at this level */
188+ c_show_v7_cache(m, "I", levelselect | 1);
189+ }
190+
191+ if (id & (4 | 2)) {
192+ /* Dump D or unified at this level */
193+ c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect);
194+ }
195+
196+ /* Next level out */
197+ levelselect += 2;
198+ id >>= CACHE_ID_LEVEL_BITS;
199+ }
200+ } else if (cache_info != processor_id) {
201 seq_printf(m, "Cache type\t: %s\n"
202 "Cache clean\t: %s\n"
203 "Cache lockdown\t: %s\n"
204diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
205index 514af79..704738e 100644
206--- a/include/asm-arm/system.h
207+++ b/include/asm-arm/system.h
208@@ -74,6 +74,24 @@
209 : "cc"); \
210 __val; \
211 })
212+#define read_extended_cpuid(op1,op2,op3,op4) \
213+ ({ \
214+ unsigned int __val; \
215+ asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \
216+ : "=r" (__val) \
217+ : \
218+ : "cc"); \
219+ __val; \
220+ })
221+
222+#define write_extended_cpuid(op1,op2,op3,op4,v) \
223+ ({ \
224+ unsigned int __val = v; \
225+ asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \
226+ : \
227+ : "r" (__val) \
228+ : "cc"); \
229+ })
230 #else
231 extern unsigned int processor_id;
232 #define read_cpuid(reg) (processor_id)
233
234
235--
236Catalin
237
238
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/defconfig b/meta/packages/linux/linux-omap2-git/beagleboard/defconfig
index 87fadae1ec..6381271cf9 100644
--- a/meta/packages/linux/linux-omap2-git/beagleboard/defconfig
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc8-omap1 3# Linux kernel version: 2.6.26-rc9-omap1
4# Fri Jul 4 09:57:18 2008 4# Tue Jul 8 15:36:02 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -1037,6 +1037,7 @@ CONFIG_MEDIA_TUNER=m
1037# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set 1037# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
1038CONFIG_MEDIA_TUNER_SIMPLE=m 1038CONFIG_MEDIA_TUNER_SIMPLE=m
1039CONFIG_MEDIA_TUNER_TDA8290=m 1039CONFIG_MEDIA_TUNER_TDA8290=m
1040CONFIG_MEDIA_TUNER_TDA18271=m
1040CONFIG_MEDIA_TUNER_TDA9887=m 1041CONFIG_MEDIA_TUNER_TDA9887=m
1041CONFIG_MEDIA_TUNER_TEA5761=m 1042CONFIG_MEDIA_TUNER_TEA5761=m
1042CONFIG_MEDIA_TUNER_TEA5767=m 1043CONFIG_MEDIA_TUNER_TEA5767=m
@@ -1048,9 +1049,17 @@ CONFIG_MEDIA_TUNER_XC2028=m
1048CONFIG_MEDIA_TUNER_XC5000=m 1049CONFIG_MEDIA_TUNER_XC5000=m
1049CONFIG_VIDEO_V4L2=m 1050CONFIG_VIDEO_V4L2=m
1050CONFIG_VIDEO_V4L1=m 1051CONFIG_VIDEO_V4L1=m
1052CONFIG_VIDEO_TVEEPROM=m
1053CONFIG_VIDEO_TUNER=m
1051CONFIG_VIDEO_CAPTURE_DRIVERS=y 1054CONFIG_VIDEO_CAPTURE_DRIVERS=y
1052# CONFIG_VIDEO_ADV_DEBUG is not set 1055# CONFIG_VIDEO_ADV_DEBUG is not set
1053CONFIG_VIDEO_HELPER_CHIPS_AUTO=y 1056CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1057CONFIG_VIDEO_MSP3400=m
1058CONFIG_VIDEO_CS53L32A=m
1059CONFIG_VIDEO_WM8775=m
1060CONFIG_VIDEO_SAA711X=m
1061CONFIG_VIDEO_CX25840=m
1062CONFIG_VIDEO_CX2341X=m
1054# CONFIG_VIDEO_VIVI is not set 1063# CONFIG_VIDEO_VIVI is not set
1055# CONFIG_VIDEO_CPIA is not set 1064# CONFIG_VIDEO_CPIA is not set
1056# CONFIG_VIDEO_CPIA2 is not set 1065# CONFIG_VIDEO_CPIA2 is not set
@@ -1059,23 +1068,29 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1059# CONFIG_TUNER_3036 is not set 1068# CONFIG_TUNER_3036 is not set
1060# CONFIG_VIDEO_AU0828 is not set 1069# CONFIG_VIDEO_AU0828 is not set
1061CONFIG_V4L_USB_DRIVERS=y 1070CONFIG_V4L_USB_DRIVERS=y
1062# CONFIG_VIDEO_PVRUSB2 is not set 1071CONFIG_USB_VIDEO_CLASS=m
1072CONFIG_VIDEO_PVRUSB2=m
1073CONFIG_VIDEO_PVRUSB2_SYSFS=y
1074CONFIG_VIDEO_PVRUSB2_DVB=y
1075# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
1063# CONFIG_VIDEO_EM28XX is not set 1076# CONFIG_VIDEO_EM28XX is not set
1064# CONFIG_VIDEO_USBVISION is not set 1077CONFIG_VIDEO_USBVISION=m
1065# CONFIG_USB_VICAM is not set 1078CONFIG_VIDEO_USBVIDEO=m
1066# CONFIG_USB_IBMCAM is not set 1079CONFIG_USB_VICAM=m
1067# CONFIG_USB_KONICAWC is not set 1080CONFIG_USB_IBMCAM=m
1068# CONFIG_USB_QUICKCAM_MESSENGER is not set 1081CONFIG_USB_KONICAWC=m
1082CONFIG_USB_QUICKCAM_MESSENGER=m
1069# CONFIG_USB_ET61X251 is not set 1083# CONFIG_USB_ET61X251 is not set
1070# CONFIG_VIDEO_OVCAMCHIP is not set 1084CONFIG_VIDEO_OVCAMCHIP=m
1071# CONFIG_USB_W9968CF is not set 1085CONFIG_USB_W9968CF=m
1072# CONFIG_USB_OV511 is not set 1086CONFIG_USB_OV511=m
1073# CONFIG_USB_SE401 is not set 1087CONFIG_USB_SE401=m
1074# CONFIG_USB_SN9C102 is not set 1088CONFIG_USB_SN9C102=m
1075# CONFIG_USB_STV680 is not set 1089CONFIG_USB_STV680=m
1076# CONFIG_USB_ZC0301 is not set 1090# CONFIG_USB_ZC0301 is not set
1077# CONFIG_USB_PWC is not set 1091CONFIG_USB_PWC=m
1078# CONFIG_USB_ZR364XX is not set 1092# CONFIG_USB_PWC_DEBUG is not set
1093CONFIG_USB_ZR364XX=m
1079# CONFIG_USB_STKWEBCAM is not set 1094# CONFIG_USB_STKWEBCAM is not set
1080# CONFIG_SOC_CAMERA is not set 1095# CONFIG_SOC_CAMERA is not set
1081CONFIG_RADIO_ADAPTERS=y 1096CONFIG_RADIO_ADAPTERS=y
@@ -1225,9 +1240,13 @@ CONFIG_FB_CFB_IMAGEBLIT=y
1225# CONFIG_FB_S1D13XXX is not set 1240# CONFIG_FB_S1D13XXX is not set
1226# CONFIG_FB_VIRTUAL is not set 1241# CONFIG_FB_VIRTUAL is not set
1227CONFIG_FB_OMAP=y 1242CONFIG_FB_OMAP=y
1243# CONFIG_FB_OMAP_031M3R is not set
1244# CONFIG_FB_OMAP_048M3R is not set
1245CONFIG_FB_OMAP_079M3R=y
1246# CONFIG_FB_OMAP_092M9R is not set
1228# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set 1247# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
1229# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set 1248# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
1230CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4 1249CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8
1231# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1250# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1232 1251
1233# 1252#
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff b/meta/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff
new file mode 100644
index 0000000000..6eb33f76b7
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff
@@ -0,0 +1,118 @@
1From linux-omap-owner@vger.kernel.org Tue Jul 15 21:23:13 2008
2Received: from localhost
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29Date: Tue, 15 Jul 2008 13:00:18 -0600 (MDT)
30From: Paul Walmsley <paul@pwsan.com>
31To: linux-omap@vger.kernel.org
32Subject: [PATCH] i2c-omap: close suspected race between omap_i2c_idle() and
33 omap_i2c_isr()
34Message-ID: <alpine.DEB.1.00.0807151259180.467@utopia.booyaka.com>
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46X-OriginalArrivalTime: 15 Jul 2008 19:01:01.0610 (UTC) FILETIME=[1FBA68A0:01C8E6AD]
47
48
49omap_i2c_idle() sets an internal flag, "dev->idle", instructing its
50ISR to decline interrupts. It sets this flag before it actually masks
51the interrupts on the I2C controller. This is problematic, since an
52I2C interrupt could arrive after dev->idle is set, but before the
53interrupt source is masked. When this happens, Linux disables the I2C
54controller's IRQ, causing all future transactions on the bus to fail.
55
56Symptoms, happening on about 7% of boots:
57
58 irq 56: nobody cared (try booting with the "irqpoll" option)
59 <warning traceback here>
60 Disabling IRQ #56
61 i2c_omap i2c_omap.1: controller timed out
62
63In omap_i2c_idle(), this patch sets dev->idle only after the interrupt
64mask write to the I2C controller has left the ARM write buffer.
65That's probably the major offender. For additional prophylaxis, in
66omap_i2c_unidle(), the patch clears the dev->idle flag before
67interrupts are enabled, rather than afterwards.
68
69The patch has survived twenty-two reboots on the 3430SDP here without
70wedging I2C1. Not absolutely dispositive, but promising!
71
72
73Signed-off-by: Paul Walmsley <paul@pwsan.com>
74---
75
76 drivers/i2c/busses/i2c-omap.c | 10 ++++++++--
77 1 files changed, 8 insertions(+), 2 deletions(-)
78
79diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
80index 55779f5..ed7e9ad 100644
81--- a/drivers/i2c/busses/i2c-omap.c
82+++ b/drivers/i2c/busses/i2c-omap.c
83@@ -209,22 +209,28 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
84 if (dev->iclk != NULL)
85 clk_enable(dev->iclk);
86 clk_enable(dev->fclk);
87+ dev->idle = 0;
88 if (dev->iestate)
89 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
90- dev->idle = 0;
91 }
92
93 static void omap_i2c_idle(struct omap_i2c_dev *dev)
94 {
95 u16 iv;
96
97- dev->idle = 1;
98 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
99 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
100 if (dev->rev1)
101 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
102 else
103 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
104+ /*
105+ * The wmb() is to ensure that the I2C interrupt mask write
106+ * reaches the I2C controller before the dev->idle store
107+ * occurs.
108+ */
109+ wmb();
110+ dev->idle = 1;
111 clk_disable(dev->fclk);
112 if (dev->iclk != NULL)
113 clk_disable(dev->iclk);
114--
115To unsubscribe from this list: send the line "unsubscribe linux-omap" in
116the body of a message to majordomo@vger.kernel.org
117More majordomo info at http://vger.kernel.org/majordomo-info.html
118
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks1.diff b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks1.diff
new file mode 100644
index 0000000000..d7dadbc85e
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks1.diff
@@ -0,0 +1,25 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Tue, 22 Jul 2008 00:31:11 +0000 (+0100)
3Subject: ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate()
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2b7b958dc79e51127d7a4ecf88ce12dbc6c31426
5
6ARM: OMAP: make dpll4_m4_ck programmable with clk_set_rate()
7
8Filling the set_rate and round_rate fields of dpll4_m4_ck makes
9this clock programmable through clk_set_rate(). This is needed
10to give omapfb control over the dss1_alwon_fck rate.
11---
12
13diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
14index 161da12..876eb13 100644
15--- a/arch/arm/mach-omap2/clock34xx.h
16+++ b/arch/arm/mach-omap2/clock34xx.h
17@@ -815,6 +815,8 @@ static struct clk dpll4_m4_ck = {
18 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
19 PARENT_CONTROLS_CLOCK,
20 .recalc = &omap2_clksel_recalc,
21+ .set_rate = &omap2_clksel_set_rate,
22+ .round_rate = &omap2_clksel_round_rate,
23 };
24
25 /* The PWRDN bit is apparently only available on 3430ES2 and above */
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks2.diff b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks2.diff
new file mode 100644
index 0000000000..c8b370da03
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks2.diff
@@ -0,0 +1,62 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Tue, 22 Jul 2008 00:58:18 +0000 (+0100)
3Subject: ARM: OMAP: add clk_get_parent() for OMAP2/3
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=e2de5e5578fbaa9b4b75074796da0608fc93e6ae
5
6ARM: OMAP: add clk_get_parent() for OMAP2/3
7
8Signed-off-by: Mans Rullgard <mans@mansr.com>
9---
10
11diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
12index 577be44..28aec36 100644
13--- a/arch/arm/mach-omap2/clock.c
14+++ b/arch/arm/mach-omap2/clock.c
15@@ -824,6 +824,11 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
16 return 0;
17 }
18
19+struct clk *omap2_clk_get_parent(struct clk *clk)
20+{
21+ return clk->parent;
22+}
23+
24 /* DPLL rate rounding code */
25
26 /**
27diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
28index 49245f7..4aa69d5 100644
29--- a/arch/arm/mach-omap2/clock.h
30+++ b/arch/arm/mach-omap2/clock.h
31@@ -29,6 +29,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
32 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
33 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
34 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
35+struct clk *omap2_clk_get_parent(struct clk *clk);
36
37 #ifdef CONFIG_OMAP_RESET_CLOCKS
38 void omap2_clk_disable_unused(struct clk *clk);
39diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
40index 54cc6e1..ed7af21 100644
41--- a/arch/arm/mach-omap2/clock24xx.c
42+++ b/arch/arm/mach-omap2/clock24xx.c
43@@ -422,6 +422,7 @@ static struct clk_functions omap2_clk_functions = {
44 .clk_round_rate = omap2_clk_round_rate,
45 .clk_set_rate = omap2_clk_set_rate,
46 .clk_set_parent = omap2_clk_set_parent,
47+ .clk_get_parent = omap2_clk_get_parent,
48 .clk_disable_unused = omap2_clk_disable_unused,
49 #ifdef CONFIG_CPU_FREQ
50 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
51diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
52index 04dedec..08c8c46 100644
53--- a/arch/arm/mach-omap2/clock34xx.c
54+++ b/arch/arm/mach-omap2/clock34xx.c
55@@ -541,6 +541,7 @@ static struct clk_functions omap2_clk_functions = {
56 .clk_round_rate = omap2_clk_round_rate,
57 .clk_set_rate = omap2_clk_set_rate,
58 .clk_set_parent = omap2_clk_set_parent,
59+ .clk_get_parent = omap2_clk_get_parent,
60 .clk_disable_unused = omap2_clk_disable_unused,
61 };
62
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks3.diff b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks3.diff
new file mode 100644
index 0000000000..f8407fc2d5
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/mru-clocks3.diff
@@ -0,0 +1,94 @@
1From: Mans Rullgard <mans@mansr.com>
2Date: Wed, 23 Jul 2008 08:40:07 +0000 (+0100)
3Subject: ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock
4X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=01ee28c50701caa94739e764c3dae9298edd8216
5
6ARM: OMAP: Set DSS1_ALWON_FCLK to a multiple of the pixel clock
7
8This sets the DSS1_ALWON_FCLK clock as close as possible to a
9multiple of the requested pixel clock, while keeping it below
10the 173MHz limit.
11
12Due to of the structure of the clock tree, dss1_alwon_fck cannot
13be set directly, and we must use dpll4_m4_ck instead.
14
15Signed-off-by: Mans Rullgard <mans@mansr.com>
16---
17
18diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
19index fd06ca2..e0e8528 100644
20--- a/drivers/video/omap/dispc.c
21+++ b/drivers/video/omap/dispc.c
22@@ -176,6 +176,7 @@ static struct {
23
24 struct clk *dss_ick, *dss1_fck;
25 struct clk *dss_54m_fck;
26+ struct clk *dpll4_m4_ck;
27
28 enum omapfb_update_mode update_mode;
29 struct omapfb_device *fbdev;
30@@ -738,21 +739,34 @@ static void setup_color_conv_coef(void)
31 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
32 }
33
34-#define MAX_FCK_LCD 173000000
35+#define MAX_FCK 173000000
36
37 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
38 {
39+ unsigned long prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
40+ unsigned long pcd_min = is_tft? 2: 3;
41+ unsigned long fck_div;
42 unsigned long fck, lck;
43
44 pck = max(1, pck);
45+
46+ if (pck * pcd_min > MAX_FCK) {
47+ dev_warn(dispc.fbdev->dev, "pixclock %d kHz too high.\n",
48+ pck / 1000);
49+ pck = MAX_FCK / pcd_min;
50+ }
51+
52+ fck = pck * 2;
53+ fck_div = (prate + pck) / fck;
54+ if (fck_div > 16)
55+ fck_div /= (fck_div + 15) / 16;
56+ if (fck_div < 1)
57+ fck_div = 1;
58+ clk_set_rate(dispc.dpll4_m4_ck, prate / fck_div);
59 fck = clk_get_rate(dispc.dss1_fck);
60- *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD;
61- lck = fck / *lck_div;
62- *pck_div = (lck + pck - 1) / pck;
63- if (is_tft)
64- *pck_div = max(2, *pck_div);
65- else
66- *pck_div = max(3, *pck_div);
67+
68+ *lck_div = 1;
69+ *pck_div = (fck + pck - 1) / pck;
70 if (*pck_div > 255) {
71 *pck_div = 255;
72 lck = pck * *pck_div;
73@@ -914,11 +928,21 @@ static int get_dss_clocks(void)
74 return PTR_ERR(dispc.dss_54m_fck);
75 }
76
77+ if (IS_ERR((dispc.dpll4_m4_ck =
78+ clk_get(dispc.fbdev->dev, "dpll4_m4_ck")))) {
79+ dev_err(dispc.fbdev->dev, "can't get dpll4_m4_ck");
80+ clk_put(dispc.dss_ick);
81+ clk_put(dispc.dss1_fck);
82+ clk_put(dispc.dss_54m_fck);
83+ return PTR_ERR(dispc.dss_54m_fck);
84+ }
85+
86 return 0;
87 }
88
89 static void put_dss_clocks(void)
90 {
91+ clk_put(dispc.dpll4_m4_ck);
92 clk_put(dispc.dss_54m_fck);
93 clk_put(dispc.dss1_fck);
94 clk_put(dispc.dss_ick);
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/serialfix.diff b/meta/packages/linux/linux-omap2-git/beagleboard/serialfix.diff
new file mode 100644
index 0000000000..74c2ebaa69
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/serialfix.diff
@@ -0,0 +1,18 @@
1--- /tmp/pm34xx.c 2008-07-14 18:09:08.000000000 +0200
2+++ git/arch/arm/mach-omap2/pm34xx.c 2008-07-14 18:09:42.453198000 +0200
3@@ -398,13 +398,13 @@
4 INT_34XX_PRCM_MPU_IRQ);
5 goto err1;
6 }
7-
8+/*
9 ret = pwrdm_for_each(pwrdms_setup);
10 if (ret) {
11 printk(KERN_ERR "Failed to setup powerdomains\n");
12 goto err2;
13 }
14-
15+*/
16 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
17 if (mpu_pwrdm == NULL) {
18 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
diff --git a/meta/packages/linux/linux-omap2-git/beagleboard/soc.patch b/meta/packages/linux/linux-omap2-git/beagleboard/soc.patch
index bb97403f29..f4cce21ca7 100644
--- a/meta/packages/linux/linux-omap2-git/beagleboard/soc.patch
+++ b/meta/packages/linux/linux-omap2-git/beagleboard/soc.patch
@@ -29,10 +29,10 @@ index 4e1314c..d2c0b12 100644
29+obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o 29+obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
30diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c 30diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
31new file mode 100644 31new file mode 100644
32index 0000000..c9eee19 32index 0000000..eb8370c
33--- /dev/null 33--- /dev/null
34+++ b/sound/soc/codecs/twl4030.c 34+++ b/sound/soc/codecs/twl4030.c
35@@ -0,0 +1,595 @@ 35@@ -0,0 +1,625 @@
36+/* 36+/*
37+ * ALSA SoC TWL4030 codec driver 37+ * ALSA SoC TWL4030 codec driver
38+ * 38+ *
@@ -196,7 +196,7 @@ index 0000000..c9eee19
196+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 196+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
197+ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); 197+ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE);
198+ 198+
199+ udelay(10); /* 10 ms delay for power settling */ 199+ udelay(10); /* delay for power settling */
200+ 200+
201+ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { 201+ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) {
202+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); 202+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i);
@@ -205,7 +205,7 @@ index 0000000..c9eee19
205+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 205+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
206+ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); 206+ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE);
207+ 207+
208+ udelay(10); /* 10 ms delay for power settling */ 208+ udelay(10); /* delay for power settling */
209+ 209+
210+ /* initiate offset cancellation */ 210+ /* initiate offset cancellation */
211+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 211+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
@@ -219,7 +219,6 @@ index 0000000..c9eee19
219+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 219+ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
220+ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); 220+ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1);
221+ 221+
222+ twl4030_dump_registers();
223+} 222+}
224+ 223+
225+static const struct snd_kcontrol_new twl4030_snd_controls[] = { 224+static const struct snd_kcontrol_new twl4030_snd_controls[] = {
@@ -247,8 +246,6 @@ index 0000000..c9eee19
247+ return 0; 246+ return 0;
248+} 247+}
249+ 248+
250+#define TWL4030_PWR 0
251+
252+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { 249+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
253+ SND_SOC_DAPM_INPUT("INL"), 250+ SND_SOC_DAPM_INPUT("INL"),
254+ SND_SOC_DAPM_INPUT("INR"), 251+ SND_SOC_DAPM_INPUT("INR"),
@@ -314,32 +311,40 @@ index 0000000..c9eee19
314+ 311+
315+static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) 312+static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode)
316+{ 313+{
314+ u8 popn, hsgain;
315+
317+ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); 316+ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ);
318+ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); 317+ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ);
319+ udelay(10); 318+ udelay(10);
320+ 319+
321+ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x40); 320+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET);
321+ popn &= RAMP_DELAY;
322+ popn |= VMID_EN | RAMP_DELAY_161MS;
322+ twl4030_write(codec, REG_HS_POPN_SET, popn); 323+ twl4030_write(codec, REG_HS_POPN_SET, popn);
323+ 324+
324+ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) | (0x0a); 325+ hsgain = HSR_GAIN_0DB| HSL_GAIN_0DB;
325+ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); 326+ twl4030_write(codec, REG_HS_GAIN_SET, hsgain);
326+ 327+
327+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x02); 328+ popn |= RAMP_EN;
328+ twl4030_write(codec, REG_HS_POPN_SET, popn); 329+ twl4030_write(codec, REG_HS_POPN_SET, popn);
329+} 330+}
330+ 331+
331+static void twl4030_power_down (struct snd_soc_codec *codec) 332+static void twl4030_power_down (struct snd_soc_codec *codec)
332+{ 333+{
333+ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x02); 334+ u8 popn, hsgain, mode;
335+
336+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET);
337+ popn &= ~RAMP_EN;
334+ twl4030_write(codec, REG_HS_POPN_SET, popn); 338+ twl4030_write(codec, REG_HS_POPN_SET, popn);
335+ 339+
336+ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) & ~(0x0f); 340+ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN;
337+ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); 341+ twl4030_write(codec, REG_HS_GAIN_SET, hsgain);
338+ 342+
339+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x40); 343+ popn &= ~VMID_EN;
340+ twl4030_write(codec, REG_HS_POPN_SET, popn); 344+ twl4030_write(codec, REG_HS_POPN_SET, popn);
341+ 345+
342+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; 346+ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE);
347+ mode &= ~CODECPDZ;
343+ twl4030_write(codec, REG_CODEC_MODE, mode); 348+ twl4030_write(codec, REG_CODEC_MODE, mode);
344+ udelay(10); 349+ udelay(10);
345+} 350+}
@@ -352,19 +357,18 @@ index 0000000..c9eee19
352+ struct snd_soc_device *socdev = rtd->socdev; 357+ struct snd_soc_device *socdev = rtd->socdev;
353+ struct snd_soc_codec *codec = socdev->codec; 358+ struct snd_soc_codec *codec = socdev->codec;
354+ struct twl4030_priv *twl4030 = codec->private_data; 359+ struct twl4030_priv *twl4030 = codec->private_data;
360+ u8 mode, old_mode, format, old_format;
355+ 361+
356+ twl4030_power_down(codec);
357+
358+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ;
359+ 362+
363+ /* bit rate */
364+ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ;
365+ mode = old_mode;
360+ mode &= ~APLL_RATE; 366+ mode &= ~APLL_RATE;
361+ switch (params_rate(params)) { 367+ switch (params_rate(params)) {
362+ case 44100: 368+ case 44100:
363+ printk(KERN_INFO "TWL4030 hw params: set rate to 44.1khz\n");
364+ mode |= APLL_RATE_44100; 369+ mode |= APLL_RATE_44100;
365+ break; 370+ break;
366+ case 48000: 371+ case 48000:
367+ printk(KERN_INFO "TWL4030 hw params: set rate to 48khz\n");
368+ mode |= APLL_RATE_48000; 372+ mode |= APLL_RATE_48000;
369+ break; 373+ break;
370+ default: 374+ default:
@@ -372,22 +376,43 @@ index 0000000..c9eee19
372+ return -EINVAL; 376+ return -EINVAL;
373+ } 377+ }
374+ 378+
375+ /* bit size */ 379+ if (mode != old_mode) {
380+ /* change rate and turn codec back on */
381+ twl4030_write(codec, REG_CODEC_MODE, mode);
382+ mode |= CODECPDZ;
383+ twl4030_write(codec, REG_CODEC_MODE, mode);
384+ }
385+
386+ /* sample size */
387+ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF);
388+ format = old_format;
389+ format &= ~DATA_WIDTH;
376+ switch (params_format(params)) { 390+ switch (params_format(params)) {
377+ case SNDRV_PCM_FORMAT_S16_LE: 391+ case SNDRV_PCM_FORMAT_S16_LE:
378+ printk(KERN_INFO "TWL4030 hw params: set format to S16_LE\n"); 392+ format |= DATA_WIDTH_16S_16W;
379+ break; 393+ break;
380+ case SNDRV_PCM_FORMAT_S24_LE: 394+ case SNDRV_PCM_FORMAT_S24_LE:
381+ printk(KERN_INFO "TWL4030 hw params: set format to S24_LE\n"); 395+ format |= DATA_WIDTH_32S_24W;
382+ break; 396+ break;
383+ default: 397+ default:
384+ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); 398+ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params));
385+ return -EINVAL; 399+ return -EINVAL;
386+ } 400+ }
387+ 401+
388+ /* change rate and turn codec back on */ 402+ if (format != old_format) {
389+ twl4030_power_up(codec, mode); 403+
404+ /* turn off codec before changing format */
405+ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE);
406+ mode &= ~CODECPDZ;
407+ twl4030_write(codec, REG_CODEC_MODE, mode);
390+ 408+
409+ /* change format */
410+ twl4030_write(codec, REG_AUDIO_IF, format);
411+
412+ /* turn on codec */
413+ mode |= CODECPDZ;
414+ twl4030_write(codec, REG_CODEC_MODE, mode);
415+ }
391+ return 0; 416+ return 0;
392+} 417+}
393+ 418+
@@ -399,14 +424,14 @@ index 0000000..c9eee19
399+ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); 424+ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA);
400+ 425+
401+ if (mute) { 426+ if (mute) {
402+ printk(KERN_INFO "TWL4030 Audio Codec mute\n"); 427+ /* printk(KERN_INFO "TWL4030 Audio Codec mute\n"); */
403+ twl4030_write(codec, REG_ARXL2PGA, 0x00); 428+ twl4030_write(codec, REG_ARXL2PGA, 0x00);
404+ twl4030_write(codec, REG_ARXR2PGA, 0x00); 429+ twl4030_write(codec, REG_ARXR2PGA, 0x00);
405+ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); 430+ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg);
406+ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); 431+ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg);
407+ } 432+ }
408+ else { 433+ else {
409+ printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); 434+ /* printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); */
410+ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); 435+ twl4030_write(codec, REG_ARXL2PGA, ldac_reg);
411+ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); 436+ twl4030_write(codec, REG_ARXR2PGA, rdac_reg);
412+ } 437+ }
@@ -419,19 +444,21 @@ index 0000000..c9eee19
419+{ 444+{
420+ struct snd_soc_codec *codec = codec_dai->codec; 445+ struct snd_soc_codec *codec = codec_dai->codec;
421+ struct twl4030_priv *twl4030 = codec->private_data; 446+ struct twl4030_priv *twl4030 = codec->private_data;
447+ u8 mode, old_format, format;
422+ 448+
423+ /* get current format */ 449+ /* get format */
424+ u8 format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); 450+ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF);
451+ format = old_format;
425+ 452+
426+ /* set master/slave audio interface */ 453+ /* set master/slave audio interface */
427+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 454+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
428+ case SND_SOC_DAIFMT_CBM_CFM: 455+ case SND_SOC_DAIFMT_CBM_CFM:
429+ printk(KERN_INFO "TWL4030 set dai fmt: master\n"); 456+ /* printk(KERN_INFO "TWL4030 set dai fmt: master\n"); */
430+ format &= ~(AIF_SLAVE_EN); 457+ format &= ~(AIF_SLAVE_EN);
431+ format |= CLK256FS_EN; 458+ format |= CLK256FS_EN;
432+ break; 459+ break;
433+ case SND_SOC_DAIFMT_CBS_CFS: 460+ case SND_SOC_DAIFMT_CBS_CFS:
434+ printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); 461+ /* printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); */
435+ format &= ~(CLK256FS_EN); 462+ format &= ~(CLK256FS_EN);
436+ format |= AIF_SLAVE_EN; 463+ format |= AIF_SLAVE_EN;
437+ break; 464+ break;
@@ -443,21 +470,26 @@ index 0000000..c9eee19
443+ format &= ~AIF_FORMAT; 470+ format &= ~AIF_FORMAT;
444+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 471+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
445+ case SND_SOC_DAIFMT_I2S: 472+ case SND_SOC_DAIFMT_I2S:
446+ printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); 473+ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */
447+ format |= AIF_FORMAT_CODEC; 474+ format |= AIF_FORMAT_CODEC;
448+ break; 475+ break;
449+ default: 476+ default:
450+ return -EINVAL; 477+ return -EINVAL;
451+ } 478+ }
452+ 479+
453+ /* turn off codec before changing format */ 480+ if (format != old_format) {
454+ twl4030_power_down(codec);
455+ 481+
456+ /* change format */ 482+ /* turn off codec before changing format */
457+ twl4030_write(codec, REG_AUDIO_IF, format); 483+ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE);
484+ mode &= ~CODECPDZ;
485+ twl4030_write(codec, REG_CODEC_MODE, mode);
458+ 486+
459+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); 487+ /* change format */
460+ twl4030_power_up(codec, mode); 488+ twl4030_write(codec, REG_AUDIO_IF, format);
489+
490+ mode |= CODECPDZ;
491+ twl4030_write(codec, REG_CODEC_MODE, mode);
492+ }
461+ 493+
462+ return 0; 494+ return 0;
463+} 495+}
@@ -530,8 +562,6 @@ index 0000000..c9eee19
530+ 562+
531+ printk(KERN_INFO "TWL4030 Audio Codec init \n"); 563+ printk(KERN_INFO "TWL4030 Audio Codec init \n");
532+ 564+
533+ twl4030_init_chip();
534+
535+ codec->name = "twl4030"; 565+ codec->name = "twl4030";
536+ codec->owner = THIS_MODULE; 566+ codec->owner = THIS_MODULE;
537+ codec->read = twl4030_read_reg_cache; 567+ codec->read = twl4030_read_reg_cache;
@@ -560,6 +590,9 @@ index 0000000..c9eee19
560+ goto card_err; 590+ goto card_err;
561+ } 591+ }
562+ 592+
593+ twl4030_init_chip();
594+ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE);
595+
563+ return ret; 596+ return ret;
564+ 597+
565+card_err: 598+card_err:
@@ -580,8 +613,6 @@ index 0000000..c9eee19
580+ struct snd_soc_codec *codec; 613+ struct snd_soc_codec *codec;
581+ struct twl4030_priv *twl4030; 614+ struct twl4030_priv *twl4030;
582+ 615+
583+ printk(KERN_INFO "TWL4030 Audio Codec probe\n");
584+
585+ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 616+ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
586+ if (codec == NULL) 617+ if (codec == NULL)
587+ return -ENOMEM; 618+ return -ENOMEM;
@@ -601,7 +632,6 @@ index 0000000..c9eee19
601+ twl4030_socdev = socdev; 632+ twl4030_socdev = socdev;
602+ twl4030_init(socdev); 633+ twl4030_init(socdev);
603+ 634+
604+ printk(KERN_INFO "TWL4030 Audio Codec probe exit\n");
605+ return 0; 635+ return 0;
606+} 636+}
607+ 637+
@@ -630,10 +660,10 @@ index 0000000..c9eee19
630+MODULE_LICENSE("GPL"); 660+MODULE_LICENSE("GPL");
631diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h 661diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h
632new file mode 100644 662new file mode 100644
633index 0000000..af8eb43 663index 0000000..e126f96
634--- /dev/null 664--- /dev/null
635+++ b/sound/soc/codecs/twl4030.h 665+++ b/sound/soc/codecs/twl4030.h
636@@ -0,0 +1,125 @@ 666@@ -0,0 +1,152 @@
637+/* 667+/*
638+ * ALSA SoC TWL4030 codec driver 668+ * ALSA SoC TWL4030 codec driver
639+ * 669+ *
@@ -722,7 +752,7 @@ index 0000000..af8eb43
722+ 752+
723+/* Bitfield Definitions */ 753+/* Bitfield Definitions */
724+ 754+
725+/* CODEC_MODE Fields */ 755+/* CODEC_MODE (0x01) Fields */
726+ 756+
727+#define APLL_RATE 0xF0 757+#define APLL_RATE 0xF0
728+#define APLL_RATE_8000 0x00 758+#define APLL_RATE_8000 0x00
@@ -738,7 +768,7 @@ index 0000000..af8eb43
738+#define CODECPDZ 0x02 768+#define CODECPDZ 0x02
739+#define OPT_MODE 0x01 769+#define OPT_MODE 0x01
740+ 770+
741+/* AUDIO_IF Fields */ 771+/* AUDIO_IF (0x0E) Fields */
742+ 772+
743+#define AIF_SLAVE_EN 0x80 773+#define AIF_SLAVE_EN 0x80
744+#define DATA_WIDTH 0x60 774+#define DATA_WIDTH 0x60
@@ -754,6 +784,33 @@ index 0000000..af8eb43
754+#define CLK256FS_EN 0x02 784+#define CLK256FS_EN 0x02
755+#define AIF_EN 0x01 785+#define AIF_EN 0x01
756+ 786+
787+/* HS_GAIN_SET (0x23) Fields */
788+
789+#define HSR_GAIN 0x0c
790+#define HSR_GAIN_PWR_DOWN 0x00
791+#define HSR_GAIN_PLUS_6DB 0x04
792+#define HSR_GAIN_0DB 0x08
793+#define HSR_GAIN_MINUS_6DB 0x0c
794+#define HSL_GAIN 0x0c
795+#define HSL_GAIN_PWR_DOWN 0x00
796+#define HSL_GAIN_PLUS_6DB 0x01
797+#define HSL_GAIN_0DB 0x02
798+#define HSL_GAIN_MINUS_6DB 0x03
799+
800+/* HS_POPN_SET (0x24) Fields */
801+
802+#define VMID_EN 0x40
803+#define EXTMUTE 0x20
804+#define RAMP_DELAY 0x1C
805+#define RAMP_DELAY_20MS 0x00
806+#define RAMP_DELAY_40MS 0x04
807+#define RAMP_DELAY_81MS 0x08
808+#define RAMP_DELAY_161MS 0x0c
809+#define RAMP_DELAY_323MS 0x10
810+#define RAMP_DELAY_645MS 0x14
811+#define RAMP_DELAY_1291MS 0x18
812+#define RAMP_DELAY_2581MS 0x1c
813+#define RAMP_EN 0x02
757+ 814+
758+extern struct snd_soc_codec_dai twl4030_dai; 815+extern struct snd_soc_codec_dai twl4030_dai;
759+extern struct snd_soc_codec_device soc_codec_dev_twl4030; 816+extern struct snd_soc_codec_device soc_codec_dev_twl4030;
@@ -801,10 +858,10 @@ index d8d8d58..638a240 100644
801+ 858+
802diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c 859diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
803new file mode 100644 860new file mode 100644
804index 0000000..fb79938 861index 0000000..878f894
805--- /dev/null 862--- /dev/null
806+++ b/sound/soc/omap/omap3beagle.c 863+++ b/sound/soc/omap/omap3beagle.c
807@@ -0,0 +1,180 @@ 864@@ -0,0 +1,142 @@
808+/* 865+/*
809+ * omap3beagle.c -- SoC audio for OMAP3 Beagle 866+ * omap3beagle.c -- SoC audio for OMAP3 Beagle
810+ * 867+ *
@@ -877,50 +934,12 @@ index 0000000..fb79938
877+ .hw_params = omap3beagle_hw_params, 934+ .hw_params = omap3beagle_hw_params,
878+}; 935+};
879+ 936+
880+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
881+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
882+ SND_SOC_DAPM_LINE("Line In", NULL),
883+};
884+
885+static const char *audio_map[][3] = {
886+ {"Headphone Jack", NULL, "HPLOUT"},
887+ {"Headphone Jack", NULL, "HPROUT"},
888+
889+ {"Line In", NULL, "Line In"},
890+ {"Line In", NULL, "Line In"},
891+};
892+
893+static int omap3beagle_twl4030_init(struct snd_soc_codec *codec)
894+{
895+ int i;
896+
897+ printk(KERN_INFO "OMAP3 Beagle TWL4030 SoC init\n");
898+
899+ /* Add omap3beagle specific widgets */
900+ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++)
901+ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]);
902+
903+ /* Set up omap3beagle specific audio path audio_map */
904+ for (i = 0; i < ARRAY_SIZE(audio_map); i++)
905+ snd_soc_dapm_connect_input(codec, audio_map[i][0],
906+ audio_map[i][1], audio_map[i][2]);
907+
908+ /* always connected */
909+ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
910+ snd_soc_dapm_set_endpoint(codec, "Line In", 1);
911+
912+ snd_soc_dapm_sync_endpoints(codec);
913+
914+ return 0;
915+}
916+
917+/* Digital audio interface glue - connects codec <--> CPU */ 937+/* Digital audio interface glue - connects codec <--> CPU */
918+static struct snd_soc_dai_link omap3beagle_dai = { 938+static struct snd_soc_dai_link omap3beagle_dai = {
919+ .name = "TWL4030", 939+ .name = "TWL4030",
920+ .stream_name = "TWL4030", 940+ .stream_name = "TWL4030",
921+ .cpu_dai = &omap_mcbsp_dai[0], 941+ .cpu_dai = &omap_mcbsp_dai[0],
922+ .codec_dai = &twl4030_dai, 942+ .codec_dai = &twl4030_dai,
923+ .init = omap3beagle_twl4030_init,
924+ .ops = &omap3beagle_ops, 943+ .ops = &omap3beagle_ops,
925+}; 944+};
926+ 945+
@@ -987,10 +1006,10 @@ index 0000000..fb79938
987+MODULE_LICENSE("GPL"); 1006+MODULE_LICENSE("GPL");
988diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c 1007diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
989new file mode 100644 1008new file mode 100644
990index 0000000..32d4f5d 1009index 0000000..a64c788
991--- /dev/null 1010--- /dev/null
992+++ b/sound/soc/omap/omap3evm.c 1011+++ b/sound/soc/omap/omap3evm.c
993@@ -0,0 +1,180 @@ 1012@@ -0,0 +1,142 @@
994+/* 1013+/*
995+ * omap3evm.c -- SoC audio for OMAP3 EVM 1014+ * omap3evm.c -- SoC audio for OMAP3 EVM
996+ * 1015+ *
@@ -1063,50 +1082,12 @@ index 0000000..32d4f5d
1063+ .hw_params = omap3evm_hw_params, 1082+ .hw_params = omap3evm_hw_params,
1064+}; 1083+};
1065+ 1084+
1066+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1067+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
1068+ SND_SOC_DAPM_LINE("Line In", NULL),
1069+};
1070+
1071+static const char *audio_map[][3] = {
1072+ {"Headphone Jack", NULL, "HPLOUT"},
1073+ {"Headphone Jack", NULL, "HPROUT"},
1074+
1075+ {"Line In", NULL, "Line In"},
1076+ {"Line In", NULL, "Line In"},
1077+};
1078+
1079+static int omap3evm_twl4030_init(struct snd_soc_codec *codec)
1080+{
1081+ int i;
1082+
1083+ printk(KERN_INFO "OMAP3 EVM TWL4030 SoC init\n");
1084+
1085+ /* Add omap3evm specific widgets */
1086+ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++)
1087+ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]);
1088+
1089+ /* Set up omap3evm specific audio path audio_map */
1090+ for (i = 0; i < ARRAY_SIZE(audio_map); i++)
1091+ snd_soc_dapm_connect_input(codec, audio_map[i][0],
1092+ audio_map[i][1], audio_map[i][2]);
1093+
1094+ /* always connected */
1095+ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
1096+ snd_soc_dapm_set_endpoint(codec, "Line In", 1);
1097+
1098+ snd_soc_dapm_sync_endpoints(codec);
1099+
1100+ return 0;
1101+}
1102+
1103+/* Digital audio interface glue - connects codec <--> CPU */ 1085+/* Digital audio interface glue - connects codec <--> CPU */
1104+static struct snd_soc_dai_link omap3evm_dai = { 1086+static struct snd_soc_dai_link omap3evm_dai = {
1105+ .name = "TWL4030", 1087+ .name = "TWL4030",
1106+ .stream_name = "TWL4030", 1088+ .stream_name = "TWL4030",
1107+ .cpu_dai = &omap_mcbsp_dai[0], 1089+ .cpu_dai = &omap_mcbsp_dai[0],
1108+ .codec_dai = &twl4030_dai, 1090+ .codec_dai = &twl4030_dai,
1109+ .init = omap3evm_twl4030_init,
1110+ .ops = &omap3evm_ops, 1091+ .ops = &omap3evm_ops,
1111+}; 1092+};
1112+ 1093+
diff --git a/meta/packages/linux/linux-omap2-git/fixes.patch b/meta/packages/linux/linux-omap2-git/fixes.patch
new file mode 100644
index 0000000000..8478682787
--- /dev/null
+++ b/meta/packages/linux/linux-omap2-git/fixes.patch
@@ -0,0 +1,25 @@
1Index: git/include/asm-arm/processor.h
2===================================================================
3--- git.orig/include/asm-arm/processor.h 2008-08-03 11:27:02.000000000 +0100
4+++ git/include/asm-arm/processor.h 2008-08-03 11:53:22.000000000 +0100
5@@ -109,14 +109,16 @@
6 #if __LINUX_ARM_ARCH__ >= 5
7
8 #define ARCH_HAS_PREFETCH
9-static inline void prefetch(const void *ptr)
10+#define prefetch(ptr) __builtin_prefetch(ptr)
11+
12+/*static inline void prefetch(const void *ptr)
13 {
14 __asm__ __volatile__(
15- "pld\t%0"
16+ "pld\ta%0"
17 :
18- : "o" (*(char *)ptr)
19+ : "p" (ptr)
20 : "cc");
21-}
22+}*/
23
24 #define ARCH_HAS_PREFETCHW
25 #define prefetchw(ptr) prefetch(ptr)
diff --git a/meta/packages/linux/linux-omap2_git.bb b/meta/packages/linux/linux-omap2_git.bb
index c4d67f553c..983678aaad 100644
--- a/meta/packages/linux/linux-omap2_git.bb
+++ b/meta/packages/linux/linux-omap2_git.bb
@@ -1,13 +1,15 @@
1require linux-omap2.inc 1require linux-omap2.inc
2 2
3FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MACHINE}" 3FILESPATH = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MACHINE}:${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git"
4 4
5SRCREV = "c32c81d59d2d8a66e63f82c9732db256d302068e" 5SRCREV = "d3b3ae0fe6c71641da19c8de466ec366d39847e3"
6 6
7PV = "2.6.25+2.6.26-rc8+${PR}+git${SRCREV}" 7PV = "2.6.26"
8PR = "r38" 8#PV = "2.6.25+2.6.26-rc9+${PR}+git${SRCREV}"
9PR = "r49"
9 10
10SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ 11SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \
12 file://fixes.patch;patch=1 \
11 file://defconfig" 13 file://defconfig"
12 14
13SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \ 15SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \
@@ -21,6 +23,29 @@ SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \
21 file://no-empty-flash-warnings.patch;patch=1 \ 23 file://no-empty-flash-warnings.patch;patch=1 \
22 file://logo_linux_clut224.ppm \ 24 file://logo_linux_clut224.ppm \
23 file://oprofile-0.9.3.armv7.diff;patch=1 \ 25 file://oprofile-0.9.3.armv7.diff;patch=1 \
26 file://01-fix-timing-print.diff;patch=1 \
27 file://03-enable-overlay-opt.diff;patch=1 \
28 file://04-use-pcd.diff;patch=1 \
29 file://05-fix-display-panning.diff;patch=1 \
30 file://06-ensure-fclk.diff;patch=1 \
31 file://07-set-burst-size.diff;patch=1 \
32 file://cache-display-fix.patch;patch=1 \
33 file://serialfix.diff;patch=1 \
34 file://i2c-omap-race-fix.diff;patch=1 \
35 file://TWL4030-01.patch;patch=1 \
36 file://TWL4030-02.patch;patch=1 \
37 file://TWL4030-03.patch;patch=1 \
38 file://TWL4030-04.patch;patch=1 \
39 file://TWL4030-05.patch;patch=1 \
40 file://TWL4030-06.patch;patch=1 \
41 file://TWL4030-07.patch;patch=1 \
42 file://TWL4030-08.patch;patch=1 \
43 file://TWL4030-09.patch;patch=1 \
44 file://mru-clocks1.diff;patch=1 \
45 file://mru-clocks2.diff;patch=1 \
46 file://mru-clocks3.diff;patch=1 \
47 file://4bitmmc.diff;patch=1 \
48 file://400khz-i2c.diff;patch=1 \
24" 49"
25 50
26SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \ 51SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-10 01:41:49 +0000