diff options
author | Jialing Zhang <zhangjialing@loongson.cn> | 2023-03-22 09:34:03 +0800 |
---|---|---|
committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2023-03-23 22:36:46 +0000 |
commit | 46186808bd614968ae8f4cec864bcdfbe9dfac86 (patch) | |
tree | de201191dc52797ea4db7f851ec3ae9ae3d2a9ee /meta/classes-recipe/rust-target-config.bbclass | |
parent | 23212c8c44315ed6612009e0e667d14ad26459b0 (diff) | |
download | poky-46186808bd614968ae8f4cec864bcdfbe9dfac86.tar.gz |
class-recipe: add support for loongarch64
(From OE-Core rev: ec88f703f753efcbad5c077d866a5dc44ad54db0)
Signed-off-by: Jialing Zhang <zhangjialing@loongson.cn>
Signed-off-by: Qizheng Zhu <zhuqizheng@loongson.cn>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/classes-recipe/rust-target-config.bbclass')
-rw-r--r-- | meta/classes-recipe/rust-target-config.bbclass | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/meta/classes-recipe/rust-target-config.bbclass b/meta/classes-recipe/rust-target-config.bbclass index 5e71546fee..21a56ede3e 100644 --- a/meta/classes-recipe/rust-target-config.bbclass +++ b/meta/classes-recipe/rust-target-config.bbclass | |||
@@ -245,6 +245,14 @@ TARGET_POINTER_WIDTH[riscv64gc] = "64" | |||
245 | TARGET_C_INT_WIDTH[riscv64gc] = "64" | 245 | TARGET_C_INT_WIDTH[riscv64gc] = "64" |
246 | MAX_ATOMIC_WIDTH[riscv64gc] = "64" | 246 | MAX_ATOMIC_WIDTH[riscv64gc] = "64" |
247 | 247 | ||
248 | ## loongarch64-unknown-linux-{gnu, musl} | ||
249 | DATA_LAYOUT[loongarch64] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" | ||
250 | TARGET_ENDIAN[loongarch64] = "little" | ||
251 | TARGET_POINTER_WIDTH[loongarch64] = "64" | ||
252 | TARGET_C_INT_WIDTH[loongarch64] = "32" | ||
253 | MAX_ATOMIC_WIDTH[loongarch64] = "64" | ||
254 | FEATURES[loongarch64] = "+d" | ||
255 | |||
248 | # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something | 256 | # Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something |
249 | # rust's internals won't choke on. | 257 | # rust's internals won't choke on. |
250 | def arch_to_rust_target_arch(arch): | 258 | def arch_to_rust_target_arch(arch): |
@@ -288,6 +296,7 @@ def llvm_cpu(d): | |||
288 | trans['mips64el'] = "mips64" | 296 | trans['mips64el'] = "mips64" |
289 | trans['riscv64'] = "generic-rv64" | 297 | trans['riscv64'] = "generic-rv64" |
290 | trans['riscv32'] = "generic-rv32" | 298 | trans['riscv32'] = "generic-rv32" |
299 | trans['loongarch64'] = "la464" | ||
291 | 300 | ||
292 | if target in ["mips", "mipsel", "powerpc"]: | 301 | if target in ["mips", "mipsel", "powerpc"]: |
293 | feat = frozenset(d.getVar('TUNE_FEATURES').split()) | 302 | feat = frozenset(d.getVar('TUNE_FEATURES').split()) |
@@ -367,6 +376,8 @@ def rust_gen_target(d, thing, wd, arch): | |||
367 | tspec['llvm-abiname'] = "lp64d" | 376 | tspec['llvm-abiname'] = "lp64d" |
368 | if "riscv32" in tspec['llvm-target']: | 377 | if "riscv32" in tspec['llvm-target']: |
369 | tspec['llvm-abiname'] = "ilp32d" | 378 | tspec['llvm-abiname'] = "ilp32d" |
379 | if "loongarch64" in tspec['llvm-target']: | ||
380 | tspec['llvm-abiname'] = "lp64d" | ||
370 | tspec['vendor'] = "unknown" | 381 | tspec['vendor'] = "unknown" |
371 | tspec['target-family'] = "unix" | 382 | tspec['target-family'] = "unix" |
372 | tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix) | 383 | tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix) |