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| author | Bruce Ashfield <bruce.ashfield@windriver.com> | 2015-05-15 14:01:00 -0400 |
|---|---|---|
| committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2015-05-24 07:19:18 +0100 |
| commit | be1442e78ef96fc9fa4873fd3bad36771849574d (patch) | |
| tree | 6ea886ca4eb6f13c346868e4c00619d1b94ff108 /meta-skeleton/recipes-kernel | |
| parent | 03abfcb0341c93736b782781c1c2562c4c5e5e4b (diff) | |
| download | poky-be1442e78ef96fc9fa4873fd3bad36771849574d.tar.gz | |
linux-yocto/3.19: Braswell DRM fixes
Updating the 3.19 kernel SRCREVs to integrate the following Braswell
changes:
374b5d0e09ea drm/i915: Only wait for required lanes in vlv_wait_port_ready()
fca99e8ee111 Revert "drm/i915: Hack to tie both common lanes together on chv"
00682f31b612 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
654b1a4497c5 drm/i915: Implement chv display PHY lane stagger setup
(From OE-Core rev: 211b631b0d7bf4df3152f4d8d626d798d023d512)
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta-skeleton/recipes-kernel')
0 files changed, 0 insertions, 0 deletions