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authorRichard Purdie <rpurdie@linux.intel.com>2009-01-16 15:37:55 +0000
committerRichard Purdie <rpurdie@linux.intel.com>2009-01-29 13:44:58 +0000
commit514aa592cd3c569e4033d7c64bc12dfc1507a951 (patch)
treef84e81b3a3488bf3e372029b5d87ce3ae57d15c0 /meta-moblin/packages
parent4b7ef3d8b58ceb3277c5083b8941e18345ff1861 (diff)
downloadpoky-514aa592cd3c569e4033d7c64bc12dfc1507a951.tar.gz
libdrm-psb: Update to use a 2.6.27 kernel and simplify patches
Diffstat (limited to 'meta-moblin/packages')
-rw-r--r--meta-moblin/packages/drm/files/menlow-config98
-rw-r--r--meta-moblin/packages/drm/files/poulsbo.patch4050
-rw-r--r--meta-moblin/packages/drm/files/poulsbo_libdrm_update.patch63492
-rw-r--r--meta-moblin/packages/drm/libdrm-psb_2.3.1.bb17
-rw-r--r--meta-moblin/packages/drm/libdrm-psb_git.bb21
-rw-r--r--meta-moblin/packages/drm/linux-psb-modules_2.6.27.bb (renamed from meta-moblin/packages/drm/linux-psb-modules_2.6.24.bb)9
6 files changed, 4122 insertions, 63565 deletions
diff --git a/meta-moblin/packages/drm/files/menlow-config b/meta-moblin/packages/drm/files/menlow-config
index 3a699b587b..da527613f0 100644
--- a/meta-moblin/packages/drm/files/menlow-config
+++ b/meta-moblin/packages/drm/files/menlow-config
@@ -1,84 +1,84 @@
1# Ubuntu config 1# Ubuntu config
2 2
3 3
4CONFIG_BLK_DEV_GNBD=m 4# CONFIG_BLK_DEV_GNBD is not set
5 5
6# Requires some headers from drivers/md 6# Requires some headers from drivers/md
7#CONFIG_BLK_DEV_DM_BBR=m 7#CONFIG_BLK_DEV_DM_BBR=m
8 8
9CONFIG_SND_BTSCO=m 9# CONFIG_SND_BTSCO is not set
10 10
11CONFIG_INPUT_ACERHK=m 11# CONFIG_INPUT_ACERHK is not set
12CONFIG_AVERATEC_5100P=m 12# CONFIG_AVERATEC_5100P is not set
13CONFIG_PACKARDBELL_E5=m 13# CONFIG_PACKARDBELL_E5 is not set
14CONFIG_LMPCM_USB=m 14# CONFIG_LMPCM_USB is not set
15CONFIG_NOZOMI=m 15# CONFIG_NOZOMI is not set
16 16
17CONFIG_NDISWRAPPER=m 17# CONFIG_NDISWRAPPER is not set
18 CONFIG_NDISWRAPPER_WQ=y 18# CONFIG_NDISWRAPPER_WQ is not set
19 19
20#CONFIG_MOL=m 20# CONFIG_MOL is not set
21 21
22CONFIG_ASFS_FS=m 22# CONFIG_ASFS_FS is not set
23 23
24# Uses unexported functions from gfs2 24# Uses unexported functions from gfs2
25CONFIG_GFS_FS=m 25# CONFIG_GFS_FS is not set
26 26
27CONFIG_SQUASHFS=m 27# CONFIG_SQUASHFS is not set
28# CONFIG_UNION_FS is not set 28# CONFIG_UNION_FS is not set
29 29
30CONFIG_USB_APPLEIR=m 30# CONFIG_USB_APPLEIR is not set
31 31
32CONFIG_GSPCA=m 32# CONFIG_GSPCA is not set
33 33
34CONFIG_USB_OV511_NEW=m 34# CONFIG_USB_OV511_NEW is not set
35CONFIG_QUICKCAM=m 35# CONFIG_QUICKCAM is not set
36CONFIG_USB_UVCCAM=m 36# CONFIG_USB_UVCCAM is not set
37 37
38CONFIG_NET_ACX=m 38# CONFIG_NET_ACX is not set
39CONFIG_IPW3945=m 39# CONFIG_IPW3945 is not set
40CONFIG_IWLWIFI=m 40# CONFIG_IWLWIFI is not set
41CONFIG_USB_ATMEL=m 41# CONFIG_USB_ATMEL is not set
42CONFIG_PRISM2_USB=m 42# CONFIG_PRISM2_USB is not set
43 43
44 44
45CONFIG_IPW2100_FS_AMILO_M7400=m 45# CONFIG_IPW2100_FS_AMILO_M7400 is not set
46 46
47 47
48CONFIG_LIRC_DEV=m 48# CONFIG_LIRC_DEV is not set
49CONFIG_LIRC_ATIUSB=m 49# CONFIG_LIRC_ATIUSB is not set
50CONFIG_LIRC_BT829=m 50# CONFIG_LIRC_BT829 is not set
51CONFIG_LIRC_CMDIR=m 51# CONFIG_LIRC_CMDIR is not set
52#CONFIG_LIRC_GPIO=m 52# CONFIG_LIRC_GPIO is not set
53CONFIG_LIRC_I2C=m 53# CONFIG_LIRC_I2C is not set
54CONFIG_LIRC_IGORPLUGUSB=m 54# CONFIG_LIRC_IGORPLUGUSB is not set
55CONFIG_LIRC_IMON=m 55# CONFIG_LIRC_IMON is not set
56CONFIG_LIRC_IT87=m 56# CONFIG_LIRC_IT87 is not set
57CONFIG_LIRC_MCEUSB=m 57# CONFIG_LIRC_MCEUSB is not set
58CONFIG_LIRC_MCEUSB2=m 58# CONFIG_LIRC_MCEUSB2 is not set
59#CONFIG_LIRC_PARALLEL=m 59# CONFIG_LIRC_PARALLEL is not set
60CONFIG_LIRC_PVR150=m 60# CONFIG_LIRC_PVR150 is not set
61CONFIG_LIRC_SASEM=m 61# CONFIG_LIRC_SASEM is not set
62CONFIG_LIRC_SERIAL=m 62# CONFIG_LIRC_SERIAL is not set
63CONFIG_LIRC_SERIAL_IGOR=m 63# CONFIG_LIRC_SERIAL_IGOR is not set
64CONFIG_LIRC_SIR=m 64# CONFIG_LIRC_SIR is not set
65CONFIG_LIRC_STREAMZAP=m 65# CONFIG_LIRC_STREAMZAP is not set
66CONFIG_LIRC_TTUSBIR=m 66# CONFIG_LIRC_TTUSBIR is not set
67 67
68 68
69CONFIG_DRM_PSB=m 69CONFIG_DRM_PSB=m
70 70
71 71
72CONFIG_AMT_HECI=m 72# CONFIG_AMT_HECI is not set
73 73
74 74
75CONFIG_ET131X=m 75# CONFIG_ET131X is not set
76 76
77 77
78CONFIG_STK11XX=m 78# CONFIG_STK11XX is not set
79 79
80CONFIG_MMC_SD8686=m 80# CONFIG_MMC_SD8686 is not set
81CONFIG_MMC_SD8688=m 81# CONFIG_MMC_SD8688 is not set
82 82
83CONFIG_WIMAX_I2400M=m 83# CONFIG_WIMAX_I2400M is not set
84# CONFIG_DVB_SIANO_SMS1XXX is not set 84# CONFIG_DVB_SIANO_SMS1XXX is not set
diff --git a/meta-moblin/packages/drm/files/poulsbo.patch b/meta-moblin/packages/drm/files/poulsbo.patch
new file mode 100644
index 0000000000..13a16bfd74
--- /dev/null
+++ b/meta-moblin/packages/drm/files/poulsbo.patch
@@ -0,0 +1,4050 @@
1Index: libdrm-2.3.1/configure.ac
2===================================================================
3--- libdrm-2.3.1.orig/configure.ac 2008-07-01 08:50:43.000000000 +0100
4+++ libdrm-2.3.1/configure.ac 2009-01-14 18:26:59.000000000 +0000
5@@ -39,5 +39,4 @@
6 Makefile
7 libdrm/Makefile
8 shared-core/Makefile
9- tests/Makefile
10 libdrm.pc])
11Index: libdrm-2.3.1/libdrm/Makefile.am
12===================================================================
13--- libdrm-2.3.1.orig/libdrm/Makefile.am 2008-07-01 08:51:40.000000000 +0100
14+++ libdrm-2.3.1/libdrm/Makefile.am 2009-01-14 18:26:59.000000000 +0000
15@@ -23,10 +23,9 @@
16 libdrm_la_LDFLAGS = -version-number 2:3:1 -no-undefined
17
18 AM_CFLAGS = -I$(top_srcdir)/shared-core
19-libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c
20+libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c xf86drmMode.c
21
22 libdrmincludedir = ${includedir}
23-
24-libdrminclude_HEADERS = xf86drm.h
25+libdrminclude_HEADERS = xf86drm.h xf86mm.h xf86drmMode.h
26
27 EXTRA_DIST = ChangeLog TODO
28Index: libdrm-2.3.1/libdrm/xf86drm.c
29===================================================================
30--- libdrm-2.3.1.orig/libdrm/xf86drm.c 2008-07-01 08:51:40.000000000 +0100
31+++ libdrm-2.3.1/libdrm/xf86drm.c 2009-01-14 18:26:59.000000000 +0000
32@@ -2337,6 +2337,569 @@
33 return 0;
34 }
35
36+
37+/*
38+ * Valid flags are
39+ * DRM_FENCE_FLAG_EMIT
40+ * DRM_FENCE_FLAG_SHAREABLE
41+ * DRM_FENCE_MASK_DRIVER
42+ */
43+
44+int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
45+ drmFence *fence)
46+{
47+ drm_fence_arg_t arg;
48+
49+ memset(&arg, 0, sizeof(arg));
50+ arg.flags = flags;
51+ arg.type = type;
52+ arg.fence_class = fence_class;
53+
54+ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
55+ return -errno;
56+ fence->handle = arg.handle;
57+ fence->fence_class = arg.fence_class;
58+ fence->type = arg.type;
59+ fence->flags = arg.flags;
60+ fence->signaled = 0;
61+ return 0;
62+}
63+
64+/*
65+ * Valid flags are
66+ * DRM_FENCE_FLAG_SHAREABLE
67+ * DRM_FENCE_MASK_DRIVER
68+ */
69+
70+int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
71+{
72+ drm_fence_arg_t arg;
73+
74+ memset(&arg, 0, sizeof(arg));
75+ arg.flags = flags;
76+ arg.fence_class = fence_class;
77+
78+ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
79+ return -errno;
80+ fence->handle = arg.handle;
81+ fence->fence_class = arg.fence_class;
82+ fence->type = arg.type;
83+ fence->flags = arg.flags;
84+ fence->sequence = arg.sequence;
85+ fence->signaled = 0;
86+ return 0;
87+}
88+
89+int drmFenceReference(int fd, unsigned handle, drmFence *fence)
90+{
91+ drm_fence_arg_t arg;
92+
93+ memset(&arg, 0, sizeof(arg));
94+ arg.handle = handle;
95+
96+ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
97+ return -errno;
98+ fence->handle = arg.handle;
99+ fence->fence_class = arg.fence_class;
100+ fence->type = arg.type;
101+ fence->flags = arg.flags;
102+ fence->signaled = arg.signaled;
103+ return 0;
104+}
105+
106+int drmFenceUnreference(int fd, const drmFence *fence)
107+{
108+ drm_fence_arg_t arg;
109+
110+ memset(&arg, 0, sizeof(arg));
111+ arg.handle = fence->handle;
112+
113+ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
114+ return -errno;
115+ return 0;
116+}
117+
118+int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
119+{
120+ drm_fence_arg_t arg;
121+
122+ memset(&arg, 0, sizeof(arg));
123+ arg.handle = fence->handle;
124+ arg.type = flush_type;
125+
126+ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
127+ return -errno;
128+ fence->fence_class = arg.fence_class;
129+ fence->type = arg.type;
130+ fence->signaled = arg.signaled;
131+ return arg.error;
132+}
133+
134+int drmFenceUpdate(int fd, drmFence *fence)
135+{
136+ drm_fence_arg_t arg;
137+
138+ memset(&arg, 0, sizeof(arg));
139+ arg.handle = fence->handle;
140+
141+ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
142+ return -errno;
143+ fence->fence_class = arg.fence_class;
144+ fence->type = arg.type;
145+ fence->signaled = arg.signaled;
146+ return 0;
147+}
148+
149+int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
150+ int *signaled)
151+{
152+ if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
153+ ((fenceType & fence->signaled) != fenceType)) {
154+ int ret = drmFenceFlush(fd, fence, fenceType);
155+ if (ret)
156+ return ret;
157+ }
158+
159+ *signaled = ((fenceType & fence->signaled) == fenceType);
160+
161+ return 0;
162+}
163+
164+/*
165+ * Valid flags are
166+ * DRM_FENCE_FLAG_SHAREABLE
167+ * DRM_FENCE_MASK_DRIVER
168+ */
169+
170+
171+int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
172+{
173+ drm_fence_arg_t arg;
174+
175+ memset(&arg, 0, sizeof(arg));
176+ arg.fence_class = fence->fence_class;
177+ arg.flags = flags;
178+ arg.handle = fence->handle;
179+ arg.type = emit_type;
180+
181+ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
182+ return -errno;
183+ fence->fence_class = arg.fence_class;
184+ fence->type = arg.type;
185+ fence->signaled = arg.signaled;
186+ fence->sequence = arg.sequence;
187+ return 0;
188+}
189+
190+/*
191+ * Valid flags are
192+ * DRM_FENCE_FLAG_WAIT_LAZY
193+ * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
194+ */
195+
196+#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
197+
198+static unsigned long
199+drmTimeDiff(struct timeval *now, struct timeval *then)
200+{
201+ uint64_t val;
202+
203+ val = now->tv_sec - then->tv_sec;
204+ val *= 1000000LL;
205+ val += now->tv_usec;
206+ val -= then->tv_usec;
207+
208+ return (unsigned long) val;
209+}
210+
211+static int
212+drmIoctlTimeout(int fd, unsigned long request, void *argp)
213+{
214+ int haveThen = 0;
215+ struct timeval then, now;
216+ int ret;
217+
218+ do {
219+ ret = ioctl(fd, request, argp);
220+ if (ret != 0 && errno == EAGAIN) {
221+ if (!haveThen) {
222+ gettimeofday(&then, NULL);
223+ haveThen = 1;
224+ }
225+ gettimeofday(&now, NULL);
226+ }
227+ } while (ret != 0 && errno == EAGAIN &&
228+ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
229+
230+ if (ret != 0)
231+ return ((errno == EAGAIN) ? -EBUSY : -errno);
232+
233+ return 0;
234+}
235+
236+
237+
238+
239+int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
240+{
241+ drm_fence_arg_t arg;
242+ int ret;
243+
244+ if (flush_type == 0) {
245+ flush_type = fence->type;
246+ }
247+
248+ if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) {
249+ if ((flush_type & fence->signaled) == flush_type) {
250+ return 0;
251+ }
252+ }
253+
254+ memset(&arg, 0, sizeof(arg));
255+ arg.handle = fence->handle;
256+ arg.type = flush_type;
257+ arg.flags = flags;
258+
259+
260+ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
261+ if (ret)
262+ return ret;
263+
264+ fence->fence_class = arg.fence_class;
265+ fence->type = arg.type;
266+ fence->signaled = arg.signaled;
267+ return arg.error;
268+}
269+
270+static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
271+{
272+ buf->handle = rep->handle;
273+ buf->flags = rep->flags;
274+ buf->size = rep->size;
275+ buf->offset = rep->offset;
276+ buf->mapHandle = rep->arg_handle;
277+ buf->mask = rep->mask;
278+ buf->start = rep->buffer_start;
279+ buf->fenceFlags = rep->fence_flags;
280+ buf->replyFlags = rep->rep_flags;
281+ buf->pageAlignment = rep->page_alignment;
282+ buf->tileInfo = rep->tile_info;
283+ buf->hwTileStride = rep->hw_tile_stride;
284+ buf->desiredTileStride = rep->desired_tile_stride;
285+}
286+
287+
288+
289+int drmBOCreate(int fd, unsigned long size,
290+ unsigned pageAlignment, void *user_buffer,
291+ uint64_t mask,
292+ unsigned hint, drmBO *buf)
293+{
294+ struct drm_bo_create_arg arg;
295+ struct drm_bo_create_req *req = &arg.d.req;
296+ struct drm_bo_info_rep *rep = &arg.d.rep;
297+ int ret;
298+
299+ memset(buf, 0, sizeof(*buf));
300+ memset(&arg, 0, sizeof(arg));
301+ req->mask = mask;
302+ req->hint = hint;
303+ req->size = size;
304+ req->page_alignment = pageAlignment;
305+ req->buffer_start = (unsigned long) user_buffer;
306+
307+ buf->virtual = NULL;
308+
309+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
310+ if (ret)
311+ return ret;
312+
313+ drmBOCopyReply(rep, buf);
314+ buf->virtual = user_buffer;
315+ buf->mapCount = 0;
316+
317+ return 0;
318+}
319+
320+int drmBOReference(int fd, unsigned handle, drmBO *buf)
321+{
322+ struct drm_bo_reference_info_arg arg;
323+ struct drm_bo_handle_arg *req = &arg.d.req;
324+ struct drm_bo_info_rep *rep = &arg.d.rep;
325+
326+ memset(&arg, 0, sizeof(arg));
327+ req->handle = handle;
328+
329+ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
330+ return -errno;
331+
332+ drmBOCopyReply(rep, buf);
333+ buf->mapVirtual = NULL;
334+ buf->mapCount = 0;
335+ buf->virtual = NULL;
336+
337+ return 0;
338+}
339+
340+int drmBOUnreference(int fd, drmBO *buf)
341+{
342+ struct drm_bo_handle_arg arg;
343+
344+ if (buf->mapVirtual && buf->mapHandle) {
345+ (void) munmap(buf->mapVirtual, buf->start + buf->size);
346+ buf->mapVirtual = NULL;
347+ buf->virtual = NULL;
348+ }
349+
350+ memset(&arg, 0, sizeof(arg));
351+ arg.handle = buf->handle;
352+
353+ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
354+ return -errno;
355+
356+ buf->handle = 0;
357+ return 0;
358+}
359+
360+
361+/*
362+ * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
363+ * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
364+ * call return an -EBUSY if it can' immediately honor the mapping request.
365+ */
366+
367+int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
368+ void **address)
369+{
370+ struct drm_bo_map_wait_idle_arg arg;
371+ struct drm_bo_info_req *req = &arg.d.req;
372+ struct drm_bo_info_rep *rep = &arg.d.rep;
373+ int ret = 0;
374+
375+ /*
376+ * Make sure we have a virtual address of the buffer.
377+ */
378+
379+ if (!buf->virtual) {
380+ drmAddress virtual;
381+ virtual = mmap(0, buf->size + buf->start,
382+ PROT_READ | PROT_WRITE, MAP_SHARED,
383+ fd, buf->mapHandle);
384+ if (virtual == MAP_FAILED) {
385+ ret = -errno;
386+ }
387+ if (ret)
388+ return ret;
389+ buf->mapVirtual = virtual;
390+ buf->virtual = ((char *) virtual) + buf->start;
391+ }
392+
393+ memset(&arg, 0, sizeof(arg));
394+ req->handle = buf->handle;
395+ req->mask = mapFlags;
396+ req->hint = mapHint;
397+
398+ /*
399+ * May hang if the buffer object is busy.
400+ * This IOCTL synchronizes the buffer.
401+ */
402+
403+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
404+ if (ret)
405+ return ret;
406+
407+ drmBOCopyReply(rep, buf);
408+ buf->mapFlags = mapFlags;
409+ ++buf->mapCount;
410+ *address = buf->virtual;
411+
412+ return 0;
413+}
414+
415+
416+int drmBOUnmap(int fd, drmBO *buf)
417+{
418+ struct drm_bo_handle_arg arg;
419+
420+ memset(&arg, 0, sizeof(arg));
421+ arg.handle = buf->handle;
422+
423+ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
424+ return -errno;
425+ }
426+ buf->mapCount--;
427+ return 0;
428+}
429+
430+int drmBOSetStatus(int fd, drmBO *buf,
431+ uint64_t flags, uint64_t mask,
432+ unsigned int hint,
433+ unsigned int desired_tile_stride,
434+ unsigned int tile_info)
435+{
436+
437+ struct drm_bo_map_wait_idle_arg arg;
438+ struct drm_bo_info_req *req = &arg.d.req;
439+ struct drm_bo_info_rep *rep = &arg.d.rep;
440+ int ret = 0;
441+
442+ memset(&arg, 0, sizeof(arg));
443+ req->mask = mask;
444+ req->flags = flags;
445+ req->handle = buf->handle;
446+ req->hint = hint;
447+ req->desired_tile_stride = desired_tile_stride;
448+ req->tile_info = tile_info;
449+
450+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
451+ if (ret)
452+ return ret;
453+
454+ drmBOCopyReply(rep, buf);
455+ return 0;
456+}
457+
458+
459+int drmBOInfo(int fd, drmBO *buf)
460+{
461+ struct drm_bo_reference_info_arg arg;
462+ struct drm_bo_handle_arg *req = &arg.d.req;
463+ struct drm_bo_info_rep *rep = &arg.d.rep;
464+ int ret = 0;
465+
466+ memset(&arg, 0, sizeof(arg));
467+ req->handle = buf->handle;
468+
469+ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
470+ if (ret)
471+ return -errno;
472+
473+ drmBOCopyReply(rep, buf);
474+ return 0;
475+}
476+
477+int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
478+{
479+ struct drm_bo_map_wait_idle_arg arg;
480+ struct drm_bo_info_req *req = &arg.d.req;
481+ struct drm_bo_info_rep *rep = &arg.d.rep;
482+ int ret = 0;
483+
484+ if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
485+ (buf->replyFlags & DRM_BO_REP_BUSY)) {
486+ memset(&arg, 0, sizeof(arg));
487+ req->handle = buf->handle;
488+ req->hint = hint;
489+
490+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
491+ if (ret)
492+ return ret;
493+
494+ drmBOCopyReply(rep, buf);
495+ }
496+ return 0;
497+}
498+
499+int drmBOBusy(int fd, drmBO *buf, int *busy)
500+{
501+ if (!(buf->flags & DRM_BO_FLAG_SHAREABLE) &&
502+ !(buf->replyFlags & DRM_BO_REP_BUSY)) {
503+ *busy = 0;
504+ return 0;
505+ }
506+ else {
507+ int ret = drmBOInfo(fd, buf);
508+ if (ret)
509+ return ret;
510+ *busy = (buf->replyFlags & DRM_BO_REP_BUSY);
511+ return 0;
512+ }
513+}
514+
515+int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
516+ unsigned memType)
517+{
518+ struct drm_mm_init_arg arg;
519+
520+ memset(&arg, 0, sizeof(arg));
521+
522+ arg.magic = DRM_BO_INIT_MAGIC;
523+ arg.major = DRM_BO_INIT_MAJOR;
524+ arg.minor = DRM_BO_INIT_MINOR;
525+ arg.p_offset = pOffset;
526+ arg.p_size = pSize;
527+ arg.mem_type = memType;
528+
529+ if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
530+ return -errno;
531+ return 0;
532+}
533+
534+int drmMMTakedown(int fd, unsigned memType)
535+{
536+ struct drm_mm_type_arg arg;
537+
538+ memset(&arg, 0, sizeof(arg));
539+ arg.mem_type = memType;
540+
541+ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
542+ return -errno;
543+ return 0;
544+}
545+
546+/*
547+ * If this function returns an error, and lockBM was set to 1,
548+ * the buffer manager is NOT locked.
549+ */
550+
551+int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
552+{
553+ struct drm_mm_type_arg arg;
554+
555+ memset(&arg, 0, sizeof(arg));
556+ arg.mem_type = memType;
557+ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
558+ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
559+
560+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
561+}
562+
563+int drmMMUnlock(int fd, unsigned memType, int unlockBM)
564+{
565+ struct drm_mm_type_arg arg;
566+
567+ memset(&arg, 0, sizeof(arg));
568+
569+ arg.mem_type = memType;
570+ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
571+
572+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
573+}
574+
575+int drmBOVersion(int fd, unsigned int *major,
576+ unsigned int *minor,
577+ unsigned int *patchlevel)
578+{
579+ struct drm_bo_version_arg arg;
580+ int ret;
581+
582+ memset(&arg, 0, sizeof(arg));
583+ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
584+ if (ret)
585+ return -errno;
586+
587+ if (major)
588+ *major = arg.major;
589+ if (minor)
590+ *minor = arg.minor;
591+ if (patchlevel)
592+ *patchlevel = arg.patchlevel;
593+
594+ return 0;
595+}
596+
597+
598+
599 #define DRM_MAX_FDS 16
600 static struct {
601 char *BusID;
602Index: libdrm-2.3.1/libdrm/xf86drm.h
603===================================================================
604--- libdrm-2.3.1.orig/libdrm/xf86drm.h 2008-07-01 08:51:40.000000000 +0100
605+++ libdrm-2.3.1/libdrm/xf86drm.h 2009-01-14 18:26:59.000000000 +0000
606@@ -658,4 +658,6 @@
607 extern int drmOpenOnce(void *unused, const char *BusID, int *newlyopened);
608 extern void drmCloseOnce(int fd);
609
610+#include "xf86mm.h"
611+
612 #endif
613Index: libdrm-2.3.1/libdrm/xf86drmMode.c
614===================================================================
615--- /dev/null 1970-01-01 00:00:00.000000000 +0000
616+++ libdrm-2.3.1/libdrm/xf86drmMode.c 2009-01-14 18:26:59.000000000 +0000
617@@ -0,0 +1,465 @@
618+/*
619+ * \file xf86drmMode.c
620+ * Header for DRM modesetting interface.
621+ *
622+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
623+ *
624+ * \par Acknowledgements:
625+ * Feb 2007, Dave Airlie <airlied@linux.ie>
626+ */
627+
628+/*
629+ * Copyright (c) <year> <copyright holders>
630+ *
631+ * Permission is hereby granted, free of charge, to any person obtaining a
632+ * copy of this software and associated documentation files (the "Software"),
633+ * to deal in the Software without restriction, including without limitation
634+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
635+ * and/or sell copies of the Software, and to permit persons to whom the
636+ * Software is furnished to do so, subject to the following conditions:
637+ *
638+ * The above copyright notice and this permission notice shall be included in
639+ * all copies or substantial portions of the Software.
640+ *
641+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
642+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
643+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
644+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
645+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
646+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
647+ * IN THE SOFTWARE.
648+ *
649+ */
650+
651+/*
652+ * TODO the types we are after are defined in diffrent headers on diffrent
653+ * platforms find which headers to include to get uint32_t
654+ */
655+#include <stdint.h>
656+
657+#include "xf86drmMode.h"
658+#include "xf86drm.h"
659+#include <drm.h>
660+#include <string.h>
661+
662+/*
663+ * Util functions
664+ */
665+
666+void* drmAllocCpy(void *array, int count, int entry_size)
667+{
668+ char *r;
669+ int i;
670+
671+ if (!count || !array || !entry_size)
672+ return 0;
673+
674+ if (!(r = drmMalloc(count*entry_size)))
675+ return 0;
676+
677+ for (i = 0; i < count; i++)
678+ memcpy(r+(entry_size*i), array+(entry_size*i), entry_size);
679+
680+ return r;
681+}
682+
683+/**
684+ * Generate crtc and output ids.
685+ *
686+ * Will generate ids starting from 1 up to count if count is greater then 0.
687+ */
688+static uint32_t* drmAllocGenerate(int count)
689+{
690+ uint32_t *r;
691+ int i;
692+
693+ if(0 <= count)
694+ return 0;
695+
696+ if (!(r = drmMalloc(count*sizeof(*r))))
697+ return 0;
698+
699+ for (i = 0; i < count; r[i] = ++i);
700+
701+ return 0;
702+}
703+
704+/*
705+ * A couple of free functions.
706+ */
707+
708+void drmModeFreeModeInfo(struct drm_mode_modeinfo *ptr)
709+{
710+ if (!ptr)
711+ return;
712+
713+ drmFree(ptr);
714+}
715+
716+void drmModeFreeResources(drmModeResPtr ptr)
717+{
718+ if (!ptr)
719+ return;
720+
721+ drmFree(ptr->modes);
722+ drmFree(ptr);
723+
724+}
725+
726+void drmModeFreeFB(drmModeFBPtr ptr)
727+{
728+ if (!ptr)
729+ return;
730+
731+ /* we might add more frees later. */
732+ drmFree(ptr);
733+}
734+
735+void drmModeFreeCrtc(drmModeCrtcPtr ptr)
736+{
737+ if (!ptr)
738+ return;
739+
740+ drmFree(ptr);
741+
742+}
743+
744+void drmModeFreeOutput(drmModeOutputPtr ptr)
745+{
746+ if (!ptr)
747+ return;
748+
749+ drmFree(ptr->modes);
750+ drmFree(ptr);
751+
752+}
753+
754+/*
755+ * ModeSetting functions.
756+ */
757+
758+drmModeResPtr drmModeGetResources(int fd)
759+{
760+ struct drm_mode_card_res res;
761+ int i;
762+ drmModeResPtr r = 0;
763+
764+ memset(&res, 0, sizeof(struct drm_mode_card_res));
765+
766+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res))
767+ return 0;
768+
769+ if (res.count_fbs)
770+ res.fb_id = drmMalloc(res.count_fbs*sizeof(uint32_t));
771+ if (res.count_crtcs)
772+ res.crtc_id = drmMalloc(res.count_crtcs*sizeof(uint32_t));
773+ if (res.count_outputs)
774+ res.output_id = drmMalloc(res.count_outputs*sizeof(uint32_t));
775+ if (res.count_modes)
776+ res.modes = drmMalloc(res.count_modes*sizeof(*res.modes));
777+
778+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) {
779+ r = NULL;
780+ goto err_allocs;
781+ }
782+
783+ /*
784+ * return
785+ */
786+
787+
788+ if (!(r = drmMalloc(sizeof(*r))))
789+ return 0;
790+
791+ r->count_fbs = res.count_fbs;
792+ r->count_crtcs = res.count_crtcs;
793+ r->count_outputs = res.count_outputs;
794+ r->count_modes = res.count_modes;
795+ /* TODO we realy should test if these allocs fails. */
796+ r->fbs = drmAllocCpy(res.fb_id, res.count_fbs, sizeof(uint32_t));
797+ r->crtcs = drmAllocCpy(res.crtc_id, res.count_crtcs, sizeof(uint32_t));
798+ r->outputs = drmAllocCpy(res.output_id, res.count_outputs, sizeof(uint32_t));
799+ r->modes = drmAllocCpy(res.modes, res.count_modes, sizeof(struct drm_mode_modeinfo));
800+
801+err_allocs:
802+ drmFree(res.fb_id);
803+ drmFree(res.crtc_id);
804+ drmFree(res.output_id);
805+ drmFree(res.modes);
806+
807+ return r;
808+}
809+
810+int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
811+ uint8_t bpp, uint32_t pitch, drmBO *bo, uint32_t *buf_id)
812+{
813+ struct drm_mode_fb_cmd f;
814+ int ret;
815+
816+ f.width = width;
817+ f.height = height;
818+ f.pitch = pitch;
819+ f.bpp = bpp;
820+ f.depth = depth;
821+ f.handle = bo->handle;
822+
823+ if (ret = ioctl(fd, DRM_IOCTL_MODE_ADDFB, &f))
824+ return ret;
825+
826+ *buf_id = f.buffer_id;
827+ return 0;
828+}
829+
830+int drmModeRmFB(int fd, uint32_t bufferId)
831+{
832+ return ioctl(fd, DRM_IOCTL_MODE_RMFB, &bufferId);
833+}
834+
835+drmModeFBPtr drmModeGetFB(int fd, uint32_t buf)
836+{
837+ struct drm_mode_fb_cmd info;
838+ drmModeFBPtr r;
839+
840+ info.buffer_id = buf;
841+
842+ if (ioctl(fd, DRM_IOCTL_MODE_GETFB, &info))
843+ return NULL;
844+
845+ if (!(r = drmMalloc(sizeof(*r))))
846+ return NULL;
847+
848+ r->buffer_id = info.buffer_id;
849+ r->width = info.width;
850+ r->height = info.height;
851+ r->pitch = info.pitch;
852+ r->bpp = info.bpp;
853+ r->handle = info.handle;
854+ r->depth = info.depth;
855+
856+ return r;
857+}
858+
859+
860+/*
861+ * Crtc functions
862+ */
863+
864+drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
865+{
866+ struct drm_mode_crtc crtc;
867+ drmModeCrtcPtr r;
868+ int i = 0;
869+
870+ crtc.count_outputs = 0;
871+ crtc.outputs = 0;
872+ crtc.count_possibles = 0;
873+ crtc.possibles = 0;
874+ crtc.crtc_id = crtcId;
875+
876+ if (ioctl(fd, DRM_IOCTL_MODE_GETCRTC, &crtc))
877+ return 0;
878+
879+ /*
880+ * return
881+ */
882+
883+ if (!(r = drmMalloc(sizeof(*r))))
884+ return 0;
885+
886+ r->crtc_id = crtc.crtc_id;
887+ r->x = crtc.x;
888+ r->y = crtc.y;
889+ r->mode = crtc.mode;
890+ r->buffer_id = crtc.fb_id;
891+ r->gamma_size = crtc.gamma_size;
892+ r->count_outputs = crtc.count_outputs;
893+ r->count_possibles = crtc.count_possibles;
894+ /* TODO we realy should test if these alloc & cpy fails. */
895+ r->outputs = crtc.outputs;
896+ r->possibles = crtc.possibles;
897+
898+ return r;
899+
900+err_allocs:
901+
902+ return 0;
903+}
904+
905+
906+int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
907+ uint32_t x, uint32_t y, uint32_t modeId,
908+ uint32_t *outputs, int count)
909+{
910+ struct drm_mode_crtc crtc;
911+
912+ crtc.count_outputs = 0;
913+ crtc.outputs = 0;
914+ crtc.count_possibles = 0;
915+ crtc.possibles = 0;
916+
917+ crtc.x = x;
918+ crtc.y = y;
919+ crtc.crtc_id = crtcId;
920+ crtc.fb_id = bufferId;
921+ crtc.set_outputs = outputs;
922+ crtc.count_outputs = count;
923+ crtc.mode = modeId;
924+
925+ return ioctl(fd, DRM_IOCTL_MODE_SETCRTC, &crtc);
926+}
927+
928+
929+/*
930+ * Output manipulation
931+ */
932+
933+drmModeOutputPtr drmModeGetOutput(int fd, uint32_t output_id)
934+{
935+ struct drm_mode_get_output out;
936+ drmModeOutputPtr r = NULL;
937+
938+ out.output = output_id;
939+ out.count_crtcs = 0;
940+ out.crtcs = 0;
941+ out.count_clones = 0;
942+ out.clones = 0;
943+ out.count_modes = 0;
944+ out.modes = 0;
945+ out.count_props = 0;
946+ out.props = NULL;
947+ out.prop_values = NULL;
948+
949+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
950+ return 0;
951+
952+ if (out.count_props) {
953+ out.props = drmMalloc(out.count_props*sizeof(uint32_t));
954+ out.prop_values = drmMalloc(out.count_props*sizeof(uint32_t));
955+ }
956+
957+ if (out.count_modes)
958+ out.modes = drmMalloc(out.count_modes*sizeof(uint32_t));
959+
960+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
961+ goto err_allocs;
962+
963+ if(!(r = drmMalloc(sizeof(*r)))) {
964+ goto err_allocs;
965+ }
966+
967+ r->output_id = out.output;
968+ r->crtc = out.crtc;
969+ r->connection = out.connection;
970+ r->mmWidth = out.mm_width;
971+ r->mmHeight = out.mm_height;
972+ r->subpixel = out.subpixel;
973+ r->count_crtcs = out.count_crtcs;
974+ r->count_clones = out.count_clones;
975+ r->count_modes = out.count_modes;
976+ /* TODO we should test if these alloc & cpy fails. */
977+ r->crtcs = out.crtcs;
978+ r->clones = out.clones;
979+ r->count_props = out.count_props;
980+ r->props = drmAllocCpy(out.props, out.count_props, sizeof(uint32_t));
981+ r->prop_values = drmAllocCpy(out.prop_values, out.count_props, sizeof(uint32_t));
982+ r->modes = drmAllocCpy(out.modes, out.count_modes, sizeof(uint32_t));
983+ strncpy(r->name, out.name, DRM_OUTPUT_NAME_LEN);
984+ r->name[DRM_OUTPUT_NAME_LEN-1] = 0;
985+
986+err_allocs:
987+ drmFree(out.prop_values);
988+ drmFree(out.props);
989+ drmFree(out.modes);
990+
991+ return r;
992+}
993+
994+uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *mode_info)
995+{
996+ if (ioctl(fd, DRM_IOCTL_MODE_ADDMODE, mode_info))
997+ return 0;
998+
999+ return mode_info->id;
1000+}
1001+
1002+int drmModeRmMode(int fd, uint32_t mode_id)
1003+{
1004+ return ioctl(fd, DRM_IOCTL_MODE_RMMODE, &mode_id);
1005+}
1006+
1007+int drmModeAttachMode(int fd, uint32_t output_id, uint32_t mode_id)
1008+{
1009+
1010+ struct drm_mode_mode_cmd res;
1011+
1012+ res.output_id = output_id;
1013+ res.mode_id = mode_id;
1014+
1015+ return ioctl(fd, DRM_IOCTL_MODE_ATTACHMODE, &res);
1016+}
1017+
1018+int drmModeDetachMode(int fd, uint32_t output_id, uint32_t mode_id)
1019+{
1020+ struct drm_mode_mode_cmd res;
1021+
1022+ res.output_id = output_id;
1023+ res.mode_id = mode_id;
1024+
1025+ return ioctl(fd, DRM_IOCTL_MODE_DETACHMODE, &res);
1026+}
1027+
1028+
1029+drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id)
1030+{
1031+ struct drm_mode_get_property prop;
1032+ drmModePropertyPtr r;
1033+
1034+ prop.prop_id = property_id;
1035+ prop.count_enums = 0;
1036+ prop.count_values = 0;
1037+ prop.flags = 0;
1038+ prop.enums = NULL;
1039+ prop.values = NULL;
1040+
1041+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop))
1042+ return 0;
1043+
1044+ if (prop.count_values)
1045+ prop.values = drmMalloc(prop.count_values * sizeof(uint32_t));
1046+
1047+ if (prop.count_enums)
1048+ prop.enums = drmMalloc(prop.count_enums * sizeof(struct drm_mode_property_enum));
1049+
1050+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop)) {
1051+ r = NULL;
1052+ goto err_allocs;
1053+ }
1054+
1055+ if (!(r = drmMalloc(sizeof(*r))))
1056+ return NULL;
1057+
1058+ r->prop_id = prop.prop_id;
1059+ r->count_values = prop.count_values;
1060+ r->count_enums = prop.count_enums;
1061+
1062+ r->values = drmAllocCpy(prop.values, prop.count_values, sizeof(uint32_t));
1063+ r->enums = drmAllocCpy(prop.enums, prop.count_enums, sizeof(struct drm_mode_property_enum));
1064+ strncpy(r->name, prop.name, DRM_PROP_NAME_LEN);
1065+ r->name[DRM_PROP_NAME_LEN-1] = 0;
1066+
1067+err_allocs:
1068+ drmFree(prop.values);
1069+ drmFree(prop.enums);
1070+
1071+ return r;
1072+}
1073+
1074+void drmModeFreeProperty(drmModePropertyPtr ptr)
1075+{
1076+ if (!ptr)
1077+ return;
1078+
1079+ drmFree(ptr->values);
1080+ drmFree(ptr->enums);
1081+ drmFree(ptr);
1082+}
1083Index: libdrm-2.3.1/libdrm/xf86drmMode.h
1084===================================================================
1085--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1086+++ libdrm-2.3.1/libdrm/xf86drmMode.h 2009-01-14 18:26:59.000000000 +0000
1087@@ -0,0 +1,226 @@
1088+/*
1089+ * \file xf86drmMode.h
1090+ * Header for DRM modesetting interface.
1091+ *
1092+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
1093+ *
1094+ * \par Acknowledgements:
1095+ * Feb 2007, Dave Airlie <airlied@linux.ie>
1096+ */
1097+
1098+/*
1099+ * Copyright (c) <year> <copyright holders>
1100+ *
1101+ * Permission is hereby granted, free of charge, to any person obtaining a
1102+ * copy of this software and associated documentation files (the "Software"),
1103+ * to deal in the Software without restriction, including without limitation
1104+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1105+ * and/or sell copies of the Software, and to permit persons to whom the
1106+ * Software is furnished to do so, subject to the following conditions:
1107+ *
1108+ * The above copyright notice and this permission notice shall be included in
1109+ * all copies or substantial portions of the Software.
1110+ *
1111+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1112+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1113+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
1114+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1115+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1116+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
1117+ * IN THE SOFTWARE.
1118+ *
1119+ */
1120+
1121+#include <drm.h>
1122+#include "xf86mm.h"
1123+
1124+/*
1125+ * This is the interface for modesetting for drm.
1126+ *
1127+ * In order to use this interface you must include either <stdint.h> or another
1128+ * header defining uint32_t, int32_t and uint16_t.
1129+ *
1130+ * It aims to provide a randr1.2 compatible interface for modesettings in the
1131+ * kernel, the interface is also ment to be used by libraries like EGL.
1132+ *
1133+ * More information can be found in randrproto.txt which can be found here:
1134+ * http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git
1135+ *
1136+ * There are some major diffrences to be noted. Unlike the randr1.2 proto you
1137+ * need to create the memory object of the framebuffer yourself with the ttm
1138+ * buffer object interface. This object needs to be pinned.
1139+ */
1140+
1141+
1142+typedef struct _drmModeRes {
1143+
1144+ int count_fbs;
1145+ uint32_t *fbs;
1146+
1147+ int count_crtcs;
1148+ uint32_t *crtcs;
1149+
1150+ int count_outputs;
1151+ uint32_t *outputs;
1152+
1153+ int count_modes;
1154+ struct drm_mode_modeinfo *modes;
1155+
1156+} drmModeRes, *drmModeResPtr;
1157+
1158+typedef struct drm_mode_fb_cmd drmModeFB, *drmModeFBPtr;
1159+
1160+typedef struct _drmModeProperty {
1161+ unsigned int prop_id;
1162+ unsigned int flags;
1163+ unsigned char name[DRM_PROP_NAME_LEN];
1164+ int count_values;
1165+ uint32_t *values;
1166+ int count_enums;
1167+ struct drm_mode_property_enum *enums;
1168+
1169+} drmModePropertyRes, *drmModePropertyPtr;
1170+
1171+typedef struct _drmModeCrtc {
1172+ unsigned int crtc_id;
1173+ unsigned int buffer_id; /**< FB id to connect to 0 = disconnect*/
1174+
1175+ uint32_t x, y; /**< Position on the frameuffer */
1176+ uint32_t width, height;
1177+ uint32_t mode; /**< Current mode used */
1178+
1179+ int count_outputs;
1180+ uint32_t outputs; /**< Outputs that are connected */
1181+
1182+ int count_possibles;
1183+ uint32_t possibles; /**< Outputs that can be connected */
1184+
1185+ int gamma_size; /**< Number of gamma stops */
1186+
1187+} drmModeCrtc, *drmModeCrtcPtr;
1188+
1189+typedef enum {
1190+ DRM_MODE_CONNECTED = 1,
1191+ DRM_MODE_DISCONNECTED = 2,
1192+ DRM_MODE_UNKNOWNCONNECTION = 3
1193+} drmModeConnection;
1194+
1195+typedef enum {
1196+ DRM_MODE_SUBPIXEL_UNKNOWN = 1,
1197+ DRM_MODE_SUBPIXEL_HORIZONTAL_RGB = 2,
1198+ DRM_MODE_SUBPIXEL_HORIZONTAL_BGR = 3,
1199+ DRM_MODE_SUBPIXEL_VERTICAL_RGB = 4,
1200+ DRM_MODE_SUBPIXEL_VERTICAL_BGR = 5,
1201+ DRM_MODE_SUBPIXEL_NONE = 6
1202+} drmModeSubPixel;
1203+
1204+typedef struct _drmModeOutput {
1205+ unsigned int output_id;
1206+
1207+ unsigned int crtc; /**< Crtc currently connected to */
1208+ unsigned char name[DRM_OUTPUT_NAME_LEN];
1209+ drmModeConnection connection;
1210+ uint32_t mmWidth, mmHeight; /**< HxW in millimeters */
1211+ drmModeSubPixel subpixel;
1212+
1213+ int count_crtcs;
1214+ uint32_t crtcs; /**< Possible crtc to connect to */
1215+
1216+ int count_clones;
1217+ uint32_t clones; /**< Mask of clones */
1218+
1219+ int count_modes;
1220+ uint32_t *modes; /**< List of modes ids */
1221+
1222+ int count_props;
1223+ uint32_t *props; /**< List of property ids */
1224+ uint32_t *prop_values; /**< List of property values */
1225+
1226+} drmModeOutput, *drmModeOutputPtr;
1227+
1228+
1229+
1230+extern void drmModeFreeModeInfo( struct drm_mode_modeinfo *ptr );
1231+extern void drmModeFreeResources( drmModeResPtr ptr );
1232+extern void drmModeFreeFB( drmModeFBPtr ptr );
1233+extern void drmModeFreeCrtc( drmModeCrtcPtr ptr );
1234+extern void drmModeFreeOutput( drmModeOutputPtr ptr );
1235+
1236+/**
1237+ * Retrives all of the resources associated with a card.
1238+ */
1239+extern drmModeResPtr drmModeGetResources(int fd);
1240+
1241+
1242+/*
1243+ * FrameBuffer manipulation.
1244+ */
1245+
1246+/**
1247+ * Retrive information about framebuffer bufferId
1248+ */
1249+extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId);
1250+
1251+/**
1252+ * Creates a new framebuffer with an buffer object as its scanout buffer.
1253+ */
1254+extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
1255+ uint8_t bpp, uint32_t pitch, drmBO *bo,
1256+ uint32_t *buf_id);
1257+/**
1258+ * Destroies the given framebuffer.
1259+ */
1260+extern int drmModeRmFB(int fd, uint32_t bufferId);
1261+
1262+
1263+/*
1264+ * Crtc functions
1265+ */
1266+
1267+/**
1268+ * Retrive information about the ctrt crtcId
1269+ */
1270+extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId);
1271+
1272+/**
1273+ * Set the mode on a crtc crtcId with the given mode modeId.
1274+ */
1275+extern int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
1276+ uint32_t x, uint32_t y, uint32_t modeId,
1277+ uint32_t *outputs, int count);
1278+
1279+
1280+/*
1281+ * Output manipulation
1282+ */
1283+
1284+/**
1285+ * Retrive information about the output outputId.
1286+ */
1287+extern drmModeOutputPtr drmModeGetOutput(int fd,
1288+ uint32_t outputId);
1289+
1290+/**
1291+ * Adds a new mode from the given mode info.
1292+ * Name must be unique.
1293+ */
1294+extern uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *modeInfo);
1295+
1296+/**
1297+ * Removes a mode created with AddMode, must be unused.
1298+ */
1299+extern int drmModeRmMode(int fd, uint32_t modeId);
1300+
1301+/**
1302+ * Attaches the given mode to an output.
1303+ */
1304+extern int drmModeAttachMode(int fd, uint32_t outputId, uint32_t modeId);
1305+
1306+/**
1307+ * Detaches a mode from the output
1308+ * must be unused, by the given mode.
1309+ */
1310+extern int drmModeDetachMode(int fd, uint32_t outputId, uint32_t modeId);
1311+
1312+extern drmModePropertyPtr drmModeGetProperty(int fd, uint32_t propertyId);
1313+extern void drmModeFreeProperty(drmModePropertyPtr ptr);
1314Index: libdrm-2.3.1/libdrm/xf86mm.h
1315===================================================================
1316--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1317+++ libdrm-2.3.1/libdrm/xf86mm.h 2009-01-14 18:26:59.000000000 +0000
1318@@ -0,0 +1,185 @@
1319+/**************************************************************************
1320+ *
1321+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA.
1322+ * All Rights Reserved.
1323+ *
1324+ * Permission is hereby granted, free of charge, to any person obtaining a
1325+ * copy of this software and associated documentation files (the
1326+ * "Software"), to deal in the Software without restriction, including
1327+ * without limitation the rights to use, copy, modify, merge, publish,
1328+ * distribute, sub license, and/or sell copies of the Software, and to
1329+ * permit persons to whom the Software is furnished to do so, subject to
1330+ * the following conditions:
1331+ *
1332+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1333+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1334+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
1335+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
1336+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
1337+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
1338+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
1339+ *
1340+ * The above copyright notice and this permission notice (including the
1341+ * next paragraph) shall be included in all copies or substantial portions
1342+ * of the Software.
1343+ *
1344+ *
1345+ **************************************************************************/
1346+
1347+#ifndef _XF86MM_H_
1348+#define _XF86MM_H_
1349+#include <stddef.h>
1350+#include <stdint.h>
1351+#include "drm.h"
1352+
1353+/*
1354+ * Note on multithreaded applications using this interface.
1355+ * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to
1356+ * be protected using an external mutex.
1357+ *
1358+ * Note: Don't protect the following functions, as it may lead to deadlocks:
1359+ * drmBOUnmap().
1360+ * The kernel is synchronizing and refcounting buffer maps.
1361+ * User space only needs to refcount object usage within the same application.
1362+ */
1363+
1364+
1365+/*
1366+ * List macros heavily inspired by the Linux kernel
1367+ * list handling. No list looping yet.
1368+ */
1369+
1370+typedef struct _drmMMListHead
1371+{
1372+ struct _drmMMListHead *prev;
1373+ struct _drmMMListHead *next;
1374+} drmMMListHead;
1375+
1376+#define DRMINITLISTHEAD(__item) \
1377+ do{ \
1378+ (__item)->prev = (__item); \
1379+ (__item)->next = (__item); \
1380+ } while (0)
1381+
1382+#define DRMLISTADD(__item, __list) \
1383+ do { \
1384+ (__item)->prev = (__list); \
1385+ (__item)->next = (__list)->next; \
1386+ (__list)->next->prev = (__item); \
1387+ (__list)->next = (__item); \
1388+ } while (0)
1389+
1390+#define DRMLISTADDTAIL(__item, __list) \
1391+ do { \
1392+ (__item)->next = (__list); \
1393+ (__item)->prev = (__list)->prev; \
1394+ (__list)->prev->next = (__item); \
1395+ (__list)->prev = (__item); \
1396+ } while(0)
1397+
1398+#define DRMLISTDEL(__item) \
1399+ do { \
1400+ (__item)->prev->next = (__item)->next; \
1401+ (__item)->next->prev = (__item)->prev; \
1402+ } while(0)
1403+
1404+#define DRMLISTDELINIT(__item) \
1405+ do { \
1406+ (__item)->prev->next = (__item)->next; \
1407+ (__item)->next->prev = (__item)->prev; \
1408+ (__item)->next = (__item); \
1409+ (__item)->prev = (__item); \
1410+ } while(0)
1411+
1412+#define DRMLISTENTRY(__type, __item, __field) \
1413+ ((__type *)(((char *) (__item)) - offsetof(__type, __field)))
1414+
1415+typedef struct _drmFence
1416+{
1417+ unsigned handle;
1418+ int fence_class;
1419+ unsigned type;
1420+ unsigned flags;
1421+ unsigned signaled;
1422+ uint32_t sequence;
1423+ unsigned pad[4]; /* for future expansion */
1424+} drmFence;
1425+
1426+typedef struct _drmBO
1427+{
1428+ unsigned handle;
1429+ uint64_t mapHandle;
1430+ uint64_t flags;
1431+ uint64_t mask;
1432+ unsigned mapFlags;
1433+ unsigned long size;
1434+ unsigned long offset;
1435+ unsigned long start;
1436+ unsigned replyFlags;
1437+ unsigned fenceFlags;
1438+ unsigned pageAlignment;
1439+ unsigned tileInfo;
1440+ unsigned hwTileStride;
1441+ unsigned desiredTileStride;
1442+ void *virtual;
1443+ void *mapVirtual;
1444+ int mapCount;
1445+ unsigned pad[8]; /* for future expansion */
1446+} drmBO;
1447+
1448+/*
1449+ * Fence functions.
1450+ */
1451+
1452+extern int drmFenceCreate(int fd, unsigned flags, int fence_class,
1453+ unsigned type, drmFence *fence);
1454+extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
1455+extern int drmFenceUnreference(int fd, const drmFence *fence);
1456+extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
1457+extern int drmFenceSignaled(int fd, drmFence *fence,
1458+ unsigned fenceType, int *signaled);
1459+extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
1460+ unsigned flush_type);
1461+extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
1462+ unsigned emit_type);
1463+extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence);
1464+
1465+
1466+/*
1467+ * Buffer object functions.
1468+ */
1469+
1470+extern int drmBOCreate(int fd, unsigned long size,
1471+ unsigned pageAlignment, void *user_buffer,
1472+ uint64_t mask, unsigned hint, drmBO *buf);
1473+extern int drmBOReference(int fd, unsigned handle, drmBO *buf);
1474+extern int drmBOUnreference(int fd, drmBO *buf);
1475+extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
1476+ void **address);
1477+extern int drmBOUnmap(int fd, drmBO *buf);
1478+extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle);
1479+extern int drmBOInfo(int fd, drmBO *buf);
1480+extern int drmBOBusy(int fd, drmBO *buf, int *busy);
1481+
1482+extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint);
1483+
1484+/*
1485+ * Initialization functions.
1486+ */
1487+
1488+extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
1489+ unsigned memType);
1490+extern int drmMMTakedown(int fd, unsigned memType);
1491+extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict);
1492+extern int drmMMUnlock(int fd, unsigned memType, int unlockBM);
1493+extern int drmBOSetStatus(int fd, drmBO *buf,
1494+ uint64_t flags, uint64_t mask,
1495+ unsigned int hint,
1496+ unsigned int desired_tile_stride,
1497+ unsigned int tile_info);
1498+extern int drmBOVersion(int fd, unsigned int *major,
1499+ unsigned int *minor,
1500+ unsigned int *patchlevel);
1501+
1502+
1503+#endif
1504Index: libdrm-2.3.1/Makefile.am
1505===================================================================
1506--- libdrm-2.3.1.orig/Makefile.am 2008-07-01 08:50:43.000000000 +0100
1507+++ libdrm-2.3.1/Makefile.am 2009-01-14 18:26:59.000000000 +0000
1508@@ -22,7 +22,7 @@
1509 # here too, but let's just do libdrm for now
1510
1511 AUTOMAKE_OPTIONS = foreign
1512-SUBDIRS = libdrm shared-core tests
1513+SUBDIRS = libdrm shared-core
1514
1515 pkgconfigdir = @pkgconfigdir@
1516 pkgconfig_DATA = libdrm.pc
1517Index: libdrm-2.3.1/shared-core/drm.h
1518===================================================================
1519--- libdrm-2.3.1.orig/shared-core/drm.h 2008-07-01 08:55:17.000000000 +0100
1520+++ libdrm-2.3.1/shared-core/drm.h 2009-01-14 18:26:59.000000000 +0000
1521@@ -236,6 +236,7 @@
1522 _DRM_AGP = 3, /**< AGP/GART */
1523 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
1524 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
1525+ _DRM_TTM = 6
1526 };
1527
1528 /**
1529@@ -640,6 +641,398 @@
1530 int drm_dd_minor;
1531 };
1532
1533+
1534+#define DRM_FENCE_FLAG_EMIT 0x00000001
1535+#define DRM_FENCE_FLAG_SHAREABLE 0x00000002
1536+#define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
1537+#define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
1538+#define DRM_FENCE_FLAG_NO_USER 0x00000010
1539+
1540+/* Reserved for driver use */
1541+#define DRM_FENCE_MASK_DRIVER 0xFF000000
1542+
1543+#define DRM_FENCE_TYPE_EXE 0x00000001
1544+
1545+struct drm_fence_arg {
1546+ unsigned int handle;
1547+ unsigned int fence_class;
1548+ unsigned int type;
1549+ unsigned int flags;
1550+ unsigned int signaled;
1551+ unsigned int error;
1552+ unsigned int sequence;
1553+ unsigned int pad64;
1554+ uint64_t expand_pad[2]; /*Future expansion */
1555+};
1556+
1557+/* Buffer permissions, referring to how the GPU uses the buffers.
1558+ * these translate to fence types used for the buffers.
1559+ * Typically a texture buffer is read, A destination buffer is write and
1560+ * a command (batch-) buffer is exe. Can be or-ed together.
1561+ */
1562+
1563+#define DRM_BO_FLAG_READ (1ULL << 0)
1564+#define DRM_BO_FLAG_WRITE (1ULL << 1)
1565+#define DRM_BO_FLAG_EXE (1ULL << 2)
1566+
1567+/*
1568+ * Status flags. Can be read to determine the actual state of a buffer.
1569+ * Can also be set in the buffer mask before validation.
1570+ */
1571+
1572+/*
1573+ * Mask: Never evict this buffer. Not even with force. This type of buffer is only
1574+ * available to root and must be manually removed before buffer manager shutdown
1575+ * or lock.
1576+ * Flags: Acknowledge
1577+ */
1578+#define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
1579+
1580+/*
1581+ * Mask: Require that the buffer is placed in mappable memory when validated.
1582+ * If not set the buffer may or may not be in mappable memory when validated.
1583+ * Flags: If set, the buffer is in mappable memory.
1584+ */
1585+#define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
1586+
1587+/* Mask: The buffer should be shareable with other processes.
1588+ * Flags: The buffer is shareable with other processes.
1589+ */
1590+#define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
1591+
1592+/* Mask: If set, place the buffer in cache-coherent memory if available.
1593+ * If clear, never place the buffer in cache coherent memory if validated.
1594+ * Flags: The buffer is currently in cache-coherent memory.
1595+ */
1596+#define DRM_BO_FLAG_CACHED (1ULL << 7)
1597+
1598+/* Mask: Make sure that every time this buffer is validated,
1599+ * it ends up on the same location provided that the memory mask is the same.
1600+ * The buffer will also not be evicted when claiming space for
1601+ * other buffers. Basically a pinned buffer but it may be thrown out as
1602+ * part of buffer manager shutdown or locking.
1603+ * Flags: Acknowledge.
1604+ */
1605+#define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
1606+
1607+/* Mask: Make sure the buffer is in cached memory when mapped
1608+ * Flags: Acknowledge.
1609+ * Buffers allocated with this flag should not be used for suballocators
1610+ * This type may have issues on CPUs with over-aggressive caching
1611+ * http://marc.info/?l=linux-kernel&m=102376926732464&w=2
1612+ */
1613+#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
1614+
1615+
1616+/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
1617+ * Flags: Acknowledge.
1618+ */
1619+#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
1620+
1621+/*
1622+ * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
1623+ * Flags: Acknowledge.
1624+ */
1625+#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
1626+#define DRM_BO_FLAG_TILE (1ULL << 15)
1627+
1628+/*
1629+ * Memory type flags that can be or'ed together in the mask, but only
1630+ * one appears in flags.
1631+ */
1632+
1633+/* System memory */
1634+#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
1635+/* Translation table memory */
1636+#define DRM_BO_FLAG_MEM_TT (1ULL << 25)
1637+/* Vram memory */
1638+#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
1639+/* Up to the driver to define. */
1640+#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
1641+#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
1642+#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
1643+#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
1644+#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
1645+/* We can add more of these now with a 64-bit flag type */
1646+
1647+/* Memory flag mask */
1648+#define DRM_BO_MASK_MEM 0x00000000FF000000ULL
1649+#define DRM_BO_MASK_MEMTYPE 0x00000000FF0800A0ULL
1650+
1651+/* Driver-private flags */
1652+#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
1653+
1654+/* Don't block on validate and map */
1655+#define DRM_BO_HINT_DONT_BLOCK 0x00000002
1656+/* Don't place this buffer on the unfenced list.*/
1657+#define DRM_BO_HINT_DONT_FENCE 0x00000004
1658+#define DRM_BO_HINT_WAIT_LAZY 0x00000008
1659+
1660+#define DRM_BO_INIT_MAGIC 0xfe769812
1661+#define DRM_BO_INIT_MAJOR 1
1662+#define DRM_BO_INIT_MINOR 0
1663+#define DRM_BO_INIT_PATCH 0
1664+
1665+
1666+struct drm_bo_info_req {
1667+ uint64_t mask;
1668+ uint64_t flags;
1669+ unsigned int handle;
1670+ unsigned int hint;
1671+ unsigned int fence_class;
1672+ unsigned int desired_tile_stride;
1673+ unsigned int tile_info;
1674+ unsigned int pad64;
1675+};
1676+
1677+struct drm_bo_create_req {
1678+ uint64_t mask;
1679+ uint64_t size;
1680+ uint64_t buffer_start;
1681+ unsigned int hint;
1682+ unsigned int page_alignment;
1683+};
1684+
1685+
1686+/*
1687+ * Reply flags
1688+ */
1689+
1690+#define DRM_BO_REP_BUSY 0x00000001
1691+
1692+struct drm_bo_info_rep {
1693+ uint64_t flags;
1694+ uint64_t mask;
1695+ uint64_t size;
1696+ uint64_t offset;
1697+ uint64_t arg_handle;
1698+ uint64_t buffer_start;
1699+ unsigned int handle;
1700+ unsigned int fence_flags;
1701+ unsigned int rep_flags;
1702+ unsigned int page_alignment;
1703+ unsigned int desired_tile_stride;
1704+ unsigned int hw_tile_stride;
1705+ unsigned int tile_info;
1706+ unsigned int pad64;
1707+ uint64_t expand_pad[4]; /*Future expansion */
1708+};
1709+
1710+struct drm_bo_arg_rep {
1711+ struct drm_bo_info_rep bo_info;
1712+ int ret;
1713+ unsigned int pad64;
1714+};
1715+
1716+struct drm_bo_create_arg {
1717+ union {
1718+ struct drm_bo_create_req req;
1719+ struct drm_bo_info_rep rep;
1720+ } d;
1721+};
1722+
1723+struct drm_bo_handle_arg {
1724+ unsigned int handle;
1725+};
1726+
1727+struct drm_bo_reference_info_arg {
1728+ union {
1729+ struct drm_bo_handle_arg req;
1730+ struct drm_bo_info_rep rep;
1731+ } d;
1732+};
1733+
1734+struct drm_bo_map_wait_idle_arg {
1735+ union {
1736+ struct drm_bo_info_req req;
1737+ struct drm_bo_info_rep rep;
1738+ } d;
1739+};
1740+
1741+struct drm_bo_op_req {
1742+ enum {
1743+ drm_bo_validate,
1744+ drm_bo_fence,
1745+ drm_bo_ref_fence,
1746+ } op;
1747+ unsigned int arg_handle;
1748+ struct drm_bo_info_req bo_req;
1749+};
1750+
1751+
1752+struct drm_bo_op_arg {
1753+ uint64_t next;
1754+ union {
1755+ struct drm_bo_op_req req;
1756+ struct drm_bo_arg_rep rep;
1757+ } d;
1758+ int handled;
1759+ unsigned int pad64;
1760+};
1761+
1762+
1763+#define DRM_BO_MEM_LOCAL 0
1764+#define DRM_BO_MEM_TT 1
1765+#define DRM_BO_MEM_VRAM 2
1766+#define DRM_BO_MEM_PRIV0 3
1767+#define DRM_BO_MEM_PRIV1 4
1768+#define DRM_BO_MEM_PRIV2 5
1769+#define DRM_BO_MEM_PRIV3 6
1770+#define DRM_BO_MEM_PRIV4 7
1771+
1772+#define DRM_BO_MEM_TYPES 8 /* For now. */
1773+
1774+#define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
1775+#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
1776+
1777+struct drm_bo_version_arg {
1778+ uint32_t major;
1779+ uint32_t minor;
1780+ uint32_t patchlevel;
1781+};
1782+
1783+struct drm_mm_type_arg {
1784+ unsigned int mem_type;
1785+ unsigned int lock_flags;
1786+};
1787+
1788+struct drm_mm_init_arg {
1789+ unsigned int magic;
1790+ unsigned int major;
1791+ unsigned int minor;
1792+ unsigned int mem_type;
1793+ uint64_t p_offset;
1794+ uint64_t p_size;
1795+};
1796+
1797+/*
1798+ * Drm mode setting
1799+ */
1800+#define DRM_DISPLAY_INFO_LEN 32
1801+#define DRM_OUTPUT_NAME_LEN 32
1802+#define DRM_DISPLAY_MODE_LEN 32
1803+#define DRM_PROP_NAME_LEN 32
1804+
1805+#define DRM_MODE_TYPE_BUILTIN (1<<0)
1806+#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
1807+#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
1808+#define DRM_MODE_TYPE_PREFERRED (1<<3)
1809+#define DRM_MODE_TYPE_DEFAULT (1<<4)
1810+#define DRM_MODE_TYPE_USERDEF (1<<5)
1811+#define DRM_MODE_TYPE_DRIVER (1<<6)
1812+
1813+struct drm_mode_modeinfo {
1814+
1815+ unsigned int id;
1816+
1817+ unsigned int clock;
1818+ unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
1819+ unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
1820+
1821+ unsigned int vrefresh; /* vertical refresh * 1000 */
1822+
1823+ unsigned int flags;
1824+ unsigned int type;
1825+ char name[DRM_DISPLAY_MODE_LEN];
1826+};
1827+
1828+struct drm_mode_card_res {
1829+
1830+ int count_fbs;
1831+ unsigned int __user *fb_id;
1832+
1833+ int count_crtcs;
1834+ unsigned int __user *crtc_id;
1835+
1836+ int count_outputs;
1837+ unsigned int __user *output_id;
1838+
1839+ int count_modes;
1840+ struct drm_mode_modeinfo __user *modes;
1841+
1842+};
1843+
1844+struct drm_mode_crtc {
1845+ unsigned int crtc_id; /**< Id */
1846+ unsigned int fb_id; /**< Id of framebuffer */
1847+
1848+ int x, y; /**< Position on the frameuffer */
1849+
1850+ unsigned int mode; /**< Current mode used */
1851+
1852+ int count_outputs;
1853+ unsigned int outputs; /**< Outputs that are connected */
1854+
1855+ int count_possibles;
1856+ unsigned int possibles; /**< Outputs that can be connected */
1857+
1858+ unsigned int __user *set_outputs; /**< Outputs to be connected */
1859+
1860+ int gamma_size;
1861+
1862+};
1863+
1864+struct drm_mode_get_output {
1865+
1866+ unsigned int output; /**< Id */
1867+ unsigned int crtc; /**< Id of crtc */
1868+ unsigned char name[DRM_OUTPUT_NAME_LEN];
1869+
1870+ unsigned int connection;
1871+ unsigned int mm_width, mm_height; /**< HxW in millimeters */
1872+ unsigned int subpixel;
1873+
1874+ int count_crtcs;
1875+ unsigned int crtcs; /**< possible crtc to connect to */
1876+
1877+ int count_clones;
1878+ unsigned int clones; /**< list of clones */
1879+
1880+ int count_modes;
1881+ unsigned int __user *modes; /**< list of modes it supports */
1882+
1883+ int count_props;
1884+ unsigned int __user *props;
1885+ unsigned int __user *prop_values;
1886+};
1887+
1888+#define DRM_MODE_PROP_PENDING (1<<0)
1889+#define DRM_MODE_PROP_RANGE (1<<1)
1890+#define DRM_MODE_PROP_IMMUTABLE (1<<2)
1891+#define DRM_MODE_PROP_ENUM (1<<3) // enumerated type with text strings
1892+
1893+struct drm_mode_property_enum {
1894+ uint32_t value;
1895+ unsigned char name[DRM_PROP_NAME_LEN];
1896+};
1897+
1898+struct drm_mode_get_property {
1899+
1900+ unsigned int prop_id;
1901+ unsigned int flags;
1902+ unsigned char name[DRM_PROP_NAME_LEN];
1903+
1904+ int count_values;
1905+ uint32_t __user *values;
1906+
1907+ int count_enums;
1908+ struct drm_mode_property_enum *enums;
1909+};
1910+
1911+struct drm_mode_fb_cmd {
1912+ unsigned int buffer_id;
1913+ unsigned int width, height;
1914+ unsigned int pitch;
1915+ unsigned int bpp;
1916+ unsigned int handle;
1917+ unsigned int depth;
1918+};
1919+
1920+struct drm_mode_mode_cmd {
1921+ unsigned int output_id;
1922+ unsigned int mode_id;
1923+};
1924+
1925 /**
1926 * \name Ioctls Definitions
1927 */
1928@@ -708,6 +1101,45 @@
1929
1930 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1931
1932+#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
1933+#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
1934+#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
1935+#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
1936+
1937+#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
1938+#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
1939+#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
1940+#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
1941+#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
1942+#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
1943+#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
1944+#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
1945+
1946+#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
1947+#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
1948+#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
1949+#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
1950+#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
1951+#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
1952+#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
1953+#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1954+#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
1955+
1956+
1957+#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1958+#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
1959+#define DRM_IOCTL_MODE_GETOUTPUT DRM_IOWR(0xA2, struct drm_mode_get_output)
1960+#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
1961+#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
1962+#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
1963+#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
1964+
1965+#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
1966+#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
1967+#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
1968+#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
1969+
1970+#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property)
1971 /*@}*/
1972
1973 /**
1974@@ -763,6 +1195,10 @@
1975 typedef struct drm_scatter_gather drm_scatter_gather_t;
1976 typedef struct drm_set_version drm_set_version_t;
1977
1978+typedef struct drm_fence_arg drm_fence_arg_t;
1979+typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1980+typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1981+typedef enum drm_bo_type drm_bo_type_t;
1982 #endif
1983
1984 #endif
1985Index: libdrm-2.3.1/shared-core/i915_drm.h
1986===================================================================
1987--- libdrm-2.3.1.orig/shared-core/i915_drm.h 2008-07-01 08:51:40.000000000 +0100
1988+++ libdrm-2.3.1/shared-core/i915_drm.h 2009-01-14 18:26:59.000000000 +0000
1989@@ -138,6 +138,14 @@
1990
1991 /* Driver specific fence types and classes.
1992 */
1993+
1994+/* The only fence class we support */
1995+#define DRM_I915_FENCE_CLASS_ACCEL 0
1996+/* Fence type that guarantees read-write flush */
1997+#define DRM_I915_FENCE_TYPE_RW 2
1998+/* MI_FLUSH programmed just before the fence */
1999+#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
2000+
2001 /* Flags for perf_boxes
2002 */
2003 #define I915_BOX_RING_EMPTY 0x1
2004@@ -167,6 +175,7 @@
2005 #define DRM_I915_VBLANK_SWAP 0x0f
2006 #define DRM_I915_MMIO 0x10
2007 #define DRM_I915_HWS_ADDR 0x11
2008+#define DRM_I915_EXECBUFFER 0x12
2009
2010 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
2011 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
2012@@ -184,7 +193,7 @@
2013 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
2014 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
2015 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
2016-#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
2017+#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
2018
2019 /* Asynchronous page flipping:
2020 */
2021@@ -333,4 +342,40 @@
2022 uint64_t addr;
2023 } drm_i915_hws_addr_t;
2024
2025+/*
2026+ * Relocation header is 4 uint32_ts
2027+ * 0 - (16-bit relocation type << 16)| 16 bit reloc count
2028+ * 1 - buffer handle for another list of relocs
2029+ * 2-3 - spare.
2030+ */
2031+#define I915_RELOC_HEADER 4
2032+
2033+/*
2034+ * type 0 relocation has 4-uint32_t stride
2035+ * 0 - offset into buffer
2036+ * 1 - delta to add in
2037+ * 2 - index into buffer list
2038+ * 3 - reserved (for optimisations later).
2039+ */
2040+#define I915_RELOC_TYPE_0 0
2041+#define I915_RELOC0_STRIDE 4
2042+
2043+struct drm_i915_op_arg {
2044+ uint64_t next;
2045+ uint32_t reloc_handle;
2046+ int handled;
2047+ union {
2048+ struct drm_bo_op_req req;
2049+ struct drm_bo_arg_rep rep;
2050+ } d;
2051+
2052+};
2053+
2054+struct drm_i915_execbuffer {
2055+ uint64_t ops_list;
2056+ uint32_t num_buffers;
2057+ struct drm_i915_batchbuffer batch;
2058+ struct drm_fence_arg fence_arg;
2059+};
2060+
2061 #endif /* _I915_DRM_H_ */
2062Index: libdrm-2.3.1/shared-core/Makefile.am
2063===================================================================
2064--- libdrm-2.3.1.orig/shared-core/Makefile.am 2008-07-01 08:51:40.000000000 +0100
2065+++ libdrm-2.3.1/shared-core/Makefile.am 2009-01-14 18:26:59.000000000 +0000
2066@@ -29,10 +29,14 @@
2067 i915_drm.h \
2068 mach64_drm.h \
2069 mga_drm.h \
2070+ nouveau_drm.h \
2071+ psb_drm.h \
2072+ psb_reg.h \
2073 r128_drm.h \
2074 radeon_drm.h \
2075 savage_drm.h \
2076 sis_drm.h \
2077 via_drm.h \
2078+ psb_reg.h \
2079 r300_reg.h \
2080 via_3d_reg.h
2081Index: libdrm-2.3.1/shared-core/nouveau_drm.h
2082===================================================================
2083--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2084+++ libdrm-2.3.1/shared-core/nouveau_drm.h 2009-01-14 18:26:59.000000000 +0000
2085@@ -0,0 +1,164 @@
2086+/*
2087+ * Copyright 2005 Stephane Marchesin.
2088+ * All Rights Reserved.
2089+ *
2090+ * Permission is hereby granted, free of charge, to any person obtaining a
2091+ * copy of this software and associated documentation files (the "Software"),
2092+ * to deal in the Software without restriction, including without limitation
2093+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
2094+ * and/or sell copies of the Software, and to permit persons to whom the
2095+ * Software is furnished to do so, subject to the following conditions:
2096+ *
2097+ * The above copyright notice and this permission notice (including the next
2098+ * paragraph) shall be included in all copies or substantial portions of the
2099+ * Software.
2100+ *
2101+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2102+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2103+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
2104+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2105+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2106+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2107+ * OTHER DEALINGS IN THE SOFTWARE.
2108+ */
2109+
2110+#ifndef __NOUVEAU_DRM_H__
2111+#define __NOUVEAU_DRM_H__
2112+
2113+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 10
2114+
2115+struct drm_nouveau_channel_alloc {
2116+ uint32_t fb_ctxdma_handle;
2117+ uint32_t tt_ctxdma_handle;
2118+
2119+ int channel;
2120+ uint32_t put_base;
2121+ /* FIFO control regs */
2122+ drm_handle_t ctrl;
2123+ int ctrl_size;
2124+ /* DMA command buffer */
2125+ drm_handle_t cmdbuf;
2126+ int cmdbuf_size;
2127+ /* Notifier memory */
2128+ drm_handle_t notifier;
2129+ int notifier_size;
2130+};
2131+
2132+struct drm_nouveau_channel_free {
2133+ int channel;
2134+};
2135+
2136+struct drm_nouveau_grobj_alloc {
2137+ int channel;
2138+ uint32_t handle;
2139+ int class;
2140+};
2141+
2142+#define NOUVEAU_MEM_ACCESS_RO 1
2143+#define NOUVEAU_MEM_ACCESS_WO 2
2144+#define NOUVEAU_MEM_ACCESS_RW 3
2145+struct drm_nouveau_notifierobj_alloc {
2146+ int channel;
2147+ uint32_t handle;
2148+ int count;
2149+
2150+ uint32_t offset;
2151+};
2152+
2153+struct drm_nouveau_gpuobj_free {
2154+ int channel;
2155+ uint32_t handle;
2156+};
2157+
2158+#define NOUVEAU_MEM_FB 0x00000001
2159+#define NOUVEAU_MEM_AGP 0x00000002
2160+#define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004
2161+#define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008
2162+#define NOUVEAU_MEM_PCI 0x00000010
2163+#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020
2164+#define NOUVEAU_MEM_PINNED 0x00000040
2165+#define NOUVEAU_MEM_USER_BACKED 0x00000080
2166+#define NOUVEAU_MEM_MAPPED 0x00000100
2167+#define NOUVEAU_MEM_INSTANCE 0x00000200 /* internal */
2168+#define NOUVEAU_MEM_NOTIFIER 0x00000400 /* internal */
2169+
2170+struct drm_nouveau_mem_alloc {
2171+ int flags;
2172+ int alignment;
2173+ uint64_t size; // in bytes
2174+ uint64_t offset;
2175+ drm_handle_t map_handle;
2176+};
2177+
2178+struct drm_nouveau_mem_free {
2179+ uint64_t offset;
2180+ int flags;
2181+};
2182+
2183+/* FIXME : maybe unify {GET,SET}PARAMs */
2184+#define NOUVEAU_GETPARAM_PCI_VENDOR 3
2185+#define NOUVEAU_GETPARAM_PCI_DEVICE 4
2186+#define NOUVEAU_GETPARAM_BUS_TYPE 5
2187+#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
2188+#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
2189+#define NOUVEAU_GETPARAM_FB_SIZE 8
2190+#define NOUVEAU_GETPARAM_AGP_SIZE 9
2191+#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
2192+#define NOUVEAU_GETPARAM_CHIPSET_ID 11
2193+struct drm_nouveau_getparam {
2194+ uint64_t param;
2195+ uint64_t value;
2196+};
2197+
2198+#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
2199+#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2
2200+struct drm_nouveau_setparam {
2201+ uint64_t param;
2202+ uint64_t value;
2203+};
2204+
2205+enum nouveau_card_type {
2206+ NV_UNKNOWN =0,
2207+ NV_04 =4,
2208+ NV_05 =5,
2209+ NV_10 =10,
2210+ NV_11 =11,
2211+ NV_15 =11,
2212+ NV_17 =17,
2213+ NV_20 =20,
2214+ NV_25 =20,
2215+ NV_30 =30,
2216+ NV_34 =30,
2217+ NV_40 =40,
2218+ NV_44 =44,
2219+ NV_50 =50,
2220+ NV_LAST =0xffff,
2221+};
2222+
2223+enum nouveau_bus_type {
2224+ NV_AGP =0,
2225+ NV_PCI =1,
2226+ NV_PCIE =2,
2227+};
2228+
2229+#define NOUVEAU_MAX_SAREA_CLIPRECTS 16
2230+
2231+struct drm_nouveau_sarea {
2232+ /* the cliprects */
2233+ struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
2234+ unsigned int nbox;
2235+};
2236+
2237+#define DRM_NOUVEAU_CARD_INIT 0x00
2238+#define DRM_NOUVEAU_GETPARAM 0x01
2239+#define DRM_NOUVEAU_SETPARAM 0x02
2240+#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
2241+#define DRM_NOUVEAU_CHANNEL_FREE 0x04
2242+#define DRM_NOUVEAU_GROBJ_ALLOC 0x05
2243+#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
2244+#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
2245+#define DRM_NOUVEAU_MEM_ALLOC 0x08
2246+#define DRM_NOUVEAU_MEM_FREE 0x09
2247+
2248+#endif /* __NOUVEAU_DRM_H__ */
2249+
2250Index: libdrm-2.3.1/shared-core/psb_drm.h
2251===================================================================
2252--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2253+++ libdrm-2.3.1/shared-core/psb_drm.h 2009-01-14 18:26:59.000000000 +0000
2254@@ -0,0 +1,359 @@
2255+/**************************************************************************
2256+ * Copyright (c) 2007, Intel Corporation.
2257+ * All Rights Reserved.
2258+ *
2259+ * This program is free software; you can redistribute it and/or modify it
2260+ * under the terms and conditions of the GNU General Public License,
2261+ * version 2, as published by the Free Software Foundation.
2262+ *
2263+ * This program is distributed in the hope it will be useful, but WITHOUT
2264+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2265+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2266+ * more details.
2267+ *
2268+ * You should have received a copy of the GNU General Public License along with
2269+ * this program; if not, write to the Free Software Foundation, Inc.,
2270+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2271+ *
2272+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
2273+ * develop this driver.
2274+ *
2275+ **************************************************************************/
2276+/*
2277+ */
2278+
2279+#ifndef _PSB_DRM_H_
2280+#define _PSB_DRM_H_
2281+
2282+#if defined(__linux__) && !defined(__KERNEL__)
2283+#include<stdint.h>
2284+#endif
2285+
2286+/*
2287+ * Intel Poulsbo driver package version.
2288+ *
2289+ */
2290+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
2291+#define PSB_PACKAGE_VERSION "2.0.0.32L.0007"
2292+
2293+#define DRM_PSB_SAREA_MAJOR 0
2294+#define DRM_PSB_SAREA_MINOR 1
2295+#define PSB_FIXED_SHIFT 16
2296+
2297+/*
2298+ * Public memory types.
2299+ */
2300+
2301+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
2302+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
2303+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
2304+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
2305+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
2306+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
2307+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
2308+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
2309+#define PSB_MEM_RASTGEOM_START 0x30000000
2310+
2311+typedef int32_t psb_fixed;
2312+typedef uint32_t psb_ufixed;
2313+
2314+static inline psb_fixed psb_int_to_fixed(int a)
2315+{
2316+ return a * (1 << PSB_FIXED_SHIFT);
2317+}
2318+
2319+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
2320+{
2321+ return a << PSB_FIXED_SHIFT;
2322+}
2323+
2324+/*Status of the command sent to the gfx device.*/
2325+typedef enum {
2326+ DRM_CMD_SUCCESS,
2327+ DRM_CMD_FAILED,
2328+ DRM_CMD_HANG
2329+} drm_cmd_status_t;
2330+
2331+struct drm_psb_scanout {
2332+ uint32_t buffer_id; /* DRM buffer object ID */
2333+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
2334+ uint32_t stride; /* Buffer stride in bytes */
2335+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
2336+ uint32_t width; /* Buffer width in pixels */
2337+ uint32_t height; /* Buffer height in lines */
2338+ psb_fixed transform[3][3]; /* Buffer composite transform */
2339+ /* (scaling, rot, reflect) */
2340+};
2341+
2342+#define DRM_PSB_SAREA_OWNERS 16
2343+#define DRM_PSB_SAREA_OWNER_2D 0
2344+#define DRM_PSB_SAREA_OWNER_3D 1
2345+
2346+#define DRM_PSB_SAREA_SCANOUTS 3
2347+
2348+struct drm_psb_sarea {
2349+ /* Track changes of this data structure */
2350+
2351+ uint32_t major;
2352+ uint32_t minor;
2353+
2354+ /* Last context to touch part of hw */
2355+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
2356+
2357+ /* Definition of front- and rotated buffers */
2358+ uint32_t num_scanouts;
2359+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
2360+
2361+ int planeA_x;
2362+ int planeA_y;
2363+ int planeA_w;
2364+ int planeA_h;
2365+ int planeB_x;
2366+ int planeB_y;
2367+ int planeB_w;
2368+ int planeB_h;
2369+ uint32_t msvdx_state;
2370+ uint32_t msvdx_context;
2371+};
2372+
2373+#define PSB_RELOC_MAGIC 0x67676767
2374+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
2375+#define PSB_RELOC_SHIFT_SHIFT 0
2376+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
2377+#define PSB_RELOC_ALSHIFT_SHIFT 16
2378+
2379+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
2380+ * buffer
2381+ */
2382+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
2383+ * buffer, relative to 2D
2384+ * base address
2385+ */
2386+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
2387+ * relative to PDS base address
2388+ */
2389+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
2390+ * buffer (for tiling)
2391+ */
2392+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
2393+ * relative to base reg
2394+ */
2395+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
2396+
2397+struct drm_psb_reloc {
2398+ uint32_t reloc_op;
2399+ uint32_t where; /* offset in destination buffer */
2400+ uint32_t buffer; /* Buffer reloc applies to */
2401+ uint32_t mask; /* Destination format: */
2402+ uint32_t shift; /* Destination format: */
2403+ uint32_t pre_add; /* Destination format: */
2404+ uint32_t background; /* Destination add */
2405+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
2406+ uint32_t arg0; /* Reloc-op dependant */
2407+ uint32_t arg1;
2408+};
2409+
2410+#define PSB_BO_FLAG_TA (1ULL << 48)
2411+#define PSB_BO_FLAG_SCENE (1ULL << 49)
2412+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
2413+#define PSB_BO_FLAG_USSE (1ULL << 51)
2414+
2415+#define PSB_ENGINE_2D 0
2416+#define PSB_ENGINE_VIDEO 1
2417+#define PSB_ENGINE_RASTERIZER 2
2418+#define PSB_ENGINE_TA 3
2419+#define PSB_ENGINE_HPRAST 4
2420+
2421+/*
2422+ * For this fence class we have a couple of
2423+ * fence types.
2424+ */
2425+
2426+#define _PSB_FENCE_EXE_SHIFT 0
2427+#define _PSB_FENCE_TA_DONE_SHIFT 1
2428+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
2429+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
2430+#define _PSB_FENCE_FEEDBACK_SHIFT 4
2431+
2432+#define _PSB_ENGINE_TA_FENCE_TYPES 5
2433+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
2434+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
2435+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
2436+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
2437+
2438+#define PSB_ENGINE_HPRAST 4
2439+#define PSB_NUM_ENGINES 5
2440+
2441+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
2442+#define PSB_TA_FLAG_LASTPASS (1 << 1)
2443+
2444+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
2445+
2446+struct drm_psb_scene {
2447+ int handle_valid;
2448+ uint32_t handle;
2449+ uint32_t w;
2450+ uint32_t h;
2451+ uint32_t num_buffers;
2452+};
2453+
2454+typedef struct drm_psb_cmdbuf_arg {
2455+ uint64_t buffer_list; /* List of buffers to validate */
2456+ uint64_t clip_rects; /* See i915 counterpart */
2457+ uint64_t scene_arg;
2458+ uint64_t fence_arg;
2459+
2460+ uint32_t ta_flags;
2461+
2462+ uint32_t ta_handle; /* TA reg-value pairs */
2463+ uint32_t ta_offset;
2464+ uint32_t ta_size;
2465+
2466+ uint32_t oom_handle;
2467+ uint32_t oom_offset;
2468+ uint32_t oom_size;
2469+
2470+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
2471+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
2472+ uint32_t cmdbuf_size;
2473+
2474+ uint32_t reloc_handle; /* Reloc buffer object */
2475+ uint32_t reloc_offset;
2476+ uint32_t num_relocs;
2477+
2478+ int32_t damage; /* Damage front buffer with cliprects */
2479+ /* Not implemented yet */
2480+ uint32_t fence_flags;
2481+ uint32_t engine;
2482+
2483+ /*
2484+ * Feedback;
2485+ */
2486+
2487+ uint32_t feedback_ops;
2488+ uint32_t feedback_handle;
2489+ uint32_t feedback_offset;
2490+ uint32_t feedback_breakpoints;
2491+ uint32_t feedback_size;
2492+} drm_psb_cmdbuf_arg_t;
2493+
2494+struct drm_psb_xhw_init_arg {
2495+ uint32_t operation;
2496+ uint32_t buffer_handle;
2497+};
2498+
2499+/*
2500+ * Feedback components:
2501+ */
2502+
2503+/*
2504+ * Vistest component. The number of these in the feedback buffer
2505+ * equals the number of vistest breakpoints + 1.
2506+ * This is currently the only feedback component.
2507+ */
2508+
2509+struct drm_psb_vistest {
2510+ uint32_t vt[8];
2511+};
2512+
2513+#define PSB_HW_COOKIE_SIZE 16
2514+#define PSB_HW_FEEDBACK_SIZE 8
2515+#define PSB_HW_OOM_CMD_SIZE 6
2516+
2517+struct drm_psb_xhw_arg {
2518+ uint32_t op;
2519+ int ret;
2520+ uint32_t irq_op;
2521+ uint32_t issue_irq;
2522+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
2523+ union {
2524+ struct {
2525+ uint32_t w;
2526+ uint32_t h;
2527+ uint32_t size;
2528+ uint32_t clear_p_start;
2529+ uint32_t clear_num_pages;
2530+ } si;
2531+ struct {
2532+ uint32_t fire_flags;
2533+ uint32_t hw_context;
2534+ uint32_t offset;
2535+ uint32_t engine;
2536+ uint32_t flags;
2537+ uint32_t rca;
2538+ uint32_t num_oom_cmds;
2539+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
2540+ } sb;
2541+ struct {
2542+ uint32_t pages;
2543+ uint32_t size;
2544+ } bi;
2545+ struct {
2546+ uint32_t bca;
2547+ uint32_t rca;
2548+ uint32_t flags;
2549+ } oom;
2550+ struct {
2551+ uint32_t pt_offset;
2552+ uint32_t param_offset;
2553+ uint32_t flags;
2554+ } bl;
2555+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
2556+ } arg;
2557+};
2558+
2559+#define DRM_PSB_CMDBUF 0x00
2560+#define DRM_PSB_XHW_INIT 0x01
2561+#define DRM_PSB_XHW 0x02
2562+#define DRM_PSB_SCENE_UNREF 0x03
2563+/* Controlling the kernel modesetting buffers */
2564+#define DRM_PSB_KMS_OFF 0x04
2565+#define DRM_PSB_KMS_ON 0x05
2566+
2567+#define PSB_XHW_INIT 0x00
2568+#define PSB_XHW_TAKEDOWN 0x01
2569+
2570+#define PSB_XHW_FIRE_RASTER 0x00
2571+#define PSB_XHW_SCENE_INFO 0x01
2572+#define PSB_XHW_SCENE_BIND_FIRE 0x02
2573+#define PSB_XHW_TA_MEM_INFO 0x03
2574+#define PSB_XHW_RESET_DPM 0x04
2575+#define PSB_XHW_OOM 0x05
2576+#define PSB_XHW_TERMINATE 0x06
2577+#define PSB_XHW_VISTEST 0x07
2578+#define PSB_XHW_RESUME 0x08
2579+#define PSB_XHW_TA_MEM_LOAD 0x09
2580+
2581+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
2582+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
2583+#define PSB_SCENE_FLAG_SETUP (1 << 2)
2584+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
2585+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
2586+
2587+#define PSB_TA_MEM_FLAG_TA (1 << 0)
2588+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
2589+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
2590+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
2591+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
2592+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
2593+
2594+/*Raster fire will deallocate memory */
2595+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
2596+/*Isp reset needed due to change in ZLS format */
2597+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
2598+/*These are set by Xpsb. */
2599+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
2600+/*The task has had at least one OOM and Xpsb will
2601+ send back messages on each fire. */
2602+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
2603+
2604+#define PSB_SCENE_ENGINE_TA 0
2605+#define PSB_SCENE_ENGINE_RASTER 1
2606+#define PSB_SCENE_NUM_ENGINES 2
2607+
2608+struct drm_psb_dev_info_arg {
2609+ uint32_t num_use_attribute_registers;
2610+};
2611+#define DRM_PSB_DEVINFO 0x01
2612+
2613+#endif
2614Index: libdrm-2.3.1/shared-core/psb_drv.h
2615===================================================================
2616--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2617+++ libdrm-2.3.1/shared-core/psb_drv.h 2009-01-14 18:26:59.000000000 +0000
2618@@ -0,0 +1,786 @@
2619+/**************************************************************************
2620+ * Copyright (c) 2007, Intel Corporation.
2621+ * All Rights Reserved.
2622+ *
2623+ * This program is free software; you can redistribute it and/or modify it
2624+ * under the terms and conditions of the GNU General Public License,
2625+ * version 2, as published by the Free Software Foundation.
2626+ *
2627+ * This program is distributed in the hope it will be useful, but WITHOUT
2628+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2629+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2630+ * more details.
2631+ *
2632+ * You should have received a copy of the GNU General Public License along with
2633+ * this program; if not, write to the Free Software Foundation, Inc.,
2634+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2635+ *
2636+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
2637+ * develop this driver.
2638+ *
2639+ **************************************************************************/
2640+/*
2641+ */
2642+#ifndef _PSB_DRV_H_
2643+#define _PSB_DRV_H_
2644+
2645+#include "drmP.h"
2646+#include "psb_drm.h"
2647+#include "psb_reg.h"
2648+#include "psb_schedule.h"
2649+#include "intel_drv.h"
2650+
2651+enum {
2652+ CHIP_PSB_8108 = 0,
2653+ CHIP_PSB_8109 = 1
2654+};
2655+
2656+#define DRIVER_NAME "psb"
2657+#define DRIVER_DESC "drm driver for the Intel GMA500"
2658+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
2659+
2660+#define PSB_DRM_DRIVER_DATE "20080107"
2661+#define PSB_DRM_DRIVER_MAJOR 4
2662+#define PSB_DRM_DRIVER_MINOR 1
2663+#define PSB_DRM_DRIVER_PATCHLEVEL 0
2664+
2665+#define PSB_VDC_OFFSET 0x00000000
2666+#define PSB_VDC_SIZE 0x000080000
2667+#define PSB_SGX_SIZE 0x8000
2668+#define PSB_SGX_OFFSET 0x00040000
2669+#define PSB_MMIO_RESOURCE 0
2670+#define PSB_GATT_RESOURCE 2
2671+#define PSB_GTT_RESOURCE 3
2672+#define PSB_GMCH_CTRL 0x52
2673+#define PSB_BSM 0x5C
2674+#define _PSB_GMCH_ENABLED 0x4
2675+#define PSB_PGETBL_CTL 0x2020
2676+#define _PSB_PGETBL_ENABLED 0x00000001
2677+#define PSB_SGX_2D_SLAVE_PORT 0x4000
2678+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
2679+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
2680+#define PSB_NUM_VALIDATE_BUFFERS 640
2681+#define PSB_MEM_KERNEL_START 0x10000000
2682+#define PSB_MEM_PDS_START 0x20000000
2683+#define PSB_MEM_MMU_START 0x40000000
2684+
2685+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
2686+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
2687+
2688+/*
2689+ * Flags for external memory type field.
2690+ */
2691+
2692+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
2693+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
2694+
2695+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
2696+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
2697+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
2698+
2699+/*
2700+ * PTE's and PDE's
2701+ */
2702+
2703+#define PSB_PDE_MASK 0x003FFFFF
2704+#define PSB_PDE_SHIFT 22
2705+#define PSB_PTE_SHIFT 12
2706+
2707+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
2708+#define PSB_PTE_WO 0x0002 /* Write only */
2709+#define PSB_PTE_RO 0x0004 /* Read only */
2710+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
2711+
2712+/*
2713+ * VDC registers and bits
2714+ */
2715+#define PSB_HWSTAM 0x2098
2716+#define PSB_INSTPM 0x20C0
2717+#define PSB_INT_IDENTITY_R 0x20A4
2718+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
2719+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
2720+#define _PSB_IRQ_SGX_FLAG (1<<18)
2721+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
2722+#define PSB_INT_MASK_R 0x20A8
2723+#define PSB_INT_ENABLE_R 0x20A0
2724+#define PSB_PIPEASTAT 0x70024
2725+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
2726+#define _PSB_VBLANK_CLEAR (1 << 1)
2727+#define PSB_PIPEBSTAT 0x71024
2728+
2729+#define _PSB_MMU_ER_MASK 0x0001FF00
2730+#define _PSB_MMU_ER_HOST (1 << 16)
2731+#define GPIOA 0x5010
2732+#define GPIOB 0x5014
2733+#define GPIOC 0x5018
2734+#define GPIOD 0x501c
2735+#define GPIOE 0x5020
2736+#define GPIOF 0x5024
2737+#define GPIOG 0x5028
2738+#define GPIOH 0x502c
2739+#define GPIO_CLOCK_DIR_MASK (1 << 0)
2740+#define GPIO_CLOCK_DIR_IN (0 << 1)
2741+#define GPIO_CLOCK_DIR_OUT (1 << 1)
2742+#define GPIO_CLOCK_VAL_MASK (1 << 2)
2743+#define GPIO_CLOCK_VAL_OUT (1 << 3)
2744+#define GPIO_CLOCK_VAL_IN (1 << 4)
2745+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2746+#define GPIO_DATA_DIR_MASK (1 << 8)
2747+#define GPIO_DATA_DIR_IN (0 << 9)
2748+#define GPIO_DATA_DIR_OUT (1 << 9)
2749+#define GPIO_DATA_VAL_MASK (1 << 10)
2750+#define GPIO_DATA_VAL_OUT (1 << 11)
2751+#define GPIO_DATA_VAL_IN (1 << 12)
2752+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2753+
2754+#define VCLK_DIVISOR_VGA0 0x6000
2755+#define VCLK_DIVISOR_VGA1 0x6004
2756+#define VCLK_POST_DIV 0x6010
2757+
2758+#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
2759+#define I915_WRITE(_offs, _val) \
2760+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
2761+#define I915_READ(_offs) \
2762+ ioread32(dev_priv->vdc_reg + (_offs))
2763+
2764+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
2765+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
2766+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
2767+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
2768+#define PSB_COMM_USER_IRQ (1024 >> 2)
2769+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
2770+#define PSB_COMM_FW (2048 >> 2)
2771+
2772+#define PSB_UIRQ_VISTEST 1
2773+#define PSB_UIRQ_OOM_REPLY 2
2774+#define PSB_UIRQ_FIRE_TA_REPLY 3
2775+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
2776+
2777+#define PSB_2D_SIZE (256*1024*1024)
2778+#define PSB_MAX_RELOC_PAGES 1024
2779+
2780+#define PSB_LOW_REG_OFFS 0x0204
2781+#define PSB_HIGH_REG_OFFS 0x0600
2782+
2783+#define PSB_NUM_VBLANKS 2
2784+
2785+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
2786+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
2787+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
2788+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
2789+#define PSB_COMM_FW (2048 >> 2)
2790+
2791+#define PSB_2D_SIZE (256*1024*1024)
2792+#define PSB_MAX_RELOC_PAGES 1024
2793+
2794+#define PSB_LOW_REG_OFFS 0x0204
2795+#define PSB_HIGH_REG_OFFS 0x0600
2796+
2797+#define PSB_NUM_VBLANKS 2
2798+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
2799+
2800+/*
2801+ * User options.
2802+ */
2803+
2804+struct drm_psb_uopt {
2805+ int disable_clock_gating;
2806+};
2807+
2808+struct psb_gtt {
2809+ struct drm_device *dev;
2810+ int initialized;
2811+ uint32_t gatt_start;
2812+ uint32_t gtt_start;
2813+ uint32_t gtt_phys_start;
2814+ unsigned gtt_pages;
2815+ unsigned gatt_pages;
2816+ uint32_t stolen_base;
2817+ uint32_t pge_ctl;
2818+ u16 gmch_ctrl;
2819+ unsigned long stolen_size;
2820+ uint32_t *gtt_map;
2821+ struct rw_semaphore sem;
2822+};
2823+
2824+struct psb_use_base {
2825+ struct list_head head;
2826+ struct drm_fence_object *fence;
2827+ unsigned int reg;
2828+ unsigned long offset;
2829+ unsigned int dm;
2830+};
2831+
2832+struct psb_buflist_item {
2833+ struct drm_buffer_object *bo;
2834+ void __user *data;
2835+ struct drm_bo_info_rep rep;
2836+ int ret;
2837+};
2838+
2839+struct psb_msvdx_cmd_queue {
2840+ struct list_head head;
2841+ void *cmd;
2842+ unsigned long cmd_size;
2843+ uint32_t sequence;
2844+};
2845+
2846+struct drm_psb_private {
2847+ unsigned long chipset;
2848+
2849+ struct psb_xhw_buf resume_buf;
2850+ struct drm_psb_dev_info_arg dev_info;
2851+ struct drm_psb_uopt uopt;
2852+
2853+ struct psb_gtt *pg;
2854+
2855+ struct page *scratch_page;
2856+ struct page *comm_page;
2857+
2858+ volatile uint32_t *comm;
2859+ uint32_t comm_mmu_offset;
2860+ uint32_t mmu_2d_offset;
2861+ uint32_t sequence[PSB_NUM_ENGINES];
2862+ uint32_t last_sequence[PSB_NUM_ENGINES];
2863+ int idle[PSB_NUM_ENGINES];
2864+ uint32_t last_submitted_seq[PSB_NUM_ENGINES];
2865+ int engine_lockup_2d;
2866+
2867+ struct psb_mmu_driver *mmu;
2868+ struct psb_mmu_pd *pf_pd;
2869+
2870+ uint8_t *sgx_reg;
2871+ uint8_t *vdc_reg;
2872+ uint8_t *msvdx_reg;
2873+ /*MSVDX*/ int msvdx_needs_reset;
2874+ int has_msvdx;
2875+ uint32_t gatt_free_offset;
2876+
2877+ /*
2878+ * Fencing / irq.
2879+ */
2880+
2881+ uint32_t sgx_irq_mask;
2882+ uint32_t vdc_irq_mask;
2883+
2884+ spinlock_t irqmask_lock;
2885+ spinlock_t sequence_lock;
2886+ int fence0_irq_on;
2887+ int irq_enabled;
2888+ unsigned int irqen_count_2d;
2889+ wait_queue_head_t event_2d_queue;
2890+
2891+ uint32_t msvdx_current_sequence;
2892+ uint32_t msvdx_last_sequence;
2893+ int fence2_irq_on;
2894+ struct mutex mutex_2d;
2895+
2896+ /*
2897+ * MSVDX Rendec Memory
2898+ */
2899+ struct drm_buffer_object *ccb0;
2900+ uint32_t base_addr0;
2901+ struct drm_buffer_object *ccb1;
2902+ uint32_t base_addr1;
2903+
2904+ /*
2905+ * Memory managers
2906+ */
2907+
2908+ int have_vram;
2909+ int have_tt;
2910+ int have_mem_mmu;
2911+ int have_mem_aper;
2912+ int have_mem_kernel;
2913+ int have_mem_pds;
2914+ int have_mem_rastgeom;
2915+ struct mutex temp_mem;
2916+
2917+ /*
2918+ * Relocation buffer mapping.
2919+ */
2920+
2921+ spinlock_t reloc_lock;
2922+ unsigned int rel_mapped_pages;
2923+ wait_queue_head_t rel_mapped_queue;
2924+
2925+ /*
2926+ * SAREA
2927+ */
2928+ struct drm_psb_sarea *sarea_priv;
2929+
2930+ /*
2931+ * LVDS info
2932+ */
2933+ uint8_t blc_type;
2934+ uint8_t blc_pol;
2935+ uint8_t blc_freq;
2936+ uint8_t blc_minbrightness;
2937+ uint8_t blc_i2caddr;
2938+ uint8_t blc_brightnesscmd;
2939+ int backlight; /* restore backlight to this value */
2940+
2941+ struct intel_i2c_chan *i2c_bus;
2942+ u32 CoreClock;
2943+ u32 PWMControlRegFreq;
2944+
2945+ unsigned char * OpRegion;
2946+ unsigned int OpRegionSize;
2947+
2948+ int backlight_duty_cycle; /* restore backlight to this value */
2949+ bool panel_wants_dither;
2950+ struct drm_display_mode *panel_fixed_mode;
2951+
2952+ /*
2953+ * Register state
2954+ */
2955+ uint32_t saveDSPACNTR;
2956+ uint32_t saveDSPBCNTR;
2957+ uint32_t savePIPEACONF;
2958+ uint32_t savePIPEBCONF;
2959+ uint32_t savePIPEASRC;
2960+ uint32_t savePIPEBSRC;
2961+ uint32_t saveFPA0;
2962+ uint32_t saveFPA1;
2963+ uint32_t saveDPLL_A;
2964+ uint32_t saveDPLL_A_MD;
2965+ uint32_t saveHTOTAL_A;
2966+ uint32_t saveHBLANK_A;
2967+ uint32_t saveHSYNC_A;
2968+ uint32_t saveVTOTAL_A;
2969+ uint32_t saveVBLANK_A;
2970+ uint32_t saveVSYNC_A;
2971+ uint32_t saveDSPASTRIDE;
2972+ uint32_t saveDSPASIZE;
2973+ uint32_t saveDSPAPOS;
2974+ uint32_t saveDSPABASE;
2975+ uint32_t saveDSPASURF;
2976+ uint32_t saveFPB0;
2977+ uint32_t saveFPB1;
2978+ uint32_t saveDPLL_B;
2979+ uint32_t saveDPLL_B_MD;
2980+ uint32_t saveHTOTAL_B;
2981+ uint32_t saveHBLANK_B;
2982+ uint32_t saveHSYNC_B;
2983+ uint32_t saveVTOTAL_B;
2984+ uint32_t saveVBLANK_B;
2985+ uint32_t saveVSYNC_B;
2986+ uint32_t saveDSPBSTRIDE;
2987+ uint32_t saveDSPBSIZE;
2988+ uint32_t saveDSPBPOS;
2989+ uint32_t saveDSPBBASE;
2990+ uint32_t saveDSPBSURF;
2991+ uint32_t saveVCLK_DIVISOR_VGA0;
2992+ uint32_t saveVCLK_DIVISOR_VGA1;
2993+ uint32_t saveVCLK_POST_DIV;
2994+ uint32_t saveVGACNTRL;
2995+ uint32_t saveADPA;
2996+ uint32_t saveLVDS;
2997+ uint32_t saveDVOA;
2998+ uint32_t saveDVOB;
2999+ uint32_t saveDVOC;
3000+ uint32_t savePP_ON;
3001+ uint32_t savePP_OFF;
3002+ uint32_t savePP_CONTROL;
3003+ uint32_t savePP_CYCLE;
3004+ uint32_t savePFIT_CONTROL;
3005+ uint32_t savePaletteA[256];
3006+ uint32_t savePaletteB[256];
3007+ uint32_t saveBLC_PWM_CTL;
3008+
3009+ /*
3010+ * USE code base register management.
3011+ */
3012+
3013+ struct drm_reg_manager use_manager;
3014+
3015+ /*
3016+ * Xhw
3017+ */
3018+
3019+ uint32_t *xhw;
3020+ struct drm_buffer_object *xhw_bo;
3021+ struct drm_bo_kmap_obj xhw_kmap;
3022+ struct list_head xhw_in;
3023+ spinlock_t xhw_lock;
3024+ atomic_t xhw_client;
3025+ struct drm_file *xhw_file;
3026+ wait_queue_head_t xhw_queue;
3027+ wait_queue_head_t xhw_caller_queue;
3028+ struct mutex xhw_mutex;
3029+ struct psb_xhw_buf *xhw_cur_buf;
3030+ int xhw_submit_ok;
3031+ int xhw_on;
3032+
3033+ /*
3034+ * Scheduling.
3035+ */
3036+
3037+ struct mutex reset_mutex;
3038+ struct mutex cmdbuf_mutex;
3039+ struct psb_scheduler scheduler;
3040+ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS];
3041+ uint32_t ta_mem_pages;
3042+ struct psb_ta_mem *ta_mem;
3043+ int force_ta_mem_load;
3044+
3045+ /*
3046+ * Watchdog
3047+ */
3048+
3049+ spinlock_t watchdog_lock;
3050+ struct timer_list watchdog_timer;
3051+ struct work_struct watchdog_wq;
3052+ struct work_struct msvdx_watchdog_wq;
3053+ int timer_available;
3054+
3055+ /*
3056+ * msvdx command queue
3057+ */
3058+ spinlock_t msvdx_lock;
3059+ struct mutex msvdx_mutex;
3060+ struct list_head msvdx_queue;
3061+ int msvdx_busy;
3062+};
3063+
3064+struct psb_mmu_driver;
3065+
3066+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
3067+ int trap_pagefaults,
3068+ int invalid_type);
3069+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
3070+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
3071+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
3072+ uint32_t gtt_start, uint32_t gtt_pages);
3073+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
3074+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
3075+ int trap_pagefaults,
3076+ int invalid_type);
3077+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
3078+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
3079+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
3080+ unsigned long address,
3081+ uint32_t num_pages);
3082+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
3083+ uint32_t start_pfn,
3084+ unsigned long address,
3085+ uint32_t num_pages, int type);
3086+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
3087+ unsigned long *pfn);
3088+
3089+/*
3090+ * Enable / disable MMU for different requestors.
3091+ */
3092+
3093+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
3094+ uint32_t mask);
3095+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
3096+ uint32_t mask);
3097+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
3098+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
3099+ unsigned long address, uint32_t num_pages,
3100+ uint32_t desired_tile_stride,
3101+ uint32_t hw_tile_stride, int type);
3102+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
3103+ uint32_t num_pages,
3104+ uint32_t desired_tile_stride,
3105+ uint32_t hw_tile_stride);
3106+/*
3107+ * psb_sgx.c
3108+ */
3109+
3110+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
3111+ uint32_t sequence);
3112+extern void psb_init_2d(struct drm_psb_private *dev_priv);
3113+extern int drm_psb_idle(struct drm_device *dev);
3114+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
3115+ uint32_t src_offset,
3116+ uint32_t dst_offset, uint32_t pages,
3117+ int direction);
3118+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
3119+ struct drm_file *file_priv);
3120+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
3121+ unsigned int cmds);
3122+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
3123+ struct drm_buffer_object *cmd_buffer,
3124+ unsigned long cmd_offset,
3125+ unsigned long cmd_size, int engine,
3126+ uint32_t * copy_buffer);
3127+
3128+extern int psb_fence_for_errors(struct drm_file *priv,
3129+ struct drm_psb_cmdbuf_arg *arg,
3130+ struct drm_fence_arg *fence_arg,
3131+ struct drm_fence_object **fence_p);
3132+
3133+/*
3134+ * psb_irq.c
3135+ */
3136+
3137+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
3138+extern void psb_irq_preinstall(struct drm_device *dev);
3139+extern void psb_irq_postinstall(struct drm_device *dev);
3140+extern void psb_irq_uninstall(struct drm_device *dev);
3141+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
3142+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
3143+
3144+/*
3145+ * psb_fence.c
3146+ */
3147+
3148+extern void psb_poke_flush(struct drm_device *dev, uint32_t class);
3149+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class,
3150+ uint32_t flags, uint32_t * sequence,
3151+ uint32_t * native_type);
3152+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
3153+extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class,
3154+ uint32_t flags);
3155+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
3156+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
3157+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
3158+ uint32_t class);
3159+extern void psb_fence_error(struct drm_device *dev,
3160+ uint32_t class,
3161+ uint32_t sequence, uint32_t type, int error);
3162+
3163+/*MSVDX stuff*/
3164+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
3165+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
3166+
3167+/*
3168+ * psb_buffer.c
3169+ */
3170+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
3171+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
3172+ uint32_t * type);
3173+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
3174+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
3175+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
3176+ struct drm_mem_type_manager *man);
3177+extern int psb_move(struct drm_buffer_object *bo,
3178+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
3179+
3180+/*
3181+ * psb_gtt.c
3182+ */
3183+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
3184+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
3185+ unsigned offset_pages, unsigned num_pages,
3186+ unsigned desired_tile_stride,
3187+ unsigned hw_tile_stride, int type);
3188+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
3189+ unsigned num_pages,
3190+ unsigned desired_tile_stride,
3191+ unsigned hw_tile_stride);
3192+
3193+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
3194+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
3195+
3196+/*
3197+ * psb_fb.c
3198+ */
3199+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
3200+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
3201+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
3202+ struct drm_file *file_priv);
3203+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
3204+ struct drm_file *file_priv);
3205+
3206+/*
3207+ * psb_reset.c
3208+ */
3209+
3210+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
3211+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
3212+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
3213+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
3214+
3215+/*
3216+ * psb_regman.c
3217+ */
3218+
3219+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
3220+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
3221+ unsigned long dev_virtual,
3222+ unsigned long size,
3223+ unsigned int data_master,
3224+ uint32_t fence_class,
3225+ uint32_t fence_type,
3226+ int no_wait,
3227+ int ignore_signals,
3228+ int *r_reg, uint32_t * r_offset);
3229+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
3230+ unsigned int reg_start, unsigned int reg_num);
3231+
3232+/*
3233+ * psb_xhw.c
3234+ */
3235+
3236+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
3237+ struct drm_file *file_priv);
3238+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
3239+ struct drm_file *file_priv);
3240+extern int psb_xhw_init(struct drm_device *dev);
3241+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
3242+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
3243+ struct drm_file *file_priv, int closing);
3244+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
3245+ struct psb_xhw_buf *buf,
3246+ uint32_t fire_flags,
3247+ uint32_t hw_context,
3248+ uint32_t * cookie,
3249+ uint32_t * oom_cmds,
3250+ uint32_t num_oom_cmds,
3251+ uint32_t offset,
3252+ uint32_t engine, uint32_t flags);
3253+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
3254+ struct psb_xhw_buf *buf, uint32_t fire_flags);
3255+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
3256+ struct psb_xhw_buf *buf,
3257+ uint32_t w,
3258+ uint32_t h,
3259+ uint32_t * hw_cookie,
3260+ uint32_t * bo_size,
3261+ uint32_t * clear_p_start,
3262+ uint32_t * clear_num_pages);
3263+
3264+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
3265+ struct psb_xhw_buf *buf);
3266+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
3267+ struct psb_xhw_buf *buf,
3268+ uint32_t pages,
3269+ uint32_t * hw_cookie, uint32_t * size);
3270+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
3271+ struct psb_xhw_buf *buf, uint32_t * cookie);
3272+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
3273+ struct psb_xhw_buf *buf,
3274+ uint32_t * cookie,
3275+ uint32_t * bca,
3276+ uint32_t * rca, uint32_t * flags);
3277+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
3278+ struct psb_xhw_buf *buf);
3279+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
3280+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
3281+ struct psb_xhw_buf *buf);
3282+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
3283+ struct psb_xhw_buf *buf, uint32_t * cookie);
3284+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
3285+ struct psb_xhw_buf *buf,
3286+ uint32_t flags,
3287+ uint32_t param_offset,
3288+ uint32_t pt_offset,
3289+ uint32_t *hw_cookie);
3290+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
3291+ struct psb_xhw_buf *buf);
3292+
3293+/*
3294+ * Utilities
3295+ */
3296+
3297+#define PSB_ALIGN_TO(_val, _align) \
3298+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
3299+#define PSB_WVDC32(_val, _offs) \
3300+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
3301+#define PSB_RVDC32(_offs) \
3302+ ioread32(dev_priv->vdc_reg + (_offs))
3303+#define PSB_WSGX32(_val, _offs) \
3304+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
3305+#define PSB_RSGX32(_offs) \
3306+ ioread32(dev_priv->sgx_reg + (_offs))
3307+#define PSB_WMSVDX32(_val, _offs) \
3308+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
3309+#define PSB_RMSVDX32(_offs) \
3310+ ioread32(dev_priv->msvdx_reg + (_offs))
3311+
3312+#define PSB_ALPL(_val, _base) \
3313+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
3314+#define PSB_ALPLM(_val, _base) \
3315+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
3316+
3317+static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b)
3318+{
3319+ s64 tmp;
3320+ s64 a64 = (s64) a;
3321+ s64 b64 = (s64) b;
3322+
3323+ tmp = a64 * b64;
3324+ return tmp / (1ULL << PSB_FIXED_SHIFT) +
3325+ ((tmp & 0x80000000ULL) ? 1 : 0);
3326+}
3327+
3328+static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b)
3329+{
3330+ u64 tmp;
3331+ u64 a64 = (u64) a;
3332+ u64 b64 = (u64) b;
3333+
3334+ tmp = a64 * b64;
3335+ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0);
3336+}
3337+
3338+static inline uint32_t psb_ufixed_to_float32(psb_ufixed a)
3339+{
3340+ uint32_t exp = 0x7f + 7;
3341+ uint32_t mantissa = (uint32_t) a;
3342+
3343+ if (a == 0)
3344+ return 0;
3345+ while ((mantissa & 0xff800000) == 0) {
3346+ exp -= 1;
3347+ mantissa <<= 1;
3348+ }
3349+ while ((mantissa & 0xff800000) > 0x00800000) {
3350+ exp += 1;
3351+ mantissa >>= 1;
3352+ }
3353+ return (mantissa & ~0xff800000) | (exp << 23);
3354+}
3355+
3356+static inline uint32_t psb_fixed_to_float32(psb_fixed a)
3357+{
3358+ if (a < 0)
3359+ return psb_ufixed_to_float32(-a) | 0x80000000;
3360+ else
3361+ return psb_ufixed_to_float32(a);
3362+}
3363+
3364+#define PSB_D_RENDER (1 << 16)
3365+
3366+#define PSB_D_GENERAL (1 << 0)
3367+#define PSB_D_INIT (1 << 1)
3368+#define PSB_D_IRQ (1 << 2)
3369+#define PSB_D_FW (1 << 3)
3370+#define PSB_D_PERF (1 << 4)
3371+#define PSB_D_TMP (1 << 5)
3372+
3373+extern int drm_psb_debug;
3374+extern int drm_psb_no_fb;
3375+extern int drm_psb_disable_vsync;
3376+
3377+#define PSB_DEBUG_FW(_fmt, _arg...) \
3378+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
3379+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
3380+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
3381+#define PSB_DEBUG_INIT(_fmt, _arg...) \
3382+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
3383+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
3384+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
3385+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
3386+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
3387+#define PSB_DEBUG_PERF(_fmt, _arg...) \
3388+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
3389+#define PSB_DEBUG_TMP(_fmt, _arg...) \
3390+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
3391+
3392+#if DRM_DEBUG_CODE
3393+#define PSB_DEBUG(_flag, _fmt, _arg...) \
3394+ do { \
3395+ if ((_flag) & drm_psb_debug) \
3396+ printk(KERN_DEBUG \
3397+ "[psb:0x%02x:%s] " _fmt , _flag, \
3398+ __FUNCTION__ , ##_arg); \
3399+ } while (0)
3400+#else
3401+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
3402+#endif
3403+
3404+#endif
3405Index: libdrm-2.3.1/shared-core/psb_reg.h
3406===================================================================
3407--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3408+++ libdrm-2.3.1/shared-core/psb_reg.h 2009-01-14 18:26:59.000000000 +0000
3409@@ -0,0 +1,555 @@
3410+/**************************************************************************
3411+ *
3412+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
3413+ * Copyright (c) 2007, Intel Corporation.
3414+ * All Rights Reserved.
3415+ *
3416+ * This program is free software; you can redistribute it and/or modify it
3417+ * under the terms and conditions of the GNU General Public License,
3418+ * version 2, as published by the Free Software Foundation.
3419+ *
3420+ * This program is distributed in the hope it will be useful, but WITHOUT
3421+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3422+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3423+ * more details.
3424+ *
3425+ * You should have received a copy of the GNU General Public License along with
3426+ * this program; if not, write to the Free Software Foundation, Inc.,
3427+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3428+ *
3429+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
3430+ * develop this driver.
3431+ *
3432+ **************************************************************************/
3433+/*
3434+ */
3435+#ifndef _PSB_REG_H_
3436+#define _PSB_REG_H_
3437+
3438+#define PSB_CR_CLKGATECTL 0x0000
3439+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
3440+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
3441+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
3442+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
3443+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
3444+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
3445+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
3446+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
3447+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
3448+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
3449+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
3450+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
3451+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
3452+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
3453+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
3454+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
3455+
3456+#define PSB_CR_CORE_ID 0x0010
3457+#define _PSB_CC_ID_ID_SHIFT (16)
3458+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
3459+#define _PSB_CC_ID_CONFIG_SHIFT (0)
3460+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
3461+
3462+#define PSB_CR_CORE_REVISION 0x0014
3463+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
3464+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
3465+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
3466+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
3467+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
3468+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
3469+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
3470+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
3471+
3472+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
3473+
3474+#define PSB_CR_SOFT_RESET 0x0080
3475+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
3476+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
3477+#define _PSB_CS_RESET_USE_RESET (1 << 4)
3478+#define _PSB_CS_RESET_TA_RESET (1 << 3)
3479+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
3480+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
3481+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
3482+
3483+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
3484+
3485+#define PSB_CR_EVENT_STATUS 0x012C
3486+
3487+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
3488+
3489+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
3490+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
3491+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
3492+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
3493+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
3494+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
3495+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
3496+#define _PSB_CE_SW_EVENT (1 << 14)
3497+#define _PSB_CE_TA_FINISHED (1 << 13)
3498+#define _PSB_CE_TA_TERMINATE (1 << 12)
3499+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
3500+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
3501+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
3502+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
3503+
3504+
3505+#define PSB_USE_OFFSET_MASK 0x0007FFFF
3506+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
3507+#define PSB_CR_USE_CODE_BASE0 0x0A0C
3508+#define PSB_CR_USE_CODE_BASE1 0x0A10
3509+#define PSB_CR_USE_CODE_BASE2 0x0A14
3510+#define PSB_CR_USE_CODE_BASE3 0x0A18
3511+#define PSB_CR_USE_CODE_BASE4 0x0A1C
3512+#define PSB_CR_USE_CODE_BASE5 0x0A20
3513+#define PSB_CR_USE_CODE_BASE6 0x0A24
3514+#define PSB_CR_USE_CODE_BASE7 0x0A28
3515+#define PSB_CR_USE_CODE_BASE8 0x0A2C
3516+#define PSB_CR_USE_CODE_BASE9 0x0A30
3517+#define PSB_CR_USE_CODE_BASE10 0x0A34
3518+#define PSB_CR_USE_CODE_BASE11 0x0A38
3519+#define PSB_CR_USE_CODE_BASE12 0x0A3C
3520+#define PSB_CR_USE_CODE_BASE13 0x0A40
3521+#define PSB_CR_USE_CODE_BASE14 0x0A44
3522+#define PSB_CR_USE_CODE_BASE15 0x0A48
3523+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
3524+#define _PSB_CUC_BASE_DM_SHIFT (25)
3525+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
3526+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
3527+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
3528+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
3529+#define _PSB_CUC_DM_VERTEX (0)
3530+#define _PSB_CUC_DM_PIXEL (1)
3531+#define _PSB_CUC_DM_RESERVED (2)
3532+#define _PSB_CUC_DM_EDM (3)
3533+
3534+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
3535+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
3536+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
3537+
3538+#define PSB_CR_EVENT_KICKER 0x0AC4
3539+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
3540+
3541+#define PSB_CR_EVENT_KICK 0x0AC8
3542+#define _PSB_CE_KICK_NOW (1 << 0)
3543+
3544+
3545+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
3546+
3547+#define PSB_CR_BIF_CTRL 0x0C00
3548+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
3549+#define _PSB_CB_CTRL_INVALDC (1 << 3)
3550+#define _PSB_CB_CTRL_FLUSH (1 << 2)
3551+
3552+#define PSB_CR_BIF_INT_STAT 0x0C04
3553+
3554+#define PSB_CR_BIF_FAULT 0x0C08
3555+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
3556+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
3557+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
3558+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
3559+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
3560+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
3561+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
3562+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
3563+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
3564+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
3565+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
3566+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
3567+
3568+#define PSB_CR_BIF_BANK0 0x0C78
3569+
3570+#define PSB_CR_BIF_BANK1 0x0C7C
3571+
3572+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
3573+
3574+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
3575+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
3576+
3577+#define PSB_CR_2D_SOCIF 0x0E18
3578+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
3579+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
3580+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
3581+
3582+#define PSB_CR_2D_BLIT_STATUS 0x0E04
3583+#define _PSB_C2B_STATUS_BUSY (1 << 24)
3584+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
3585+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
3586+
3587+/*
3588+ * 2D defs.
3589+ */
3590+
3591+/*
3592+ * 2D Slave Port Data : Block Header's Object Type
3593+ */
3594+
3595+#define PSB_2D_CLIP_BH (0x00000000)
3596+#define PSB_2D_PAT_BH (0x10000000)
3597+#define PSB_2D_CTRL_BH (0x20000000)
3598+#define PSB_2D_SRC_OFF_BH (0x30000000)
3599+#define PSB_2D_MASK_OFF_BH (0x40000000)
3600+#define PSB_2D_RESERVED1_BH (0x50000000)
3601+#define PSB_2D_RESERVED2_BH (0x60000000)
3602+#define PSB_2D_FENCE_BH (0x70000000)
3603+#define PSB_2D_BLIT_BH (0x80000000)
3604+#define PSB_2D_SRC_SURF_BH (0x90000000)
3605+#define PSB_2D_DST_SURF_BH (0xA0000000)
3606+#define PSB_2D_PAT_SURF_BH (0xB0000000)
3607+#define PSB_2D_SRC_PAL_BH (0xC0000000)
3608+#define PSB_2D_PAT_PAL_BH (0xD0000000)
3609+#define PSB_2D_MASK_SURF_BH (0xE0000000)
3610+#define PSB_2D_FLUSH_BH (0xF0000000)
3611+
3612+/*
3613+ * Clip Definition block (PSB_2D_CLIP_BH)
3614+ */
3615+#define PSB_2D_CLIPCOUNT_MAX (1)
3616+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
3617+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
3618+#define PSB_2D_CLIPCOUNT_SHIFT (0)
3619+// clip rectangle min & max
3620+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
3621+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
3622+#define PSB_2D_CLIP_XMAX_SHIFT (12)
3623+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
3624+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
3625+#define PSB_2D_CLIP_XMIN_SHIFT (0)
3626+// clip rectangle offset
3627+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
3628+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
3629+#define PSB_2D_CLIP_YMAX_SHIFT (12)
3630+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
3631+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
3632+#define PSB_2D_CLIP_YMIN_SHIFT (0)
3633+
3634+/*
3635+ * Pattern Control (PSB_2D_PAT_BH)
3636+ */
3637+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
3638+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
3639+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
3640+#define PSB_2D_PAT_WIDTH_SHIFT (5)
3641+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
3642+#define PSB_2D_PAT_YSTART_SHIFT (10)
3643+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
3644+#define PSB_2D_PAT_XSTART_SHIFT (15)
3645+
3646+/*
3647+ * 2D Control block (PSB_2D_CTRL_BH)
3648+ */
3649+// Present Flags
3650+#define PSB_2D_SRCCK_CTRL (0x00000001)
3651+#define PSB_2D_DSTCK_CTRL (0x00000002)
3652+#define PSB_2D_ALPHA_CTRL (0x00000004)
3653+// Colour Key Colour (SRC/DST)
3654+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
3655+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
3656+#define PSB_2D_CK_COL_SHIFT (0)
3657+// Colour Key Mask (SRC/DST)
3658+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
3659+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
3660+#define PSB_2D_CK_MASK_SHIFT (0)
3661+// Alpha Control (Alpha/RGB)
3662+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
3663+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
3664+#define PSB_2D_GBLALPHA_SHIFT (12)
3665+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
3666+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
3667+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
3668+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
3669+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
3670+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
3671+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
3672+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
3673+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
3674+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
3675+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
3676+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
3677+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
3678+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
3679+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
3680+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
3681+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
3682+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
3683+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
3684+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
3685+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
3686+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
3687+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
3688+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
3689+
3690+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
3691+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
3692+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
3693+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
3694+
3695+/*
3696+ *Source Offset (PSB_2D_SRC_OFF_BH)
3697+ */
3698+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
3699+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
3700+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
3701+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
3702+
3703+/*
3704+ * Mask Offset (PSB_2D_MASK_OFF_BH)
3705+ */
3706+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
3707+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
3708+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
3709+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
3710+
3711+/*
3712+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
3713+ */
3714+
3715+/*
3716+ *Blit Rectangle (PSB_2D_BLIT_BH)
3717+ */
3718+
3719+#define PSB_2D_ROT_MASK (3<<25)
3720+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
3721+#define PSB_2D_ROT_NONE (0<<25)
3722+#define PSB_2D_ROT_90DEGS (1<<25)
3723+#define PSB_2D_ROT_180DEGS (2<<25)
3724+#define PSB_2D_ROT_270DEGS (3<<25)
3725+
3726+#define PSB_2D_COPYORDER_MASK (3<<23)
3727+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
3728+#define PSB_2D_COPYORDER_TL2BR (0<<23)
3729+#define PSB_2D_COPYORDER_BR2TL (1<<23)
3730+#define PSB_2D_COPYORDER_TR2BL (2<<23)
3731+#define PSB_2D_COPYORDER_BL2TR (3<<23)
3732+
3733+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
3734+#define PSB_2D_DSTCK_DISABLE (0x00000000)
3735+#define PSB_2D_DSTCK_PASS (0x00200000)
3736+#define PSB_2D_DSTCK_REJECT (0x00400000)
3737+
3738+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
3739+#define PSB_2D_SRCCK_DISABLE (0x00000000)
3740+#define PSB_2D_SRCCK_PASS (0x00080000)
3741+#define PSB_2D_SRCCK_REJECT (0x00100000)
3742+
3743+#define PSB_2D_CLIP_ENABLE (0x00040000)
3744+
3745+#define PSB_2D_ALPHA_ENABLE (0x00020000)
3746+
3747+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
3748+#define PSB_2D_PAT_MASK (0x00010000)
3749+#define PSB_2D_USE_PAT (0x00010000)
3750+#define PSB_2D_USE_FILL (0x00000000)
3751+/*
3752+ * Tungsten Graphics note on rop codes: If rop A and rop B are
3753+ * identical, the mask surface will not be read and need not be
3754+ * set up.
3755+ */
3756+
3757+#define PSB_2D_ROP3B_MASK (0x0000FF00)
3758+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
3759+#define PSB_2D_ROP3B_SHIFT (8)
3760+// rop code A
3761+#define PSB_2D_ROP3A_MASK (0x000000FF)
3762+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
3763+#define PSB_2D_ROP3A_SHIFT (0)
3764+
3765+#define PSB_2D_ROP4_MASK (0x0000FFFF)
3766+/*
3767+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
3768+ * Fill Colour RGBA8888
3769+ */
3770+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
3771+#define PSB_2D_FILLCOLOUR_SHIFT (0)
3772+/*
3773+ * DWORD1: (Always Present)
3774+ * X Start (Dest)
3775+ * Y Start (Dest)
3776+ */
3777+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
3778+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
3779+#define PSB_2D_DST_XSTART_SHIFT (12)
3780+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
3781+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
3782+#define PSB_2D_DST_YSTART_SHIFT (0)
3783+/*
3784+ * DWORD2: (Always Present)
3785+ * X Size (Dest)
3786+ * Y Size (Dest)
3787+ */
3788+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
3789+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
3790+#define PSB_2D_DST_XSIZE_SHIFT (12)
3791+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
3792+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
3793+#define PSB_2D_DST_YSIZE_SHIFT (0)
3794+
3795+/*
3796+ * Source Surface (PSB_2D_SRC_SURF_BH)
3797+ */
3798+/*
3799+ * WORD 0
3800+ */
3801+
3802+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
3803+#define PSB_2D_SRC_1_PAL (0x00000000)
3804+#define PSB_2D_SRC_2_PAL (0x00008000)
3805+#define PSB_2D_SRC_4_PAL (0x00010000)
3806+#define PSB_2D_SRC_8_PAL (0x00018000)
3807+#define PSB_2D_SRC_8_ALPHA (0x00020000)
3808+#define PSB_2D_SRC_4_ALPHA (0x00028000)
3809+#define PSB_2D_SRC_332RGB (0x00030000)
3810+#define PSB_2D_SRC_4444ARGB (0x00038000)
3811+#define PSB_2D_SRC_555RGB (0x00040000)
3812+#define PSB_2D_SRC_1555ARGB (0x00048000)
3813+#define PSB_2D_SRC_565RGB (0x00050000)
3814+#define PSB_2D_SRC_0888ARGB (0x00058000)
3815+#define PSB_2D_SRC_8888ARGB (0x00060000)
3816+#define PSB_2D_SRC_8888UYVY (0x00068000)
3817+#define PSB_2D_SRC_RESERVED (0x00070000)
3818+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
3819+
3820+
3821+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
3822+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
3823+#define PSB_2D_SRC_STRIDE_SHIFT (0)
3824+/*
3825+ * WORD 1 - Base Address
3826+ */
3827+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
3828+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
3829+#define PSB_2D_SRC_ADDR_SHIFT (2)
3830+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
3831+
3832+/*
3833+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
3834+ */
3835+/*
3836+ * WORD 0
3837+ */
3838+
3839+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
3840+#define PSB_2D_PAT_1_PAL (0x00000000)
3841+#define PSB_2D_PAT_2_PAL (0x00008000)
3842+#define PSB_2D_PAT_4_PAL (0x00010000)
3843+#define PSB_2D_PAT_8_PAL (0x00018000)
3844+#define PSB_2D_PAT_8_ALPHA (0x00020000)
3845+#define PSB_2D_PAT_4_ALPHA (0x00028000)
3846+#define PSB_2D_PAT_332RGB (0x00030000)
3847+#define PSB_2D_PAT_4444ARGB (0x00038000)
3848+#define PSB_2D_PAT_555RGB (0x00040000)
3849+#define PSB_2D_PAT_1555ARGB (0x00048000)
3850+#define PSB_2D_PAT_565RGB (0x00050000)
3851+#define PSB_2D_PAT_0888ARGB (0x00058000)
3852+#define PSB_2D_PAT_8888ARGB (0x00060000)
3853+
3854+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
3855+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
3856+#define PSB_2D_PAT_STRIDE_SHIFT (0)
3857+/*
3858+ * WORD 1 - Base Address
3859+ */
3860+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
3861+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
3862+#define PSB_2D_PAT_ADDR_SHIFT (2)
3863+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
3864+
3865+/*
3866+ * Destination Surface (PSB_2D_DST_SURF_BH)
3867+ */
3868+/*
3869+ * WORD 0
3870+ */
3871+
3872+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
3873+#define PSB_2D_DST_332RGB (0x00030000)
3874+#define PSB_2D_DST_4444ARGB (0x00038000)
3875+#define PSB_2D_DST_555RGB (0x00040000)
3876+#define PSB_2D_DST_1555ARGB (0x00048000)
3877+#define PSB_2D_DST_565RGB (0x00050000)
3878+#define PSB_2D_DST_0888ARGB (0x00058000)
3879+#define PSB_2D_DST_8888ARGB (0x00060000)
3880+#define PSB_2D_DST_8888AYUV (0x00070000)
3881+
3882+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
3883+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
3884+#define PSB_2D_DST_STRIDE_SHIFT (0)
3885+/*
3886+ * WORD 1 - Base Address
3887+ */
3888+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
3889+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
3890+#define PSB_2D_DST_ADDR_SHIFT (2)
3891+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
3892+
3893+/*
3894+ * Mask Surface (PSB_2D_MASK_SURF_BH)
3895+ */
3896+/*
3897+ * WORD 0
3898+ */
3899+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
3900+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
3901+#define PSB_2D_MASK_STRIDE_SHIFT (0)
3902+/*
3903+ * WORD 1 - Base Address
3904+ */
3905+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
3906+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
3907+#define PSB_2D_MASK_ADDR_SHIFT (2)
3908+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
3909+
3910+/*
3911+ * Source Palette (PSB_2D_SRC_PAL_BH)
3912+ */
3913+
3914+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
3915+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
3916+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
3917+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
3918+
3919+/*
3920+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
3921+ */
3922+
3923+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
3924+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
3925+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
3926+#define PSB_2D_PATPAL_BYTEALIGN (1024)
3927+
3928+/*
3929+ * Rop3 Codes (2 LS bytes)
3930+ */
3931+
3932+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
3933+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
3934+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
3935+#define PSB_2D_ROP3_BLACKNESS (0x0000)
3936+#define PSB_2D_ROP3_SRC (0xCC)
3937+#define PSB_2D_ROP3_PAT (0xF0)
3938+#define PSB_2D_ROP3_DST (0xAA)
3939+
3940+
3941+/*
3942+ * Sizes.
3943+ */
3944+
3945+#define PSB_SCENE_HW_COOKIE_SIZE 16
3946+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
3947+
3948+/*
3949+ * Scene stuff.
3950+ */
3951+
3952+#define PSB_NUM_HW_SCENES 2
3953+
3954+/*
3955+ * Scheduler completion actions.
3956+ */
3957+
3958+#define PSB_RASTER_BLOCK 0
3959+#define PSB_RASTER 1
3960+#define PSB_RETURN 2
3961+#define PSB_TA 3
3962+
3963+
3964+#endif
3965Index: libdrm-2.3.1/shared-core/radeon_drm.h
3966===================================================================
3967--- libdrm-2.3.1.orig/shared-core/radeon_drm.h 2008-07-01 08:50:43.000000000 +0100
3968+++ libdrm-2.3.1/shared-core/radeon_drm.h 2009-01-14 18:26:59.000000000 +0000
3969@@ -453,8 +453,17 @@
3970 int pfCurrentPage; /* which buffer is being displayed? */
3971 int crtc2_base; /* CRTC2 frame offset */
3972 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
3973+
3974+ unsigned int last_fence;
3975 } drm_radeon_sarea_t;
3976
3977+/* The only fence class we support */
3978+#define DRM_RADEON_FENCE_CLASS_ACCEL 0
3979+/* Fence type that guarantees read-write flush */
3980+#define DRM_RADEON_FENCE_TYPE_RW 2
3981+/* cache flushes programmed just before the fence */
3982+#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000
3983+
3984 /* WARNING: If you change any of these defines, make sure to change the
3985 * defines in the Xserver file (xf86drmRadeon.h)
3986 *
3987Index: libdrm-2.3.1/shared-core/tdfx_drv.h
3988===================================================================
3989--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3990+++ libdrm-2.3.1/shared-core/tdfx_drv.h 2009-01-14 18:26:59.000000000 +0000
3991@@ -0,0 +1,47 @@
3992+/* tdfx.h -- 3dfx DRM template customization -*- linux-c -*-
3993+ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
3994+ */
3995+/*
3996+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3997+ * All Rights Reserved.
3998+ *
3999+ * Permission is hereby granted, free of charge, to any person obtaining a
4000+ * copy of this software and associated documentation files (the "Software"),
4001+ * to deal in the Software without restriction, including without limitation
4002+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
4003+ * and/or sell copies of the Software, and to permit persons to whom the
4004+ * Software is furnished to do so, subject to the following conditions:
4005+ *
4006+ * The above copyright notice and this permission notice (including the next
4007+ * paragraph) shall be included in all copies or substantial portions of the
4008+ * Software.
4009+ *
4010+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
4011+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
4012+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
4013+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
4014+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
4015+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4016+ * OTHER DEALINGS IN THE SOFTWARE.
4017+ *
4018+ * Authors:
4019+ * Gareth Hughes <gareth@valinux.com>
4020+ */
4021+
4022+#ifndef __TDFX_H__
4023+#define __TDFX_H__
4024+
4025+/* General customization:
4026+ */
4027+
4028+#define DRIVER_AUTHOR "VA Linux Systems Inc."
4029+
4030+#define DRIVER_NAME "tdfx"
4031+#define DRIVER_DESC "3dfx Banshee/Voodoo3+"
4032+#define DRIVER_DATE "20010216"
4033+
4034+#define DRIVER_MAJOR 1
4035+#define DRIVER_MINOR 0
4036+#define DRIVER_PATCHLEVEL 0
4037+
4038+#endif
4039Index: libdrm-2.3.1/shared-core/via_3d_reg.h
4040===================================================================
4041--- libdrm-2.3.1.orig/shared-core/via_3d_reg.h 2008-07-01 08:50:43.000000000 +0100
4042+++ libdrm-2.3.1/shared-core/via_3d_reg.h 2009-01-14 18:26:59.000000000 +0000
4043@@ -1643,6 +1643,7 @@
4044 #define HC_HAGPBpID_STOP 0x00000002
4045 #define HC_HAGPBpH_MASK 0x00ffffff
4046
4047+
4048 #define VIA_VIDEO_HEADER5 0xFE040000
4049 #define VIA_VIDEO_HEADER6 0xFE050000
4050 #define VIA_VIDEO_HEADER7 0xFE060000
diff --git a/meta-moblin/packages/drm/files/poulsbo_libdrm_update.patch b/meta-moblin/packages/drm/files/poulsbo_libdrm_update.patch
deleted file mode 100644
index 5fb84302aa..0000000000
--- a/meta-moblin/packages/drm/files/poulsbo_libdrm_update.patch
+++ /dev/null
@@ -1,63492 +0,0 @@
1From eea94c0cd2198bd46ae4417b7eb7ab5f45df0c3c Mon Sep 17 00:00:00 2001
2From: Inuka Gunawardana <inuka.gunawardana@intel.com>
3Date: Sun, 20 Jan 2008 00:46:32 -0800
4Subject: [PATCH] added changes
5
6---
7 configure.ac | 2 +-
8 libdrm/Makefile.am | 4 +-
9 libdrm/xf86drm.c | 1194 ++---
10 libdrm/xf86drm.h | 4 +-
11 libdrm/xf86drmHash.c | 20 +-
12 libdrm/xf86drmMode.c | 465 ++
13 libdrm/xf86drmMode.h | 226 +
14 libdrm/xf86drmRandom.c | 20 +-
15 libdrm/xf86drmSL.c | 23 +-
16 libdrm/xf86mm.h | 120 +-
17 shared-core/Makefile.am | 7 +-
18 shared-core/Makefile.in | 5 +-
19 shared-core/drm.h | 908 ++--
20 shared-core/drm_pciids.txt | 744 +++
21 shared-core/drm_sarea.h | 30 +-
22 shared-core/i915_dma.c | 968 ++++
23 shared-core/i915_drm.h | 131 +-
24 shared-core/i915_drv.h | 676 +++
25 shared-core/i915_irq.c | 752 +++
26 shared-core/i915_mem.c | 386 ++
27 shared-core/imagine_drv.h | 43 +
28 shared-core/mach64_dma.c | 1532 ++++++
29 shared-core/mach64_drm.h | 4 +-
30 shared-core/mach64_drv.h | 1058 ++++
31 shared-core/mach64_irq.c | 136 +
32 shared-core/mach64_state.c | 897 ++++
33 shared-core/mga_dma.c | 1164 ++++
34 shared-core/mga_drm.h | 22 +-
35 shared-core/mga_drv.h | 688 +++
36 shared-core/mga_irq.c | 150 +
37 shared-core/mga_state.c | 1143 ++++
38 shared-core/mga_ucode.h |11645 ++++++++++++++++++++++++++++++++++++++++
39 shared-core/mga_warp.c | 198 +
40 shared-core/nouveau_drm.h | 164 +
41 shared-core/nouveau_drv.h | 584 ++
42 shared-core/nouveau_fifo.c | 554 ++
43 shared-core/nouveau_irq.c | 430 ++
44 shared-core/nouveau_mem.c | 608 +++
45 shared-core/nouveau_notifier.c | 173 +
46 shared-core/nouveau_object.c | 1148 ++++
47 shared-core/nouveau_reg.h | 550 ++
48 shared-core/nouveau_state.c | 566 ++
49 shared-core/nv04_fb.c | 24 +
50 shared-core/nv04_fifo.c | 129 +
51 shared-core/nv04_graph.c | 474 ++
52 shared-core/nv04_mc.c | 23 +
53 shared-core/nv04_timer.c | 45 +
54 shared-core/nv10_fb.c | 26 +
55 shared-core/nv10_fifo.c | 160 +
56 shared-core/nv10_graph.c | 872 +++
57 shared-core/nv20_graph.c | 249 +
58 shared-core/nv30_graph.c | 2912 ++++++++++
59 shared-core/nv40_fb.c | 56 +
60 shared-core/nv40_fifo.c | 208 +
61 shared-core/nv40_graph.c | 2055 +++++++
62 shared-core/nv40_mc.c | 39 +
63 shared-core/nv50_fifo.c | 327 ++
64 shared-core/nv50_graph.c | 316 ++
65 shared-core/nv50_mc.c | 43 +
66 shared-core/nv_drv.h | 52 +
67 shared-core/psb_drm.h | 359 ++
68 shared-core/psb_drv.h | 786 +++
69 shared-core/psb_reg.h | 555 ++
70 shared-core/r128_cce.c | 932 ++++
71 shared-core/r128_drm.h | 22 +-
72 shared-core/r128_drv.h | 523 ++
73 shared-core/r128_irq.c | 101 +
74 shared-core/r128_state.c | 1682 ++++++
75 shared-core/r300_cmdbuf.c | 954 ++++
76 shared-core/r300_reg.h | 1078 +++--
77 shared-core/radeon_cp.c | 2316 ++++++++
78 shared-core/radeon_drm.h | 29 +-
79 shared-core/radeon_drv.h | 1269 +++++
80 shared-core/radeon_irq.c | 321 ++
81 shared-core/radeon_mem.c | 302 ++
82 shared-core/radeon_state.c | 3240 +++++++++++
83 shared-core/savage_bci.c | 1095 ++++
84 shared-core/savage_drm.h | 4 +-
85 shared-core/savage_drv.h | 575 ++
86 shared-core/savage_state.c | 1165 ++++
87 shared-core/sis_drv.h | 92 +
88 shared-core/sis_ds.c | 299 +
89 shared-core/sis_ds.h | 146 +
90 shared-core/sis_mm.c | 386 ++
91 shared-core/tdfx_drv.h | 47 +
92 shared-core/via_dma.c | 719 +++
93 shared-core/via_drm.h | 40 +-
94 shared-core/via_drv.c | 161 +
95 shared-core/via_drv.h | 219 +
96 shared-core/via_ds.c | 274 +
97 shared-core/via_ds.h | 104 +
98 shared-core/via_irq.c | 393 ++
99 shared-core/via_map.c | 143 +
100 shared-core/via_mm.c | 347 ++
101 shared-core/via_mm.h | 40 +
102 shared-core/via_verifier.c | 1121 ++++
103 shared-core/via_verifier.h | 64 +
104 shared-core/via_video.c | 93 +
105 98 files changed, 58391 insertions(+), 1757 deletions(-)
106 create mode 100644 libdrm/xf86drmMode.c
107 create mode 100644 libdrm/xf86drmMode.h
108 create mode 100644 shared-core/drm_pciids.txt
109 create mode 100644 shared-core/i915_dma.c
110 create mode 100644 shared-core/i915_drv.h
111 create mode 100644 shared-core/i915_irq.c
112 create mode 100644 shared-core/i915_mem.c
113 create mode 100644 shared-core/imagine_drv.h
114 create mode 100644 shared-core/mach64_dma.c
115 create mode 100644 shared-core/mach64_drv.h
116 create mode 100644 shared-core/mach64_irq.c
117 create mode 100644 shared-core/mach64_state.c
118 create mode 100644 shared-core/mga_dma.c
119 create mode 100644 shared-core/mga_drv.h
120 create mode 100644 shared-core/mga_irq.c
121 create mode 100644 shared-core/mga_state.c
122 create mode 100644 shared-core/mga_ucode.h
123 create mode 100644 shared-core/mga_warp.c
124 create mode 100644 shared-core/nouveau_drm.h
125 create mode 100644 shared-core/nouveau_drv.h
126 create mode 100644 shared-core/nouveau_fifo.c
127 create mode 100644 shared-core/nouveau_irq.c
128 create mode 100644 shared-core/nouveau_mem.c
129 create mode 100644 shared-core/nouveau_notifier.c
130 create mode 100644 shared-core/nouveau_object.c
131 create mode 100644 shared-core/nouveau_reg.h
132 create mode 100644 shared-core/nouveau_state.c
133 create mode 100644 shared-core/nv04_fb.c
134 create mode 100644 shared-core/nv04_fifo.c
135 create mode 100644 shared-core/nv04_graph.c
136 create mode 100644 shared-core/nv04_mc.c
137 create mode 100644 shared-core/nv04_timer.c
138 create mode 100644 shared-core/nv10_fb.c
139 create mode 100644 shared-core/nv10_fifo.c
140 create mode 100644 shared-core/nv10_graph.c
141 create mode 100644 shared-core/nv20_graph.c
142 create mode 100644 shared-core/nv30_graph.c
143 create mode 100644 shared-core/nv40_fb.c
144 create mode 100644 shared-core/nv40_fifo.c
145 create mode 100644 shared-core/nv40_graph.c
146 create mode 100644 shared-core/nv40_mc.c
147 create mode 100644 shared-core/nv50_fifo.c
148 create mode 100644 shared-core/nv50_graph.c
149 create mode 100644 shared-core/nv50_mc.c
150 create mode 100644 shared-core/nv_drv.h
151 create mode 100644 shared-core/psb_drm.h
152 create mode 100644 shared-core/psb_drv.h
153 create mode 100644 shared-core/psb_reg.h
154 create mode 100644 shared-core/r128_cce.c
155 create mode 100644 shared-core/r128_drv.h
156 create mode 100644 shared-core/r128_irq.c
157 create mode 100644 shared-core/r128_state.c
158 create mode 100644 shared-core/r300_cmdbuf.c
159 create mode 100644 shared-core/radeon_cp.c
160 create mode 100644 shared-core/radeon_drv.h
161 create mode 100644 shared-core/radeon_irq.c
162 create mode 100644 shared-core/radeon_mem.c
163 create mode 100644 shared-core/radeon_state.c
164 create mode 100644 shared-core/savage_bci.c
165 create mode 100644 shared-core/savage_drv.h
166 create mode 100644 shared-core/savage_state.c
167 create mode 100644 shared-core/sis_drv.h
168 create mode 100644 shared-core/sis_ds.c
169 create mode 100644 shared-core/sis_ds.h
170 create mode 100644 shared-core/sis_mm.c
171 create mode 100644 shared-core/tdfx_drv.h
172 create mode 100644 shared-core/via_dma.c
173 create mode 100644 shared-core/via_drv.c
174 create mode 100644 shared-core/via_drv.h
175 create mode 100644 shared-core/via_ds.c
176 create mode 100644 shared-core/via_ds.h
177 create mode 100644 shared-core/via_irq.c
178 create mode 100644 shared-core/via_map.c
179 create mode 100644 shared-core/via_mm.c
180 create mode 100644 shared-core/via_mm.h
181 create mode 100644 shared-core/via_verifier.c
182 create mode 100644 shared-core/via_verifier.h
183 create mode 100644 shared-core/via_video.c
184
185Index: git/configure.ac
186===================================================================
187--- git.orig/configure.ac 2008-12-12 17:20:14.000000000 +0000
188+++ git/configure.ac 2008-12-12 17:35:22.000000000 +0000
189@@ -19,7 +19,7 @@
190 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
191
192 AC_PREREQ(2.57)
193-AC_INIT([libdrm], 2.3.0, [dri-devel@lists.sourceforge.net], libdrm)
194+AC_INIT([libdrm], 2.3.1, [dri-devel@lists.sourceforge.net], libdrm)
195 AC_CONFIG_SRCDIR([Makefile.am])
196 AM_INIT_AUTOMAKE([dist-bzip2])
197
198Index: git/libdrm/Makefile.am
199===================================================================
200--- git.orig/libdrm/Makefile.am 2008-12-12 17:20:14.000000000 +0000
201+++ git/libdrm/Makefile.am 2008-12-12 17:35:22.000000000 +0000
202@@ -23,9 +23,9 @@
203 libdrm_la_LDFLAGS = -version-number 2:3:0 -no-undefined
204
205 AM_CFLAGS = -I$(top_srcdir)/shared-core
206-libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c
207+libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c xf86drmMode.c
208
209 libdrmincludedir = ${includedir}
210-libdrminclude_HEADERS = xf86drm.h xf86mm.h
211+libdrminclude_HEADERS = xf86drm.h xf86mm.h xf86drmMode.h
212
213 EXTRA_DIST = ChangeLog TODO
214Index: git/libdrm/xf86drm.c
215===================================================================
216--- git.orig/libdrm/xf86drm.c 2008-12-12 17:20:14.000000000 +0000
217+++ git/libdrm/xf86drm.c 2008-12-12 17:35:22.000000000 +0000
218@@ -31,10 +31,6 @@
219 * DEALINGS IN THE SOFTWARE.
220 */
221
222-#ifdef HAVE_XORG_CONFIG_H
223-#include <xorg-config.h>
224-#endif
225-
226 #ifdef HAVE_CONFIG_H
227 # include <config.h>
228 #endif
229@@ -53,7 +49,6 @@
230 #include <sys/mman.h>
231 #include <sys/time.h>
232 #include <stdarg.h>
233-#include "drm.h"
234
235 /* Not all systems have MAP_FAILED defined */
236 #ifndef MAP_FAILED
237@@ -96,7 +91,7 @@
238
239 void drmSetServerInfo(drmServerInfoPtr info)
240 {
241- drm_server_info = info;
242+ drm_server_info = info;
243 }
244
245 /**
246@@ -110,7 +105,7 @@
247
248 static int drmDebugPrint(const char *format, va_list ap)
249 {
250- return vfprintf(stderr, format, ap);
251+ return vfprintf(stderr, format, ap);
252 }
253
254 static int (*drm_debug_print)(const char *format, va_list ap) = drmDebugPrint;
255@@ -135,26 +130,28 @@
256 void
257 drmSetDebugMsgFunction(int (*debug_msg_ptr)(const char *format, va_list ap))
258 {
259- drm_debug_print = debug_msg_ptr;
260+ drm_debug_print = debug_msg_ptr;
261 }
262
263 static void *drmHashTable = NULL; /* Context switch callbacks */
264
265 void *drmGetHashTable(void)
266 {
267- return drmHashTable;
268+ return drmHashTable;
269 }
270
271 void *drmMalloc(int size)
272 {
273 void *pt;
274- if ((pt = malloc(size))) memset(pt, 0, size);
275+ if ((pt = malloc(size)))
276+ memset(pt, 0, size);
277 return pt;
278 }
279
280 void drmFree(void *pt)
281 {
282- if (pt) free(pt);
283+ if (pt)
284+ free(pt);
285 }
286
287 /* drmStrdup can't use strdup(3), since it doesn't call _DRM_MALLOC... */
288@@ -190,7 +187,8 @@
289 void *value;
290 drmHashEntry *entry;
291
292- if (!drmHashTable) drmHashTable = drmHashCreate();
293+ if (!drmHashTable)
294+ drmHashTable = drmHashCreate();
295
296 if (drmHashLookup(drmHashTable, key, &value)) {
297 entry = drmMalloc(sizeof(*entry));
298@@ -280,14 +278,15 @@
299 drmMsg("drmOpenDevice: node name is %s\n", buf);
300
301 if (drm_server_info) {
302- drm_server_info->get_perms(&serv_group, &serv_mode);
303- devmode = serv_mode ? serv_mode : DRM_DEV_MODE;
304- devmode &= ~(S_IXUSR|S_IXGRP|S_IXOTH);
305- group = (serv_group >= 0) ? serv_group : DRM_DEV_GID;
306+ drm_server_info->get_perms(&serv_group, &serv_mode);
307+ devmode = serv_mode ? serv_mode : DRM_DEV_MODE;
308+ devmode &= ~(S_IXUSR|S_IXGRP|S_IXOTH);
309+ group = (serv_group >= 0) ? serv_group : DRM_DEV_GID;
310 }
311
312 if (stat(DRM_DIR_NAME, &st)) {
313- if (!isroot) return DRM_ERR_NOT_ROOT;
314+ if (!isroot)
315+ return DRM_ERR_NOT_ROOT;
316 mkdir(DRM_DIR_NAME, DRM_DEV_DIRMODE);
317 chown(DRM_DIR_NAME, 0, 0); /* root:root */
318 chmod(DRM_DIR_NAME, DRM_DEV_DIRMODE);
319@@ -295,37 +294,41 @@
320
321 /* Check if the device node exists and create it if necessary. */
322 if (stat(buf, &st)) {
323- if (!isroot) return DRM_ERR_NOT_ROOT;
324+ if (!isroot)
325+ return DRM_ERR_NOT_ROOT;
326 remove(buf);
327 mknod(buf, S_IFCHR | devmode, dev);
328 }
329
330 if (drm_server_info) {
331- chown(buf, user, group);
332- chmod(buf, devmode);
333+ chown(buf, user, group);
334+ chmod(buf, devmode);
335 }
336
337 fd = open(buf, O_RDWR, 0);
338 drmMsg("drmOpenDevice: open result is %d, (%s)\n",
339 fd, fd < 0 ? strerror(errno) : "OK");
340- if (fd >= 0) return fd;
341+ if (fd >= 0)
342+ return fd;
343
344 /* Check if the device node is not what we expect it to be, and recreate it
345 * and try again if so.
346 */
347 if (st.st_rdev != dev) {
348- if (!isroot) return DRM_ERR_NOT_ROOT;
349+ if (!isroot)
350+ return DRM_ERR_NOT_ROOT;
351 remove(buf);
352 mknod(buf, S_IFCHR | devmode, dev);
353 if (drm_server_info) {
354- chown(buf, user, group);
355- chmod(buf, devmode);
356+ chown(buf, user, group);
357+ chmod(buf, devmode);
358 }
359 }
360 fd = open(buf, O_RDWR, 0);
361 drmMsg("drmOpenDevice: open result is %d, (%s)\n",
362 fd, fd < 0 ? strerror(errno) : "OK");
363- if (fd >= 0) return fd;
364+ if (fd >= 0)
365+ return fd;
366
367 drmMsg("drmOpenDevice: Open failed\n");
368 remove(buf);
369@@ -350,10 +353,12 @@
370 int fd;
371 char buf[64];
372
373- if (create) return drmOpenDevice(makedev(DRM_MAJOR, minor), minor);
374+ if (create)
375+ return drmOpenDevice(makedev(DRM_MAJOR, minor), minor);
376
377 sprintf(buf, DRM_DEV_NAME, DRM_DIR_NAME, minor);
378- if ((fd = open(buf, O_RDWR, 0)) >= 0) return fd;
379+ if ((fd = open(buf, O_RDWR, 0)) >= 0)
380+ return fd;
381 return -errno;
382 }
383
384@@ -377,7 +382,8 @@
385 if ((fd = drmOpenMinor(0, 1)) < 0) {
386 #ifdef __linux__
387 /* Try proc for backward Linux compatibility */
388- if (!access("/proc/dri/0", R_OK)) return 1;
389+ if (!access("/proc/dri/0", R_OK))
390+ return 1;
391 #endif
392 return 0;
393 }
394@@ -428,7 +434,8 @@
395 drmFreeBusid(buf);
396 return fd;
397 }
398- if (buf) drmFreeBusid(buf);
399+ if (buf)
400+ drmFreeBusid(buf);
401 close(fd);
402 }
403 }
404@@ -458,16 +465,16 @@
405 char * id;
406
407 if (!drmAvailable()) {
408- if (!drm_server_info)
409- return -1;
410- else {
411- /* try to load the kernel module now */
412- if (!drm_server_info->load_module(name)) {
413- drmMsg("[drm] failed to load kernel module \"%s\"\n",
414- name);
415- return -1;
416- }
417- }
418+ if (!drm_server_info) {
419+ return -1;
420+ }
421+ else {
422+ /* try to load the kernel module now */
423+ if (!drm_server_info->load_module(name)) {
424+ drmMsg("[drm] failed to load kernel module \"%s\"\n", name);
425+ return -1;
426+ }
427+ }
428 }
429
430 /*
431@@ -552,16 +559,13 @@
432 if (!drmAvailable() && name != NULL && drm_server_info) {
433 /* try to load the kernel */
434 if (!drm_server_info->load_module(name)) {
435- drmMsg("[drm] failed to load kernel module \"%s\"\n",
436- name);
437+ drmMsg("[drm] failed to load kernel module \"%s\"\n", name);
438 return -1;
439 }
440 }
441
442 if (busid) {
443- int fd;
444-
445- fd = drmOpenByBusid(busid);
446+ int fd = drmOpenByBusid(busid);
447 if (fd >= 0)
448 return fd;
449 }
450@@ -584,10 +588,11 @@
451 */
452 void drmFreeVersion(drmVersionPtr v)
453 {
454- if (!v) return;
455- if (v->name) drmFree(v->name);
456- if (v->date) drmFree(v->date);
457- if (v->desc) drmFree(v->desc);
458+ if (!v)
459+ return;
460+ drmFree(v->name);
461+ drmFree(v->date);
462+ drmFree(v->desc);
463 drmFree(v);
464 }
465
466@@ -603,10 +608,11 @@
467 */
468 static void drmFreeKernelVersion(drm_version_t *v)
469 {
470- if (!v) return;
471- if (v->name) drmFree(v->name);
472- if (v->date) drmFree(v->date);
473- if (v->desc) drmFree(v->desc);
474+ if (!v)
475+ return;
476+ drmFree(v->name);
477+ drmFree(v->date);
478+ drmFree(v->desc);
479 drmFree(v);
480 }
481
482@@ -760,9 +766,11 @@
483 u.unique_len = 0;
484 u.unique = NULL;
485
486- if (ioctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) return NULL;
487+ if (ioctl(fd, DRM_IOCTL_GET_UNIQUE, &u))
488+ return NULL;
489 u.unique = drmMalloc(u.unique_len + 1);
490- if (ioctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) return NULL;
491+ if (ioctl(fd, DRM_IOCTL_GET_UNIQUE, &u))
492+ return NULL;
493 u.unique[u.unique_len] = '\0';
494
495 return u.unique;
496@@ -799,7 +807,8 @@
497 drm_auth_t auth;
498
499 *magic = 0;
500- if (ioctl(fd, DRM_IOCTL_GET_MAGIC, &auth)) return -errno;
501+ if (ioctl(fd, DRM_IOCTL_GET_MAGIC, &auth))
502+ return -errno;
503 *magic = auth.magic;
504 return 0;
505 }
506@@ -809,7 +818,8 @@
507 drm_auth_t auth;
508
509 auth.magic = magic;
510- if (ioctl(fd, DRM_IOCTL_AUTH_MAGIC, &auth)) return -errno;
511+ if (ioctl(fd, DRM_IOCTL_AUTH_MAGIC, &auth))
512+ return -errno;
513 return 0;
514 }
515
516@@ -873,8 +883,10 @@
517 map.handle = 0;
518 map.type = type;
519 map.flags = flags;
520- if (ioctl(fd, DRM_IOCTL_ADD_MAP, &map)) return -errno;
521- if (handle) *handle = (drm_handle_t)map.handle;
522+ if (ioctl(fd, DRM_IOCTL_ADD_MAP, &map))
523+ return -errno;
524+ if (handle)
525+ *handle = (drm_handle_t)map.handle;
526 return 0;
527 }
528
529@@ -884,7 +896,8 @@
530
531 map.handle = (void *)handle;
532
533- if(ioctl(fd, DRM_IOCTL_RM_MAP, &map)) return -errno;
534+ if(ioctl(fd, DRM_IOCTL_RM_MAP, &map))
535+ return -errno;
536 return 0;
537 }
538
539@@ -916,7 +929,8 @@
540 request.flags = flags;
541 request.agp_start = agp_offset;
542
543- if (ioctl(fd, DRM_IOCTL_ADD_BUFS, &request)) return -errno;
544+ if (ioctl(fd, DRM_IOCTL_ADD_BUFS, &request))
545+ return -errno;
546 return request.count;
547 }
548
549@@ -928,9 +942,11 @@
550 info.count = 0;
551 info.list = NULL;
552
553- if (ioctl(fd, DRM_IOCTL_INFO_BUFS, &info)) return -EINVAL;
554+ if (ioctl(fd, DRM_IOCTL_INFO_BUFS, &info))
555+ return -EINVAL;
556
557- if (!info.count) return -EINVAL;
558+ if (!info.count)
559+ return -EINVAL;
560
561 if (!(info.list = drmMalloc(info.count * sizeof(*info.list))))
562 return -ENOMEM;
563@@ -976,7 +992,8 @@
564
565 request.count = count;
566 request.list = list;
567- if (ioctl(fd, DRM_IOCTL_FREE_BUFS, &request)) return -errno;
568+ if (ioctl(fd, DRM_IOCTL_FREE_BUFS, &request))
569+ return -errno;
570 return 0;
571 }
572
573@@ -1024,7 +1041,8 @@
574 {
575 static unsigned long pagesize_mask = 0;
576
577- if (fd < 0) return -EINVAL;
578+ if (fd < 0)
579+ return -EINVAL;
580
581 if (!pagesize_mask)
582 pagesize_mask = getpagesize() - 1;
583@@ -1032,7 +1050,8 @@
584 size = (size + pagesize_mask) & ~pagesize_mask;
585
586 *address = mmap(0, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, handle);
587- if (*address == MAP_FAILED) return -errno;
588+ if (*address == MAP_FAILED)
589+ return -errno;
590 return 0;
591 }
592
593@@ -1062,7 +1081,8 @@
594 info.count = 0;
595 info.list = NULL;
596
597- if (ioctl(fd, DRM_IOCTL_INFO_BUFS, &info)) return NULL;
598+ if (ioctl(fd, DRM_IOCTL_INFO_BUFS, &info))
599+ return NULL;
600
601 if (info.count) {
602 if (!(info.list = drmMalloc(info.count * sizeof(*info.list))))
603@@ -1112,9 +1132,11 @@
604 bufs.count = 0;
605 bufs.list = NULL;
606 bufs.virtual = NULL;
607- if (ioctl(fd, DRM_IOCTL_MAP_BUFS, &bufs)) return NULL;
608+ if (ioctl(fd, DRM_IOCTL_MAP_BUFS, &bufs))
609+ return NULL;
610
611- if (!bufs.count) return NULL;
612+ if (!bufs.count)
613+ return NULL;
614
615 if (!(bufs.list = drmMalloc(bufs.count * sizeof(*bufs.list))))
616 return NULL;
617@@ -1269,20 +1291,25 @@
618
619 res.count = 0;
620 res.contexts = NULL;
621- if (ioctl(fd, DRM_IOCTL_RES_CTX, &res)) return NULL;
622+ if (ioctl(fd, DRM_IOCTL_RES_CTX, &res))
623+ return NULL;
624
625- if (!res.count) return NULL;
626+ if (!res.count)
627+ return NULL;
628
629- if (!(list = drmMalloc(res.count * sizeof(*list)))) return NULL;
630+ if (!(list = drmMalloc(res.count * sizeof(*list))))
631+ return NULL;
632 if (!(retval = drmMalloc(res.count * sizeof(*retval)))) {
633 drmFree(list);
634 return NULL;
635 }
636
637 res.contexts = list;
638- if (ioctl(fd, DRM_IOCTL_RES_CTX, &res)) return NULL;
639+ if (ioctl(fd, DRM_IOCTL_RES_CTX, &res))
640+ return NULL;
641
642- for (i = 0; i < res.count; i++) retval[i] = list[i].handle;
643+ for (i = 0; i < res.count; i++)
644+ retval[i] = list[i].handle;
645 drmFree(list);
646
647 *count = res.count;
648@@ -1317,7 +1344,8 @@
649 drm_ctx_t ctx;
650
651 ctx.flags = 0; /* Modified with functions below */
652- if (ioctl(fd, DRM_IOCTL_ADD_CTX, &ctx)) return -errno;
653+ if (ioctl(fd, DRM_IOCTL_ADD_CTX, &ctx))
654+ return -errno;
655 *handle = ctx.handle;
656 return 0;
657 }
658@@ -1327,7 +1355,8 @@
659 drm_ctx_t ctx;
660
661 ctx.handle = context;
662- if (ioctl(fd, DRM_IOCTL_SWITCH_CTX, &ctx)) return -errno;
663+ if (ioctl(fd, DRM_IOCTL_SWITCH_CTX, &ctx))
664+ return -errno;
665 return 0;
666 }
667
668@@ -1343,9 +1372,12 @@
669 */
670 ctx.handle = context;
671 ctx.flags = 0;
672- if (flags & DRM_CONTEXT_PRESERVED) ctx.flags |= _DRM_CONTEXT_PRESERVED;
673- if (flags & DRM_CONTEXT_2DONLY) ctx.flags |= _DRM_CONTEXT_2DONLY;
674- if (ioctl(fd, DRM_IOCTL_MOD_CTX, &ctx)) return -errno;
675+ if (flags & DRM_CONTEXT_PRESERVED)
676+ ctx.flags |= _DRM_CONTEXT_PRESERVED;
677+ if (flags & DRM_CONTEXT_2DONLY)
678+ ctx.flags |= _DRM_CONTEXT_2DONLY;
679+ if (ioctl(fd, DRM_IOCTL_MOD_CTX, &ctx))
680+ return -errno;
681 return 0;
682 }
683
684@@ -1355,10 +1387,13 @@
685 drm_ctx_t ctx;
686
687 ctx.handle = context;
688- if (ioctl(fd, DRM_IOCTL_GET_CTX, &ctx)) return -errno;
689+ if (ioctl(fd, DRM_IOCTL_GET_CTX, &ctx))
690+ return -errno;
691 *flags = 0;
692- if (ctx.flags & _DRM_CONTEXT_PRESERVED) *flags |= DRM_CONTEXT_PRESERVED;
693- if (ctx.flags & _DRM_CONTEXT_2DONLY) *flags |= DRM_CONTEXT_2DONLY;
694+ if (ctx.flags & _DRM_CONTEXT_PRESERVED)
695+ *flags |= DRM_CONTEXT_PRESERVED;
696+ if (ctx.flags & _DRM_CONTEXT_2DONLY)
697+ *flags |= DRM_CONTEXT_2DONLY;
698 return 0;
699 }
700
701@@ -1383,14 +1418,16 @@
702 {
703 drm_ctx_t ctx;
704 ctx.handle = handle;
705- if (ioctl(fd, DRM_IOCTL_RM_CTX, &ctx)) return -errno;
706+ if (ioctl(fd, DRM_IOCTL_RM_CTX, &ctx))
707+ return -errno;
708 return 0;
709 }
710
711 int drmCreateDrawable(int fd, drm_drawable_t *handle)
712 {
713 drm_draw_t draw;
714- if (ioctl(fd, DRM_IOCTL_ADD_DRAW, &draw)) return -errno;
715+ if (ioctl(fd, DRM_IOCTL_ADD_DRAW, &draw))
716+ return -errno;
717 *handle = draw.handle;
718 return 0;
719 }
720@@ -1399,7 +1436,8 @@
721 {
722 drm_draw_t draw;
723 draw.handle = handle;
724- if (ioctl(fd, DRM_IOCTL_RM_DRAW, &draw)) return -errno;
725+ if (ioctl(fd, DRM_IOCTL_RM_DRAW, &draw))
726+ return -errno;
727 return 0;
728 }
729
730@@ -1414,7 +1452,8 @@
731 update.num = num;
732 update.data = (unsigned long long)(unsigned long)data;
733
734- if (ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update)) return -errno;
735+ if (ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update))
736+ return -errno;
737
738 return 0;
739 }
740@@ -1433,7 +1472,8 @@
741 */
742 int drmAgpAcquire(int fd)
743 {
744- if (ioctl(fd, DRM_IOCTL_AGP_ACQUIRE, NULL)) return -errno;
745+ if (ioctl(fd, DRM_IOCTL_AGP_ACQUIRE, NULL))
746+ return -errno;
747 return 0;
748 }
749
750@@ -1450,7 +1490,8 @@
751 */
752 int drmAgpRelease(int fd)
753 {
754- if (ioctl(fd, DRM_IOCTL_AGP_RELEASE, NULL)) return -errno;
755+ if (ioctl(fd, DRM_IOCTL_AGP_RELEASE, NULL))
756+ return -errno;
757 return 0;
758 }
759
760@@ -1472,7 +1513,8 @@
761 drm_agp_mode_t m;
762
763 m.mode = mode;
764- if (ioctl(fd, DRM_IOCTL_AGP_ENABLE, &m)) return -errno;
765+ if (ioctl(fd, DRM_IOCTL_AGP_ENABLE, &m))
766+ return -errno;
767 return 0;
768 }
769
770@@ -1502,8 +1544,10 @@
771 b.size = size;
772 b.handle = 0;
773 b.type = type;
774- if (ioctl(fd, DRM_IOCTL_AGP_ALLOC, &b)) return -errno;
775- if (address != 0UL) *address = b.physical;
776+ if (ioctl(fd, DRM_IOCTL_AGP_ALLOC, &b))
777+ return -errno;
778+ if (address != 0UL)
779+ *address = b.physical;
780 *handle = b.handle;
781 return 0;
782 }
783@@ -1527,7 +1571,8 @@
784
785 b.size = 0;
786 b.handle = handle;
787- if (ioctl(fd, DRM_IOCTL_AGP_FREE, &b)) return -errno;
788+ if (ioctl(fd, DRM_IOCTL_AGP_FREE, &b))
789+ return -errno;
790 return 0;
791 }
792
793@@ -1551,7 +1596,8 @@
794
795 b.handle = handle;
796 b.offset = offset;
797- if (ioctl(fd, DRM_IOCTL_AGP_BIND, &b)) return -errno;
798+ if (ioctl(fd, DRM_IOCTL_AGP_BIND, &b))
799+ return -errno;
800 return 0;
801 }
802
803@@ -1574,7 +1620,8 @@
804
805 b.handle = handle;
806 b.offset = 0;
807- if (ioctl(fd, DRM_IOCTL_AGP_UNBIND, &b)) return -errno;
808+ if (ioctl(fd, DRM_IOCTL_AGP_UNBIND, &b))
809+ return -errno;
810 return 0;
811 }
812
813@@ -1594,7 +1641,8 @@
814 {
815 drm_agp_info_t i;
816
817- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return -errno;
818+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
819+ return -errno;
820 return i.agp_version_major;
821 }
822
823@@ -1614,7 +1662,8 @@
824 {
825 drm_agp_info_t i;
826
827- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return -errno;
828+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
829+ return -errno;
830 return i.agp_version_minor;
831 }
832
833@@ -1634,7 +1683,8 @@
834 {
835 drm_agp_info_t i;
836
837- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
838+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
839+ return 0;
840 return i.mode;
841 }
842
843@@ -1654,7 +1704,8 @@
844 {
845 drm_agp_info_t i;
846
847- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
848+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
849+ return 0;
850 return i.aperture_base;
851 }
852
853@@ -1674,7 +1725,8 @@
854 {
855 drm_agp_info_t i;
856
857- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
858+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
859+ return 0;
860 return i.aperture_size;
861 }
862
863@@ -1694,7 +1746,8 @@
864 {
865 drm_agp_info_t i;
866
867- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
868+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
869+ return 0;
870 return i.memory_used;
871 }
872
873@@ -1714,7 +1767,8 @@
874 {
875 drm_agp_info_t i;
876
877- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
878+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
879+ return 0;
880 return i.memory_allowed;
881 }
882
883@@ -1734,7 +1788,8 @@
884 {
885 drm_agp_info_t i;
886
887- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
888+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
889+ return 0;
890 return i.id_vendor;
891 }
892
893@@ -1754,7 +1809,8 @@
894 {
895 drm_agp_info_t i;
896
897- if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i)) return 0;
898+ if (ioctl(fd, DRM_IOCTL_AGP_INFO, &i))
899+ return 0;
900 return i.id_device;
901 }
902
903@@ -1765,7 +1821,8 @@
904 *handle = 0;
905 sg.size = size;
906 sg.handle = 0;
907- if (ioctl(fd, DRM_IOCTL_SG_ALLOC, &sg)) return -errno;
908+ if (ioctl(fd, DRM_IOCTL_SG_ALLOC, &sg))
909+ return -errno;
910 *handle = sg.handle;
911 return 0;
912 }
913@@ -1776,7 +1833,8 @@
914
915 sg.size = 0;
916 sg.handle = handle;
917- if (ioctl(fd, DRM_IOCTL_SG_FREE, &sg)) return -errno;
918+ if (ioctl(fd, DRM_IOCTL_SG_FREE, &sg))
919+ return -errno;
920 return 0;
921 }
922
923@@ -1806,12 +1864,21 @@
924 int drmError(int err, const char *label)
925 {
926 switch (err) {
927- case DRM_ERR_NO_DEVICE: fprintf(stderr, "%s: no device\n", label); break;
928- case DRM_ERR_NO_ACCESS: fprintf(stderr, "%s: no access\n", label); break;
929- case DRM_ERR_NOT_ROOT: fprintf(stderr, "%s: not root\n", label); break;
930- case DRM_ERR_INVALID: fprintf(stderr, "%s: invalid args\n", label);break;
931+ case DRM_ERR_NO_DEVICE:
932+ fprintf(stderr, "%s: no device\n", label);
933+ break;
934+ case DRM_ERR_NO_ACCESS:
935+ fprintf(stderr, "%s: no access\n", label);
936+ break;
937+ case DRM_ERR_NOT_ROOT:
938+ fprintf(stderr, "%s: not root\n", label);
939+ break;
940+ case DRM_ERR_INVALID:
941+ fprintf(stderr, "%s: invalid args\n", label);
942+ break;
943 default:
944- if (err < 0) err = -err;
945+ if (err < 0)
946+ err = -err;
947 fprintf( stderr, "%s: error %d (%s)\n", label, err, strerror(err) );
948 break;
949 }
950@@ -1837,7 +1904,8 @@
951
952 ctl.func = DRM_INST_HANDLER;
953 ctl.irq = irq;
954- if (ioctl(fd, DRM_IOCTL_CONTROL, &ctl)) return -errno;
955+ if (ioctl(fd, DRM_IOCTL_CONTROL, &ctl))
956+ return -errno;
957 return 0;
958 }
959
960@@ -1859,7 +1927,8 @@
961
962 ctl.func = DRM_UNINST_HANDLER;
963 ctl.irq = 0;
964- if (ioctl(fd, DRM_IOCTL_CONTROL, &ctl)) return -errno;
965+ if (ioctl(fd, DRM_IOCTL_CONTROL, &ctl))
966+ return -errno;
967 return 0;
968 }
969
970@@ -1875,7 +1944,8 @@
971 if (flags & DRM_LOCK_FLUSH_ALL) lock.flags |= _DRM_LOCK_FLUSH_ALL;
972 if (flags & DRM_HALT_ALL_QUEUES) lock.flags |= _DRM_HALT_ALL_QUEUES;
973 if (flags & DRM_HALT_CUR_QUEUES) lock.flags |= _DRM_HALT_CUR_QUEUES;
974- if (ioctl(fd, DRM_IOCTL_FINISH, &lock)) return -errno;
975+ if (ioctl(fd, DRM_IOCTL_FINISH, &lock))
976+ return -errno;
977 return 0;
978 }
979
980@@ -1900,7 +1970,8 @@
981 p.busnum = busnum;
982 p.devnum = devnum;
983 p.funcnum = funcnum;
984- if (ioctl(fd, DRM_IOCTL_IRQ_BUSID, &p)) return -errno;
985+ if (ioctl(fd, DRM_IOCTL_IRQ_BUSID, &p))
986+ return -errno;
987 return p.irq;
988 }
989
990@@ -1927,7 +1998,8 @@
991 drmHashEntry *entry = drmGetEntry(fd);
992 void *value;
993
994- if (drmHashLookup(entry->tagTable, context, &value)) return NULL;
995+ if (drmHashLookup(entry->tagTable, context, &value))
996+ return NULL;
997
998 return value;
999 }
1000@@ -1940,7 +2012,8 @@
1001 map.ctx_id = ctx_id;
1002 map.handle = (void *)handle;
1003
1004- if (ioctl(fd, DRM_IOCTL_SET_SAREA_CTX, &map)) return -errno;
1005+ if (ioctl(fd, DRM_IOCTL_SET_SAREA_CTX, &map))
1006+ return -errno;
1007 return 0;
1008 }
1009
1010@@ -1951,8 +2024,10 @@
1011
1012 map.ctx_id = ctx_id;
1013
1014- if (ioctl(fd, DRM_IOCTL_GET_SAREA_CTX, &map)) return -errno;
1015- if (handle) *handle = (drm_handle_t)map.handle;
1016+ if (ioctl(fd, DRM_IOCTL_GET_SAREA_CTX, &map))
1017+ return -errno;
1018+ if (handle)
1019+ *handle = (drm_handle_t)map.handle;
1020
1021 return 0;
1022 }
1023@@ -1964,7 +2039,8 @@
1024 drm_map_t map;
1025
1026 map.offset = idx;
1027- if (ioctl(fd, DRM_IOCTL_GET_MAP, &map)) return -errno;
1028+ if (ioctl(fd, DRM_IOCTL_GET_MAP, &map))
1029+ return -errno;
1030 *offset = map.offset;
1031 *size = map.size;
1032 *type = map.type;
1033@@ -1980,7 +2056,8 @@
1034 drm_client_t client;
1035
1036 client.idx = idx;
1037- if (ioctl(fd, DRM_IOCTL_GET_CLIENT, &client)) return -errno;
1038+ if (ioctl(fd, DRM_IOCTL_GET_CLIENT, &client))
1039+ return -errno;
1040 *auth = client.auth;
1041 *pid = client.pid;
1042 *uid = client.uid;
1043@@ -1994,7 +2071,8 @@
1044 drm_stats_t s;
1045 int i;
1046
1047- if (ioctl(fd, DRM_IOCTL_GET_STATS, &s)) return -errno;
1048+ if (ioctl(fd, DRM_IOCTL_GET_STATS, &s))
1049+ return -errno;
1050
1051 stats->count = 0;
1052 memset(stats, 0, sizeof(*stats));
1053@@ -2267,19 +2345,20 @@
1054 * DRM_FENCE_MASK_DRIVER
1055 */
1056
1057-int drmFenceCreate(int fd, unsigned flags, int class,unsigned type,
1058+int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
1059 drmFence *fence)
1060 {
1061 drm_fence_arg_t arg;
1062-
1063+
1064 memset(&arg, 0, sizeof(arg));
1065+ arg.flags = flags;
1066 arg.type = type;
1067- arg.class = class;
1068- arg.op = drm_fence_create;
1069- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1070+ arg.fence_class = fence_class;
1071+
1072+ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
1073 return -errno;
1074 fence->handle = arg.handle;
1075- fence->class = arg.class;
1076+ fence->fence_class = arg.fence_class;
1077 fence->type = arg.type;
1078 fence->flags = arg.flags;
1079 fence->signaled = 0;
1080@@ -2292,46 +2371,36 @@
1081 * DRM_FENCE_MASK_DRIVER
1082 */
1083
1084-int drmFenceBuffers(int fd, unsigned flags, drmFence *fence)
1085+int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
1086 {
1087 drm_fence_arg_t arg;
1088-
1089+
1090 memset(&arg, 0, sizeof(arg));
1091 arg.flags = flags;
1092- arg.op = drm_fence_buffers;
1093- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1094+ arg.fence_class = fence_class;
1095+
1096+ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
1097 return -errno;
1098 fence->handle = arg.handle;
1099- fence->class = arg.class;
1100+ fence->fence_class = arg.fence_class;
1101 fence->type = arg.type;
1102 fence->flags = arg.flags;
1103+ fence->sequence = arg.sequence;
1104 fence->signaled = 0;
1105 return 0;
1106 }
1107-
1108-int drmFenceDestroy(int fd, const drmFence *fence)
1109-{
1110- drm_fence_arg_t arg;
1111-
1112- memset(&arg, 0, sizeof(arg));
1113- arg.handle = fence->handle;
1114- arg.op = drm_fence_destroy;
1115- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1116- return -errno;
1117- return 0;
1118-}
1119
1120 int drmFenceReference(int fd, unsigned handle, drmFence *fence)
1121 {
1122 drm_fence_arg_t arg;
1123-
1124+
1125 memset(&arg, 0, sizeof(arg));
1126 arg.handle = handle;
1127- arg.op = drm_fence_reference;
1128- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1129+
1130+ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
1131 return -errno;
1132 fence->handle = arg.handle;
1133- fence->class = arg.class;
1134+ fence->fence_class = arg.fence_class;
1135 fence->type = arg.type;
1136 fence->flags = arg.flags;
1137 fence->signaled = arg.signaled;
1138@@ -2341,11 +2410,11 @@
1139 int drmFenceUnreference(int fd, const drmFence *fence)
1140 {
1141 drm_fence_arg_t arg;
1142-
1143+
1144 memset(&arg, 0, sizeof(arg));
1145 arg.handle = fence->handle;
1146- arg.op = drm_fence_unreference;
1147- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1148+
1149+ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
1150 return -errno;
1151 return 0;
1152 }
1153@@ -2353,29 +2422,29 @@
1154 int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
1155 {
1156 drm_fence_arg_t arg;
1157-
1158+
1159 memset(&arg, 0, sizeof(arg));
1160 arg.handle = fence->handle;
1161 arg.type = flush_type;
1162- arg.op = drm_fence_flush;
1163- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1164+
1165+ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
1166 return -errno;
1167- fence->class = arg.class;
1168+ fence->fence_class = arg.fence_class;
1169 fence->type = arg.type;
1170 fence->signaled = arg.signaled;
1171- return 0;
1172+ return arg.error;
1173 }
1174
1175 int drmFenceUpdate(int fd, drmFence *fence)
1176 {
1177- drm_fence_arg_t arg;
1178-
1179+ drm_fence_arg_t arg;
1180+
1181 memset(&arg, 0, sizeof(arg));
1182 arg.handle = fence->handle;
1183- arg.op = drm_fence_signaled;
1184- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1185+
1186+ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
1187 return -errno;
1188- fence->class = arg.class;
1189+ fence->fence_class = arg.fence_class;
1190 fence->type = arg.type;
1191 fence->signaled = arg.signaled;
1192 return 0;
1193@@ -2384,13 +2453,9 @@
1194 int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
1195 int *signaled)
1196 {
1197- int
1198- ret;
1199-
1200 if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
1201 ((fenceType & fence->signaled) != fenceType)) {
1202-
1203- ret = drmFenceFlush(fd, fence, fenceType);
1204+ int ret = drmFenceFlush(fd, fence, fenceType);
1205 if (ret)
1206 return ret;
1207 }
1208@@ -2410,17 +2475,19 @@
1209 int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
1210 {
1211 drm_fence_arg_t arg;
1212-
1213+
1214 memset(&arg, 0, sizeof(arg));
1215+ arg.fence_class = fence->fence_class;
1216 arg.flags = flags;
1217 arg.handle = fence->handle;
1218 arg.type = emit_type;
1219- arg.op = drm_fence_emit;
1220- if (ioctl(fd, DRM_IOCTL_FENCE, &arg))
1221+
1222+ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
1223 return -errno;
1224- fence->class = arg.class;
1225+ fence->fence_class = arg.fence_class;
1226 fence->type = arg.type;
1227 fence->signaled = arg.signaled;
1228+ fence->sequence = arg.sequence;
1229 return 0;
1230 }
1231
1232@@ -2429,7 +2496,50 @@
1233 * DRM_FENCE_FLAG_WAIT_LAZY
1234 * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
1235 */
1236+
1237+#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
1238+
1239+static unsigned long
1240+drmTimeDiff(struct timeval *now, struct timeval *then)
1241+{
1242+ uint64_t val;
1243+
1244+ val = now->tv_sec - then->tv_sec;
1245+ val *= 1000000LL;
1246+ val += now->tv_usec;
1247+ val -= then->tv_usec;
1248+
1249+ return (unsigned long) val;
1250+}
1251+
1252+static int
1253+drmIoctlTimeout(int fd, unsigned long request, void *argp)
1254+{
1255+ int haveThen = 0;
1256+ struct timeval then, now;
1257+ int ret;
1258+
1259+ do {
1260+ ret = ioctl(fd, request, argp);
1261+ if (ret != 0 && errno == EAGAIN) {
1262+ if (!haveThen) {
1263+ gettimeofday(&then, NULL);
1264+ haveThen = 1;
1265+ }
1266+ gettimeofday(&now, NULL);
1267+ }
1268+ } while (ret != 0 && errno == EAGAIN &&
1269+ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
1270+
1271+ if (ret != 0)
1272+ return ((errno == EAGAIN) ? -EBUSY : -errno);
1273+
1274+ return 0;
1275+}
1276
1277+
1278+
1279+
1280 int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
1281 {
1282 drm_fence_arg_t arg;
1283@@ -2449,160 +2559,19 @@
1284 arg.handle = fence->handle;
1285 arg.type = flush_type;
1286 arg.flags = flags;
1287- arg.op = drm_fence_wait;
1288- do {
1289- ret = ioctl(fd, DRM_IOCTL_FENCE, &arg);
1290- } while (ret != 0 && errno == EAGAIN);
1291
1292+
1293+ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
1294 if (ret)
1295- return -errno;
1296+ return ret;
1297
1298- fence->class = arg.class;
1299+ fence->fence_class = arg.fence_class;
1300 fence->type = arg.type;
1301 fence->signaled = arg.signaled;
1302- return 0;
1303+ return arg.error;
1304 }
1305
1306-static int drmAdjustListNodes(drmBOList *list)
1307-{
1308- drmBONode *node;
1309- drmMMListHead *l;
1310- int ret = 0;
1311-
1312- while(list->numCurrent < list->numTarget) {
1313- node = (drmBONode *) malloc(sizeof(*node));
1314- if (!node) {
1315- ret = -ENOMEM;
1316- break;
1317- }
1318- list->numCurrent++;
1319- DRMLISTADD(&node->head, &list->free);
1320- }
1321-
1322- while(list->numCurrent > list->numTarget) {
1323- l = list->free.next;
1324- if (l == &list->free)
1325- break;
1326- DRMLISTDEL(l);
1327- node = DRMLISTENTRY(drmBONode, l, head);
1328- free(node);
1329- list->numCurrent--;
1330- }
1331- return ret;
1332-}
1333-
1334-void drmBOFreeList(drmBOList *list)
1335-{
1336- drmBONode *node;
1337- drmMMListHead *l;
1338-
1339- l = list->list.next;
1340- while(l != &list->list) {
1341- DRMLISTDEL(l);
1342- node = DRMLISTENTRY(drmBONode, l, head);
1343- free(node);
1344- l = list->free.next;
1345- list->numCurrent--;
1346- list->numOnList--;
1347- }
1348-
1349- l = list->free.next;
1350- while(l != &list->free) {
1351- DRMLISTDEL(l);
1352- node = DRMLISTENTRY(drmBONode, l, head);
1353- free(node);
1354- l = list->free.next;
1355- list->numCurrent--;
1356- }
1357-}
1358-
1359-int drmBOResetList(drmBOList *list) {
1360-
1361- drmMMListHead *l;
1362- int ret;
1363-
1364- ret = drmAdjustListNodes(list);
1365- if (ret)
1366- return ret;
1367-
1368- l = list->list.next;
1369- while(l != &list->list) {
1370- DRMLISTDEL(l);
1371- DRMLISTADD(l, &list->free);
1372- list->numOnList--;
1373- l = list->list.next;
1374- }
1375- return drmAdjustListNodes(list);
1376-}
1377-
1378-static drmBONode *drmAddListItem(drmBOList *list, drmBO *item,
1379- unsigned long arg0,
1380- unsigned long arg1)
1381-{
1382- drmBONode *node;
1383- drmMMListHead *l;
1384-
1385- l = list->free.next;
1386- if (l == &list->free) {
1387- node = (drmBONode *) malloc(sizeof(*node));
1388- if (!node) {
1389- return NULL;
1390- }
1391- list->numCurrent++;
1392- } else {
1393- DRMLISTDEL(l);
1394- node = DRMLISTENTRY(drmBONode, l, head);
1395- }
1396- node->buf = item;
1397- node->arg0 = arg0;
1398- node->arg1 = arg1;
1399- DRMLISTADD(&node->head, &list->list);
1400- list->numOnList++;
1401- return node;
1402-}
1403-
1404-void *drmBOListIterator(drmBOList *list)
1405-{
1406- void *ret = list->list.next;
1407-
1408- if (ret == &list->list)
1409- return NULL;
1410- return ret;
1411-}
1412-
1413-void *drmBOListNext(drmBOList *list, void *iterator)
1414-{
1415- void *ret;
1416-
1417- drmMMListHead *l = (drmMMListHead *) iterator;
1418- ret = l->next;
1419- if (ret == &list->list)
1420- return NULL;
1421- return ret;
1422-}
1423-
1424-drmBO *drmBOListBuf(void *iterator)
1425-{
1426- drmBONode *node;
1427- drmMMListHead *l = (drmMMListHead *) iterator;
1428- node = DRMLISTENTRY(drmBONode, l, head);
1429-
1430- return node->buf;
1431-}
1432-
1433-
1434-int drmBOCreateList(int numTarget, drmBOList *list)
1435-{
1436- DRMINITLISTHEAD(&list->list);
1437- DRMINITLISTHEAD(&list->free);
1438- list->numTarget = numTarget;
1439- list->numCurrent = 0;
1440- list->numOnList = 0;
1441- return drmAdjustListNodes(list);
1442-}
1443-
1444-static void drmBOCopyReply(const drm_bo_arg_reply_t *rep,
1445- drmBO *buf)
1446+static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
1447 {
1448 buf->handle = rep->handle;
1449 buf->flags = rep->flags;
1450@@ -2614,18 +2583,21 @@
1451 buf->fenceFlags = rep->fence_flags;
1452 buf->replyFlags = rep->rep_flags;
1453 buf->pageAlignment = rep->page_alignment;
1454+ buf->tileInfo = rep->tile_info;
1455+ buf->hwTileStride = rep->hw_tile_stride;
1456+ buf->desiredTileStride = rep->desired_tile_stride;
1457 }
1458-
1459-
1460
1461-int drmBOCreate(int fd, unsigned long start, unsigned long size,
1462- unsigned pageAlignment, void *user_buffer, drm_bo_type_t type,
1463- unsigned mask,
1464+
1465+
1466+int drmBOCreate(int fd, unsigned long size,
1467+ unsigned pageAlignment, void *user_buffer,
1468+ uint64_t mask,
1469 unsigned hint, drmBO *buf)
1470 {
1471- drm_bo_arg_t arg;
1472- drm_bo_arg_request_t *req = &arg.d.req;
1473- drm_bo_arg_reply_t *rep = &arg.d.rep;
1474+ struct drm_bo_create_arg arg;
1475+ struct drm_bo_create_req *req = &arg.d.req;
1476+ struct drm_bo_info_rep *rep = &arg.d.rep;
1477 int ret;
1478
1479 memset(buf, 0, sizeof(*buf));
1480@@ -2633,99 +2605,35 @@
1481 req->mask = mask;
1482 req->hint = hint;
1483 req->size = size;
1484- req->type = type;
1485 req->page_alignment = pageAlignment;
1486+ req->buffer_start = (unsigned long) user_buffer;
1487
1488 buf->virtual = NULL;
1489
1490- switch(type) {
1491- case drm_bo_type_dc:
1492- req->buffer_start = start;
1493- break;
1494- case drm_bo_type_user:
1495- req->buffer_start = (unsigned long) user_buffer;
1496- buf->virtual = user_buffer;
1497- break;
1498- case drm_bo_type_fake:
1499- req->buffer_start = start;
1500- break;
1501- default:
1502- return -EINVAL;
1503- }
1504- req->op = drm_bo_create;
1505-
1506- do {
1507- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1508- } while (ret != 0 && errno == EAGAIN);
1509-
1510+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
1511 if (ret)
1512- return -errno;
1513- if (!arg.handled) {
1514- return -EFAULT;
1515- }
1516- if (rep->ret) {
1517- fprintf(stderr, "Error %d\n", rep->ret);
1518- return rep->ret;
1519- }
1520-
1521+ return ret;
1522+
1523 drmBOCopyReply(rep, buf);
1524- buf->mapVirtual = NULL;
1525+ buf->virtual = user_buffer;
1526 buf->mapCount = 0;
1527
1528 return 0;
1529 }
1530
1531-int drmBODestroy(int fd, drmBO *buf)
1532-{
1533- drm_bo_arg_t arg;
1534- drm_bo_arg_request_t *req = &arg.d.req;
1535- drm_bo_arg_reply_t *rep = &arg.d.rep;
1536-
1537- if (buf->mapVirtual && (buf->type != drm_bo_type_fake)) {
1538- (void) drmUnmap(buf->mapVirtual, buf->start + buf->size);
1539- buf->mapVirtual = NULL;
1540- buf->virtual = NULL;
1541- }
1542-
1543- memset(&arg, 0, sizeof(arg));
1544- req->handle = buf->handle;
1545- req->op = drm_bo_destroy;
1546-
1547- if (ioctl(fd, DRM_IOCTL_BUFOBJ, &arg))
1548- return -errno;
1549- if (!arg.handled) {
1550- return -EFAULT;
1551- }
1552- if (rep->ret) {
1553- return rep->ret;
1554- }
1555-
1556- buf->handle = 0;
1557- return 0;
1558-}
1559-
1560 int drmBOReference(int fd, unsigned handle, drmBO *buf)
1561 {
1562-
1563- drm_bo_arg_t arg;
1564- drm_bo_arg_request_t *req = &arg.d.req;
1565- drm_bo_arg_reply_t *rep = &arg.d.rep;
1566+ struct drm_bo_reference_info_arg arg;
1567+ struct drm_bo_handle_arg *req = &arg.d.req;
1568+ struct drm_bo_info_rep *rep = &arg.d.rep;
1569
1570 memset(&arg, 0, sizeof(arg));
1571 req->handle = handle;
1572- req->op = drm_bo_reference;
1573
1574- if (ioctl(fd, DRM_IOCTL_BUFOBJ, &arg))
1575+ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
1576 return -errno;
1577- if (!arg.handled) {
1578- return -EFAULT;
1579- }
1580- if (rep->ret) {
1581- return rep->ret;
1582- }
1583
1584 drmBOCopyReply(rep, buf);
1585- buf->type = drm_bo_type_dc;
1586 buf->mapVirtual = NULL;
1587 buf->mapCount = 0;
1588 buf->virtual = NULL;
1589@@ -2733,36 +2641,27 @@
1590 return 0;
1591 }
1592
1593-int drmBOUnReference(int fd, drmBO *buf)
1594+int drmBOUnreference(int fd, drmBO *buf)
1595 {
1596- drm_bo_arg_t arg;
1597- drm_bo_arg_request_t *req = &arg.d.req;
1598- drm_bo_arg_reply_t *rep = &arg.d.rep;
1599-
1600+ struct drm_bo_handle_arg arg;
1601
1602- if (buf->mapVirtual && (buf->type != drm_bo_type_fake)) {
1603+ if (buf->mapVirtual && buf->mapHandle) {
1604 (void) munmap(buf->mapVirtual, buf->start + buf->size);
1605 buf->mapVirtual = NULL;
1606 buf->virtual = NULL;
1607 }
1608
1609 memset(&arg, 0, sizeof(arg));
1610- req->handle = buf->handle;
1611- req->op = drm_bo_unreference;
1612+ arg.handle = buf->handle;
1613
1614- if (ioctl(fd, DRM_IOCTL_BUFOBJ, &arg))
1615+ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
1616 return -errno;
1617- if (!arg.handled) {
1618- return -EFAULT;
1619- }
1620- if (rep->ret) {
1621- return rep->ret;
1622- }
1623
1624 buf->handle = 0;
1625 return 0;
1626 }
1627
1628+
1629 /*
1630 * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
1631 * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
1632@@ -2772,17 +2671,16 @@
1633 int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
1634 void **address)
1635 {
1636-
1637- drm_bo_arg_t arg;
1638- drm_bo_arg_request_t *req = &arg.d.req;
1639- drm_bo_arg_reply_t *rep = &arg.d.rep;
1640+ struct drm_bo_map_wait_idle_arg arg;
1641+ struct drm_bo_info_req *req = &arg.d.req;
1642+ struct drm_bo_info_rep *rep = &arg.d.rep;
1643 int ret = 0;
1644
1645 /*
1646 * Make sure we have a virtual address of the buffer.
1647 */
1648
1649- if (!buf->virtual && buf->type != drm_bo_type_fake) {
1650+ if (!buf->virtual) {
1651 drmAddress virtual;
1652 virtual = mmap(0, buf->size + buf->start,
1653 PROT_READ | PROT_WRITE, MAP_SHARED,
1654@@ -2800,23 +2698,15 @@
1655 req->handle = buf->handle;
1656 req->mask = mapFlags;
1657 req->hint = mapHint;
1658- req->op = drm_bo_map;
1659
1660 /*
1661 * May hang if the buffer object is busy.
1662 * This IOCTL synchronizes the buffer.
1663 */
1664
1665- do {
1666- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1667- } while (ret != 0 && errno == EAGAIN);
1668-
1669- if (ret)
1670+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
1671+ if (ret)
1672 return ret;
1673- if (!arg.handled)
1674- return -EFAULT;
1675- if (rep->ret)
1676- return rep->ret;
1677
1678 drmBOCopyReply(rep, buf);
1679 buf->mapFlags = mapFlags;
1680@@ -2826,130 +2716,85 @@
1681 return 0;
1682 }
1683
1684+
1685 int drmBOUnmap(int fd, drmBO *buf)
1686 {
1687- drm_bo_arg_t arg;
1688- drm_bo_arg_request_t *req = &arg.d.req;
1689- drm_bo_arg_reply_t *rep = &arg.d.rep;
1690+ struct drm_bo_handle_arg arg;
1691
1692-
1693 memset(&arg, 0, sizeof(arg));
1694- req->handle = buf->handle;
1695- req->op = drm_bo_unmap;
1696+ arg.handle = buf->handle;
1697
1698- if (ioctl(fd, DRM_IOCTL_BUFOBJ, &arg)) {
1699+ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
1700 return -errno;
1701 }
1702- if (!arg.handled)
1703- return -EFAULT;
1704- if (rep->ret)
1705- return rep->ret;
1706-
1707+ buf->mapCount--;
1708 return 0;
1709 }
1710-
1711-int drmBOValidate(int fd, drmBO *buf, unsigned flags, unsigned mask,
1712- unsigned hint)
1713+
1714+int drmBOSetStatus(int fd, drmBO *buf,
1715+ uint64_t flags, uint64_t mask,
1716+ unsigned int hint,
1717+ unsigned int desired_tile_stride,
1718+ unsigned int tile_info)
1719 {
1720- drm_bo_arg_t arg;
1721- drm_bo_arg_request_t *req = &arg.d.req;
1722- drm_bo_arg_reply_t *rep = &arg.d.rep;
1723+
1724+ struct drm_bo_map_wait_idle_arg arg;
1725+ struct drm_bo_info_req *req = &arg.d.req;
1726+ struct drm_bo_info_rep *rep = &arg.d.rep;
1727 int ret = 0;
1728
1729 memset(&arg, 0, sizeof(arg));
1730+ req->mask = mask;
1731+ req->flags = flags;
1732 req->handle = buf->handle;
1733- req->mask = flags;
1734 req->hint = hint;
1735- req->arg_handle = mask; /* Encode mask in the arg_handle field :/ */
1736- req->op = drm_bo_validate;
1737-
1738- do{
1739- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1740- } while (ret && errno == EAGAIN);
1741+ req->desired_tile_stride = desired_tile_stride;
1742+ req->tile_info = tile_info;
1743
1744+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
1745 if (ret)
1746- return ret;
1747- if (!arg.handled)
1748- return -EFAULT;
1749- if (rep->ret)
1750- return rep->ret;
1751+ return ret;
1752
1753 drmBOCopyReply(rep, buf);
1754 return 0;
1755 }
1756
1757
1758-int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle)
1759-{
1760- drm_bo_arg_t arg;
1761- drm_bo_arg_request_t *req = &arg.d.req;
1762- drm_bo_arg_reply_t *rep = &arg.d.rep;
1763- int ret = 0;
1764-
1765- memset(&arg, 0, sizeof(arg));
1766- req->handle = buf->handle;
1767- req->mask = flags;
1768- req->arg_handle = fenceHandle;
1769- req->op = drm_bo_validate;
1770-
1771- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1772-
1773- if (ret)
1774- return ret;
1775- if (!arg.handled)
1776- return -EFAULT;
1777- if (rep->ret)
1778- return rep->ret;
1779- return 0;
1780-}
1781-
1782 int drmBOInfo(int fd, drmBO *buf)
1783 {
1784- drm_bo_arg_t arg;
1785- drm_bo_arg_request_t *req = &arg.d.req;
1786- drm_bo_arg_reply_t *rep = &arg.d.rep;
1787+ struct drm_bo_reference_info_arg arg;
1788+ struct drm_bo_handle_arg *req = &arg.d.req;
1789+ struct drm_bo_info_rep *rep = &arg.d.rep;
1790 int ret = 0;
1791
1792 memset(&arg, 0, sizeof(arg));
1793 req->handle = buf->handle;
1794- req->op = drm_bo_info;
1795
1796- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1797-
1798+ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
1799 if (ret)
1800- return ret;
1801- if (!arg.handled)
1802- return -EFAULT;
1803- if (rep->ret)
1804- return rep->ret;
1805+ return -errno;
1806+
1807 drmBOCopyReply(rep, buf);
1808 return 0;
1809 }
1810
1811 int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
1812 {
1813- drm_bo_arg_t arg;
1814- drm_bo_arg_request_t *req = &arg.d.req;
1815- drm_bo_arg_reply_t *rep = &arg.d.rep;
1816+ struct drm_bo_map_wait_idle_arg arg;
1817+ struct drm_bo_info_req *req = &arg.d.req;
1818+ struct drm_bo_info_rep *rep = &arg.d.rep;
1819 int ret = 0;
1820
1821 if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
1822 (buf->replyFlags & DRM_BO_REP_BUSY)) {
1823 memset(&arg, 0, sizeof(arg));
1824 req->handle = buf->handle;
1825- req->op = drm_bo_wait_idle;
1826 req->hint = hint;
1827
1828- do {
1829- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, &arg);
1830- } while (ret && errno == EAGAIN);
1831-
1832+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
1833 if (ret)
1834 return ret;
1835- if (!arg.handled)
1836- return -EFAULT;
1837- if (rep->ret)
1838- return rep->ret;
1839+
1840 drmBOCopyReply(rep, buf);
1841 }
1842 return 0;
1843@@ -2961,7 +2806,8 @@
1844 !(buf->replyFlags & DRM_BO_REP_BUSY)) {
1845 *busy = 0;
1846 return 0;
1847- } else {
1848+ }
1849+ else {
1850 int ret = drmBOInfo(fd, buf);
1851 if (ret)
1852 return ret;
1853@@ -2970,257 +2816,95 @@
1854 }
1855 }
1856
1857-
1858-int drmAddValidateItem(drmBOList *list, drmBO *buf, unsigned flags,
1859- unsigned mask,
1860- int *newItem)
1861-{
1862- drmBONode *node, *cur;
1863- drmMMListHead *l;
1864-
1865- *newItem = 0;
1866- cur = NULL;
1867-
1868- for (l = list->list.next; l != &list->list; l = l->next) {
1869- node = DRMLISTENTRY(drmBONode, l, head);
1870- if (node->buf == buf) {
1871- cur = node;
1872- break;
1873- }
1874- }
1875- if (!cur) {
1876- cur = drmAddListItem(list, buf, flags, mask);
1877- if (!cur) {
1878- drmMsg("Out of memory creating validate list node.\n");
1879- return -ENOMEM;
1880- }
1881- *newItem = 1;
1882- cur->arg0 = flags;
1883- cur->arg1 = mask;
1884- } else {
1885- unsigned memMask = (cur->arg1 | mask) & DRM_BO_MASK_MEM;
1886- unsigned memFlags = cur->arg0 & flags & memMask;
1887-
1888- if (!memFlags) {
1889- drmMsg("Incompatible memory location requests "
1890- "on validate list.\n");
1891- drmMsg("Previous flag: 0x%08lx, mask: 0x%08lx\n",
1892- cur->arg0, cur->arg1);
1893- drmMsg("Current flag: 0x%08lx, mask: 0x%08lx\n",
1894- flags, mask);
1895- return -EINVAL;
1896- }
1897- if (mask & cur->arg1 & ~DRM_BO_MASK_MEM & (cur->arg0 ^ flags)) {
1898- drmMsg("Incompatible buffer flag requests "
1899- "on validate list.\n");
1900- drmMsg("Previous flag: 0x%08lx, mask: 0x%08lx\n",
1901- cur->arg0, cur->arg1);
1902- drmMsg("Current flag: 0x%08lx, mask: 0x%08lx\n",
1903- flags, mask);
1904- return -EINVAL;
1905- }
1906- cur->arg1 |= mask;
1907- cur->arg0 = memFlags | ((cur->arg0 | flags) &
1908- cur->arg1 & ~DRM_BO_MASK_MEM);
1909- }
1910- return 0;
1911-}
1912-
1913-
1914-int drmBOValidateList(int fd, drmBOList *list)
1915-{
1916-
1917- drmBONode *node;
1918- drmMMListHead *l;
1919- drm_bo_arg_t *arg, *first;
1920- drm_bo_arg_request_t *req;
1921- drm_bo_arg_reply_t *rep;
1922- drm_u64_t *prevNext = NULL;
1923- drmBO *buf;
1924- int ret;
1925-
1926- first = NULL;
1927-
1928- for (l = list->list.next; l != &list->list; l = l->next) {
1929- node = DRMLISTENTRY(drmBONode, l, head);
1930-
1931- arg = &node->bo_arg;
1932- req = &arg->d.req;
1933-
1934- if (!first)
1935- first = arg;
1936-
1937- if (prevNext)
1938- *prevNext = (unsigned long) arg;
1939-
1940- memset(arg, 0, sizeof(*arg));
1941- prevNext = &arg->next;
1942- req->handle = node->buf->handle;
1943- req->op = drm_bo_validate;
1944- req->mask = node->arg0;
1945- req->hint = 0;
1946- req->arg_handle = node->arg1;
1947- }
1948-
1949- if (!first)
1950- return 0;
1951-
1952- do{
1953- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, first);
1954- } while (ret && errno == EAGAIN);
1955-
1956-
1957- if (ret)
1958- return -errno;
1959-
1960- for (l = list->list.next; l != &list->list; l = l->next) {
1961- node = DRMLISTENTRY(drmBONode, l, head);
1962- arg = &node->bo_arg;
1963- rep = &arg->d.rep;
1964-
1965- if (!arg->handled) {
1966- drmMsg("Unhandled request\n");
1967- return -EFAULT;
1968- }
1969- if (rep->ret)
1970- return rep->ret;
1971-
1972- buf = node->buf;
1973- drmBOCopyReply(rep, buf);
1974- }
1975-
1976- return 0;
1977-}
1978-
1979-
1980-int drmBOFenceList(int fd, drmBOList *list, unsigned fenceHandle)
1981-{
1982-
1983- drmBONode *node;
1984- drmMMListHead *l;
1985- drm_bo_arg_t *arg, *first;
1986- drm_bo_arg_request_t *req;
1987- drm_bo_arg_reply_t *rep;
1988- drm_u64_t *prevNext = NULL;
1989- drmBO *buf;
1990- unsigned fence_flags;
1991- int ret;
1992-
1993- first = NULL;
1994-
1995- for (l = list->list.next; l != &list->list; l = l->next) {
1996- node = DRMLISTENTRY(drmBONode, l, head);
1997-
1998- arg = &node->bo_arg;
1999- req = &arg->d.req;
2000-
2001- if (!first)
2002- first = arg;
2003-
2004- if (prevNext)
2005- *prevNext = (unsigned long) arg;
2006-
2007- memset(arg, 0, sizeof(*arg));
2008- prevNext = &arg->next;
2009- req->handle = node->buf->handle;
2010- req->op = drm_bo_fence;
2011- req->mask = node->arg0;
2012- req->arg_handle = fenceHandle;
2013- }
2014-
2015- if (!first)
2016- return 0;
2017-
2018- ret = ioctl(fd, DRM_IOCTL_BUFOBJ, first);
2019-
2020- if (ret)
2021- return -errno;
2022-
2023- for (l = list->list.next; l != &list->list; l = l->next) {
2024- node = DRMLISTENTRY(drmBONode, l, head);
2025-
2026- arg = &node->bo_arg;
2027- rep = &arg->d.rep;
2028-
2029- if (!arg->handled)
2030- return -EFAULT;
2031- if (rep->ret)
2032- return rep->ret;
2033- drmBOCopyReply(rep, node->buf);
2034- }
2035-
2036- return 0;
2037-}
2038-
2039 int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
2040 unsigned memType)
2041 {
2042- drm_mm_init_arg_t arg;
2043-
2044+ struct drm_mm_init_arg arg;
2045+
2046 memset(&arg, 0, sizeof(arg));
2047- arg.req.op = mm_init;
2048- arg.req.p_offset = pOffset;
2049- arg.req.p_size = pSize;
2050- arg.req.mem_type = memType;
2051+
2052+ arg.magic = DRM_BO_INIT_MAGIC;
2053+ arg.major = DRM_BO_INIT_MAJOR;
2054+ arg.minor = DRM_BO_INIT_MINOR;
2055+ arg.p_offset = pOffset;
2056+ arg.p_size = pSize;
2057+ arg.mem_type = memType;
2058
2059 if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
2060 return -errno;
2061-
2062 return 0;
2063 }
2064
2065 int drmMMTakedown(int fd, unsigned memType)
2066 {
2067- drm_mm_init_arg_t arg;
2068-
2069+ struct drm_mm_type_arg arg;
2070
2071 memset(&arg, 0, sizeof(arg));
2072- arg.req.op = mm_takedown;
2073- arg.req.mem_type = memType;
2074+ arg.mem_type = memType;
2075
2076- if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
2077+ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
2078 return -errno;
2079-
2080 return 0;
2081 }
2082
2083-int drmMMLock(int fd, unsigned memType)
2084+/*
2085+ * If this function returns an error, and lockBM was set to 1,
2086+ * the buffer manager is NOT locked.
2087+ */
2088+
2089+int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
2090 {
2091- drm_mm_init_arg_t arg;
2092- int ret;
2093+ struct drm_mm_type_arg arg;
2094
2095 memset(&arg, 0, sizeof(arg));
2096- arg.req.op = mm_lock;
2097- arg.req.mem_type = memType;
2098+ arg.mem_type = memType;
2099+ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
2100+ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
2101
2102- do{
2103- ret = ioctl(fd, DRM_IOCTL_MM_INIT, &arg);
2104- } while (ret && errno == EAGAIN);
2105+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
2106+}
2107+
2108+int drmMMUnlock(int fd, unsigned memType, int unlockBM)
2109+{
2110+ struct drm_mm_type_arg arg;
2111+
2112+ memset(&arg, 0, sizeof(arg));
2113
2114- return ret;
2115+ arg.mem_type = memType;
2116+ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
2117+
2118+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
2119 }
2120
2121-int drmMMUnlock(int fd, unsigned memType)
2122+int drmBOVersion(int fd, unsigned int *major,
2123+ unsigned int *minor,
2124+ unsigned int *patchlevel)
2125 {
2126- drm_mm_init_arg_t arg;
2127+ struct drm_bo_version_arg arg;
2128 int ret;
2129
2130 memset(&arg, 0, sizeof(arg));
2131- arg.req.op = mm_unlock;
2132- arg.req.mem_type = memType;
2133+ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
2134+ if (ret)
2135+ return -errno;
2136
2137- do{
2138- ret = ioctl(fd, DRM_IOCTL_MM_INIT, &arg);
2139- } while (ret && errno == EAGAIN);
2140-
2141- return ret;
2142+ if (major)
2143+ *major = arg.major;
2144+ if (minor)
2145+ *minor = arg.minor;
2146+ if (patchlevel)
2147+ *patchlevel = arg.patchlevel;
2148+
2149+ return 0;
2150 }
2151
2152+
2153+
2154 #define DRM_MAX_FDS 16
2155 static struct {
2156- char *BusID;
2157- int fd;
2158- int refcount;
2159+ char *BusID;
2160+ int fd;
2161+ int refcount;
2162 } connection[DRM_MAX_FDS];
2163
2164 static int nr_fds = 0;
2165@@ -3229,50 +2913,50 @@
2166 const char *BusID,
2167 int *newlyopened)
2168 {
2169- int i;
2170- int fd;
2171+ int i;
2172+ int fd;
2173
2174- for (i = 0; i < nr_fds; i++)
2175- if (strcmp(BusID, connection[i].BusID) == 0) {
2176- connection[i].refcount++;
2177- *newlyopened = 0;
2178- return connection[i].fd;
2179- }
2180-
2181- fd = drmOpen(unused, BusID);
2182- if (fd <= 0 || nr_fds == DRM_MAX_FDS)
2183- return fd;
2184+ for (i = 0; i < nr_fds; i++)
2185+ if (strcmp(BusID, connection[i].BusID) == 0) {
2186+ connection[i].refcount++;
2187+ *newlyopened = 0;
2188+ return connection[i].fd;
2189+ }
2190+
2191+ fd = drmOpen(unused, BusID);
2192+ if (fd <= 0 || nr_fds == DRM_MAX_FDS)
2193+ return fd;
2194
2195- connection[nr_fds].BusID = strdup(BusID);
2196- connection[nr_fds].fd = fd;
2197- connection[nr_fds].refcount = 1;
2198- *newlyopened = 1;
2199-
2200- if (0)
2201- fprintf(stderr, "saved connection %d for %s %d\n",
2202- nr_fds, connection[nr_fds].BusID,
2203- strcmp(BusID, connection[nr_fds].BusID));
2204+ connection[nr_fds].BusID = strdup(BusID);
2205+ connection[nr_fds].fd = fd;
2206+ connection[nr_fds].refcount = 1;
2207+ *newlyopened = 1;
2208+
2209+ if (0)
2210+ fprintf(stderr, "saved connection %d for %s %d\n",
2211+ nr_fds, connection[nr_fds].BusID,
2212+ strcmp(BusID, connection[nr_fds].BusID));
2213
2214- nr_fds++;
2215+ nr_fds++;
2216
2217- return fd;
2218+ return fd;
2219 }
2220
2221 void drmCloseOnce(int fd)
2222 {
2223- int i;
2224+ int i;
2225
2226- for (i = 0; i < nr_fds; i++) {
2227- if (fd == connection[i].fd) {
2228- if (--connection[i].refcount == 0) {
2229- drmClose(connection[i].fd);
2230- free(connection[i].BusID);
2231+ for (i = 0; i < nr_fds; i++) {
2232+ if (fd == connection[i].fd) {
2233+ if (--connection[i].refcount == 0) {
2234+ drmClose(connection[i].fd);
2235+ free(connection[i].BusID);
2236
2237- if (i < --nr_fds)
2238- connection[i] = connection[nr_fds];
2239+ if (i < --nr_fds)
2240+ connection[i] = connection[nr_fds];
2241
2242- return;
2243- }
2244- }
2245- }
2246+ return;
2247+ }
2248+ }
2249+ }
2250 }
2251Index: git/libdrm/xf86drm.h
2252===================================================================
2253--- git.orig/libdrm/xf86drm.h 2008-12-12 17:20:14.000000000 +0000
2254+++ git/libdrm/xf86drm.h 2008-12-12 17:35:22.000000000 +0000
2255@@ -31,13 +31,12 @@
2256 *
2257 */
2258
2259-/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drm.h,v 1.26 2003/08/16 19:26:37 dawes Exp $ */
2260-
2261 #ifndef _XF86DRM_H_
2262 #define _XF86DRM_H_
2263
2264 #include <stdarg.h>
2265 #include <sys/types.h>
2266+#include <stdint.h>
2267 #include <drm.h>
2268
2269 /* Defaults, if nothing set in xf86config */
2270@@ -270,6 +269,7 @@
2271 typedef enum {
2272 DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
2273 DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
2274+ DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
2275 DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
2276 DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
2277 DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */
2278Index: git/libdrm/xf86drmHash.c
2279===================================================================
2280--- git.orig/libdrm/xf86drmHash.c 2008-12-12 17:20:14.000000000 +0000
2281+++ git/libdrm/xf86drmHash.c 2008-12-12 17:35:22.000000000 +0000
2282@@ -25,8 +25,6 @@
2283 *
2284 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
2285 *
2286- * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drmHash.c,v 1.4 2001/03/21 18:08:54 dawes Exp $
2287- *
2288 * DESCRIPTION
2289 *
2290 * This file contains a straightforward implementation of a fixed-sized
2291@@ -70,25 +68,13 @@
2292 *
2293 */
2294
2295-#ifdef HAVE_XORG_CONFIG_H
2296-#include <xorg-config.h>
2297-#endif
2298+#include <stdio.h>
2299+#include <stdlib.h>
2300
2301 #define HASH_MAIN 0
2302
2303-#if HASH_MAIN
2304-# include <stdio.h>
2305-# include <stdlib.h>
2306-#else
2307-# include "drm.h"
2308+#if !HASH_MAIN
2309 # include "xf86drm.h"
2310-# ifdef XFree86LOADER
2311-# include "xf86.h"
2312-# include "xf86_ansic.h"
2313-# else
2314-# include <stdio.h>
2315-# include <stdlib.h>
2316-# endif
2317 #endif
2318
2319 #define HASH_MAGIC 0xdeadbeef
2320Index: git/libdrm/xf86drmMode.c
2321===================================================================
2322--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2323+++ git/libdrm/xf86drmMode.c 2008-12-12 17:35:22.000000000 +0000
2324@@ -0,0 +1,465 @@
2325+/*
2326+ * \file xf86drmMode.c
2327+ * Header for DRM modesetting interface.
2328+ *
2329+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
2330+ *
2331+ * \par Acknowledgements:
2332+ * Feb 2007, Dave Airlie <airlied@linux.ie>
2333+ */
2334+
2335+/*
2336+ * Copyright (c) <year> <copyright holders>
2337+ *
2338+ * Permission is hereby granted, free of charge, to any person obtaining a
2339+ * copy of this software and associated documentation files (the "Software"),
2340+ * to deal in the Software without restriction, including without limitation
2341+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
2342+ * and/or sell copies of the Software, and to permit persons to whom the
2343+ * Software is furnished to do so, subject to the following conditions:
2344+ *
2345+ * The above copyright notice and this permission notice shall be included in
2346+ * all copies or substantial portions of the Software.
2347+ *
2348+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2349+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2350+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
2351+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2352+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2353+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2354+ * IN THE SOFTWARE.
2355+ *
2356+ */
2357+
2358+/*
2359+ * TODO the types we are after are defined in diffrent headers on diffrent
2360+ * platforms find which headers to include to get uint32_t
2361+ */
2362+#include <stdint.h>
2363+
2364+#include "xf86drmMode.h"
2365+#include "xf86drm.h"
2366+#include <drm.h>
2367+#include <string.h>
2368+
2369+/*
2370+ * Util functions
2371+ */
2372+
2373+void* drmAllocCpy(void *array, int count, int entry_size)
2374+{
2375+ char *r;
2376+ int i;
2377+
2378+ if (!count || !array || !entry_size)
2379+ return 0;
2380+
2381+ if (!(r = drmMalloc(count*entry_size)))
2382+ return 0;
2383+
2384+ for (i = 0; i < count; i++)
2385+ memcpy(r+(entry_size*i), array+(entry_size*i), entry_size);
2386+
2387+ return r;
2388+}
2389+
2390+/**
2391+ * Generate crtc and output ids.
2392+ *
2393+ * Will generate ids starting from 1 up to count if count is greater then 0.
2394+ */
2395+static uint32_t* drmAllocGenerate(int count)
2396+{
2397+ uint32_t *r;
2398+ int i;
2399+
2400+ if(0 <= count)
2401+ return 0;
2402+
2403+ if (!(r = drmMalloc(count*sizeof(*r))))
2404+ return 0;
2405+
2406+ for (i = 0; i < count; r[i] = ++i);
2407+
2408+ return 0;
2409+}
2410+
2411+/*
2412+ * A couple of free functions.
2413+ */
2414+
2415+void drmModeFreeModeInfo(struct drm_mode_modeinfo *ptr)
2416+{
2417+ if (!ptr)
2418+ return;
2419+
2420+ drmFree(ptr);
2421+}
2422+
2423+void drmModeFreeResources(drmModeResPtr ptr)
2424+{
2425+ if (!ptr)
2426+ return;
2427+
2428+ drmFree(ptr->modes);
2429+ drmFree(ptr);
2430+
2431+}
2432+
2433+void drmModeFreeFB(drmModeFBPtr ptr)
2434+{
2435+ if (!ptr)
2436+ return;
2437+
2438+ /* we might add more frees later. */
2439+ drmFree(ptr);
2440+}
2441+
2442+void drmModeFreeCrtc(drmModeCrtcPtr ptr)
2443+{
2444+ if (!ptr)
2445+ return;
2446+
2447+ drmFree(ptr);
2448+
2449+}
2450+
2451+void drmModeFreeOutput(drmModeOutputPtr ptr)
2452+{
2453+ if (!ptr)
2454+ return;
2455+
2456+ drmFree(ptr->modes);
2457+ drmFree(ptr);
2458+
2459+}
2460+
2461+/*
2462+ * ModeSetting functions.
2463+ */
2464+
2465+drmModeResPtr drmModeGetResources(int fd)
2466+{
2467+ struct drm_mode_card_res res;
2468+ int i;
2469+ drmModeResPtr r = 0;
2470+
2471+ memset(&res, 0, sizeof(struct drm_mode_card_res));
2472+
2473+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res))
2474+ return 0;
2475+
2476+ if (res.count_fbs)
2477+ res.fb_id = drmMalloc(res.count_fbs*sizeof(uint32_t));
2478+ if (res.count_crtcs)
2479+ res.crtc_id = drmMalloc(res.count_crtcs*sizeof(uint32_t));
2480+ if (res.count_outputs)
2481+ res.output_id = drmMalloc(res.count_outputs*sizeof(uint32_t));
2482+ if (res.count_modes)
2483+ res.modes = drmMalloc(res.count_modes*sizeof(*res.modes));
2484+
2485+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) {
2486+ r = NULL;
2487+ goto err_allocs;
2488+ }
2489+
2490+ /*
2491+ * return
2492+ */
2493+
2494+
2495+ if (!(r = drmMalloc(sizeof(*r))))
2496+ return 0;
2497+
2498+ r->count_fbs = res.count_fbs;
2499+ r->count_crtcs = res.count_crtcs;
2500+ r->count_outputs = res.count_outputs;
2501+ r->count_modes = res.count_modes;
2502+ /* TODO we realy should test if these allocs fails. */
2503+ r->fbs = drmAllocCpy(res.fb_id, res.count_fbs, sizeof(uint32_t));
2504+ r->crtcs = drmAllocCpy(res.crtc_id, res.count_crtcs, sizeof(uint32_t));
2505+ r->outputs = drmAllocCpy(res.output_id, res.count_outputs, sizeof(uint32_t));
2506+ r->modes = drmAllocCpy(res.modes, res.count_modes, sizeof(struct drm_mode_modeinfo));
2507+
2508+err_allocs:
2509+ drmFree(res.fb_id);
2510+ drmFree(res.crtc_id);
2511+ drmFree(res.output_id);
2512+ drmFree(res.modes);
2513+
2514+ return r;
2515+}
2516+
2517+int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
2518+ uint8_t bpp, uint32_t pitch, drmBO *bo, uint32_t *buf_id)
2519+{
2520+ struct drm_mode_fb_cmd f;
2521+ int ret;
2522+
2523+ f.width = width;
2524+ f.height = height;
2525+ f.pitch = pitch;
2526+ f.bpp = bpp;
2527+ f.depth = depth;
2528+ f.handle = bo->handle;
2529+
2530+ if (ret = ioctl(fd, DRM_IOCTL_MODE_ADDFB, &f))
2531+ return ret;
2532+
2533+ *buf_id = f.buffer_id;
2534+ return 0;
2535+}
2536+
2537+int drmModeRmFB(int fd, uint32_t bufferId)
2538+{
2539+ return ioctl(fd, DRM_IOCTL_MODE_RMFB, &bufferId);
2540+}
2541+
2542+drmModeFBPtr drmModeGetFB(int fd, uint32_t buf)
2543+{
2544+ struct drm_mode_fb_cmd info;
2545+ drmModeFBPtr r;
2546+
2547+ info.buffer_id = buf;
2548+
2549+ if (ioctl(fd, DRM_IOCTL_MODE_GETFB, &info))
2550+ return NULL;
2551+
2552+ if (!(r = drmMalloc(sizeof(*r))))
2553+ return NULL;
2554+
2555+ r->buffer_id = info.buffer_id;
2556+ r->width = info.width;
2557+ r->height = info.height;
2558+ r->pitch = info.pitch;
2559+ r->bpp = info.bpp;
2560+ r->handle = info.handle;
2561+ r->depth = info.depth;
2562+
2563+ return r;
2564+}
2565+
2566+
2567+/*
2568+ * Crtc functions
2569+ */
2570+
2571+drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
2572+{
2573+ struct drm_mode_crtc crtc;
2574+ drmModeCrtcPtr r;
2575+ int i = 0;
2576+
2577+ crtc.count_outputs = 0;
2578+ crtc.outputs = 0;
2579+ crtc.count_possibles = 0;
2580+ crtc.possibles = 0;
2581+ crtc.crtc_id = crtcId;
2582+
2583+ if (ioctl(fd, DRM_IOCTL_MODE_GETCRTC, &crtc))
2584+ return 0;
2585+
2586+ /*
2587+ * return
2588+ */
2589+
2590+ if (!(r = drmMalloc(sizeof(*r))))
2591+ return 0;
2592+
2593+ r->crtc_id = crtc.crtc_id;
2594+ r->x = crtc.x;
2595+ r->y = crtc.y;
2596+ r->mode = crtc.mode;
2597+ r->buffer_id = crtc.fb_id;
2598+ r->gamma_size = crtc.gamma_size;
2599+ r->count_outputs = crtc.count_outputs;
2600+ r->count_possibles = crtc.count_possibles;
2601+ /* TODO we realy should test if these alloc & cpy fails. */
2602+ r->outputs = crtc.outputs;
2603+ r->possibles = crtc.possibles;
2604+
2605+ return r;
2606+
2607+err_allocs:
2608+
2609+ return 0;
2610+}
2611+
2612+
2613+int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
2614+ uint32_t x, uint32_t y, uint32_t modeId,
2615+ uint32_t *outputs, int count)
2616+{
2617+ struct drm_mode_crtc crtc;
2618+
2619+ crtc.count_outputs = 0;
2620+ crtc.outputs = 0;
2621+ crtc.count_possibles = 0;
2622+ crtc.possibles = 0;
2623+
2624+ crtc.x = x;
2625+ crtc.y = y;
2626+ crtc.crtc_id = crtcId;
2627+ crtc.fb_id = bufferId;
2628+ crtc.set_outputs = outputs;
2629+ crtc.count_outputs = count;
2630+ crtc.mode = modeId;
2631+
2632+ return ioctl(fd, DRM_IOCTL_MODE_SETCRTC, &crtc);
2633+}
2634+
2635+
2636+/*
2637+ * Output manipulation
2638+ */
2639+
2640+drmModeOutputPtr drmModeGetOutput(int fd, uint32_t output_id)
2641+{
2642+ struct drm_mode_get_output out;
2643+ drmModeOutputPtr r = NULL;
2644+
2645+ out.output = output_id;
2646+ out.count_crtcs = 0;
2647+ out.crtcs = 0;
2648+ out.count_clones = 0;
2649+ out.clones = 0;
2650+ out.count_modes = 0;
2651+ out.modes = 0;
2652+ out.count_props = 0;
2653+ out.props = NULL;
2654+ out.prop_values = NULL;
2655+
2656+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
2657+ return 0;
2658+
2659+ if (out.count_props) {
2660+ out.props = drmMalloc(out.count_props*sizeof(uint32_t));
2661+ out.prop_values = drmMalloc(out.count_props*sizeof(uint32_t));
2662+ }
2663+
2664+ if (out.count_modes)
2665+ out.modes = drmMalloc(out.count_modes*sizeof(uint32_t));
2666+
2667+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
2668+ goto err_allocs;
2669+
2670+ if(!(r = drmMalloc(sizeof(*r)))) {
2671+ goto err_allocs;
2672+ }
2673+
2674+ r->output_id = out.output;
2675+ r->crtc = out.crtc;
2676+ r->connection = out.connection;
2677+ r->mmWidth = out.mm_width;
2678+ r->mmHeight = out.mm_height;
2679+ r->subpixel = out.subpixel;
2680+ r->count_crtcs = out.count_crtcs;
2681+ r->count_clones = out.count_clones;
2682+ r->count_modes = out.count_modes;
2683+ /* TODO we should test if these alloc & cpy fails. */
2684+ r->crtcs = out.crtcs;
2685+ r->clones = out.clones;
2686+ r->count_props = out.count_props;
2687+ r->props = drmAllocCpy(out.props, out.count_props, sizeof(uint32_t));
2688+ r->prop_values = drmAllocCpy(out.prop_values, out.count_props, sizeof(uint32_t));
2689+ r->modes = drmAllocCpy(out.modes, out.count_modes, sizeof(uint32_t));
2690+ strncpy(r->name, out.name, DRM_OUTPUT_NAME_LEN);
2691+ r->name[DRM_OUTPUT_NAME_LEN-1] = 0;
2692+
2693+err_allocs:
2694+ drmFree(out.prop_values);
2695+ drmFree(out.props);
2696+ drmFree(out.modes);
2697+
2698+ return r;
2699+}
2700+
2701+uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *mode_info)
2702+{
2703+ if (ioctl(fd, DRM_IOCTL_MODE_ADDMODE, mode_info))
2704+ return 0;
2705+
2706+ return mode_info->id;
2707+}
2708+
2709+int drmModeRmMode(int fd, uint32_t mode_id)
2710+{
2711+ return ioctl(fd, DRM_IOCTL_MODE_RMMODE, &mode_id);
2712+}
2713+
2714+int drmModeAttachMode(int fd, uint32_t output_id, uint32_t mode_id)
2715+{
2716+
2717+ struct drm_mode_mode_cmd res;
2718+
2719+ res.output_id = output_id;
2720+ res.mode_id = mode_id;
2721+
2722+ return ioctl(fd, DRM_IOCTL_MODE_ATTACHMODE, &res);
2723+}
2724+
2725+int drmModeDetachMode(int fd, uint32_t output_id, uint32_t mode_id)
2726+{
2727+ struct drm_mode_mode_cmd res;
2728+
2729+ res.output_id = output_id;
2730+ res.mode_id = mode_id;
2731+
2732+ return ioctl(fd, DRM_IOCTL_MODE_DETACHMODE, &res);
2733+}
2734+
2735+
2736+drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id)
2737+{
2738+ struct drm_mode_get_property prop;
2739+ drmModePropertyPtr r;
2740+
2741+ prop.prop_id = property_id;
2742+ prop.count_enums = 0;
2743+ prop.count_values = 0;
2744+ prop.flags = 0;
2745+ prop.enums = NULL;
2746+ prop.values = NULL;
2747+
2748+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop))
2749+ return 0;
2750+
2751+ if (prop.count_values)
2752+ prop.values = drmMalloc(prop.count_values * sizeof(uint32_t));
2753+
2754+ if (prop.count_enums)
2755+ prop.enums = drmMalloc(prop.count_enums * sizeof(struct drm_mode_property_enum));
2756+
2757+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop)) {
2758+ r = NULL;
2759+ goto err_allocs;
2760+ }
2761+
2762+ if (!(r = drmMalloc(sizeof(*r))))
2763+ return NULL;
2764+
2765+ r->prop_id = prop.prop_id;
2766+ r->count_values = prop.count_values;
2767+ r->count_enums = prop.count_enums;
2768+
2769+ r->values = drmAllocCpy(prop.values, prop.count_values, sizeof(uint32_t));
2770+ r->enums = drmAllocCpy(prop.enums, prop.count_enums, sizeof(struct drm_mode_property_enum));
2771+ strncpy(r->name, prop.name, DRM_PROP_NAME_LEN);
2772+ r->name[DRM_PROP_NAME_LEN-1] = 0;
2773+
2774+err_allocs:
2775+ drmFree(prop.values);
2776+ drmFree(prop.enums);
2777+
2778+ return r;
2779+}
2780+
2781+void drmModeFreeProperty(drmModePropertyPtr ptr)
2782+{
2783+ if (!ptr)
2784+ return;
2785+
2786+ drmFree(ptr->values);
2787+ drmFree(ptr->enums);
2788+ drmFree(ptr);
2789+}
2790Index: git/libdrm/xf86drmMode.h
2791===================================================================
2792--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2793+++ git/libdrm/xf86drmMode.h 2008-12-12 17:35:22.000000000 +0000
2794@@ -0,0 +1,226 @@
2795+/*
2796+ * \file xf86drmMode.h
2797+ * Header for DRM modesetting interface.
2798+ *
2799+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
2800+ *
2801+ * \par Acknowledgements:
2802+ * Feb 2007, Dave Airlie <airlied@linux.ie>
2803+ */
2804+
2805+/*
2806+ * Copyright (c) <year> <copyright holders>
2807+ *
2808+ * Permission is hereby granted, free of charge, to any person obtaining a
2809+ * copy of this software and associated documentation files (the "Software"),
2810+ * to deal in the Software without restriction, including without limitation
2811+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
2812+ * and/or sell copies of the Software, and to permit persons to whom the
2813+ * Software is furnished to do so, subject to the following conditions:
2814+ *
2815+ * The above copyright notice and this permission notice shall be included in
2816+ * all copies or substantial portions of the Software.
2817+ *
2818+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2819+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2820+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
2821+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2822+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2823+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2824+ * IN THE SOFTWARE.
2825+ *
2826+ */
2827+
2828+#include <drm.h>
2829+#include "xf86mm.h"
2830+
2831+/*
2832+ * This is the interface for modesetting for drm.
2833+ *
2834+ * In order to use this interface you must include either <stdint.h> or another
2835+ * header defining uint32_t, int32_t and uint16_t.
2836+ *
2837+ * It aims to provide a randr1.2 compatible interface for modesettings in the
2838+ * kernel, the interface is also ment to be used by libraries like EGL.
2839+ *
2840+ * More information can be found in randrproto.txt which can be found here:
2841+ * http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git
2842+ *
2843+ * There are some major diffrences to be noted. Unlike the randr1.2 proto you
2844+ * need to create the memory object of the framebuffer yourself with the ttm
2845+ * buffer object interface. This object needs to be pinned.
2846+ */
2847+
2848+
2849+typedef struct _drmModeRes {
2850+
2851+ int count_fbs;
2852+ uint32_t *fbs;
2853+
2854+ int count_crtcs;
2855+ uint32_t *crtcs;
2856+
2857+ int count_outputs;
2858+ uint32_t *outputs;
2859+
2860+ int count_modes;
2861+ struct drm_mode_modeinfo *modes;
2862+
2863+} drmModeRes, *drmModeResPtr;
2864+
2865+typedef struct drm_mode_fb_cmd drmModeFB, *drmModeFBPtr;
2866+
2867+typedef struct _drmModeProperty {
2868+ unsigned int prop_id;
2869+ unsigned int flags;
2870+ unsigned char name[DRM_PROP_NAME_LEN];
2871+ int count_values;
2872+ uint32_t *values;
2873+ int count_enums;
2874+ struct drm_mode_property_enum *enums;
2875+
2876+} drmModePropertyRes, *drmModePropertyPtr;
2877+
2878+typedef struct _drmModeCrtc {
2879+ unsigned int crtc_id;
2880+ unsigned int buffer_id; /**< FB id to connect to 0 = disconnect*/
2881+
2882+ uint32_t x, y; /**< Position on the frameuffer */
2883+ uint32_t width, height;
2884+ uint32_t mode; /**< Current mode used */
2885+
2886+ int count_outputs;
2887+ uint32_t outputs; /**< Outputs that are connected */
2888+
2889+ int count_possibles;
2890+ uint32_t possibles; /**< Outputs that can be connected */
2891+
2892+ int gamma_size; /**< Number of gamma stops */
2893+
2894+} drmModeCrtc, *drmModeCrtcPtr;
2895+
2896+typedef enum {
2897+ DRM_MODE_CONNECTED = 1,
2898+ DRM_MODE_DISCONNECTED = 2,
2899+ DRM_MODE_UNKNOWNCONNECTION = 3
2900+} drmModeConnection;
2901+
2902+typedef enum {
2903+ DRM_MODE_SUBPIXEL_UNKNOWN = 1,
2904+ DRM_MODE_SUBPIXEL_HORIZONTAL_RGB = 2,
2905+ DRM_MODE_SUBPIXEL_HORIZONTAL_BGR = 3,
2906+ DRM_MODE_SUBPIXEL_VERTICAL_RGB = 4,
2907+ DRM_MODE_SUBPIXEL_VERTICAL_BGR = 5,
2908+ DRM_MODE_SUBPIXEL_NONE = 6
2909+} drmModeSubPixel;
2910+
2911+typedef struct _drmModeOutput {
2912+ unsigned int output_id;
2913+
2914+ unsigned int crtc; /**< Crtc currently connected to */
2915+ unsigned char name[DRM_OUTPUT_NAME_LEN];
2916+ drmModeConnection connection;
2917+ uint32_t mmWidth, mmHeight; /**< HxW in millimeters */
2918+ drmModeSubPixel subpixel;
2919+
2920+ int count_crtcs;
2921+ uint32_t crtcs; /**< Possible crtc to connect to */
2922+
2923+ int count_clones;
2924+ uint32_t clones; /**< Mask of clones */
2925+
2926+ int count_modes;
2927+ uint32_t *modes; /**< List of modes ids */
2928+
2929+ int count_props;
2930+ uint32_t *props; /**< List of property ids */
2931+ uint32_t *prop_values; /**< List of property values */
2932+
2933+} drmModeOutput, *drmModeOutputPtr;
2934+
2935+
2936+
2937+extern void drmModeFreeModeInfo( struct drm_mode_modeinfo *ptr );
2938+extern void drmModeFreeResources( drmModeResPtr ptr );
2939+extern void drmModeFreeFB( drmModeFBPtr ptr );
2940+extern void drmModeFreeCrtc( drmModeCrtcPtr ptr );
2941+extern void drmModeFreeOutput( drmModeOutputPtr ptr );
2942+
2943+/**
2944+ * Retrives all of the resources associated with a card.
2945+ */
2946+extern drmModeResPtr drmModeGetResources(int fd);
2947+
2948+
2949+/*
2950+ * FrameBuffer manipulation.
2951+ */
2952+
2953+/**
2954+ * Retrive information about framebuffer bufferId
2955+ */
2956+extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId);
2957+
2958+/**
2959+ * Creates a new framebuffer with an buffer object as its scanout buffer.
2960+ */
2961+extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
2962+ uint8_t bpp, uint32_t pitch, drmBO *bo,
2963+ uint32_t *buf_id);
2964+/**
2965+ * Destroies the given framebuffer.
2966+ */
2967+extern int drmModeRmFB(int fd, uint32_t bufferId);
2968+
2969+
2970+/*
2971+ * Crtc functions
2972+ */
2973+
2974+/**
2975+ * Retrive information about the ctrt crtcId
2976+ */
2977+extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId);
2978+
2979+/**
2980+ * Set the mode on a crtc crtcId with the given mode modeId.
2981+ */
2982+extern int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
2983+ uint32_t x, uint32_t y, uint32_t modeId,
2984+ uint32_t *outputs, int count);
2985+
2986+
2987+/*
2988+ * Output manipulation
2989+ */
2990+
2991+/**
2992+ * Retrive information about the output outputId.
2993+ */
2994+extern drmModeOutputPtr drmModeGetOutput(int fd,
2995+ uint32_t outputId);
2996+
2997+/**
2998+ * Adds a new mode from the given mode info.
2999+ * Name must be unique.
3000+ */
3001+extern uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *modeInfo);
3002+
3003+/**
3004+ * Removes a mode created with AddMode, must be unused.
3005+ */
3006+extern int drmModeRmMode(int fd, uint32_t modeId);
3007+
3008+/**
3009+ * Attaches the given mode to an output.
3010+ */
3011+extern int drmModeAttachMode(int fd, uint32_t outputId, uint32_t modeId);
3012+
3013+/**
3014+ * Detaches a mode from the output
3015+ * must be unused, by the given mode.
3016+ */
3017+extern int drmModeDetachMode(int fd, uint32_t outputId, uint32_t modeId);
3018+
3019+extern drmModePropertyPtr drmModeGetProperty(int fd, uint32_t propertyId);
3020+extern void drmModeFreeProperty(drmModePropertyPtr ptr);
3021Index: git/libdrm/xf86drmRandom.c
3022===================================================================
3023--- git.orig/libdrm/xf86drmRandom.c 2008-12-12 17:20:14.000000000 +0000
3024+++ git/libdrm/xf86drmRandom.c 2008-12-12 17:35:22.000000000 +0000
3025@@ -25,8 +25,6 @@
3026 *
3027 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
3028 *
3029- * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drmRandom.c,v 1.4 2000/06/17 00:03:34 martin Exp $
3030- *
3031 * DESCRIPTION
3032 *
3033 * This file contains a simple, straightforward implementation of the Park
3034@@ -73,25 +71,13 @@
3035 *
3036 */
3037
3038-#ifdef HAVE_XORG_CONFIG_H
3039-#include <xorg-config.h>
3040-#endif
3041+#include <stdio.h>
3042+#include <stdlib.h>
3043
3044 #define RANDOM_MAIN 0
3045
3046-#if RANDOM_MAIN
3047-# include <stdio.h>
3048-# include <stdlib.h>
3049-#else
3050-# include "drm.h"
3051+#if !RANDOM_MAIN
3052 # include "xf86drm.h"
3053-# ifdef XFree86LOADER
3054-# include "xf86.h"
3055-# include "xf86_ansic.h"
3056-# else
3057-# include <stdio.h>
3058-# include <stdlib.h>
3059-# endif
3060 #endif
3061
3062 #define RANDOM_MAGIC 0xfeedbeef
3063Index: git/libdrm/xf86drmSL.c
3064===================================================================
3065--- git.orig/libdrm/xf86drmSL.c 2008-12-12 17:20:14.000000000 +0000
3066+++ git/libdrm/xf86drmSL.c 2008-12-12 17:35:22.000000000 +0000
3067@@ -25,8 +25,6 @@
3068 *
3069 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
3070 *
3071- * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drmSL.c,v 1.3 2000/06/17 00:03:34 martin Exp $
3072- *
3073 * DESCRIPTION
3074 *
3075 * This file contains a straightforward skip list implementation.n
3076@@ -40,26 +38,15 @@
3077 *
3078 */
3079
3080-#ifdef HAVE_XORG_CONFIG_H
3081-#include <xorg-config.h>
3082-#endif
3083+#include <stdio.h>
3084+#include <stdlib.h>
3085
3086 #define SL_MAIN 0
3087
3088-#if SL_MAIN
3089-# include <stdio.h>
3090-# include <stdlib.h>
3091-# include <sys/time.h>
3092-#else
3093-# include "drm.h"
3094+#if !SL_MAIN
3095 # include "xf86drm.h"
3096-# ifdef XFree86LOADER
3097-# include "xf86.h"
3098-# include "xf86_ansic.h"
3099-# else
3100-# include <stdio.h>
3101-# include <stdlib.h>
3102-# endif
3103+#else
3104+# include <sys/time.h>
3105 #endif
3106
3107 #define SL_LIST_MAGIC 0xfacade00LU
3108Index: git/libdrm/xf86mm.h
3109===================================================================
3110--- git.orig/libdrm/xf86mm.h 2008-12-12 17:20:14.000000000 +0000
3111+++ git/libdrm/xf86mm.h 2008-12-12 17:35:22.000000000 +0000
3112@@ -29,6 +29,7 @@
3113 #ifndef _XF86MM_H_
3114 #define _XF86MM_H_
3115 #include <stddef.h>
3116+#include <stdint.h>
3117 #include "drm.h"
3118
3119 /*
3120@@ -37,7 +38,7 @@
3121 * be protected using an external mutex.
3122 *
3123 * Note: Don't protect the following functions, as it may lead to deadlocks:
3124- * drmBOUnmap(), drmFenceBuffers().
3125+ * drmBOUnmap().
3126 * The kernel is synchronizing and refcounting buffer maps.
3127 * User space only needs to refcount object usage within the same application.
3128 */
3129@@ -60,7 +61,7 @@
3130 (__item)->next = (__item); \
3131 } while (0)
3132
3133-#define DRMLISTADD(__item, __list) \
3134+#define DRMLISTADD(__item, __list) \
3135 do { \
3136 (__item)->prev = (__list); \
3137 (__item)->next = (__list)->next; \
3138@@ -93,21 +94,23 @@
3139 #define DRMLISTENTRY(__type, __item, __field) \
3140 ((__type *)(((char *) (__item)) - offsetof(__type, __field)))
3141
3142-typedef struct _drmFence{
3143- unsigned handle;
3144- int class;
3145- unsigned type;
3146- unsigned flags;
3147- unsigned signaled;
3148- unsigned pad[4]; /* for future expansion */
3149+typedef struct _drmFence
3150+{
3151+ unsigned handle;
3152+ int fence_class;
3153+ unsigned type;
3154+ unsigned flags;
3155+ unsigned signaled;
3156+ uint32_t sequence;
3157+ unsigned pad[4]; /* for future expansion */
3158 } drmFence;
3159
3160-typedef struct _drmBO{
3161- drm_bo_type_t type;
3162+typedef struct _drmBO
3163+{
3164 unsigned handle;
3165- drm_u64_t mapHandle;
3166- unsigned flags;
3167- unsigned mask;
3168+ uint64_t mapHandle;
3169+ uint64_t flags;
3170+ uint64_t mask;
3171 unsigned mapFlags;
3172 unsigned long size;
3173 unsigned long offset;
3174@@ -115,84 +118,49 @@
3175 unsigned replyFlags;
3176 unsigned fenceFlags;
3177 unsigned pageAlignment;
3178+ unsigned tileInfo;
3179+ unsigned hwTileStride;
3180+ unsigned desiredTileStride;
3181 void *virtual;
3182 void *mapVirtual;
3183 int mapCount;
3184 unsigned pad[8]; /* for future expansion */
3185 } drmBO;
3186
3187-
3188-typedef struct _drmBONode {
3189- drmMMListHead head;
3190- drmBO *buf;
3191- drm_bo_arg_t bo_arg;
3192- unsigned long arg0;
3193- unsigned long arg1;
3194-} drmBONode;
3195-
3196-typedef struct _drmBOList {
3197- unsigned numTarget;
3198- unsigned numCurrent;
3199- unsigned numOnList;
3200- drmMMListHead list;
3201- drmMMListHead free;
3202-} drmBOList;
3203-
3204-/* Fencing */
3205-
3206-extern int drmFenceCreate(int fd, unsigned flags, int class,
3207- unsigned type,
3208- drmFence *fence);
3209-extern int drmFenceDestroy(int fd, const drmFence *fence);
3210-extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
3211-extern int drmFenceUnreference(int fd, const drmFence *fence);
3212-extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
3213-extern int drmFenceSignaled(int fd, drmFence *fence,
3214- unsigned fenceType, int *signaled);
3215-extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
3216- unsigned flush_type);
3217-extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
3218- unsigned emit_type);
3219-extern int drmFenceBuffers(int fd, unsigned flags, drmFence *fence);
3220-
3221-
3222 /*
3223- * Buffer object list functions.
3224+ * Fence functions.
3225 */
3226
3227-extern void drmBOFreeList(drmBOList *list);
3228-extern int drmBOResetList(drmBOList *list);
3229-extern void *drmBOListIterator(drmBOList *list);
3230-extern void *drmBOListNext(drmBOList *list, void *iterator);
3231-extern drmBO *drmBOListBuf(void *iterator);
3232-extern int drmBOCreateList(int numTarget, drmBOList *list);
3233+extern int drmFenceCreate(int fd, unsigned flags, int fence_class,
3234+ unsigned type, drmFence *fence);
3235+extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
3236+extern int drmFenceUnreference(int fd, const drmFence *fence);
3237+extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
3238+extern int drmFenceSignaled(int fd, drmFence *fence,
3239+ unsigned fenceType, int *signaled);
3240+extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
3241+ unsigned flush_type);
3242+extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
3243+ unsigned emit_type);
3244+extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence);
3245+
3246
3247 /*
3248 * Buffer object functions.
3249 */
3250
3251-extern int drmBOCreate(int fd, unsigned long start, unsigned long size,
3252- unsigned pageAlignment,void *user_buffer,
3253- drm_bo_type_t type, unsigned mask,
3254- unsigned hint, drmBO *buf);
3255-extern int drmBODestroy(int fd, drmBO *buf);
3256+extern int drmBOCreate(int fd, unsigned long size,
3257+ unsigned pageAlignment, void *user_buffer,
3258+ uint64_t mask, unsigned hint, drmBO *buf);
3259 extern int drmBOReference(int fd, unsigned handle, drmBO *buf);
3260-extern int drmBOUnReference(int fd, drmBO *buf);
3261+extern int drmBOUnreference(int fd, drmBO *buf);
3262 extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
3263 void **address);
3264 extern int drmBOUnmap(int fd, drmBO *buf);
3265-extern int drmBOValidate(int fd, drmBO *buf, unsigned flags, unsigned mask,
3266- unsigned hint);
3267 extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle);
3268 extern int drmBOInfo(int fd, drmBO *buf);
3269 extern int drmBOBusy(int fd, drmBO *buf, int *busy);
3270
3271-
3272-extern int drmAddValidateItem(drmBOList *list, drmBO *buf, unsigned flags,
3273- unsigned mask,
3274- int *newItem);
3275-extern int drmBOValidateList(int fd, drmBOList *list);
3276-extern int drmBOFenceList(int fd, drmBOList *list, unsigned fenceHandle);
3277 extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint);
3278
3279 /*
3280@@ -202,8 +170,16 @@
3281 extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
3282 unsigned memType);
3283 extern int drmMMTakedown(int fd, unsigned memType);
3284-extern int drmMMLock(int fd, unsigned memType);
3285-extern int drmMMUnlock(int fd, unsigned memType);
3286+extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict);
3287+extern int drmMMUnlock(int fd, unsigned memType, int unlockBM);
3288+extern int drmBOSetStatus(int fd, drmBO *buf,
3289+ uint64_t flags, uint64_t mask,
3290+ unsigned int hint,
3291+ unsigned int desired_tile_stride,
3292+ unsigned int tile_info);
3293+extern int drmBOVersion(int fd, unsigned int *major,
3294+ unsigned int *minor,
3295+ unsigned int *patchlevel);
3296
3297
3298 #endif
3299Index: git/shared-core/Makefile.am
3300===================================================================
3301--- git.orig/shared-core/Makefile.am 2008-12-12 17:20:14.000000000 +0000
3302+++ git/shared-core/Makefile.am 2008-12-12 17:36:30.000000000 +0000
3303@@ -29,10 +29,14 @@
3304 i915_drm.h \
3305 mach64_drm.h \
3306 mga_drm.h \
3307+ nouveau_drm.h \
3308+ psb_drm.h \
3309+ psb_reg.h \
3310 r128_drm.h \
3311 radeon_drm.h \
3312 savage_drm.h \
3313 sis_drm.h \
3314 via_drm.h \
3315+ psb_reg.h \
3316 r300_reg.h \
3317 via_3d_reg.h
3318Index: git/shared-core/Makefile.in
3319===================================================================
3320--- git.orig/shared-core/Makefile.in 2008-12-12 17:20:14.000000000 +0000
3321+++ git/shared-core/Makefile.in 2008-12-12 17:35:31.000000000 +0000
3322@@ -1,8 +1,8 @@
3323-# Makefile.in generated by automake 1.9.6 from Makefile.am.
3324+# Makefile.in generated by automake 1.10.1 from Makefile.am.
3325 # @configure_input@
3326
3327 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3328-# 2003, 2004, 2005 Free Software Foundation, Inc.
3329+# 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3330 # This Makefile.in is free software; the Free Software Foundation
3331 # gives unlimited permission to copy and/or distribute it,
3332 # with or without modifications, as long as this notice is preserved.
3333@@ -38,15 +38,11 @@
3334 # however, r300 and via need their reg headers installed in order to build.
3335 # better solutions are welcome.
3336
3337-srcdir = @srcdir@
3338-top_srcdir = @top_srcdir@
3339 VPATH = @srcdir@
3340 pkgdatadir = $(datadir)/@PACKAGE@
3341 pkglibdir = $(libdir)/@PACKAGE@
3342 pkgincludedir = $(includedir)/@PACKAGE@
3343-top_builddir = ..
3344 am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
3345-INSTALL = @INSTALL@
3346 install_sh_DATA = $(install_sh) -c -m 644
3347 install_sh_PROGRAM = $(install_sh) -c
3348 install_sh_SCRIPT = $(install_sh) -c
3349@@ -85,8 +81,6 @@
3350 CTAGS = ctags
3351 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
3352 ACLOCAL = @ACLOCAL@
3353-AMDEP_FALSE = @AMDEP_FALSE@
3354-AMDEP_TRUE = @AMDEP_TRUE@
3355 AMTAR = @AMTAR@
3356 AR = @AR@
3357 AUTOCONF = @AUTOCONF@
3358@@ -98,33 +92,39 @@
3359 CFLAGS = @CFLAGS@
3360 CPP = @CPP@
3361 CPPFLAGS = @CPPFLAGS@
3362-CXX = @CXX@
3363-CXXCPP = @CXXCPP@
3364-CXXDEPMODE = @CXXDEPMODE@
3365-CXXFLAGS = @CXXFLAGS@
3366 CYGPATH_W = @CYGPATH_W@
3367 DEFS = @DEFS@
3368 DEPDIR = @DEPDIR@
3369-ECHO = @ECHO@
3370+DSYMUTIL = @DSYMUTIL@
3371+DUMPBIN = @DUMPBIN@
3372 ECHO_C = @ECHO_C@
3373 ECHO_N = @ECHO_N@
3374 ECHO_T = @ECHO_T@
3375 EGREP = @EGREP@
3376 EXEEXT = @EXEEXT@
3377-F77 = @F77@
3378-FFLAGS = @FFLAGS@
3379+FGREP = @FGREP@
3380+GREP = @GREP@
3381+INSTALL = @INSTALL@
3382 INSTALL_DATA = @INSTALL_DATA@
3383 INSTALL_PROGRAM = @INSTALL_PROGRAM@
3384 INSTALL_SCRIPT = @INSTALL_SCRIPT@
3385 INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
3386+LD = @LD@
3387 LDFLAGS = @LDFLAGS@
3388 LIBOBJS = @LIBOBJS@
3389 LIBS = @LIBS@
3390 LIBTOOL = @LIBTOOL@
3391+LIPO = @LIPO@
3392 LN_S = @LN_S@
3393 LTLIBOBJS = @LTLIBOBJS@
3394 MAKEINFO = @MAKEINFO@
3395+MKDIR_P = @MKDIR_P@
3396+NM = @NM@
3397+NMEDIT = @NMEDIT@
3398+OBJDUMP = @OBJDUMP@
3399 OBJEXT = @OBJEXT@
3400+OTOOL = @OTOOL@
3401+OTOOL64 = @OTOOL64@
3402 PACKAGE = @PACKAGE@
3403 PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
3404 PACKAGE_NAME = @PACKAGE_NAME@
3405@@ -133,20 +133,17 @@
3406 PACKAGE_VERSION = @PACKAGE_VERSION@
3407 PATH_SEPARATOR = @PATH_SEPARATOR@
3408 RANLIB = @RANLIB@
3409+SED = @SED@
3410 SET_MAKE = @SET_MAKE@
3411 SHELL = @SHELL@
3412 STRIP = @STRIP@
3413 VERSION = @VERSION@
3414-ac_ct_AR = @ac_ct_AR@
3415+abs_builddir = @abs_builddir@
3416+abs_srcdir = @abs_srcdir@
3417+abs_top_builddir = @abs_top_builddir@
3418+abs_top_srcdir = @abs_top_srcdir@
3419 ac_ct_CC = @ac_ct_CC@
3420-ac_ct_CXX = @ac_ct_CXX@
3421-ac_ct_F77 = @ac_ct_F77@
3422-ac_ct_RANLIB = @ac_ct_RANLIB@
3423-ac_ct_STRIP = @ac_ct_STRIP@
3424-am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
3425-am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
3426-am__fastdepCXX_FALSE = @am__fastdepCXX_FALSE@
3427-am__fastdepCXX_TRUE = @am__fastdepCXX_TRUE@
3428+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
3429 am__include = @am__include@
3430 am__leading_dot = @am__leading_dot@
3431 am__quote = @am__quote@
3432@@ -158,29 +155,41 @@
3433 build_cpu = @build_cpu@
3434 build_os = @build_os@
3435 build_vendor = @build_vendor@
3436+builddir = @builddir@
3437 datadir = @datadir@
3438+datarootdir = @datarootdir@
3439+docdir = @docdir@
3440+dvidir = @dvidir@
3441 exec_prefix = @exec_prefix@
3442 host = @host@
3443 host_alias = @host_alias@
3444 host_cpu = @host_cpu@
3445 host_os = @host_os@
3446 host_vendor = @host_vendor@
3447+htmldir = @htmldir@
3448 includedir = @includedir@
3449 infodir = @infodir@
3450 install_sh = @install_sh@
3451 libdir = @libdir@
3452 libexecdir = @libexecdir@
3453+localedir = @localedir@
3454 localstatedir = @localstatedir@
3455+lt_ECHO = @lt_ECHO@
3456 mandir = @mandir@
3457 mkdir_p = @mkdir_p@
3458 oldincludedir = @oldincludedir@
3459+pdfdir = @pdfdir@
3460 pkgconfigdir = @pkgconfigdir@
3461 prefix = @prefix@
3462 program_transform_name = @program_transform_name@
3463+psdir = @psdir@
3464 sbindir = @sbindir@
3465 sharedstatedir = @sharedstatedir@
3466+srcdir = @srcdir@
3467 sysconfdir = @sysconfdir@
3468 target_alias = @target_alias@
3469+top_builddir = @top_builddir@
3470+top_srcdir = @top_srcdir@
3471 klibdrmincludedir = ${includedir}/drm
3472 klibdrminclude_HEADERS = \
3473 drm.h \
3474@@ -188,13 +197,18 @@
3475 i915_drm.h \
3476 mach64_drm.h \
3477 mga_drm.h \
3478+ nouveau_drm.h \
3479+ psb_drm.h \
3480+ psb_reg.h \
3481 r128_drm.h \
3482 radeon_drm.h \
3483 savage_drm.h \
3484 sis_drm.h \
3485 via_drm.h \
3486+ psb_reg.h \
3487 r300_reg.h \
3488- via_3d_reg.h
3489+ via_3d_reg.h \
3490+ xgi_drm.h
3491
3492 all: all-am
3493
3494@@ -234,13 +248,9 @@
3495
3496 clean-libtool:
3497 -rm -rf .libs _libs
3498-
3499-distclean-libtool:
3500- -rm -f libtool
3501-uninstall-info-am:
3502 install-klibdrmincludeHEADERS: $(klibdrminclude_HEADERS)
3503 @$(NORMAL_INSTALL)
3504- test -z "$(klibdrmincludedir)" || $(mkdir_p) "$(DESTDIR)$(klibdrmincludedir)"
3505+ test -z "$(klibdrmincludedir)" || $(MKDIR_P) "$(DESTDIR)$(klibdrmincludedir)"
3506 @list='$(klibdrminclude_HEADERS)'; for p in $$list; do \
3507 if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
3508 f=$(am__strip_dir) \
3509@@ -261,8 +271,8 @@
3510 unique=`for i in $$list; do \
3511 if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
3512 done | \
3513- $(AWK) ' { files[$$0] = 1; } \
3514- END { for (i in files) print i; }'`; \
3515+ $(AWK) '{ files[$$0] = 1; nonemtpy = 1; } \
3516+ END { if (nonempty) { for (i in files) print i; }; }'`; \
3517 mkid -fID $$unique
3518 tags: TAGS
3519
3520@@ -274,8 +284,8 @@
3521 unique=`for i in $$list; do \
3522 if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
3523 done | \
3524- $(AWK) ' { files[$$0] = 1; } \
3525- END { for (i in files) print i; }'`; \
3526+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
3527+ END { if (nonempty) { for (i in files) print i; }; }'`; \
3528 if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \
3529 test -n "$$unique" || unique=$$empty_fix; \
3530 $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
3531@@ -285,13 +295,12 @@
3532 CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \
3533 $(TAGS_FILES) $(LISP)
3534 tags=; \
3535- here=`pwd`; \
3536 list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
3537 unique=`for i in $$list; do \
3538 if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
3539 done | \
3540- $(AWK) ' { files[$$0] = 1; } \
3541- END { for (i in files) print i; }'`; \
3542+ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
3543+ END { if (nonempty) { for (i in files) print i; }; }'`; \
3544 test -z "$(CTAGS_ARGS)$$tags$$unique" \
3545 || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
3546 $$tags $$unique
3547@@ -305,22 +314,21 @@
3548 -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
3549
3550 distdir: $(DISTFILES)
3551- @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
3552- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
3553- list='$(DISTFILES)'; for file in $$list; do \
3554- case $$file in \
3555- $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \
3556- $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \
3557- esac; \
3558+ @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
3559+ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
3560+ list='$(DISTFILES)'; \
3561+ dist_files=`for file in $$list; do echo $$file; done | \
3562+ sed -e "s|^$$srcdirstrip/||;t" \
3563+ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
3564+ case $$dist_files in \
3565+ */*) $(MKDIR_P) `echo "$$dist_files" | \
3566+ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
3567+ sort -u` ;; \
3568+ esac; \
3569+ for file in $$dist_files; do \
3570 if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
3571- dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \
3572- if test "$$dir" != "$$file" && test "$$dir" != "."; then \
3573- dir="/$$dir"; \
3574- $(mkdir_p) "$(distdir)$$dir"; \
3575- else \
3576- dir=''; \
3577- fi; \
3578 if test -d $$d/$$file; then \
3579+ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
3580 if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
3581 cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \
3582 fi; \
3583@@ -336,7 +344,7 @@
3584 all-am: Makefile $(HEADERS)
3585 installdirs:
3586 for dir in "$(DESTDIR)$(klibdrmincludedir)"; do \
3587- test -z "$$dir" || $(mkdir_p) "$$dir"; \
3588+ test -z "$$dir" || $(MKDIR_P) "$$dir"; \
3589 done
3590 install: install-am
3591 install-exec: install-exec-am
3592@@ -368,8 +376,7 @@
3593
3594 distclean: distclean-am
3595 -rm -f Makefile
3596-distclean-am: clean-am distclean-generic distclean-libtool \
3597- distclean-tags
3598+distclean-am: clean-am distclean-generic distclean-tags
3599
3600 dvi: dvi-am
3601
3602@@ -383,12 +390,20 @@
3603
3604 install-data-am: install-klibdrmincludeHEADERS
3605
3606+install-dvi: install-dvi-am
3607+
3608 install-exec-am:
3609
3610+install-html: install-html-am
3611+
3612 install-info: install-info-am
3613
3614 install-man:
3615
3616+install-pdf: install-pdf-am
3617+
3618+install-ps: install-ps-am
3619+
3620 installcheck-am:
3621
3622 maintainer-clean: maintainer-clean-am
3623@@ -407,19 +422,22 @@
3624
3625 ps-am:
3626
3627-uninstall-am: uninstall-info-am uninstall-klibdrmincludeHEADERS
3628+uninstall-am: uninstall-klibdrmincludeHEADERS
3629+
3630+.MAKE: install-am install-strip
3631
3632 .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \
3633 clean-libtool ctags distclean distclean-generic \
3634 distclean-libtool distclean-tags distdir dvi dvi-am html \
3635 html-am info info-am install install-am install-data \
3636- install-data-am install-exec install-exec-am install-info \
3637+ install-data-am install-dvi install-dvi-am install-exec \
3638+ install-exec-am install-html install-html-am install-info \
3639 install-info-am install-klibdrmincludeHEADERS install-man \
3640+ install-pdf install-pdf-am install-ps install-ps-am \
3641 install-strip installcheck installcheck-am installdirs \
3642 maintainer-clean maintainer-clean-generic mostlyclean \
3643 mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
3644- tags uninstall uninstall-am uninstall-info-am \
3645- uninstall-klibdrmincludeHEADERS
3646+ tags uninstall uninstall-am uninstall-klibdrmincludeHEADERS
3647
3648 # Tell versions [3.59,3.63) of GNU make to not export all variables.
3649 # Otherwise a system limit (for SysV at least) may be exceeded.
3650Index: git/shared-core/drm.h
3651===================================================================
3652--- git.orig/shared-core/drm.h 2008-12-12 17:20:14.000000000 +0000
3653+++ git/shared-core/drm.h 2008-12-12 17:35:22.000000000 +0000
3654@@ -61,6 +61,9 @@
3655 #ifndef __user
3656 #define __user
3657 #endif
3658+#ifndef __iomem
3659+#define __iomem
3660+#endif
3661
3662 #ifdef __GNUC__
3663 # define DEPRECATED __attribute__ ((deprecated))
3664@@ -77,14 +80,7 @@
3665 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
3666 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
3667 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
3668-#if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
3669-/* Prevent name collision when including sys/ioccom.h */
3670-#undef ioctl
3671-#include <sys/ioccom.h>
3672-#define ioctl(a,b,c) xf86ioctl(a,b,c)
3673-#else
3674 #include <sys/ioccom.h>
3675-#endif /* __FreeBSD__ && xf86ioctl */
3676 #define DRM_IOCTL_NR(n) ((n) & 0xff)
3677 #define DRM_IOC_VOID IOC_VOID
3678 #define DRM_IOC_READ IOC_OUT
3679@@ -93,24 +89,6 @@
3680 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
3681 #endif
3682
3683-#define XFREE86_VERSION(major,minor,patch,snap) \
3684- ((major << 16) | (minor << 8) | patch)
3685-
3686-#ifndef CONFIG_XFREE86_VERSION
3687-#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
3688-#endif
3689-
3690-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
3691-#define DRM_PROC_DEVICES "/proc/devices"
3692-#define DRM_PROC_MISC "/proc/misc"
3693-#define DRM_PROC_DRM "/proc/drm"
3694-#define DRM_DEV_DRM "/dev/drm"
3695-#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
3696-#define DRM_DEV_UID 0
3697-#define DRM_DEV_GID 0
3698-#endif
3699-
3700-#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
3701 #ifdef __OpenBSD__
3702 #define DRM_MAJOR 81
3703 #endif
3704@@ -118,7 +96,7 @@
3705 #define DRM_MAJOR 226
3706 #endif
3707 #define DRM_MAX_MINOR 15
3708-#endif
3709+
3710 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
3711 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
3712 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
3713@@ -131,16 +109,9 @@
3714 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
3715
3716 #if defined(__linux__)
3717-#if defined(__KERNEL__)
3718-typedef __u64 drm_u64_t;
3719-#else
3720-typedef unsigned long long drm_u64_t;
3721-#endif
3722-
3723 typedef unsigned int drm_handle_t;
3724 #else
3725 #include <sys/types.h>
3726-typedef u_int64_t drm_u64_t;
3727 typedef unsigned long drm_handle_t; /**< To mapped regions */
3728 #endif
3729 typedef unsigned int drm_context_t; /**< GLXContext handle */
3730@@ -156,31 +127,23 @@
3731 * \note KW: Actually it's illegal to change either for
3732 * backwards-compatibility reasons.
3733 */
3734-typedef struct drm_clip_rect {
3735+struct drm_clip_rect {
3736 unsigned short x1;
3737 unsigned short y1;
3738 unsigned short x2;
3739 unsigned short y2;
3740-} drm_clip_rect_t;
3741-
3742-/**
3743- * Drawable information.
3744- */
3745-typedef struct drm_drawable_info {
3746- unsigned int num_rects;
3747- drm_clip_rect_t *rects;
3748-} drm_drawable_info_t;
3749+};
3750
3751 /**
3752 * Texture region,
3753 */
3754-typedef struct drm_tex_region {
3755+struct drm_tex_region {
3756 unsigned char next;
3757 unsigned char prev;
3758 unsigned char in_use;
3759 unsigned char padding;
3760 unsigned int age;
3761-} drm_tex_region_t;
3762+};
3763
3764 /**
3765 * Hardware lock.
3766@@ -189,10 +152,10 @@
3767 * processor bus contention on a multiprocessor system, there should not be any
3768 * other data stored in the same cache line.
3769 */
3770-typedef struct drm_hw_lock {
3771+struct drm_hw_lock {
3772 __volatile__ unsigned int lock; /**< lock variable */
3773 char padding[60]; /**< Pad to cache line */
3774-} drm_hw_lock_t;
3775+};
3776
3777 /* This is beyond ugly, and only works on GCC. However, it allows me to use
3778 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
3779@@ -215,7 +178,7 @@
3780 *
3781 * \sa drmGetVersion().
3782 */
3783-typedef struct drm_version {
3784+struct drm_version {
3785 int version_major; /**< Major version */
3786 int version_minor; /**< Minor version */
3787 int version_patchlevel; /**< Patch level */
3788@@ -225,35 +188,35 @@
3789 char __user *date; /**< User-space buffer to hold date */
3790 DRM_SIZE_T desc_len; /**< Length of desc buffer */
3791 char __user *desc; /**< User-space buffer to hold desc */
3792-} drm_version_t;
3793+};
3794
3795 /**
3796 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
3797 *
3798 * \sa drmGetBusid() and drmSetBusId().
3799 */
3800-typedef struct drm_unique {
3801+struct drm_unique {
3802 DRM_SIZE_T unique_len; /**< Length of unique */
3803 char __user *unique; /**< Unique name for driver instantiation */
3804-} drm_unique_t;
3805+};
3806
3807 #undef DRM_SIZE_T
3808
3809-typedef struct drm_list {
3810+struct drm_list {
3811 int count; /**< Length of user-space structures */
3812- drm_version_t __user *version;
3813-} drm_list_t;
3814+ struct drm_version __user *version;
3815+};
3816
3817-typedef struct drm_block {
3818+struct drm_block {
3819 int unused;
3820-} drm_block_t;
3821+};
3822
3823 /**
3824 * DRM_IOCTL_CONTROL ioctl argument type.
3825 *
3826 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
3827 */
3828-typedef struct drm_control {
3829+struct drm_control {
3830 enum {
3831 DRM_ADD_COMMAND,
3832 DRM_RM_COMMAND,
3833@@ -261,12 +224,12 @@
3834 DRM_UNINST_HANDLER
3835 } func;
3836 int irq;
3837-} drm_control_t;
3838+};
3839
3840 /**
3841 * Type of memory to map.
3842 */
3843-typedef enum drm_map_type {
3844+enum drm_map_type {
3845 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
3846 _DRM_REGISTERS = 1, /**< no caching, no core dump */
3847 _DRM_SHM = 2, /**< shared, cached */
3848@@ -274,25 +237,26 @@
3849 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
3850 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
3851 _DRM_TTM = 6
3852-} drm_map_type_t;
3853+};
3854
3855 /**
3856 * Memory mapping flags.
3857 */
3858-typedef enum drm_map_flags {
3859+enum drm_map_flags {
3860 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
3861 _DRM_READ_ONLY = 0x02,
3862 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
3863 _DRM_KERNEL = 0x08, /**< kernel requires access */
3864 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
3865 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
3866- _DRM_REMOVABLE = 0x40 /**< Removable mapping */
3867-} drm_map_flags_t;
3868+ _DRM_REMOVABLE = 0x40, /**< Removable mapping */
3869+ _DRM_DRIVER = 0x80 /**< Driver will take care of it */
3870+};
3871
3872-typedef struct drm_ctx_priv_map {
3873+struct drm_ctx_priv_map {
3874 unsigned int ctx_id; /**< Context requesting private mapping */
3875 void *handle; /**< Handle of map */
3876-} drm_ctx_priv_map_t;
3877+};
3878
3879 /**
3880 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
3881@@ -300,30 +264,30 @@
3882 *
3883 * \sa drmAddMap().
3884 */
3885-typedef struct drm_map {
3886+struct drm_map {
3887 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
3888 unsigned long size; /**< Requested physical size (bytes) */
3889- drm_map_type_t type; /**< Type of memory to map */
3890- drm_map_flags_t flags; /**< Flags */
3891+ enum drm_map_type type; /**< Type of memory to map */
3892+ enum drm_map_flags flags; /**< Flags */
3893 void *handle; /**< User-space: "Handle" to pass to mmap() */
3894 /**< Kernel-space: kernel-virtual address */
3895 int mtrr; /**< MTRR slot used */
3896 /* Private data */
3897-} drm_map_t;
3898+};
3899
3900 /**
3901 * DRM_IOCTL_GET_CLIENT ioctl argument type.
3902 */
3903-typedef struct drm_client {
3904+struct drm_client {
3905 int idx; /**< Which client desired? */
3906 int auth; /**< Is client authenticated? */
3907 unsigned long pid; /**< Process ID */
3908 unsigned long uid; /**< User ID */
3909 unsigned long magic; /**< Magic */
3910 unsigned long iocs; /**< Ioctl count */
3911-} drm_client_t;
3912+};
3913
3914-typedef enum {
3915+enum drm_stat_type {
3916 _DRM_STAT_LOCK,
3917 _DRM_STAT_OPENS,
3918 _DRM_STAT_CLOSES,
3919@@ -341,23 +305,23 @@
3920 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
3921 _DRM_STAT_MISSED /**< Missed DMA opportunity */
3922 /* Add to the *END* of the list */
3923-} drm_stat_type_t;
3924+};
3925
3926 /**
3927 * DRM_IOCTL_GET_STATS ioctl argument type.
3928 */
3929-typedef struct drm_stats {
3930+struct drm_stats {
3931 unsigned long count;
3932 struct {
3933 unsigned long value;
3934- drm_stat_type_t type;
3935+ enum drm_stat_type type;
3936 } data[15];
3937-} drm_stats_t;
3938+};
3939
3940 /**
3941 * Hardware locking flags.
3942 */
3943-typedef enum drm_lock_flags {
3944+enum drm_lock_flags {
3945 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
3946 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
3947 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
3948@@ -367,17 +331,17 @@
3949 full-screen DGA-like mode. */
3950 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
3951 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
3952-} drm_lock_flags_t;
3953+};
3954
3955 /**
3956 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
3957 *
3958 * \sa drmGetLock() and drmUnlock().
3959 */
3960-typedef struct drm_lock {
3961+struct drm_lock {
3962 int context;
3963- drm_lock_flags_t flags;
3964-} drm_lock_t;
3965+ enum drm_lock_flags flags;
3966+};
3967
3968 /**
3969 * DMA flags
3970@@ -387,7 +351,7 @@
3971 *
3972 * \sa drm_dma.
3973 */
3974-typedef enum drm_dma_flags {
3975+enum drm_dma_flags {
3976 /* Flags for DMA buffer dispatch */
3977 _DRM_DMA_BLOCK = 0x01, /**<
3978 * Block until buffer dispatched.
3979@@ -406,14 +370,14 @@
3980 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
3981 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
3982 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
3983-} drm_dma_flags_t;
3984+};
3985
3986 /**
3987 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
3988 *
3989 * \sa drmAddBufs().
3990 */
3991-typedef struct drm_buf_desc {
3992+struct drm_buf_desc {
3993 int count; /**< Number of buffers of this size */
3994 int size; /**< Size in bytes */
3995 int low_mark; /**< Low water mark */
3996@@ -429,48 +393,48 @@
3997 * Start address of where the AGP buffers are
3998 * in the AGP aperture
3999 */
4000-} drm_buf_desc_t;
4001+};
4002
4003 /**
4004 * DRM_IOCTL_INFO_BUFS ioctl argument type.
4005 */
4006-typedef struct drm_buf_info {
4007+struct drm_buf_info {
4008 int count; /**< Number of buffers described in list */
4009- drm_buf_desc_t __user *list; /**< List of buffer descriptions */
4010-} drm_buf_info_t;
4011+ struct drm_buf_desc __user *list; /**< List of buffer descriptions */
4012+};
4013
4014 /**
4015 * DRM_IOCTL_FREE_BUFS ioctl argument type.
4016 */
4017-typedef struct drm_buf_free {
4018+struct drm_buf_free {
4019 int count;
4020 int __user *list;
4021-} drm_buf_free_t;
4022+};
4023
4024 /**
4025 * Buffer information
4026 *
4027 * \sa drm_buf_map.
4028 */
4029-typedef struct drm_buf_pub {
4030+struct drm_buf_pub {
4031 int idx; /**< Index into the master buffer list */
4032 int total; /**< Buffer size */
4033 int used; /**< Amount of buffer in use (for DMA) */
4034 void __user *address; /**< Address of buffer */
4035-} drm_buf_pub_t;
4036+};
4037
4038 /**
4039 * DRM_IOCTL_MAP_BUFS ioctl argument type.
4040 */
4041-typedef struct drm_buf_map {
4042+struct drm_buf_map {
4043 int count; /**< Length of the buffer list */
4044 #if defined(__cplusplus)
4045 void __user *c_virtual;
4046 #else
4047 void __user *virtual; /**< Mmap'd area in user-virtual */
4048 #endif
4049- drm_buf_pub_t __user *list; /**< Buffer information */
4050-} drm_buf_map_t;
4051+ struct drm_buf_pub __user *list; /**< Buffer information */
4052+};
4053
4054 /**
4055 * DRM_IOCTL_DMA ioctl argument type.
4056@@ -479,48 +443,48 @@
4057 *
4058 * \sa drmDMA().
4059 */
4060-typedef struct drm_dma {
4061+struct drm_dma {
4062 int context; /**< Context handle */
4063 int send_count; /**< Number of buffers to send */
4064 int __user *send_indices; /**< List of handles to buffers */
4065 int __user *send_sizes; /**< Lengths of data to send */
4066- drm_dma_flags_t flags; /**< Flags */
4067+ enum drm_dma_flags flags; /**< Flags */
4068 int request_count; /**< Number of buffers requested */
4069 int request_size; /**< Desired size for buffers */
4070 int __user *request_indices; /**< Buffer information */
4071 int __user *request_sizes;
4072 int granted_count; /**< Number of buffers granted */
4073-} drm_dma_t;
4074+};
4075
4076-typedef enum {
4077+enum drm_ctx_flags {
4078 _DRM_CONTEXT_PRESERVED = 0x01,
4079 _DRM_CONTEXT_2DONLY = 0x02
4080-} drm_ctx_flags_t;
4081+};
4082
4083 /**
4084 * DRM_IOCTL_ADD_CTX ioctl argument type.
4085 *
4086 * \sa drmCreateContext() and drmDestroyContext().
4087 */
4088-typedef struct drm_ctx {
4089+struct drm_ctx {
4090 drm_context_t handle;
4091- drm_ctx_flags_t flags;
4092-} drm_ctx_t;
4093+ enum drm_ctx_flags flags;
4094+};
4095
4096 /**
4097 * DRM_IOCTL_RES_CTX ioctl argument type.
4098 */
4099-typedef struct drm_ctx_res {
4100+struct drm_ctx_res {
4101 int count;
4102- drm_ctx_t __user *contexts;
4103-} drm_ctx_res_t;
4104+ struct drm_ctx __user *contexts;
4105+};
4106
4107 /**
4108 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
4109 */
4110-typedef struct drm_draw {
4111+struct drm_draw {
4112 drm_drawable_t handle;
4113-} drm_draw_t;
4114+};
4115
4116 /**
4117 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
4118@@ -529,52 +493,53 @@
4119 DRM_DRAWABLE_CLIPRECTS,
4120 } drm_drawable_info_type_t;
4121
4122-typedef struct drm_update_draw {
4123+struct drm_update_draw {
4124 drm_drawable_t handle;
4125 unsigned int type;
4126 unsigned int num;
4127 unsigned long long data;
4128-} drm_update_draw_t;
4129+};
4130
4131 /**
4132 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
4133 */
4134-typedef struct drm_auth {
4135+struct drm_auth {
4136 drm_magic_t magic;
4137-} drm_auth_t;
4138+};
4139
4140 /**
4141 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
4142 *
4143 * \sa drmGetInterruptFromBusID().
4144 */
4145-typedef struct drm_irq_busid {
4146+struct drm_irq_busid {
4147 int irq; /**< IRQ number */
4148 int busnum; /**< bus number */
4149 int devnum; /**< device number */
4150 int funcnum; /**< function number */
4151-} drm_irq_busid_t;
4152+};
4153
4154-typedef enum {
4155+enum drm_vblank_seq_type {
4156 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
4157 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
4158+ _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
4159 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
4160 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
4161 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
4162-} drm_vblank_seq_type_t;
4163+};
4164
4165 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
4166 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
4167 _DRM_VBLANK_NEXTONMISS)
4168
4169 struct drm_wait_vblank_request {
4170- drm_vblank_seq_type_t type;
4171+ enum drm_vblank_seq_type type;
4172 unsigned int sequence;
4173 unsigned long signal;
4174 };
4175
4176 struct drm_wait_vblank_reply {
4177- drm_vblank_seq_type_t type;
4178+ enum drm_vblank_seq_type type;
4179 unsigned int sequence;
4180 long tval_sec;
4181 long tval_usec;
4182@@ -585,41 +550,41 @@
4183 *
4184 * \sa drmWaitVBlank().
4185 */
4186-typedef union drm_wait_vblank {
4187+union drm_wait_vblank {
4188 struct drm_wait_vblank_request request;
4189 struct drm_wait_vblank_reply reply;
4190-} drm_wait_vblank_t;
4191+};
4192
4193 /**
4194 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
4195 *
4196 * \sa drmAgpEnable().
4197 */
4198-typedef struct drm_agp_mode {
4199+struct drm_agp_mode {
4200 unsigned long mode; /**< AGP mode */
4201-} drm_agp_mode_t;
4202+};
4203
4204 /**
4205 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
4206 *
4207 * \sa drmAgpAlloc() and drmAgpFree().
4208 */
4209-typedef struct drm_agp_buffer {
4210+struct drm_agp_buffer {
4211 unsigned long size; /**< In bytes -- will round to page boundary */
4212 unsigned long handle; /**< Used for binding / unbinding */
4213 unsigned long type; /**< Type of memory to allocate */
4214 unsigned long physical; /**< Physical used by i810 */
4215-} drm_agp_buffer_t;
4216+};
4217
4218 /**
4219 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
4220 *
4221 * \sa drmAgpBind() and drmAgpUnbind().
4222 */
4223-typedef struct drm_agp_binding {
4224+struct drm_agp_binding {
4225 unsigned long handle; /**< From drm_agp_buffer */
4226 unsigned long offset; /**< In bytes -- will round to page boundary */
4227-} drm_agp_binding_t;
4228+};
4229
4230 /**
4231 * DRM_IOCTL_AGP_INFO ioctl argument type.
4232@@ -628,7 +593,7 @@
4233 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
4234 * drmAgpVendorId() and drmAgpDeviceId().
4235 */
4236-typedef struct drm_agp_info {
4237+struct drm_agp_info {
4238 int agp_version_major;
4239 int agp_version_minor;
4240 unsigned long mode;
4241@@ -642,151 +607,177 @@
4242 unsigned short id_vendor;
4243 unsigned short id_device;
4244 /*@} */
4245-} drm_agp_info_t;
4246+};
4247
4248 /**
4249 * DRM_IOCTL_SG_ALLOC ioctl argument type.
4250 */
4251-typedef struct drm_scatter_gather {
4252+struct drm_scatter_gather {
4253 unsigned long size; /**< In bytes -- will round to page boundary */
4254 unsigned long handle; /**< Used for mapping / unmapping */
4255-} drm_scatter_gather_t;
4256+};
4257
4258 /**
4259 * DRM_IOCTL_SET_VERSION ioctl argument type.
4260 */
4261-typedef struct drm_set_version {
4262+struct drm_set_version {
4263 int drm_di_major;
4264 int drm_di_minor;
4265 int drm_dd_major;
4266 int drm_dd_minor;
4267-} drm_set_version_t;
4268+};
4269
4270
4271 #define DRM_FENCE_FLAG_EMIT 0x00000001
4272 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
4273 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
4274 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
4275+#define DRM_FENCE_FLAG_NO_USER 0x00000010
4276
4277 /* Reserved for driver use */
4278 #define DRM_FENCE_MASK_DRIVER 0xFF000000
4279
4280 #define DRM_FENCE_TYPE_EXE 0x00000001
4281
4282-typedef struct drm_fence_arg {
4283- unsigned handle;
4284- int class;
4285- unsigned type;
4286- unsigned flags;
4287- unsigned signaled;
4288- unsigned expand_pad[4]; /*Future expansion */
4289- enum {
4290- drm_fence_create,
4291- drm_fence_destroy,
4292- drm_fence_reference,
4293- drm_fence_unreference,
4294- drm_fence_signaled,
4295- drm_fence_flush,
4296- drm_fence_wait,
4297- drm_fence_emit,
4298- drm_fence_buffers
4299- } op;
4300-} drm_fence_arg_t;
4301+struct drm_fence_arg {
4302+ unsigned int handle;
4303+ unsigned int fence_class;
4304+ unsigned int type;
4305+ unsigned int flags;
4306+ unsigned int signaled;
4307+ unsigned int error;
4308+ unsigned int sequence;
4309+ unsigned int pad64;
4310+ uint64_t expand_pad[2]; /*Future expansion */
4311+};
4312
4313 /* Buffer permissions, referring to how the GPU uses the buffers.
4314- these translate to fence types used for the buffers.
4315- Typically a texture buffer is read, A destination buffer is write and
4316- a command (batch-) buffer is exe. Can be or-ed together. */
4317-
4318-#define DRM_BO_FLAG_READ 0x00000001
4319-#define DRM_BO_FLAG_WRITE 0x00000002
4320-#define DRM_BO_FLAG_EXE 0x00000004
4321+ * these translate to fence types used for the buffers.
4322+ * Typically a texture buffer is read, A destination buffer is write and
4323+ * a command (batch-) buffer is exe. Can be or-ed together.
4324+ */
4325+
4326+#define DRM_BO_FLAG_READ (1ULL << 0)
4327+#define DRM_BO_FLAG_WRITE (1ULL << 1)
4328+#define DRM_BO_FLAG_EXE (1ULL << 2)
4329
4330 /*
4331 * Status flags. Can be read to determine the actual state of a buffer.
4332+ * Can also be set in the buffer mask before validation.
4333+ */
4334+
4335+/*
4336+ * Mask: Never evict this buffer. Not even with force. This type of buffer is only
4337+ * available to root and must be manually removed before buffer manager shutdown
4338+ * or lock.
4339+ * Flags: Acknowledge
4340+ */
4341+#define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
4342+
4343+/*
4344+ * Mask: Require that the buffer is placed in mappable memory when validated.
4345+ * If not set the buffer may or may not be in mappable memory when validated.
4346+ * Flags: If set, the buffer is in mappable memory.
4347+ */
4348+#define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
4349+
4350+/* Mask: The buffer should be shareable with other processes.
4351+ * Flags: The buffer is shareable with other processes.
4352+ */
4353+#define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
4354+
4355+/* Mask: If set, place the buffer in cache-coherent memory if available.
4356+ * If clear, never place the buffer in cache coherent memory if validated.
4357+ * Flags: The buffer is currently in cache-coherent memory.
4358+ */
4359+#define DRM_BO_FLAG_CACHED (1ULL << 7)
4360+
4361+/* Mask: Make sure that every time this buffer is validated,
4362+ * it ends up on the same location provided that the memory mask is the same.
4363+ * The buffer will also not be evicted when claiming space for
4364+ * other buffers. Basically a pinned buffer but it may be thrown out as
4365+ * part of buffer manager shutdown or locking.
4366+ * Flags: Acknowledge.
4367+ */
4368+#define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
4369+
4370+/* Mask: Make sure the buffer is in cached memory when mapped
4371+ * Flags: Acknowledge.
4372+ * Buffers allocated with this flag should not be used for suballocators
4373+ * This type may have issues on CPUs with over-aggressive caching
4374+ * http://marc.info/?l=linux-kernel&m=102376926732464&w=2
4375+ */
4376+#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
4377+
4378+
4379+/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
4380+ * Flags: Acknowledge.
4381 */
4382+#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
4383
4384-/*
4385- * Cannot evict this buffer. Not even with force. This type of buffer should
4386- * only be available for root, and must be manually removed before buffer
4387- * manager shutdown or swapout.
4388- */
4389-#define DRM_BO_FLAG_NO_EVICT 0x00000010
4390-/* Always keep a system memory shadow to a vram buffer */
4391-#define DRM_BO_FLAG_SHADOW_VRAM 0x00000020
4392-/* The buffer is shareable with other processes */
4393-#define DRM_BO_FLAG_SHAREABLE 0x00000040
4394-/* The buffer is currently cached */
4395-#define DRM_BO_FLAG_CACHED 0x00000080
4396-/* Make sure that every time this buffer is validated, it ends up on the same
4397- * location. The buffer will also not be evicted when claiming space for
4398- * other buffers. Basically a pinned buffer but it may be thrown out as
4399- * part of buffer manager shutdown or swapout. Not supported yet.*/
4400-#define DRM_BO_FLAG_NO_MOVE 0x00000100
4401-
4402-/* Make sure the buffer is in cached memory when mapped for reading */
4403-#define DRM_BO_FLAG_READ_CACHED 0x00080000
4404-/* When there is a choice between VRAM and TT, prefer VRAM.
4405- The default behaviour is to prefer TT. */
4406-#define DRM_BO_FLAG_PREFER_VRAM 0x00040000
4407-/* Bind this buffer cached if the hardware supports it. */
4408-#define DRM_BO_FLAG_BIND_CACHED 0x0002000
4409+/*
4410+ * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
4411+ * Flags: Acknowledge.
4412+ */
4413+#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
4414+#define DRM_BO_FLAG_TILE (1ULL << 15)
4415
4416-/* System Memory */
4417-#define DRM_BO_FLAG_MEM_LOCAL 0x01000000
4418+/*
4419+ * Memory type flags that can be or'ed together in the mask, but only
4420+ * one appears in flags.
4421+ */
4422+
4423+/* System memory */
4424+#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
4425 /* Translation table memory */
4426-#define DRM_BO_FLAG_MEM_TT 0x02000000
4427+#define DRM_BO_FLAG_MEM_TT (1ULL << 25)
4428 /* Vram memory */
4429-#define DRM_BO_FLAG_MEM_VRAM 0x04000000
4430-/* Unmappable Vram memory */
4431-#define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000
4432+#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
4433+/* Up to the driver to define. */
4434+#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
4435+#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
4436+#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
4437+#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
4438+#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
4439+/* We can add more of these now with a 64-bit flag type */
4440+
4441 /* Memory flag mask */
4442-#define DRM_BO_MASK_MEM 0xFF000000
4443+#define DRM_BO_MASK_MEM 0x00000000FF000000ULL
4444+#define DRM_BO_MASK_MEMTYPE 0x00000000FF0800A0ULL
4445+
4446+/* Driver-private flags */
4447+#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
4448
4449-/* When creating a buffer, Avoid system storage even if allowed */
4450-#define DRM_BO_HINT_AVOID_LOCAL 0x00000001
4451 /* Don't block on validate and map */
4452 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
4453 /* Don't place this buffer on the unfenced list.*/
4454 #define DRM_BO_HINT_DONT_FENCE 0x00000004
4455 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
4456-#define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
4457
4458+#define DRM_BO_INIT_MAGIC 0xfe769812
4459+#define DRM_BO_INIT_MAJOR 1
4460+#define DRM_BO_INIT_MINOR 0
4461+#define DRM_BO_INIT_PATCH 0
4462
4463-/* Driver specific flags. Could be for example rendering engine */
4464-#define DRM_BO_MASK_DRIVER 0x00F00000
4465
4466-typedef enum {
4467- drm_bo_type_dc,
4468- drm_bo_type_user,
4469- drm_bo_type_fake
4470-}drm_bo_type_t;
4471-
4472-
4473-typedef struct drm_bo_arg_request {
4474- unsigned handle; /* User space handle */
4475- unsigned mask;
4476- unsigned hint;
4477- drm_u64_t size;
4478- drm_bo_type_t type;
4479- unsigned arg_handle;
4480- drm_u64_t buffer_start;
4481- unsigned page_alignment;
4482- unsigned expand_pad[4]; /*Future expansion */
4483- enum {
4484- drm_bo_create,
4485- drm_bo_validate,
4486- drm_bo_map,
4487- drm_bo_unmap,
4488- drm_bo_fence,
4489- drm_bo_destroy,
4490- drm_bo_reference,
4491- drm_bo_unreference,
4492- drm_bo_info,
4493- drm_bo_wait_idle,
4494- drm_bo_ref_fence
4495- } op;
4496-} drm_bo_arg_request_t;
4497+struct drm_bo_info_req {
4498+ uint64_t mask;
4499+ uint64_t flags;
4500+ unsigned int handle;
4501+ unsigned int hint;
4502+ unsigned int fence_class;
4503+ unsigned int desired_tile_stride;
4504+ unsigned int tile_info;
4505+ unsigned int pad64;
4506+};
4507+
4508+struct drm_bo_create_req {
4509+ uint64_t mask;
4510+ uint64_t size;
4511+ uint64_t buffer_start;
4512+ unsigned int hint;
4513+ unsigned int page_alignment;
4514+};
4515
4516
4517 /*
4518@@ -795,56 +786,238 @@
4519
4520 #define DRM_BO_REP_BUSY 0x00000001
4521
4522-typedef struct drm_bo_arg_reply {
4523+struct drm_bo_info_rep {
4524+ uint64_t flags;
4525+ uint64_t mask;
4526+ uint64_t size;
4527+ uint64_t offset;
4528+ uint64_t arg_handle;
4529+ uint64_t buffer_start;
4530+ unsigned int handle;
4531+ unsigned int fence_flags;
4532+ unsigned int rep_flags;
4533+ unsigned int page_alignment;
4534+ unsigned int desired_tile_stride;
4535+ unsigned int hw_tile_stride;
4536+ unsigned int tile_info;
4537+ unsigned int pad64;
4538+ uint64_t expand_pad[4]; /*Future expansion */
4539+};
4540+
4541+struct drm_bo_arg_rep {
4542+ struct drm_bo_info_rep bo_info;
4543 int ret;
4544- unsigned handle;
4545- unsigned flags;
4546- drm_u64_t size;
4547- drm_u64_t offset;
4548- drm_u64_t arg_handle;
4549- unsigned mask;
4550- drm_u64_t buffer_start;
4551- unsigned fence_flags;
4552- unsigned rep_flags;
4553- unsigned page_alignment;
4554- unsigned expand_pad[4]; /*Future expansion */
4555-}drm_bo_arg_reply_t;
4556-
4557-
4558-typedef struct drm_bo_arg{
4559- int handled;
4560- drm_u64_t next;
4561+ unsigned int pad64;
4562+};
4563+
4564+struct drm_bo_create_arg {
4565 union {
4566- drm_bo_arg_request_t req;
4567- drm_bo_arg_reply_t rep;
4568+ struct drm_bo_create_req req;
4569+ struct drm_bo_info_rep rep;
4570 } d;
4571-} drm_bo_arg_t;
4572+};
4573+
4574+struct drm_bo_handle_arg {
4575+ unsigned int handle;
4576+};
4577+
4578+struct drm_bo_reference_info_arg {
4579+ union {
4580+ struct drm_bo_handle_arg req;
4581+ struct drm_bo_info_rep rep;
4582+ } d;
4583+};
4584+
4585+struct drm_bo_map_wait_idle_arg {
4586+ union {
4587+ struct drm_bo_info_req req;
4588+ struct drm_bo_info_rep rep;
4589+ } d;
4590+};
4591+
4592+struct drm_bo_op_req {
4593+ enum {
4594+ drm_bo_validate,
4595+ drm_bo_fence,
4596+ drm_bo_ref_fence,
4597+ } op;
4598+ unsigned int arg_handle;
4599+ struct drm_bo_info_req bo_req;
4600+};
4601+
4602+
4603+struct drm_bo_op_arg {
4604+ uint64_t next;
4605+ union {
4606+ struct drm_bo_op_req req;
4607+ struct drm_bo_arg_rep rep;
4608+ } d;
4609+ int handled;
4610+ unsigned int pad64;
4611+};
4612+
4613
4614 #define DRM_BO_MEM_LOCAL 0
4615 #define DRM_BO_MEM_TT 1
4616 #define DRM_BO_MEM_VRAM 2
4617-#define DRM_BO_MEM_VRAM_NM 3
4618-#define DRM_BO_MEM_TYPES 2 /* For now. */
4619+#define DRM_BO_MEM_PRIV0 3
4620+#define DRM_BO_MEM_PRIV1 4
4621+#define DRM_BO_MEM_PRIV2 5
4622+#define DRM_BO_MEM_PRIV3 6
4623+#define DRM_BO_MEM_PRIV4 7
4624+
4625+#define DRM_BO_MEM_TYPES 8 /* For now. */
4626+
4627+#define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
4628+#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
4629+
4630+struct drm_bo_version_arg {
4631+ uint32_t major;
4632+ uint32_t minor;
4633+ uint32_t patchlevel;
4634+};
4635
4636-typedef union drm_mm_init_arg{
4637- struct {
4638- enum {
4639- mm_init,
4640- mm_takedown,
4641- mm_query,
4642- mm_lock,
4643- mm_unlock
4644- } op;
4645- drm_u64_t p_offset;
4646- drm_u64_t p_size;
4647- unsigned mem_type;
4648- unsigned expand_pad[8]; /*Future expansion */
4649- } req;
4650- struct {
4651- drm_handle_t mm_sarea;
4652- unsigned expand_pad[8]; /*Future expansion */
4653- } rep;
4654-} drm_mm_init_arg_t;
4655+struct drm_mm_type_arg {
4656+ unsigned int mem_type;
4657+ unsigned int lock_flags;
4658+};
4659+
4660+struct drm_mm_init_arg {
4661+ unsigned int magic;
4662+ unsigned int major;
4663+ unsigned int minor;
4664+ unsigned int mem_type;
4665+ uint64_t p_offset;
4666+ uint64_t p_size;
4667+};
4668+
4669+/*
4670+ * Drm mode setting
4671+ */
4672+#define DRM_DISPLAY_INFO_LEN 32
4673+#define DRM_OUTPUT_NAME_LEN 32
4674+#define DRM_DISPLAY_MODE_LEN 32
4675+#define DRM_PROP_NAME_LEN 32
4676+
4677+#define DRM_MODE_TYPE_BUILTIN (1<<0)
4678+#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
4679+#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
4680+#define DRM_MODE_TYPE_PREFERRED (1<<3)
4681+#define DRM_MODE_TYPE_DEFAULT (1<<4)
4682+#define DRM_MODE_TYPE_USERDEF (1<<5)
4683+#define DRM_MODE_TYPE_DRIVER (1<<6)
4684+
4685+struct drm_mode_modeinfo {
4686+
4687+ unsigned int id;
4688+
4689+ unsigned int clock;
4690+ unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
4691+ unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
4692+
4693+ unsigned int vrefresh; /* vertical refresh * 1000 */
4694+
4695+ unsigned int flags;
4696+ unsigned int type;
4697+ char name[DRM_DISPLAY_MODE_LEN];
4698+};
4699+
4700+struct drm_mode_card_res {
4701+
4702+ int count_fbs;
4703+ unsigned int __user *fb_id;
4704+
4705+ int count_crtcs;
4706+ unsigned int __user *crtc_id;
4707+
4708+ int count_outputs;
4709+ unsigned int __user *output_id;
4710+
4711+ int count_modes;
4712+ struct drm_mode_modeinfo __user *modes;
4713+
4714+};
4715+
4716+struct drm_mode_crtc {
4717+ unsigned int crtc_id; /**< Id */
4718+ unsigned int fb_id; /**< Id of framebuffer */
4719+
4720+ int x, y; /**< Position on the frameuffer */
4721+
4722+ unsigned int mode; /**< Current mode used */
4723+
4724+ int count_outputs;
4725+ unsigned int outputs; /**< Outputs that are connected */
4726+
4727+ int count_possibles;
4728+ unsigned int possibles; /**< Outputs that can be connected */
4729+
4730+ unsigned int __user *set_outputs; /**< Outputs to be connected */
4731+
4732+ int gamma_size;
4733+
4734+};
4735+
4736+struct drm_mode_get_output {
4737+
4738+ unsigned int output; /**< Id */
4739+ unsigned int crtc; /**< Id of crtc */
4740+ unsigned char name[DRM_OUTPUT_NAME_LEN];
4741+
4742+ unsigned int connection;
4743+ unsigned int mm_width, mm_height; /**< HxW in millimeters */
4744+ unsigned int subpixel;
4745+
4746+ int count_crtcs;
4747+ unsigned int crtcs; /**< possible crtc to connect to */
4748+
4749+ int count_clones;
4750+ unsigned int clones; /**< list of clones */
4751+
4752+ int count_modes;
4753+ unsigned int __user *modes; /**< list of modes it supports */
4754+
4755+ int count_props;
4756+ unsigned int __user *props;
4757+ unsigned int __user *prop_values;
4758+};
4759+
4760+#define DRM_MODE_PROP_PENDING (1<<0)
4761+#define DRM_MODE_PROP_RANGE (1<<1)
4762+#define DRM_MODE_PROP_IMMUTABLE (1<<2)
4763+#define DRM_MODE_PROP_ENUM (1<<3) // enumerated type with text strings
4764+
4765+struct drm_mode_property_enum {
4766+ uint32_t value;
4767+ unsigned char name[DRM_PROP_NAME_LEN];
4768+};
4769+
4770+struct drm_mode_get_property {
4771+
4772+ unsigned int prop_id;
4773+ unsigned int flags;
4774+ unsigned char name[DRM_PROP_NAME_LEN];
4775+
4776+ int count_values;
4777+ uint32_t __user *values;
4778+
4779+ int count_enums;
4780+ struct drm_mode_property_enum *enums;
4781+};
4782+
4783+struct drm_mode_fb_cmd {
4784+ unsigned int buffer_id;
4785+ unsigned int width, height;
4786+ unsigned int pitch;
4787+ unsigned int bpp;
4788+ unsigned int handle;
4789+ unsigned int depth;
4790+};
4791+
4792+struct drm_mode_mode_cmd {
4793+ unsigned int output_id;
4794+ unsigned int mode_id;
4795+};
4796
4797 /**
4798 * \name Ioctls Definitions
4799@@ -857,66 +1030,101 @@
4800 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
4801 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
4802
4803-#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
4804-#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
4805-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
4806-#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
4807-#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
4808-#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
4809-#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
4810-#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
4811-
4812-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
4813-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
4814-#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
4815-#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
4816-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
4817-#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
4818-#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
4819-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
4820-#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
4821-#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
4822-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
4823-
4824-#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
4825-
4826-#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
4827-#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
4828-
4829-#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
4830-#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
4831-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
4832-#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
4833-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
4834-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
4835-#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
4836-#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
4837-#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
4838-#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
4839-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
4840-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
4841-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
4842+#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
4843+#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
4844+#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
4845+#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
4846+#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
4847+#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
4848+#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
4849+#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
4850+
4851+#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
4852+#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
4853+#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
4854+#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
4855+#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
4856+#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
4857+#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
4858+#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
4859+#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
4860+#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
4861+#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
4862+
4863+#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
4864+
4865+#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
4866+#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
4867+
4868+#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
4869+#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
4870+#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
4871+#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
4872+#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
4873+#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
4874+#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
4875+#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
4876+#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
4877+#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
4878+#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
4879+#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
4880+#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
4881
4882 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
4883 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
4884-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
4885-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
4886-#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
4887-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
4888-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
4889-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
4890-
4891-#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
4892-#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
4893-
4894-#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
4895-
4896-#define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
4897-#define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
4898-#define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
4899-
4900-#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
4901+#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
4902+#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
4903+#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
4904+#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
4905+#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
4906+#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
4907+
4908+#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
4909+#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
4910+
4911+#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
4912+
4913+#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
4914+
4915+#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
4916+#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
4917+#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
4918+#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
4919+
4920+#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
4921+#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
4922+#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
4923+#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
4924+#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
4925+#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
4926+#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
4927+#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
4928+
4929+#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
4930+#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
4931+#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
4932+#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
4933+#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
4934+#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
4935+#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
4936+#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
4937+#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
4938+
4939+
4940+#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
4941+#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
4942+#define DRM_IOCTL_MODE_GETOUTPUT DRM_IOWR(0xA2, struct drm_mode_get_output)
4943+#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
4944+#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
4945+#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
4946+#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
4947+
4948+#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
4949+#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
4950+#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
4951+#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
4952
4953+#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property)
4954 /*@}*/
4955
4956 /**
4957@@ -930,4 +1138,52 @@
4958 #define DRM_COMMAND_BASE 0x40
4959 #define DRM_COMMAND_END 0xA0
4960
4961+/* typedef area */
4962+#if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)
4963+typedef struct drm_clip_rect drm_clip_rect_t;
4964+typedef struct drm_tex_region drm_tex_region_t;
4965+typedef struct drm_hw_lock drm_hw_lock_t;
4966+typedef struct drm_version drm_version_t;
4967+typedef struct drm_unique drm_unique_t;
4968+typedef struct drm_list drm_list_t;
4969+typedef struct drm_block drm_block_t;
4970+typedef struct drm_control drm_control_t;
4971+typedef enum drm_map_type drm_map_type_t;
4972+typedef enum drm_map_flags drm_map_flags_t;
4973+typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
4974+typedef struct drm_map drm_map_t;
4975+typedef struct drm_client drm_client_t;
4976+typedef enum drm_stat_type drm_stat_type_t;
4977+typedef struct drm_stats drm_stats_t;
4978+typedef enum drm_lock_flags drm_lock_flags_t;
4979+typedef struct drm_lock drm_lock_t;
4980+typedef enum drm_dma_flags drm_dma_flags_t;
4981+typedef struct drm_buf_desc drm_buf_desc_t;
4982+typedef struct drm_buf_info drm_buf_info_t;
4983+typedef struct drm_buf_free drm_buf_free_t;
4984+typedef struct drm_buf_pub drm_buf_pub_t;
4985+typedef struct drm_buf_map drm_buf_map_t;
4986+typedef struct drm_dma drm_dma_t;
4987+typedef union drm_wait_vblank drm_wait_vblank_t;
4988+typedef struct drm_agp_mode drm_agp_mode_t;
4989+typedef enum drm_ctx_flags drm_ctx_flags_t;
4990+typedef struct drm_ctx drm_ctx_t;
4991+typedef struct drm_ctx_res drm_ctx_res_t;
4992+typedef struct drm_draw drm_draw_t;
4993+typedef struct drm_update_draw drm_update_draw_t;
4994+typedef struct drm_auth drm_auth_t;
4995+typedef struct drm_irq_busid drm_irq_busid_t;
4996+typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
4997+typedef struct drm_agp_buffer drm_agp_buffer_t;
4998+typedef struct drm_agp_binding drm_agp_binding_t;
4999+typedef struct drm_agp_info drm_agp_info_t;
5000+typedef struct drm_scatter_gather drm_scatter_gather_t;
5001+typedef struct drm_set_version drm_set_version_t;
5002+
5003+typedef struct drm_fence_arg drm_fence_arg_t;
5004+typedef struct drm_mm_type_arg drm_mm_type_arg_t;
5005+typedef struct drm_mm_init_arg drm_mm_init_arg_t;
5006+typedef enum drm_bo_type drm_bo_type_t;
5007+#endif
5008+
5009 #endif
5010Index: git/shared-core/drm_pciids.txt
5011===================================================================
5012--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5013+++ git/shared-core/drm_pciids.txt 2008-12-12 17:35:22.000000000 +0000
5014@@ -0,0 +1,744 @@
5015+[radeon]
5016+0x1002 0x3150 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X600 M24"
5017+0x1002 0x3152 CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X300 M24"
5018+0x1002 0x3154 CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI FireGL M24 GL"
5019+0x1002 0x3E50 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV380 X600"
5020+0x1002 0x3E54 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireGL V3200 RV380"
5021+0x1002 0x4136 CHIP_RS100|RADEON_IS_IGP "ATI Radeon RS100 IGP 320"
5022+0x1002 0x4137 CHIP_RS200|RADEON_IS_IGP "ATI Radeon RS200 IGP 340"
5023+0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500"
5024+0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
5025+0x1002 0x4146 CHIP_R300 "ATI Radeon AF R300 9600TX"
5026+0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1"
5027+0x1002 0x4148 CHIP_R350 "ATI Radeon AH 9800 SE"
5028+0x1002 0x4149 CHIP_R350 "ATI Radeon AI 9800"
5029+0x1002 0x414A CHIP_R350 "ATI Radeon AJ 9800"
5030+0x1002 0x414B CHIP_R350 "ATI FireGL AK X2"
5031+0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
5032+0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600 SE"
5033+0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600 XT"
5034+0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9550"
5035+0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
5036+0x1002 0x4155 CHIP_RV350 "ATI Radeon 9650"
5037+0x1002 0x4156 CHIP_RV350 "ATI FireGL AV RV360 T2"
5038+0x1002 0x4237 CHIP_RS200|RADEON_IS_IGP "ATI Radeon RS250 IGP"
5039+0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
5040+0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200"
5041+0x1002 0x4336 CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS100 Mobility U1"
5042+0x1002 0x4337 CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M"
5043+0x1002 0x4437 CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS250 Mobility IGP"
5044+0x1002 0x4966 CHIP_RV250 "ATI Radeon If RV250 9000"
5045+0x1002 0x4967 CHIP_RV250 "ATI Radeon Ig RV250 9000"
5046+0x1002 0x4A48 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JH R420 X800"
5047+0x1002 0x4A49 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JI R420 X800 Pro"
5048+0x1002 0x4A4A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JJ R420 X800 SE"
5049+0x1002 0x4A4B CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JK R420 X800 XT"
5050+0x1002 0x4A4C CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JL R420 X800"
5051+0x1002 0x4A4D CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL JM X3-256"
5052+0x1002 0x4A4E CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon JN R420 Mobility M18"
5053+0x1002 0x4A4F CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JO R420 X800 SE"
5054+0x1002 0x4A50 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JP R420 X800 XT PE"
5055+0x1002 0x4A54 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon JT R420 AIW X800 VE"
5056+0x1002 0x4B49 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 XT"
5057+0x1002 0x4B4A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 SE"
5058+0x1002 0x4B4B CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 Pro"
5059+0x1002 0x4B4C CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R481 X850 XT PE"
5060+0x1002 0x4C57 CHIP_RV200|RADEON_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500 M7"
5061+0x1002 0x4C58 CHIP_RV200|RADEON_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL 7800 M7"
5062+0x1002 0x4C59 CHIP_RV100|RADEON_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
5063+0x1002 0x4C5A CHIP_RV100|RADEON_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
5064+0x1002 0x4C64 CHIP_RV250|RADEON_IS_MOBILITY "ATI Radeon Ld RV250 Mobility 9000 M9"
5065+0x1002 0x4C66 CHIP_RV250 "ATI Radeon Lf RV250 Mobility 9000 M9 / FireMV 2400 PCI"
5066+0x1002 0x4C67 CHIP_RV250|RADEON_IS_MOBILITY "ATI Radeon Lg RV250 Mobility 9000 M9"
5067+0x1002 0x4E44 CHIP_R300 "ATI Radeon ND R300 9700 Pro"
5068+0x1002 0x4E45 CHIP_R300 "ATI Radeon NE R300 9500 Pro / 9700"
5069+0x1002 0x4E46 CHIP_R300 "ATI Radeon NF R300 9600TX"
5070+0x1002 0x4E47 CHIP_R300 "ATI Radeon NG R300 FireGL X1"
5071+0x1002 0x4E48 CHIP_R350 "ATI Radeon NH R350 9800 Pro"
5072+0x1002 0x4E49 CHIP_R350 "ATI Radeon NI R350 9800"
5073+0x1002 0x4E4A CHIP_R350 "ATI Radeon NJ R360 9800 XT"
5074+0x1002 0x4E4B CHIP_R350 "ATI FireGL NK X2"
5075+0x1002 0x4E50 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NP"
5076+0x1002 0x4E51 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NQ"
5077+0x1002 0x4E52 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M11 NR"
5078+0x1002 0x4E53 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon RV350 Mobility 9600 M10 NS"
5079+0x1002 0x4E54 CHIP_RV350|RADEON_IS_MOBILITY "ATI FireGL T2/T2e"
5080+0x1002 0x4E56 CHIP_RV350|RADEON_IS_MOBILITY "ATI Radeon Mobility 9550"
5081+0x1002 0x5144 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QD R100"
5082+0x1002 0x5145 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QE R100"
5083+0x1002 0x5146 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QF R100"
5084+0x1002 0x5147 CHIP_R100|RADEON_SINGLE_CRTC "ATI Radeon QG R100"
5085+0x1002 0x5148 CHIP_R200 "ATI Radeon QH R200 8500"
5086+0x1002 0x514C CHIP_R200 "ATI Radeon QL R200 8500 LE"
5087+0x1002 0x514D CHIP_R200 "ATI Radeon QM R200 9100"
5088+0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
5089+0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
5090+0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
5091+0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
5092+0x1002 0x515E CHIP_RV100 "ATI ES1000 RN50"
5093+0x1002 0x5460 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X300 M22"
5094+0x1002 0x5462 CHIP_RV380|RADEON_IS_MOBILITY "ATI Radeon Mobility X600 SE M24C"
5095+0x1002 0x5464 CHIP_RV380|RADEON_IS_MOBILITY "ATI FireGL M22 GL 5464"
5096+0x1002 0x5548 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800"
5097+0x1002 0x5549 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 Pro"
5098+0x1002 0x554A CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 XT PE"
5099+0x1002 0x554B CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 SE"
5100+0x1002 0x554C CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 XTP"
5101+0x1002 0x554D CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 XL"
5102+0x1002 0x554E CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R430 X800 SE"
5103+0x1002 0x554F CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R430 X800"
5104+0x1002 0x5550 CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL V7100 R423"
5105+0x1002 0x5551 CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL V5100 R423 UQ"
5106+0x1002 0x5552 CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL unknown R423 UR"
5107+0x1002 0x5554 CHIP_R420|RADEON_NEW_MEMMAP "ATI FireGL unknown R423 UT"
5108+0x1002 0x564A CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5000 M26"
5109+0x1002 0x564B CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5000 M26"
5110+0x1002 0x564F CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 XL M26"
5111+0x1002 0x5652 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26"
5112+0x1002 0x5653 CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon Mobility X700 M26"
5113+0x1002 0x5834 CHIP_RS300|RADEON_IS_IGP "ATI Radeon RS300 9100 IGP"
5114+0x1002 0x5835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY "ATI Radeon RS300 Mobility IGP"
5115+0x1002 0x5954 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI RS480 XPRESS 200G"
5116+0x1002 0x5955 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon XPRESS 200M 5955"
5117+0x1002 0x5974 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS482 XPRESS 200"
5118+0x1002 0x5975 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS485 XPRESS 1100 IGP"
5119+0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9250"
5120+0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200"
5121+0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
5122+0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
5123+0x1002 0x5965 CHIP_RV280 "ATI FireMV 2200 PCI"
5124+0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50"
5125+0x1002 0x5a41 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200"
5126+0x1002 0x5a42 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RS400 XPRESS 200M"
5127+0x1002 0x5a61 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200"
5128+0x1002 0x5a62 CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART "ATI Radeon RC410 XPRESS 200M"
5129+0x1002 0x5b60 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X300 SE"
5130+0x1002 0x5b62 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X600 Pro"
5131+0x1002 0x5b63 CHIP_RV380|RADEON_NEW_MEMMAP "ATI Radeon RV370 X550"
5132+0x1002 0x5b64 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireGL V3100 (RV370) 5B64"
5133+0x1002 0x5b65 CHIP_RV380|RADEON_NEW_MEMMAP "ATI FireMV 2200 PCIE (RV370) 5B65"
5134+0x1002 0x5c61 CHIP_RV280|RADEON_IS_MOBILITY "ATI Radeon RV280 Mobility"
5135+0x1002 0x5c63 CHIP_RV280|RADEON_IS_MOBILITY "ATI Radeon RV280 Mobility"
5136+0x1002 0x5d48 CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X800 XT M28"
5137+0x1002 0x5d49 CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility FireGL V5100 M28"
5138+0x1002 0x5d4a CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon X800 M28"
5139+0x1002 0x5d4c CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R480 X850"
5140+0x1002 0x5d4d CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 XT PE"
5141+0x1002 0x5d4e CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 SE"
5142+0x1002 0x5d4f CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 Pro"
5143+0x1002 0x5d50 CHIP_R420|RADEON_NEW_MEMMAP "ATI unknown Radeon / FireGL R480"
5144+0x1002 0x5d52 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R480 X850 XT"
5145+0x1002 0x5d57 CHIP_R420|RADEON_NEW_MEMMAP "ATI Radeon R423 X800 XT"
5146+0x1002 0x5e48 CHIP_RV410|RADEON_NEW_MEMMAP "ATI FireGL V5000 RV410"
5147+0x1002 0x5e4a CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 XT"
5148+0x1002 0x5e4b CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 Pro"
5149+0x1002 0x5e4c CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE"
5150+0x1002 0x5e4d CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700"
5151+0x1002 0x5e4f CHIP_RV410|RADEON_NEW_MEMMAP "ATI Radeon RV410 X700 SE"
5152+0x1002 0x7834 CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP "ATI Radeon RS350 9000/9100 IGP"
5153+0x1002 0x7835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon RS350 Mobility IGP"
5154+
5155+[r128]
5156+0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
5157+0x1002 0x4c46 0 "ATI Rage 128 Mobility LF (AGP)"
5158+0x1002 0x4d46 0 "ATI Rage 128 Mobility MF (AGP)"
5159+0x1002 0x4d4c 0 "ATI Rage 128 Mobility ML (AGP)"
5160+0x1002 0x5041 0 "ATI Rage 128 Pro PA (PCI)"
5161+0x1002 0x5042 0 "ATI Rage 128 Pro PB (AGP)"
5162+0x1002 0x5043 0 "ATI Rage 128 Pro PC (AGP)"
5163+0x1002 0x5044 0 "ATI Rage 128 Pro PD (PCI)"
5164+0x1002 0x5045 0 "ATI Rage 128 Pro PE (AGP)"
5165+0x1002 0x5046 0 "ATI Rage 128 Pro PF (AGP)"
5166+0x1002 0x5047 0 "ATI Rage 128 Pro PG (PCI)"
5167+0x1002 0x5048 0 "ATI Rage 128 Pro PH (AGP)"
5168+0x1002 0x5049 0 "ATI Rage 128 Pro PI (AGP)"
5169+0x1002 0x504A 0 "ATI Rage 128 Pro PJ (PCI)"
5170+0x1002 0x504B 0 "ATI Rage 128 Pro PK (AGP)"
5171+0x1002 0x504C 0 "ATI Rage 128 Pro PL (AGP)"
5172+0x1002 0x504D 0 "ATI Rage 128 Pro PM (PCI)"
5173+0x1002 0x504E 0 "ATI Rage 128 Pro PN (AGP)"
5174+0x1002 0x504F 0 "ATI Rage 128 Pro PO (AGP)"
5175+0x1002 0x5050 0 "ATI Rage 128 Pro PP (PCI)"
5176+0x1002 0x5051 0 "ATI Rage 128 Pro PQ (AGP)"
5177+0x1002 0x5052 0 "ATI Rage 128 Pro PR (PCI)"
5178+0x1002 0x5053 0 "ATI Rage 128 Pro PS (PCI)"
5179+0x1002 0x5054 0 "ATI Rage 128 Pro PT (AGP)"
5180+0x1002 0x5055 0 "ATI Rage 128 Pro PU (AGP)"
5181+0x1002 0x5056 0 "ATI Rage 128 Pro PV (PCI)"
5182+0x1002 0x5057 0 "ATI Rage 128 Pro PW (AGP)"
5183+0x1002 0x5058 0 "ATI Rage 128 Pro PX (AGP)"
5184+0x1002 0x5245 0 "ATI Rage 128 RE (PCI)"
5185+0x1002 0x5246 0 "ATI Rage 128 RF (AGP)"
5186+0x1002 0x5247 0 "ATI Rage 128 RG (AGP)"
5187+0x1002 0x524b 0 "ATI Rage 128 RK (PCI)"
5188+0x1002 0x524c 0 "ATI Rage 128 RL (AGP)"
5189+0x1002 0x534d 0 "ATI Rage 128 SM (AGP)"
5190+0x1002 0x5446 0 "ATI Rage 128 Pro Ultra TF (AGP)"
5191+0x1002 0x544C 0 "ATI Rage 128 Pro Ultra TL (AGP)"
5192+0x1002 0x5452 0 "ATI Rage 128 Pro Ultra TR (AGP)"
5193+
5194+[mga]
5195+0x102b 0x0520 MGA_CARD_TYPE_G200 "Matrox G200 (PCI)"
5196+0x102b 0x0521 MGA_CARD_TYPE_G200 "Matrox G200 (AGP)"
5197+0x102b 0x0525 MGA_CARD_TYPE_G400 "Matrox G400/G450 (AGP)"
5198+0x102b 0x2527 MGA_CARD_TYPE_G550 "Matrox G550 (AGP)"
5199+
5200+[mach64]
5201+0x1002 0x4749 0 "3D Rage Pro"
5202+0x1002 0x4750 0 "3D Rage Pro 215GP"
5203+0x1002 0x4751 0 "3D Rage Pro 215GQ"
5204+0x1002 0x4742 0 "3D Rage Pro AGP 1X/2X"
5205+0x1002 0x4744 0 "3D Rage Pro AGP 1X"
5206+0x1002 0x4c49 0 "3D Rage LT Pro"
5207+0x1002 0x4c50 0 "3D Rage LT Pro"
5208+0x1002 0x4c51 0 "3D Rage LT Pro"
5209+0x1002 0x4c42 0 "3D Rage LT Pro AGP-133"
5210+0x1002 0x4c44 0 "3D Rage LT Pro AGP-66"
5211+0x1002 0x474c 0 "Rage XC"
5212+0x1002 0x474f 0 "Rage XL"
5213+0x1002 0x4752 0 "Rage XL"
5214+0x1002 0x4753 0 "Rage XC"
5215+0x1002 0x474d 0 "Rage XL AGP 2X"
5216+0x1002 0x474e 0 "Rage XC AGP"
5217+0x1002 0x4c52 0 "Rage Mobility P/M"
5218+0x1002 0x4c53 0 "Rage Mobility L"
5219+0x1002 0x4c4d 0 "Rage Mobility P/M AGP 2X"
5220+0x1002 0x4c4e 0 "Rage Mobility L AGP 2X"
5221+
5222+[sis]
5223+0x1039 0x0300 0 "SiS 300/305"
5224+0x1039 0x5300 0 "SiS 540"
5225+0x1039 0x6300 0 "SiS 630"
5226+0x1039 0x6330 SIS_CHIP_315 "SiS 661"
5227+0x1039 0x7300 0 "SiS 730"
5228+0x18CA 0x0040 SIS_CHIP_315 "Volari V3XT/V5/V8"
5229+0x18CA 0x0042 SIS_CHIP_315 "Volari Unknown"
5230+
5231+[tdfx]
5232+0x121a 0x0003 0 "3dfx Voodoo Banshee"
5233+0x121a 0x0004 0 "3dfx Voodoo3 2000"
5234+0x121a 0x0005 0 "3dfx Voodoo3 3000"
5235+0x121a 0x0007 0 "3dfx Voodoo4 4500"
5236+0x121a 0x0009 0 "3dfx Voodoo5 5500"
5237+0x121a 0x000b 0 "3dfx Voodoo4 4200"
5238+
5239+[viadrv]
5240+0x1106 0x3022 0 "VIA CLE266 3022"
5241+0x1106 0x3118 VIA_PRO_GROUP_A "VIA CN400 / PM8X0"
5242+0x1106 0x3122 0 "VIA CLE266"
5243+0x1106 0x7205 0 "VIA KM400"
5244+0x1106 0x3108 0 "VIA K8M800"
5245+0x1106 0x3344 0 "VIA CN700 / VM800 / P4M800Pro"
5246+0x1106 0x3343 0 "VIA P4M890"
5247+0x1106 0x3230 VIA_DX9_0 "VIA K8M890"
5248+0x1106 0x3157 VIA_PRO_GROUP_A "VIA CX700"
5249+
5250+[i810]
5251+0x8086 0x7121 0 "Intel i810 GMCH"
5252+0x8086 0x7123 0 "Intel i810-DC100 GMCH"
5253+0x8086 0x7125 0 "Intel i810E GMCH"
5254+0x8086 0x1132 0 "Intel i815 GMCH"
5255+
5256+[i830]
5257+0x8086 0x3577 0 "Intel i830M GMCH"
5258+0x8086 0x2562 0 "Intel i845G GMCH"
5259+0x8086 0x3582 0 "Intel i852GM/i855GM GMCH"
5260+0x8086 0x2572 0 "Intel i865G GMCH"
5261+
5262+[gamma]
5263+0x3d3d 0x0008 0 "3DLabs GLINT Gamma G1"
5264+
5265+[savage]
5266+0x5333 0x8a20 S3_SAVAGE3D "Savage 3D"
5267+0x5333 0x8a21 S3_SAVAGE3D "Savage 3D/MV"
5268+0x5333 0x8a22 S3_SAVAGE4 "Savage4"
5269+0x5333 0x8a23 S3_SAVAGE4 "Savage4"
5270+0x5333 0x8c10 S3_SAVAGE_MX "Savage/MX-MV"
5271+0x5333 0x8c11 S3_SAVAGE_MX "Savage/MX"
5272+0x5333 0x8c12 S3_SAVAGE_MX "Savage/IX-MV"
5273+0x5333 0x8c13 S3_SAVAGE_MX "Savage/IX"
5274+0x5333 0x8c22 S3_SUPERSAVAGE "SuperSavage MX/128"
5275+0x5333 0x8c24 S3_SUPERSAVAGE "SuperSavage MX/64"
5276+0x5333 0x8c26 S3_SUPERSAVAGE "SuperSavage MX/64C"
5277+0x5333 0x8c2a S3_SUPERSAVAGE "SuperSavage IX/128 SDR"
5278+0x5333 0x8c2b S3_SUPERSAVAGE "SuperSavage IX/128 DDR"
5279+0x5333 0x8c2c S3_SUPERSAVAGE "SuperSavage IX/64 SDR"
5280+0x5333 0x8c2d S3_SUPERSAVAGE "SuperSavage IX/64 DDR"
5281+0x5333 0x8c2e S3_SUPERSAVAGE "SuperSavage IX/C SDR"
5282+0x5333 0x8c2f S3_SUPERSAVAGE "SuperSavage IX/C DDR"
5283+0x5333 0x8a25 S3_PROSAVAGE "ProSavage PM133"
5284+0x5333 0x8a26 S3_PROSAVAGE "ProSavage KM133"
5285+0x5333 0x8d01 S3_TWISTER "ProSavage Twister PN133"
5286+0x5333 0x8d02 S3_TWISTER "ProSavage Twister KN133"
5287+0x5333 0x8d03 S3_PROSAVAGEDDR "ProSavage DDR"
5288+0x5333 0x8d04 S3_PROSAVAGEDDR "ProSavage DDR-K"
5289+
5290+[ffb]
5291+
5292+[i915]
5293+0x8086 0x3577 CHIP_I8XX "Intel i830M GMCH"
5294+0x8086 0x2562 CHIP_I8XX "Intel i845G GMCH"
5295+0x8086 0x3582 CHIP_I8XX "Intel i852GM/i855GM GMCH"
5296+0x8086 0x2572 CHIP_I8XX "Intel i865G GMCH"
5297+0x8086 0x2582 CHIP_I9XX|CHIP_I915 "Intel i915G"
5298+0x8086 0x2592 CHIP_I9XX|CHIP_I915 "Intel i915GM"
5299+0x8086 0x2772 CHIP_I9XX|CHIP_I915 "Intel i945G"
5300+0x8086 0x27A2 CHIP_I9XX|CHIP_I915 "Intel i945GM"
5301+0x8086 0x27AE CHIP_I9XX|CHIP_I915 "Intel i945GME"
5302+0x8086 0x2972 CHIP_I9XX|CHIP_I965 "Intel i946GZ"
5303+0x8086 0x2982 CHIP_I9XX|CHIP_I965 "Intel i965G"
5304+0x8086 0x2992 CHIP_I9XX|CHIP_I965 "Intel i965Q"
5305+0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G"
5306+0x8086 0x2A02 CHIP_I9XX|CHIP_I965 "Intel i965GM"
5307+0x8086 0x2A12 CHIP_I9XX|CHIP_I965 "Intel i965GME/GLE"
5308+0x8086 0x29C2 CHIP_I9XX|CHIP_I915 "Intel G33"
5309+0x8086 0x29B2 CHIP_I9XX|CHIP_I915 "Intel Q35"
5310+0x8086 0x29D2 CHIP_I9XX|CHIP_I915 "Intel Q33"
5311+
5312+[psb]
5313+0x8086 0x8108 CHIP_PSB_8108 "Intel Poulsbo"
5314+
5315+[imagine]
5316+0x105d 0x2309 IMAGINE_128 "Imagine 128"
5317+0x105d 0x2339 IMAGINE_128_2 "Imagine 128-II"
5318+0x105d 0x493d IMAGINE_T2R "Ticket to Ride"
5319+0x105d 0x5348 IMAGINE_REV4 "Revolution IV"
5320+
5321+[nv]
5322+0x10DE 0x0020 NV04 "NVidia RIVA TNT"
5323+0x10DE 0x0028 NV04 "NVidia RIVA TNT2"
5324+0x10DE 0x002A NV04 "NVidia Unknown TNT2"
5325+0x10DE 0x002C NV04 "NVidia Vanta"
5326+0x10DE 0x0029 NV04 "NVidia RIVA TNT2 Ultra"
5327+0x10DE 0x002D NV04 "NVidia RIVA TNT2 Model 64"
5328+0x10DE 0x00A0 NV04 "NVidia Aladdin TNT2"
5329+0x10DE 0x0100 NV10 "NVidia GeForce 256"
5330+0x10DE 0x0101 NV10 "NVidia GeForce DDR"
5331+0x10DE 0x0103 NV10 "NVidia Quadro"
5332+0x10DE 0x0110 NV10 "NVidia GeForce2 MX/MX 400"
5333+0x10DE 0x0111 NV10 "NVidia GeForce2 MX 100/200"
5334+0x10DE 0x0112 NV10 "NVidia GeForce2 Go"
5335+0x10DE 0x0113 NV10 "NVidia Quadro2 MXR/EX/Go"
5336+0x10DE 0x0150 NV10 "NVidia GeForce2 GTS"
5337+0x10DE 0x0151 NV10 "NVidia GeForce2 Ti"
5338+0x10DE 0x0152 NV10 "NVidia GeForce2 Ultra"
5339+0x10DE 0x0153 NV10 "NVidia Quadro2 Pro"
5340+0x10DE 0x0170 NV10 "NVidia GeForce4 MX 460"
5341+0x10DE 0x0171 NV10 "NVidia GeForce4 MX 440"
5342+0x10DE 0x0172 NV10 "NVidia GeForce4 MX 420"
5343+0x10DE 0x0173 NV10 "NVidia GeForce4 MX 440-SE"
5344+0x10DE 0x0174 NV10 "NVidia GeForce4 440 Go"
5345+0x10DE 0x0175 NV10 "NVidia GeForce4 420 Go"
5346+0x10DE 0x0176 NV10 "NVidia GeForce4 420 Go 32M"
5347+0x10DE 0x0177 NV10 "NVidia GeForce4 460 Go"
5348+0x10DE 0x0178 NV10 "NVidia Quadro4 550 XGL"
5349+0x10DE 0x0179 NV10 "NVidia GeForce4"
5350+0x10DE 0x017A NV10 "NVidia Quadro4 NVS"
5351+0x10DE 0x017C NV10 "NVidia Quadro4 500 GoGL"
5352+0x10DE 0x017D NV10 "NVidia GeForce4 410 Go 16M"
5353+0x10DE 0x0181 NV10 "NVidia GeForce4 MX 440 with AGP8X"
5354+0x10DE 0x0182 NV10 "NVidia GeForce4 MX 440SE with AGP8X"
5355+0x10DE 0x0183 NV10 "NVidia GeForce4 MX 420 with AGP8X"
5356+0x10DE 0x0185 NV10 "NVidia GeForce4 MX 4000"
5357+0x10DE 0x0186 NV10 "NVidia GeForce4 448 Go"
5358+0x10DE 0x0187 NV10 "NVidia GeForce4 488 Go"
5359+0x10DE 0x0188 NV10 "NVidia Quadro4 580 XGL"
5360+0x10DE 0x0189 NV10 "NVidia GeForce4 MX with AGP8X (Mac)"
5361+0x10DE 0x018A NV10 "NVidia Quadro4 280 NVS"
5362+0x10DE 0x018B NV10 "NVidia Quadro4 380 XGL"
5363+0x10DE 0x018C NV10 "NVidia Quadro NVS 50 PCI"
5364+0x10DE 0x018D NV10 "NVidia GeForce4 448 Go"
5365+0x10DE 0x01A0 NV10 "NVidia GeForce2 Integrated GPU"
5366+0x10DE 0x01F0 NV10 "NVidia GeForce4 MX Integrated GPU"
5367+0x10DE 0x0200 NV20 "NVidia GeForce3"
5368+0x10DE 0x0201 NV20 "NVidia GeForce3 Ti 200"
5369+0x10DE 0x0202 NV20 "NVidia GeForce3 Ti 500"
5370+0x10DE 0x0203 NV20 "NVidia Quadro DCC"
5371+0x10DE 0x0250 NV20 "NVidia GeForce4 Ti 4600"
5372+0x10DE 0x0251 NV20 "NVidia GeForce4 Ti 4400"
5373+0x10DE 0x0252 NV20 "NVidia 0x0252"
5374+0x10DE 0x0253 NV20 "NVidia GeForce4 Ti 4200"
5375+0x10DE 0x0258 NV20 "NVidia Quadro4 900 XGL"
5376+0x10DE 0x0259 NV20 "NVidia Quadro4 750 XGL"
5377+0x10DE 0x025B NV20 "NVidia Quadro4 700 XGL"
5378+0x10DE 0x0280 NV20 "NVidia GeForce4 Ti 4800"
5379+0x10DE 0x0281 NV20 "NVidia GeForce4 Ti 4200 with AGP8X"
5380+0x10DE 0x0282 NV20 "NVidia GeForce4 Ti 4800 SE"
5381+0x10DE 0x0286 NV20 "NVidia GeForce4 4200 Go"
5382+0x10DE 0x028C NV20 "NVidia Quadro4 700 GoGL"
5383+0x10DE 0x0288 NV20 "NVidia Quadro4 980 XGL"
5384+0x10DE 0x0289 NV20 "NVidia Quadro4 780 XGL"
5385+0x10DE 0x0301 NV30 "NVidia GeForce FX 5800 Ultra"
5386+0x10DE 0x0302 NV30 "NVidia GeForce FX 5800"
5387+0x10DE 0x0308 NV30 "NVidia Quadro FX 2000"
5388+0x10DE 0x0309 NV30 "NVidia Quadro FX 1000"
5389+0x10DE 0x0311 NV30 "NVidia GeForce FX 5600 Ultra"
5390+0x10DE 0x0312 NV30 "NVidia GeForce FX 5600"
5391+0x10DE 0x0313 NV30 "NVidia 0x0313"
5392+0x10DE 0x0314 NV30 "NVidia GeForce FX 5600SE"
5393+0x10DE 0x0316 NV30 "NVidia 0x0316"
5394+0x10DE 0x0317 NV30 "NVidia 0x0317"
5395+0x10DE 0x031A NV30 "NVidia GeForce FX Go5600"
5396+0x10DE 0x031B NV30 "NVidia GeForce FX Go5650"
5397+0x10DE 0x031C NV30 "NVidia Quadro FX Go700"
5398+0x10DE 0x031D NV30 "NVidia 0x031D"
5399+0x10DE 0x031E NV30 "NVidia 0x031E"
5400+0x10DE 0x031F NV30 "NVidia 0x031F"
5401+0x10DE 0x0320 NV30 "NVidia GeForce FX 5200"
5402+0x10DE 0x0321 NV30 "NVidia GeForce FX 5200 Ultra"
5403+0x10DE 0x0322 NV30 "NVidia GeForce FX 5200"
5404+0x10DE 0x0323 NV30 "NVidia GeForce FX 5200SE"
5405+0x10DE 0x0324 NV30 "NVidia GeForce FX Go5200"
5406+0x10DE 0x0325 NV30 "NVidia GeForce FX Go5250"
5407+0x10DE 0x0326 NV30 "NVidia GeForce FX 5500"
5408+0x10DE 0x0327 NV30 "NVidia GeForce FX 5100"
5409+0x10DE 0x0328 NV30 "NVidia GeForce FX Go5200 32M/64M"
5410+0x10DE 0x0329 NV30 "NVidia GeForce FX 5200 (Mac)"
5411+0x10DE 0x032A NV30 "NVidia Quadro NVS 280 PCI"
5412+0x10DE 0x032B NV30 "NVidia Quadro FX 500/600 PCI"
5413+0x10DE 0x032C NV30 "NVidia GeForce FX Go53xx Series"
5414+0x10DE 0x032D NV30 "NVidia GeForce FX Go5100"
5415+0x10DE 0x032F NV30 "NVidia 0x032F"
5416+0x10DE 0x0330 NV30 "NVidia GeForce FX 5900 Ultra"
5417+0x10DE 0x0331 NV30 "NVidia GeForce FX 5900"
5418+0x10DE 0x0332 NV30 "NVidia GeForce FX 5900XT"
5419+0x10DE 0x0333 NV30 "NVidia GeForce FX 5950 Ultra"
5420+0x10DE 0x033F NV30 "NVidia Quadro FX 700"
5421+0x10DE 0x0334 NV30 "NVidia GeForce FX 5900ZT"
5422+0x10DE 0x0338 NV30 "NVidia Quadro FX 3000"
5423+0x10DE 0x0341 NV30 "NVidia GeForce FX 5700 Ultra"
5424+0x10DE 0x0342 NV30 "NVidia GeForce FX 5700"
5425+0x10DE 0x0343 NV30 "NVidia GeForce FX 5700LE"
5426+0x10DE 0x0344 NV30 "NVidia GeForce FX 5700VE"
5427+0x10DE 0x0345 NV30 "NVidia 0x0345"
5428+0x10DE 0x0347 NV30 "NVidia GeForce FX Go5700"
5429+0x10DE 0x0348 NV30 "NVidia GeForce FX Go5700"
5430+0x10DE 0x0349 NV30 "NVidia 0x0349"
5431+0x10DE 0x034B NV30 "NVidia 0x034B"
5432+0x10DE 0x034C NV30 "NVidia Quadro FX Go1000"
5433+0x10DE 0x034E NV30 "NVidia Quadro FX 1100"
5434+0x10DE 0x034F NV30 "NVidia 0x034F"
5435+0x10DE 0x0040 NV40 "NVidia GeForce 6800 Ultra"
5436+0x10DE 0x0041 NV40 "NVidia GeForce 6800"
5437+0x10DE 0x0042 NV40 "NVidia GeForce 6800 LE"
5438+0x10DE 0x0043 NV40 "NVidia 0x0043"
5439+0x10DE 0x0045 NV40 "NVidia GeForce 6800 GT"
5440+0x10DE 0x0046 NV40 "NVidia GeForce 6800 GT"
5441+0x10DE 0x0049 NV40 "NVidia 0x0049"
5442+0x10DE 0x004E NV40 "NVidia Quadro FX 4000"
5443+0x10DE 0x00C0 NV40 "NVidia 0x00C0"
5444+0x10DE 0x00C1 NV40 "NVidia GeForce 6800"
5445+0x10DE 0x00C2 NV40 "NVidia GeForce 6800 LE"
5446+0x10DE 0x00C8 NV40 "NVidia GeForce Go 6800"
5447+0x10DE 0x00C9 NV40 "NVidia GeForce Go 6800 Ultra"
5448+0x10DE 0x00CC NV40 "NVidia Quadro FX Go1400"
5449+0x10DE 0x00CD NV40 "NVidia Quadro FX 3450/4000 SDI"
5450+0x10DE 0x00CE NV40 "NVidia Quadro FX 1400"
5451+0x10de 0x00f0 NV40 "Nvidia GeForce 6600 GT"
5452+0x10de 0x00f1 NV40 "Nvidia GeForce 6600 GT"
5453+0x10DE 0x0140 NV40 "NVidia GeForce 6600 GT"
5454+0x10DE 0x0141 NV40 "NVidia GeForce 6600"
5455+0x10DE 0x0142 NV40 "NVidia GeForce 6600 LE"
5456+0x10DE 0x0143 NV40 "NVidia 0x0143"
5457+0x10DE 0x0144 NV40 "NVidia GeForce Go 6600"
5458+0x10DE 0x0145 NV40 "NVidia GeForce 6610 XL"
5459+0x10DE 0x0146 NV40 "NVidia GeForce Go 6600 TE/6200 TE"
5460+0x10DE 0x0147 NV40 "NVidia GeForce 6700 XL"
5461+0x10DE 0x0148 NV40 "NVidia GeForce Go 6600"
5462+0x10DE 0x0149 NV40 "NVidia GeForce Go 6600 GT"
5463+0x10DE 0x014B NV40 "NVidia 0x014B"
5464+0x10DE 0x014C NV40 "NVidia 0x014C"
5465+0x10DE 0x014D NV40 "NVidia 0x014D"
5466+0x10DE 0x014E NV40 "NVidia Quadro FX 540"
5467+0x10DE 0x014F NV40 "NVidia GeForce 6200"
5468+0x10DE 0x0160 NV40 "NVidia 0x0160"
5469+0x10DE 0x0161 NV40 "NVidia GeForce 6200 TurboCache(TM)"
5470+0x10DE 0x0162 NV40 "NVidia GeForce 6200SE TurboCache(TM)"
5471+0x10DE 0x0163 NV40 "NVidia 0x0163"
5472+0x10DE 0x0164 NV40 "NVidia GeForce Go 6200"
5473+0x10DE 0x0165 NV40 "NVidia Quadro NVS 285"
5474+0x10DE 0x0166 NV40 "NVidia GeForce Go 6400"
5475+0x10DE 0x0167 NV40 "NVidia GeForce Go 6200"
5476+0x10DE 0x0168 NV40 "NVidia GeForce Go 6400"
5477+0x10DE 0x0169 NV40 "NVidia 0x0169"
5478+0x10DE 0x016B NV40 "NVidia 0x016B"
5479+0x10DE 0x016C NV40 "NVidia 0x016C"
5480+0x10DE 0x016D NV40 "NVidia 0x016D"
5481+0x10DE 0x016E NV40 "NVidia 0x016E"
5482+0x10DE 0x0210 NV40 "NVidia 0x0210"
5483+0x10DE 0x0211 NV40 "NVidia GeForce 6800"
5484+0x10DE 0x0212 NV40 "NVidia GeForce 6800 LE"
5485+0x10DE 0x0215 NV40 "NVidia GeForce 6800 GT"
5486+0x10DE 0x0220 NV40 "NVidia 0x0220"
5487+0x10DE 0x0221 NV40 "NVidia GeForce 6200"
5488+0x10DE 0x0222 NV40 "NVidia 0x0222"
5489+0x10DE 0x0228 NV40 "NVidia 0x0228"
5490+0x10DE 0x0090 NV40 "NVidia 0x0090"
5491+0x10DE 0x0091 NV40 "NVidia GeForce 7800 GTX"
5492+0x10DE 0x0092 NV40 "NVidia 0x0092"
5493+0x10DE 0x0093 NV40 "NVidia 0x0093"
5494+0x10DE 0x0094 NV40 "NVidia 0x0094"
5495+0x10DE 0x0098 NV40 "NVidia 0x0098"
5496+0x10DE 0x0099 NV40 "NVidia GeForce Go 7800 GTX"
5497+0x10DE 0x009C NV40 "NVidia 0x009C"
5498+0x10DE 0x009D NV40 "NVidia Quadro FX 4500"
5499+0x10DE 0x009E NV40 "NVidia 0x009E"
5500+
5501+[nouveau]
5502+0x10de 0x0020 NV_04 "RIVA TNT"
5503+0x10de 0x0028 NV_04 "RIVA TNT2/TNT2 Pro"
5504+0x10de 0x0029 NV_04 "RIVA TNT2 Ultra"
5505+0x10de 0x002a NV_04 "Riva TnT2"
5506+0x10de 0x002b NV_04 "Riva TnT2"
5507+0x10de 0x002c NV_04 "Vanta/Vanta LT"
5508+0x10de 0x002d NV_04 "RIVA TNT2 Model 64/Model 64 Pro"
5509+0x10de 0x002e NV_04 "Vanta"
5510+0x10de 0x002f NV_04 "Vanta"
5511+0x10de 0x0040 NV_40 "GeForce 6800 Ultra"
5512+0x10de 0x0041 NV_40 "GeForce 6800"
5513+0x10de 0x0042 NV_40 "GeForce 6800 LE"
5514+0x10de 0x0043 NV_40 "NV40.3"
5515+0x10de 0x0044 NV_40 "GeForce 6800 XT"
5516+0x10de 0x0045 NV_40 "GeForce 6800 GT"
5517+0x10de 0x0046 NV_40 "GeForce 6800 GT"
5518+0x10de 0x0047 NV_40 "GeForce 6800 GS"
5519+0x10de 0x0048 NV_40 "GeForce 6800 XT"
5520+0x10de 0x0049 NV_40 "NV40GL"
5521+0x10de 0x004d NV_40 "Quadro FX 4000"
5522+0x10de 0x004e NV_40 "Quadro FX 4000"
5523+0x10de 0x0090 NV_40 "GeForce 7800 GTX"
5524+0x10de 0x0091 NV_40 "GeForce 7800 GTX"
5525+0x10de 0x0092 NV_40 "GeForce 7800 GT"
5526+0x10de 0x0093 NV_40 "GeForce 7800 GS"
5527+0x10de 0x0095 NV_40 "GeForce 7800 SLI"
5528+0x10de 0x0098 NV_40 "GeForce Go 7800"
5529+0x10de 0x0099 NV_40 "GeForce Go 7800 GTX"
5530+0x10de 0x009d NV_40 "Quadro FX4500"
5531+0x10de 0x00a0 NV_04 "Aladdin TNT2"
5532+0x10de 0x00c0 NV_40 "GeForce 6800 GS"
5533+0x10de 0x00c1 NV_40 "GeForce 6800"
5534+0x10de 0x00c2 NV_40 "GeForce 6800 LE"
5535+0x10de 0x00c3 NV_40 "Geforce 6800 XT"
5536+0x10de 0x00c8 NV_40 "GeForce Go 6800"
5537+0x10de 0x00c9 NV_40 "GeForce Go 6800 Ultra"
5538+0x10de 0x00cc NV_40 "Quadro FX Go1400"
5539+0x10de 0x00cd NV_40 "Quadro FX 3450/4000 SDI"
5540+0x10de 0x00ce NV_40 "Quadro FX 1400"
5541+0x10de 0x00f0 NV_40 "GeForce 6800/GeForce 6800 Ultra"
5542+0x10de 0x00f1 NV_40 "GeForce 6600/GeForce 6600 GT"
5543+0x10de 0x00f2 NV_40 "GeForce 6600/GeForce 6600 GT"
5544+0x10de 0x00f3 NV_40 "GeForce 6200"
5545+0x10de 0x00f4 NV_40 "GeForce 6600 LE"
5546+0x10de 0x00f5 NV_40 "GeForce 7800 GS"
5547+0x10de 0x00f6 NV_40 "GeForce 6600 GS"
5548+0x10de 0x00f8 NV_40 "Quadro FX 3400/4400"
5549+0x10de 0x00f9 NV_40 "GeForce 6800 Ultra/GeForce 6800 GT"
5550+0x10de 0x00fa NV_30 "GeForce PCX 5750"
5551+0x10de 0x00fb NV_30 "GeForce PCX 5900"
5552+0x10de 0x00fc NV_30 "Quadro FX 330/GeForce PCX 5300"
5553+0x10de 0x00fd NV_30 "Quadro FX 330/Quadro NVS280"
5554+0x10de 0x00fe NV_30 "Quadro FX 1300"
5555+0x10de 0x00ff NV_17 "GeForce PCX 4300"
5556+0x10de 0x0100 NV_10 "GeForce 256 SDR"
5557+0x10de 0x0101 NV_10 "GeForce 256 DDR"
5558+0x10de 0x0103 NV_10 "Quadro"
5559+0x10de 0x0110 NV_11 "GeForce2 MX/MX 400"
5560+0x10de 0x0111 NV_11 "GeForce2 MX 100 DDR/200 DDR"
5561+0x10de 0x0112 NV_11 "GeForce2 Go"
5562+0x10de 0x0113 NV_11 "Quadro2 MXR/EX/Go"
5563+0x10de 0x0140 NV_40 "GeForce 6600 GT"
5564+0x10de 0x0141 NV_40 "GeForce 6600"
5565+0x10de 0x0142 NV_40 "GeForce 6600 LE"
5566+0x10de 0x0143 NV_40 "GeForce 6600 VE"
5567+0x10de 0x0144 NV_40 "GeForce Go 6600"
5568+0x10de 0x0145 NV_40 "GeForce 6610 XL"
5569+0x10de 0x0146 NV_40 "Geforce Go 6600TE/6200TE"
5570+0x10de 0x0147 NV_40 "GeForce 6700 XL"
5571+0x10de 0x0148 NV_40 "GeForce Go 6600"
5572+0x10de 0x0149 NV_40 "GeForce Go 6600 GT"
5573+0x10de 0x014a NV_40 "Quadro NVS 440"
5574+0x10de 0x014c NV_40 "Quadro FX 550"
5575+0x10de 0x014d NV_17 "Quadro FX 550"
5576+0x10de 0x014e NV_40 "Quadro FX 540"
5577+0x10de 0x014f NV_40 "GeForce 6200"
5578+0x10de 0x0150 NV_15 "GeForce2 GTS/Pro"
5579+0x10de 0x0151 NV_15 "GeForce2 Ti"
5580+0x10de 0x0152 NV_15 "GeForce2 Ultra, Bladerunner"
5581+0x10de 0x0153 NV_15 "Quadro2 Pro"
5582+0x10de 0x0160 NV_44 "GeForce 6500"
5583+0x10de 0x0161 NV_44 "GeForce 6200 TurboCache(TM)"
5584+0x10de 0x0162 NV_44 "GeForce 6200 SE TurboCache (TM)"
5585+0x10de 0x0163 NV_44 "GeForce 6200 LE"
5586+0x10de 0x0164 NV_44 "GeForce Go 6200"
5587+0x10de 0x0165 NV_44 "Quadro NVS 285"
5588+0x10de 0x0166 NV_44 "GeForce Go 6400"
5589+0x10de 0x0167 NV_44 "GeForce Go 6200 TurboCache"
5590+0x10de 0x0168 NV_44 "GeForce Go 6200 TurboCache"
5591+0x10de 0x0169 NV_44 "GeForce 6250"
5592+0x10de 0x0170 NV_17 "GeForce4 MX 460"
5593+0x10de 0x0171 NV_17 "GeForce4 MX 440"
5594+0x10de 0x0172 NV_17 "GeForce4 MX 420"
5595+0x10de 0x0173 NV_17 "GeForce4 MX 440-SE"
5596+0x10de 0x0174 NV_17 "GeForce4 440 Go"
5597+0x10de 0x0175 NV_17 "GeForce4 420 Go"
5598+0x10de 0x0176 NV_17 "GeForce4 420 Go 32M"
5599+0x10de 0x0177 NV_17 "GeForce4 460 Go"
5600+0x10de 0x0178 NV_17 "Quadro4 550 XGL"
5601+0x10de 0x0179 NV_17 "GeForce4 420 Go 32M"
5602+0x10de 0x017a NV_17 "Quadro4 200/400 NVS"
5603+0x10de 0x017b NV_17 "Quadro4 550 XGL"
5604+0x10de 0x017c NV_17 "Quadro4 500 GoGL"
5605+0x10de 0x017d NV_17 "GeForce4 410 Go 16M"
5606+0x10de 0x0181 NV_17 "GeForce4 MX 440 AGP 8x"
5607+0x10de 0x0182 NV_17 "GeForce4 MX 440SE AGP 8x"
5608+0x10de 0x0183 NV_17 "GeForce4 MX 420 AGP 8x"
5609+0x10de 0x0185 NV_17 "GeForce4 MX 4000 AGP 8x"
5610+0x10de 0x0186 NV_17 "GeForce4 448 Go"
5611+0x10de 0x0187 NV_17 "GeForce4 488 Go"
5612+0x10de 0x0188 NV_17 "Quadro4 580 XGL"
5613+0x10de 0x018a NV_17 "Quadro4 NVS AGP 8x"
5614+0x10de 0x018b NV_17 "Quadro4 380 XGL"
5615+0x10de 0x018c NV_17 "Quadro NVS 50 PCI"
5616+0x10de 0x018d NV_17 "GeForce4 448 Go"
5617+0x10de 0x0191 NV_50 "GeForce 8800 GTX"
5618+0x10de 0x0193 NV_50 "GeForce 8800 GTS"
5619+0x10de 0x0194 NV_50 "GeForce 8800 Ultra"
5620+0x10de 0x019d NV_50 "Quadro FX 5600"
5621+0x10de 0x019e NV_50 "Quadro FX 4600"
5622+0x10de 0x01a0 NV_11|NV_NFORCE "GeForce2 MX Integrated Graphics"
5623+0x10de 0x01d1 NV_44 "GeForce 7300 LE"
5624+0x10de 0x01d3 NV_44 "Geforce 7300 SE"
5625+0x10de 0x01d6 NV_44 "GeForce Go 7200"
5626+0x10de 0x01d7 NV_44 "Quadro NVS 110M / GeForce Go 7300"
5627+0x10de 0x01d8 NV_44 "GeForce Go 7400"
5628+0x10de 0x01d9 NV_44 "GeForce Go 7400 GS"
5629+0x10de 0x01da NV_44 "Quadro NVS 110M"
5630+0x10de 0x01db NV_44 "Quadro NVS 120M"
5631+0x10de 0x01dc NV_44 "Quadro FX 350M"
5632+0x10de 0x01dd NV_44 "GeForce 7500 LE"
5633+0x10de 0x01de NV_44 "Quadro FX 350"
5634+0x10de 0x01df NV_44 "GeForce 7300 GS"
5635+0x10de 0x01f0 NV_17|NV_NFORCE2 "GeForce4 MX - nForce GPU"
5636+0x10de 0x0200 NV_20 "GeForce3"
5637+0x10de 0x0201 NV_20 "GeForce3 Ti 200"
5638+0x10de 0x0202 NV_20 "GeForce3 Ti 500"
5639+0x10de 0x0203 NV_20 "Quadro DCC"
5640+0x10de 0x0211 NV_40 "GeForce 6800"
5641+0x10de 0x0212 NV_40 "GeForce 6800 LE"
5642+0x10de 0x0215 NV_40 "GeForce 6800 GT"
5643+0x10de 0x0218 NV_40 "GeForce 6800 XT"
5644+0x10de 0x0221 NV_44 "GeForce 6200"
5645+0x10de 0x0222 NV_44 "GeForce 6200 A-LE"
5646+0x10de 0x0240 NV_44 "GeForce 6150"
5647+0x10de 0x0241 NV_44 "GeForce 6150 LE"
5648+0x10de 0x0242 NV_44 "GeForce 6100"
5649+0x10de 0x0244 NV_44 "GeForce Go 6150"
5650+0x10de 0x0247 NV_44 "GeForce Go 6100"
5651+0x10de 0x0250 NV_25 "GeForce4 Ti 4600"
5652+0x10de 0x0251 NV_25 "GeForce4 Ti 4400"
5653+0x10de 0x0252 NV_25 "GeForce4 Ti"
5654+0x10de 0x0253 NV_25 "GeForce4 Ti 4200"
5655+0x10de 0x0258 NV_25 "Quadro4 900 XGL"
5656+0x10de 0x0259 NV_25 "Quadro4 750 XGL"
5657+0x10de 0x025b NV_25 "Quadro4 700 XGL"
5658+0x10de 0x0280 NV_25 "GeForce4 Ti 4800"
5659+0x10de 0x0281 NV_25 "GeForce4 Ti 4200 AGP 8x"
5660+0x10de 0x0282 NV_25 "GeForce4 Ti 4800 SE"
5661+0x10de 0x0286 NV_25 "GeForce4 Ti 4200 Go AGP 8x"
5662+0x10de 0x0288 NV_25 "Quadro4 980 XGL"
5663+0x10de 0x0289 NV_25 "Quadro4 780 XGL"
5664+0x10de 0x028c NV_25 "Quadro4 700 GoGL"
5665+0x10de 0x0290 NV_40 "GeForce 7900 GTX"
5666+0x10de 0x0291 NV_40 "GeForce 7900 GT"
5667+0x10de 0x0292 NV_40 "GeForce 7900 GS"
5668+0x10de 0x0298 NV_40 "GeForce Go 7900 GS"
5669+0x10de 0x0299 NV_40 "GeForce Go 7900 GTX"
5670+0x10de 0x029a NV_40 "Quadro FX 2500M"
5671+0x10de 0x029b NV_40 "Quadro FX 1500M"
5672+0x10de 0x029c NV_40 "Quadro FX 5500"
5673+0x10de 0x029d NV_40 "Quadro FX 3500"
5674+0x10de 0x029e NV_40 "Quadro FX 1500"
5675+0x10de 0x029f NV_40 "Quadro FX 4500 X2"
5676+0x10de 0x02a0 NV_20 "XGPU"
5677+0x10de 0x02e1 NV_40 "GeForce 7600 GS"
5678+0x10de 0x0300 NV_30 "GeForce FX"
5679+0x10de 0x0301 NV_30 "GeForce FX 5800 Ultra"
5680+0x10de 0x0302 NV_30 "GeForce FX 5800"
5681+0x10de 0x0308 NV_30 "Quadro FX 2000"
5682+0x10de 0x0309 NV_30 "Quadro FX 1000"
5683+0x10de 0x0311 NV_30 "GeForce FX 5600 Ultra"
5684+0x10de 0x0312 NV_30 "GeForce FX 5600"
5685+0x10de 0x0313 NV_30 "NV31"
5686+0x10de 0x0314 NV_30 "GeForce FX 5600XT"
5687+0x10de 0x0316 NV_30 "NV31M"
5688+0x10de 0x0317 NV_30 "NV31M Pro"
5689+0x10de 0x031a NV_30 "GeForce FX Go5600"
5690+0x10de 0x031b NV_30 "GeForce FX Go5650"
5691+0x10de 0x031d NV_30 "NV31GLM"
5692+0x10de 0x031e NV_30 "NV31GLM Pro"
5693+0x10de 0x031f NV_30 "NV31GLM Pro"
5694+0x10de 0x0320 NV_34 "GeForce FX 5200"
5695+0x10de 0x0321 NV_34 "GeForce FX 5200 Ultra"
5696+0x10de 0x0322 NV_34 "GeForce FX 5200"
5697+0x10de 0x0323 NV_34 "GeForce FX 5200LE"
5698+0x10de 0x0324 NV_34 "GeForce FX Go5200"
5699+0x10de 0x0325 NV_34 "GeForce FX Go5250"
5700+0x10de 0x0326 NV_34 "GeForce FX 5500"
5701+0x10de 0x0327 NV_34 "GeForce FX 5100"
5702+0x10de 0x0328 NV_34 "GeForce FX Go5200 32M/64M"
5703+0x10de 0x0329 NV_34 "GeForce FX Go5200"
5704+0x10de 0x032a NV_34 "Quadro NVS 280 PCI"
5705+0x10de 0x032b NV_34 "Quadro FX 500/600 PCI"
5706+0x10de 0x032c NV_34 "GeForce FX Go 5300"
5707+0x10de 0x032d NV_34 "GeForce FX Go5100"
5708+0x10de 0x032f NV_34 "NV34GL"
5709+0x10de 0x0330 NV_30 "GeForce FX 5900 Ultra"
5710+0x10de 0x0331 NV_30 "GeForce FX 5900"
5711+0x10de 0x0332 NV_30 "GeForce FX 5900XT"
5712+0x10de 0x0333 NV_30 "GeForce FX 5950 Ultra"
5713+0x10de 0x0334 NV_30 "GeForce FX 5900ZT"
5714+0x10de 0x0338 NV_30 "Quadro FX 3000"
5715+0x10de 0x033f NV_30 "Quadro FX 700"
5716+0x10de 0x0341 NV_30 "GeForce FX 5700 Ultra"
5717+0x10de 0x0342 NV_30 "GeForce FX 5700"
5718+0x10de 0x0343 NV_30 "GeForce FX 5700LE"
5719+0x10de 0x0344 NV_30 "GeForce FX 5700VE"
5720+0x10de 0x0345 NV_30 "NV36.5"
5721+0x10de 0x0347 NV_30 "GeForce FX Go5700"
5722+0x10de 0x0348 NV_30 "GeForce FX Go5700"
5723+0x10de 0x0349 NV_30 "NV36M Pro"
5724+0x10de 0x034b NV_30 "NV36MAP"
5725+0x10de 0x034c NV_30 "Quadro FX Go1000"
5726+0x10de 0x034e NV_30 "Quadro FX 1100"
5727+0x10de 0x034f NV_30 "NV36GL"
5728+0x10de 0x0391 NV_40 "GeForce 7600 GT"
5729+0x10de 0x0392 NV_40 "GeForce 7600 GS"
5730+0x10de 0x0393 NV_40 "GeForce 7300 GT"
5731+0x10de 0x0394 NV_40 "GeForce 7600 LE"
5732+0x10de 0x0395 NV_40 "GeForce 7300 GT"
5733+0x10de 0x0397 NV_40 "GeForce Go 7700"
5734+0x10de 0x0398 NV_40 "GeForce Go 7600"
5735+0x10de 0x0399 NV_40 "GeForce Go 7600 GT"
5736+0x10de 0x039a NV_40 "Quadro NVS 300M"
5737+0x10de 0x039b NV_40 "GeForce Go 7900 SE"
5738+0x10de 0x039c NV_40 "Quadro FX 550M"
5739+0x10de 0x039e NV_40 "Quadro FX 560"
5740+0x10de 0x03d0 NV_44 "GeForce 6100 nForce 430"
5741+0x10de 0x03d1 NV_44 "GeForce 6100 nForce 405"
5742+0x10de 0x03d2 NV_44 "GeForce 6100 nForce 400"
5743+0x10de 0x03d5 NV_44 "GeForce 6100 nForce 420"
5744+0x10de 0x0400 NV_50 "GeForce 8600 GTS"
5745+0x10de 0x0402 NV_50 "GeForce 8600 GT"
5746+0x10de 0x0421 NV_50 "GeForce 8500 GT"
5747+0x10de 0x0422 NV_50 "GeForce 8400 GS"
5748+0x10de 0x0423 NV_50 "GeForce 8300 GS"
5749+0x10de 0x0429 NV_50 "Quadro NVS 140"
5750+0x12d2 0x0020 NV_04 "TNT"
5751+0x12d2 0x0028 NV_04 "TNT2"
5752+0x12d2 0x0029 NV_04 "UTNT2"
5753+0x12d2 0x002c NV_04 "VTNT2"
5754+0x12d2 0x00a0 NV_04 "ITNT2"
5755+
5756+[xgi]
5757+0x18ca 0x2200 0 "XP5"
5758+0x18ca 0x0047 0 "XP10 / XG47"
5759Index: git/shared-core/drm_sarea.h
5760===================================================================
5761--- git.orig/shared-core/drm_sarea.h 2008-12-12 17:20:14.000000000 +0000
5762+++ git/shared-core/drm_sarea.h 2008-12-12 17:35:22.000000000 +0000
5763@@ -41,38 +41,44 @@
5764 #define SAREA_MAX 0x10000 /* 64kB */
5765 #else
5766 /* Intel 830M driver needs at least 8k SAREA */
5767-#define SAREA_MAX 0x2000
5768+#define SAREA_MAX 0x2000UL
5769 #endif
5770
5771 /** Maximum number of drawables in the SAREA */
5772-#define SAREA_MAX_DRAWABLES 256
5773+#define SAREA_MAX_DRAWABLES 256
5774
5775 #define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
5776
5777 /** SAREA drawable */
5778-typedef struct drm_sarea_drawable {
5779+struct drm_sarea_drawable {
5780 unsigned int stamp;
5781 unsigned int flags;
5782-} drm_sarea_drawable_t;
5783+};
5784
5785 /** SAREA frame */
5786-typedef struct drm_sarea_frame {
5787+struct drm_sarea_frame {
5788 unsigned int x;
5789 unsigned int y;
5790 unsigned int width;
5791 unsigned int height;
5792 unsigned int fullscreen;
5793-} drm_sarea_frame_t;
5794+};
5795
5796 /** SAREA */
5797-typedef struct drm_sarea {
5798+struct drm_sarea {
5799 /** first thing is always the DRM locking structure */
5800- drm_hw_lock_t lock;
5801+ struct drm_hw_lock lock;
5802 /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
5803- drm_hw_lock_t drawable_lock;
5804- drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
5805- drm_sarea_frame_t frame; /**< frame */
5806+ struct drm_hw_lock drawable_lock;
5807+ struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
5808+ struct drm_sarea_frame frame; /**< frame */
5809 drm_context_t dummy_context;
5810-} drm_sarea_t;
5811+};
5812+
5813+#ifndef __KERNEL__
5814+typedef struct drm_sarea_drawable drm_sarea_drawable_t;
5815+typedef struct drm_sarea_frame drm_sarea_frame_t;
5816+typedef struct drm_sarea drm_sarea_t;
5817+#endif
5818
5819 #endif /* _DRM_SAREA_H_ */
5820Index: git/shared-core/i915_dma.c
5821===================================================================
5822--- /dev/null 1970-01-01 00:00:00.000000000 +0000
5823+++ git/shared-core/i915_dma.c 2008-12-12 17:35:22.000000000 +0000
5824@@ -0,0 +1,968 @@
5825+/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
5826+ */
5827+/*
5828+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5829+ * All Rights Reserved.
5830+ *
5831+ * Permission is hereby granted, free of charge, to any person obtaining a
5832+ * copy of this software and associated documentation files (the
5833+ * "Software"), to deal in the Software without restriction, including
5834+ * without limitation the rights to use, copy, modify, merge, publish,
5835+ * distribute, sub license, and/or sell copies of the Software, and to
5836+ * permit persons to whom the Software is furnished to do so, subject to
5837+ * the following conditions:
5838+ *
5839+ * The above copyright notice and this permission notice (including the
5840+ * next paragraph) shall be included in all copies or substantial portions
5841+ * of the Software.
5842+ *
5843+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
5844+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
5845+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
5846+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
5847+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
5848+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
5849+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
5850+ *
5851+ */
5852+
5853+#include "drmP.h"
5854+#include "drm.h"
5855+#include "i915_drm.h"
5856+#include "i915_drv.h"
5857+
5858+#define IS_I965G(dev) (dev->pci_device == 0x2972 || \
5859+ dev->pci_device == 0x2982 || \
5860+ dev->pci_device == 0x2992 || \
5861+ dev->pci_device == 0x29A2 || \
5862+ dev->pci_device == 0x2A02 || \
5863+ dev->pci_device == 0x2A12)
5864+
5865+#define IS_G33(dev) (dev->pci_device == 0x29C2 || \
5866+ dev->pci_device == 0x29B2 || \
5867+ dev->pci_device == 0x29D2)
5868+
5869+/* Really want an OS-independent resettable timer. Would like to have
5870+ * this loop run for (eg) 3 sec, but have the timer reset every time
5871+ * the head pointer changes, so that EBUSY only happens if the ring
5872+ * actually stalls for (eg) 3 seconds.
5873+ */
5874+int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
5875+{
5876+ drm_i915_private_t *dev_priv = dev->dev_private;
5877+ drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
5878+ u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
5879+ int i;
5880+
5881+ for (i = 0; i < 10000; i++) {
5882+ ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
5883+ ring->space = ring->head - (ring->tail + 8);
5884+ if (ring->space < 0)
5885+ ring->space += ring->Size;
5886+ if (ring->space >= n)
5887+ return 0;
5888+
5889+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
5890+
5891+ if (ring->head != last_head)
5892+ i = 0;
5893+
5894+ last_head = ring->head;
5895+ DRM_UDELAY(1);
5896+ }
5897+
5898+ return -EBUSY;
5899+}
5900+
5901+void i915_kernel_lost_context(struct drm_device * dev)
5902+{
5903+ drm_i915_private_t *dev_priv = dev->dev_private;
5904+ drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
5905+
5906+ ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
5907+ ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
5908+ ring->space = ring->head - (ring->tail + 8);
5909+ if (ring->space < 0)
5910+ ring->space += ring->Size;
5911+
5912+ if (ring->head == ring->tail)
5913+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
5914+}
5915+
5916+static int i915_dma_cleanup(struct drm_device * dev)
5917+{
5918+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5919+ /* Make sure interrupts are disabled here because the uninstall ioctl
5920+ * may not have been called from userspace and after dev_private
5921+ * is freed, it's too late.
5922+ */
5923+ I915_WRITE(LP_RING + RING_LEN, 0);
5924+
5925+ if (dev->irq)
5926+ drm_irq_uninstall(dev);
5927+
5928+ if (dev->dev_private) {
5929+ drm_i915_private_t *dev_priv =
5930+ (drm_i915_private_t *) dev->dev_private;
5931+
5932+ if (dev_priv->ring.virtual_start) {
5933+ drm_core_ioremapfree(&dev_priv->ring.map, dev);
5934+ }
5935+
5936+ if (dev_priv->status_page_dmah) {
5937+ drm_pci_free(dev, dev_priv->status_page_dmah);
5938+ /* Need to rewrite hardware status page */
5939+ I915_WRITE(0x02080, 0x1ffff000);
5940+ }
5941+ if (dev_priv->status_gfx_addr) {
5942+ dev_priv->status_gfx_addr = 0;
5943+ drm_core_ioremapfree(&dev_priv->hws_map, dev);
5944+ I915_WRITE(0x02080, 0x1ffff000);
5945+ }
5946+ drm_free(dev->dev_private, sizeof(drm_i915_private_t),
5947+ DRM_MEM_DRIVER);
5948+
5949+ dev->dev_private = NULL;
5950+ }
5951+
5952+ return 0;
5953+}
5954+
5955+static int i915_initialize(struct drm_device * dev,
5956+ drm_i915_private_t * dev_priv,
5957+ drm_i915_init_t * init)
5958+{
5959+ dev_priv->sarea = drm_getsarea(dev);
5960+ if (!dev_priv->sarea) {
5961+ DRM_ERROR("can not find sarea!\n");
5962+ dev->dev_private = (void *)dev_priv;
5963+ i915_dma_cleanup(dev);
5964+ return -EINVAL;
5965+ }
5966+
5967+ memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
5968+
5969+ I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
5970+ I915_WRITE(LP_RING + RING_LEN, ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) | (RING_NO_REPORT | RING_VALID));
5971+
5972+ dev_priv->cpp = init->cpp;
5973+ dev_priv->sarea_priv->pf_current_page = 0;
5974+
5975+ /* We are using separate values as placeholders for mechanisms for
5976+ * private backbuffer/depthbuffer usage.
5977+ */
5978+ dev_priv->use_mi_batchbuffer_start = 0;
5979+
5980+ /* Allow hardware batchbuffers unless told otherwise.
5981+ */
5982+ dev_priv->allow_batchbuffer = 1;
5983+
5984+ /* Enable vblank on pipe A for older X servers
5985+ */
5986+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
5987+
5988+ /* Program Hardware Status Page */
5989+ if (!IS_G33(dev)) {
5990+ dev_priv->status_page_dmah =
5991+ drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
5992+
5993+ if (!dev_priv->status_page_dmah) {
5994+ dev->dev_private = (void *)dev_priv;
5995+ i915_dma_cleanup(dev);
5996+ DRM_ERROR("Can not allocate hardware status page\n");
5997+ return -ENOMEM;
5998+ }
5999+ dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
6000+ dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
6001+
6002+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
6003+
6004+ I915_WRITE(0x02080, dev_priv->dma_status_page);
6005+ }
6006+ DRM_DEBUG("Enabled hardware status page\n");
6007+ dev->dev_private = (void *)dev_priv;
6008+ return 0;
6009+}
6010+
6011+static int i915_dma_resume(struct drm_device * dev)
6012+{
6013+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
6014+
6015+ DRM_DEBUG("%s\n", __FUNCTION__);
6016+
6017+ if (!dev_priv->sarea) {
6018+ DRM_ERROR("can not find sarea!\n");
6019+ return -EINVAL;
6020+ }
6021+
6022+ if (!dev_priv->mmio_map) {
6023+ DRM_ERROR("can not find mmio map!\n");
6024+ return -EINVAL;
6025+ }
6026+
6027+ if (dev_priv->ring.map.handle == NULL) {
6028+ DRM_ERROR("can not ioremap virtual address for"
6029+ " ring buffer\n");
6030+ return -ENOMEM;
6031+ }
6032+
6033+ /* Program Hardware Status Page */
6034+ if (!dev_priv->hw_status_page) {
6035+ DRM_ERROR("Can not find hardware status page\n");
6036+ return -EINVAL;
6037+ }
6038+ DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
6039+
6040+ if (dev_priv->status_gfx_addr != 0)
6041+ I915_WRITE(0x02080, dev_priv->status_gfx_addr);
6042+ else
6043+ I915_WRITE(0x02080, dev_priv->dma_status_page);
6044+ DRM_DEBUG("Enabled hardware status page\n");
6045+
6046+ return 0;
6047+}
6048+
6049+static int i915_dma_init(struct drm_device *dev, void *data,
6050+ struct drm_file *file_priv)
6051+{
6052+ DRM_DEVICE;
6053+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
6054+ drm_i915_init_t init;
6055+ int retcode = 0;
6056+
6057+ switch (init->func) {
6058+ case I915_INIT_DMA:
6059+ retcode = i915_initialize(dev, dev_priv, &init);
6060+ break;
6061+ case I915_CLEANUP_DMA:
6062+ retcode = i915_dma_cleanup(dev);
6063+ break;
6064+ case I915_RESUME_DMA:
6065+ retcode = i915_dma_resume(dev);
6066+ break;
6067+ default:
6068+ retcode = -EINVAL;
6069+ break;
6070+ }
6071+
6072+ return retcode;
6073+}
6074+
6075+/* Implement basically the same security restrictions as hardware does
6076+ * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
6077+ *
6078+ * Most of the calculations below involve calculating the size of a
6079+ * particular instruction. It's important to get the size right as
6080+ * that tells us where the next instruction to check is. Any illegal
6081+ * instruction detected will be given a size of zero, which is a
6082+ * signal to abort the rest of the buffer.
6083+ */
6084+static int do_validate_cmd(int cmd)
6085+{
6086+ switch (((cmd >> 29) & 0x7)) {
6087+ case 0x0:
6088+ switch ((cmd >> 23) & 0x3f) {
6089+ case 0x0:
6090+ return 1; /* MI_NOOP */
6091+ case 0x4:
6092+ return 1; /* MI_FLUSH */
6093+ default:
6094+ return 0; /* disallow everything else */
6095+ }
6096+ break;
6097+ case 0x1:
6098+ return 0; /* reserved */
6099+ case 0x2:
6100+ return (cmd & 0xff) + 2; /* 2d commands */
6101+ case 0x3:
6102+ if (((cmd >> 24) & 0x1f) <= 0x18)
6103+ return 1;
6104+
6105+ switch ((cmd >> 24) & 0x1f) {
6106+ case 0x1c:
6107+ return 1;
6108+ case 0x1d:
6109+ switch ((cmd >> 16) & 0xff) {
6110+ case 0x3:
6111+ return (cmd & 0x1f) + 2;
6112+ case 0x4:
6113+ return (cmd & 0xf) + 2;
6114+ default:
6115+ return (cmd & 0xffff) + 2;
6116+ }
6117+ case 0x1e:
6118+ if (cmd & (1 << 23))
6119+ return (cmd & 0xffff) + 1;
6120+ else
6121+ return 1;
6122+ case 0x1f:
6123+ if ((cmd & (1 << 23)) == 0) /* inline vertices */
6124+ return (cmd & 0x1ffff) + 2;
6125+ else if (cmd & (1 << 17)) /* indirect random */
6126+ if ((cmd & 0xffff) == 0)
6127+ return 0; /* unknown length, too hard */
6128+ else
6129+ return (((cmd & 0xffff) + 1) / 2) + 1;
6130+ else
6131+ return 2; /* indirect sequential */
6132+ default:
6133+ return 0;
6134+ }
6135+ default:
6136+ return 0;
6137+ }
6138+
6139+ return 0;
6140+}
6141+
6142+static int validate_cmd(int cmd)
6143+{
6144+ int ret = do_validate_cmd(cmd);
6145+
6146+/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
6147+
6148+ return ret;
6149+}
6150+
6151+static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
6152+ int dwords)
6153+{
6154+ drm_i915_private_t *dev_priv = dev->dev_private;
6155+ int i;
6156+ RING_LOCALS;
6157+
6158+ if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
6159+ return -EINVAL;
6160+
6161+ BEGIN_LP_RING((dwords+1)&~1);
6162+
6163+ for (i = 0; i < dwords;) {
6164+ int cmd, sz;
6165+
6166+ if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
6167+ return -EINVAL;
6168+
6169+ if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
6170+ return -EINVAL;
6171+
6172+ OUT_RING(cmd);
6173+
6174+ while (++i, --sz) {
6175+ if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
6176+ sizeof(cmd))) {
6177+ return -EINVAL;
6178+ }
6179+ OUT_RING(cmd);
6180+ }
6181+ }
6182+
6183+ if (dwords & 1)
6184+ OUT_RING(0);
6185+
6186+ ADVANCE_LP_RING();
6187+
6188+ return 0;
6189+}
6190+
6191+static int i915_emit_box(struct drm_device * dev,
6192+ struct drm_clip_rect __user * boxes,
6193+ int i, int DR1, int DR4)
6194+{
6195+ drm_i915_private_t *dev_priv = dev->dev_private;
6196+ struct drm_clip_rect box;
6197+ RING_LOCALS;
6198+
6199+ if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
6200+ return -EFAULT;
6201+ }
6202+
6203+ if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
6204+ DRM_ERROR("Bad box %d,%d..%d,%d\n",
6205+ box.x1, box.y1, box.x2, box.y2);
6206+ return -EINVAL;
6207+ }
6208+
6209+ if (IS_I965G(dev)) {
6210+ BEGIN_LP_RING(4);
6211+ OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
6212+ OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
6213+ OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
6214+ OUT_RING(DR4);
6215+ ADVANCE_LP_RING();
6216+ } else {
6217+ BEGIN_LP_RING(6);
6218+ OUT_RING(GFX_OP_DRAWRECT_INFO);
6219+ OUT_RING(DR1);
6220+ OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
6221+ OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
6222+ OUT_RING(DR4);
6223+ OUT_RING(0);
6224+ ADVANCE_LP_RING();
6225+ }
6226+
6227+ return 0;
6228+}
6229+
6230+/* XXX: Emitting the counter should really be moved to part of the IRQ
6231+ * emit. For now, do it in both places:
6232+ */
6233+
6234+void i915_emit_breadcrumb(struct drm_device *dev)
6235+{
6236+ drm_i915_private_t *dev_priv = dev->dev_private;
6237+ RING_LOCALS;
6238+
6239+ if (++dev_priv->counter > BREADCRUMB_MASK) {
6240+ dev_priv->counter = 1;
6241+ DRM_DEBUG("Breadcrumb counter wrapped around\n");
6242+ }
6243+
6244+ dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
6245+
6246+ BEGIN_LP_RING(4);
6247+ OUT_RING(CMD_STORE_DWORD_IDX);
6248+ OUT_RING(20);
6249+ OUT_RING(dev_priv->counter);
6250+ OUT_RING(0);
6251+ ADVANCE_LP_RING();
6252+}
6253+
6254+
6255+int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
6256+{
6257+ drm_i915_private_t *dev_priv = dev->dev_private;
6258+ uint32_t flush_cmd = CMD_MI_FLUSH;
6259+ RING_LOCALS;
6260+
6261+ flush_cmd |= flush;
6262+
6263+ i915_kernel_lost_context(dev);
6264+
6265+ BEGIN_LP_RING(4);
6266+ OUT_RING(flush_cmd);
6267+ OUT_RING(0);
6268+ OUT_RING(0);
6269+ OUT_RING(0);
6270+ ADVANCE_LP_RING();
6271+
6272+ return 0;
6273+}
6274+
6275+
6276+static int i915_dispatch_cmdbuffer(struct drm_device * dev,
6277+ drm_i915_cmdbuffer_t * cmd)
6278+{
6279+#ifdef I915_HAVE_FENCE
6280+ drm_i915_private_t *dev_priv = dev->dev_private;
6281+#endif
6282+ int nbox = cmd->num_cliprects;
6283+ int i = 0, count, ret;
6284+
6285+ if (cmd->sz & 0x3) {
6286+ DRM_ERROR("alignment");
6287+ return -EINVAL;
6288+ }
6289+
6290+ i915_kernel_lost_context(dev);
6291+
6292+ count = nbox ? nbox : 1;
6293+
6294+ for (i = 0; i < count; i++) {
6295+ if (i < nbox) {
6296+ ret = i915_emit_box(dev, cmd->cliprects, i,
6297+ cmd->DR1, cmd->DR4);
6298+ if (ret)
6299+ return ret;
6300+ }
6301+
6302+ ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
6303+ if (ret)
6304+ return ret;
6305+ }
6306+
6307+ i915_emit_breadcrumb( dev );
6308+#ifdef I915_HAVE_FENCE
6309+ drm_fence_flush_old(dev, 0, dev_priv->counter);
6310+#endif
6311+ return 0;
6312+}
6313+
6314+static int i915_dispatch_batchbuffer(struct drm_device * dev,
6315+ drm_i915_batchbuffer_t * batch)
6316+{
6317+ drm_i915_private_t *dev_priv = dev->dev_private;
6318+ struct drm_clip_rect __user *boxes = batch->cliprects;
6319+ int nbox = batch->num_cliprects;
6320+ int i = 0, count;
6321+ RING_LOCALS;
6322+
6323+ if ((batch->start | batch->used) & 0x7) {
6324+ DRM_ERROR("alignment");
6325+ return -EINVAL;
6326+ }
6327+
6328+ i915_kernel_lost_context(dev);
6329+
6330+ count = nbox ? nbox : 1;
6331+
6332+ for (i = 0; i < count; i++) {
6333+ if (i < nbox) {
6334+ int ret = i915_emit_box(dev, boxes, i,
6335+ batch->DR1, batch->DR4);
6336+ if (ret)
6337+ return ret;
6338+ }
6339+
6340+ if (dev_priv->use_mi_batchbuffer_start) {
6341+ BEGIN_LP_RING(2);
6342+ if (IS_I965G(dev)) {
6343+ OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
6344+ OUT_RING(batch->start);
6345+ } else {
6346+ OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
6347+ OUT_RING(batch->start | MI_BATCH_NON_SECURE);
6348+ }
6349+ ADVANCE_LP_RING();
6350+
6351+ } else {
6352+ BEGIN_LP_RING(4);
6353+ OUT_RING(MI_BATCH_BUFFER);
6354+ OUT_RING(batch->start | MI_BATCH_NON_SECURE);
6355+ OUT_RING(batch->start + batch->used - 4);
6356+ OUT_RING(0);
6357+ ADVANCE_LP_RING();
6358+ }
6359+ }
6360+
6361+ i915_emit_breadcrumb( dev );
6362+#ifdef I915_HAVE_FENCE
6363+ drm_fence_flush_old(dev, 0, dev_priv->counter);
6364+#endif
6365+ return 0;
6366+}
6367+
6368+static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
6369+{
6370+ drm_i915_private_t *dev_priv = dev->dev_private;
6371+ u32 num_pages, current_page, next_page, dspbase;
6372+ int shift = 2 * plane, x, y;
6373+ RING_LOCALS;
6374+
6375+ /* Calculate display base offset */
6376+ num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
6377+ current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
6378+ next_page = (current_page + 1) % num_pages;
6379+
6380+ switch (next_page) {
6381+ default:
6382+ case 0:
6383+ dspbase = dev_priv->sarea_priv->front_offset;
6384+ break;
6385+ case 1:
6386+ dspbase = dev_priv->sarea_priv->back_offset;
6387+ break;
6388+ case 2:
6389+ dspbase = dev_priv->sarea_priv->third_offset;
6390+ break;
6391+ }
6392+
6393+ if (plane == 0) {
6394+ x = dev_priv->sarea_priv->planeA_x;
6395+ y = dev_priv->sarea_priv->planeA_y;
6396+ } else {
6397+ x = dev_priv->sarea_priv->planeB_x;
6398+ y = dev_priv->sarea_priv->planeB_y;
6399+ }
6400+
6401+ dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
6402+
6403+ DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
6404+ dspbase);
6405+
6406+ BEGIN_LP_RING(4);
6407+ OUT_RING(sync ? 0 :
6408+ (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
6409+ MI_WAIT_FOR_PLANE_A_FLIP)));
6410+ OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
6411+ (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
6412+ OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
6413+ OUT_RING(dspbase);
6414+ ADVANCE_LP_RING();
6415+
6416+ dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
6417+ dev_priv->sarea_priv->pf_current_page |= next_page << shift;
6418+}
6419+
6420+void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
6421+{
6422+ drm_i915_private_t *dev_priv = dev->dev_private;
6423+ int i;
6424+
6425+ DRM_DEBUG("%s: planes=0x%x pfCurrentPage=%d\n",
6426+ __FUNCTION__,
6427+ planes, dev_priv->sarea_priv->pf_current_page);
6428+
6429+ i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
6430+
6431+ for (i = 0; i < 2; i++)
6432+ if (planes & (1 << i))
6433+ i915_do_dispatch_flip(dev, i, sync);
6434+
6435+ i915_emit_breadcrumb(dev);
6436+#ifdef I915_HAVE_FENCE
6437+ if (!sync)
6438+ drm_fence_flush_old(dev, 0, dev_priv->counter);
6439+#endif
6440+}
6441+
6442+static int i915_quiescent(struct drm_device * dev)
6443+{
6444+ drm_i915_private_t *dev_priv = dev->dev_private;
6445+
6446+ i915_kernel_lost_context(dev);
6447+ return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
6448+}
6449+
6450+static int i915_flush_ioctl(struct drm_device *dev, void *data,
6451+ struct drm_file *file_priv)
6452+{
6453+
6454+ LOCK_TEST_WITH_RETURN(dev, file_priv);
6455+
6456+ return i915_quiescent(dev);
6457+}
6458+
6459+static int i915_batchbuffer(struct drm_device *dev, void *data,
6460+ struct drm_file *file_priv)
6461+{
6462+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
6463+ drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
6464+ dev_priv->sarea_priv;
6465+ drm_i915_batchbuffer_t *batch = data;
6466+ int ret;
6467+
6468+ if (!dev_priv->allow_batchbuffer) {
6469+ DRM_ERROR("Batchbuffer ioctl disabled\n");
6470+ return -EINVAL;
6471+ }
6472+
6473+ DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
6474+ batch->start, batch->used, batch->num_cliprects);
6475+
6476+ LOCK_TEST_WITH_RETURN(dev, file_priv);
6477+
6478+ if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
6479+ batch->num_cliprects *
6480+ sizeof(struct drm_clip_rect)))
6481+ return -EFAULT;
6482+
6483+ ret = i915_dispatch_batchbuffer(dev, batch);
6484+
6485+ sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
6486+ return ret;
6487+}
6488+
6489+static int i915_cmdbuffer(struct drm_device *dev, void *data,
6490+ struct drm_file *file_priv)
6491+{
6492+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
6493+ drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
6494+ dev_priv->sarea_priv;
6495+ drm_i915_cmdbuffer_t *cmdbuf = data;
6496+ int ret;
6497+
6498+ DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
6499+ cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
6500+
6501+ LOCK_TEST_WITH_RETURN(dev, file_priv);
6502+
6503+ if (cmdbuf->num_cliprects &&
6504+ DRM_VERIFYAREA_READ(cmdbuf->cliprects,
6505+ cmdbuf->num_cliprects *
6506+ sizeof(struct drm_clip_rect))) {
6507+ DRM_ERROR("Fault accessing cliprects\n");
6508+ return -EFAULT;
6509+ }
6510+
6511+ ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
6512+ if (ret) {
6513+ DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
6514+ return ret;
6515+ }
6516+
6517+ sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
6518+ return 0;
6519+}
6520+
6521+static int i915_do_cleanup_pageflip(struct drm_device * dev)
6522+{
6523+ drm_i915_private_t *dev_priv = dev->dev_private;
6524+ int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
6525+
6526+ DRM_DEBUG("%s\n", __FUNCTION__);
6527+
6528+ for (i = 0, planes = 0; i < 2; i++)
6529+ if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
6530+ dev_priv->sarea_priv->pf_current_page =
6531+ (dev_priv->sarea_priv->pf_current_page &
6532+ ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
6533+
6534+ planes |= 1 << i;
6535+ }
6536+
6537+ if (planes)
6538+ i915_dispatch_flip(dev, planes, 0);
6539+
6540+ return 0;
6541+}
6542+
6543+static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
6544+{
6545+ drm_i915_flip_t *param = data;
6546+
6547+ DRM_DEBUG("%s\n", __FUNCTION__);
6548+
6549+ LOCK_TEST_WITH_RETURN(dev, file_priv);
6550+
6551+ if (param->planes & ~0x3) {
6552+ DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
6553+ param->planes);
6554+ return -EINVAL;
6555+ }
6556+
6557+ i915_dispatch_flip(dev, param->planes, 0);
6558+
6559+ return 0;
6560+}
6561+
6562+
6563+static int i915_getparam(struct drm_device *dev, void *data,
6564+ struct drm_file *file_priv)
6565+{
6566+ drm_i915_private_t *dev_priv = dev->dev_private;
6567+ drm_i915_getparam_t *param = data;
6568+ int value;
6569+
6570+ if (!dev_priv) {
6571+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
6572+ return -EINVAL;
6573+ }
6574+
6575+ switch (param->param) {
6576+ case I915_PARAM_IRQ_ACTIVE:
6577+ value = dev->irq ? 1 : 0;
6578+ break;
6579+ case I915_PARAM_ALLOW_BATCHBUFFER:
6580+ value = dev_priv->allow_batchbuffer ? 1 : 0;
6581+ break;
6582+ case I915_PARAM_LAST_DISPATCH:
6583+ value = READ_BREADCRUMB(dev_priv);
6584+ break;
6585+ default:
6586+ DRM_ERROR("Unknown parameter %d\n", param->param);
6587+ return -EINVAL;
6588+ }
6589+
6590+ if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
6591+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
6592+ return -EFAULT;
6593+ }
6594+
6595+ return 0;
6596+}
6597+
6598+static int i915_setparam(struct drm_device *dev, void *data,
6599+ struct drm_file *file_priv)
6600+{
6601+ drm_i915_private_t *dev_priv = dev->dev_private;
6602+ drm_i915_setparam_t *param = data;
6603+
6604+ if (!dev_priv) {
6605+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
6606+ return -EINVAL;
6607+ }
6608+
6609+ switch (param->param) {
6610+ case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
6611+ dev_priv->use_mi_batchbuffer_start = param->value;
6612+ break;
6613+ case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
6614+ dev_priv->tex_lru_log_granularity = param->value;
6615+ break;
6616+ case I915_SETPARAM_ALLOW_BATCHBUFFER:
6617+ dev_priv->allow_batchbuffer = param->value;
6618+ break;
6619+ default:
6620+ DRM_ERROR("unknown parameter %d\n", param->param);
6621+ return -EINVAL;
6622+ }
6623+
6624+ return 0;
6625+}
6626+
6627+drm_i915_mmio_entry_t mmio_table[] = {
6628+ [MMIO_REGS_PS_DEPTH_COUNT] = {
6629+ I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
6630+ 0x2350,
6631+ 8
6632+ }
6633+};
6634+
6635+static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
6636+
6637+static int i915_mmio(struct drm_device *dev, void *data,
6638+ struct drm_file *file_priv)
6639+{
6640+ uint32_t buf[8];
6641+ drm_i915_private_t *dev_priv = dev->dev_private;
6642+ drm_i915_mmio_entry_t *e;
6643+ drm_i915_mmio_t *mmio = data;
6644+ void __iomem *base;
6645+ int i;
6646+
6647+ if (!dev_priv) {
6648+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
6649+ return -EINVAL;
6650+ }
6651+
6652+ if (mmio->reg >= mmio_table_size)
6653+ return -EINVAL;
6654+
6655+ e = &mmio_table[mmio->reg];
6656+ base = (u8 *) dev_priv->mmio_map->handle + e->offset;
6657+
6658+ switch (mmio->read_write) {
6659+ case I915_MMIO_READ:
6660+ if (!(e->flag & I915_MMIO_MAY_READ))
6661+ return -EINVAL;
6662+ for (i = 0; i < e->size / 4; i++)
6663+ buf[i] = I915_READ(e->offset + i * 4);
6664+ if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
6665+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
6666+ return -EFAULT;
6667+ }
6668+ break;
6669+
6670+ case I915_MMIO_WRITE:
6671+ if (!(e->flag & I915_MMIO_MAY_WRITE))
6672+ return -EINVAL;
6673+ if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
6674+ DRM_ERROR("DRM_COPY_TO_USER failed\n");
6675+ return -EFAULT;
6676+ }
6677+ for (i = 0; i < e->size / 4; i++)
6678+ I915_WRITE(e->offset + i * 4, buf[i]);
6679+ break;
6680+ }
6681+ return 0;
6682+}
6683+
6684+static int i915_set_status_page(struct drm_device *dev, void *data,
6685+ struct drm_file *file_priv)
6686+{
6687+ drm_i915_private_t *dev_priv = dev->dev_private;
6688+ drm_i915_hws_addr_t *hws = data;
6689+
6690+ if (!dev_priv) {
6691+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
6692+ return -EINVAL;
6693+ }
6694+ DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
6695+
6696+ dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
6697+
6698+ dev_priv->hws_map.offset = dev->agp->base + hws->addr;
6699+ dev_priv->hws_map.size = 4*1024;
6700+ dev_priv->hws_map.type = 0;
6701+ dev_priv->hws_map.flags = 0;
6702+ dev_priv->hws_map.mtrr = 0;
6703+
6704+ drm_core_ioremap(&dev_priv->hws_map, dev);
6705+ if (dev_priv->hws_map.handle == NULL) {
6706+ dev->dev_private = (void *)dev_priv;
6707+ i915_dma_cleanup(dev);
6708+ dev_priv->status_gfx_addr = 0;
6709+ DRM_ERROR("can not ioremap virtual address for"
6710+ " G33 hw status page\n");
6711+ return -ENOMEM;
6712+ }
6713+ dev_priv->hw_status_page = dev_priv->hws_map.handle;
6714+
6715+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
6716+ I915_WRITE(0x02080, dev_priv->status_gfx_addr);
6717+ DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
6718+ dev_priv->status_gfx_addr);
6719+ DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
6720+ return 0;
6721+}
6722+
6723+int i915_driver_load(struct drm_device *dev, unsigned long flags)
6724+{
6725+ /* i915 has 4 more counters */
6726+ dev->counters += 4;
6727+ dev->types[6] = _DRM_STAT_IRQ;
6728+ dev->types[7] = _DRM_STAT_PRIMARY;
6729+ dev->types[8] = _DRM_STAT_SECONDARY;
6730+ dev->types[9] = _DRM_STAT_DMA;
6731+
6732+ return 0;
6733+}
6734+
6735+void i915_driver_lastclose(struct drm_device * dev)
6736+{
6737+ if (dev->dev_private) {
6738+ drm_i915_private_t *dev_priv = dev->dev_private;
6739+ i915_do_cleanup_pageflip(dev);
6740+ i915_mem_takedown(&(dev_priv->agp_heap));
6741+ }
6742+ i915_dma_cleanup(dev);
6743+}
6744+
6745+void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
6746+{
6747+ if (dev->dev_private) {
6748+ drm_i915_private_t *dev_priv = dev->dev_private;
6749+ i915_mem_release(dev, file_priv, dev_priv->agp_heap);
6750+ }
6751+}
6752+
6753+struct drm_ioctl_desc i915_ioctls[] = {
6754+ DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
6755+ DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
6756+ DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
6757+ DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
6758+ DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
6759+ DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
6760+ DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
6761+ DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
6762+ DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
6763+ DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
6764+ DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
6765+ DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
6766+ DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
6767+ DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
6768+ DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
6769+ DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
6770+ DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
6771+ DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
6772+};
6773+
6774+int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
6775+
6776+/**
6777+ * Determine if the device really is AGP or not.
6778+ *
6779+ * All Intel graphics chipsets are treated as AGP, even if they are really
6780+ * PCI-e.
6781+ *
6782+ * \param dev The device to be tested.
6783+ *
6784+ * \returns
6785+ * A value of 1 is always retured to indictate every i9x5 is AGP.
6786+ */
6787+int i915_driver_device_is_agp(struct drm_device * dev)
6788+{
6789+ return 1;
6790+}
6791+
6792+
6793Index: git/shared-core/i915_drm.h
6794===================================================================
6795--- git.orig/shared-core/i915_drm.h 2008-12-12 17:20:14.000000000 +0000
6796+++ git/shared-core/i915_drm.h 2008-12-12 17:35:22.000000000 +0000
6797@@ -1,7 +1,7 @@
6798 /*
6799 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6800 * All Rights Reserved.
6801- *
6802+ *
6803 * Permission is hereby granted, free of charge, to any person obtaining a
6804 * copy of this software and associated documentation files (the
6805 * "Software"), to deal in the Software without restriction, including
6806@@ -9,11 +9,11 @@
6807 * distribute, sub license, and/or sell copies of the Software, and to
6808 * permit persons to whom the Software is furnished to do so, subject to
6809 * the following conditions:
6810- *
6811+ *
6812 * The above copyright notice and this permission notice (including the
6813 * next paragraph) shall be included in all copies or substantial portions
6814 * of the Software.
6815- *
6816+ *
6817 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
6818 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
6819 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
6820@@ -21,7 +21,7 @@
6821 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
6822 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
6823 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
6824- *
6825+ *
6826 */
6827
6828 #ifndef _I915_DRM_H_
6829@@ -39,7 +39,7 @@
6830 * of chars for next/prev indices */
6831 #define I915_LOG_MIN_TEX_REGION_SIZE 14
6832
6833-typedef struct _drm_i915_init {
6834+typedef struct drm_i915_init {
6835 enum {
6836 I915_INIT_DMA = 0x01,
6837 I915_CLEANUP_DMA = 0x02,
6838@@ -63,8 +63,8 @@
6839 unsigned int chipset;
6840 } drm_i915_init_t;
6841
6842-typedef struct _drm_i915_sarea {
6843- drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
6844+typedef struct drm_i915_sarea {
6845+ struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
6846 int last_upload; /* last time texture was uploaded */
6847 int last_enqueue; /* last time a buffer was enqueued */
6848 int last_dispatch; /* age of the most recently dispatched buffer */
6849@@ -105,14 +105,20 @@
6850 unsigned int rotated_tiled;
6851 unsigned int rotated2_tiled;
6852
6853- int pipeA_x;
6854- int pipeA_y;
6855- int pipeA_w;
6856- int pipeA_h;
6857- int pipeB_x;
6858- int pipeB_y;
6859- int pipeB_w;
6860- int pipeB_h;
6861+ int planeA_x;
6862+ int planeA_y;
6863+ int planeA_w;
6864+ int planeA_h;
6865+ int planeB_x;
6866+ int planeB_y;
6867+ int planeB_w;
6868+ int planeB_h;
6869+
6870+ /* Triple buffering */
6871+ drm_handle_t third_handle;
6872+ int third_offset;
6873+ int third_size;
6874+ unsigned int third_tiled;
6875 } drm_i915_sarea_t;
6876
6877 /* Driver specific fence types and classes.
6878@@ -152,10 +158,13 @@
6879 #define DRM_I915_SET_VBLANK_PIPE 0x0d
6880 #define DRM_I915_GET_VBLANK_PIPE 0x0e
6881 #define DRM_I915_VBLANK_SWAP 0x0f
6882+#define DRM_I915_MMIO 0x10
6883+#define DRM_I915_HWS_ADDR 0x11
6884+#define DRM_I915_EXECBUFFER 0x12
6885
6886 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
6887 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
6888-#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
6889+#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
6890 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
6891 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
6892 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
6893@@ -169,30 +178,42 @@
6894 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
6895 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
6896 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
6897+#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
6898
6899+/* Asynchronous page flipping:
6900+ */
6901+typedef struct drm_i915_flip {
6902+ /*
6903+ * This is really talking about planes, and we could rename it
6904+ * except for the fact that some of the duplicated i915_drm.h files
6905+ * out there check for HAVE_I915_FLIP and so might pick up this
6906+ * version.
6907+ */
6908+ int pipes;
6909+} drm_i915_flip_t;
6910
6911 /* Allow drivers to submit batchbuffers directly to hardware, relying
6912 * on the security mechanisms provided by hardware.
6913 */
6914-typedef struct _drm_i915_batchbuffer {
6915+typedef struct drm_i915_batchbuffer {
6916 int start; /* agp offset */
6917 int used; /* nr bytes in use */
6918 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
6919 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
6920 int num_cliprects; /* mulitpass with multiple cliprects? */
6921- drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
6922+ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
6923 } drm_i915_batchbuffer_t;
6924
6925 /* As above, but pass a pointer to userspace buffer which can be
6926 * validated by the kernel prior to sending to hardware.
6927 */
6928-typedef struct _drm_i915_cmdbuffer {
6929+typedef struct drm_i915_cmdbuffer {
6930 char __user *buf; /* pointer to userspace command buffer */
6931 int sz; /* nr bytes in buf */
6932 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
6933 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
6934 int num_cliprects; /* mulitpass with multiple cliprects? */
6935- drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
6936+ struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
6937 } drm_i915_cmdbuffer_t;
6938
6939 /* Userspace can request & wait on irq's:
6940@@ -269,8 +290,76 @@
6941 */
6942 typedef struct drm_i915_vblank_swap {
6943 drm_drawable_t drawable;
6944- drm_vblank_seq_type_t seqtype;
6945+ enum drm_vblank_seq_type seqtype;
6946 unsigned int sequence;
6947 } drm_i915_vblank_swap_t;
6948
6949+#define I915_MMIO_READ 0
6950+#define I915_MMIO_WRITE 1
6951+
6952+#define I915_MMIO_MAY_READ 0x1
6953+#define I915_MMIO_MAY_WRITE 0x2
6954+
6955+#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
6956+#define MMIO_REGS_IA_VERTICES_COUNT 1
6957+#define MMIO_REGS_VS_INVOCATION_COUNT 2
6958+#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
6959+#define MMIO_REGS_GS_INVOCATION_COUNT 4
6960+#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
6961+#define MMIO_REGS_CL_INVOCATION_COUNT 6
6962+#define MMIO_REGS_PS_INVOCATION_COUNT 7
6963+#define MMIO_REGS_PS_DEPTH_COUNT 8
6964+
6965+typedef struct drm_i915_mmio_entry {
6966+ unsigned int flag;
6967+ unsigned int offset;
6968+ unsigned int size;
6969+}drm_i915_mmio_entry_t;
6970+
6971+typedef struct drm_i915_mmio {
6972+ unsigned int read_write:1;
6973+ unsigned int reg:31;
6974+ void __user *data;
6975+} drm_i915_mmio_t;
6976+
6977+typedef struct drm_i915_hws_addr {
6978+ uint64_t addr;
6979+} drm_i915_hws_addr_t;
6980+
6981+/*
6982+ * Relocation header is 4 uint32_ts
6983+ * 0 - (16-bit relocation type << 16)| 16 bit reloc count
6984+ * 1 - buffer handle for another list of relocs
6985+ * 2-3 - spare.
6986+ */
6987+#define I915_RELOC_HEADER 4
6988+
6989+/*
6990+ * type 0 relocation has 4-uint32_t stride
6991+ * 0 - offset into buffer
6992+ * 1 - delta to add in
6993+ * 2 - index into buffer list
6994+ * 3 - reserved (for optimisations later).
6995+ */
6996+#define I915_RELOC_TYPE_0 0
6997+#define I915_RELOC0_STRIDE 4
6998+
6999+struct drm_i915_op_arg {
7000+ uint64_t next;
7001+ uint32_t reloc_handle;
7002+ int handled;
7003+ union {
7004+ struct drm_bo_op_req req;
7005+ struct drm_bo_arg_rep rep;
7006+ } d;
7007+
7008+};
7009+
7010+struct drm_i915_execbuffer {
7011+ uint64_t ops_list;
7012+ uint32_t num_buffers;
7013+ struct drm_i915_batchbuffer batch;
7014+ struct drm_fence_arg fence_arg;
7015+};
7016+
7017 #endif /* _I915_DRM_H_ */
7018Index: git/shared-core/i915_drv.h
7019===================================================================
7020--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7021+++ git/shared-core/i915_drv.h 2008-12-12 17:35:22.000000000 +0000
7022@@ -0,0 +1,676 @@
7023+/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
7024+ */
7025+/*
7026+ *
7027+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7028+ * All Rights Reserved.
7029+ *
7030+ * Permission is hereby granted, free of charge, to any person obtaining a
7031+ * copy of this software and associated documentation files (the
7032+ * "Software"), to deal in the Software without restriction, including
7033+ * without limitation the rights to use, copy, modify, merge, publish,
7034+ * distribute, sub license, and/or sell copies of the Software, and to
7035+ * permit persons to whom the Software is furnished to do so, subject to
7036+ * the following conditions:
7037+ *
7038+ * The above copyright notice and this permission notice (including the
7039+ * next paragraph) shall be included in all copies or substantial portions
7040+ * of the Software.
7041+ *
7042+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
7043+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
7044+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
7045+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
7046+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
7047+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
7048+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7049+ *
7050+ */
7051+
7052+#ifndef _I915_DRV_H_
7053+#define _I915_DRV_H_
7054+
7055+#include "i915_reg.h"
7056+
7057+/* General customization:
7058+ */
7059+
7060+#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
7061+
7062+#define DRIVER_NAME "i915"
7063+#define DRIVER_DESC "Intel Graphics"
7064+#define DRIVER_DATE "20070209"
7065+
7066+#if defined(__linux__)
7067+#define I915_HAVE_FENCE
7068+#define I915_HAVE_BUFFER
7069+#endif
7070+
7071+/* Interface history:
7072+ *
7073+ * 1.1: Original.
7074+ * 1.2: Add Power Management
7075+ * 1.3: Add vblank support
7076+ * 1.4: Fix cmdbuffer path, add heap destroy
7077+ * 1.5: Add vblank pipe configuration
7078+ * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
7079+ * - Support vertical blank on secondary display pipe
7080+ * 1.8: New ioctl for ARB_Occlusion_Query
7081+ * 1.9: Usable page flipping and triple buffering
7082+ * 1.10: Plane/pipe disentangling
7083+ */
7084+#define DRIVER_MAJOR 1
7085+#if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
7086+#define DRIVER_MINOR 10
7087+#else
7088+#define DRIVER_MINOR 6
7089+#endif
7090+#define DRIVER_PATCHLEVEL 0
7091+
7092+#define DRM_DRIVER_PRIVATE_T drm_i915_private_t
7093+
7094+typedef struct _drm_i915_ring_buffer {
7095+ int tail_mask;
7096+ unsigned long Start;
7097+ unsigned long End;
7098+ unsigned long Size;
7099+ u8 *virtual_start;
7100+ int head;
7101+ int tail;
7102+ int space;
7103+ drm_local_map_t map;
7104+} drm_i915_ring_buffer_t;
7105+
7106+struct mem_block {
7107+ struct mem_block *next;
7108+ struct mem_block *prev;
7109+ int start;
7110+ int size;
7111+ struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
7112+};
7113+
7114+typedef struct _drm_i915_vbl_swap {
7115+ struct list_head head;
7116+ drm_drawable_t drw_id;
7117+ unsigned int plane;
7118+ unsigned int sequence;
7119+ int flip;
7120+} drm_i915_vbl_swap_t;
7121+
7122+typedef struct drm_i915_private {
7123+ drm_buffer_object_t *ring_buffer;
7124+ drm_local_map_t *sarea;
7125+ drm_local_map_t *mmio_map;
7126+
7127+ unsigned long mmiobase;
7128+ unsigned long mmiolen;
7129+
7130+ drm_i915_sarea_t *sarea_priv;
7131+ drm_i915_ring_buffer_t ring;
7132+
7133+ drm_dma_handle_t *status_page_dmah;
7134+ void *hw_status_page;
7135+ dma_addr_t dma_status_page;
7136+ uint32_t counter;
7137+ unsigned int status_gfx_addr;
7138+ drm_local_map_t hws_map;
7139+
7140+ unsigned int cpp;
7141+ int use_mi_batchbuffer_start;
7142+
7143+ wait_queue_head_t irq_queue;
7144+ atomic_t irq_received;
7145+ atomic_t irq_emitted;
7146+
7147+ int tex_lru_log_granularity;
7148+ int allow_batchbuffer;
7149+ struct mem_block *agp_heap;
7150+ unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
7151+ int vblank_pipe;
7152+ DRM_SPINTYPE user_irq_lock;
7153+ int user_irq_refcount;
7154+ int fence_irq_on;
7155+ uint32_t irq_enable_reg;
7156+ int irq_enabled;
7157+
7158+#ifdef I915_HAVE_FENCE
7159+ uint32_t flush_sequence;
7160+ uint32_t flush_flags;
7161+ uint32_t flush_pending;
7162+ uint32_t saved_flush_status;
7163+#endif
7164+#ifdef I915_HAVE_BUFFER
7165+ void *agp_iomap;
7166+#endif
7167+ DRM_SPINTYPE swaps_lock;
7168+ drm_i915_vbl_swap_t vbl_swaps;
7169+ unsigned int swaps_pending;
7170+
7171+ /* LVDS info */
7172+ int backlight_duty_cycle; /* restore backlight to this value */
7173+ bool panel_wants_dither;
7174+ struct drm_display_mode *panel_fixed_mode;
7175+
7176+ /* Register state */
7177+ u32 saveDSPACNTR;
7178+ u32 saveDSPBCNTR;
7179+ u32 savePIPEACONF;
7180+ u32 savePIPEBCONF;
7181+ u32 savePIPEASRC;
7182+ u32 savePIPEBSRC;
7183+ u32 saveFPA0;
7184+ u32 saveFPA1;
7185+ u32 saveDPLL_A;
7186+ u32 saveDPLL_A_MD;
7187+ u32 saveHTOTAL_A;
7188+ u32 saveHBLANK_A;
7189+ u32 saveHSYNC_A;
7190+ u32 saveVTOTAL_A;
7191+ u32 saveVBLANK_A;
7192+ u32 saveVSYNC_A;
7193+ u32 saveDSPASTRIDE;
7194+ u32 saveDSPASIZE;
7195+ u32 saveDSPAPOS;
7196+ u32 saveDSPABASE;
7197+ u32 saveDSPASURF;
7198+ u32 saveFPB0;
7199+ u32 saveFPB1;
7200+ u32 saveDPLL_B;
7201+ u32 saveDPLL_B_MD;
7202+ u32 saveHTOTAL_B;
7203+ u32 saveHBLANK_B;
7204+ u32 saveHSYNC_B;
7205+ u32 saveVTOTAL_B;
7206+ u32 saveVBLANK_B;
7207+ u32 saveVSYNC_B;
7208+ u32 saveDSPBSTRIDE;
7209+ u32 saveDSPBSIZE;
7210+ u32 saveDSPBPOS;
7211+ u32 saveDSPBBASE;
7212+ u32 saveDSPBSURF;
7213+ u32 saveVCLK_DIVISOR_VGA0;
7214+ u32 saveVCLK_DIVISOR_VGA1;
7215+ u32 saveVCLK_POST_DIV;
7216+ u32 saveVGACNTRL;
7217+ u32 saveADPA;
7218+ u32 saveLVDS;
7219+ u32 saveDVOA;
7220+ u32 saveDVOB;
7221+ u32 saveDVOC;
7222+ u32 savePP_ON;
7223+ u32 savePP_OFF;
7224+ u32 savePP_CONTROL;
7225+ u32 savePP_CYCLE;
7226+ u32 savePFIT_CONTROL;
7227+ u32 savePaletteA[256];
7228+ u32 savePaletteB[256];
7229+ u32 saveSWF[17];
7230+ u32 saveBLC_PWM_CTL;
7231+} drm_i915_private_t;
7232+
7233+enum intel_chip_family {
7234+ CHIP_I8XX = 0x01,
7235+ CHIP_I9XX = 0x02,
7236+ CHIP_I915 = 0x04,
7237+ CHIP_I965 = 0x08,
7238+ CHIP_POULSBO = 0x10,
7239+};
7240+
7241+extern struct drm_ioctl_desc i915_ioctls[];
7242+extern int i915_max_ioctl;
7243+
7244+ /* i915_dma.c */
7245+extern void i915_kernel_lost_context(struct drm_device * dev);
7246+extern int i915_driver_load(struct drm_device *, unsigned long flags);
7247+extern void i915_driver_lastclose(struct drm_device * dev);
7248+extern void i915_driver_preclose(struct drm_device *dev,
7249+ struct drm_file *file_priv);
7250+extern int i915_driver_device_is_agp(struct drm_device * dev);
7251+extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
7252+ unsigned long arg);
7253+extern void i915_emit_breadcrumb(struct drm_device *dev);
7254+extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
7255+extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
7256+extern int i915_driver_firstopen(struct drm_device *dev);
7257+extern int i915_dma_cleanup(drm_device_t * dev);
7258+
7259+/* i915_irq.c */
7260+extern int i915_irq_emit(struct drm_device *dev, void *data,
7261+ struct drm_file *file_priv);
7262+extern int i915_irq_wait(struct drm_device *dev, void *data,
7263+ struct drm_file *file_priv);
7264+
7265+extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
7266+extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
7267+extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
7268+extern void i915_driver_irq_preinstall(struct drm_device * dev);
7269+extern void i915_driver_irq_postinstall(struct drm_device * dev);
7270+extern void i915_driver_irq_uninstall(struct drm_device * dev);
7271+extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
7272+ struct drm_file *file_priv);
7273+extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
7274+ struct drm_file *file_priv);
7275+extern int i915_emit_irq(struct drm_device * dev);
7276+extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
7277+extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
7278+extern int i915_vblank_swap(struct drm_device *dev, void *data,
7279+ struct drm_file *file_priv);
7280+
7281+/* i915_mem.c */
7282+extern int i915_mem_alloc(struct drm_device *dev, void *data,
7283+ struct drm_file *file_priv);
7284+extern int i915_mem_free(struct drm_device *dev, void *data,
7285+ struct drm_file *file_priv);
7286+extern int i915_mem_init_heap(struct drm_device *dev, void *data,
7287+ struct drm_file *file_priv);
7288+extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
7289+ struct drm_file *file_priv);
7290+extern void i915_mem_takedown(struct mem_block **heap);
7291+extern void i915_mem_release(struct drm_device * dev,
7292+ struct drm_file *file_priv,
7293+ struct mem_block *heap);
7294+#ifdef I915_HAVE_FENCE
7295+/* i915_fence.c */
7296+
7297+
7298+extern void i915_fence_handler(struct drm_device *dev);
7299+extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
7300+ uint32_t flags,
7301+ uint32_t *sequence,
7302+ uint32_t *native_type);
7303+extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
7304+extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
7305+#endif
7306+
7307+#ifdef I915_HAVE_BUFFER
7308+/* i915_buffer.c */
7309+extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
7310+extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *fclass,
7311+ uint32_t *type);
7312+extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
7313+extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
7314+ struct drm_mem_type_manager *man);
7315+extern uint32_t i915_evict_mask(struct drm_buffer_object *bo);
7316+extern int i915_move(struct drm_buffer_object *bo, int evict,
7317+ int no_wait, struct drm_bo_mem_reg *new_mem);
7318+
7319+#endif
7320+
7321+
7322+/* modesetting */
7323+extern void intel_modeset_init(drm_device_t *dev);
7324+extern void intel_modeset_cleanup(drm_device_t *dev);
7325+
7326+
7327+#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
7328+#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
7329+#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
7330+#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
7331+
7332+#define I915_VERBOSE 0
7333+
7334+#define RING_LOCALS unsigned int outring, ringmask, outcount; \
7335+ volatile char *virt;
7336+
7337+#define BEGIN_LP_RING(n) do { \
7338+ if (I915_VERBOSE) \
7339+ DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
7340+ (n), __FUNCTION__); \
7341+ if (dev_priv->ring.space < (n)*4) \
7342+ i915_wait_ring(dev, (n)*4, __FUNCTION__); \
7343+ outcount = 0; \
7344+ outring = dev_priv->ring.tail; \
7345+ ringmask = dev_priv->ring.tail_mask; \
7346+ virt = dev_priv->ring.virtual_start; \
7347+} while (0)
7348+
7349+#define OUT_RING(n) do { \
7350+ if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
7351+ *(volatile unsigned int *)(virt + outring) = (n); \
7352+ outcount++; \
7353+ outring += 4; \
7354+ outring &= ringmask; \
7355+} while (0)
7356+
7357+#define ADVANCE_LP_RING() do { \
7358+ if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
7359+ dev_priv->ring.tail = outring; \
7360+ dev_priv->ring.space -= outcount * 4; \
7361+ I915_WRITE(LP_RING + RING_TAIL, outring); \
7362+} while(0)
7363+
7364+extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
7365+
7366+/*
7367+ * The Bridge device's PCI config space has information about the
7368+ * fb aperture size and the amount of pre-reserved memory.
7369+ */
7370+#define INTEL_GMCH_CTRL 0x52
7371+#define INTEL_GMCH_ENABLED 0x4
7372+#define INTEL_GMCH_MEM_MASK 0x1
7373+#define INTEL_GMCH_MEM_64M 0x1
7374+#define INTEL_GMCH_MEM_128M 0
7375+
7376+#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
7377+#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
7378+#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
7379+#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
7380+#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
7381+#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
7382+#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
7383+
7384+#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
7385+#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
7386+
7387+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
7388+#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
7389+#define CMD_REPORT_HEAD (7<<23)
7390+#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
7391+#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
7392+
7393+#define CMD_MI_FLUSH (0x04 << 23)
7394+#define MI_NO_WRITE_FLUSH (1 << 2)
7395+#define MI_READ_FLUSH (1 << 0)
7396+#define MI_EXE_FLUSH (1 << 1)
7397+#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
7398+#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
7399+
7400+/* Packet to load a register value from the ring/batch command stream:
7401+ */
7402+#define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
7403+
7404+#define BB1_START_ADDR_MASK (~0x7)
7405+#define BB1_PROTECTED (1<<0)
7406+#define BB1_UNPROTECTED (0<<0)
7407+#define BB2_END_ADDR_MASK (~0x7)
7408+
7409+/* Interrupt bits:
7410+ */
7411+#define USER_INT_FLAG (1<<1)
7412+#define VSYNC_PIPEB_FLAG (1<<5)
7413+#define VSYNC_PIPEA_FLAG (1<<7)
7414+#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
7415+
7416+#define I915REG_HWSTAM 0x02098
7417+#define I915REG_INT_IDENTITY_R 0x020a4
7418+#define I915REG_INT_MASK_R 0x020a8
7419+#define I915REG_INT_ENABLE_R 0x020a0
7420+#define I915REG_INSTPM 0x020c0
7421+
7422+#define I915REG_PIPEASTAT 0x70024
7423+#define I915REG_PIPEBSTAT 0x71024
7424+
7425+#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
7426+#define I915_VBLANK_CLEAR (1UL<<1)
7427+
7428+#define GPIOA 0x5010
7429+#define GPIOB 0x5014
7430+#define GPIOC 0x5018
7431+#define GPIOD 0x501c
7432+#define GPIOE 0x5020
7433+#define GPIOF 0x5024
7434+#define GPIOG 0x5028
7435+#define GPIOH 0x502c
7436+# define GPIO_CLOCK_DIR_MASK (1 << 0)
7437+# define GPIO_CLOCK_DIR_IN (0 << 1)
7438+# define GPIO_CLOCK_DIR_OUT (1 << 1)
7439+# define GPIO_CLOCK_VAL_MASK (1 << 2)
7440+# define GPIO_CLOCK_VAL_OUT (1 << 3)
7441+# define GPIO_CLOCK_VAL_IN (1 << 4)
7442+# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
7443+# define GPIO_DATA_DIR_MASK (1 << 8)
7444+# define GPIO_DATA_DIR_IN (0 << 9)
7445+# define GPIO_DATA_DIR_OUT (1 << 9)
7446+# define GPIO_DATA_VAL_MASK (1 << 10)
7447+# define GPIO_DATA_VAL_OUT (1 << 11)
7448+# define GPIO_DATA_VAL_IN (1 << 12)
7449+# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
7450+
7451+/* p317, 319
7452+ */
7453+#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
7454+#define VCLK2_VCO_N 0x600a
7455+#define VCLK2_VCO_DIV_SEL 0x6012
7456+
7457+#define VCLK_DIVISOR_VGA0 0x6000
7458+#define VCLK_DIVISOR_VGA1 0x6004
7459+#define VCLK_POST_DIV 0x6010
7460+/** Selects a post divisor of 4 instead of 2. */
7461+# define VGA1_PD_P2_DIV_4 (1 << 15)
7462+/** Overrides the p2 post divisor field */
7463+# define VGA1_PD_P1_DIV_2 (1 << 13)
7464+# define VGA1_PD_P1_SHIFT 8
7465+/** P1 value is 2 greater than this field */
7466+# define VGA1_PD_P1_MASK (0x1f << 8)
7467+/** Selects a post divisor of 4 instead of 2. */
7468+# define VGA0_PD_P2_DIV_4 (1 << 7)
7469+/** Overrides the p2 post divisor field */
7470+# define VGA0_PD_P1_DIV_2 (1 << 5)
7471+# define VGA0_PD_P1_SHIFT 0
7472+/** P1 value is 2 greater than this field */
7473+# define VGA0_PD_P1_MASK (0x1f << 0)
7474+
7475+#define POST_DIV_SELECT 0x70
7476+#define POST_DIV_1 0x00
7477+#define POST_DIV_2 0x10
7478+#define POST_DIV_4 0x20
7479+#define POST_DIV_8 0x30
7480+#define POST_DIV_16 0x40
7481+#define POST_DIV_32 0x50
7482+#define VCO_LOOP_DIV_BY_4M 0x00
7483+#define VCO_LOOP_DIV_BY_16M 0x04
7484+
7485+#define SRX_INDEX 0x3c4
7486+#define SRX_DATA 0x3c5
7487+#define SR01 1
7488+#define SR01_SCREEN_OFF (1<<5)
7489+
7490+#define PPCR 0x61204
7491+#define PPCR_ON (1<<0)
7492+
7493+#define DVOA 0x61120
7494+#define DVOA_ON (1<<31)
7495+#define DVOB 0x61140
7496+#define DVOB_ON (1<<31)
7497+#define DVOC 0x61160
7498+#define DVOC_ON (1<<31)
7499+#define LVDS 0x61180
7500+#define LVDS_ON (1<<31)
7501+
7502+#define ADPA 0x61100
7503+#define ADPA_DPMS_MASK (~(3<<10))
7504+#define ADPA_DPMS_ON (0<<10)
7505+#define ADPA_DPMS_SUSPEND (1<<10)
7506+#define ADPA_DPMS_STANDBY (2<<10)
7507+#define ADPA_DPMS_OFF (3<<10)
7508+
7509+#define NOPID 0x2094
7510+#define LP_RING 0x2030
7511+#define HP_RING 0x2040
7512+/* The binner has its own ring buffer:
7513+ */
7514+#define HWB_RING 0x2400
7515+
7516+#define RING_TAIL 0x00
7517+#define TAIL_ADDR 0x001FFFF8
7518+#define RING_HEAD 0x04
7519+#define HEAD_WRAP_COUNT 0xFFE00000
7520+#define HEAD_WRAP_ONE 0x00200000
7521+#define HEAD_ADDR 0x001FFFFC
7522+#define RING_START 0x08
7523+#define START_ADDR 0x0xFFFFF000
7524+#define RING_LEN 0x0C
7525+#define RING_NR_PAGES 0x001FF000
7526+#define RING_REPORT_MASK 0x00000006
7527+#define RING_REPORT_64K 0x00000002
7528+#define RING_REPORT_128K 0x00000004
7529+#define RING_NO_REPORT 0x00000000
7530+#define RING_VALID_MASK 0x00000001
7531+#define RING_VALID 0x00000001
7532+#define RING_INVALID 0x00000000
7533+
7534+/* Instruction parser error reg:
7535+ */
7536+#define IPEIR 0x2088
7537+
7538+/* Scratch pad debug 0 reg:
7539+ */
7540+#define SCPD0 0x209c
7541+
7542+/* Error status reg:
7543+ */
7544+#define ESR 0x20b8
7545+
7546+/* Secondary DMA fetch address debug reg:
7547+ */
7548+#define DMA_FADD_S 0x20d4
7549+
7550+/* Cache mode 0 reg.
7551+ * - Manipulating render cache behaviour is central
7552+ * to the concept of zone rendering, tuning this reg can help avoid
7553+ * unnecessary render cache reads and even writes (for z/stencil)
7554+ * at beginning and end of scene.
7555+ *
7556+ * - To change a bit, write to this reg with a mask bit set and the
7557+ * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
7558+ */
7559+#define Cache_Mode_0 0x2120
7560+#define CM0_MASK_SHIFT 16
7561+#define CM0_IZ_OPT_DISABLE (1<<6)
7562+#define CM0_ZR_OPT_DISABLE (1<<5)
7563+#define CM0_DEPTH_EVICT_DISABLE (1<<4)
7564+#define CM0_COLOR_EVICT_DISABLE (1<<3)
7565+#define CM0_DEPTH_WRITE_DISABLE (1<<1)
7566+#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
7567+
7568+
7569+/* Graphics flush control. A CPU write flushes the GWB of all writes.
7570+ * The data is discarded.
7571+ */
7572+#define GFX_FLSH_CNTL 0x2170
7573+
7574+/* Binner control. Defines the location of the bin pointer list:
7575+ */
7576+#define BINCTL 0x2420
7577+#define BC_MASK (1 << 9)
7578+
7579+/* Binned scene info.
7580+ */
7581+#define BINSCENE 0x2428
7582+#define BS_OP_LOAD (1 << 8)
7583+#define BS_MASK (1 << 22)
7584+
7585+/* Bin command parser debug reg:
7586+ */
7587+#define BCPD 0x2480
7588+
7589+/* Bin memory control debug reg:
7590+ */
7591+#define BMCD 0x2484
7592+
7593+/* Bin data cache debug reg:
7594+ */
7595+#define BDCD 0x2488
7596+
7597+/* Binner pointer cache debug reg:
7598+ */
7599+#define BPCD 0x248c
7600+
7601+/* Binner scratch pad debug reg:
7602+ */
7603+#define BINSKPD 0x24f0
7604+
7605+/* HWB scratch pad debug reg:
7606+ */
7607+#define HWBSKPD 0x24f4
7608+
7609+/* Binner memory pool reg:
7610+ */
7611+#define BMP_BUFFER 0x2430
7612+#define BMP_PAGE_SIZE_4K (0 << 10)
7613+#define BMP_BUFFER_SIZE_SHIFT 1
7614+#define BMP_ENABLE (1 << 0)
7615+
7616+/* Get/put memory from the binner memory pool:
7617+ */
7618+#define BMP_GET 0x2438
7619+#define BMP_PUT 0x2440
7620+#define BMP_OFFSET_SHIFT 5
7621+
7622+/* 3D state packets:
7623+ */
7624+#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
7625+
7626+#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
7627+#define SC_UPDATE_SCISSOR (0x1<<1)
7628+#define SC_ENABLE_MASK (0x1<<0)
7629+#define SC_ENABLE (0x1<<0)
7630+
7631+#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
7632+
7633+#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
7634+#define SCI_YMIN_MASK (0xffff<<16)
7635+#define SCI_XMIN_MASK (0xffff<<0)
7636+#define SCI_YMAX_MASK (0xffff<<16)
7637+#define SCI_XMAX_MASK (0xffff<<0)
7638+
7639+#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
7640+#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
7641+#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
7642+#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
7643+#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
7644+#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
7645+#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
7646+
7647+#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
7648+
7649+#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
7650+#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
7651+#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
7652+#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
7653+#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
7654+#define BLT_DEPTH_8 (0<<24)
7655+#define BLT_DEPTH_16_565 (1<<24)
7656+#define BLT_DEPTH_16_1555 (2<<24)
7657+#define BLT_DEPTH_32 (3<<24)
7658+#define BLT_ROP_GXCOPY (0xcc<<16)
7659+
7660+#define MI_BATCH_BUFFER ((0x30<<23)|1)
7661+#define MI_BATCH_BUFFER_START (0x31<<23)
7662+#define MI_BATCH_BUFFER_END (0xA<<23)
7663+#define MI_BATCH_NON_SECURE (1)
7664+
7665+#define MI_BATCH_NON_SECURE_I965 (1<<8)
7666+
7667+#define MI_WAIT_FOR_EVENT ((0x3<<23))
7668+#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
7669+#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
7670+#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
7671+
7672+#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
7673+
7674+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
7675+#define ASYNC_FLIP (1<<22)
7676+#define DISPLAY_PLANE_A (0<<20)
7677+#define DISPLAY_PLANE_B (1<<20)
7678+
7679+/* Display regs */
7680+#define DSPACNTR 0x70180
7681+#define DSPBCNTR 0x71180
7682+#define DISPPLANE_SEL_PIPE_MASK (1<<24)
7683+
7684+/* Define the region of interest for the binner:
7685+ */
7686+#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
7687+
7688+#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
7689+
7690+#define BREADCRUMB_BITS 31
7691+#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
7692+
7693+#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
7694+#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
7695+
7696+#define PRIMARY_RINGBUFFER_SIZE (128*1024)
7697+
7698+#endif
7699Index: git/shared-core/i915_irq.c
7700===================================================================
7701--- /dev/null 1970-01-01 00:00:00.000000000 +0000
7702+++ git/shared-core/i915_irq.c 2008-12-12 17:35:22.000000000 +0000
7703@@ -0,0 +1,752 @@
7704+/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
7705+ */
7706+/*
7707+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7708+ * All Rights Reserved.
7709+ *
7710+ * Permission is hereby granted, free of charge, to any person obtaining a
7711+ * copy of this software and associated documentation files (the
7712+ * "Software"), to deal in the Software without restriction, including
7713+ * without limitation the rights to use, copy, modify, merge, publish,
7714+ * distribute, sub license, and/or sell copies of the Software, and to
7715+ * permit persons to whom the Software is furnished to do so, subject to
7716+ * the following conditions:
7717+ *
7718+ * The above copyright notice and this permission notice (including the
7719+ * next paragraph) shall be included in all copies or substantial portions
7720+ * of the Software.
7721+ *
7722+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
7723+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
7724+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
7725+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
7726+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
7727+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
7728+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
7729+ *
7730+ */
7731+
7732+#include "drmP.h"
7733+#include "drm.h"
7734+#include "i915_drm.h"
7735+#include "i915_drv.h"
7736+
7737+#define USER_INT_FLAG (1<<1)
7738+#define VSYNC_PIPEB_FLAG (1<<5)
7739+#define VSYNC_PIPEA_FLAG (1<<7)
7740+
7741+#define MAX_NOPID ((u32)~0)
7742+
7743+/**
7744+ * i915_get_pipe - return the the pipe associated with a given plane
7745+ * @dev: DRM device
7746+ * @plane: plane to look for
7747+ *
7748+ * We need to get the pipe associated with a given plane to correctly perform
7749+ * vblank driven swapping, and they may not always be equal. So look up the
7750+ * pipe associated with @plane here.
7751+ */
7752+static int
7753+i915_get_pipe(struct drm_device *dev, int plane)
7754+{
7755+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7756+ u32 dspcntr;
7757+
7758+ dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
7759+
7760+ return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
7761+}
7762+
7763+/**
7764+ * Emit a synchronous flip.
7765+ *
7766+ * This function must be called with the drawable spinlock held.
7767+ */
7768+static void
7769+i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
7770+ int plane)
7771+{
7772+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7773+ drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
7774+ u16 x1, y1, x2, y2;
7775+ int pf_planes = 1 << plane;
7776+
7777+ DRM_SPINLOCK_ASSERT(&dev->drw_lock);
7778+
7779+ /* If the window is visible on the other plane, we have to flip on that
7780+ * plane as well.
7781+ */
7782+ if (plane == 1) {
7783+ x1 = sarea_priv->planeA_x;
7784+ y1 = sarea_priv->planeA_y;
7785+ x2 = x1 + sarea_priv->planeA_w;
7786+ y2 = y1 + sarea_priv->planeA_h;
7787+ } else {
7788+ x1 = sarea_priv->planeB_x;
7789+ y1 = sarea_priv->planeB_y;
7790+ x2 = x1 + sarea_priv->planeB_w;
7791+ y2 = y1 + sarea_priv->planeB_h;
7792+ }
7793+
7794+ if (x2 > 0 && y2 > 0) {
7795+ int i, num_rects = drw->num_rects;
7796+ struct drm_clip_rect *rect = drw->rects;
7797+
7798+ for (i = 0; i < num_rects; i++)
7799+ if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
7800+ rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
7801+ pf_planes = 0x3;
7802+
7803+ break;
7804+ }
7805+ }
7806+
7807+ i915_dispatch_flip(dev, pf_planes, 1);
7808+}
7809+
7810+/**
7811+ * Emit blits for scheduled buffer swaps.
7812+ *
7813+ * This function will be called with the HW lock held.
7814+ */
7815+static void i915_vblank_tasklet(struct drm_device *dev)
7816+{
7817+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7818+ struct list_head *list, *tmp, hits, *hit;
7819+ int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
7820+ unsigned counter[2] = { atomic_read(&dev->vbl_received),
7821+ atomic_read(&dev->vbl_received2) };
7822+ struct drm_drawable_info *drw;
7823+ drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
7824+ u32 cpp = dev_priv->cpp, offsets[3];
7825+ u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
7826+ XY_SRC_COPY_BLT_WRITE_ALPHA |
7827+ XY_SRC_COPY_BLT_WRITE_RGB)
7828+ : XY_SRC_COPY_BLT_CMD;
7829+ u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
7830+ (cpp << 23) | (1 << 24);
7831+ RING_LOCALS;
7832+
7833+ DRM_DEBUG("\n");
7834+
7835+ INIT_LIST_HEAD(&hits);
7836+
7837+ nhits = nrects = 0;
7838+
7839+ /* No irqsave/restore necessary. This tasklet may be run in an
7840+ * interrupt context or normal context, but we don't have to worry
7841+ * about getting interrupted by something acquiring the lock, because
7842+ * we are the interrupt context thing that acquires the lock.
7843+ */
7844+ DRM_SPINLOCK(&dev_priv->swaps_lock);
7845+
7846+ /* Find buffer swaps scheduled for this vertical blank */
7847+ list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
7848+ drm_i915_vbl_swap_t *vbl_swap =
7849+ list_entry(list, drm_i915_vbl_swap_t, head);
7850+ int pipe = i915_get_pipe(dev, vbl_swap->plane);
7851+
7852+ if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
7853+ continue;
7854+
7855+ list_del(list);
7856+ dev_priv->swaps_pending--;
7857+
7858+ DRM_SPINUNLOCK(&dev_priv->swaps_lock);
7859+ DRM_SPINLOCK(&dev->drw_lock);
7860+
7861+ drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
7862+
7863+ if (!drw) {
7864+ DRM_SPINUNLOCK(&dev->drw_lock);
7865+ drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
7866+ DRM_SPINLOCK(&dev_priv->swaps_lock);
7867+ continue;
7868+ }
7869+
7870+ list_for_each(hit, &hits) {
7871+ drm_i915_vbl_swap_t *swap_cmp =
7872+ list_entry(hit, drm_i915_vbl_swap_t, head);
7873+ struct drm_drawable_info *drw_cmp =
7874+ drm_get_drawable_info(dev, swap_cmp->drw_id);
7875+
7876+ if (drw_cmp &&
7877+ drw_cmp->rects[0].y1 > drw->rects[0].y1) {
7878+ list_add_tail(list, hit);
7879+ break;
7880+ }
7881+ }
7882+
7883+ DRM_SPINUNLOCK(&dev->drw_lock);
7884+
7885+ /* List of hits was empty, or we reached the end of it */
7886+ if (hit == &hits)
7887+ list_add_tail(list, hits.prev);
7888+
7889+ nhits++;
7890+
7891+ DRM_SPINLOCK(&dev_priv->swaps_lock);
7892+ }
7893+
7894+ DRM_SPINUNLOCK(&dev->drw_lock);
7895+
7896+ if (nhits == 0) {
7897+ return;
7898+ }
7899+
7900+ i915_kernel_lost_context(dev);
7901+
7902+ upper[0] = upper[1] = 0;
7903+ slice[0] = max(sarea_priv->planeA_h / nhits, 1);
7904+ slice[1] = max(sarea_priv->planeB_h / nhits, 1);
7905+ lower[0] = sarea_priv->planeA_y + slice[0];
7906+ lower[1] = sarea_priv->planeB_y + slice[0];
7907+
7908+ offsets[0] = sarea_priv->front_offset;
7909+ offsets[1] = sarea_priv->back_offset;
7910+ offsets[2] = sarea_priv->third_offset;
7911+ num_pages = sarea_priv->third_handle ? 3 : 2;
7912+
7913+ DRM_SPINLOCK(&dev->drw_lock);
7914+
7915+ /* Emit blits for buffer swaps, partitioning both outputs into as many
7916+ * slices as there are buffer swaps scheduled in order to avoid tearing
7917+ * (based on the assumption that a single buffer swap would always
7918+ * complete before scanout starts).
7919+ */
7920+ for (i = 0; i++ < nhits;
7921+ upper[0] = lower[0], lower[0] += slice[0],
7922+ upper[1] = lower[1], lower[1] += slice[1]) {
7923+ int init_drawrect = 1;
7924+
7925+ if (i == nhits)
7926+ lower[0] = lower[1] = sarea_priv->height;
7927+
7928+ list_for_each(hit, &hits) {
7929+ drm_i915_vbl_swap_t *swap_hit =
7930+ list_entry(hit, drm_i915_vbl_swap_t, head);
7931+ struct drm_clip_rect *rect;
7932+ int num_rects, plane, front, back;
7933+ unsigned short top, bottom;
7934+
7935+ drw = drm_get_drawable_info(dev, swap_hit->drw_id);
7936+
7937+ if (!drw)
7938+ continue;
7939+
7940+ plane = swap_hit->plane;
7941+
7942+ if (swap_hit->flip) {
7943+ i915_dispatch_vsync_flip(dev, drw, plane);
7944+ continue;
7945+ }
7946+
7947+ if (init_drawrect) {
7948+ BEGIN_LP_RING(6);
7949+
7950+ OUT_RING(GFX_OP_DRAWRECT_INFO);
7951+ OUT_RING(0);
7952+ OUT_RING(0);
7953+ OUT_RING(sarea_priv->width | sarea_priv->height << 16);
7954+ OUT_RING(sarea_priv->width | sarea_priv->height << 16);
7955+ OUT_RING(0);
7956+
7957+ ADVANCE_LP_RING();
7958+
7959+ sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
7960+
7961+ init_drawrect = 0;
7962+ }
7963+
7964+ rect = drw->rects;
7965+ top = upper[plane];
7966+ bottom = lower[plane];
7967+
7968+ front = (dev_priv->sarea_priv->pf_current_page >>
7969+ (2 * plane)) & 0x3;
7970+ back = (front + 1) % num_pages;
7971+
7972+ for (num_rects = drw->num_rects; num_rects--; rect++) {
7973+ int y1 = max(rect->y1, top);
7974+ int y2 = min(rect->y2, bottom);
7975+
7976+ if (y1 >= y2)
7977+ continue;
7978+
7979+ BEGIN_LP_RING(8);
7980+
7981+ OUT_RING(cmd);
7982+ OUT_RING(pitchropcpp);
7983+ OUT_RING((y1 << 16) | rect->x1);
7984+ OUT_RING((y2 << 16) | rect->x2);
7985+ OUT_RING(offsets[front]);
7986+ OUT_RING((y1 << 16) | rect->x1);
7987+ OUT_RING(pitchropcpp & 0xffff);
7988+ OUT_RING(offsets[back]);
7989+
7990+ ADVANCE_LP_RING();
7991+ }
7992+ }
7993+ }
7994+
7995+ DRM_SPINUNLOCK(&dev->drw_lock);
7996+
7997+ list_for_each_safe(hit, tmp, &hits) {
7998+ drm_i915_vbl_swap_t *swap_hit =
7999+ list_entry(hit, drm_i915_vbl_swap_t, head);
8000+
8001+ list_del(hit);
8002+
8003+ drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
8004+ }
8005+}
8006+
8007+irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
8008+{
8009+ struct drm_device *dev = (struct drm_device *) arg;
8010+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8011+ u16 temp;
8012+ u32 pipea_stats, pipeb_stats;
8013+
8014+ pipea_stats = I915_READ(I915REG_PIPEASTAT);
8015+ pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
8016+
8017+ temp = I915_READ16(I915REG_INT_IDENTITY_R);
8018+ temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
8019+
8020+#if 0
8021+ DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
8022+#endif
8023+ if (temp == 0)
8024+ return IRQ_NONE;
8025+
8026+ I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
8027+ (void) I915_READ16(I915REG_INT_IDENTITY_R);
8028+ DRM_READMEMORYBARRIER();
8029+
8030+ dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
8031+
8032+ if (temp & USER_INT_FLAG) {
8033+ DRM_WAKEUP(&dev_priv->irq_queue);
8034+#ifdef I915_HAVE_FENCE
8035+ i915_fence_handler(dev);
8036+#endif
8037+ }
8038+
8039+ if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
8040+ int vblank_pipe = dev_priv->vblank_pipe;
8041+
8042+ if ((vblank_pipe &
8043+ (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
8044+ == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
8045+ if (temp & VSYNC_PIPEA_FLAG)
8046+ atomic_inc(&dev->vbl_received);
8047+ if (temp & VSYNC_PIPEB_FLAG)
8048+ atomic_inc(&dev->vbl_received2);
8049+ } else if (((temp & VSYNC_PIPEA_FLAG) &&
8050+ (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
8051+ ((temp & VSYNC_PIPEB_FLAG) &&
8052+ (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
8053+ atomic_inc(&dev->vbl_received);
8054+
8055+ DRM_WAKEUP(&dev->vbl_queue);
8056+ drm_vbl_send_signals(dev);
8057+
8058+ if (dev_priv->swaps_pending > 0)
8059+ drm_locked_tasklet(dev, i915_vblank_tasklet);
8060+ I915_WRITE(I915REG_PIPEASTAT,
8061+ pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
8062+ I915_VBLANK_CLEAR);
8063+ I915_WRITE(I915REG_PIPEBSTAT,
8064+ pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
8065+ I915_VBLANK_CLEAR);
8066+ }
8067+
8068+ return IRQ_HANDLED;
8069+}
8070+
8071+int i915_emit_irq(struct drm_device * dev)
8072+{
8073+
8074+ drm_i915_private_t *dev_priv = dev->dev_private;
8075+ RING_LOCALS;
8076+
8077+ i915_kernel_lost_context(dev);
8078+
8079+ DRM_DEBUG("%s\n", __FUNCTION__);
8080+
8081+ i915_emit_breadcrumb(dev);
8082+
8083+ BEGIN_LP_RING(2);
8084+ OUT_RING(0);
8085+ OUT_RING(GFX_OP_USER_INTERRUPT);
8086+ ADVANCE_LP_RING();
8087+
8088+ return dev_priv->counter;
8089+
8090+
8091+}
8092+
8093+void i915_user_irq_on(drm_i915_private_t *dev_priv)
8094+{
8095+ DRM_SPINLOCK(&dev_priv->user_irq_lock);
8096+ if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
8097+ dev_priv->irq_enable_reg |= USER_INT_FLAG;
8098+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
8099+ }
8100+ DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
8101+
8102+}
8103+
8104+void i915_user_irq_off(drm_i915_private_t *dev_priv)
8105+{
8106+ DRM_SPINLOCK(&dev_priv->user_irq_lock);
8107+ if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
8108+ // dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
8109+ // I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
8110+ }
8111+ DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
8112+}
8113+
8114+
8115+static int i915_wait_irq(struct drm_device * dev, int irq_nr)
8116+{
8117+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8118+ int ret = 0;
8119+
8120+ DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr,
8121+ READ_BREADCRUMB(dev_priv));
8122+
8123+ if (READ_BREADCRUMB(dev_priv) >= irq_nr)
8124+ return 0;
8125+
8126+ dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
8127+
8128+ i915_user_irq_on(dev_priv);
8129+ DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
8130+ READ_BREADCRUMB(dev_priv) >= irq_nr);
8131+ i915_user_irq_off(dev_priv);
8132+
8133+ if (ret == -EBUSY) {
8134+ DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n",
8135+ __FUNCTION__,
8136+ READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
8137+ }
8138+
8139+ dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
8140+ return ret;
8141+}
8142+
8143+static int i915_driver_vblank_do_wait(struct drm_device *dev,
8144+ unsigned int *sequence,
8145+ atomic_t *counter)
8146+{
8147+ drm_i915_private_t *dev_priv = dev->dev_private;
8148+ unsigned int cur_vblank;
8149+ int ret = 0;
8150+
8151+ if (!dev_priv) {
8152+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8153+ return -EINVAL;
8154+ }
8155+
8156+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
8157+ (((cur_vblank = atomic_read(counter))
8158+ - *sequence) <= (1<<23)));
8159+
8160+ *sequence = cur_vblank;
8161+
8162+ return ret;
8163+}
8164+
8165+int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
8166+{
8167+ return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
8168+}
8169+
8170+int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
8171+{
8172+ return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
8173+}
8174+
8175+/* Needs the lock as it touches the ring.
8176+ */
8177+int i915_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
8178+{
8179+ drm_i915_private_t *dev_priv = dev->dev_private;
8180+ drm_i915_irq_emit_t *emit = data;
8181+ int result;
8182+
8183+ LOCK_TEST_WITH_RETURN(dev, file_priv);
8184+
8185+ if (!dev_priv) {
8186+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8187+ return -EINVAL;
8188+ }
8189+
8190+ result = i915_emit_irq(dev);
8191+
8192+ if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
8193+ DRM_ERROR("copy_to_user\n");
8194+ return -EFAULT;
8195+ }
8196+
8197+ return 0;
8198+}
8199+
8200+/* Doesn't need the hardware lock.
8201+ */
8202+int i915_irq_wait(struct drm_device *dev, void *data,
8203+ struct drm_file *file_priv)
8204+{
8205+ drm_i915_private_t *dev_priv = dev->dev_private;
8206+ drm_i915_irq_wait_t *irqwait = data;
8207+
8208+ if (!dev_priv) {
8209+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8210+ return -EINVAL;
8211+ }
8212+
8213+ return i915_wait_irq(dev, irqwait->irq_seq);
8214+}
8215+
8216+static void i915_enable_interrupt (struct drm_device *dev)
8217+{
8218+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8219+
8220+ dev_priv->irq_enable_reg = USER_INT_FLAG;
8221+ if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
8222+ dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
8223+ if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
8224+ dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
8225+
8226+ I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
8227+ dev_priv->irq_enabled = 1;
8228+}
8229+
8230+/* Set the vblank monitor pipe
8231+ */
8232+int i915_vblank_pipe_set(struct drm_device *dev, void *data,
8233+ struct drm_file *file_priv)
8234+{
8235+ drm_i915_private_t *dev_priv = dev->dev_private;
8236+ drm_i915_vblank_pipe_t *pipe = data;
8237+
8238+ if (!dev_priv) {
8239+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8240+ return -EINVAL;
8241+ }
8242+
8243+ if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
8244+ DRM_ERROR("%s called with invalid pipe 0x%x\n",
8245+ __FUNCTION__, pipe->pipe);
8246+ return -EINVAL;
8247+ }
8248+
8249+ dev_priv->vblank_pipe = pipe->pipe;
8250+
8251+ i915_enable_interrupt (dev);
8252+
8253+ return 0;
8254+}
8255+
8256+int i915_vblank_pipe_get(struct drm_device *dev, void *data,
8257+ struct drm_file *file_priv)
8258+{
8259+ drm_i915_private_t *dev_priv = dev->dev_private;
8260+ drm_i915_vblank_pipe_t *pipe = data;
8261+ u16 flag;
8262+
8263+ if (!dev_priv) {
8264+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8265+ return -EINVAL;
8266+ }
8267+
8268+ flag = I915_READ(I915REG_INT_ENABLE_R);
8269+ pipe->pipe = 0;
8270+ if (flag & VSYNC_PIPEA_FLAG)
8271+ pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
8272+ if (flag & VSYNC_PIPEB_FLAG)
8273+ pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
8274+
8275+ return 0;
8276+}
8277+
8278+/**
8279+ * Schedule buffer swap at given vertical blank.
8280+ */
8281+int i915_vblank_swap(struct drm_device *dev, void *data,
8282+ struct drm_file *file_priv)
8283+{
8284+ drm_i915_private_t *dev_priv = dev->dev_private;
8285+ drm_i915_vblank_swap_t *swap = data;
8286+ drm_i915_vbl_swap_t *vbl_swap;
8287+ unsigned int pipe, seqtype, curseq, plane;
8288+ unsigned long irqflags;
8289+ struct list_head *list;
8290+
8291+ if (!dev_priv) {
8292+ DRM_ERROR("%s called with no initialization\n", __func__);
8293+ return -EINVAL;
8294+ }
8295+
8296+ if (dev_priv->sarea_priv->rotation) {
8297+ DRM_DEBUG("Rotation not supported\n");
8298+ return -EINVAL;
8299+ }
8300+
8301+ if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
8302+ _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
8303+ _DRM_VBLANK_FLIP)) {
8304+ DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
8305+ return -EINVAL;
8306+ }
8307+
8308+ plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
8309+ pipe = i915_get_pipe(dev, plane);
8310+
8311+ seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
8312+
8313+ if (!(dev_priv->vblank_pipe & (1 << pipe))) {
8314+ DRM_ERROR("Invalid pipe %d\n", pipe);
8315+ return -EINVAL;
8316+ }
8317+
8318+ curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
8319+
8320+ if (seqtype == _DRM_VBLANK_RELATIVE)
8321+ swap->sequence += curseq;
8322+
8323+ if ((curseq - swap->sequence) <= (1<<23)) {
8324+ if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
8325+ swap->sequence = curseq + 1;
8326+ } else {
8327+ DRM_DEBUG("Missed target sequence\n");
8328+ return -EINVAL;
8329+ }
8330+ }
8331+
8332+ if (swap->seqtype & _DRM_VBLANK_FLIP) {
8333+ swap->sequence--;
8334+
8335+ if ((curseq - swap->sequence) <= (1<<23)) {
8336+ struct drm_drawable_info *drw;
8337+
8338+ LOCK_TEST_WITH_RETURN(dev, file_priv);
8339+
8340+ DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
8341+
8342+ drw = drm_get_drawable_info(dev, swap->drawable);
8343+
8344+ if (!drw) {
8345+ DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
8346+ irqflags);
8347+ DRM_DEBUG("Invalid drawable ID %d\n",
8348+ swap->drawable);
8349+ return -EINVAL;
8350+ }
8351+
8352+ i915_dispatch_vsync_flip(dev, drw, plane);
8353+
8354+ DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
8355+
8356+ return 0;
8357+ }
8358+ }
8359+
8360+ DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
8361+
8362+ list_for_each(list, &dev_priv->vbl_swaps.head) {
8363+ vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
8364+
8365+ if (vbl_swap->drw_id == swap->drawable &&
8366+ vbl_swap->plane == plane &&
8367+ vbl_swap->sequence == swap->sequence) {
8368+ vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
8369+ DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
8370+ DRM_DEBUG("Already scheduled\n");
8371+ return 0;
8372+ }
8373+ }
8374+
8375+ DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
8376+
8377+ if (dev_priv->swaps_pending >= 100) {
8378+ DRM_DEBUG("Too many swaps queued\n");
8379+ return -EBUSY;
8380+ }
8381+
8382+ vbl_swap = drm_calloc(1, sizeof(vbl_swap), DRM_MEM_DRIVER);
8383+
8384+ if (!vbl_swap) {
8385+ DRM_ERROR("Failed to allocate memory to queue swap\n");
8386+ return -ENOMEM;
8387+ }
8388+
8389+ DRM_DEBUG("\n");
8390+
8391+ vbl_swap->drw_id = swap->drawable;
8392+ vbl_swap->plane = plane;
8393+ vbl_swap->sequence = swap->sequence;
8394+ vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
8395+
8396+ if (vbl_swap->flip)
8397+ swap->sequence++;
8398+
8399+ DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
8400+
8401+ list_add_tail((struct list_head *)vbl_swap, &dev_priv->vbl_swaps.head);
8402+ dev_priv->swaps_pending++;
8403+
8404+ DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
8405+
8406+ return 0;
8407+}
8408+
8409+/* drm_dma.h hooks
8410+*/
8411+void i915_driver_irq_preinstall(struct drm_device * dev)
8412+{
8413+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8414+
8415+ I915_WRITE16(I915REG_HWSTAM, 0xeffe);
8416+ I915_WRITE16(I915REG_INT_MASK_R, 0x0);
8417+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
8418+}
8419+
8420+void i915_driver_irq_postinstall(struct drm_device * dev)
8421+{
8422+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8423+
8424+ DRM_SPININIT(&dev_priv->swaps_lock, "swap");
8425+ INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
8426+ dev_priv->swaps_pending = 0;
8427+
8428+ DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
8429+ dev_priv->user_irq_refcount = 0;
8430+
8431+ i915_enable_interrupt(dev);
8432+ DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
8433+
8434+ /*
8435+ * Initialize the hardware status page IRQ location.
8436+ */
8437+
8438+ I915_WRITE(I915REG_INSTPM, ( 1 << 5) | ( 1 << 21));
8439+}
8440+
8441+void i915_driver_irq_uninstall(struct drm_device * dev)
8442+{
8443+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8444+ u16 temp;
8445+ if (!dev_priv)
8446+ return;
8447+
8448+ dev_priv->irq_enabled = 0;
8449+ I915_WRITE16(I915REG_HWSTAM, 0xffff);
8450+ I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
8451+ I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
8452+
8453+ temp = I915_READ16(I915REG_INT_IDENTITY_R);
8454+ I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
8455+}
8456Index: git/shared-core/i915_mem.c
8457===================================================================
8458--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8459+++ git/shared-core/i915_mem.c 2008-12-12 17:35:22.000000000 +0000
8460@@ -0,0 +1,386 @@
8461+/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
8462+ */
8463+/*
8464+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8465+ * All Rights Reserved.
8466+ *
8467+ * Permission is hereby granted, free of charge, to any person obtaining a
8468+ * copy of this software and associated documentation files (the
8469+ * "Software"), to deal in the Software without restriction, including
8470+ * without limitation the rights to use, copy, modify, merge, publish,
8471+ * distribute, sub license, and/or sell copies of the Software, and to
8472+ * permit persons to whom the Software is furnished to do so, subject to
8473+ * the following conditions:
8474+ *
8475+ * The above copyright notice and this permission notice (including the
8476+ * next paragraph) shall be included in all copies or substantial portions
8477+ * of the Software.
8478+ *
8479+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
8480+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
8481+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
8482+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
8483+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
8484+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
8485+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
8486+ *
8487+ */
8488+
8489+#include "drmP.h"
8490+#include "drm.h"
8491+#include "i915_drm.h"
8492+#include "i915_drv.h"
8493+
8494+/* This memory manager is integrated into the global/local lru
8495+ * mechanisms used by the clients. Specifically, it operates by
8496+ * setting the 'in_use' fields of the global LRU to indicate whether
8497+ * this region is privately allocated to a client.
8498+ *
8499+ * This does require the client to actually respect that field.
8500+ *
8501+ * Currently no effort is made to allocate 'private' memory in any
8502+ * clever way - the LRU information isn't used to determine which
8503+ * block to allocate, and the ring is drained prior to allocations --
8504+ * in other words allocation is expensive.
8505+ */
8506+static void mark_block(struct drm_device * dev, struct mem_block *p, int in_use)
8507+{
8508+ drm_i915_private_t *dev_priv = dev->dev_private;
8509+ drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
8510+ struct drm_tex_region *list;
8511+ unsigned shift, nr;
8512+ unsigned start;
8513+ unsigned end;
8514+ unsigned i;
8515+ int age;
8516+
8517+ shift = dev_priv->tex_lru_log_granularity;
8518+ nr = I915_NR_TEX_REGIONS;
8519+
8520+ start = p->start >> shift;
8521+ end = (p->start + p->size - 1) >> shift;
8522+
8523+ age = ++sarea_priv->texAge;
8524+ list = sarea_priv->texList;
8525+
8526+ /* Mark the regions with the new flag and update their age. Move
8527+ * them to head of list to preserve LRU semantics.
8528+ */
8529+ for (i = start; i <= end; i++) {
8530+ list[i].in_use = in_use;
8531+ list[i].age = age;
8532+
8533+ /* remove_from_list(i)
8534+ */
8535+ list[(unsigned)list[i].next].prev = list[i].prev;
8536+ list[(unsigned)list[i].prev].next = list[i].next;
8537+
8538+ /* insert_at_head(list, i)
8539+ */
8540+ list[i].prev = nr;
8541+ list[i].next = list[nr].next;
8542+ list[(unsigned)list[nr].next].prev = i;
8543+ list[nr].next = i;
8544+ }
8545+}
8546+
8547+/* Very simple allocator for agp memory, working on a static range
8548+ * already mapped into each client's address space.
8549+ */
8550+
8551+static struct mem_block *split_block(struct mem_block *p, int start, int size,
8552+ struct drm_file *file_priv)
8553+{
8554+ /* Maybe cut off the start of an existing block */
8555+ if (start > p->start) {
8556+ struct mem_block *newblock =
8557+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
8558+ if (!newblock)
8559+ goto out;
8560+ newblock->start = start;
8561+ newblock->size = p->size - (start - p->start);
8562+ newblock->file_priv = NULL;
8563+ newblock->next = p->next;
8564+ newblock->prev = p;
8565+ p->next->prev = newblock;
8566+ p->next = newblock;
8567+ p->size -= newblock->size;
8568+ p = newblock;
8569+ }
8570+
8571+ /* Maybe cut off the end of an existing block */
8572+ if (size < p->size) {
8573+ struct mem_block *newblock =
8574+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
8575+ if (!newblock)
8576+ goto out;
8577+ newblock->start = start + size;
8578+ newblock->size = p->size - size;
8579+ newblock->file_priv = NULL;
8580+ newblock->next = p->next;
8581+ newblock->prev = p;
8582+ p->next->prev = newblock;
8583+ p->next = newblock;
8584+ p->size = size;
8585+ }
8586+
8587+ out:
8588+ /* Our block is in the middle */
8589+ p->file_priv = file_priv;
8590+ return p;
8591+}
8592+
8593+static struct mem_block *alloc_block(struct mem_block *heap, int size,
8594+ int align2, struct drm_file *file_priv)
8595+{
8596+ struct mem_block *p;
8597+ int mask = (1 << align2) - 1;
8598+
8599+ for (p = heap->next; p != heap; p = p->next) {
8600+ int start = (p->start + mask) & ~mask;
8601+ if (p->file_priv == NULL && start + size <= p->start + p->size)
8602+ return split_block(p, start, size, file_priv);
8603+ }
8604+
8605+ return NULL;
8606+}
8607+
8608+static struct mem_block *find_block(struct mem_block *heap, int start)
8609+{
8610+ struct mem_block *p;
8611+
8612+ for (p = heap->next; p != heap; p = p->next)
8613+ if (p->start == start)
8614+ return p;
8615+
8616+ return NULL;
8617+}
8618+
8619+static void free_block(struct mem_block *p)
8620+{
8621+ p->file_priv = NULL;
8622+
8623+ /* Assumes a single contiguous range. Needs a special file_priv in
8624+ * 'heap' to stop it being subsumed.
8625+ */
8626+ if (p->next->file_priv == NULL) {
8627+ struct mem_block *q = p->next;
8628+ p->size += q->size;
8629+ p->next = q->next;
8630+ p->next->prev = p;
8631+ drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS);
8632+ }
8633+
8634+ if (p->prev->file_priv == NULL) {
8635+ struct mem_block *q = p->prev;
8636+ q->size += p->size;
8637+ q->next = p->next;
8638+ q->next->prev = q;
8639+ drm_free(p, sizeof(*q), DRM_MEM_BUFLISTS);
8640+ }
8641+}
8642+
8643+/* Initialize. How to check for an uninitialized heap?
8644+ */
8645+static int init_heap(struct mem_block **heap, int start, int size)
8646+{
8647+ struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFLISTS);
8648+
8649+ if (!blocks)
8650+ return -ENOMEM;
8651+
8652+ *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFLISTS);
8653+ if (!*heap) {
8654+ drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFLISTS);
8655+ return -ENOMEM;
8656+ }
8657+
8658+ blocks->start = start;
8659+ blocks->size = size;
8660+ blocks->file_priv = NULL;
8661+ blocks->next = blocks->prev = *heap;
8662+
8663+ memset(*heap, 0, sizeof(**heap));
8664+ (*heap)->file_priv = (struct drm_file *) - 1;
8665+ (*heap)->next = (*heap)->prev = blocks;
8666+ return 0;
8667+}
8668+
8669+/* Free all blocks associated with the releasing file.
8670+ */
8671+void i915_mem_release(struct drm_device * dev, struct drm_file *file_priv,
8672+ struct mem_block *heap)
8673+{
8674+ struct mem_block *p;
8675+
8676+ if (!heap || !heap->next)
8677+ return;
8678+
8679+ for (p = heap->next; p != heap; p = p->next) {
8680+ if (p->file_priv == file_priv) {
8681+ p->file_priv = NULL;
8682+ mark_block(dev, p, 0);
8683+ }
8684+ }
8685+
8686+ /* Assumes a single contiguous range. Needs a special file_priv in
8687+ * 'heap' to stop it being subsumed.
8688+ */
8689+ for (p = heap->next; p != heap; p = p->next) {
8690+ while (p->file_priv == NULL && p->next->file_priv == NULL) {
8691+ struct mem_block *q = p->next;
8692+ p->size += q->size;
8693+ p->next = q->next;
8694+ p->next->prev = p;
8695+ drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS);
8696+ }
8697+ }
8698+}
8699+
8700+/* Shutdown.
8701+ */
8702+void i915_mem_takedown(struct mem_block **heap)
8703+{
8704+ struct mem_block *p;
8705+
8706+ if (!*heap)
8707+ return;
8708+
8709+ for (p = (*heap)->next; p != *heap;) {
8710+ struct mem_block *q = p;
8711+ p = p->next;
8712+ drm_free(q, sizeof(*q), DRM_MEM_BUFLISTS);
8713+ }
8714+
8715+ drm_free(*heap, sizeof(**heap), DRM_MEM_BUFLISTS);
8716+ *heap = NULL;
8717+}
8718+
8719+static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region)
8720+{
8721+ switch (region) {
8722+ case I915_MEM_REGION_AGP:
8723+ return &dev_priv->agp_heap;
8724+ default:
8725+ return NULL;
8726+ }
8727+}
8728+
8729+/* IOCTL HANDLERS */
8730+
8731+int i915_mem_alloc(struct drm_device *dev, void *data,
8732+ struct drm_file *file_priv)
8733+{
8734+ drm_i915_private_t *dev_priv = dev->dev_private;
8735+ drm_i915_mem_alloc_t *alloc = data;
8736+ struct mem_block *block, **heap;
8737+
8738+ if (!dev_priv) {
8739+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8740+ return -EINVAL;
8741+ }
8742+
8743+ heap = get_heap(dev_priv, alloc->region);
8744+ if (!heap || !*heap)
8745+ return -EFAULT;
8746+
8747+ /* Make things easier on ourselves: all allocations at least
8748+ * 4k aligned.
8749+ */
8750+ if (alloc->alignment < 12)
8751+ alloc->alignment = 12;
8752+
8753+ block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv);
8754+
8755+ if (!block)
8756+ return -ENOMEM;
8757+
8758+ mark_block(dev, block, 1);
8759+
8760+ if (DRM_COPY_TO_USER(alloc->region_offset, &block->start,
8761+ sizeof(int))) {
8762+ DRM_ERROR("copy_to_user\n");
8763+ return -EFAULT;
8764+ }
8765+
8766+ return 0;
8767+}
8768+
8769+int i915_mem_free(struct drm_device *dev, void *data,
8770+ struct drm_file *file_priv)
8771+{
8772+ drm_i915_private_t *dev_priv = dev->dev_private;
8773+ drm_i915_mem_free_t *memfree = data;
8774+ struct mem_block *block, **heap;
8775+
8776+ if (!dev_priv) {
8777+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8778+ return -EINVAL;
8779+ }
8780+
8781+ heap = get_heap(dev_priv, memfree->region);
8782+ if (!heap || !*heap)
8783+ return -EFAULT;
8784+
8785+ block = find_block(*heap, memfree->region_offset);
8786+ if (!block)
8787+ return -EFAULT;
8788+
8789+ if (block->file_priv != file_priv)
8790+ return -EPERM;
8791+
8792+ mark_block(dev, block, 0);
8793+ free_block(block);
8794+ return 0;
8795+}
8796+
8797+int i915_mem_init_heap(struct drm_device *dev, void *data,
8798+ struct drm_file *file_priv)
8799+{
8800+ drm_i915_private_t *dev_priv = dev->dev_private;
8801+ drm_i915_mem_init_heap_t *initheap = data;
8802+ struct mem_block **heap;
8803+
8804+ if (!dev_priv) {
8805+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
8806+ return -EINVAL;
8807+ }
8808+
8809+ heap = get_heap(dev_priv, initheap->region);
8810+ if (!heap)
8811+ return -EFAULT;
8812+
8813+ if (*heap) {
8814+ DRM_ERROR("heap already initialized?");
8815+ return -EFAULT;
8816+ }
8817+
8818+ return init_heap(heap, initheap->start, initheap->size);
8819+}
8820+
8821+int i915_mem_destroy_heap( struct drm_device *dev, void *data,
8822+ struct drm_file *file_priv )
8823+{
8824+ drm_i915_private_t *dev_priv = dev->dev_private;
8825+ drm_i915_mem_destroy_heap_t *destroyheap = data;
8826+ struct mem_block **heap;
8827+
8828+ if ( !dev_priv ) {
8829+ DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
8830+ return -EINVAL;
8831+ }
8832+
8833+ heap = get_heap( dev_priv, destroyheap->region );
8834+ if (!heap) {
8835+ DRM_ERROR("get_heap failed");
8836+ return -EFAULT;
8837+ }
8838+
8839+ if (!*heap) {
8840+ DRM_ERROR("heap not initialized?");
8841+ return -EFAULT;
8842+ }
8843+
8844+ i915_mem_takedown( heap );
8845+ return 0;
8846+}
8847Index: git/shared-core/imagine_drv.h
8848===================================================================
8849--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8850+++ git/shared-core/imagine_drv.h 2008-12-12 17:35:22.000000000 +0000
8851@@ -0,0 +1,43 @@
8852+/*
8853+ * Copyright 2005 Adam Jackson.
8854+ *
8855+ * Permission is hereby granted, free of charge, to any person obtaining a
8856+ * copy of this software and associated documentation files (the "Software"),
8857+ * to deal in the Software without restriction, including without limitation
8858+ * on the rights to use, copy, modify, merge, publish, distribute, sub
8859+ * license, and/or sell copies of the Software, and to permit persons to whom
8860+ * the Software is furnished to do so, subject to the following conditions:
8861+ *
8862+ * The above copyright notice and this permission notice (including the next
8863+ * paragraph) shall be included in all copies or substantial portions of the
8864+ * Software.
8865+ *
8866+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
8867+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
8868+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
8869+ * ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
8870+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
8871+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
8872+ */
8873+
8874+/* derived from tdfx_drv.h */
8875+
8876+#ifndef __IMAGINE_DRV_H__
8877+#define __IMAGINE_DRV_H__
8878+
8879+#define DRIVER_AUTHOR "Adam Jackson"
8880+#define DRIVER_NAME "imagine"
8881+#define DRIVER_DESC "#9 Imagine128 and Ticket 2 Ride"
8882+#define DRIVER_DATE "20050328"
8883+#define DRIVER_MAJOR 0
8884+#define DRIVER_MINOR 0
8885+#define DRIVER_PATCHLEVEL 1
8886+
8887+enum imagine_family {
8888+ IMAGINE_128,
8889+ IMAGINE_128_2,
8890+ IMAGINE_T2R,
8891+ IMAGINE_REV4
8892+};
8893+
8894+#endif /* __IMAGINE_DRV_H__ */
8895Index: git/shared-core/mach64_dma.c
8896===================================================================
8897--- /dev/null 1970-01-01 00:00:00.000000000 +0000
8898+++ git/shared-core/mach64_dma.c 2008-12-12 17:35:22.000000000 +0000
8899@@ -0,0 +1,1532 @@
8900+/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- */
8901+/**
8902+ * \file mach64_dma.c
8903+ * DMA support for mach64 (Rage Pro) driver
8904+ *
8905+ * \author Gareth Hughes <gareth@valinux.com>
8906+ * \author Frank C. Earl <fearl@airmail.net>
8907+ * \author Leif Delgass <ldelgass@retinalburn.net>
8908+ * \author Jose Fonseca <j_r_fonseca@yahoo.co.uk>
8909+ */
8910+
8911+/*
8912+ * Copyright 2000 Gareth Hughes
8913+ * Copyright 2002 Frank C. Earl
8914+ * Copyright 2002-2003 Leif Delgass
8915+ * All Rights Reserved.
8916+ *
8917+ * Permission is hereby granted, free of charge, to any person obtaining a
8918+ * copy of this software and associated documentation files (the "Software"),
8919+ * to deal in the Software without restriction, including without limitation
8920+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8921+ * and/or sell copies of the Software, and to permit persons to whom the
8922+ * Software is furnished to do so, subject to the following conditions:
8923+ *
8924+ * The above copyright notice and this permission notice (including the next
8925+ * paragraph) shall be included in all copies or substantial portions of the
8926+ * Software.
8927+ *
8928+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
8929+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
8930+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
8931+ * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
8932+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
8933+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
8934+ */
8935+
8936+#include "drmP.h"
8937+#include "drm.h"
8938+#include "mach64_drm.h"
8939+#include "mach64_drv.h"
8940+
8941+/*******************************************************************/
8942+/** \name Engine, FIFO control */
8943+/*@{*/
8944+
8945+/**
8946+ * Waits for free entries in the FIFO.
8947+ *
8948+ * \note Most writes to Mach64 registers are automatically routed through
8949+ * command FIFO which is 16 entry deep. Prior to writing to any draw engine
8950+ * register one has to ensure that enough FIFO entries are available by calling
8951+ * this function. Failure to do so may cause the engine to lock.
8952+ *
8953+ * \param dev_priv pointer to device private data structure.
8954+ * \param entries number of free entries in the FIFO to wait for.
8955+ *
8956+ * \returns zero on success, or -EBUSY if the timeout (specificed by
8957+ * drm_mach64_private::usec_timeout) occurs.
8958+ */
8959+int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries)
8960+{
8961+ int slots = 0, i;
8962+
8963+ for (i = 0; i < dev_priv->usec_timeout; i++) {
8964+ slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK);
8965+ if (slots <= (0x8000 >> entries))
8966+ return 0;
8967+ DRM_UDELAY(1);
8968+ }
8969+
8970+ DRM_INFO("%s failed! slots=%d entries=%d\n", __FUNCTION__, slots,
8971+ entries);
8972+ return -EBUSY;
8973+}
8974+
8975+/**
8976+ * Wait for the draw engine to be idle.
8977+ */
8978+int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv)
8979+{
8980+ int i, ret;
8981+
8982+ ret = mach64_do_wait_for_fifo(dev_priv, 16);
8983+ if (ret < 0)
8984+ return ret;
8985+
8986+ for (i = 0; i < dev_priv->usec_timeout; i++) {
8987+ if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
8988+ return 0;
8989+ }
8990+ DRM_UDELAY(1);
8991+ }
8992+
8993+ DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__,
8994+ MACH64_READ(MACH64_GUI_STAT));
8995+ mach64_dump_ring_info(dev_priv);
8996+ return -EBUSY;
8997+}
8998+
8999+/**
9000+ * Wait for free entries in the ring buffer.
9001+ *
9002+ * The Mach64 bus master can be configured to act as a virtual FIFO, using a
9003+ * circular buffer (commonly referred as "ring buffer" in other drivers) with
9004+ * pointers to engine commands. This allows the CPU to do other things while
9005+ * the graphics engine is busy, i.e., DMA mode.
9006+ *
9007+ * This function should be called before writing new entries to the ring
9008+ * buffer.
9009+ *
9010+ * \param dev_priv pointer to device private data structure.
9011+ * \param n number of free entries in the ring buffer to wait for.
9012+ *
9013+ * \returns zero on success, or -EBUSY if the timeout (specificed by
9014+ * drm_mach64_private_t::usec_timeout) occurs.
9015+ *
9016+ * \sa mach64_dump_ring_info()
9017+ */
9018+int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n)
9019+{
9020+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
9021+ int i;
9022+
9023+ for (i = 0; i < dev_priv->usec_timeout; i++) {
9024+ mach64_update_ring_snapshot(dev_priv);
9025+ if (ring->space >= n) {
9026+ if (i > 0) {
9027+ DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i);
9028+ }
9029+ return 0;
9030+ }
9031+ DRM_UDELAY(1);
9032+ }
9033+
9034+ /* FIXME: This is being ignored... */
9035+ DRM_ERROR("failed!\n");
9036+ mach64_dump_ring_info(dev_priv);
9037+ return -EBUSY;
9038+}
9039+
9040+/**
9041+ * Wait until all DMA requests have been processed...
9042+ *
9043+ * \sa mach64_wait_ring()
9044+ */
9045+static int mach64_ring_idle(drm_mach64_private_t * dev_priv)
9046+{
9047+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
9048+ u32 head;
9049+ int i;
9050+
9051+ head = ring->head;
9052+ i = 0;
9053+ while (i < dev_priv->usec_timeout) {
9054+ mach64_update_ring_snapshot(dev_priv);
9055+ if (ring->head == ring->tail &&
9056+ !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
9057+ if (i > 0) {
9058+ DRM_DEBUG("%s: %d usecs\n", __FUNCTION__, i);
9059+ }
9060+ return 0;
9061+ }
9062+ if (ring->head == head) {
9063+ ++i;
9064+ } else {
9065+ head = ring->head;
9066+ i = 0;
9067+ }
9068+ DRM_UDELAY(1);
9069+ }
9070+
9071+ DRM_INFO("%s failed! GUI_STAT=0x%08x\n", __FUNCTION__,
9072+ MACH64_READ(MACH64_GUI_STAT));
9073+ mach64_dump_ring_info(dev_priv);
9074+ return -EBUSY;
9075+}
9076+
9077+/**
9078+ * Reset the the ring buffer descriptors.
9079+ *
9080+ * \sa mach64_do_engine_reset()
9081+ */
9082+static void mach64_ring_reset(drm_mach64_private_t * dev_priv)
9083+{
9084+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
9085+
9086+ mach64_do_release_used_buffers(dev_priv);
9087+ ring->head_addr = ring->start_addr;
9088+ ring->head = ring->tail = 0;
9089+ ring->space = ring->size;
9090+
9091+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
9092+ ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
9093+
9094+ dev_priv->ring_running = 0;
9095+}
9096+
9097+/**
9098+ * Ensure the all the queued commands will be processed.
9099+ */
9100+int mach64_do_dma_flush(drm_mach64_private_t * dev_priv)
9101+{
9102+ /* FIXME: It's not necessary to wait for idle when flushing
9103+ * we just need to ensure the ring will be completely processed
9104+ * in finite time without another ioctl
9105+ */
9106+ return mach64_ring_idle(dev_priv);
9107+}
9108+
9109+/**
9110+ * Stop all DMA activity.
9111+ */
9112+int mach64_do_dma_idle(drm_mach64_private_t * dev_priv)
9113+{
9114+ int ret;
9115+
9116+ /* wait for completion */
9117+ if ((ret = mach64_ring_idle(dev_priv)) < 0) {
9118+ DRM_ERROR("%s failed BM_GUI_TABLE=0x%08x tail: %u\n",
9119+ __FUNCTION__, MACH64_READ(MACH64_BM_GUI_TABLE),
9120+ dev_priv->ring.tail);
9121+ return ret;
9122+ }
9123+
9124+ mach64_ring_stop(dev_priv);
9125+
9126+ /* clean up after pass */
9127+ mach64_do_release_used_buffers(dev_priv);
9128+ return 0;
9129+}
9130+
9131+/**
9132+ * Reset the engine. This will stop the DMA if it is running.
9133+ */
9134+int mach64_do_engine_reset(drm_mach64_private_t * dev_priv)
9135+{
9136+ u32 tmp;
9137+
9138+ DRM_DEBUG("%s\n", __FUNCTION__);
9139+
9140+ /* Kill off any outstanding DMA transfers.
9141+ */
9142+ tmp = MACH64_READ(MACH64_BUS_CNTL);
9143+ MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS);
9144+
9145+ /* Reset the GUI engine (high to low transition).
9146+ */
9147+ tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
9148+ MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE);
9149+ /* Enable the GUI engine
9150+ */
9151+ tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
9152+ MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE);
9153+
9154+ /* ensure engine is not locked up by clearing any FIFO or HOST errors
9155+ */
9156+ tmp = MACH64_READ(MACH64_BUS_CNTL);
9157+ MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000);
9158+
9159+ /* Once GUI engine is restored, disable bus mastering */
9160+ MACH64_WRITE(MACH64_SRC_CNTL, 0);
9161+
9162+ /* Reset descriptor ring */
9163+ mach64_ring_reset(dev_priv);
9164+
9165+ return 0;
9166+}
9167+
9168+/*@}*/
9169+
9170+
9171+/*******************************************************************/
9172+/** \name Debugging output */
9173+/*@{*/
9174+
9175+/**
9176+ * Dump engine registers values.
9177+ */
9178+void mach64_dump_engine_info(drm_mach64_private_t * dev_priv)
9179+{
9180+ DRM_INFO("\n");
9181+ if (!dev_priv->is_pci) {
9182+ DRM_INFO(" AGP_BASE = 0x%08x\n",
9183+ MACH64_READ(MACH64_AGP_BASE));
9184+ DRM_INFO(" AGP_CNTL = 0x%08x\n",
9185+ MACH64_READ(MACH64_AGP_CNTL));
9186+ }
9187+ DRM_INFO(" ALPHA_TST_CNTL = 0x%08x\n",
9188+ MACH64_READ(MACH64_ALPHA_TST_CNTL));
9189+ DRM_INFO("\n");
9190+ DRM_INFO(" BM_COMMAND = 0x%08x\n",
9191+ MACH64_READ(MACH64_BM_COMMAND));
9192+ DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
9193+ MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
9194+ DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
9195+ MACH64_READ(MACH64_BM_GUI_TABLE));
9196+ DRM_INFO(" BM_STATUS = 0x%08x\n",
9197+ MACH64_READ(MACH64_BM_STATUS));
9198+ DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
9199+ MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
9200+ DRM_INFO(" BM_SYSTEM_TABLE = 0x%08x\n",
9201+ MACH64_READ(MACH64_BM_SYSTEM_TABLE));
9202+ DRM_INFO(" BUS_CNTL = 0x%08x\n",
9203+ MACH64_READ(MACH64_BUS_CNTL));
9204+ DRM_INFO("\n");
9205+ /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */
9206+ DRM_INFO(" CLR_CMP_CLR = 0x%08x\n",
9207+ MACH64_READ(MACH64_CLR_CMP_CLR));
9208+ DRM_INFO(" CLR_CMP_CNTL = 0x%08x\n",
9209+ MACH64_READ(MACH64_CLR_CMP_CNTL));
9210+ /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */
9211+ DRM_INFO(" CONFIG_CHIP_ID = 0x%08x\n",
9212+ MACH64_READ(MACH64_CONFIG_CHIP_ID));
9213+ DRM_INFO(" CONFIG_CNTL = 0x%08x\n",
9214+ MACH64_READ(MACH64_CONFIG_CNTL));
9215+ DRM_INFO(" CONFIG_STAT0 = 0x%08x\n",
9216+ MACH64_READ(MACH64_CONFIG_STAT0));
9217+ DRM_INFO(" CONFIG_STAT1 = 0x%08x\n",
9218+ MACH64_READ(MACH64_CONFIG_STAT1));
9219+ DRM_INFO(" CONFIG_STAT2 = 0x%08x\n",
9220+ MACH64_READ(MACH64_CONFIG_STAT2));
9221+ DRM_INFO(" CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG));
9222+ DRM_INFO(" CUSTOM_MACRO_CNTL = 0x%08x\n",
9223+ MACH64_READ(MACH64_CUSTOM_MACRO_CNTL));
9224+ DRM_INFO("\n");
9225+ /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */
9226+ /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */
9227+ DRM_INFO(" DP_BKGD_CLR = 0x%08x\n",
9228+ MACH64_READ(MACH64_DP_BKGD_CLR));
9229+ DRM_INFO(" DP_FRGD_CLR = 0x%08x\n",
9230+ MACH64_READ(MACH64_DP_FRGD_CLR));
9231+ DRM_INFO(" DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX));
9232+ DRM_INFO(" DP_PIX_WIDTH = 0x%08x\n",
9233+ MACH64_READ(MACH64_DP_PIX_WIDTH));
9234+ DRM_INFO(" DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC));
9235+ DRM_INFO(" DP_WRITE_MASK = 0x%08x\n",
9236+ MACH64_READ(MACH64_DP_WRITE_MASK));
9237+ DRM_INFO(" DSP_CONFIG = 0x%08x\n",
9238+ MACH64_READ(MACH64_DSP_CONFIG));
9239+ DRM_INFO(" DSP_ON_OFF = 0x%08x\n",
9240+ MACH64_READ(MACH64_DSP_ON_OFF));
9241+ DRM_INFO(" DST_CNTL = 0x%08x\n",
9242+ MACH64_READ(MACH64_DST_CNTL));
9243+ DRM_INFO(" DST_OFF_PITCH = 0x%08x\n",
9244+ MACH64_READ(MACH64_DST_OFF_PITCH));
9245+ DRM_INFO("\n");
9246+ /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */
9247+ DRM_INFO(" EXT_MEM_CNTL = 0x%08x\n",
9248+ MACH64_READ(MACH64_EXT_MEM_CNTL));
9249+ DRM_INFO("\n");
9250+ DRM_INFO(" FIFO_STAT = 0x%08x\n",
9251+ MACH64_READ(MACH64_FIFO_STAT));
9252+ DRM_INFO("\n");
9253+ DRM_INFO(" GEN_TEST_CNTL = 0x%08x\n",
9254+ MACH64_READ(MACH64_GEN_TEST_CNTL));
9255+ /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */
9256+ DRM_INFO(" GUI_CMDFIFO_DATA = 0x%08x\n",
9257+ MACH64_READ(MACH64_GUI_CMDFIFO_DATA));
9258+ DRM_INFO(" GUI_CMDFIFO_DEBUG = 0x%08x\n",
9259+ MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG));
9260+ DRM_INFO(" GUI_CNTL = 0x%08x\n",
9261+ MACH64_READ(MACH64_GUI_CNTL));
9262+ DRM_INFO(" GUI_STAT = 0x%08x\n",
9263+ MACH64_READ(MACH64_GUI_STAT));
9264+ DRM_INFO(" GUI_TRAJ_CNTL = 0x%08x\n",
9265+ MACH64_READ(MACH64_GUI_TRAJ_CNTL));
9266+ DRM_INFO("\n");
9267+ DRM_INFO(" HOST_CNTL = 0x%08x\n",
9268+ MACH64_READ(MACH64_HOST_CNTL));
9269+ DRM_INFO(" HW_DEBUG = 0x%08x\n",
9270+ MACH64_READ(MACH64_HW_DEBUG));
9271+ DRM_INFO("\n");
9272+ DRM_INFO(" MEM_ADDR_CONFIG = 0x%08x\n",
9273+ MACH64_READ(MACH64_MEM_ADDR_CONFIG));
9274+ DRM_INFO(" MEM_BUF_CNTL = 0x%08x\n",
9275+ MACH64_READ(MACH64_MEM_BUF_CNTL));
9276+ DRM_INFO("\n");
9277+ DRM_INFO(" PAT_REG0 = 0x%08x\n",
9278+ MACH64_READ(MACH64_PAT_REG0));
9279+ DRM_INFO(" PAT_REG1 = 0x%08x\n",
9280+ MACH64_READ(MACH64_PAT_REG1));
9281+ DRM_INFO("\n");
9282+ DRM_INFO(" SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT));
9283+ DRM_INFO(" SC_RIGHT = 0x%08x\n",
9284+ MACH64_READ(MACH64_SC_RIGHT));
9285+ DRM_INFO(" SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP));
9286+ DRM_INFO(" SC_BOTTOM = 0x%08x\n",
9287+ MACH64_READ(MACH64_SC_BOTTOM));
9288+ DRM_INFO("\n");
9289+ DRM_INFO(" SCALE_3D_CNTL = 0x%08x\n",
9290+ MACH64_READ(MACH64_SCALE_3D_CNTL));
9291+ DRM_INFO(" SCRATCH_REG0 = 0x%08x\n",
9292+ MACH64_READ(MACH64_SCRATCH_REG0));
9293+ DRM_INFO(" SCRATCH_REG1 = 0x%08x\n",
9294+ MACH64_READ(MACH64_SCRATCH_REG1));
9295+ DRM_INFO(" SETUP_CNTL = 0x%08x\n",
9296+ MACH64_READ(MACH64_SETUP_CNTL));
9297+ DRM_INFO(" SRC_CNTL = 0x%08x\n",
9298+ MACH64_READ(MACH64_SRC_CNTL));
9299+ DRM_INFO("\n");
9300+ DRM_INFO(" TEX_CNTL = 0x%08x\n",
9301+ MACH64_READ(MACH64_TEX_CNTL));
9302+ DRM_INFO(" TEX_SIZE_PITCH = 0x%08x\n",
9303+ MACH64_READ(MACH64_TEX_SIZE_PITCH));
9304+ DRM_INFO(" TIMER_CONFIG = 0x%08x\n",
9305+ MACH64_READ(MACH64_TIMER_CONFIG));
9306+ DRM_INFO("\n");
9307+ DRM_INFO(" Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL));
9308+ DRM_INFO(" Z_OFF_PITCH = 0x%08x\n",
9309+ MACH64_READ(MACH64_Z_OFF_PITCH));
9310+ DRM_INFO("\n");
9311+}
9312+
9313+#define MACH64_DUMP_CONTEXT 3
9314+
9315+/**
9316+ * Used by mach64_dump_ring_info() to dump the contents of the current buffer
9317+ * pointed by the ring head.
9318+ */
9319+static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv,
9320+ struct drm_buf * buf)
9321+{
9322+ u32 addr = GETBUFADDR(buf);
9323+ u32 used = buf->used >> 2;
9324+ u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR);
9325+ u32 *p = GETBUFPTR(buf);
9326+ int skipped = 0;
9327+
9328+ DRM_INFO("buffer contents:\n");
9329+
9330+ while (used) {
9331+ u32 reg, count;
9332+
9333+ reg = le32_to_cpu(*p++);
9334+ if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
9335+ (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
9336+ addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
9337+ addr >=
9338+ GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) {
9339+ DRM_INFO("%08x: 0x%08x\n", addr, reg);
9340+ }
9341+ addr += 4;
9342+ used--;
9343+
9344+ count = (reg >> 16) + 1;
9345+ reg = reg & 0xffff;
9346+ reg = MMSELECT(reg);
9347+ while (count && used) {
9348+ if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
9349+ (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
9350+ addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
9351+ addr >=
9352+ GETBUFADDR(buf) + buf->used -
9353+ MACH64_DUMP_CONTEXT * 4) {
9354+ DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr,
9355+ reg, le32_to_cpu(*p));
9356+ skipped = 0;
9357+ } else {
9358+ if (!skipped) {
9359+ DRM_INFO(" ...\n");
9360+ skipped = 1;
9361+ }
9362+ }
9363+ p++;
9364+ addr += 4;
9365+ used--;
9366+
9367+ reg += 4;
9368+ count--;
9369+ }
9370+ }
9371+
9372+ DRM_INFO("\n");
9373+}
9374+
9375+/**
9376+ * Dump the ring state and contents, including the contents of the buffer being
9377+ * processed by the graphics engine.
9378+ */
9379+void mach64_dump_ring_info(drm_mach64_private_t * dev_priv)
9380+{
9381+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
9382+ int i, skipped;
9383+
9384+ DRM_INFO("\n");
9385+
9386+ DRM_INFO("ring contents:\n");
9387+ DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n",
9388+ ring->head_addr, ring->head, ring->tail);
9389+
9390+ skipped = 0;
9391+ for (i = 0; i < ring->size / sizeof(u32); i += 4) {
9392+ if (i <= MACH64_DUMP_CONTEXT * 4 ||
9393+ i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 ||
9394+ (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 &&
9395+ i <= ring->tail + MACH64_DUMP_CONTEXT * 4) ||
9396+ (i >= ring->head - MACH64_DUMP_CONTEXT * 4 &&
9397+ i <= ring->head + MACH64_DUMP_CONTEXT * 4)) {
9398+ DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n",
9399+ (u32)(ring->start_addr + i * sizeof(u32)),
9400+ le32_to_cpu(((u32 *) ring->start)[i + 0]),
9401+ le32_to_cpu(((u32 *) ring->start)[i + 1]),
9402+ le32_to_cpu(((u32 *) ring->start)[i + 2]),
9403+ le32_to_cpu(((u32 *) ring->start)[i + 3]),
9404+ i == ring->head ? " (head)" : "",
9405+ i == ring->tail ? " (tail)" : "");
9406+ skipped = 0;
9407+ } else {
9408+ if (!skipped) {
9409+ DRM_INFO(" ...\n");
9410+ skipped = 1;
9411+ }
9412+ }
9413+ }
9414+
9415+ DRM_INFO("\n");
9416+
9417+ if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) {
9418+ struct list_head *ptr;
9419+ u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]);
9420+
9421+ list_for_each(ptr, &dev_priv->pending) {
9422+ drm_mach64_freelist_t *entry =
9423+ list_entry(ptr, drm_mach64_freelist_t, list);
9424+ struct drm_buf *buf = entry->buf;
9425+
9426+ u32 buf_addr = GETBUFADDR(buf);
9427+
9428+ if (buf_addr <= addr && addr < buf_addr + buf->used) {
9429+ mach64_dump_buf_info(dev_priv, buf);
9430+ }
9431+ }
9432+ }
9433+
9434+ DRM_INFO("\n");
9435+ DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
9436+ MACH64_READ(MACH64_BM_GUI_TABLE));
9437+ DRM_INFO("\n");
9438+ DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
9439+ MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
9440+ DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
9441+ MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
9442+ DRM_INFO(" BM_COMMAND = 0x%08x\n",
9443+ MACH64_READ(MACH64_BM_COMMAND));
9444+ DRM_INFO("\n");
9445+ DRM_INFO(" BM_STATUS = 0x%08x\n",
9446+ MACH64_READ(MACH64_BM_STATUS));
9447+ DRM_INFO(" BUS_CNTL = 0x%08x\n",
9448+ MACH64_READ(MACH64_BUS_CNTL));
9449+ DRM_INFO(" FIFO_STAT = 0x%08x\n",
9450+ MACH64_READ(MACH64_FIFO_STAT));
9451+ DRM_INFO(" GUI_STAT = 0x%08x\n",
9452+ MACH64_READ(MACH64_GUI_STAT));
9453+ DRM_INFO(" SRC_CNTL = 0x%08x\n",
9454+ MACH64_READ(MACH64_SRC_CNTL));
9455+}
9456+
9457+/*@}*/
9458+
9459+
9460+/*******************************************************************/
9461+/** \name DMA test and initialization */
9462+/*@{*/
9463+
9464+/**
9465+ * Perform a simple DMA operation using the pattern registers to test whether
9466+ * DMA works.
9467+ *
9468+ * \return zero if successful.
9469+ *
9470+ * \note This function was the testbed for many experiences regarding Mach64
9471+ * DMA operation. It is left here since it so tricky to get DMA operating
9472+ * properly in some architectures and hardware.
9473+ */
9474+static int mach64_bm_dma_test(struct drm_device * dev)
9475+{
9476+ drm_mach64_private_t *dev_priv = dev->dev_private;
9477+ drm_dma_handle_t *cpu_addr_dmah;
9478+ u32 data_addr;
9479+ u32 *table, *data;
9480+ u32 expected[2];
9481+ u32 src_cntl, pat_reg0, pat_reg1;
9482+ int i, count, failed;
9483+
9484+ DRM_DEBUG("%s\n", __FUNCTION__);
9485+
9486+ table = (u32 *) dev_priv->ring.start;
9487+
9488+ /* FIXME: get a dma buffer from the freelist here */
9489+ DRM_DEBUG("Allocating data memory ...\n");
9490+ cpu_addr_dmah =
9491+ drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful);
9492+ if (!cpu_addr_dmah) {
9493+ DRM_INFO("data-memory allocation failed!\n");
9494+ return -ENOMEM;
9495+ } else {
9496+ data = (u32 *) cpu_addr_dmah->vaddr;
9497+ data_addr = (u32) cpu_addr_dmah->busaddr;
9498+ }
9499+
9500+ /* Save the X server's value for SRC_CNTL and restore it
9501+ * in case our test fails. This prevents the X server
9502+ * from disabling it's cache for this register
9503+ */
9504+ src_cntl = MACH64_READ(MACH64_SRC_CNTL);
9505+ pat_reg0 = MACH64_READ(MACH64_PAT_REG0);
9506+ pat_reg1 = MACH64_READ(MACH64_PAT_REG1);
9507+
9508+ mach64_do_wait_for_fifo(dev_priv, 3);
9509+
9510+ MACH64_WRITE(MACH64_SRC_CNTL, 0);
9511+ MACH64_WRITE(MACH64_PAT_REG0, 0x11111111);
9512+ MACH64_WRITE(MACH64_PAT_REG1, 0x11111111);
9513+
9514+ mach64_do_wait_for_idle(dev_priv);
9515+
9516+ for (i = 0; i < 2; i++) {
9517+ u32 reg;
9518+ reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
9519+ DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg);
9520+ if (reg != 0x11111111) {
9521+ DRM_INFO("Error initializing test registers\n");
9522+ DRM_INFO("resetting engine ...\n");
9523+ mach64_do_engine_reset(dev_priv);
9524+ DRM_INFO("freeing data buffer memory.\n");
9525+ drm_pci_free(dev, cpu_addr_dmah);
9526+ return -EIO;
9527+ }
9528+ }
9529+
9530+ /* fill up a buffer with sets of 2 consecutive writes starting with PAT_REG0 */
9531+ count = 0;
9532+
9533+ data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
9534+ data[count++] = expected[0] = 0x22222222;
9535+ data[count++] = expected[1] = 0xaaaaaaaa;
9536+
9537+ while (count < 1020) {
9538+ data[count++] =
9539+ cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
9540+ data[count++] = 0x22222222;
9541+ data[count++] = 0xaaaaaaaa;
9542+ }
9543+ data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16));
9544+ data[count++] = 0;
9545+
9546+ DRM_DEBUG("Preparing table ...\n");
9547+ table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR +
9548+ MACH64_APERTURE_OFFSET);
9549+ table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr);
9550+ table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32)
9551+ | MACH64_DMA_HOLD_OFFSET
9552+ | MACH64_DMA_EOL);
9553+ table[MACH64_DMA_RESERVED] = 0;
9554+
9555+ DRM_DEBUG("table[0] = 0x%08x\n", table[0]);
9556+ DRM_DEBUG("table[1] = 0x%08x\n", table[1]);
9557+ DRM_DEBUG("table[2] = 0x%08x\n", table[2]);
9558+ DRM_DEBUG("table[3] = 0x%08x\n", table[3]);
9559+
9560+ for (i = 0; i < 6; i++) {
9561+ DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
9562+ }
9563+ DRM_DEBUG(" ...\n");
9564+ for (i = count - 5; i < count; i++) {
9565+ DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
9566+ }
9567+
9568+ DRM_MEMORYBARRIER();
9569+
9570+ DRM_DEBUG("waiting for idle...\n");
9571+ if ((i = mach64_do_wait_for_idle(dev_priv))) {
9572+ DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
9573+ DRM_INFO("resetting engine ...\n");
9574+ mach64_do_engine_reset(dev_priv);
9575+ mach64_do_wait_for_fifo(dev_priv, 3);
9576+ MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
9577+ MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
9578+ MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
9579+ DRM_INFO("freeing data buffer memory.\n");
9580+ drm_pci_free(dev, cpu_addr_dmah);
9581+ return i;
9582+ }
9583+ DRM_DEBUG("waiting for idle...done\n");
9584+
9585+ DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL));
9586+ DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL));
9587+ DRM_DEBUG("\n");
9588+ DRM_DEBUG("data bus addr = 0x%08x\n", data_addr);
9589+ DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr);
9590+
9591+ DRM_DEBUG("starting DMA transfer...\n");
9592+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
9593+ dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
9594+
9595+ MACH64_WRITE(MACH64_SRC_CNTL,
9596+ MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
9597+ MACH64_SRC_BM_OP_SYSTEM_TO_REG);
9598+
9599+ /* Kick off the transfer */
9600+ DRM_DEBUG("starting DMA transfer... done.\n");
9601+ MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
9602+
9603+ DRM_DEBUG("waiting for idle...\n");
9604+
9605+ if ((i = mach64_do_wait_for_idle(dev_priv))) {
9606+ /* engine locked up, dump register state and reset */
9607+ DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
9608+ mach64_dump_engine_info(dev_priv);
9609+ DRM_INFO("resetting engine ...\n");
9610+ mach64_do_engine_reset(dev_priv);
9611+ mach64_do_wait_for_fifo(dev_priv, 3);
9612+ MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
9613+ MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
9614+ MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
9615+ DRM_INFO("freeing data buffer memory.\n");
9616+ drm_pci_free(dev, cpu_addr_dmah);
9617+ return i;
9618+ }
9619+
9620+ DRM_DEBUG("waiting for idle...done\n");
9621+
9622+ /* restore SRC_CNTL */
9623+ mach64_do_wait_for_fifo(dev_priv, 1);
9624+ MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
9625+
9626+ failed = 0;
9627+
9628+ /* Check register values to see if the GUI master operation succeeded */
9629+ for (i = 0; i < 2; i++) {
9630+ u32 reg;
9631+ reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
9632+ DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg);
9633+ if (reg != expected[i]) {
9634+ failed = -1;
9635+ }
9636+ }
9637+
9638+ /* restore pattern registers */
9639+ mach64_do_wait_for_fifo(dev_priv, 2);
9640+ MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
9641+ MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
9642+
9643+ DRM_DEBUG("freeing data buffer memory.\n");
9644+ drm_pci_free(dev, cpu_addr_dmah);
9645+ DRM_DEBUG("returning ...\n");
9646+
9647+ return failed;
9648+}
9649+
9650+/**
9651+ * Called during the DMA initialization ioctl to initialize all the necessary
9652+ * software and hardware state for DMA operation.
9653+ */
9654+static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init)
9655+{
9656+ drm_mach64_private_t *dev_priv;
9657+ u32 tmp;
9658+ int i, ret;
9659+
9660+ DRM_DEBUG("%s\n", __FUNCTION__);
9661+
9662+ dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER);
9663+ if (dev_priv == NULL)
9664+ return -ENOMEM;
9665+
9666+ memset(dev_priv, 0, sizeof(drm_mach64_private_t));
9667+
9668+ dev_priv->is_pci = init->is_pci;
9669+
9670+ dev_priv->fb_bpp = init->fb_bpp;
9671+ dev_priv->front_offset = init->front_offset;
9672+ dev_priv->front_pitch = init->front_pitch;
9673+ dev_priv->back_offset = init->back_offset;
9674+ dev_priv->back_pitch = init->back_pitch;
9675+
9676+ dev_priv->depth_bpp = init->depth_bpp;
9677+ dev_priv->depth_offset = init->depth_offset;
9678+ dev_priv->depth_pitch = init->depth_pitch;
9679+
9680+ dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) |
9681+ (dev_priv->front_offset >> 3));
9682+ dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) |
9683+ (dev_priv->back_offset >> 3));
9684+ dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) |
9685+ (dev_priv->depth_offset >> 3));
9686+
9687+ dev_priv->usec_timeout = 1000000;
9688+
9689+ /* Set up the freelist, placeholder list and pending list */
9690+ INIT_LIST_HEAD(&dev_priv->free_list);
9691+ INIT_LIST_HEAD(&dev_priv->placeholders);
9692+ INIT_LIST_HEAD(&dev_priv->pending);
9693+
9694+ dev_priv->sarea = drm_getsarea(dev);
9695+ if (!dev_priv->sarea) {
9696+ DRM_ERROR("can not find sarea!\n");
9697+ dev->dev_private = (void *)dev_priv;
9698+ mach64_do_cleanup_dma(dev);
9699+ return -EINVAL;
9700+ }
9701+ dev_priv->fb = drm_core_findmap(dev, init->fb_offset);
9702+ if (!dev_priv->fb) {
9703+ DRM_ERROR("can not find frame buffer map!\n");
9704+ dev->dev_private = (void *)dev_priv;
9705+ mach64_do_cleanup_dma(dev);
9706+ return -EINVAL;
9707+ }
9708+ dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
9709+ if (!dev_priv->mmio) {
9710+ DRM_ERROR("can not find mmio map!\n");
9711+ dev->dev_private = (void *)dev_priv;
9712+ mach64_do_cleanup_dma(dev);
9713+ return -EINVAL;
9714+ }
9715+
9716+ dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset);
9717+ if (!dev_priv->ring_map) {
9718+ DRM_ERROR("can not find ring map!\n");
9719+ dev->dev_private = (void *)dev_priv;
9720+ mach64_do_cleanup_dma(dev);
9721+ return -EINVAL;
9722+ }
9723+
9724+ dev_priv->sarea_priv = (drm_mach64_sarea_t *)
9725+ ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
9726+
9727+ if (!dev_priv->is_pci) {
9728+ drm_core_ioremap(dev_priv->ring_map, dev);
9729+ if (!dev_priv->ring_map->handle) {
9730+ DRM_ERROR("can not ioremap virtual address for"
9731+ " descriptor ring\n");
9732+ dev->dev_private = (void *)dev_priv;
9733+ mach64_do_cleanup_dma(dev);
9734+ return -ENOMEM;
9735+ }
9736+ dev->agp_buffer_token = init->buffers_offset;
9737+ dev->agp_buffer_map =
9738+ drm_core_findmap(dev, init->buffers_offset);
9739+ if (!dev->agp_buffer_map) {
9740+ DRM_ERROR("can not find dma buffer map!\n");
9741+ dev->dev_private = (void *)dev_priv;
9742+ mach64_do_cleanup_dma(dev);
9743+ return -EINVAL;
9744+ }
9745+ /* there might be a nicer way to do this -
9746+ dev isn't passed all the way though the mach64 - DA */
9747+ dev_priv->dev_buffers = dev->agp_buffer_map;
9748+
9749+ drm_core_ioremap(dev->agp_buffer_map, dev);
9750+ if (!dev->agp_buffer_map->handle) {
9751+ DRM_ERROR("can not ioremap virtual address for"
9752+ " dma buffer\n");
9753+ dev->dev_private = (void *)dev_priv;
9754+ mach64_do_cleanup_dma(dev);
9755+ return -ENOMEM;
9756+ }
9757+ dev_priv->agp_textures =
9758+ drm_core_findmap(dev, init->agp_textures_offset);
9759+ if (!dev_priv->agp_textures) {
9760+ DRM_ERROR("can not find agp texture region!\n");
9761+ dev->dev_private = (void *)dev_priv;
9762+ mach64_do_cleanup_dma(dev);
9763+ return -EINVAL;
9764+ }
9765+ }
9766+
9767+ dev->dev_private = (void *)dev_priv;
9768+
9769+ dev_priv->driver_mode = init->dma_mode;
9770+
9771+ /* changing the FIFO size from the default causes problems with DMA */
9772+ tmp = MACH64_READ(MACH64_GUI_CNTL);
9773+ if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) {
9774+ DRM_INFO("Setting FIFO size to 128 entries\n");
9775+ /* FIFO must be empty to change the FIFO depth */
9776+ if ((ret = mach64_do_wait_for_idle(dev_priv))) {
9777+ DRM_ERROR
9778+ ("wait for idle failed before changing FIFO depth!\n");
9779+ mach64_do_cleanup_dma(dev);
9780+ return ret;
9781+ }
9782+ MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK)
9783+ | MACH64_CMDFIFO_SIZE_128));
9784+ /* need to read GUI_STAT for proper sync according to docs */
9785+ if ((ret = mach64_do_wait_for_idle(dev_priv))) {
9786+ DRM_ERROR
9787+ ("wait for idle failed when changing FIFO depth!\n");
9788+ mach64_do_cleanup_dma(dev);
9789+ return ret;
9790+ }
9791+ }
9792+
9793+ dev_priv->ring.size = 0x4000; /* 16KB */
9794+ dev_priv->ring.start = dev_priv->ring_map->handle;
9795+ dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset;
9796+
9797+ memset(dev_priv->ring.start, 0, dev_priv->ring.size);
9798+ DRM_INFO("descriptor ring: cpu addr %p, bus addr: 0x%08x\n",
9799+ dev_priv->ring.start, dev_priv->ring.start_addr);
9800+
9801+ ret = 0;
9802+ if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
9803+
9804+ /* enable block 1 registers and bus mastering */
9805+ MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL)
9806+ | MACH64_BUS_EXT_REG_EN)
9807+ & ~MACH64_BUS_MASTER_DIS));
9808+
9809+ /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */
9810+ DRM_DEBUG("Starting DMA test...\n");
9811+ if ((ret = mach64_bm_dma_test(dev))) {
9812+ dev_priv->driver_mode = MACH64_MODE_MMIO;
9813+ }
9814+ }
9815+
9816+ switch (dev_priv->driver_mode) {
9817+ case MACH64_MODE_MMIO:
9818+ MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL)
9819+ | MACH64_BUS_EXT_REG_EN
9820+ | MACH64_BUS_MASTER_DIS));
9821+ if (init->dma_mode == MACH64_MODE_MMIO)
9822+ DRM_INFO("Forcing pseudo-DMA mode\n");
9823+ else
9824+ DRM_INFO
9825+ ("DMA test failed (ret=%d), using pseudo-DMA mode\n",
9826+ ret);
9827+ break;
9828+ case MACH64_MODE_DMA_SYNC:
9829+ DRM_INFO("DMA test succeeded, using synchronous DMA mode\n");
9830+ break;
9831+ case MACH64_MODE_DMA_ASYNC:
9832+ default:
9833+ DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n");
9834+ }
9835+
9836+ dev_priv->ring_running = 0;
9837+
9838+ /* setup offsets for physical address of table start and end */
9839+ dev_priv->ring.head_addr = dev_priv->ring.start_addr;
9840+ dev_priv->ring.head = dev_priv->ring.tail = 0;
9841+ dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
9842+ dev_priv->ring.space = dev_priv->ring.size;
9843+
9844+ /* setup physical address and size of descriptor table */
9845+ mach64_do_wait_for_fifo(dev_priv, 1);
9846+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
9847+ (dev_priv->ring.
9848+ head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB));
9849+
9850+ /* init frame counter */
9851+ dev_priv->sarea_priv->frames_queued = 0;
9852+ for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) {
9853+ dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */
9854+ }
9855+
9856+ /* Allocate the DMA buffer freelist */
9857+ if ((ret = mach64_init_freelist(dev))) {
9858+ DRM_ERROR("Freelist allocation failed\n");
9859+ mach64_do_cleanup_dma(dev);
9860+ return ret;
9861+ }
9862+
9863+ return 0;
9864+}
9865+
9866+/*******************************************************************/
9867+/** MMIO Pseudo-DMA (intended primarily for debugging, not performance)
9868+ */
9869+
9870+int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv)
9871+{
9872+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
9873+ volatile u32 *ring_read;
9874+ struct list_head *ptr;
9875+ drm_mach64_freelist_t *entry;
9876+ struct drm_buf *buf = NULL;
9877+ u32 *buf_ptr;
9878+ u32 used, reg, target;
9879+ int fifo, count, found, ret, no_idle_wait;
9880+
9881+ fifo = count = reg = no_idle_wait = 0;
9882+ target = MACH64_BM_ADDR;
9883+
9884+ if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
9885+ DRM_INFO
9886+ ("%s: idle failed before pseudo-dma dispatch, resetting engine\n",
9887+ __FUNCTION__);
9888+ mach64_dump_engine_info(dev_priv);
9889+ mach64_do_engine_reset(dev_priv);
9890+ return ret;
9891+ }
9892+
9893+ ring_read = (u32 *) ring->start;
9894+
9895+ while (ring->tail != ring->head) {
9896+ u32 buf_addr, new_target, offset;
9897+ u32 bytes, remaining, head, eol;
9898+
9899+ head = ring->head;
9900+
9901+ new_target =
9902+ le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET;
9903+ buf_addr = le32_to_cpu(ring_read[head++]);
9904+ eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL;
9905+ bytes = le32_to_cpu(ring_read[head++])
9906+ & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL);
9907+ head++;
9908+ head &= ring->tail_mask;
9909+
9910+ /* can't wait for idle between a blit setup descriptor
9911+ * and a HOSTDATA descriptor or the engine will lock
9912+ */
9913+ if (new_target == MACH64_BM_HOSTDATA
9914+ && target == MACH64_BM_ADDR)
9915+ no_idle_wait = 1;
9916+
9917+ target = new_target;
9918+
9919+ found = 0;
9920+ offset = 0;
9921+ list_for_each(ptr, &dev_priv->pending) {
9922+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
9923+ buf = entry->buf;
9924+ offset = buf_addr - GETBUFADDR(buf);
9925+ if (offset >= 0 && offset < MACH64_BUFFER_SIZE) {
9926+ found = 1;
9927+ break;
9928+ }
9929+ }
9930+
9931+ if (!found || buf == NULL) {
9932+ DRM_ERROR
9933+ ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n",
9934+ head, ring->tail, buf_addr, (eol ? "eol" : ""));
9935+ mach64_dump_ring_info(dev_priv);
9936+ mach64_do_engine_reset(dev_priv);
9937+ return -EINVAL;
9938+ }
9939+
9940+ /* Hand feed the buffer to the card via MMIO, waiting for the fifo
9941+ * every 16 writes
9942+ */
9943+ DRM_DEBUG("target: (0x%08x) %s\n", target,
9944+ (target ==
9945+ MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR"));
9946+ DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes,
9947+ buf->used);
9948+
9949+ remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */
9950+ used = bytes >> 2; /* dwords in buffer for this descriptor */
9951+ buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset);
9952+
9953+ while (used) {
9954+
9955+ if (count == 0) {
9956+ if (target == MACH64_BM_HOSTDATA) {
9957+ reg = DMAREG(MACH64_HOST_DATA0);
9958+ count =
9959+ (remaining > 16) ? 16 : remaining;
9960+ fifo = 0;
9961+ } else {
9962+ reg = le32_to_cpu(*buf_ptr++);
9963+ used--;
9964+ count = (reg >> 16) + 1;
9965+ }
9966+
9967+ reg = reg & 0xffff;
9968+ reg = MMSELECT(reg);
9969+ }
9970+ while (count && used) {
9971+ if (!fifo) {
9972+ if (no_idle_wait) {
9973+ if ((ret =
9974+ mach64_do_wait_for_fifo
9975+ (dev_priv, 16)) < 0) {
9976+ no_idle_wait = 0;
9977+ return ret;
9978+ }
9979+ } else {
9980+ if ((ret =
9981+ mach64_do_wait_for_idle
9982+ (dev_priv)) < 0) {
9983+ return ret;
9984+ }
9985+ }
9986+ fifo = 16;
9987+ }
9988+ --fifo;
9989+ MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++));
9990+ used--;
9991+ remaining--;
9992+
9993+ reg += 4;
9994+ count--;
9995+ }
9996+ }
9997+ ring->head = head;
9998+ ring->head_addr = ring->start_addr + (ring->head * sizeof(u32));
9999+ ring->space += (4 * sizeof(u32));
10000+ }
10001+
10002+ if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
10003+ return ret;
10004+ }
10005+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
10006+ ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
10007+
10008+ DRM_DEBUG("%s completed\n", __FUNCTION__);
10009+ return 0;
10010+}
10011+
10012+/*@}*/
10013+
10014+
10015+/*******************************************************************/
10016+/** \name DMA cleanup */
10017+/*@{*/
10018+
10019+int mach64_do_cleanup_dma(struct drm_device * dev)
10020+{
10021+ DRM_DEBUG("%s\n", __FUNCTION__);
10022+
10023+ /* Make sure interrupts are disabled here because the uninstall ioctl
10024+ * may not have been called from userspace and after dev_private
10025+ * is freed, it's too late.
10026+ */
10027+ if (dev->irq)
10028+ drm_irq_uninstall(dev);
10029+
10030+ if (dev->dev_private) {
10031+ drm_mach64_private_t *dev_priv = dev->dev_private;
10032+
10033+ if (!dev_priv->is_pci) {
10034+ if (dev_priv->ring_map)
10035+ drm_core_ioremapfree(dev_priv->ring_map, dev);
10036+
10037+ if (dev->agp_buffer_map) {
10038+ drm_core_ioremapfree(dev->agp_buffer_map, dev);
10039+ dev->agp_buffer_map = NULL;
10040+ }
10041+ }
10042+
10043+ mach64_destroy_freelist(dev);
10044+
10045+ drm_free(dev_priv, sizeof(drm_mach64_private_t),
10046+ DRM_MEM_DRIVER);
10047+ dev->dev_private = NULL;
10048+ }
10049+
10050+ return 0;
10051+}
10052+
10053+/*@}*/
10054+
10055+
10056+/*******************************************************************/
10057+/** \name IOCTL handlers */
10058+/*@{*/
10059+
10060+int mach64_dma_init(struct drm_device *dev, void *data,
10061+ struct drm_file *file_priv)
10062+{
10063+ drm_mach64_init_t *init = data;
10064+
10065+ DRM_DEBUG("%s\n", __FUNCTION__);
10066+
10067+ LOCK_TEST_WITH_RETURN(dev, file_priv);
10068+
10069+ switch (init->func) {
10070+ case DRM_MACH64_INIT_DMA:
10071+ return mach64_do_dma_init(dev, init);
10072+ case DRM_MACH64_CLEANUP_DMA:
10073+ return mach64_do_cleanup_dma(dev);
10074+ }
10075+
10076+ return -EINVAL;
10077+}
10078+
10079+int mach64_dma_idle(struct drm_device *dev, void *data,
10080+ struct drm_file *file_priv)
10081+{
10082+ drm_mach64_private_t *dev_priv = dev->dev_private;
10083+
10084+ DRM_DEBUG("%s\n", __FUNCTION__);
10085+
10086+ LOCK_TEST_WITH_RETURN(dev, file_priv);
10087+
10088+ return mach64_do_dma_idle(dev_priv);
10089+}
10090+
10091+int mach64_dma_flush(struct drm_device *dev, void *data,
10092+ struct drm_file *file_priv)
10093+{
10094+ drm_mach64_private_t *dev_priv = dev->dev_private;
10095+
10096+ DRM_DEBUG("%s\n", __FUNCTION__);
10097+
10098+ LOCK_TEST_WITH_RETURN(dev, file_priv);
10099+
10100+ return mach64_do_dma_flush(dev_priv);
10101+}
10102+
10103+int mach64_engine_reset(struct drm_device *dev, void *data,
10104+ struct drm_file *file_priv)
10105+{
10106+ drm_mach64_private_t *dev_priv = dev->dev_private;
10107+
10108+ DRM_DEBUG("%s\n", __FUNCTION__);
10109+
10110+ LOCK_TEST_WITH_RETURN(dev, file_priv);
10111+
10112+ return mach64_do_engine_reset(dev_priv);
10113+}
10114+
10115+/*@}*/
10116+
10117+
10118+/*******************************************************************/
10119+/** \name Freelist management */
10120+/*@{*/
10121+
10122+int mach64_init_freelist(struct drm_device * dev)
10123+{
10124+ struct drm_device_dma *dma = dev->dma;
10125+ drm_mach64_private_t *dev_priv = dev->dev_private;
10126+ drm_mach64_freelist_t *entry;
10127+ struct list_head *ptr;
10128+ int i;
10129+
10130+ DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__,
10131+ dma->buf_count);
10132+
10133+ for (i = 0; i < dma->buf_count; i++) {
10134+ if ((entry =
10135+ (drm_mach64_freelist_t *)
10136+ drm_alloc(sizeof(drm_mach64_freelist_t),
10137+ DRM_MEM_BUFLISTS)) == NULL)
10138+ return -ENOMEM;
10139+ memset(entry, 0, sizeof(drm_mach64_freelist_t));
10140+ entry->buf = dma->buflist[i];
10141+ ptr = &entry->list;
10142+ list_add_tail(ptr, &dev_priv->free_list);
10143+ }
10144+
10145+ return 0;
10146+}
10147+
10148+void mach64_destroy_freelist(struct drm_device * dev)
10149+{
10150+ drm_mach64_private_t *dev_priv = dev->dev_private;
10151+ drm_mach64_freelist_t *entry;
10152+ struct list_head *ptr;
10153+ struct list_head *tmp;
10154+
10155+ DRM_DEBUG("%s\n", __FUNCTION__);
10156+
10157+ list_for_each_safe(ptr, tmp, &dev_priv->pending) {
10158+ list_del(ptr);
10159+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10160+ drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
10161+ }
10162+ list_for_each_safe(ptr, tmp, &dev_priv->placeholders) {
10163+ list_del(ptr);
10164+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10165+ drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
10166+ }
10167+
10168+ list_for_each_safe(ptr, tmp, &dev_priv->free_list) {
10169+ list_del(ptr);
10170+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10171+ drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
10172+ }
10173+}
10174+
10175+/* IMPORTANT: This function should only be called when the engine is idle or locked up,
10176+ * as it assumes all buffers in the pending list have been completed by the hardware.
10177+ */
10178+int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv)
10179+{
10180+ struct list_head *ptr;
10181+ struct list_head *tmp;
10182+ drm_mach64_freelist_t *entry;
10183+ int i;
10184+
10185+ if (list_empty(&dev_priv->pending))
10186+ return 0;
10187+
10188+ /* Iterate the pending list and move all buffers into the freelist... */
10189+ i = 0;
10190+ list_for_each_safe(ptr, tmp, &dev_priv->pending) {
10191+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10192+ if (entry->discard) {
10193+ entry->buf->pending = 0;
10194+ list_del(ptr);
10195+ list_add_tail(ptr, &dev_priv->free_list);
10196+ i++;
10197+ }
10198+ }
10199+
10200+ DRM_DEBUG("%s: released %d buffers from pending list\n", __FUNCTION__,
10201+ i);
10202+
10203+ return 0;
10204+}
10205+
10206+static int mach64_do_reclaim_completed(drm_mach64_private_t * dev_priv)
10207+{
10208+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
10209+ struct list_head *ptr;
10210+ struct list_head *tmp;
10211+ drm_mach64_freelist_t *entry;
10212+ u32 head, tail, ofs;
10213+
10214+ mach64_ring_tick(dev_priv, ring);
10215+ head = ring->head;
10216+ tail = ring->tail;
10217+
10218+ if (head == tail) {
10219+#if MACH64_EXTRA_CHECKING
10220+ if (MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) {
10221+ DRM_ERROR("Empty ring with non-idle engine!\n");
10222+ mach64_dump_ring_info(dev_priv);
10223+ return -1;
10224+ }
10225+#endif
10226+ /* last pass is complete, so release everything */
10227+ mach64_do_release_used_buffers(dev_priv);
10228+ DRM_DEBUG("%s: idle engine, freed all buffers.\n",
10229+ __FUNCTION__);
10230+ if (list_empty(&dev_priv->free_list)) {
10231+ DRM_ERROR("Freelist empty with idle engine\n");
10232+ return -1;
10233+ }
10234+ return 0;
10235+ }
10236+ /* Look for a completed buffer and bail out of the loop
10237+ * as soon as we find one -- don't waste time trying
10238+ * to free extra bufs here, leave that to do_release_used_buffers
10239+ */
10240+ list_for_each_safe(ptr, tmp, &dev_priv->pending) {
10241+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10242+ ofs = entry->ring_ofs;
10243+ if (entry->discard &&
10244+ ((head < tail && (ofs < head || ofs >= tail)) ||
10245+ (head > tail && (ofs < head && ofs >= tail)))) {
10246+#if MACH64_EXTRA_CHECKING
10247+ int i;
10248+
10249+ for (i = head; i != tail; i = (i + 4) & ring->tail_mask)
10250+ {
10251+ u32 o1 = le32_to_cpu(((u32 *) ring->
10252+ start)[i + 1]);
10253+ u32 o2 = GETBUFADDR(entry->buf);
10254+
10255+ if (o1 == o2) {
10256+ DRM_ERROR
10257+ ("Attempting to free used buffer: "
10258+ "i=%d buf=0x%08x\n",
10259+ i, o1);
10260+ mach64_dump_ring_info(dev_priv);
10261+ return -1;
10262+ }
10263+ }
10264+#endif
10265+ /* found a processed buffer */
10266+ entry->buf->pending = 0;
10267+ list_del(ptr);
10268+ list_add_tail(ptr, &dev_priv->free_list);
10269+ DRM_DEBUG
10270+ ("%s: freed processed buffer (head=%d tail=%d "
10271+ "buf ring ofs=%d).\n",
10272+ __FUNCTION__, head, tail, ofs);
10273+ return 0;
10274+ }
10275+ }
10276+
10277+ return 1;
10278+}
10279+
10280+struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv)
10281+{
10282+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
10283+ drm_mach64_freelist_t *entry;
10284+ struct list_head *ptr;
10285+ int t;
10286+
10287+ if (list_empty(&dev_priv->free_list)) {
10288+ if (list_empty(&dev_priv->pending)) {
10289+ DRM_ERROR
10290+ ("Couldn't get buffer - pending and free lists empty\n");
10291+ t = 0;
10292+ list_for_each(ptr, &dev_priv->placeholders) {
10293+ t++;
10294+ }
10295+ DRM_INFO("Placeholders: %d\n", t);
10296+ return NULL;
10297+ }
10298+
10299+ for (t = 0; t < dev_priv->usec_timeout; t++) {
10300+ int ret;
10301+
10302+ ret = mach64_do_reclaim_completed(dev_priv);
10303+ if (ret == 0)
10304+ goto _freelist_entry_found;
10305+ if (ret < 0)
10306+ return NULL;
10307+
10308+ DRM_UDELAY(1);
10309+ }
10310+ mach64_dump_ring_info(dev_priv);
10311+ DRM_ERROR
10312+ ("timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n",
10313+ ring->head_addr, ring->head, ring->tail);
10314+ return NULL;
10315+ }
10316+
10317+ _freelist_entry_found:
10318+ ptr = dev_priv->free_list.next;
10319+ list_del(ptr);
10320+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10321+ entry->buf->used = 0;
10322+ list_add_tail(ptr, &dev_priv->placeholders);
10323+ return entry->buf;
10324+}
10325+
10326+int mach64_freelist_put(drm_mach64_private_t * dev_priv, struct drm_buf * copy_buf)
10327+{
10328+ struct list_head *ptr;
10329+ drm_mach64_freelist_t *entry;
10330+
10331+#if MACH64_EXTRA_CHECKING
10332+ list_for_each(ptr, &dev_priv->pending) {
10333+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10334+ if (copy_buf == entry->buf) {
10335+ DRM_ERROR("%s: Trying to release a pending buf\n",
10336+ __FUNCTION__);
10337+ return -EFAULT;
10338+ }
10339+ }
10340+#endif
10341+ ptr = dev_priv->placeholders.next;
10342+ entry = list_entry(ptr, drm_mach64_freelist_t, list);
10343+ copy_buf->pending = 0;
10344+ copy_buf->used = 0;
10345+ entry->buf = copy_buf;
10346+ entry->discard = 1;
10347+ list_del(ptr);
10348+ list_add_tail(ptr, &dev_priv->free_list);
10349+
10350+ return 0;
10351+}
10352+
10353+/*@}*/
10354+
10355+
10356+/*******************************************************************/
10357+/** \name DMA buffer request and submission IOCTL handler */
10358+/*@{*/
10359+
10360+static int mach64_dma_get_buffers(struct drm_device *dev,
10361+ struct drm_file *file_priv,
10362+ struct drm_dma * d)
10363+{
10364+ int i;
10365+ struct drm_buf *buf;
10366+ drm_mach64_private_t *dev_priv = dev->dev_private;
10367+
10368+ for (i = d->granted_count; i < d->request_count; i++) {
10369+ buf = mach64_freelist_get(dev_priv);
10370+#if MACH64_EXTRA_CHECKING
10371+ if (!buf)
10372+ return -EFAULT;
10373+#else
10374+ if (!buf)
10375+ return -EAGAIN;
10376+#endif
10377+
10378+ buf->file_priv = file_priv;
10379+
10380+ if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
10381+ sizeof(buf->idx)))
10382+ return -EFAULT;
10383+ if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
10384+ sizeof(buf->total)))
10385+ return -EFAULT;
10386+
10387+ d->granted_count++;
10388+ }
10389+ return 0;
10390+}
10391+
10392+int mach64_dma_buffers(struct drm_device *dev, void *data,
10393+ struct drm_file *file_priv)
10394+{
10395+ struct drm_device_dma *dma = dev->dma;
10396+ struct drm_dma *d = data;
10397+ int ret = 0;
10398+
10399+ LOCK_TEST_WITH_RETURN(dev, file_priv);
10400+
10401+ /* Please don't send us buffers.
10402+ */
10403+ if (d->send_count != 0) {
10404+ DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
10405+ DRM_CURRENTPID, d->send_count);
10406+ return -EINVAL;
10407+ }
10408+
10409+ /* We'll send you buffers.
10410+ */
10411+ if (d->request_count < 0 || d->request_count > dma->buf_count) {
10412+ DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
10413+ DRM_CURRENTPID, d->request_count, dma->buf_count);
10414+ ret = -EINVAL;
10415+ }
10416+
10417+ d->granted_count = 0;
10418+
10419+ if (d->request_count) {
10420+ ret = mach64_dma_get_buffers(dev, file_priv, d);
10421+ }
10422+
10423+ return ret;
10424+}
10425+
10426+void mach64_driver_lastclose(struct drm_device * dev)
10427+{
10428+ mach64_do_cleanup_dma(dev);
10429+}
10430+
10431+/*@}*/
10432Index: git/shared-core/mach64_drm.h
10433===================================================================
10434--- git.orig/shared-core/mach64_drm.h 2008-12-12 17:20:14.000000000 +0000
10435+++ git/shared-core/mach64_drm.h 2008-12-12 17:35:22.000000000 +0000
10436@@ -130,7 +130,7 @@
10437
10438 /* The current cliprects, or a subset thereof.
10439 */
10440- drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
10441+ struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
10442 unsigned int nbox;
10443
10444 /* Counters for client-side throttling of rendering clients.
10445@@ -139,7 +139,7 @@
10446
10447 /* Texture memory LRU.
10448 */
10449- drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
10450+ struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
10451 1];
10452 unsigned int tex_age[MACH64_NR_TEX_HEAPS];
10453 int ctx_owner;
10454Index: git/shared-core/mach64_drv.h
10455===================================================================
10456--- /dev/null 1970-01-01 00:00:00.000000000 +0000
10457+++ git/shared-core/mach64_drv.h 2008-12-12 17:35:22.000000000 +0000
10458@@ -0,0 +1,1058 @@
10459+/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*-
10460+ * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com
10461+ */
10462+/*
10463+ * Copyright 2000 Gareth Hughes
10464+ * Copyright 2002 Frank C. Earl
10465+ * Copyright 2002-2003 Leif Delgass
10466+ * All Rights Reserved.
10467+ *
10468+ * Permission is hereby granted, free of charge, to any person obtaining a
10469+ * copy of this software and associated documentation files (the "Software"),
10470+ * to deal in the Software without restriction, including without limitation
10471+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10472+ * and/or sell copies of the Software, and to permit persons to whom the
10473+ * Software is furnished to do so, subject to the following conditions:
10474+ *
10475+ * The above copyright notice and this permission notice (including the next
10476+ * paragraph) shall be included in all copies or substantial portions of the
10477+ * Software.
10478+ *
10479+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
10480+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
10481+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
10482+ * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
10483+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
10484+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
10485+ *
10486+ * Authors:
10487+ * Gareth Hughes <gareth@valinux.com>
10488+ * Frank C. Earl <fearl@airmail.net>
10489+ * Leif Delgass <ldelgass@retinalburn.net>
10490+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
10491+ */
10492+
10493+#ifndef __MACH64_DRV_H__
10494+#define __MACH64_DRV_H__
10495+
10496+/* General customization:
10497+ */
10498+
10499+#define DRIVER_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca"
10500+
10501+#define DRIVER_NAME "mach64"
10502+#define DRIVER_DESC "DRM module for the ATI Rage Pro"
10503+#define DRIVER_DATE "20060718"
10504+
10505+#define DRIVER_MAJOR 2
10506+#define DRIVER_MINOR 0
10507+#define DRIVER_PATCHLEVEL 0
10508+
10509+/* FIXME: remove these when not needed */
10510+/* Development driver options */
10511+#define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */
10512+#define MACH64_VERBOSE 0 /* Verbose debugging output */
10513+
10514+typedef struct drm_mach64_freelist {
10515+ struct list_head list; /* List pointers for free_list, placeholders, or pending list */
10516+ struct drm_buf *buf; /* Pointer to the buffer */
10517+ int discard; /* This flag is set when we're done (re)using a buffer */
10518+ u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */
10519+} drm_mach64_freelist_t;
10520+
10521+typedef struct drm_mach64_descriptor_ring {
10522+ void *start; /* write pointer (cpu address) to start of descriptor ring */
10523+ u32 start_addr; /* bus address of beginning of descriptor ring */
10524+ int size; /* size of ring in bytes */
10525+
10526+ u32 head_addr; /* bus address of descriptor ring head */
10527+ u32 head; /* dword offset of descriptor ring head */
10528+ u32 tail; /* dword offset of descriptor ring tail */
10529+ u32 tail_mask; /* mask used to wrap ring */
10530+ int space; /* number of free bytes in ring */
10531+} drm_mach64_descriptor_ring_t;
10532+
10533+typedef struct drm_mach64_private {
10534+ drm_mach64_sarea_t *sarea_priv;
10535+
10536+ int is_pci;
10537+ drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */
10538+
10539+ int usec_timeout; /* Timeout for the wait functions */
10540+
10541+ drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */
10542+ int ring_running; /* Is bus mastering is enabled */
10543+
10544+ struct list_head free_list; /* Free-list head */
10545+ struct list_head placeholders; /* Placeholder list for buffers held by clients */
10546+ struct list_head pending; /* Buffers pending completion */
10547+
10548+ u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */
10549+
10550+ unsigned int fb_bpp;
10551+ unsigned int front_offset, front_pitch;
10552+ unsigned int back_offset, back_pitch;
10553+
10554+ unsigned int depth_bpp;
10555+ unsigned int depth_offset, depth_pitch;
10556+
10557+ u32 front_offset_pitch;
10558+ u32 back_offset_pitch;
10559+ u32 depth_offset_pitch;
10560+
10561+ drm_local_map_t *sarea;
10562+ drm_local_map_t *fb;
10563+ drm_local_map_t *mmio;
10564+ drm_local_map_t *ring_map;
10565+ drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */
10566+ drm_local_map_t *agp_textures;
10567+} drm_mach64_private_t;
10568+
10569+extern struct drm_ioctl_desc mach64_ioctls[];
10570+extern int mach64_max_ioctl;
10571+
10572+ /* mach64_dma.c */
10573+extern int mach64_dma_init(struct drm_device *dev, void *data,
10574+ struct drm_file *file_priv);
10575+extern int mach64_dma_idle(struct drm_device *dev, void *data,
10576+ struct drm_file *file_priv);
10577+extern int mach64_dma_flush(struct drm_device *dev, void *data,
10578+ struct drm_file *file_priv);
10579+extern int mach64_engine_reset(struct drm_device *dev, void *data,
10580+ struct drm_file *file_priv);
10581+extern int mach64_dma_buffers(struct drm_device *dev, void *data,
10582+ struct drm_file *file_priv);
10583+extern void mach64_driver_lastclose(struct drm_device * dev);
10584+
10585+extern int mach64_init_freelist(struct drm_device * dev);
10586+extern void mach64_destroy_freelist(struct drm_device * dev);
10587+extern struct drm_buf *mach64_freelist_get(drm_mach64_private_t * dev_priv);
10588+extern int mach64_freelist_put(drm_mach64_private_t * dev_priv,
10589+ struct drm_buf * copy_buf);
10590+
10591+extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv,
10592+ int entries);
10593+extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv);
10594+extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n);
10595+extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv);
10596+extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv);
10597+extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv);
10598+extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv);
10599+extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv);
10600+
10601+extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv);
10602+extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv);
10603+extern int mach64_do_cleanup_dma(struct drm_device * dev);
10604+
10605+ /* mach64_state.c */
10606+extern int mach64_dma_clear(struct drm_device *dev, void *data,
10607+ struct drm_file *file_priv);
10608+extern int mach64_dma_swap(struct drm_device *dev, void *data,
10609+ struct drm_file *file_priv);
10610+extern int mach64_dma_vertex(struct drm_device *dev, void *data,
10611+ struct drm_file *file_priv);
10612+extern int mach64_dma_blit(struct drm_device *dev, void *data,
10613+ struct drm_file *file_priv);
10614+extern int mach64_get_param(struct drm_device *dev, void *data,
10615+ struct drm_file *file_priv);
10616+extern int mach64_driver_vblank_wait(struct drm_device * dev,
10617+ unsigned int *sequence);
10618+
10619+extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS);
10620+extern void mach64_driver_irq_preinstall(struct drm_device * dev);
10621+extern void mach64_driver_irq_postinstall(struct drm_device * dev);
10622+extern void mach64_driver_irq_uninstall(struct drm_device * dev);
10623+
10624+/* ================================================================
10625+ * Registers
10626+ */
10627+
10628+#define MACH64_AGP_BASE 0x0148
10629+#define MACH64_AGP_CNTL 0x014c
10630+#define MACH64_ALPHA_TST_CNTL 0x0550
10631+
10632+#define MACH64_DSP_CONFIG 0x0420
10633+#define MACH64_DSP_ON_OFF 0x0424
10634+#define MACH64_EXT_MEM_CNTL 0x04ac
10635+#define MACH64_GEN_TEST_CNTL 0x04d0
10636+#define MACH64_HW_DEBUG 0x047c
10637+#define MACH64_MEM_ADDR_CONFIG 0x0434
10638+#define MACH64_MEM_BUF_CNTL 0x042c
10639+#define MACH64_MEM_CNTL 0x04b0
10640+
10641+#define MACH64_BM_ADDR 0x0648
10642+#define MACH64_BM_COMMAND 0x0188
10643+#define MACH64_BM_DATA 0x0648
10644+#define MACH64_BM_FRAME_BUF_OFFSET 0x0180
10645+#define MACH64_BM_GUI_TABLE 0x01b8
10646+#define MACH64_BM_GUI_TABLE_CMD 0x064c
10647+# define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0)
10648+# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0)
10649+# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0)
10650+# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0)
10651+# define MACH64_LAST_DESCRIPTOR (1 << 31)
10652+#define MACH64_BM_HOSTDATA 0x0644
10653+#define MACH64_BM_STATUS 0x018c
10654+#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184
10655+#define MACH64_BM_SYSTEM_TABLE 0x01bc
10656+#define MACH64_BUS_CNTL 0x04a0
10657+# define MACH64_BUS_MSTR_RESET (1 << 1)
10658+# define MACH64_BUS_APER_REG_DIS (1 << 4)
10659+# define MACH64_BUS_FLUSH_BUF (1 << 2)
10660+# define MACH64_BUS_MASTER_DIS (1 << 6)
10661+# define MACH64_BUS_EXT_REG_EN (1 << 27)
10662+
10663+#define MACH64_CLR_CMP_CLR 0x0700
10664+#define MACH64_CLR_CMP_CNTL 0x0708
10665+#define MACH64_CLR_CMP_MASK 0x0704
10666+#define MACH64_CONFIG_CHIP_ID 0x04e0
10667+#define MACH64_CONFIG_CNTL 0x04dc
10668+#define MACH64_CONFIG_STAT0 0x04e4
10669+#define MACH64_CONFIG_STAT1 0x0494
10670+#define MACH64_CONFIG_STAT2 0x0498
10671+#define MACH64_CONTEXT_LOAD_CNTL 0x072c
10672+#define MACH64_CONTEXT_MASK 0x0720
10673+#define MACH64_COMPOSITE_SHADOW_ID 0x0798
10674+#define MACH64_CRC_SIG 0x04e8
10675+#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
10676+
10677+#define MACH64_DP_BKGD_CLR 0x06c0
10678+#define MACH64_DP_FOG_CLR 0x06c4
10679+#define MACH64_DP_FGRD_BKGD_CLR 0x06e0
10680+#define MACH64_DP_FRGD_CLR 0x06c4
10681+#define MACH64_DP_FGRD_CLR_MIX 0x06dc
10682+
10683+#define MACH64_DP_MIX 0x06d4
10684+# define BKGD_MIX_NOT_D (0 << 0)
10685+# define BKGD_MIX_ZERO (1 << 0)
10686+# define BKGD_MIX_ONE (2 << 0)
10687+# define MACH64_BKGD_MIX_D (3 << 0)
10688+# define BKGD_MIX_NOT_S (4 << 0)
10689+# define BKGD_MIX_D_XOR_S (5 << 0)
10690+# define BKGD_MIX_NOT_D_XOR_S (6 << 0)
10691+# define MACH64_BKGD_MIX_S (7 << 0)
10692+# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0)
10693+# define BKGD_MIX_D_OR_NOT_S (9 << 0)
10694+# define BKGD_MIX_NOT_D_OR_S (10 << 0)
10695+# define BKGD_MIX_D_OR_S (11 << 0)
10696+# define BKGD_MIX_D_AND_S (12 << 0)
10697+# define BKGD_MIX_NOT_D_AND_S (13 << 0)
10698+# define BKGD_MIX_D_AND_NOT_S (14 << 0)
10699+# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0)
10700+# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0)
10701+# define FRGD_MIX_NOT_D (0 << 16)
10702+# define FRGD_MIX_ZERO (1 << 16)
10703+# define FRGD_MIX_ONE (2 << 16)
10704+# define FRGD_MIX_D (3 << 16)
10705+# define FRGD_MIX_NOT_S (4 << 16)
10706+# define FRGD_MIX_D_XOR_S (5 << 16)
10707+# define FRGD_MIX_NOT_D_XOR_S (6 << 16)
10708+# define MACH64_FRGD_MIX_S (7 << 16)
10709+# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16)
10710+# define FRGD_MIX_D_OR_NOT_S (9 << 16)
10711+# define FRGD_MIX_NOT_D_OR_S (10 << 16)
10712+# define FRGD_MIX_D_OR_S (11 << 16)
10713+# define FRGD_MIX_D_AND_S (12 << 16)
10714+# define FRGD_MIX_NOT_D_AND_S (13 << 16)
10715+# define FRGD_MIX_D_AND_NOT_S (14 << 16)
10716+# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16)
10717+# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16)
10718+
10719+#define MACH64_DP_PIX_WIDTH 0x06d0
10720+# define MACH64_HOST_TRIPLE_ENABLE (1 << 13)
10721+# define MACH64_BYTE_ORDER_MSB_TO_LSB (0 << 24)
10722+# define MACH64_BYTE_ORDER_LSB_TO_MSB (1 << 24)
10723+
10724+#define MACH64_DP_SRC 0x06d8
10725+# define MACH64_BKGD_SRC_BKGD_CLR (0 << 0)
10726+# define MACH64_BKGD_SRC_FRGD_CLR (1 << 0)
10727+# define MACH64_BKGD_SRC_HOST (2 << 0)
10728+# define MACH64_BKGD_SRC_BLIT (3 << 0)
10729+# define MACH64_BKGD_SRC_PATTERN (4 << 0)
10730+# define MACH64_BKGD_SRC_3D (5 << 0)
10731+# define MACH64_FRGD_SRC_BKGD_CLR (0 << 8)
10732+# define MACH64_FRGD_SRC_FRGD_CLR (1 << 8)
10733+# define MACH64_FRGD_SRC_HOST (2 << 8)
10734+# define MACH64_FRGD_SRC_BLIT (3 << 8)
10735+# define MACH64_FRGD_SRC_PATTERN (4 << 8)
10736+# define MACH64_FRGD_SRC_3D (5 << 8)
10737+# define MACH64_MONO_SRC_ONE (0 << 16)
10738+# define MACH64_MONO_SRC_PATTERN (1 << 16)
10739+# define MACH64_MONO_SRC_HOST (2 << 16)
10740+# define MACH64_MONO_SRC_BLIT (3 << 16)
10741+
10742+#define MACH64_DP_WRITE_MASK 0x06c8
10743+
10744+#define MACH64_DST_CNTL 0x0530
10745+# define MACH64_DST_X_RIGHT_TO_LEFT (0 << 0)
10746+# define MACH64_DST_X_LEFT_TO_RIGHT (1 << 0)
10747+# define MACH64_DST_Y_BOTTOM_TO_TOP (0 << 1)
10748+# define MACH64_DST_Y_TOP_TO_BOTTOM (1 << 1)
10749+# define MACH64_DST_X_MAJOR (0 << 2)
10750+# define MACH64_DST_Y_MAJOR (1 << 2)
10751+# define MACH64_DST_X_TILE (1 << 3)
10752+# define MACH64_DST_Y_TILE (1 << 4)
10753+# define MACH64_DST_LAST_PEL (1 << 5)
10754+# define MACH64_DST_POLYGON_ENABLE (1 << 6)
10755+# define MACH64_DST_24_ROTATION_ENABLE (1 << 7)
10756+
10757+#define MACH64_DST_HEIGHT_WIDTH 0x0518
10758+#define MACH64_DST_OFF_PITCH 0x0500
10759+#define MACH64_DST_WIDTH_HEIGHT 0x06ec
10760+#define MACH64_DST_X_Y 0x06e8
10761+#define MACH64_DST_Y_X 0x050c
10762+
10763+#define MACH64_FIFO_STAT 0x0710
10764+# define MACH64_FIFO_SLOT_MASK 0x0000ffff
10765+# define MACH64_FIFO_ERR (1 << 31)
10766+
10767+#define MACH64_GEN_TEST_CNTL 0x04d0
10768+# define MACH64_GUI_ENGINE_ENABLE (1 << 8)
10769+#define MACH64_GUI_CMDFIFO_DEBUG 0x0170
10770+#define MACH64_GUI_CMDFIFO_DATA 0x0174
10771+#define MACH64_GUI_CNTL 0x0178
10772+# define MACH64_CMDFIFO_SIZE_MASK 0x00000003ul
10773+# define MACH64_CMDFIFO_SIZE_192 0x00000000ul
10774+# define MACH64_CMDFIFO_SIZE_128 0x00000001ul
10775+# define MACH64_CMDFIFO_SIZE_64 0x00000002ul
10776+#define MACH64_GUI_STAT 0x0738
10777+# define MACH64_GUI_ACTIVE (1 << 0)
10778+#define MACH64_GUI_TRAJ_CNTL 0x0730
10779+
10780+#define MACH64_HOST_CNTL 0x0640
10781+#define MACH64_HOST_DATA0 0x0600
10782+
10783+#define MACH64_ONE_OVER_AREA 0x029c
10784+#define MACH64_ONE_OVER_AREA_UC 0x0300
10785+
10786+#define MACH64_PAT_REG0 0x0680
10787+#define MACH64_PAT_REG1 0x0684
10788+
10789+#define MACH64_SC_LEFT 0x06a0
10790+#define MACH64_SC_RIGHT 0x06a4
10791+#define MACH64_SC_LEFT_RIGHT 0x06a8
10792+#define MACH64_SC_TOP 0x06ac
10793+#define MACH64_SC_BOTTOM 0x06b0
10794+#define MACH64_SC_TOP_BOTTOM 0x06b4
10795+
10796+#define MACH64_SCALE_3D_CNTL 0x05fc
10797+#define MACH64_SCRATCH_REG0 0x0480
10798+#define MACH64_SCRATCH_REG1 0x0484
10799+#define MACH64_SECONDARY_TEX_OFF 0x0778
10800+#define MACH64_SETUP_CNTL 0x0304
10801+#define MACH64_SRC_CNTL 0x05b4
10802+# define MACH64_SRC_BM_ENABLE (1 << 8)
10803+# define MACH64_SRC_BM_SYNC (1 << 9)
10804+# define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10)
10805+# define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10)
10806+# define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10)
10807+# define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10)
10808+#define MACH64_SRC_HEIGHT1 0x0594
10809+#define MACH64_SRC_HEIGHT2 0x05ac
10810+#define MACH64_SRC_HEIGHT1_WIDTH1 0x0598
10811+#define MACH64_SRC_HEIGHT2_WIDTH2 0x05b0
10812+#define MACH64_SRC_OFF_PITCH 0x0580
10813+#define MACH64_SRC_WIDTH1 0x0590
10814+#define MACH64_SRC_Y_X 0x058c
10815+
10816+#define MACH64_TEX_0_OFF 0x05c0
10817+#define MACH64_TEX_CNTL 0x0774
10818+#define MACH64_TEX_SIZE_PITCH 0x0770
10819+#define MACH64_TIMER_CONFIG 0x0428
10820+
10821+#define MACH64_VERTEX_1_ARGB 0x0254
10822+#define MACH64_VERTEX_1_S 0x0240
10823+#define MACH64_VERTEX_1_SECONDARY_S 0x0328
10824+#define MACH64_VERTEX_1_SECONDARY_T 0x032c
10825+#define MACH64_VERTEX_1_SECONDARY_W 0x0330
10826+#define MACH64_VERTEX_1_SPEC_ARGB 0x024c
10827+#define MACH64_VERTEX_1_T 0x0244
10828+#define MACH64_VERTEX_1_W 0x0248
10829+#define MACH64_VERTEX_1_X_Y 0x0258
10830+#define MACH64_VERTEX_1_Z 0x0250
10831+#define MACH64_VERTEX_2_ARGB 0x0274
10832+#define MACH64_VERTEX_2_S 0x0260
10833+#define MACH64_VERTEX_2_SECONDARY_S 0x0334
10834+#define MACH64_VERTEX_2_SECONDARY_T 0x0338
10835+#define MACH64_VERTEX_2_SECONDARY_W 0x033c
10836+#define MACH64_VERTEX_2_SPEC_ARGB 0x026c
10837+#define MACH64_VERTEX_2_T 0x0264
10838+#define MACH64_VERTEX_2_W 0x0268
10839+#define MACH64_VERTEX_2_X_Y 0x0278
10840+#define MACH64_VERTEX_2_Z 0x0270
10841+#define MACH64_VERTEX_3_ARGB 0x0294
10842+#define MACH64_VERTEX_3_S 0x0280
10843+#define MACH64_VERTEX_3_SECONDARY_S 0x02a0
10844+#define MACH64_VERTEX_3_SECONDARY_T 0x02a4
10845+#define MACH64_VERTEX_3_SECONDARY_W 0x02a8
10846+#define MACH64_VERTEX_3_SPEC_ARGB 0x028c
10847+#define MACH64_VERTEX_3_T 0x0284
10848+#define MACH64_VERTEX_3_W 0x0288
10849+#define MACH64_VERTEX_3_X_Y 0x0298
10850+#define MACH64_VERTEX_3_Z 0x0290
10851+
10852+#define MACH64_Z_CNTL 0x054c
10853+#define MACH64_Z_OFF_PITCH 0x0548
10854+
10855+#define MACH64_CRTC_VLINE_CRNT_VLINE 0x0410
10856+# define MACH64_CRTC_VLINE_MASK 0x000007ff
10857+# define MACH64_CRTC_CRNT_VLINE_MASK 0x07ff0000
10858+#define MACH64_CRTC_OFF_PITCH 0x0414
10859+#define MACH64_CRTC_INT_CNTL 0x0418
10860+# define MACH64_CRTC_VBLANK (1 << 0)
10861+# define MACH64_CRTC_VBLANK_INT_EN (1 << 1)
10862+# define MACH64_CRTC_VBLANK_INT (1 << 2)
10863+# define MACH64_CRTC_VLINE_INT_EN (1 << 3)
10864+# define MACH64_CRTC_VLINE_INT (1 << 4)
10865+# define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */
10866+# define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */
10867+# define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7)
10868+# define MACH64_CRTC_SNAPSHOT_INT (1 << 8)
10869+# define MACH64_CRTC_I2C_INT_EN (1 << 9)
10870+# define MACH64_CRTC_I2C_INT (1 << 10)
10871+# define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */
10872+# define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */
10873+# define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */
10874+# define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */
10875+# define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */
10876+# define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16)
10877+# define MACH64_CRTC_CAPBUF0_INT (1 << 17)
10878+# define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18)
10879+# define MACH64_CRTC_CAPBUF1_INT (1 << 19)
10880+# define MACH64_CRTC_OVERLAY_EOF_INT_EN (1 << 20)
10881+# define MACH64_CRTC_OVERLAY_EOF_INT (1 << 21)
10882+# define MACH64_CRTC_ONESHOT_CAP_INT_EN (1 << 22)
10883+# define MACH64_CRTC_ONESHOT_CAP_INT (1 << 23)
10884+# define MACH64_CRTC_BUSMASTER_EOL_INT_EN (1 << 24)
10885+# define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25)
10886+# define MACH64_CRTC_GP_INT_EN (1 << 26)
10887+# define MACH64_CRTC_GP_INT (1 << 27)
10888+# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */
10889+# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */
10890+# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */
10891+# define MACH64_CRTC_VBLANK2_INT (1 << 31)
10892+# define MACH64_CRTC_INT_ENS \
10893+ ( \
10894+ MACH64_CRTC_VBLANK_INT_EN | \
10895+ MACH64_CRTC_VLINE_INT_EN | \
10896+ MACH64_CRTC_SNAPSHOT_INT_EN | \
10897+ MACH64_CRTC_I2C_INT_EN | \
10898+ MACH64_CRTC2_VBLANK_INT_EN | \
10899+ MACH64_CRTC2_VLINE_INT_EN | \
10900+ MACH64_CRTC_CAPBUF0_INT_EN | \
10901+ MACH64_CRTC_CAPBUF1_INT_EN | \
10902+ MACH64_CRTC_OVERLAY_EOF_INT_EN | \
10903+ MACH64_CRTC_ONESHOT_CAP_INT_EN | \
10904+ MACH64_CRTC_BUSMASTER_EOL_INT_EN | \
10905+ MACH64_CRTC_GP_INT_EN | \
10906+ MACH64_CRTC_SNAPSHOT2_INT_EN | \
10907+ 0 \
10908+ )
10909+# define MACH64_CRTC_INT_ACKS \
10910+ ( \
10911+ MACH64_CRTC_VBLANK_INT | \
10912+ MACH64_CRTC_VLINE_INT | \
10913+ MACH64_CRTC_SNAPSHOT_INT | \
10914+ MACH64_CRTC_I2C_INT | \
10915+ MACH64_CRTC2_VBLANK_INT | \
10916+ MACH64_CRTC2_VLINE_INT | \
10917+ MACH64_CRTC_CAPBUF0_INT | \
10918+ MACH64_CRTC_CAPBUF1_INT | \
10919+ MACH64_CRTC_OVERLAY_EOF_INT | \
10920+ MACH64_CRTC_ONESHOT_CAP_INT | \
10921+ MACH64_CRTC_BUSMASTER_EOL_INT | \
10922+ MACH64_CRTC_GP_INT | \
10923+ MACH64_CRTC_SNAPSHOT2_INT | \
10924+ MACH64_CRTC_VBLANK2_INT | \
10925+ 0 \
10926+ )
10927+
10928+#define MACH64_DATATYPE_CI8 2
10929+#define MACH64_DATATYPE_ARGB1555 3
10930+#define MACH64_DATATYPE_RGB565 4
10931+#define MACH64_DATATYPE_ARGB8888 6
10932+#define MACH64_DATATYPE_RGB332 7
10933+#define MACH64_DATATYPE_Y8 8
10934+#define MACH64_DATATYPE_RGB8 9
10935+#define MACH64_DATATYPE_VYUY422 11
10936+#define MACH64_DATATYPE_YVYU422 12
10937+#define MACH64_DATATYPE_AYUV444 14
10938+#define MACH64_DATATYPE_ARGB4444 15
10939+
10940+#define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) )
10941+#define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) )
10942+
10943+#define DWMREG0 0x0400
10944+#define DWMREG0_END 0x07ff
10945+#define DWMREG1 0x0000
10946+#define DWMREG1_END 0x03ff
10947+
10948+#define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END))
10949+#define DMAREG0(r) (((r) - DWMREG0) >> 2)
10950+#define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100)
10951+#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
10952+
10953+#define MMREG0 0x0000
10954+#define MMREG0_END 0x00ff
10955+
10956+#define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END))
10957+#define MMSELECT0(r) (((r) << 2) + DWMREG0)
10958+#define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1))
10959+#define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r))
10960+
10961+/* ================================================================
10962+ * DMA constants
10963+ */
10964+
10965+/* DMA descriptor field indices:
10966+ * The descriptor fields are loaded into the read-only
10967+ * BM_* system bus master registers during a bus-master operation
10968+ */
10969+#define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */
10970+#define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */
10971+#define MACH64_DMA_COMMAND 2 /* BM_COMMAND */
10972+#define MACH64_DMA_RESERVED 3 /* BM_STATUS */
10973+
10974+/* BM_COMMAND descriptor field flags */
10975+#define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */
10976+#define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */
10977+
10978+#define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */
10979+#define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */
10980+
10981+/* ================================================================
10982+ * Misc helper macros
10983+ */
10984+
10985+static __inline__ void mach64_set_dma_eol(volatile u32 * addr)
10986+{
10987+#if defined(__i386__)
10988+ int nr = 31;
10989+
10990+ /* Taken from include/asm-i386/bitops.h linux header */
10991+ __asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr)
10992+ :"Ir"(nr));
10993+#elif defined(__powerpc__)
10994+ u32 old;
10995+ u32 mask = cpu_to_le32(MACH64_DMA_EOL);
10996+
10997+ /* Taken from the include/asm-ppc/bitops.h linux header */
10998+ __asm__ __volatile__("\n\
10999+1: lwarx %0,0,%3 \n\
11000+ or %0,%0,%2 \n\
11001+ stwcx. %0,0,%3 \n\
11002+ bne- 1b":"=&r"(old), "=m"(*addr)
11003+ :"r"(mask), "r"(addr), "m"(*addr)
11004+ :"cc");
11005+#elif defined(__alpha__)
11006+ u32 temp;
11007+ u32 mask = MACH64_DMA_EOL;
11008+
11009+ /* Taken from the include/asm-alpha/bitops.h linux header */
11010+ __asm__ __volatile__("1: ldl_l %0,%3\n"
11011+ " bis %0,%2,%0\n"
11012+ " stl_c %0,%1\n"
11013+ " beq %0,2f\n"
11014+ ".subsection 2\n"
11015+ "2: br 1b\n"
11016+ ".previous":"=&r"(temp), "=m"(*addr)
11017+ :"Ir"(mask), "m"(*addr));
11018+#else
11019+ u32 mask = cpu_to_le32(MACH64_DMA_EOL);
11020+
11021+ *addr |= mask;
11022+#endif
11023+}
11024+
11025+static __inline__ void mach64_clear_dma_eol(volatile u32 * addr)
11026+{
11027+#if defined(__i386__)
11028+ int nr = 31;
11029+
11030+ /* Taken from include/asm-i386/bitops.h linux header */
11031+ __asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr)
11032+ :"Ir"(nr));
11033+#elif defined(__powerpc__)
11034+ u32 old;
11035+ u32 mask = cpu_to_le32(MACH64_DMA_EOL);
11036+
11037+ /* Taken from the include/asm-ppc/bitops.h linux header */
11038+ __asm__ __volatile__("\n\
11039+1: lwarx %0,0,%3 \n\
11040+ andc %0,%0,%2 \n\
11041+ stwcx. %0,0,%3 \n\
11042+ bne- 1b":"=&r"(old), "=m"(*addr)
11043+ :"r"(mask), "r"(addr), "m"(*addr)
11044+ :"cc");
11045+#elif defined(__alpha__)
11046+ u32 temp;
11047+ u32 mask = ~MACH64_DMA_EOL;
11048+
11049+ /* Taken from the include/asm-alpha/bitops.h linux header */
11050+ __asm__ __volatile__("1: ldl_l %0,%3\n"
11051+ " and %0,%2,%0\n"
11052+ " stl_c %0,%1\n"
11053+ " beq %0,2f\n"
11054+ ".subsection 2\n"
11055+ "2: br 1b\n"
11056+ ".previous":"=&r"(temp), "=m"(*addr)
11057+ :"Ir"(mask), "m"(*addr));
11058+#else
11059+ u32 mask = cpu_to_le32(~MACH64_DMA_EOL);
11060+
11061+ *addr &= mask;
11062+#endif
11063+}
11064+
11065+static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv)
11066+{
11067+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
11068+
11069+ DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
11070+ __FUNCTION__,
11071+ ring->head_addr, ring->head, ring->tail, ring->space);
11072+
11073+ if (mach64_do_wait_for_idle(dev_priv) < 0) {
11074+ mach64_do_engine_reset(dev_priv);
11075+ }
11076+
11077+ if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
11078+ /* enable bus mastering and block 1 registers */
11079+ MACH64_WRITE(MACH64_BUS_CNTL,
11080+ (MACH64_READ(MACH64_BUS_CNTL) &
11081+ ~MACH64_BUS_MASTER_DIS)
11082+ | MACH64_BUS_EXT_REG_EN);
11083+ mach64_do_wait_for_idle(dev_priv);
11084+ }
11085+
11086+ /* reset descriptor table ring head */
11087+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
11088+ ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
11089+
11090+ dev_priv->ring_running = 1;
11091+}
11092+
11093+static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv,
11094+ drm_mach64_descriptor_ring_t * ring)
11095+{
11096+ DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
11097+ __FUNCTION__,
11098+ ring->head_addr, ring->head, ring->tail, ring->space);
11099+
11100+ /* reset descriptor table ring head */
11101+ MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
11102+ ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
11103+
11104+ if (dev_priv->driver_mode == MACH64_MODE_MMIO) {
11105+ mach64_do_dispatch_pseudo_dma(dev_priv);
11106+ } else {
11107+ /* enable GUI bus mastering, and sync the bus master to the GUI */
11108+ MACH64_WRITE(MACH64_SRC_CNTL,
11109+ MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
11110+ MACH64_SRC_BM_OP_SYSTEM_TO_REG);
11111+
11112+ /* kick off the transfer */
11113+ MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
11114+ if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) {
11115+ if ((mach64_do_wait_for_idle(dev_priv)) < 0) {
11116+ DRM_ERROR("%s: idle failed, resetting engine\n",
11117+ __FUNCTION__);
11118+ mach64_dump_engine_info(dev_priv);
11119+ mach64_do_engine_reset(dev_priv);
11120+ return;
11121+ }
11122+ mach64_do_release_used_buffers(dev_priv);
11123+ }
11124+ }
11125+}
11126+
11127+static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv,
11128+ drm_mach64_descriptor_ring_t * ring)
11129+{
11130+ DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
11131+ __FUNCTION__,
11132+ ring->head_addr, ring->head, ring->tail, ring->space);
11133+
11134+ if (!dev_priv->ring_running) {
11135+ mach64_ring_start(dev_priv);
11136+
11137+ if (ring->head != ring->tail) {
11138+ mach64_ring_resume(dev_priv, ring);
11139+ }
11140+ } else {
11141+ /* GUI_ACTIVE must be read before BM_GUI_TABLE to
11142+ * correctly determine the ring head
11143+ */
11144+ int gui_active =
11145+ MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;
11146+
11147+ ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0;
11148+
11149+ if (gui_active) {
11150+ /* If not idle, BM_GUI_TABLE points one descriptor
11151+ * past the current head
11152+ */
11153+ if (ring->head_addr == ring->start_addr) {
11154+ ring->head_addr += ring->size;
11155+ }
11156+ ring->head_addr -= 4 * sizeof(u32);
11157+ }
11158+
11159+ if (ring->head_addr < ring->start_addr ||
11160+ ring->head_addr >= ring->start_addr + ring->size) {
11161+ DRM_ERROR("bad ring head address: 0x%08x\n",
11162+ ring->head_addr);
11163+ mach64_dump_ring_info(dev_priv);
11164+ mach64_do_engine_reset(dev_priv);
11165+ return;
11166+ }
11167+
11168+ ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32);
11169+
11170+ if (!gui_active && ring->head != ring->tail) {
11171+ mach64_ring_resume(dev_priv, ring);
11172+ }
11173+ }
11174+}
11175+
11176+static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv)
11177+{
11178+ DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
11179+ __FUNCTION__,
11180+ dev_priv->ring.head_addr, dev_priv->ring.head,
11181+ dev_priv->ring.tail, dev_priv->ring.space);
11182+
11183+ /* restore previous SRC_CNTL to disable busmastering */
11184+ mach64_do_wait_for_fifo(dev_priv, 1);
11185+ MACH64_WRITE(MACH64_SRC_CNTL, 0);
11186+
11187+ /* disable busmastering but keep the block 1 registers enabled */
11188+ mach64_do_wait_for_idle(dev_priv);
11189+ MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL)
11190+ | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN);
11191+
11192+ dev_priv->ring_running = 0;
11193+}
11194+
11195+static __inline__ void
11196+mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv)
11197+{
11198+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
11199+
11200+ DRM_DEBUG("%s\n", __FUNCTION__);
11201+
11202+ mach64_ring_tick(dev_priv, ring);
11203+
11204+ ring->space = (ring->head - ring->tail) * sizeof(u32);
11205+ if (ring->space <= 0) {
11206+ ring->space += ring->size;
11207+ }
11208+}
11209+
11210+/* ================================================================
11211+ * DMA descriptor ring macros
11212+ */
11213+
11214+#define RING_LOCALS \
11215+ int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring
11216+
11217+#define RING_WRITE_OFS _ring_write
11218+
11219+#define BEGIN_RING( n ) \
11220+do { \
11221+ if ( MACH64_VERBOSE ) { \
11222+ DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
11223+ (n), __FUNCTION__ ); \
11224+ } \
11225+ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
11226+ int ret; \
11227+ if ((ret=mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \
11228+ DRM_ERROR( "wait_ring failed, resetting engine\n"); \
11229+ mach64_dump_engine_info( dev_priv ); \
11230+ mach64_do_engine_reset( dev_priv ); \
11231+ return ret; \
11232+ } \
11233+ } \
11234+ dev_priv->ring.space -= (n) * sizeof(u32); \
11235+ _ring = (u32 *) dev_priv->ring.start; \
11236+ _ring_tail = _ring_write = dev_priv->ring.tail; \
11237+ _ring_mask = dev_priv->ring.tail_mask; \
11238+} while (0)
11239+
11240+#define OUT_RING( x ) \
11241+do { \
11242+ if ( MACH64_VERBOSE ) { \
11243+ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
11244+ (unsigned int)(x), _ring_write ); \
11245+ } \
11246+ _ring[_ring_write++] = cpu_to_le32( x ); \
11247+ _ring_write &= _ring_mask; \
11248+} while (0)
11249+
11250+#define ADVANCE_RING() \
11251+do { \
11252+ if ( MACH64_VERBOSE ) { \
11253+ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
11254+ _ring_write, _ring_tail ); \
11255+ } \
11256+ DRM_MEMORYBARRIER(); \
11257+ mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \
11258+ DRM_MEMORYBARRIER(); \
11259+ dev_priv->ring.tail = _ring_write; \
11260+ mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \
11261+} while (0)
11262+
11263+/* ================================================================
11264+ * DMA macros
11265+ */
11266+
11267+#define DMALOCALS \
11268+ drm_mach64_freelist_t *_entry = NULL; \
11269+ struct drm_buf *_buf = NULL; \
11270+ u32 *_buf_wptr; int _outcount
11271+
11272+#define GETBUFPTR( __buf ) \
11273+((dev_priv->is_pci) ? \
11274+ ((u32 *)(__buf)->address) : \
11275+ ((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset)))
11276+
11277+#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address)
11278+
11279+#define GETRINGOFFSET() (_entry->ring_ofs)
11280+
11281+static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t *
11282+ dev_priv,
11283+ drm_mach64_freelist_t **
11284+ entry, struct drm_buf * buf)
11285+{
11286+ struct list_head *ptr;
11287+#if MACH64_EXTRA_CHECKING
11288+ if (list_empty(&dev_priv->pending)) {
11289+ DRM_ERROR("Empty pending list in %s\n", __FUNCTION__);
11290+ return -EINVAL;
11291+ }
11292+#endif
11293+ ptr = dev_priv->pending.prev;
11294+ *entry = list_entry(ptr, drm_mach64_freelist_t, list);
11295+ while ((*entry)->buf != buf) {
11296+ if (ptr == &dev_priv->pending) {
11297+ return -EFAULT;
11298+ }
11299+ ptr = ptr->prev;
11300+ *entry = list_entry(ptr, drm_mach64_freelist_t, list);
11301+ }
11302+ return 0;
11303+}
11304+
11305+#define DMASETPTR( _p ) \
11306+do { \
11307+ _buf = (_p); \
11308+ _outcount = 0; \
11309+ _buf_wptr = GETBUFPTR( _buf ); \
11310+} while(0)
11311+
11312+/* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */
11313+#define DMAGETPTR( file_priv, dev_priv, n ) \
11314+do { \
11315+ if ( MACH64_VERBOSE ) { \
11316+ DRM_INFO( "DMAGETPTR( %d ) in %s\n", \
11317+ n, __FUNCTION__ ); \
11318+ } \
11319+ _buf = mach64_freelist_get( dev_priv ); \
11320+ if (_buf == NULL) { \
11321+ DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", \
11322+ __FUNCTION__ ); \
11323+ return -EAGAIN; \
11324+ } \
11325+ if (_buf->pending) { \
11326+ DRM_ERROR("%s: pending buf in DMAGETPTR\n", \
11327+ __FUNCTION__ ); \
11328+ return -EFAULT; \
11329+ } \
11330+ _buf->file_priv = file_priv; \
11331+ _outcount = 0; \
11332+ \
11333+ _buf_wptr = GETBUFPTR( _buf ); \
11334+} while (0)
11335+
11336+#define DMAOUTREG( reg, val ) \
11337+do { \
11338+ if ( MACH64_VERBOSE ) { \
11339+ DRM_INFO( " DMAOUTREG( 0x%x = 0x%08x )\n", \
11340+ reg, val ); \
11341+ } \
11342+ _buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg)); \
11343+ _buf_wptr[_outcount++] = cpu_to_le32((val)); \
11344+ _buf->used += 8; \
11345+} while (0)
11346+
11347+#define DMAADVANCE( dev_priv, _discard ) \
11348+do { \
11349+ struct list_head *ptr; \
11350+ RING_LOCALS; \
11351+ \
11352+ if ( MACH64_VERBOSE ) { \
11353+ DRM_INFO( "DMAADVANCE() in %s\n", __FUNCTION__ ); \
11354+ } \
11355+ \
11356+ if (_buf->used <= 0) { \
11357+ DRM_ERROR( "DMAADVANCE() in %s: sending empty buf %d\n", \
11358+ __FUNCTION__, _buf->idx ); \
11359+ return -EFAULT; \
11360+ } \
11361+ if (_buf->pending) { \
11362+ /* This is a resued buffer, so we need to find it in the pending list */ \
11363+ int ret; \
11364+ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \
11365+ DRM_ERROR( "DMAADVANCE() in %s: couldn't find pending buf %d\n", \
11366+ __FUNCTION__, _buf->idx ); \
11367+ return ret; \
11368+ } \
11369+ if (_entry->discard) { \
11370+ DRM_ERROR( "DMAADVANCE() in %s: sending discarded pending buf %d\n", \
11371+ __FUNCTION__, _buf->idx ); \
11372+ return -EFAULT; \
11373+ } \
11374+ } else { \
11375+ if (list_empty(&dev_priv->placeholders)) { \
11376+ DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \
11377+ __FUNCTION__ ); \
11378+ return -EFAULT; \
11379+ } \
11380+ ptr = dev_priv->placeholders.next; \
11381+ list_del(ptr); \
11382+ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \
11383+ _buf->pending = 1; \
11384+ _entry->buf = _buf; \
11385+ list_add_tail(ptr, &dev_priv->pending); \
11386+ } \
11387+ _entry->discard = (_discard); \
11388+ ADD_BUF_TO_RING( dev_priv ); \
11389+} while (0)
11390+
11391+#define DMADISCARDBUF() \
11392+do { \
11393+ if (_entry == NULL) { \
11394+ int ret; \
11395+ if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \
11396+ DRM_ERROR( "%s: couldn't find pending buf %d\n", \
11397+ __FUNCTION__, _buf->idx ); \
11398+ return ret; \
11399+ } \
11400+ } \
11401+ _entry->discard = 1; \
11402+} while(0)
11403+
11404+#define ADD_BUF_TO_RING( dev_priv ) \
11405+do { \
11406+ int bytes, pages, remainder; \
11407+ u32 address, page; \
11408+ int i; \
11409+ \
11410+ bytes = _buf->used; \
11411+ address = GETBUFADDR( _buf ); \
11412+ \
11413+ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \
11414+ \
11415+ BEGIN_RING( pages * 4 ); \
11416+ \
11417+ for ( i = 0 ; i < pages-1 ; i++ ) { \
11418+ page = address + i * MACH64_DMA_CHUNKSIZE; \
11419+ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \
11420+ OUT_RING( page ); \
11421+ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \
11422+ OUT_RING( 0 ); \
11423+ } \
11424+ \
11425+ /* generate the final descriptor for any remaining commands in this buffer */ \
11426+ page = address + i * MACH64_DMA_CHUNKSIZE; \
11427+ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \
11428+ \
11429+ /* Save dword offset of last descriptor for this buffer. \
11430+ * This is needed to check for completion of the buffer in freelist_get \
11431+ */ \
11432+ _entry->ring_ofs = RING_WRITE_OFS; \
11433+ \
11434+ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \
11435+ OUT_RING( page ); \
11436+ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \
11437+ OUT_RING( 0 ); \
11438+ \
11439+ ADVANCE_RING(); \
11440+} while(0)
11441+
11442+#define DMAADVANCEHOSTDATA( dev_priv ) \
11443+do { \
11444+ struct list_head *ptr; \
11445+ RING_LOCALS; \
11446+ \
11447+ if ( MACH64_VERBOSE ) { \
11448+ DRM_INFO( "DMAADVANCEHOSTDATA() in %s\n", __FUNCTION__ ); \
11449+ } \
11450+ \
11451+ if (_buf->used <= 0) { \
11452+ DRM_ERROR( "DMAADVANCEHOSTDATA() in %s: sending empty buf %d\n", \
11453+ __FUNCTION__, _buf->idx ); \
11454+ return -EFAULT; \
11455+ } \
11456+ if (list_empty(&dev_priv->placeholders)) { \
11457+ DRM_ERROR( "%s: empty placeholder list in DMAADVANCEHOSTDATA()\n", \
11458+ __FUNCTION__ ); \
11459+ return -EFAULT; \
11460+ } \
11461+ \
11462+ ptr = dev_priv->placeholders.next; \
11463+ list_del(ptr); \
11464+ _entry = list_entry(ptr, drm_mach64_freelist_t, list); \
11465+ _entry->buf = _buf; \
11466+ _entry->buf->pending = 1; \
11467+ list_add_tail(ptr, &dev_priv->pending); \
11468+ _entry->discard = 1; \
11469+ ADD_HOSTDATA_BUF_TO_RING( dev_priv ); \
11470+} while (0)
11471+
11472+#define ADD_HOSTDATA_BUF_TO_RING( dev_priv ) \
11473+do { \
11474+ int bytes, pages, remainder; \
11475+ u32 address, page; \
11476+ int i; \
11477+ \
11478+ bytes = _buf->used - MACH64_HOSTDATA_BLIT_OFFSET; \
11479+ pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \
11480+ address = GETBUFADDR( _buf ); \
11481+ \
11482+ BEGIN_RING( 4 + pages * 4 ); \
11483+ \
11484+ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \
11485+ OUT_RING( address ); \
11486+ OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); \
11487+ OUT_RING( 0 ); \
11488+ \
11489+ address += MACH64_HOSTDATA_BLIT_OFFSET; \
11490+ \
11491+ for ( i = 0 ; i < pages-1 ; i++ ) { \
11492+ page = address + i * MACH64_DMA_CHUNKSIZE; \
11493+ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \
11494+ OUT_RING( page ); \
11495+ OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \
11496+ OUT_RING( 0 ); \
11497+ } \
11498+ \
11499+ /* generate the final descriptor for any remaining commands in this buffer */ \
11500+ page = address + i * MACH64_DMA_CHUNKSIZE; \
11501+ remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \
11502+ \
11503+ /* Save dword offset of last descriptor for this buffer. \
11504+ * This is needed to check for completion of the buffer in freelist_get \
11505+ */ \
11506+ _entry->ring_ofs = RING_WRITE_OFS; \
11507+ \
11508+ OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \
11509+ OUT_RING( page ); \
11510+ OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \
11511+ OUT_RING( 0 ); \
11512+ \
11513+ ADVANCE_RING(); \
11514+} while(0)
11515+
11516+#endif /* __MACH64_DRV_H__ */
11517Index: git/shared-core/mach64_irq.c
11518===================================================================
11519--- /dev/null 1970-01-01 00:00:00.000000000 +0000
11520+++ git/shared-core/mach64_irq.c 2008-12-12 17:35:22.000000000 +0000
11521@@ -0,0 +1,136 @@
11522+/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*-
11523+ * Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c
11524+ */
11525+/*-
11526+ * Copyright (C) The Weather Channel, Inc. 2002.
11527+ * Copyright 2003 Leif Delgass
11528+ * All Rights Reserved.
11529+ *
11530+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
11531+ * initial release of the Radeon 8500 driver under the XFree86 license.
11532+ * This notice must be preserved.
11533+ *
11534+ * Permission is hereby granted, free of charge, to any person obtaining a
11535+ * copy of this software and associated documentation files (the "Software"),
11536+ * to deal in the Software without restriction, including without limitation
11537+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11538+ * and/or sell copies of the Software, and to permit persons to whom the
11539+ * Software is furnished to do so, subject to the following conditions:
11540+ *
11541+ * The above copyright notice and this permission notice (including the next
11542+ * paragraph) shall be included in all copies or substantial portions of the
11543+ * Software.
11544+ *
11545+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
11546+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
11547+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
11548+ * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
11549+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
11550+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
11551+ * DEALINGS IN THE SOFTWARE.
11552+ *
11553+ * Authors:
11554+ * Keith Whitwell <keith@tungstengraphics.com>
11555+ * Eric Anholt <anholt@FreeBSD.org>
11556+ * Leif Delgass <ldelgass@retinalburn.net>
11557+ */
11558+
11559+#include "drmP.h"
11560+#include "drm.h"
11561+#include "mach64_drm.h"
11562+#include "mach64_drv.h"
11563+
11564+irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS)
11565+{
11566+ struct drm_device *dev = (struct drm_device *) arg;
11567+ drm_mach64_private_t *dev_priv =
11568+ (drm_mach64_private_t *) dev->dev_private;
11569+ int status;
11570+
11571+ status = MACH64_READ(MACH64_CRTC_INT_CNTL);
11572+
11573+ /* VBLANK interrupt */
11574+ if (status & MACH64_CRTC_VBLANK_INT) {
11575+ /* Mask off all interrupt ack bits before setting the ack bit, since
11576+ * there may be other handlers outside the DRM.
11577+ *
11578+ * NOTE: On mach64, you need to keep the enable bits set when doing
11579+ * the ack, despite what the docs say about not acking and enabling
11580+ * in a single write.
11581+ */
11582+ MACH64_WRITE(MACH64_CRTC_INT_CNTL,
11583+ (status & ~MACH64_CRTC_INT_ACKS)
11584+ | MACH64_CRTC_VBLANK_INT);
11585+
11586+ atomic_inc(&dev->vbl_received);
11587+ DRM_WAKEUP(&dev->vbl_queue);
11588+ drm_vbl_send_signals(dev);
11589+ return IRQ_HANDLED;
11590+ }
11591+ return IRQ_NONE;
11592+}
11593+
11594+int mach64_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
11595+{
11596+ unsigned int cur_vblank;
11597+ int ret = 0;
11598+
11599+ /* Assume that the user has missed the current sequence number
11600+ * by about a day rather than she wants to wait for years
11601+ * using vertical blanks...
11602+ */
11603+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
11604+ (((cur_vblank = atomic_read(&dev->vbl_received))
11605+ - *sequence) <= (1 << 23)));
11606+
11607+ *sequence = cur_vblank;
11608+
11609+ return ret;
11610+}
11611+
11612+/* drm_dma.h hooks
11613+*/
11614+void mach64_driver_irq_preinstall(struct drm_device * dev)
11615+{
11616+ drm_mach64_private_t *dev_priv =
11617+ (drm_mach64_private_t *) dev->dev_private;
11618+
11619+ u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL);
11620+
11621+ DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status);
11622+
11623+ /* Disable and clear VBLANK interrupt */
11624+ MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN)
11625+ | MACH64_CRTC_VBLANK_INT);
11626+}
11627+
11628+void mach64_driver_irq_postinstall(struct drm_device * dev)
11629+{
11630+ drm_mach64_private_t *dev_priv =
11631+ (drm_mach64_private_t *) dev->dev_private;
11632+
11633+ /* Turn on VBLANK interrupt */
11634+ MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL)
11635+ | MACH64_CRTC_VBLANK_INT_EN);
11636+
11637+ DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n",
11638+ MACH64_READ(MACH64_CRTC_INT_CNTL));
11639+
11640+}
11641+
11642+void mach64_driver_irq_uninstall(struct drm_device * dev)
11643+{
11644+ drm_mach64_private_t *dev_priv =
11645+ (drm_mach64_private_t *) dev->dev_private;
11646+ if (!dev_priv)
11647+ return;
11648+
11649+ /* Disable and clear VBLANK interrupt */
11650+ MACH64_WRITE(MACH64_CRTC_INT_CNTL,
11651+ (MACH64_READ(MACH64_CRTC_INT_CNTL) &
11652+ ~MACH64_CRTC_VBLANK_INT_EN)
11653+ | MACH64_CRTC_VBLANK_INT);
11654+
11655+ DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n",
11656+ MACH64_READ(MACH64_CRTC_INT_CNTL));
11657+}
11658Index: git/shared-core/mach64_state.c
11659===================================================================
11660--- /dev/null 1970-01-01 00:00:00.000000000 +0000
11661+++ git/shared-core/mach64_state.c 2008-12-12 17:35:22.000000000 +0000
11662@@ -0,0 +1,897 @@
11663+/* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
11664+ * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
11665+ */
11666+/*
11667+ * Copyright 2000 Gareth Hughes
11668+ * Copyright 2002-2003 Leif Delgass
11669+ * All Rights Reserved.
11670+ *
11671+ * Permission is hereby granted, free of charge, to any person obtaining a
11672+ * copy of this software and associated documentation files (the "Software"),
11673+ * to deal in the Software without restriction, including without limitation
11674+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11675+ * and/or sell copies of the Software, and to permit persons to whom the
11676+ * Software is furnished to do so, subject to the following conditions:
11677+ *
11678+ * The above copyright notice and this permission notice (including the next
11679+ * paragraph) shall be included in all copies or substantial portions of the
11680+ * Software.
11681+ *
11682+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
11683+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
11684+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
11685+ * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
11686+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
11687+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
11688+ *
11689+ * Authors:
11690+ * Gareth Hughes <gareth@valinux.com>
11691+ * Leif Delgass <ldelgass@retinalburn.net>
11692+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
11693+ */
11694+
11695+#include "drmP.h"
11696+#include "drm.h"
11697+#include "mach64_drm.h"
11698+#include "mach64_drv.h"
11699+
11700+/* Interface history:
11701+ *
11702+ * 1.0 - Initial mach64 DRM
11703+ *
11704+ */
11705+struct drm_ioctl_desc mach64_ioctls[] = {
11706+ DRM_IOCTL_DEF(DRM_MACH64_INIT, mach64_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
11707+ DRM_IOCTL_DEF(DRM_MACH64_CLEAR, mach64_dma_clear, DRM_AUTH),
11708+ DRM_IOCTL_DEF(DRM_MACH64_SWAP, mach64_dma_swap, DRM_AUTH),
11709+ DRM_IOCTL_DEF(DRM_MACH64_IDLE, mach64_dma_idle, DRM_AUTH),
11710+ DRM_IOCTL_DEF(DRM_MACH64_RESET, mach64_engine_reset, DRM_AUTH),
11711+ DRM_IOCTL_DEF(DRM_MACH64_VERTEX, mach64_dma_vertex, DRM_AUTH),
11712+ DRM_IOCTL_DEF(DRM_MACH64_BLIT, mach64_dma_blit, DRM_AUTH),
11713+ DRM_IOCTL_DEF(DRM_MACH64_FLUSH, mach64_dma_flush, DRM_AUTH),
11714+ DRM_IOCTL_DEF(DRM_MACH64_GETPARAM, mach64_get_param, DRM_AUTH),
11715+};
11716+
11717+int mach64_max_ioctl = DRM_ARRAY_SIZE(mach64_ioctls);
11718+
11719+/* ================================================================
11720+ * DMA hardware state programming functions
11721+ */
11722+
11723+static void mach64_print_dirty(const char *msg, unsigned int flags)
11724+{
11725+ DRM_DEBUG("%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n",
11726+ msg,
11727+ flags,
11728+ (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " :
11729+ "",
11730+ (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "",
11731+ (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " :
11732+ "", (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "",
11733+ (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " :
11734+ "",
11735+ (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "",
11736+ (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "",
11737+ (flags & MACH64_UPLOAD_MISC) ? "misc, " : "",
11738+ (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "",
11739+ (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "",
11740+ (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "",
11741+ (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "");
11742+}
11743+
11744+/* Mach64 doesn't have hardware cliprects, just one hardware scissor,
11745+ * so the GL scissor is intersected with each cliprect here
11746+ */
11747+/* This function returns 0 on success, 1 for no intersection, and
11748+ * negative for an error
11749+ */
11750+static int mach64_emit_cliprect(struct drm_file *file_priv,
11751+ drm_mach64_private_t * dev_priv,
11752+ struct drm_clip_rect * box)
11753+{
11754+ u32 sc_left_right, sc_top_bottom;
11755+ struct drm_clip_rect scissor;
11756+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
11757+ drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
11758+ DMALOCALS;
11759+
11760+ DRM_DEBUG("%s: box=%p\n", __FUNCTION__, box);
11761+
11762+ /* Get GL scissor */
11763+ /* FIXME: store scissor in SAREA as a cliprect instead of in
11764+ * hardware format, or do intersection client-side
11765+ */
11766+ scissor.x1 = regs->sc_left_right & 0xffff;
11767+ scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16;
11768+ scissor.y1 = regs->sc_top_bottom & 0xffff;
11769+ scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16;
11770+
11771+ /* Intersect GL scissor with cliprect */
11772+ if (box->x1 > scissor.x1)
11773+ scissor.x1 = box->x1;
11774+ if (box->y1 > scissor.y1)
11775+ scissor.y1 = box->y1;
11776+ if (box->x2 < scissor.x2)
11777+ scissor.x2 = box->x2;
11778+ if (box->y2 < scissor.y2)
11779+ scissor.y2 = box->y2;
11780+ /* positive return means skip */
11781+ if (scissor.x1 >= scissor.x2)
11782+ return 1;
11783+ if (scissor.y1 >= scissor.y2)
11784+ return 1;
11785+
11786+ DMAGETPTR(file_priv, dev_priv, 2); /* returns on failure to get buffer */
11787+
11788+ sc_left_right = ((scissor.x1 << 0) | (scissor.x2 << 16));
11789+ sc_top_bottom = ((scissor.y1 << 0) | (scissor.y2 << 16));
11790+
11791+ DMAOUTREG(MACH64_SC_LEFT_RIGHT, sc_left_right);
11792+ DMAOUTREG(MACH64_SC_TOP_BOTTOM, sc_top_bottom);
11793+
11794+ DMAADVANCE(dev_priv, 1);
11795+
11796+ return 0;
11797+}
11798+
11799+static __inline__ int mach64_emit_state(struct drm_file *file_priv,
11800+ drm_mach64_private_t * dev_priv)
11801+{
11802+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
11803+ drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
11804+ unsigned int dirty = sarea_priv->dirty;
11805+ u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
11806+ DMALOCALS;
11807+
11808+ if (MACH64_VERBOSE) {
11809+ mach64_print_dirty(__FUNCTION__, dirty);
11810+ } else {
11811+ DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
11812+ }
11813+
11814+ DMAGETPTR(file_priv, dev_priv, 17); /* returns on failure to get buffer */
11815+
11816+ if (dirty & MACH64_UPLOAD_MISC) {
11817+ DMAOUTREG(MACH64_DP_MIX, regs->dp_mix);
11818+ DMAOUTREG(MACH64_DP_SRC, regs->dp_src);
11819+ DMAOUTREG(MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl);
11820+ DMAOUTREG(MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl);
11821+ sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
11822+ }
11823+
11824+ if (dirty & MACH64_UPLOAD_DST_OFF_PITCH) {
11825+ DMAOUTREG(MACH64_DST_OFF_PITCH, regs->dst_off_pitch);
11826+ sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
11827+ }
11828+ if (dirty & MACH64_UPLOAD_Z_OFF_PITCH) {
11829+ DMAOUTREG(MACH64_Z_OFF_PITCH, regs->z_off_pitch);
11830+ sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
11831+ }
11832+ if (dirty & MACH64_UPLOAD_Z_ALPHA_CNTL) {
11833+ DMAOUTREG(MACH64_Z_CNTL, regs->z_cntl);
11834+ DMAOUTREG(MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl);
11835+ sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
11836+ }
11837+ if (dirty & MACH64_UPLOAD_SCALE_3D_CNTL) {
11838+ DMAOUTREG(MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl);
11839+ sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
11840+ }
11841+ if (dirty & MACH64_UPLOAD_DP_FOG_CLR) {
11842+ DMAOUTREG(MACH64_DP_FOG_CLR, regs->dp_fog_clr);
11843+ sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
11844+ }
11845+ if (dirty & MACH64_UPLOAD_DP_WRITE_MASK) {
11846+ DMAOUTREG(MACH64_DP_WRITE_MASK, regs->dp_write_mask);
11847+ sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
11848+ }
11849+ if (dirty & MACH64_UPLOAD_DP_PIX_WIDTH) {
11850+ DMAOUTREG(MACH64_DP_PIX_WIDTH, regs->dp_pix_width);
11851+ sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
11852+ }
11853+ if (dirty & MACH64_UPLOAD_SETUP_CNTL) {
11854+ DMAOUTREG(MACH64_SETUP_CNTL, regs->setup_cntl);
11855+ sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
11856+ }
11857+
11858+ if (dirty & MACH64_UPLOAD_TEXTURE) {
11859+ DMAOUTREG(MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch);
11860+ DMAOUTREG(MACH64_TEX_CNTL, regs->tex_cntl);
11861+ DMAOUTREG(MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off);
11862+ DMAOUTREG(MACH64_TEX_0_OFF + offset, regs->tex_offset);
11863+ sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
11864+ }
11865+
11866+ DMAADVANCE(dev_priv, 1);
11867+
11868+ sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS;
11869+
11870+ return 0;
11871+
11872+}
11873+
11874+/* ================================================================
11875+ * DMA command dispatch functions
11876+ */
11877+
11878+static int mach64_dma_dispatch_clear(struct drm_device * dev,
11879+ struct drm_file *file_priv,
11880+ unsigned int flags,
11881+ int cx, int cy, int cw, int ch,
11882+ unsigned int clear_color,
11883+ unsigned int clear_depth)
11884+{
11885+ drm_mach64_private_t *dev_priv = dev->dev_private;
11886+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
11887+ drm_mach64_context_regs_t *ctx = &sarea_priv->context_state;
11888+ int nbox = sarea_priv->nbox;
11889+ struct drm_clip_rect *pbox = sarea_priv->boxes;
11890+ u32 fb_bpp, depth_bpp;
11891+ int i;
11892+ DMALOCALS;
11893+
11894+ DRM_DEBUG("%s\n", __FUNCTION__);
11895+
11896+ switch (dev_priv->fb_bpp) {
11897+ case 16:
11898+ fb_bpp = MACH64_DATATYPE_RGB565;
11899+ break;
11900+ case 32:
11901+ fb_bpp = MACH64_DATATYPE_ARGB8888;
11902+ break;
11903+ default:
11904+ return -EINVAL;
11905+ }
11906+ switch (dev_priv->depth_bpp) {
11907+ case 16:
11908+ depth_bpp = MACH64_DATATYPE_RGB565;
11909+ break;
11910+ case 24:
11911+ case 32:
11912+ depth_bpp = MACH64_DATATYPE_ARGB8888;
11913+ break;
11914+ default:
11915+ return -EINVAL;
11916+ }
11917+
11918+ if (!nbox)
11919+ return 0;
11920+
11921+ DMAGETPTR(file_priv, dev_priv, nbox * 31); /* returns on failure to get buffer */
11922+
11923+ for (i = 0; i < nbox; i++) {
11924+ int x = pbox[i].x1;
11925+ int y = pbox[i].y1;
11926+ int w = pbox[i].x2 - x;
11927+ int h = pbox[i].y2 - y;
11928+
11929+ DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
11930+ pbox[i].x1, pbox[i].y1,
11931+ pbox[i].x2, pbox[i].y2, flags);
11932+
11933+ if (flags & (MACH64_FRONT | MACH64_BACK)) {
11934+ /* Setup for color buffer clears
11935+ */
11936+
11937+ DMAOUTREG(MACH64_Z_CNTL, 0);
11938+ DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
11939+
11940+ DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
11941+ DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
11942+
11943+ DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
11944+ DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
11945+ (MACH64_DST_X_LEFT_TO_RIGHT |
11946+ MACH64_DST_Y_TOP_TO_BOTTOM));
11947+
11948+ DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
11949+ (fb_bpp << 4) |
11950+ (fb_bpp << 8) |
11951+ (fb_bpp << 16) |
11952+ (fb_bpp << 28)));
11953+
11954+ DMAOUTREG(MACH64_DP_FRGD_CLR, clear_color);
11955+ DMAOUTREG(MACH64_DP_WRITE_MASK, ctx->dp_write_mask);
11956+ DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
11957+ MACH64_FRGD_MIX_S));
11958+ DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
11959+ MACH64_FRGD_SRC_FRGD_CLR |
11960+ MACH64_MONO_SRC_ONE));
11961+
11962+ }
11963+
11964+ if (flags & MACH64_FRONT) {
11965+
11966+ DMAOUTREG(MACH64_DST_OFF_PITCH,
11967+ dev_priv->front_offset_pitch);
11968+ DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
11969+ DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
11970+
11971+ }
11972+
11973+ if (flags & MACH64_BACK) {
11974+
11975+ DMAOUTREG(MACH64_DST_OFF_PITCH,
11976+ dev_priv->back_offset_pitch);
11977+ DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
11978+ DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
11979+
11980+ }
11981+
11982+ if (flags & MACH64_DEPTH) {
11983+ /* Setup for depth buffer clear
11984+ */
11985+ DMAOUTREG(MACH64_Z_CNTL, 0);
11986+ DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
11987+
11988+ DMAOUTREG(MACH64_SC_LEFT_RIGHT, ctx->sc_left_right);
11989+ DMAOUTREG(MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom);
11990+
11991+ DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
11992+ DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
11993+ (MACH64_DST_X_LEFT_TO_RIGHT |
11994+ MACH64_DST_Y_TOP_TO_BOTTOM));
11995+
11996+ DMAOUTREG(MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) |
11997+ (depth_bpp << 4) |
11998+ (depth_bpp << 8) |
11999+ (depth_bpp << 16) |
12000+ (depth_bpp << 28)));
12001+
12002+ DMAOUTREG(MACH64_DP_FRGD_CLR, clear_depth);
12003+ DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
12004+ DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D |
12005+ MACH64_FRGD_MIX_S));
12006+ DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR |
12007+ MACH64_FRGD_SRC_FRGD_CLR |
12008+ MACH64_MONO_SRC_ONE));
12009+
12010+ DMAOUTREG(MACH64_DST_OFF_PITCH,
12011+ dev_priv->depth_offset_pitch);
12012+ DMAOUTREG(MACH64_DST_X_Y, (y << 16) | x);
12013+ DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
12014+ }
12015+ }
12016+
12017+ DMAADVANCE(dev_priv, 1);
12018+
12019+ return 0;
12020+}
12021+
12022+static int mach64_dma_dispatch_swap(struct drm_device * dev,
12023+ struct drm_file *file_priv)
12024+{
12025+ drm_mach64_private_t *dev_priv = dev->dev_private;
12026+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12027+ int nbox = sarea_priv->nbox;
12028+ struct drm_clip_rect *pbox = sarea_priv->boxes;
12029+ u32 fb_bpp;
12030+ int i;
12031+ DMALOCALS;
12032+
12033+ DRM_DEBUG("%s\n", __FUNCTION__);
12034+
12035+ switch (dev_priv->fb_bpp) {
12036+ case 16:
12037+ fb_bpp = MACH64_DATATYPE_RGB565;
12038+ break;
12039+ case 32:
12040+ default:
12041+ fb_bpp = MACH64_DATATYPE_ARGB8888;
12042+ break;
12043+ }
12044+
12045+ if (!nbox)
12046+ return 0;
12047+
12048+ DMAGETPTR(file_priv, dev_priv, 13 + nbox * 4); /* returns on failure to get buffer */
12049+
12050+ DMAOUTREG(MACH64_Z_CNTL, 0);
12051+ DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
12052+
12053+ DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */
12054+ DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
12055+
12056+ DMAOUTREG(MACH64_CLR_CMP_CNTL, 0);
12057+ DMAOUTREG(MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT |
12058+ MACH64_DST_Y_TOP_TO_BOTTOM));
12059+
12060+ DMAOUTREG(MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) |
12061+ (fb_bpp << 4) |
12062+ (fb_bpp << 8) |
12063+ (fb_bpp << 16) | (fb_bpp << 28)));
12064+
12065+ DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff);
12066+ DMAOUTREG(MACH64_DP_MIX, (MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S));
12067+ DMAOUTREG(MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR |
12068+ MACH64_FRGD_SRC_BLIT | MACH64_MONO_SRC_ONE));
12069+
12070+ DMAOUTREG(MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch);
12071+ DMAOUTREG(MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch);
12072+
12073+ for (i = 0; i < nbox; i++) {
12074+ int x = pbox[i].x1;
12075+ int y = pbox[i].y1;
12076+ int w = pbox[i].x2 - x;
12077+ int h = pbox[i].y2 - y;
12078+
12079+ DRM_DEBUG("dispatch swap %d,%d-%d,%d\n",
12080+ pbox[i].x1, pbox[i].y1, pbox[i].x2, pbox[i].y2);
12081+
12082+ DMAOUTREG(MACH64_SRC_WIDTH1, w);
12083+ DMAOUTREG(MACH64_SRC_Y_X, (x << 16) | y);
12084+ DMAOUTREG(MACH64_DST_Y_X, (x << 16) | y);
12085+ DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (h << 16) | w);
12086+
12087+ }
12088+
12089+ DMAADVANCE(dev_priv, 1);
12090+
12091+ if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) {
12092+ for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) {
12093+ dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i + 1];
12094+ }
12095+ dev_priv->frame_ofs[i] = GETRINGOFFSET();
12096+
12097+ dev_priv->sarea_priv->frames_queued++;
12098+ }
12099+
12100+ return 0;
12101+}
12102+
12103+static int mach64_do_get_frames_queued(drm_mach64_private_t * dev_priv)
12104+{
12105+ drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
12106+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12107+ int i, start;
12108+ u32 head, tail, ofs;
12109+
12110+ DRM_DEBUG("%s\n", __FUNCTION__);
12111+
12112+ if (sarea_priv->frames_queued == 0)
12113+ return 0;
12114+
12115+ tail = ring->tail;
12116+ mach64_ring_tick(dev_priv, ring);
12117+ head = ring->head;
12118+
12119+ start = (MACH64_MAX_QUEUED_FRAMES -
12120+ DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued));
12121+
12122+ if (head == tail) {
12123+ sarea_priv->frames_queued = 0;
12124+ for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
12125+ dev_priv->frame_ofs[i] = ~0;
12126+ }
12127+ return 0;
12128+ }
12129+
12130+ for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) {
12131+ ofs = dev_priv->frame_ofs[i];
12132+ DRM_DEBUG("frame_ofs[%d] ofs: %d\n", i, ofs);
12133+ if (ofs == ~0 ||
12134+ (head < tail && (ofs < head || ofs >= tail)) ||
12135+ (head > tail && (ofs < head && ofs >= tail))) {
12136+ sarea_priv->frames_queued =
12137+ (MACH64_MAX_QUEUED_FRAMES - 1) - i;
12138+ dev_priv->frame_ofs[i] = ~0;
12139+ }
12140+ }
12141+
12142+ return sarea_priv->frames_queued;
12143+}
12144+
12145+/* Copy and verify a client submited buffer.
12146+ * FIXME: Make an assembly optimized version
12147+ */
12148+static __inline__ int copy_from_user_vertex(u32 *to,
12149+ const u32 __user *ufrom,
12150+ unsigned long bytes)
12151+{
12152+ unsigned long n = bytes; /* dwords remaining in buffer */
12153+ u32 *from, *orig_from;
12154+
12155+ from = drm_alloc(bytes, DRM_MEM_DRIVER);
12156+ if (from == NULL)
12157+ return -ENOMEM;
12158+
12159+ if (DRM_COPY_FROM_USER(from, ufrom, bytes)) {
12160+ drm_free(from, bytes, DRM_MEM_DRIVER);
12161+ return -EFAULT;
12162+ }
12163+ orig_from = from; /* we'll be modifying the "from" ptr, so save it */
12164+
12165+ n >>= 2;
12166+
12167+ while (n > 1) {
12168+ u32 data, reg, count;
12169+
12170+ data = *from++;
12171+
12172+ n--;
12173+
12174+ reg = le32_to_cpu(data);
12175+ count = (reg >> 16) + 1;
12176+ if (count <= n) {
12177+ n -= count;
12178+ reg &= 0xffff;
12179+
12180+ /* This is an exact match of Mach64's Setup Engine registers,
12181+ * excluding SETUP_CNTL (1_C1).
12182+ */
12183+ if ((reg >= 0x0190 && reg < 0x01c1) ||
12184+ (reg >= 0x01ca && reg <= 0x01cf)) {
12185+ *to++ = data;
12186+ memcpy(to, from, count << 2);
12187+ from += count;
12188+ to += count;
12189+ } else {
12190+ DRM_ERROR("%s: Got bad command: 0x%04x\n",
12191+ __FUNCTION__, reg);
12192+ drm_free(orig_from, bytes, DRM_MEM_DRIVER);
12193+ return -EACCES;
12194+ }
12195+ } else {
12196+ DRM_ERROR
12197+ ("%s: Got bad command count(=%u) dwords remaining=%lu\n",
12198+ __FUNCTION__, count, n);
12199+ drm_free(orig_from, bytes, DRM_MEM_DRIVER);
12200+ return -EINVAL;
12201+ }
12202+ }
12203+
12204+ drm_free(orig_from, bytes, DRM_MEM_DRIVER);
12205+ if (n == 0)
12206+ return 0;
12207+ else {
12208+ DRM_ERROR("%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes);
12209+ return -EINVAL;
12210+ }
12211+}
12212+
12213+static int mach64_dma_dispatch_vertex(struct drm_device * dev,
12214+ struct drm_file *file_priv,
12215+ drm_mach64_vertex_t * vertex)
12216+{
12217+ drm_mach64_private_t *dev_priv = dev->dev_private;
12218+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12219+ struct drm_buf *copy_buf;
12220+ void *buf = vertex->buf;
12221+ unsigned long used = vertex->used;
12222+ int ret = 0;
12223+ int i = 0;
12224+ int done = 0;
12225+ int verify_ret = 0;
12226+ DMALOCALS;
12227+
12228+ DRM_DEBUG("%s: buf=%p used=%lu nbox=%d\n",
12229+ __FUNCTION__, buf, used, sarea_priv->nbox);
12230+
12231+ if (!used)
12232+ goto _vertex_done;
12233+
12234+ copy_buf = mach64_freelist_get(dev_priv);
12235+ if (copy_buf == NULL) {
12236+ DRM_ERROR("%s: couldn't get buffer\n", __FUNCTION__);
12237+ return -EAGAIN;
12238+ }
12239+
12240+ verify_ret = copy_from_user_vertex(GETBUFPTR(copy_buf), buf, used);
12241+
12242+ if (verify_ret != 0) {
12243+ mach64_freelist_put(dev_priv, copy_buf);
12244+ goto _vertex_done;
12245+ }
12246+
12247+ copy_buf->used = used;
12248+
12249+ DMASETPTR(copy_buf);
12250+
12251+ if (sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS) {
12252+ ret = mach64_emit_state(file_priv, dev_priv);
12253+ if (ret < 0)
12254+ return ret;
12255+ }
12256+
12257+ do {
12258+ /* Emit the next cliprect */
12259+ if (i < sarea_priv->nbox) {
12260+ ret = mach64_emit_cliprect(file_priv, dev_priv,
12261+ &sarea_priv->boxes[i]);
12262+ if (ret < 0) {
12263+ /* failed to get buffer */
12264+ return ret;
12265+ } else if (ret != 0) {
12266+ /* null intersection with scissor */
12267+ continue;
12268+ }
12269+ }
12270+ if ((i >= sarea_priv->nbox - 1))
12271+ done = 1;
12272+
12273+ /* Add the buffer to the DMA queue */
12274+ DMAADVANCE(dev_priv, done);
12275+
12276+ } while (++i < sarea_priv->nbox);
12277+
12278+ if (!done) {
12279+ if (copy_buf->pending) {
12280+ DMADISCARDBUF();
12281+ } else {
12282+ /* This buffer wasn't used (no cliprects), so place it
12283+ * back on the free list
12284+ */
12285+ mach64_freelist_put(dev_priv, copy_buf);
12286+ }
12287+ }
12288+
12289+_vertex_done:
12290+ sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
12291+ sarea_priv->nbox = 0;
12292+
12293+ return verify_ret;
12294+}
12295+
12296+static __inline__ int copy_from_user_blit(u32 *to,
12297+ const u32 __user *ufrom,
12298+ unsigned long bytes)
12299+{
12300+ to = (u32 *)((char *)to + MACH64_HOSTDATA_BLIT_OFFSET);
12301+
12302+ if (DRM_COPY_FROM_USER(to, ufrom, bytes)) {
12303+ return -EFAULT;
12304+ }
12305+
12306+ return 0;
12307+}
12308+
12309+static int mach64_dma_dispatch_blit(struct drm_device * dev,
12310+ struct drm_file *file_priv,
12311+ drm_mach64_blit_t * blit)
12312+{
12313+ drm_mach64_private_t *dev_priv = dev->dev_private;
12314+ int dword_shift, dwords;
12315+ unsigned long used;
12316+ struct drm_buf *copy_buf;
12317+ int verify_ret = 0;
12318+ DMALOCALS;
12319+
12320+ /* The compiler won't optimize away a division by a variable,
12321+ * even if the only legal values are powers of two. Thus, we'll
12322+ * use a shift instead.
12323+ */
12324+ switch (blit->format) {
12325+ case MACH64_DATATYPE_ARGB8888:
12326+ dword_shift = 0;
12327+ break;
12328+ case MACH64_DATATYPE_ARGB1555:
12329+ case MACH64_DATATYPE_RGB565:
12330+ case MACH64_DATATYPE_VYUY422:
12331+ case MACH64_DATATYPE_YVYU422:
12332+ case MACH64_DATATYPE_ARGB4444:
12333+ dword_shift = 1;
12334+ break;
12335+ case MACH64_DATATYPE_CI8:
12336+ case MACH64_DATATYPE_RGB8:
12337+ dword_shift = 2;
12338+ break;
12339+ default:
12340+ DRM_ERROR("invalid blit format %d\n", blit->format);
12341+ return -EINVAL;
12342+ }
12343+
12344+ /* Set buf->used to the bytes of blit data based on the blit dimensions
12345+ * and verify the size. When the setup is emitted to the buffer with
12346+ * the DMA* macros below, buf->used is incremented to include the bytes
12347+ * used for setup as well as the blit data.
12348+ */
12349+ dwords = (blit->width * blit->height) >> dword_shift;
12350+ used = dwords << 2;
12351+ if (used <= 0 ||
12352+ used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET) {
12353+ DRM_ERROR("Invalid blit size: %lu bytes\n", used);
12354+ return -EINVAL;
12355+ }
12356+
12357+ copy_buf = mach64_freelist_get(dev_priv);
12358+ if (copy_buf == NULL) {
12359+ DRM_ERROR("%s: couldn't get buffer\n", __FUNCTION__);
12360+ return -EAGAIN;
12361+ }
12362+
12363+ verify_ret = copy_from_user_blit(GETBUFPTR(copy_buf), blit->buf, used);
12364+
12365+ if (verify_ret != 0) {
12366+ mach64_freelist_put(dev_priv, copy_buf);
12367+ goto _blit_done;
12368+ }
12369+
12370+ copy_buf->used = used;
12371+
12372+ /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent,
12373+ * continuation buffers?
12374+ */
12375+
12376+ /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require
12377+ * a register command every 16 dwords. State setup is added at the start of the
12378+ * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET
12379+ */
12380+ DMASETPTR(copy_buf);
12381+
12382+ DMAOUTREG(MACH64_Z_CNTL, 0);
12383+ DMAOUTREG(MACH64_SCALE_3D_CNTL, 0);
12384+
12385+ DMAOUTREG(MACH64_SC_LEFT_RIGHT, 0 | (8191 << 16)); /* no scissor */
12386+ DMAOUTREG(MACH64_SC_TOP_BOTTOM, 0 | (16383 << 16));
12387+
12388+ DMAOUTREG(MACH64_CLR_CMP_CNTL, 0); /* disable */
12389+ DMAOUTREG(MACH64_GUI_TRAJ_CNTL,
12390+ MACH64_DST_X_LEFT_TO_RIGHT | MACH64_DST_Y_TOP_TO_BOTTOM);
12391+
12392+ DMAOUTREG(MACH64_DP_PIX_WIDTH, (blit->format << 0) /* dst pix width */
12393+ |(blit->format << 4) /* composite pix width */
12394+ |(blit->format << 8) /* src pix width */
12395+ |(blit->format << 16) /* host data pix width */
12396+ |(blit->format << 28) /* scaler/3D pix width */
12397+ );
12398+
12399+ DMAOUTREG(MACH64_DP_WRITE_MASK, 0xffffffff); /* enable all planes */
12400+ DMAOUTREG(MACH64_DP_MIX, MACH64_BKGD_MIX_D | MACH64_FRGD_MIX_S);
12401+ DMAOUTREG(MACH64_DP_SRC,
12402+ MACH64_BKGD_SRC_BKGD_CLR
12403+ | MACH64_FRGD_SRC_HOST | MACH64_MONO_SRC_ONE);
12404+
12405+ DMAOUTREG(MACH64_DST_OFF_PITCH,
12406+ (blit->pitch << 22) | (blit->offset >> 3));
12407+ DMAOUTREG(MACH64_DST_X_Y, (blit->y << 16) | blit->x);
12408+ DMAOUTREG(MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width);
12409+
12410+ DRM_DEBUG("%s: %lu bytes\n", __FUNCTION__, used);
12411+
12412+ /* Add the buffer to the queue */
12413+ DMAADVANCEHOSTDATA(dev_priv);
12414+
12415+_blit_done:
12416+ return verify_ret;
12417+}
12418+
12419+/* ================================================================
12420+ * IOCTL functions
12421+ */
12422+
12423+int mach64_dma_clear(struct drm_device *dev, void *data,
12424+ struct drm_file *file_priv)
12425+{
12426+ drm_mach64_private_t *dev_priv = dev->dev_private;
12427+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12428+ drm_mach64_clear_t *clear = data;
12429+ int ret;
12430+
12431+ DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID);
12432+
12433+ LOCK_TEST_WITH_RETURN(dev, file_priv);
12434+
12435+ if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
12436+ sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
12437+
12438+ ret = mach64_dma_dispatch_clear(dev, file_priv, clear->flags,
12439+ clear->x, clear->y, clear->w, clear->h,
12440+ clear->clear_color,
12441+ clear->clear_depth);
12442+
12443+ /* Make sure we restore the 3D state next time.
12444+ */
12445+ sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
12446+ return ret;
12447+}
12448+
12449+int mach64_dma_swap(struct drm_device *dev, void *data,
12450+ struct drm_file *file_priv)
12451+{
12452+ drm_mach64_private_t *dev_priv = dev->dev_private;
12453+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12454+ int ret;
12455+
12456+ DRM_DEBUG("%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID);
12457+
12458+ LOCK_TEST_WITH_RETURN(dev, file_priv);
12459+
12460+ if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
12461+ sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
12462+
12463+ ret = mach64_dma_dispatch_swap(dev, file_priv);
12464+
12465+ /* Make sure we restore the 3D state next time.
12466+ */
12467+ sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | MACH64_UPLOAD_MISC);
12468+ return ret;
12469+}
12470+
12471+int mach64_dma_vertex(struct drm_device *dev, void *data,
12472+ struct drm_file *file_priv)
12473+{
12474+ drm_mach64_private_t *dev_priv = dev->dev_private;
12475+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12476+ drm_mach64_vertex_t *vertex = data;
12477+
12478+ LOCK_TEST_WITH_RETURN(dev, file_priv);
12479+
12480+ if (!dev_priv) {
12481+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
12482+ return -EINVAL;
12483+ }
12484+
12485+ DRM_DEBUG("%s: pid=%d buf=%p used=%lu discard=%d\n",
12486+ __FUNCTION__, DRM_CURRENTPID,
12487+ vertex->buf, vertex->used, vertex->discard);
12488+
12489+ if (vertex->prim < 0 || vertex->prim > MACH64_PRIM_POLYGON) {
12490+ DRM_ERROR("buffer prim %d\n", vertex->prim);
12491+ return -EINVAL;
12492+ }
12493+
12494+ if (vertex->used > MACH64_BUFFER_SIZE || (vertex->used & 3) != 0) {
12495+ DRM_ERROR("Invalid vertex buffer size: %lu bytes\n",
12496+ vertex->used);
12497+ return -EINVAL;
12498+ }
12499+
12500+ if (sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS)
12501+ sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS;
12502+
12503+ return mach64_dma_dispatch_vertex(dev, file_priv, vertex);
12504+}
12505+
12506+int mach64_dma_blit(struct drm_device *dev, void *data,
12507+ struct drm_file *file_priv)
12508+{
12509+ drm_mach64_private_t *dev_priv = dev->dev_private;
12510+ drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv;
12511+ drm_mach64_blit_t *blit = data;
12512+ int ret;
12513+
12514+ LOCK_TEST_WITH_RETURN(dev, file_priv);
12515+
12516+ ret = mach64_dma_dispatch_blit(dev, file_priv, blit);
12517+
12518+ /* Make sure we restore the 3D state next time.
12519+ */
12520+ sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
12521+ MACH64_UPLOAD_MISC | MACH64_UPLOAD_CLIPRECTS);
12522+
12523+ return ret;
12524+}
12525+
12526+int mach64_get_param(struct drm_device *dev, void *data,
12527+ struct drm_file *file_priv)
12528+{
12529+ drm_mach64_private_t *dev_priv = dev->dev_private;
12530+ drm_mach64_getparam_t *param = data;
12531+ int value;
12532+
12533+ DRM_DEBUG("%s\n", __FUNCTION__);
12534+
12535+ if (!dev_priv) {
12536+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
12537+ return -EINVAL;
12538+ }
12539+
12540+ switch (param->param) {
12541+ case MACH64_PARAM_FRAMES_QUEUED:
12542+ /* Needs lock since it calls mach64_ring_tick() */
12543+ LOCK_TEST_WITH_RETURN(dev, file_priv);
12544+ value = mach64_do_get_frames_queued(dev_priv);
12545+ break;
12546+ case MACH64_PARAM_IRQ_NR:
12547+ value = dev->irq;
12548+ break;
12549+ default:
12550+ return -EINVAL;
12551+ }
12552+
12553+ if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
12554+ DRM_ERROR("copy_to_user\n");
12555+ return -EFAULT;
12556+ }
12557+
12558+ return 0;
12559+}
12560Index: git/shared-core/mga_dma.c
12561===================================================================
12562--- /dev/null 1970-01-01 00:00:00.000000000 +0000
12563+++ git/shared-core/mga_dma.c 2008-12-12 17:35:22.000000000 +0000
12564@@ -0,0 +1,1164 @@
12565+/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
12566+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
12567+ */
12568+/* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
12569+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12570+ * All Rights Reserved.
12571+ *
12572+ * Permission is hereby granted, free of charge, to any person obtaining a
12573+ * copy of this software and associated documentation files (the "Software"),
12574+ * to deal in the Software without restriction, including without limitation
12575+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12576+ * and/or sell copies of the Software, and to permit persons to whom the
12577+ * Software is furnished to do so, subject to the following conditions:
12578+ *
12579+ * The above copyright notice and this permission notice (including the next
12580+ * paragraph) shall be included in all copies or substantial portions of the
12581+ * Software.
12582+ *
12583+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
12584+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
12585+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
12586+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
12587+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
12588+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
12589+ * DEALINGS IN THE SOFTWARE.
12590+ */
12591+
12592+/**
12593+ * \file mga_dma.c
12594+ * DMA support for MGA G200 / G400.
12595+ *
12596+ * \author Rickard E. (Rik) Faith <faith@valinux.com>
12597+ * \author Jeff Hartmann <jhartmann@valinux.com>
12598+ * \author Keith Whitwell <keith@tungstengraphics.com>
12599+ * \author Gareth Hughes <gareth@valinux.com>
12600+ */
12601+
12602+#include "drmP.h"
12603+#include "drm.h"
12604+#include "drm_sarea.h"
12605+#include "mga_drm.h"
12606+#include "mga_drv.h"
12607+
12608+#define MGA_DEFAULT_USEC_TIMEOUT 10000
12609+#define MGA_FREELIST_DEBUG 0
12610+
12611+#define MINIMAL_CLEANUP 0
12612+#define FULL_CLEANUP 1
12613+static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup);
12614+
12615+/* ================================================================
12616+ * Engine control
12617+ */
12618+
12619+int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
12620+{
12621+ u32 status = 0;
12622+ int i;
12623+ DRM_DEBUG("\n");
12624+
12625+ for (i = 0; i < dev_priv->usec_timeout; i++) {
12626+ status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
12627+ if (status == MGA_ENDPRDMASTS) {
12628+ MGA_WRITE8(MGA_CRTC_INDEX, 0);
12629+ return 0;
12630+ }
12631+ DRM_UDELAY(1);
12632+ }
12633+
12634+#if MGA_DMA_DEBUG
12635+ DRM_ERROR("failed!\n");
12636+ DRM_INFO(" status=0x%08x\n", status);
12637+#endif
12638+ return -EBUSY;
12639+}
12640+
12641+static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
12642+{
12643+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
12644+ drm_mga_primary_buffer_t *primary = &dev_priv->prim;
12645+
12646+ DRM_DEBUG("\n");
12647+
12648+ /* The primary DMA stream should look like new right about now.
12649+ */
12650+ primary->tail = 0;
12651+ primary->space = primary->size;
12652+ primary->last_flush = 0;
12653+
12654+ sarea_priv->last_wrap = 0;
12655+
12656+ /* FIXME: Reset counters, buffer ages etc...
12657+ */
12658+
12659+ /* FIXME: What else do we need to reinitialize? WARP stuff?
12660+ */
12661+
12662+ return 0;
12663+}
12664+
12665+/* ================================================================
12666+ * Primary DMA stream
12667+ */
12668+
12669+void mga_do_dma_flush(drm_mga_private_t * dev_priv)
12670+{
12671+ drm_mga_primary_buffer_t *primary = &dev_priv->prim;
12672+ u32 head, tail;
12673+ u32 status = 0;
12674+ int i;
12675+ DMA_LOCALS;
12676+ DRM_DEBUG("\n");
12677+
12678+ /* We need to wait so that we can do an safe flush */
12679+ for (i = 0; i < dev_priv->usec_timeout; i++) {
12680+ status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
12681+ if (status == MGA_ENDPRDMASTS)
12682+ break;
12683+ DRM_UDELAY(1);
12684+ }
12685+
12686+ if (primary->tail == primary->last_flush) {
12687+ DRM_DEBUG(" bailing out...\n");
12688+ return;
12689+ }
12690+
12691+ tail = primary->tail + dev_priv->primary->offset;
12692+
12693+ /* We need to pad the stream between flushes, as the card
12694+ * actually (partially?) reads the first of these commands.
12695+ * See page 4-16 in the G400 manual, middle of the page or so.
12696+ */
12697+ BEGIN_DMA(1);
12698+
12699+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
12700+ MGA_DMAPAD, 0x00000000,
12701+ MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
12702+
12703+ ADVANCE_DMA();
12704+
12705+ primary->last_flush = primary->tail;
12706+
12707+ head = MGA_READ(MGA_PRIMADDRESS);
12708+
12709+ if (head <= tail) {
12710+ primary->space = primary->size - primary->tail;
12711+ } else {
12712+ primary->space = head - tail;
12713+ }
12714+
12715+ DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
12716+ DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
12717+ DRM_DEBUG(" space = 0x%06x\n", primary->space);
12718+
12719+ mga_flush_write_combine();
12720+ MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
12721+
12722+ DRM_DEBUG("done.\n");
12723+}
12724+
12725+void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
12726+{
12727+ drm_mga_primary_buffer_t *primary = &dev_priv->prim;
12728+ u32 head, tail;
12729+ DMA_LOCALS;
12730+ DRM_DEBUG("\n");
12731+
12732+ BEGIN_DMA_WRAP();
12733+
12734+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
12735+ MGA_DMAPAD, 0x00000000,
12736+ MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
12737+
12738+ ADVANCE_DMA();
12739+
12740+ tail = primary->tail + dev_priv->primary->offset;
12741+
12742+ primary->tail = 0;
12743+ primary->last_flush = 0;
12744+ primary->last_wrap++;
12745+
12746+ head = MGA_READ(MGA_PRIMADDRESS);
12747+
12748+ if (head == dev_priv->primary->offset) {
12749+ primary->space = primary->size;
12750+ } else {
12751+ primary->space = head - dev_priv->primary->offset;
12752+ }
12753+
12754+ DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
12755+ DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
12756+ DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
12757+ DRM_DEBUG(" space = 0x%06x\n", primary->space);
12758+
12759+ mga_flush_write_combine();
12760+ MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
12761+
12762+ set_bit(0, &primary->wrapped);
12763+ DRM_DEBUG("done.\n");
12764+}
12765+
12766+void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
12767+{
12768+ drm_mga_primary_buffer_t *primary = &dev_priv->prim;
12769+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
12770+ u32 head = dev_priv->primary->offset;
12771+ DRM_DEBUG("\n");
12772+
12773+ sarea_priv->last_wrap++;
12774+ DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
12775+
12776+ mga_flush_write_combine();
12777+ MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
12778+
12779+ clear_bit(0, &primary->wrapped);
12780+ DRM_DEBUG("done.\n");
12781+}
12782+
12783+/* ================================================================
12784+ * Freelist management
12785+ */
12786+
12787+#define MGA_BUFFER_USED ~0
12788+#define MGA_BUFFER_FREE 0
12789+
12790+#if MGA_FREELIST_DEBUG
12791+static void mga_freelist_print(struct drm_device * dev)
12792+{
12793+ drm_mga_private_t *dev_priv = dev->dev_private;
12794+ drm_mga_freelist_t *entry;
12795+
12796+ DRM_INFO("\n");
12797+ DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
12798+ dev_priv->sarea_priv->last_dispatch,
12799+ (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
12800+ dev_priv->primary->offset));
12801+ DRM_INFO("current freelist:\n");
12802+
12803+ for (entry = dev_priv->head->next; entry; entry = entry->next) {
12804+ DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
12805+ entry, entry->buf->idx, entry->age.head,
12806+ entry->age.head - dev_priv->primary->offset);
12807+ }
12808+ DRM_INFO("\n");
12809+}
12810+#endif
12811+
12812+static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
12813+{
12814+ struct drm_device_dma *dma = dev->dma;
12815+ struct drm_buf *buf;
12816+ drm_mga_buf_priv_t *buf_priv;
12817+ drm_mga_freelist_t *entry;
12818+ int i;
12819+ DRM_DEBUG("count=%d\n", dma->buf_count);
12820+
12821+ dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
12822+ if (dev_priv->head == NULL)
12823+ return -ENOMEM;
12824+
12825+ memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
12826+ SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
12827+
12828+ for (i = 0; i < dma->buf_count; i++) {
12829+ buf = dma->buflist[i];
12830+ buf_priv = buf->dev_private;
12831+
12832+ entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
12833+ if (entry == NULL)
12834+ return -ENOMEM;
12835+
12836+ memset(entry, 0, sizeof(drm_mga_freelist_t));
12837+
12838+ entry->next = dev_priv->head->next;
12839+ entry->prev = dev_priv->head;
12840+ SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
12841+ entry->buf = buf;
12842+
12843+ if (dev_priv->head->next != NULL)
12844+ dev_priv->head->next->prev = entry;
12845+ if (entry->next == NULL)
12846+ dev_priv->tail = entry;
12847+
12848+ buf_priv->list_entry = entry;
12849+ buf_priv->discard = 0;
12850+ buf_priv->dispatched = 0;
12851+
12852+ dev_priv->head->next = entry;
12853+ }
12854+
12855+ return 0;
12856+}
12857+
12858+static void mga_freelist_cleanup(struct drm_device * dev)
12859+{
12860+ drm_mga_private_t *dev_priv = dev->dev_private;
12861+ drm_mga_freelist_t *entry;
12862+ drm_mga_freelist_t *next;
12863+ DRM_DEBUG("\n");
12864+
12865+ entry = dev_priv->head;
12866+ while (entry) {
12867+ next = entry->next;
12868+ drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
12869+ entry = next;
12870+ }
12871+
12872+ dev_priv->head = dev_priv->tail = NULL;
12873+}
12874+
12875+#if 0
12876+/* FIXME: Still needed?
12877+ */
12878+static void mga_freelist_reset(struct drm_device * dev)
12879+{
12880+ drm_device_dma_t *dma = dev->dma;
12881+ struct drm_buf *buf;
12882+ drm_mga_buf_priv_t *buf_priv;
12883+ int i;
12884+
12885+ for (i = 0; i < dma->buf_count; i++) {
12886+ buf = dma->buflist[i];
12887+ buf_priv = buf->dev_private;
12888+ SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
12889+ }
12890+}
12891+#endif
12892+
12893+static struct drm_buf *mga_freelist_get(struct drm_device * dev)
12894+{
12895+ drm_mga_private_t *dev_priv = dev->dev_private;
12896+ drm_mga_freelist_t *next;
12897+ drm_mga_freelist_t *prev;
12898+ drm_mga_freelist_t *tail = dev_priv->tail;
12899+ u32 head, wrap;
12900+ DRM_DEBUG("\n");
12901+
12902+ head = MGA_READ(MGA_PRIMADDRESS);
12903+ wrap = dev_priv->sarea_priv->last_wrap;
12904+
12905+ DRM_DEBUG(" tail=0x%06lx %d\n",
12906+ tail->age.head ?
12907+ tail->age.head - dev_priv->primary->offset : 0,
12908+ tail->age.wrap);
12909+ DRM_DEBUG(" head=0x%06lx %d\n",
12910+ head - dev_priv->primary->offset, wrap);
12911+
12912+ if (TEST_AGE(&tail->age, head, wrap)) {
12913+ prev = dev_priv->tail->prev;
12914+ next = dev_priv->tail;
12915+ prev->next = NULL;
12916+ next->prev = next->next = NULL;
12917+ dev_priv->tail = prev;
12918+ SET_AGE(&next->age, MGA_BUFFER_USED, 0);
12919+ return next->buf;
12920+ }
12921+
12922+ DRM_DEBUG("returning NULL!\n");
12923+ return NULL;
12924+}
12925+
12926+int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
12927+{
12928+ drm_mga_private_t *dev_priv = dev->dev_private;
12929+ drm_mga_buf_priv_t *buf_priv = buf->dev_private;
12930+ drm_mga_freelist_t *head, *entry, *prev;
12931+
12932+ DRM_DEBUG("age=0x%06lx wrap=%d\n",
12933+ buf_priv->list_entry->age.head -
12934+ dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
12935+
12936+ entry = buf_priv->list_entry;
12937+ head = dev_priv->head;
12938+
12939+ if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
12940+ SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
12941+ prev = dev_priv->tail;
12942+ prev->next = entry;
12943+ entry->prev = prev;
12944+ entry->next = NULL;
12945+ } else {
12946+ prev = head->next;
12947+ head->next = entry;
12948+ prev->prev = entry;
12949+ entry->prev = head;
12950+ entry->next = prev;
12951+ }
12952+
12953+ return 0;
12954+}
12955+
12956+/* ================================================================
12957+ * DMA initialization, cleanup
12958+ */
12959+
12960+int mga_driver_load(struct drm_device *dev, unsigned long flags)
12961+{
12962+ drm_mga_private_t * dev_priv;
12963+
12964+ dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
12965+ if (!dev_priv)
12966+ return -ENOMEM;
12967+
12968+ dev->dev_private = (void *)dev_priv;
12969+ memset(dev_priv, 0, sizeof(drm_mga_private_t));
12970+
12971+ dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
12972+ dev_priv->chipset = flags;
12973+
12974+ dev_priv->mmio_base = drm_get_resource_start(dev, 1);
12975+ dev_priv->mmio_size = drm_get_resource_len(dev, 1);
12976+
12977+ dev->counters += 3;
12978+ dev->types[6] = _DRM_STAT_IRQ;
12979+ dev->types[7] = _DRM_STAT_PRIMARY;
12980+ dev->types[8] = _DRM_STAT_SECONDARY;
12981+
12982+ return 0;
12983+}
12984+
12985+/**
12986+ * Bootstrap the driver for AGP DMA.
12987+ *
12988+ * \todo
12989+ * Investigate whether there is any benifit to storing the WARP microcode in
12990+ * AGP memory. If not, the microcode may as well always be put in PCI
12991+ * memory.
12992+ *
12993+ * \todo
12994+ * This routine needs to set dma_bs->agp_mode to the mode actually configured
12995+ * in the hardware. Looking just at the Linux AGP driver code, I don't see
12996+ * an easy way to determine this.
12997+ *
12998+ * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
12999+ */
13000+static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
13001+ drm_mga_dma_bootstrap_t * dma_bs)
13002+{
13003+ drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
13004+ unsigned int warp_size = mga_warp_microcode_size(dev_priv);
13005+ int err;
13006+ unsigned offset;
13007+ const unsigned secondary_size = dma_bs->secondary_bin_count
13008+ * dma_bs->secondary_bin_size;
13009+ const unsigned agp_size = (dma_bs->agp_size << 20);
13010+ struct drm_buf_desc req;
13011+ struct drm_agp_mode mode;
13012+ struct drm_agp_info info;
13013+ struct drm_agp_buffer agp_req;
13014+ struct drm_agp_binding bind_req;
13015+
13016+ /* Acquire AGP. */
13017+ err = drm_agp_acquire(dev);
13018+ if (err) {
13019+ DRM_ERROR("Unable to acquire AGP: %d\n", err);
13020+ return err;
13021+ }
13022+
13023+ err = drm_agp_info(dev, &info);
13024+ if (err) {
13025+ DRM_ERROR("Unable to get AGP info: %d\n", err);
13026+ return err;
13027+ }
13028+
13029+ mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
13030+ err = drm_agp_enable(dev, mode);
13031+ if (err) {
13032+ DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
13033+ return err;
13034+ }
13035+
13036+ /* In addition to the usual AGP mode configuration, the G200 AGP cards
13037+ * need to have the AGP mode "manually" set.
13038+ */
13039+
13040+ if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
13041+ if (mode.mode & 0x02) {
13042+ MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
13043+ } else {
13044+ MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
13045+ }
13046+ }
13047+
13048+
13049+ /* Allocate and bind AGP memory. */
13050+ agp_req.size = agp_size;
13051+ agp_req.type = 0;
13052+ err = drm_agp_alloc( dev, & agp_req );
13053+ if (err) {
13054+ dev_priv->agp_size = 0;
13055+ DRM_ERROR("Unable to allocate %uMB AGP memory\n",
13056+ dma_bs->agp_size);
13057+ return err;
13058+ }
13059+
13060+ dev_priv->agp_size = agp_size;
13061+ dev_priv->agp_handle = agp_req.handle;
13062+
13063+ bind_req.handle = agp_req.handle;
13064+ bind_req.offset = 0;
13065+ err = drm_agp_bind( dev, &bind_req );
13066+ if (err) {
13067+ DRM_ERROR("Unable to bind AGP memory: %d\n", err);
13068+ return err;
13069+ }
13070+
13071+ /* Make drm_addbufs happy by not trying to create a mapping for less
13072+ * than a page.
13073+ */
13074+ if (warp_size < PAGE_SIZE)
13075+ warp_size = PAGE_SIZE;
13076+
13077+ offset = 0;
13078+ err = drm_addmap( dev, offset, warp_size,
13079+ _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp );
13080+ if (err) {
13081+ DRM_ERROR("Unable to map WARP microcode: %d\n", err);
13082+ return err;
13083+ }
13084+
13085+ offset += warp_size;
13086+ err = drm_addmap( dev, offset, dma_bs->primary_size,
13087+ _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary );
13088+ if (err) {
13089+ DRM_ERROR("Unable to map primary DMA region: %d\n", err);
13090+ return err;
13091+ }
13092+
13093+ offset += dma_bs->primary_size;
13094+ err = drm_addmap( dev, offset, secondary_size,
13095+ _DRM_AGP, 0, & dev->agp_buffer_map );
13096+ if (err) {
13097+ DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
13098+ return err;
13099+ }
13100+
13101+ (void) memset( &req, 0, sizeof(req) );
13102+ req.count = dma_bs->secondary_bin_count;
13103+ req.size = dma_bs->secondary_bin_size;
13104+ req.flags = _DRM_AGP_BUFFER;
13105+ req.agp_start = offset;
13106+
13107+ err = drm_addbufs_agp( dev, & req );
13108+ if (err) {
13109+ DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
13110+ return err;
13111+ }
13112+
13113+#ifdef __linux__
13114+ {
13115+ struct drm_map_list *_entry;
13116+ unsigned long agp_token = 0;
13117+
13118+ list_for_each_entry(_entry, &dev->maplist, head) {
13119+ if (_entry->map == dev->agp_buffer_map)
13120+ agp_token = _entry->user_token;
13121+ }
13122+ if (!agp_token)
13123+ return -EFAULT;
13124+
13125+ dev->agp_buffer_token = agp_token;
13126+ }
13127+#endif
13128+
13129+ offset += secondary_size;
13130+ err = drm_addmap( dev, offset, agp_size - offset,
13131+ _DRM_AGP, 0, & dev_priv->agp_textures );
13132+ if (err) {
13133+ DRM_ERROR("Unable to map AGP texture region: %d\n", err);
13134+ return err;
13135+ }
13136+
13137+ drm_core_ioremap(dev_priv->warp, dev);
13138+ drm_core_ioremap(dev_priv->primary, dev);
13139+ drm_core_ioremap(dev->agp_buffer_map, dev);
13140+
13141+ if (!dev_priv->warp->handle ||
13142+ !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
13143+ DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
13144+ dev_priv->warp->handle, dev_priv->primary->handle,
13145+ dev->agp_buffer_map->handle);
13146+ return -ENOMEM;
13147+ }
13148+
13149+ dev_priv->dma_access = MGA_PAGPXFER;
13150+ dev_priv->wagp_enable = MGA_WAGP_ENABLE;
13151+
13152+ DRM_INFO("Initialized card for AGP DMA.\n");
13153+ return 0;
13154+}
13155+
13156+/**
13157+ * Bootstrap the driver for PCI DMA.
13158+ *
13159+ * \todo
13160+ * The algorithm for decreasing the size of the primary DMA buffer could be
13161+ * better. The size should be rounded up to the nearest page size, then
13162+ * decrease the request size by a single page each pass through the loop.
13163+ *
13164+ * \todo
13165+ * Determine whether the maximum address passed to drm_pci_alloc is correct.
13166+ * The same goes for drm_addbufs_pci.
13167+ *
13168+ * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
13169+ */
13170+static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
13171+ drm_mga_dma_bootstrap_t * dma_bs)
13172+{
13173+ drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private;
13174+ unsigned int warp_size = mga_warp_microcode_size(dev_priv);
13175+ unsigned int primary_size;
13176+ unsigned int bin_count;
13177+ int err;
13178+ struct drm_buf_desc req;
13179+
13180+
13181+ if (dev->dma == NULL) {
13182+ DRM_ERROR("dev->dma is NULL\n");
13183+ return -EFAULT;
13184+ }
13185+
13186+ /* Make drm_addbufs happy by not trying to create a mapping for less
13187+ * than a page.
13188+ */
13189+ if (warp_size < PAGE_SIZE)
13190+ warp_size = PAGE_SIZE;
13191+
13192+ /* The proper alignment is 0x100 for this mapping */
13193+ err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
13194+ _DRM_READ_ONLY, &dev_priv->warp);
13195+ if (err != 0) {
13196+ DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
13197+ err);
13198+ return err;
13199+ }
13200+
13201+ /* Other than the bottom two bits being used to encode other
13202+ * information, there don't appear to be any restrictions on the
13203+ * alignment of the primary or secondary DMA buffers.
13204+ */
13205+
13206+ for ( primary_size = dma_bs->primary_size
13207+ ; primary_size != 0
13208+ ; primary_size >>= 1 ) {
13209+ /* The proper alignment for this mapping is 0x04 */
13210+ err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
13211+ _DRM_READ_ONLY, &dev_priv->primary);
13212+ if (!err)
13213+ break;
13214+ }
13215+
13216+ if (err != 0) {
13217+ DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
13218+ return -ENOMEM;
13219+ }
13220+
13221+ if (dev_priv->primary->size != dma_bs->primary_size) {
13222+ DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
13223+ dma_bs->primary_size,
13224+ (unsigned) dev_priv->primary->size);
13225+ dma_bs->primary_size = dev_priv->primary->size;
13226+ }
13227+
13228+ for ( bin_count = dma_bs->secondary_bin_count
13229+ ; bin_count > 0
13230+ ; bin_count-- ) {
13231+ (void) memset( &req, 0, sizeof(req) );
13232+ req.count = bin_count;
13233+ req.size = dma_bs->secondary_bin_size;
13234+
13235+ err = drm_addbufs_pci( dev, & req );
13236+ if (!err) {
13237+ break;
13238+ }
13239+ }
13240+
13241+ if (bin_count == 0) {
13242+ DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
13243+ return err;
13244+ }
13245+
13246+ if (bin_count != dma_bs->secondary_bin_count) {
13247+ DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
13248+ "to %u.\n", dma_bs->secondary_bin_count, bin_count);
13249+
13250+ dma_bs->secondary_bin_count = bin_count;
13251+ }
13252+
13253+ dev_priv->dma_access = 0;
13254+ dev_priv->wagp_enable = 0;
13255+
13256+ dma_bs->agp_mode = 0;
13257+
13258+ DRM_INFO("Initialized card for PCI DMA.\n");
13259+ return 0;
13260+}
13261+
13262+
13263+static int mga_do_dma_bootstrap(struct drm_device * dev,
13264+ drm_mga_dma_bootstrap_t * dma_bs)
13265+{
13266+ const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
13267+ int err;
13268+ drm_mga_private_t * const dev_priv =
13269+ (drm_mga_private_t *) dev->dev_private;
13270+
13271+
13272+ dev_priv->used_new_dma_init = 1;
13273+
13274+ /* The first steps are the same for both PCI and AGP based DMA. Map
13275+ * the cards MMIO registers and map a status page.
13276+ */
13277+ err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size,
13278+ _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio );
13279+ if (err) {
13280+ DRM_ERROR("Unable to map MMIO region: %d\n", err);
13281+ return err;
13282+ }
13283+
13284+
13285+ err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM,
13286+ _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
13287+ & dev_priv->status );
13288+ if (err) {
13289+ DRM_ERROR("Unable to map status region: %d\n", err);
13290+ return err;
13291+ }
13292+
13293+
13294+ /* The DMA initialization procedure is slightly different for PCI and
13295+ * AGP cards. AGP cards just allocate a large block of AGP memory and
13296+ * carve off portions of it for internal uses. The remaining memory
13297+ * is returned to user-mode to be used for AGP textures.
13298+ */
13299+
13300+ if (is_agp) {
13301+ err = mga_do_agp_dma_bootstrap(dev, dma_bs);
13302+ }
13303+
13304+ /* If we attempted to initialize the card for AGP DMA but failed,
13305+ * clean-up any mess that may have been created.
13306+ */
13307+
13308+ if (err) {
13309+ mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
13310+ }
13311+
13312+
13313+ /* Not only do we want to try and initialized PCI cards for PCI DMA,
13314+ * but we also try to initialized AGP cards that could not be
13315+ * initialized for AGP DMA. This covers the case where we have an AGP
13316+ * card in a system with an unsupported AGP chipset. In that case the
13317+ * card will be detected as AGP, but we won't be able to allocate any
13318+ * AGP memory, etc.
13319+ */
13320+
13321+ if (!is_agp || err) {
13322+ err = mga_do_pci_dma_bootstrap(dev, dma_bs);
13323+ }
13324+
13325+
13326+ return err;
13327+}
13328+
13329+int mga_dma_bootstrap(struct drm_device *dev, void *data,
13330+ struct drm_file *file_priv)
13331+{
13332+ drm_mga_dma_bootstrap_t *bootstrap = data;
13333+ int err;
13334+ static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
13335+ const drm_mga_private_t * const dev_priv =
13336+ (drm_mga_private_t *) dev->dev_private;
13337+
13338+
13339+ err = mga_do_dma_bootstrap(dev, bootstrap);
13340+ if (err) {
13341+ mga_do_cleanup_dma(dev, FULL_CLEANUP);
13342+ return err;
13343+ }
13344+
13345+ if (dev_priv->agp_textures != NULL) {
13346+ bootstrap->texture_handle = dev_priv->agp_textures->offset;
13347+ bootstrap->texture_size = dev_priv->agp_textures->size;
13348+ } else {
13349+ bootstrap->texture_handle = 0;
13350+ bootstrap->texture_size = 0;
13351+ }
13352+
13353+ bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
13354+
13355+ return 0;
13356+}
13357+
13358+
13359+static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
13360+{
13361+ drm_mga_private_t *dev_priv;
13362+ int ret;
13363+ DRM_DEBUG("\n");
13364+
13365+
13366+ dev_priv = dev->dev_private;
13367+
13368+ if (init->sgram) {
13369+ dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
13370+ } else {
13371+ dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
13372+ }
13373+ dev_priv->maccess = init->maccess;
13374+
13375+ dev_priv->fb_cpp = init->fb_cpp;
13376+ dev_priv->front_offset = init->front_offset;
13377+ dev_priv->front_pitch = init->front_pitch;
13378+ dev_priv->back_offset = init->back_offset;
13379+ dev_priv->back_pitch = init->back_pitch;
13380+
13381+ dev_priv->depth_cpp = init->depth_cpp;
13382+ dev_priv->depth_offset = init->depth_offset;
13383+ dev_priv->depth_pitch = init->depth_pitch;
13384+
13385+ /* FIXME: Need to support AGP textures...
13386+ */
13387+ dev_priv->texture_offset = init->texture_offset[0];
13388+ dev_priv->texture_size = init->texture_size[0];
13389+
13390+ dev_priv->sarea = drm_getsarea(dev);
13391+ if (!dev_priv->sarea) {
13392+ DRM_ERROR("failed to find sarea!\n");
13393+ return -EINVAL;
13394+ }
13395+
13396+ if (! dev_priv->used_new_dma_init) {
13397+
13398+ dev_priv->dma_access = MGA_PAGPXFER;
13399+ dev_priv->wagp_enable = MGA_WAGP_ENABLE;
13400+
13401+ dev_priv->status = drm_core_findmap(dev, init->status_offset);
13402+ if (!dev_priv->status) {
13403+ DRM_ERROR("failed to find status page!\n");
13404+ return -EINVAL;
13405+ }
13406+ dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
13407+ if (!dev_priv->mmio) {
13408+ DRM_ERROR("failed to find mmio region!\n");
13409+ return -EINVAL;
13410+ }
13411+ dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
13412+ if (!dev_priv->warp) {
13413+ DRM_ERROR("failed to find warp microcode region!\n");
13414+ return -EINVAL;
13415+ }
13416+ dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
13417+ if (!dev_priv->primary) {
13418+ DRM_ERROR("failed to find primary dma region!\n");
13419+ return -EINVAL;
13420+ }
13421+ dev->agp_buffer_token = init->buffers_offset;
13422+ dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
13423+ if (!dev->agp_buffer_map) {
13424+ DRM_ERROR("failed to find dma buffer region!\n");
13425+ return -EINVAL;
13426+ }
13427+
13428+ drm_core_ioremap(dev_priv->warp, dev);
13429+ drm_core_ioremap(dev_priv->primary, dev);
13430+ drm_core_ioremap(dev->agp_buffer_map, dev);
13431+ }
13432+
13433+ dev_priv->sarea_priv =
13434+ (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
13435+ init->sarea_priv_offset);
13436+
13437+ if (!dev_priv->warp->handle ||
13438+ !dev_priv->primary->handle ||
13439+ ((dev_priv->dma_access != 0) &&
13440+ ((dev->agp_buffer_map == NULL) ||
13441+ (dev->agp_buffer_map->handle == NULL)))) {
13442+ DRM_ERROR("failed to ioremap agp regions!\n");
13443+ return -ENOMEM;
13444+ }
13445+
13446+ ret = mga_warp_install_microcode(dev_priv);
13447+ if (ret != 0) {
13448+ DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
13449+ return ret;
13450+ }
13451+
13452+ ret = mga_warp_init(dev_priv);
13453+ if (ret != 0) {
13454+ DRM_ERROR("failed to init WARP engine: %d!\n", ret);
13455+ return ret;
13456+ }
13457+
13458+ dev_priv->prim.status = (u32 *) dev_priv->status->handle;
13459+
13460+ mga_do_wait_for_idle(dev_priv);
13461+
13462+ /* Init the primary DMA registers.
13463+ */
13464+ MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
13465+#if 0
13466+ MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
13467+ MGA_PRIMPTREN1); /* DWGSYNC */
13468+#endif
13469+
13470+ dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
13471+ dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
13472+ + dev_priv->primary->size);
13473+ dev_priv->prim.size = dev_priv->primary->size;
13474+
13475+ dev_priv->prim.tail = 0;
13476+ dev_priv->prim.space = dev_priv->prim.size;
13477+ dev_priv->prim.wrapped = 0;
13478+
13479+ dev_priv->prim.last_flush = 0;
13480+ dev_priv->prim.last_wrap = 0;
13481+
13482+ dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
13483+
13484+ dev_priv->prim.status[0] = dev_priv->primary->offset;
13485+ dev_priv->prim.status[1] = 0;
13486+
13487+ dev_priv->sarea_priv->last_wrap = 0;
13488+ dev_priv->sarea_priv->last_frame.head = 0;
13489+ dev_priv->sarea_priv->last_frame.wrap = 0;
13490+
13491+ if (mga_freelist_init(dev, dev_priv) < 0) {
13492+ DRM_ERROR("could not initialize freelist\n");
13493+ return -ENOMEM;
13494+ }
13495+
13496+ return 0;
13497+}
13498+
13499+static int mga_do_cleanup_dma(struct drm_device * dev, int full_cleanup)
13500+{
13501+ int err = 0;
13502+ DRM_DEBUG("\n");
13503+
13504+ /* Make sure interrupts are disabled here because the uninstall ioctl
13505+ * may not have been called from userspace and after dev_private
13506+ * is freed, it's too late.
13507+ */
13508+ if (dev->irq_enabled)
13509+ drm_irq_uninstall(dev);
13510+
13511+ if (dev->dev_private) {
13512+ drm_mga_private_t *dev_priv = dev->dev_private;
13513+
13514+ if ((dev_priv->warp != NULL)
13515+ && (dev_priv->warp->type != _DRM_CONSISTENT))
13516+ drm_core_ioremapfree(dev_priv->warp, dev);
13517+
13518+ if ((dev_priv->primary != NULL)
13519+ && (dev_priv->primary->type != _DRM_CONSISTENT))
13520+ drm_core_ioremapfree(dev_priv->primary, dev);
13521+
13522+ if (dev->agp_buffer_map != NULL)
13523+ drm_core_ioremapfree(dev->agp_buffer_map, dev);
13524+
13525+ if (dev_priv->used_new_dma_init) {
13526+ if (dev_priv->agp_handle != 0) {
13527+ struct drm_agp_binding unbind_req;
13528+ struct drm_agp_buffer free_req;
13529+
13530+ unbind_req.handle = dev_priv->agp_handle;
13531+ drm_agp_unbind(dev, &unbind_req);
13532+
13533+ free_req.handle = dev_priv->agp_handle;
13534+ drm_agp_free(dev, &free_req);
13535+
13536+ dev_priv->agp_textures = NULL;
13537+ dev_priv->agp_size = 0;
13538+ dev_priv->agp_handle = 0;
13539+ }
13540+
13541+ if ((dev->agp != NULL) && dev->agp->acquired) {
13542+ err = drm_agp_release(dev);
13543+ }
13544+ }
13545+
13546+ dev_priv->warp = NULL;
13547+ dev_priv->primary = NULL;
13548+ dev_priv->sarea = NULL;
13549+ dev_priv->sarea_priv = NULL;
13550+ dev->agp_buffer_map = NULL;
13551+
13552+ if (full_cleanup) {
13553+ dev_priv->mmio = NULL;
13554+ dev_priv->status = NULL;
13555+ dev_priv->used_new_dma_init = 0;
13556+ }
13557+
13558+ memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
13559+ dev_priv->warp_pipe = 0;
13560+ memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
13561+
13562+ if (dev_priv->head != NULL) {
13563+ mga_freelist_cleanup(dev);
13564+ }
13565+ }
13566+
13567+ return 0;
13568+}
13569+
13570+int mga_dma_init(struct drm_device *dev, void *data,
13571+ struct drm_file *file_priv)
13572+{
13573+ drm_mga_init_t *init = data;
13574+ int err;
13575+
13576+ LOCK_TEST_WITH_RETURN(dev, file_priv);
13577+
13578+ switch (init->func) {
13579+ case MGA_INIT_DMA:
13580+ err = mga_do_init_dma(dev, init);
13581+ if (err) {
13582+ (void) mga_do_cleanup_dma(dev, FULL_CLEANUP);
13583+ }
13584+ return err;
13585+ case MGA_CLEANUP_DMA:
13586+ return mga_do_cleanup_dma(dev, FULL_CLEANUP);
13587+ }
13588+
13589+ return -EINVAL;
13590+}
13591+
13592+/* ================================================================
13593+ * Primary DMA stream management
13594+ */
13595+
13596+int mga_dma_flush(struct drm_device *dev, void *data,
13597+ struct drm_file *file_priv)
13598+{
13599+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
13600+ struct drm_lock *lock = data;
13601+
13602+ LOCK_TEST_WITH_RETURN(dev, file_priv);
13603+
13604+ DRM_DEBUG("%s%s%s\n",
13605+ (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
13606+ (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
13607+ (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
13608+
13609+ WRAP_WAIT_WITH_RETURN(dev_priv);
13610+
13611+ if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
13612+ mga_do_dma_flush(dev_priv);
13613+ }
13614+
13615+ if (lock->flags & _DRM_LOCK_QUIESCENT) {
13616+#if MGA_DMA_DEBUG
13617+ int ret = mga_do_wait_for_idle(dev_priv);
13618+ if (ret < 0)
13619+ DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
13620+ return ret;
13621+#else
13622+ return mga_do_wait_for_idle(dev_priv);
13623+#endif
13624+ } else {
13625+ return 0;
13626+ }
13627+}
13628+
13629+int mga_dma_reset(struct drm_device *dev, void *data,
13630+ struct drm_file *file_priv)
13631+{
13632+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
13633+
13634+ LOCK_TEST_WITH_RETURN(dev, file_priv);
13635+
13636+ return mga_do_dma_reset(dev_priv);
13637+}
13638+
13639+/* ================================================================
13640+ * DMA buffer management
13641+ */
13642+
13643+static int mga_dma_get_buffers(struct drm_device * dev,
13644+ struct drm_file *file_priv, struct drm_dma * d)
13645+{
13646+ struct drm_buf *buf;
13647+ int i;
13648+
13649+ for (i = d->granted_count; i < d->request_count; i++) {
13650+ buf = mga_freelist_get(dev);
13651+ if (!buf)
13652+ return -EAGAIN;
13653+
13654+ buf->file_priv = file_priv;
13655+
13656+ if (DRM_COPY_TO_USER(&d->request_indices[i],
13657+ &buf->idx, sizeof(buf->idx)))
13658+ return -EFAULT;
13659+ if (DRM_COPY_TO_USER(&d->request_sizes[i],
13660+ &buf->total, sizeof(buf->total)))
13661+ return -EFAULT;
13662+
13663+ d->granted_count++;
13664+ }
13665+ return 0;
13666+}
13667+
13668+int mga_dma_buffers(struct drm_device *dev, void *data,
13669+ struct drm_file *file_priv)
13670+{
13671+ struct drm_device_dma *dma = dev->dma;
13672+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
13673+ struct drm_dma *d = data;
13674+ int ret = 0;
13675+
13676+ LOCK_TEST_WITH_RETURN(dev, file_priv);
13677+
13678+ /* Please don't send us buffers.
13679+ */
13680+ if (d->send_count != 0) {
13681+ DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
13682+ DRM_CURRENTPID, d->send_count);
13683+ return -EINVAL;
13684+ }
13685+
13686+ /* We'll send you buffers.
13687+ */
13688+ if (d->request_count < 0 || d->request_count > dma->buf_count) {
13689+ DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
13690+ DRM_CURRENTPID, d->request_count, dma->buf_count);
13691+ return -EINVAL;
13692+ }
13693+
13694+ WRAP_TEST_WITH_RETURN(dev_priv);
13695+
13696+ d->granted_count = 0;
13697+
13698+ if (d->request_count) {
13699+ ret = mga_dma_get_buffers(dev, file_priv, d);
13700+ }
13701+
13702+ return ret;
13703+}
13704+
13705+/**
13706+ * Called just before the module is unloaded.
13707+ */
13708+int mga_driver_unload(struct drm_device * dev)
13709+{
13710+ drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
13711+ dev->dev_private = NULL;
13712+
13713+ return 0;
13714+}
13715+
13716+/**
13717+ * Called when the last opener of the device is closed.
13718+ */
13719+void mga_driver_lastclose(struct drm_device * dev)
13720+{
13721+ mga_do_cleanup_dma(dev, FULL_CLEANUP);
13722+}
13723+
13724+int mga_driver_dma_quiescent(struct drm_device * dev)
13725+{
13726+ drm_mga_private_t *dev_priv = dev->dev_private;
13727+ return mga_do_wait_for_idle(dev_priv);
13728+}
13729Index: git/shared-core/mga_drm.h
13730===================================================================
13731--- git.orig/shared-core/mga_drm.h 2008-12-12 17:20:14.000000000 +0000
13732+++ git/shared-core/mga_drm.h 2008-12-12 17:35:22.000000000 +0000
13733@@ -181,7 +181,7 @@
13734
13735 /* The current cliprects, or a subset thereof.
13736 */
13737- drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
13738+ struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
13739 unsigned int nbox;
13740
13741 /* Information about the most recently used 3d drawable. The
13742@@ -202,7 +202,7 @@
13743 unsigned int exported_nback;
13744 int exported_back_x, exported_front_x, exported_w;
13745 int exported_back_y, exported_front_y, exported_h;
13746- drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
13747+ struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
13748
13749 /* Counters for aging textures and for client-side throttling.
13750 */
13751@@ -216,7 +216,7 @@
13752
13753 /* LRU lists for texture memory in agp space and on the card.
13754 */
13755- drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
13756+ struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
13757 unsigned int texAge[MGA_NR_TEX_HEAPS];
13758
13759 /* Mechanism to validate card state.
13760@@ -302,10 +302,10 @@
13761 typedef struct drm_mga_dma_bootstrap {
13762 /**
13763 * \name AGP texture region
13764- *
13765+ *
13766 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
13767 * be filled in with the actual AGP texture settings.
13768- *
13769+ *
13770 * \warning
13771 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
13772 * is zero, it means that PCI memory (most likely through the use of
13773@@ -319,7 +319,7 @@
13774
13775 /**
13776 * Requested size of the primary DMA region.
13777- *
13778+ *
13779 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
13780 * filled in with the actual AGP mode. If AGP was not available
13781 */
13782@@ -328,18 +328,18 @@
13783
13784 /**
13785 * Requested number of secondary DMA buffers.
13786- *
13787+ *
13788 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
13789 * filled in with the actual number of secondary DMA buffers
13790 * allocated. Particularly when PCI DMA is used, this may be
13791 * (subtantially) less than the number requested.
13792 */
13793 uint32_t secondary_bin_count;
13794-
13795-
13796+
13797+
13798 /**
13799 * Requested size of each secondary DMA buffer.
13800- *
13801+ *
13802 * While the kernel \b is free to reduce
13803 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
13804 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
13805@@ -352,7 +352,7 @@
13806 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
13807 * zero, it means that PCI DMA should be used, even if AGP is
13808 * possible.
13809- *
13810+ *
13811 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
13812 * filled in with the actual AGP mode. If AGP was not available
13813 * (i.e., PCI DMA was used), this value will be zero.
13814Index: git/shared-core/mga_drv.h
13815===================================================================
13816--- /dev/null 1970-01-01 00:00:00.000000000 +0000
13817+++ git/shared-core/mga_drv.h 2008-12-12 17:35:22.000000000 +0000
13818@@ -0,0 +1,688 @@
13819+/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
13820+ * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
13821+ *
13822+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13823+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
13824+ * All rights reserved.
13825+ *
13826+ * Permission is hereby granted, free of charge, to any person obtaining a
13827+ * copy of this software and associated documentation files (the "Software"),
13828+ * to deal in the Software without restriction, including without limitation
13829+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13830+ * and/or sell copies of the Software, and to permit persons to whom the
13831+ * Software is furnished to do so, subject to the following conditions:
13832+ *
13833+ * The above copyright notice and this permission notice (including the next
13834+ * paragraph) shall be included in all copies or substantial portions of the
13835+ * Software.
13836+ *
13837+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13838+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
13839+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
13840+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
13841+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
13842+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
13843+ * OTHER DEALINGS IN THE SOFTWARE.
13844+ *
13845+ * Authors:
13846+ * Gareth Hughes <gareth@valinux.com>
13847+ */
13848+
13849+#ifndef __MGA_DRV_H__
13850+#define __MGA_DRV_H__
13851+
13852+/* General customization:
13853+ */
13854+
13855+#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
13856+
13857+#define DRIVER_NAME "mga"
13858+#define DRIVER_DESC "Matrox G200/G400"
13859+#define DRIVER_DATE "20060319"
13860+
13861+#define DRIVER_MAJOR 3
13862+#define DRIVER_MINOR 2
13863+#define DRIVER_PATCHLEVEL 2
13864+
13865+typedef struct drm_mga_primary_buffer {
13866+ u8 *start;
13867+ u8 *end;
13868+ int size;
13869+
13870+ u32 tail;
13871+ int space;
13872+ volatile long wrapped;
13873+
13874+ volatile u32 *status;
13875+
13876+ u32 last_flush;
13877+ u32 last_wrap;
13878+
13879+ u32 high_mark;
13880+} drm_mga_primary_buffer_t;
13881+
13882+typedef struct drm_mga_freelist {
13883+ struct drm_mga_freelist *next;
13884+ struct drm_mga_freelist *prev;
13885+ drm_mga_age_t age;
13886+ struct drm_buf *buf;
13887+} drm_mga_freelist_t;
13888+
13889+typedef struct {
13890+ drm_mga_freelist_t *list_entry;
13891+ int discard;
13892+ int dispatched;
13893+} drm_mga_buf_priv_t;
13894+
13895+typedef struct drm_mga_private {
13896+ drm_mga_primary_buffer_t prim;
13897+ drm_mga_sarea_t *sarea_priv;
13898+
13899+ drm_mga_freelist_t *head;
13900+ drm_mga_freelist_t *tail;
13901+
13902+ unsigned int warp_pipe;
13903+ unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
13904+
13905+ int chipset;
13906+ int usec_timeout;
13907+
13908+ /**
13909+ * If set, the new DMA initialization sequence was used. This is
13910+ * primarilly used to select how the driver should uninitialized its
13911+ * internal DMA structures.
13912+ */
13913+ int used_new_dma_init;
13914+
13915+ /**
13916+ * If AGP memory is used for DMA buffers, this will be the value
13917+ * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
13918+ */
13919+ u32 dma_access;
13920+
13921+ /**
13922+ * If AGP memory is used for DMA buffers, this will be the value
13923+ * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
13924+ * transfer).
13925+ */
13926+ u32 wagp_enable;
13927+
13928+ /**
13929+ * \name MMIO region parameters.
13930+ *
13931+ * \sa drm_mga_private_t::mmio
13932+ */
13933+ /*@{*/
13934+ u32 mmio_base; /**< Bus address of base of MMIO. */
13935+ u32 mmio_size; /**< Size of the MMIO region. */
13936+ /*@}*/
13937+
13938+ u32 clear_cmd;
13939+ u32 maccess;
13940+
13941+ wait_queue_head_t fence_queue;
13942+ atomic_t last_fence_retired;
13943+ u32 next_fence_to_post;
13944+
13945+ unsigned int fb_cpp;
13946+ unsigned int front_offset;
13947+ unsigned int front_pitch;
13948+ unsigned int back_offset;
13949+ unsigned int back_pitch;
13950+
13951+ unsigned int depth_cpp;
13952+ unsigned int depth_offset;
13953+ unsigned int depth_pitch;
13954+
13955+ unsigned int texture_offset;
13956+ unsigned int texture_size;
13957+
13958+ drm_local_map_t *sarea;
13959+ drm_local_map_t *mmio;
13960+ drm_local_map_t *status;
13961+ drm_local_map_t *warp;
13962+ drm_local_map_t *primary;
13963+ drm_local_map_t *agp_textures;
13964+
13965+ unsigned long agp_handle;
13966+ unsigned int agp_size;
13967+} drm_mga_private_t;
13968+
13969+extern struct drm_ioctl_desc mga_ioctls[];
13970+extern int mga_max_ioctl;
13971+
13972+ /* mga_dma.c */
13973+extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
13974+ struct drm_file *file_priv);
13975+extern int mga_dma_init(struct drm_device *dev, void *data,
13976+ struct drm_file *file_priv);
13977+extern int mga_dma_flush(struct drm_device *dev, void *data,
13978+ struct drm_file *file_priv);
13979+extern int mga_dma_reset(struct drm_device *dev, void *data,
13980+ struct drm_file *file_priv);
13981+extern int mga_dma_buffers(struct drm_device *dev, void *data,
13982+ struct drm_file *file_priv);
13983+extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
13984+extern int mga_driver_unload(struct drm_device * dev);
13985+extern void mga_driver_lastclose(struct drm_device * dev);
13986+extern int mga_driver_dma_quiescent(struct drm_device * dev);
13987+
13988+extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
13989+
13990+extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
13991+extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
13992+extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
13993+
13994+extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
13995+
13996+ /* mga_warp.c */
13997+extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
13998+extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
13999+extern int mga_warp_init(drm_mga_private_t * dev_priv);
14000+
14001+ /* mga_irq.c */
14002+extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
14003+extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
14004+extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
14005+extern void mga_driver_irq_preinstall(struct drm_device * dev);
14006+extern void mga_driver_irq_postinstall(struct drm_device * dev);
14007+extern void mga_driver_irq_uninstall(struct drm_device * dev);
14008+extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
14009+ unsigned long arg);
14010+
14011+#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
14012+
14013+#if defined(__linux__) && defined(__alpha__)
14014+#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
14015+#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
14016+
14017+#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
14018+#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
14019+
14020+#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
14021+#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
14022+#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
14023+#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
14024+
14025+static inline u32 _MGA_READ(u32 * addr)
14026+{
14027+ DRM_MEMORYBARRIER();
14028+ return *(volatile u32 *)addr;
14029+}
14030+#else
14031+#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
14032+#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
14033+#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
14034+#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
14035+#endif
14036+
14037+#define DWGREG0 0x1c00
14038+#define DWGREG0_END 0x1dff
14039+#define DWGREG1 0x2c00
14040+#define DWGREG1_END 0x2dff
14041+
14042+#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
14043+#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
14044+#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
14045+#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
14046+
14047+/* ================================================================
14048+ * Helper macross...
14049+ */
14050+
14051+#define MGA_EMIT_STATE( dev_priv, dirty ) \
14052+do { \
14053+ if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
14054+ if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \
14055+ mga_g400_emit_state( dev_priv ); \
14056+ } else { \
14057+ mga_g200_emit_state( dev_priv ); \
14058+ } \
14059+ } \
14060+} while (0)
14061+
14062+#define WRAP_TEST_WITH_RETURN( dev_priv ) \
14063+do { \
14064+ if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
14065+ if ( mga_is_idle( dev_priv ) ) { \
14066+ mga_do_dma_wrap_end( dev_priv ); \
14067+ } else if ( dev_priv->prim.space < \
14068+ dev_priv->prim.high_mark ) { \
14069+ if ( MGA_DMA_DEBUG ) \
14070+ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
14071+ return -EBUSY; \
14072+ } \
14073+ } \
14074+} while (0)
14075+
14076+#define WRAP_WAIT_WITH_RETURN( dev_priv ) \
14077+do { \
14078+ if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
14079+ if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
14080+ if ( MGA_DMA_DEBUG ) \
14081+ DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
14082+ return -EBUSY; \
14083+ } \
14084+ mga_do_dma_wrap_end( dev_priv ); \
14085+ } \
14086+} while (0)
14087+
14088+/* ================================================================
14089+ * Primary DMA command stream
14090+ */
14091+
14092+#define MGA_VERBOSE 0
14093+
14094+#define DMA_LOCALS unsigned int write; volatile u8 *prim;
14095+
14096+#define DMA_BLOCK_SIZE (5 * sizeof(u32))
14097+
14098+#define BEGIN_DMA( n ) \
14099+do { \
14100+ if ( MGA_VERBOSE ) { \
14101+ DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
14102+ (n), __FUNCTION__ ); \
14103+ DRM_INFO( " space=0x%x req=0x%Zx\n", \
14104+ dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
14105+ } \
14106+ prim = dev_priv->prim.start; \
14107+ write = dev_priv->prim.tail; \
14108+} while (0)
14109+
14110+#define BEGIN_DMA_WRAP() \
14111+do { \
14112+ if ( MGA_VERBOSE ) { \
14113+ DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
14114+ DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
14115+ } \
14116+ prim = dev_priv->prim.start; \
14117+ write = dev_priv->prim.tail; \
14118+} while (0)
14119+
14120+#define ADVANCE_DMA() \
14121+do { \
14122+ dev_priv->prim.tail = write; \
14123+ if ( MGA_VERBOSE ) { \
14124+ DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
14125+ write, dev_priv->prim.space ); \
14126+ } \
14127+} while (0)
14128+
14129+#define FLUSH_DMA() \
14130+do { \
14131+ if ( 0 ) { \
14132+ DRM_INFO( "%s:\n", __FUNCTION__ ); \
14133+ DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
14134+ dev_priv->prim.tail, \
14135+ MGA_READ( MGA_PRIMADDRESS ) - \
14136+ dev_priv->primary->offset ); \
14137+ } \
14138+ if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
14139+ if ( dev_priv->prim.space < \
14140+ dev_priv->prim.high_mark ) { \
14141+ mga_do_dma_wrap_start( dev_priv ); \
14142+ } else { \
14143+ mga_do_dma_flush( dev_priv ); \
14144+ } \
14145+ } \
14146+} while (0)
14147+
14148+/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
14149+ */
14150+#define DMA_WRITE( offset, val ) \
14151+do { \
14152+ if ( MGA_VERBOSE ) { \
14153+ DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
14154+ (u32)(val), write + (offset) * sizeof(u32) ); \
14155+ } \
14156+ *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
14157+} while (0)
14158+
14159+#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
14160+do { \
14161+ DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
14162+ (DMAREG( reg1 ) << 8) | \
14163+ (DMAREG( reg2 ) << 16) | \
14164+ (DMAREG( reg3 ) << 24)) ); \
14165+ DMA_WRITE( 1, val0 ); \
14166+ DMA_WRITE( 2, val1 ); \
14167+ DMA_WRITE( 3, val2 ); \
14168+ DMA_WRITE( 4, val3 ); \
14169+ write += DMA_BLOCK_SIZE; \
14170+} while (0)
14171+
14172+/* Buffer aging via primary DMA stream head pointer.
14173+ */
14174+
14175+#define SET_AGE( age, h, w ) \
14176+do { \
14177+ (age)->head = h; \
14178+ (age)->wrap = w; \
14179+} while (0)
14180+
14181+#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
14182+ ( (age)->wrap == w && \
14183+ (age)->head < h ) )
14184+
14185+#define AGE_BUFFER( buf_priv ) \
14186+do { \
14187+ drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
14188+ if ( (buf_priv)->dispatched ) { \
14189+ entry->age.head = (dev_priv->prim.tail + \
14190+ dev_priv->primary->offset); \
14191+ entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
14192+ } else { \
14193+ entry->age.head = 0; \
14194+ entry->age.wrap = 0; \
14195+ } \
14196+} while (0)
14197+
14198+#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
14199+ MGA_DWGENGSTS | \
14200+ MGA_ENDPRDMASTS)
14201+#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
14202+ MGA_ENDPRDMASTS)
14203+
14204+#define MGA_DMA_DEBUG 0
14205+
14206+/* A reduced set of the mga registers.
14207+ */
14208+#define MGA_CRTC_INDEX 0x1fd4
14209+#define MGA_CRTC_DATA 0x1fd5
14210+
14211+/* CRTC11 */
14212+#define MGA_VINTCLR (1 << 4)
14213+#define MGA_VINTEN (1 << 5)
14214+
14215+#define MGA_ALPHACTRL 0x2c7c
14216+#define MGA_AR0 0x1c60
14217+#define MGA_AR1 0x1c64
14218+#define MGA_AR2 0x1c68
14219+#define MGA_AR3 0x1c6c
14220+#define MGA_AR4 0x1c70
14221+#define MGA_AR5 0x1c74
14222+#define MGA_AR6 0x1c78
14223+
14224+#define MGA_CXBNDRY 0x1c80
14225+#define MGA_CXLEFT 0x1ca0
14226+#define MGA_CXRIGHT 0x1ca4
14227+
14228+#define MGA_DMAPAD 0x1c54
14229+#define MGA_DSTORG 0x2cb8
14230+#define MGA_DWGCTL 0x1c00
14231+# define MGA_OPCOD_MASK (15 << 0)
14232+# define MGA_OPCOD_TRAP (4 << 0)
14233+# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
14234+# define MGA_OPCOD_BITBLT (8 << 0)
14235+# define MGA_OPCOD_ILOAD (9 << 0)
14236+# define MGA_ATYPE_MASK (7 << 4)
14237+# define MGA_ATYPE_RPL (0 << 4)
14238+# define MGA_ATYPE_RSTR (1 << 4)
14239+# define MGA_ATYPE_ZI (3 << 4)
14240+# define MGA_ATYPE_BLK (4 << 4)
14241+# define MGA_ATYPE_I (7 << 4)
14242+# define MGA_LINEAR (1 << 7)
14243+# define MGA_ZMODE_MASK (7 << 8)
14244+# define MGA_ZMODE_NOZCMP (0 << 8)
14245+# define MGA_ZMODE_ZE (2 << 8)
14246+# define MGA_ZMODE_ZNE (3 << 8)
14247+# define MGA_ZMODE_ZLT (4 << 8)
14248+# define MGA_ZMODE_ZLTE (5 << 8)
14249+# define MGA_ZMODE_ZGT (6 << 8)
14250+# define MGA_ZMODE_ZGTE (7 << 8)
14251+# define MGA_SOLID (1 << 11)
14252+# define MGA_ARZERO (1 << 12)
14253+# define MGA_SGNZERO (1 << 13)
14254+# define MGA_SHIFTZERO (1 << 14)
14255+# define MGA_BOP_MASK (15 << 16)
14256+# define MGA_BOP_ZERO (0 << 16)
14257+# define MGA_BOP_DST (10 << 16)
14258+# define MGA_BOP_SRC (12 << 16)
14259+# define MGA_BOP_ONE (15 << 16)
14260+# define MGA_TRANS_SHIFT 20
14261+# define MGA_TRANS_MASK (15 << 20)
14262+# define MGA_BLTMOD_MASK (15 << 25)
14263+# define MGA_BLTMOD_BMONOLEF (0 << 25)
14264+# define MGA_BLTMOD_BMONOWF (4 << 25)
14265+# define MGA_BLTMOD_PLAN (1 << 25)
14266+# define MGA_BLTMOD_BFCOL (2 << 25)
14267+# define MGA_BLTMOD_BU32BGR (3 << 25)
14268+# define MGA_BLTMOD_BU32RGB (7 << 25)
14269+# define MGA_BLTMOD_BU24BGR (11 << 25)
14270+# define MGA_BLTMOD_BU24RGB (15 << 25)
14271+# define MGA_PATTERN (1 << 29)
14272+# define MGA_TRANSC (1 << 30)
14273+# define MGA_CLIPDIS (1 << 31)
14274+#define MGA_DWGSYNC 0x2c4c
14275+
14276+#define MGA_FCOL 0x1c24
14277+#define MGA_FIFOSTATUS 0x1e10
14278+#define MGA_FOGCOL 0x1cf4
14279+#define MGA_FXBNDRY 0x1c84
14280+#define MGA_FXLEFT 0x1ca8
14281+#define MGA_FXRIGHT 0x1cac
14282+
14283+#define MGA_ICLEAR 0x1e18
14284+# define MGA_SOFTRAPICLR (1 << 0)
14285+# define MGA_VLINEICLR (1 << 5)
14286+#define MGA_IEN 0x1e1c
14287+# define MGA_SOFTRAPIEN (1 << 0)
14288+# define MGA_VLINEIEN (1 << 5)
14289+
14290+#define MGA_LEN 0x1c5c
14291+
14292+#define MGA_MACCESS 0x1c04
14293+
14294+#define MGA_PITCH 0x1c8c
14295+#define MGA_PLNWT 0x1c1c
14296+#define MGA_PRIMADDRESS 0x1e58
14297+# define MGA_DMA_GENERAL (0 << 0)
14298+# define MGA_DMA_BLIT (1 << 0)
14299+# define MGA_DMA_VECTOR (2 << 0)
14300+# define MGA_DMA_VERTEX (3 << 0)
14301+#define MGA_PRIMEND 0x1e5c
14302+# define MGA_PRIMNOSTART (1 << 0)
14303+# define MGA_PAGPXFER (1 << 1)
14304+#define MGA_PRIMPTR 0x1e50
14305+# define MGA_PRIMPTREN0 (1 << 0)
14306+# define MGA_PRIMPTREN1 (1 << 1)
14307+
14308+#define MGA_RST 0x1e40
14309+# define MGA_SOFTRESET (1 << 0)
14310+# define MGA_SOFTEXTRST (1 << 1)
14311+
14312+#define MGA_SECADDRESS 0x2c40
14313+#define MGA_SECEND 0x2c44
14314+#define MGA_SETUPADDRESS 0x2cd0
14315+#define MGA_SETUPEND 0x2cd4
14316+#define MGA_SGN 0x1c58
14317+#define MGA_SOFTRAP 0x2c48
14318+#define MGA_SRCORG 0x2cb4
14319+# define MGA_SRMMAP_MASK (1 << 0)
14320+# define MGA_SRCMAP_FB (0 << 0)
14321+# define MGA_SRCMAP_SYSMEM (1 << 0)
14322+# define MGA_SRCACC_MASK (1 << 1)
14323+# define MGA_SRCACC_PCI (0 << 1)
14324+# define MGA_SRCACC_AGP (1 << 1)
14325+#define MGA_STATUS 0x1e14
14326+# define MGA_SOFTRAPEN (1 << 0)
14327+# define MGA_VSYNCPEN (1 << 4)
14328+# define MGA_VLINEPEN (1 << 5)
14329+# define MGA_DWGENGSTS (1 << 16)
14330+# define MGA_ENDPRDMASTS (1 << 17)
14331+#define MGA_STENCIL 0x2cc8
14332+#define MGA_STENCILCTL 0x2ccc
14333+
14334+#define MGA_TDUALSTAGE0 0x2cf8
14335+#define MGA_TDUALSTAGE1 0x2cfc
14336+#define MGA_TEXBORDERCOL 0x2c5c
14337+#define MGA_TEXCTL 0x2c30
14338+#define MGA_TEXCTL2 0x2c3c
14339+# define MGA_DUALTEX (1 << 7)
14340+# define MGA_G400_TC2_MAGIC (1 << 15)
14341+# define MGA_MAP1_ENABLE (1 << 31)
14342+#define MGA_TEXFILTER 0x2c58
14343+#define MGA_TEXHEIGHT 0x2c2c
14344+#define MGA_TEXORG 0x2c24
14345+# define MGA_TEXORGMAP_MASK (1 << 0)
14346+# define MGA_TEXORGMAP_FB (0 << 0)
14347+# define MGA_TEXORGMAP_SYSMEM (1 << 0)
14348+# define MGA_TEXORGACC_MASK (1 << 1)
14349+# define MGA_TEXORGACC_PCI (0 << 1)
14350+# define MGA_TEXORGACC_AGP (1 << 1)
14351+#define MGA_TEXORG1 0x2ca4
14352+#define MGA_TEXORG2 0x2ca8
14353+#define MGA_TEXORG3 0x2cac
14354+#define MGA_TEXORG4 0x2cb0
14355+#define MGA_TEXTRANS 0x2c34
14356+#define MGA_TEXTRANSHIGH 0x2c38
14357+#define MGA_TEXWIDTH 0x2c28
14358+
14359+#define MGA_WACCEPTSEQ 0x1dd4
14360+#define MGA_WCODEADDR 0x1e6c
14361+#define MGA_WFLAG 0x1dc4
14362+#define MGA_WFLAG1 0x1de0
14363+#define MGA_WFLAGNB 0x1e64
14364+#define MGA_WFLAGNB1 0x1e08
14365+#define MGA_WGETMSB 0x1dc8
14366+#define MGA_WIADDR 0x1dc0
14367+#define MGA_WIADDR2 0x1dd8
14368+# define MGA_WMODE_SUSPEND (0 << 0)
14369+# define MGA_WMODE_RESUME (1 << 0)
14370+# define MGA_WMODE_JUMP (2 << 0)
14371+# define MGA_WMODE_START (3 << 0)
14372+# define MGA_WAGP_ENABLE (1 << 2)
14373+#define MGA_WMISC 0x1e70
14374+# define MGA_WUCODECACHE_ENABLE (1 << 0)
14375+# define MGA_WMASTER_ENABLE (1 << 1)
14376+# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
14377+#define MGA_WVRTXSZ 0x1dcc
14378+
14379+#define MGA_YBOT 0x1c9c
14380+#define MGA_YDST 0x1c90
14381+#define MGA_YDSTLEN 0x1c88
14382+#define MGA_YDSTORG 0x1c94
14383+#define MGA_YTOP 0x1c98
14384+
14385+#define MGA_ZORG 0x1c0c
14386+
14387+/* This finishes the current batch of commands
14388+ */
14389+#define MGA_EXEC 0x0100
14390+
14391+/* AGP PLL encoding (for G200 only).
14392+ */
14393+#define MGA_AGP_PLL 0x1e4c
14394+# define MGA_AGP2XPLL_DISABLE (0 << 0)
14395+# define MGA_AGP2XPLL_ENABLE (1 << 0)
14396+
14397+/* Warp registers
14398+ */
14399+#define MGA_WR0 0x2d00
14400+#define MGA_WR1 0x2d04
14401+#define MGA_WR2 0x2d08
14402+#define MGA_WR3 0x2d0c
14403+#define MGA_WR4 0x2d10
14404+#define MGA_WR5 0x2d14
14405+#define MGA_WR6 0x2d18
14406+#define MGA_WR7 0x2d1c
14407+#define MGA_WR8 0x2d20
14408+#define MGA_WR9 0x2d24
14409+#define MGA_WR10 0x2d28
14410+#define MGA_WR11 0x2d2c
14411+#define MGA_WR12 0x2d30
14412+#define MGA_WR13 0x2d34
14413+#define MGA_WR14 0x2d38
14414+#define MGA_WR15 0x2d3c
14415+#define MGA_WR16 0x2d40
14416+#define MGA_WR17 0x2d44
14417+#define MGA_WR18 0x2d48
14418+#define MGA_WR19 0x2d4c
14419+#define MGA_WR20 0x2d50
14420+#define MGA_WR21 0x2d54
14421+#define MGA_WR22 0x2d58
14422+#define MGA_WR23 0x2d5c
14423+#define MGA_WR24 0x2d60
14424+#define MGA_WR25 0x2d64
14425+#define MGA_WR26 0x2d68
14426+#define MGA_WR27 0x2d6c
14427+#define MGA_WR28 0x2d70
14428+#define MGA_WR29 0x2d74
14429+#define MGA_WR30 0x2d78
14430+#define MGA_WR31 0x2d7c
14431+#define MGA_WR32 0x2d80
14432+#define MGA_WR33 0x2d84
14433+#define MGA_WR34 0x2d88
14434+#define MGA_WR35 0x2d8c
14435+#define MGA_WR36 0x2d90
14436+#define MGA_WR37 0x2d94
14437+#define MGA_WR38 0x2d98
14438+#define MGA_WR39 0x2d9c
14439+#define MGA_WR40 0x2da0
14440+#define MGA_WR41 0x2da4
14441+#define MGA_WR42 0x2da8
14442+#define MGA_WR43 0x2dac
14443+#define MGA_WR44 0x2db0
14444+#define MGA_WR45 0x2db4
14445+#define MGA_WR46 0x2db8
14446+#define MGA_WR47 0x2dbc
14447+#define MGA_WR48 0x2dc0
14448+#define MGA_WR49 0x2dc4
14449+#define MGA_WR50 0x2dc8
14450+#define MGA_WR51 0x2dcc
14451+#define MGA_WR52 0x2dd0
14452+#define MGA_WR53 0x2dd4
14453+#define MGA_WR54 0x2dd8
14454+#define MGA_WR55 0x2ddc
14455+#define MGA_WR56 0x2de0
14456+#define MGA_WR57 0x2de4
14457+#define MGA_WR58 0x2de8
14458+#define MGA_WR59 0x2dec
14459+#define MGA_WR60 0x2df0
14460+#define MGA_WR61 0x2df4
14461+#define MGA_WR62 0x2df8
14462+#define MGA_WR63 0x2dfc
14463+# define MGA_G400_WR_MAGIC (1 << 6)
14464+# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
14465+
14466+#define MGA_ILOAD_ALIGN 64
14467+#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
14468+
14469+#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
14470+ MGA_ATYPE_I | \
14471+ MGA_ZMODE_NOZCMP | \
14472+ MGA_ARZERO | \
14473+ MGA_SGNZERO | \
14474+ MGA_BOP_SRC | \
14475+ (15 << MGA_TRANS_SHIFT))
14476+
14477+#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
14478+ MGA_ZMODE_NOZCMP | \
14479+ MGA_SOLID | \
14480+ MGA_ARZERO | \
14481+ MGA_SGNZERO | \
14482+ MGA_SHIFTZERO | \
14483+ MGA_BOP_SRC | \
14484+ (0 << MGA_TRANS_SHIFT) | \
14485+ MGA_BLTMOD_BMONOLEF | \
14486+ MGA_TRANSC | \
14487+ MGA_CLIPDIS)
14488+
14489+#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
14490+ MGA_ATYPE_RPL | \
14491+ MGA_SGNZERO | \
14492+ MGA_SHIFTZERO | \
14493+ MGA_BOP_SRC | \
14494+ (0 << MGA_TRANS_SHIFT) | \
14495+ MGA_BLTMOD_BFCOL | \
14496+ MGA_CLIPDIS)
14497+
14498+/* Simple idle test.
14499+ */
14500+static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
14501+{
14502+ u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
14503+ return (status == MGA_ENDPRDMASTS);
14504+}
14505+
14506+#endif
14507Index: git/shared-core/mga_irq.c
14508===================================================================
14509--- /dev/null 1970-01-01 00:00:00.000000000 +0000
14510+++ git/shared-core/mga_irq.c 2008-12-12 17:35:22.000000000 +0000
14511@@ -0,0 +1,150 @@
14512+/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
14513+ */
14514+/*
14515+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
14516+ *
14517+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
14518+ * initial release of the Radeon 8500 driver under the XFree86 license.
14519+ * This notice must be preserved.
14520+ *
14521+ * Permission is hereby granted, free of charge, to any person obtaining a
14522+ * copy of this software and associated documentation files (the "Software"),
14523+ * to deal in the Software without restriction, including without limitation
14524+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14525+ * and/or sell copies of the Software, and to permit persons to whom the
14526+ * Software is furnished to do so, subject to the following conditions:
14527+ *
14528+ * The above copyright notice and this permission notice (including the next
14529+ * paragraph) shall be included in all copies or substantial portions of the
14530+ * Software.
14531+ *
14532+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14533+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14534+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
14535+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
14536+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
14537+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
14538+ * DEALINGS IN THE SOFTWARE.
14539+ *
14540+ * Authors:
14541+ * Keith Whitwell <keith@tungstengraphics.com>
14542+ * Eric Anholt <anholt@FreeBSD.org>
14543+ */
14544+
14545+#include "drmP.h"
14546+#include "drm.h"
14547+#include "mga_drm.h"
14548+#include "mga_drv.h"
14549+
14550+irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
14551+{
14552+ struct drm_device *dev = (struct drm_device *) arg;
14553+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
14554+ int status;
14555+ int handled = 0;
14556+
14557+ status = MGA_READ(MGA_STATUS);
14558+
14559+ /* VBLANK interrupt */
14560+ if (status & MGA_VLINEPEN) {
14561+ MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
14562+ atomic_inc(&dev->vbl_received);
14563+ DRM_WAKEUP(&dev->vbl_queue);
14564+ drm_vbl_send_signals(dev);
14565+ handled = 1;
14566+ }
14567+
14568+ /* SOFTRAP interrupt */
14569+ if (status & MGA_SOFTRAPEN) {
14570+ const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
14571+ const u32 prim_end = MGA_READ(MGA_PRIMEND);
14572+
14573+
14574+ MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
14575+
14576+ /* In addition to clearing the interrupt-pending bit, we
14577+ * have to write to MGA_PRIMEND to re-start the DMA operation.
14578+ */
14579+ if ( (prim_start & ~0x03) != (prim_end & ~0x03) ) {
14580+ MGA_WRITE(MGA_PRIMEND, prim_end);
14581+ }
14582+
14583+ atomic_inc(&dev_priv->last_fence_retired);
14584+ DRM_WAKEUP(&dev_priv->fence_queue);
14585+ handled = 1;
14586+ }
14587+
14588+ if ( handled ) {
14589+ return IRQ_HANDLED;
14590+ }
14591+ return IRQ_NONE;
14592+}
14593+
14594+int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
14595+{
14596+ unsigned int cur_vblank;
14597+ int ret = 0;
14598+
14599+ /* Assume that the user has missed the current sequence number
14600+ * by about a day rather than she wants to wait for years
14601+ * using vertical blanks...
14602+ */
14603+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
14604+ (((cur_vblank = atomic_read(&dev->vbl_received))
14605+ - *sequence) <= (1 << 23)));
14606+
14607+ *sequence = cur_vblank;
14608+
14609+ return ret;
14610+}
14611+
14612+int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence)
14613+{
14614+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
14615+ unsigned int cur_fence;
14616+ int ret = 0;
14617+
14618+ /* Assume that the user has missed the current sequence number
14619+ * by about a day rather than she wants to wait for years
14620+ * using fences.
14621+ */
14622+ DRM_WAIT_ON(ret, dev_priv->fence_queue, 3 * DRM_HZ,
14623+ (((cur_fence = atomic_read(&dev_priv->last_fence_retired))
14624+ - *sequence) <= (1 << 23)));
14625+
14626+ *sequence = cur_fence;
14627+
14628+ return ret;
14629+}
14630+
14631+void mga_driver_irq_preinstall(struct drm_device * dev)
14632+{
14633+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
14634+
14635+ /* Disable *all* interrupts */
14636+ MGA_WRITE(MGA_IEN, 0);
14637+ /* Clear bits if they're already high */
14638+ MGA_WRITE(MGA_ICLEAR, ~0);
14639+}
14640+
14641+void mga_driver_irq_postinstall(struct drm_device * dev)
14642+{
14643+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
14644+
14645+ DRM_INIT_WAITQUEUE( &dev_priv->fence_queue );
14646+
14647+ /* Turn on vertical blank interrupt and soft trap interrupt. */
14648+ MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
14649+}
14650+
14651+void mga_driver_irq_uninstall(struct drm_device * dev)
14652+{
14653+ drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
14654+ if (!dev_priv)
14655+ return;
14656+
14657+ /* Disable *all* interrupts */
14658+ MGA_WRITE(MGA_IEN, 0);
14659+
14660+ dev->irq_enabled = 0;
14661+}
14662Index: git/shared-core/mga_state.c
14663===================================================================
14664--- /dev/null 1970-01-01 00:00:00.000000000 +0000
14665+++ git/shared-core/mga_state.c 2008-12-12 17:35:22.000000000 +0000
14666@@ -0,0 +1,1143 @@
14667+/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
14668+ * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
14669+ */
14670+/*
14671+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
14672+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14673+ * All Rights Reserved.
14674+ *
14675+ * Permission is hereby granted, free of charge, to any person obtaining a
14676+ * copy of this software and associated documentation files (the "Software"),
14677+ * to deal in the Software without restriction, including without limitation
14678+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14679+ * and/or sell copies of the Software, and to permit persons to whom the
14680+ * Software is furnished to do so, subject to the following conditions:
14681+ *
14682+ * The above copyright notice and this permission notice (including the next
14683+ * paragraph) shall be included in all copies or substantial portions of the
14684+ * Software.
14685+ *
14686+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14687+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14688+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
14689+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
14690+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
14691+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
14692+ * OTHER DEALINGS IN THE SOFTWARE.
14693+ *
14694+ * Authors:
14695+ * Jeff Hartmann <jhartmann@valinux.com>
14696+ * Keith Whitwell <keith@tungstengraphics.com>
14697+ *
14698+ * Rewritten by:
14699+ * Gareth Hughes <gareth@valinux.com>
14700+ */
14701+
14702+#include "drmP.h"
14703+#include "drm.h"
14704+#include "mga_drm.h"
14705+#include "mga_drv.h"
14706+
14707+/* ================================================================
14708+ * DMA hardware state programming functions
14709+ */
14710+
14711+static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
14712+ struct drm_clip_rect * box)
14713+{
14714+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14715+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
14716+ unsigned int pitch = dev_priv->front_pitch;
14717+ DMA_LOCALS;
14718+
14719+ BEGIN_DMA(2);
14720+
14721+ /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
14722+ */
14723+ if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
14724+ DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
14725+ MGA_LEN + MGA_EXEC, 0x80000000,
14726+ MGA_DWGCTL, ctx->dwgctl,
14727+ MGA_LEN + MGA_EXEC, 0x80000000);
14728+ }
14729+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
14730+ MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
14731+ MGA_YTOP, box->y1 * pitch,
14732+ MGA_YBOT, (box->y2 - 1) * pitch);
14733+
14734+ ADVANCE_DMA();
14735+}
14736+
14737+static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
14738+{
14739+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14740+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
14741+ DMA_LOCALS;
14742+
14743+ BEGIN_DMA(3);
14744+
14745+ DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
14746+ MGA_MACCESS, ctx->maccess,
14747+ MGA_PLNWT, ctx->plnwt,
14748+ MGA_DWGCTL, ctx->dwgctl);
14749+
14750+ DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
14751+ MGA_FOGCOL, ctx->fogcolor,
14752+ MGA_WFLAG, ctx->wflag,
14753+ MGA_ZORG, dev_priv->depth_offset);
14754+
14755+ DMA_BLOCK(MGA_FCOL, ctx->fcol,
14756+ MGA_DMAPAD, 0x00000000,
14757+ MGA_DMAPAD, 0x00000000,
14758+ MGA_DMAPAD, 0x00000000);
14759+
14760+ ADVANCE_DMA();
14761+}
14762+
14763+static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
14764+{
14765+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14766+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
14767+ DMA_LOCALS;
14768+
14769+ BEGIN_DMA(4);
14770+
14771+ DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
14772+ MGA_MACCESS, ctx->maccess,
14773+ MGA_PLNWT, ctx->plnwt,
14774+ MGA_DWGCTL, ctx->dwgctl);
14775+
14776+ DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
14777+ MGA_FOGCOL, ctx->fogcolor,
14778+ MGA_WFLAG, ctx->wflag,
14779+ MGA_ZORG, dev_priv->depth_offset);
14780+
14781+ DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
14782+ MGA_TDUALSTAGE0, ctx->tdualstage0,
14783+ MGA_TDUALSTAGE1, ctx->tdualstage1,
14784+ MGA_FCOL, ctx->fcol);
14785+
14786+ DMA_BLOCK(MGA_STENCIL, ctx->stencil,
14787+ MGA_STENCILCTL, ctx->stencilctl,
14788+ MGA_DMAPAD, 0x00000000,
14789+ MGA_DMAPAD, 0x00000000);
14790+
14791+ ADVANCE_DMA();
14792+}
14793+
14794+static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
14795+{
14796+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14797+ drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
14798+ DMA_LOCALS;
14799+
14800+ BEGIN_DMA(4);
14801+
14802+ DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
14803+ MGA_TEXCTL, tex->texctl,
14804+ MGA_TEXFILTER, tex->texfilter,
14805+ MGA_TEXBORDERCOL, tex->texbordercol);
14806+
14807+ DMA_BLOCK(MGA_TEXORG, tex->texorg,
14808+ MGA_TEXORG1, tex->texorg1,
14809+ MGA_TEXORG2, tex->texorg2,
14810+ MGA_TEXORG3, tex->texorg3);
14811+
14812+ DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
14813+ MGA_TEXWIDTH, tex->texwidth,
14814+ MGA_TEXHEIGHT, tex->texheight,
14815+ MGA_WR24, tex->texwidth);
14816+
14817+ DMA_BLOCK(MGA_WR34, tex->texheight,
14818+ MGA_TEXTRANS, 0x0000ffff,
14819+ MGA_TEXTRANSHIGH, 0x0000ffff,
14820+ MGA_DMAPAD, 0x00000000);
14821+
14822+ ADVANCE_DMA();
14823+}
14824+
14825+static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
14826+{
14827+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14828+ drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
14829+ DMA_LOCALS;
14830+
14831+/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
14832+/* tex->texctl, tex->texctl2); */
14833+
14834+ BEGIN_DMA(6);
14835+
14836+ DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
14837+ MGA_TEXCTL, tex->texctl,
14838+ MGA_TEXFILTER, tex->texfilter,
14839+ MGA_TEXBORDERCOL, tex->texbordercol);
14840+
14841+ DMA_BLOCK(MGA_TEXORG, tex->texorg,
14842+ MGA_TEXORG1, tex->texorg1,
14843+ MGA_TEXORG2, tex->texorg2,
14844+ MGA_TEXORG3, tex->texorg3);
14845+
14846+ DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
14847+ MGA_TEXWIDTH, tex->texwidth,
14848+ MGA_TEXHEIGHT, tex->texheight,
14849+ MGA_WR49, 0x00000000);
14850+
14851+ DMA_BLOCK(MGA_WR57, 0x00000000,
14852+ MGA_WR53, 0x00000000,
14853+ MGA_WR61, 0x00000000,
14854+ MGA_WR52, MGA_G400_WR_MAGIC);
14855+
14856+ DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
14857+ MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
14858+ MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
14859+ MGA_DMAPAD, 0x00000000);
14860+
14861+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
14862+ MGA_DMAPAD, 0x00000000,
14863+ MGA_TEXTRANS, 0x0000ffff,
14864+ MGA_TEXTRANSHIGH, 0x0000ffff);
14865+
14866+ ADVANCE_DMA();
14867+}
14868+
14869+static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
14870+{
14871+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14872+ drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
14873+ DMA_LOCALS;
14874+
14875+/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
14876+/* tex->texctl, tex->texctl2); */
14877+
14878+ BEGIN_DMA(5);
14879+
14880+ DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
14881+ MGA_MAP1_ENABLE |
14882+ MGA_G400_TC2_MAGIC),
14883+ MGA_TEXCTL, tex->texctl,
14884+ MGA_TEXFILTER, tex->texfilter,
14885+ MGA_TEXBORDERCOL, tex->texbordercol);
14886+
14887+ DMA_BLOCK(MGA_TEXORG, tex->texorg,
14888+ MGA_TEXORG1, tex->texorg1,
14889+ MGA_TEXORG2, tex->texorg2,
14890+ MGA_TEXORG3, tex->texorg3);
14891+
14892+ DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
14893+ MGA_TEXWIDTH, tex->texwidth,
14894+ MGA_TEXHEIGHT, tex->texheight,
14895+ MGA_WR49, 0x00000000);
14896+
14897+ DMA_BLOCK(MGA_WR57, 0x00000000,
14898+ MGA_WR53, 0x00000000,
14899+ MGA_WR61, 0x00000000,
14900+ MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
14901+
14902+ DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
14903+ MGA_TEXTRANS, 0x0000ffff,
14904+ MGA_TEXTRANSHIGH, 0x0000ffff,
14905+ MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
14906+
14907+ ADVANCE_DMA();
14908+}
14909+
14910+static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
14911+{
14912+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14913+ unsigned int pipe = sarea_priv->warp_pipe;
14914+ DMA_LOCALS;
14915+
14916+ BEGIN_DMA(3);
14917+
14918+ DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
14919+ MGA_WVRTXSZ, 0x00000007,
14920+ MGA_WFLAG, 0x00000000,
14921+ MGA_WR24, 0x00000000);
14922+
14923+ DMA_BLOCK(MGA_WR25, 0x00000100,
14924+ MGA_WR34, 0x00000000,
14925+ MGA_WR42, 0x0000ffff,
14926+ MGA_WR60, 0x0000ffff);
14927+
14928+ /* Padding required to to hardware bug.
14929+ */
14930+ DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
14931+ MGA_DMAPAD, 0xffffffff,
14932+ MGA_DMAPAD, 0xffffffff,
14933+ MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
14934+ MGA_WMODE_START | dev_priv->wagp_enable));
14935+
14936+ ADVANCE_DMA();
14937+}
14938+
14939+static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
14940+{
14941+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
14942+ unsigned int pipe = sarea_priv->warp_pipe;
14943+ DMA_LOCALS;
14944+
14945+/* printk("mga_g400_emit_pipe %x\n", pipe); */
14946+
14947+ BEGIN_DMA(10);
14948+
14949+ DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
14950+ MGA_DMAPAD, 0x00000000,
14951+ MGA_DMAPAD, 0x00000000,
14952+ MGA_DMAPAD, 0x00000000);
14953+
14954+ if (pipe & MGA_T2) {
14955+ DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
14956+ MGA_DMAPAD, 0x00000000,
14957+ MGA_DMAPAD, 0x00000000,
14958+ MGA_DMAPAD, 0x00000000);
14959+
14960+ DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
14961+ MGA_WACCEPTSEQ, 0x00000000,
14962+ MGA_WACCEPTSEQ, 0x00000000,
14963+ MGA_WACCEPTSEQ, 0x1e000000);
14964+ } else {
14965+ if (dev_priv->warp_pipe & MGA_T2) {
14966+ /* Flush the WARP pipe */
14967+ DMA_BLOCK(MGA_YDST, 0x00000000,
14968+ MGA_FXLEFT, 0x00000000,
14969+ MGA_FXRIGHT, 0x00000001,
14970+ MGA_DWGCTL, MGA_DWGCTL_FLUSH);
14971+
14972+ DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
14973+ MGA_DWGSYNC, 0x00007000,
14974+ MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
14975+ MGA_LEN + MGA_EXEC, 0x00000000);
14976+
14977+ DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
14978+ MGA_G400_TC2_MAGIC),
14979+ MGA_LEN + MGA_EXEC, 0x00000000,
14980+ MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
14981+ MGA_DMAPAD, 0x00000000);
14982+ }
14983+
14984+ DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
14985+ MGA_DMAPAD, 0x00000000,
14986+ MGA_DMAPAD, 0x00000000,
14987+ MGA_DMAPAD, 0x00000000);
14988+
14989+ DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
14990+ MGA_WACCEPTSEQ, 0x00000000,
14991+ MGA_WACCEPTSEQ, 0x00000000,
14992+ MGA_WACCEPTSEQ, 0x18000000);
14993+ }
14994+
14995+ DMA_BLOCK(MGA_WFLAG, 0x00000000,
14996+ MGA_WFLAG1, 0x00000000,
14997+ MGA_WR56, MGA_G400_WR56_MAGIC,
14998+ MGA_DMAPAD, 0x00000000);
14999+
15000+ DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */
15001+ MGA_WR57, 0x00000000, /* tex0 */
15002+ MGA_WR53, 0x00000000, /* tex1 */
15003+ MGA_WR61, 0x00000000); /* tex1 */
15004+
15005+ DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
15006+ MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
15007+ MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
15008+ MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */
15009+
15010+ /* Padding required to to hardware bug */
15011+ DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
15012+ MGA_DMAPAD, 0xffffffff,
15013+ MGA_DMAPAD, 0xffffffff,
15014+ MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
15015+ MGA_WMODE_START | dev_priv->wagp_enable));
15016+
15017+ ADVANCE_DMA();
15018+}
15019+
15020+static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
15021+{
15022+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15023+ unsigned int dirty = sarea_priv->dirty;
15024+
15025+ if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
15026+ mga_g200_emit_pipe(dev_priv);
15027+ dev_priv->warp_pipe = sarea_priv->warp_pipe;
15028+ }
15029+
15030+ if (dirty & MGA_UPLOAD_CONTEXT) {
15031+ mga_g200_emit_context(dev_priv);
15032+ sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
15033+ }
15034+
15035+ if (dirty & MGA_UPLOAD_TEX0) {
15036+ mga_g200_emit_tex0(dev_priv);
15037+ sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
15038+ }
15039+}
15040+
15041+static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
15042+{
15043+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15044+ unsigned int dirty = sarea_priv->dirty;
15045+ int multitex = sarea_priv->warp_pipe & MGA_T2;
15046+
15047+ if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
15048+ mga_g400_emit_pipe(dev_priv);
15049+ dev_priv->warp_pipe = sarea_priv->warp_pipe;
15050+ }
15051+
15052+ if (dirty & MGA_UPLOAD_CONTEXT) {
15053+ mga_g400_emit_context(dev_priv);
15054+ sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
15055+ }
15056+
15057+ if (dirty & MGA_UPLOAD_TEX0) {
15058+ mga_g400_emit_tex0(dev_priv);
15059+ sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
15060+ }
15061+
15062+ if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
15063+ mga_g400_emit_tex1(dev_priv);
15064+ sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
15065+ }
15066+}
15067+
15068+/* ================================================================
15069+ * SAREA state verification
15070+ */
15071+
15072+/* Disallow all write destinations except the front and backbuffer.
15073+ */
15074+static int mga_verify_context(drm_mga_private_t * dev_priv)
15075+{
15076+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15077+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
15078+
15079+ if (ctx->dstorg != dev_priv->front_offset &&
15080+ ctx->dstorg != dev_priv->back_offset) {
15081+ DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
15082+ ctx->dstorg, dev_priv->front_offset,
15083+ dev_priv->back_offset);
15084+ ctx->dstorg = 0;
15085+ return -EINVAL;
15086+ }
15087+
15088+ return 0;
15089+}
15090+
15091+/* Disallow texture reads from PCI space.
15092+ */
15093+static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
15094+{
15095+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15096+ drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
15097+ unsigned int org;
15098+
15099+ org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
15100+
15101+ if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
15102+ DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
15103+ tex->texorg = 0;
15104+ return -EINVAL;
15105+ }
15106+
15107+ return 0;
15108+}
15109+
15110+static int mga_verify_state(drm_mga_private_t * dev_priv)
15111+{
15112+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15113+ unsigned int dirty = sarea_priv->dirty;
15114+ int ret = 0;
15115+
15116+ if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
15117+ sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
15118+
15119+ if (dirty & MGA_UPLOAD_CONTEXT)
15120+ ret |= mga_verify_context(dev_priv);
15121+
15122+ if (dirty & MGA_UPLOAD_TEX0)
15123+ ret |= mga_verify_tex(dev_priv, 0);
15124+
15125+ if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
15126+ if (dirty & MGA_UPLOAD_TEX1)
15127+ ret |= mga_verify_tex(dev_priv, 1);
15128+
15129+ if (dirty & MGA_UPLOAD_PIPE)
15130+ ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
15131+ } else {
15132+ if (dirty & MGA_UPLOAD_PIPE)
15133+ ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
15134+ }
15135+
15136+ return (ret == 0);
15137+}
15138+
15139+static int mga_verify_iload(drm_mga_private_t * dev_priv,
15140+ unsigned int dstorg, unsigned int length)
15141+{
15142+ if (dstorg < dev_priv->texture_offset ||
15143+ dstorg + length > (dev_priv->texture_offset +
15144+ dev_priv->texture_size)) {
15145+ DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
15146+ return -EINVAL;
15147+ }
15148+
15149+ if (length & MGA_ILOAD_MASK) {
15150+ DRM_ERROR("*** bad iload length: 0x%x\n",
15151+ length & MGA_ILOAD_MASK);
15152+ return -EINVAL;
15153+ }
15154+
15155+ return 0;
15156+}
15157+
15158+static int mga_verify_blit(drm_mga_private_t * dev_priv,
15159+ unsigned int srcorg, unsigned int dstorg)
15160+{
15161+ if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
15162+ (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
15163+ DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
15164+ return -EINVAL;
15165+ }
15166+ return 0;
15167+}
15168+
15169+/* ================================================================
15170+ *
15171+ */
15172+
15173+static void mga_dma_dispatch_clear(struct drm_device * dev, drm_mga_clear_t * clear)
15174+{
15175+ drm_mga_private_t *dev_priv = dev->dev_private;
15176+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15177+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
15178+ struct drm_clip_rect *pbox = sarea_priv->boxes;
15179+ int nbox = sarea_priv->nbox;
15180+ int i;
15181+ DMA_LOCALS;
15182+ DRM_DEBUG("\n");
15183+
15184+ BEGIN_DMA(1);
15185+
15186+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15187+ MGA_DMAPAD, 0x00000000,
15188+ MGA_DWGSYNC, 0x00007100,
15189+ MGA_DWGSYNC, 0x00007000);
15190+
15191+ ADVANCE_DMA();
15192+
15193+ for (i = 0; i < nbox; i++) {
15194+ struct drm_clip_rect *box = &pbox[i];
15195+ u32 height = box->y2 - box->y1;
15196+
15197+ DRM_DEBUG(" from=%d,%d to=%d,%d\n",
15198+ box->x1, box->y1, box->x2, box->y2);
15199+
15200+ if (clear->flags & MGA_FRONT) {
15201+ BEGIN_DMA(2);
15202+
15203+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15204+ MGA_PLNWT, clear->color_mask,
15205+ MGA_YDSTLEN, (box->y1 << 16) | height,
15206+ MGA_FXBNDRY, (box->x2 << 16) | box->x1);
15207+
15208+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15209+ MGA_FCOL, clear->clear_color,
15210+ MGA_DSTORG, dev_priv->front_offset,
15211+ MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
15212+
15213+ ADVANCE_DMA();
15214+ }
15215+
15216+ if (clear->flags & MGA_BACK) {
15217+ BEGIN_DMA(2);
15218+
15219+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15220+ MGA_PLNWT, clear->color_mask,
15221+ MGA_YDSTLEN, (box->y1 << 16) | height,
15222+ MGA_FXBNDRY, (box->x2 << 16) | box->x1);
15223+
15224+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15225+ MGA_FCOL, clear->clear_color,
15226+ MGA_DSTORG, dev_priv->back_offset,
15227+ MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
15228+
15229+ ADVANCE_DMA();
15230+ }
15231+
15232+ if (clear->flags & MGA_DEPTH) {
15233+ BEGIN_DMA(2);
15234+
15235+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15236+ MGA_PLNWT, clear->depth_mask,
15237+ MGA_YDSTLEN, (box->y1 << 16) | height,
15238+ MGA_FXBNDRY, (box->x2 << 16) | box->x1);
15239+
15240+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15241+ MGA_FCOL, clear->clear_depth,
15242+ MGA_DSTORG, dev_priv->depth_offset,
15243+ MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
15244+
15245+ ADVANCE_DMA();
15246+ }
15247+
15248+ }
15249+
15250+ BEGIN_DMA(1);
15251+
15252+ /* Force reset of DWGCTL */
15253+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15254+ MGA_DMAPAD, 0x00000000,
15255+ MGA_PLNWT, ctx->plnwt,
15256+ MGA_DWGCTL, ctx->dwgctl);
15257+
15258+ ADVANCE_DMA();
15259+
15260+ FLUSH_DMA();
15261+}
15262+
15263+static void mga_dma_dispatch_swap(struct drm_device * dev)
15264+{
15265+ drm_mga_private_t *dev_priv = dev->dev_private;
15266+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15267+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
15268+ struct drm_clip_rect *pbox = sarea_priv->boxes;
15269+ int nbox = sarea_priv->nbox;
15270+ int i;
15271+ DMA_LOCALS;
15272+ DRM_DEBUG("\n");
15273+
15274+ sarea_priv->last_frame.head = dev_priv->prim.tail;
15275+ sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
15276+
15277+ BEGIN_DMA(4 + nbox);
15278+
15279+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15280+ MGA_DMAPAD, 0x00000000,
15281+ MGA_DWGSYNC, 0x00007100,
15282+ MGA_DWGSYNC, 0x00007000);
15283+
15284+ DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
15285+ MGA_MACCESS, dev_priv->maccess,
15286+ MGA_SRCORG, dev_priv->back_offset,
15287+ MGA_AR5, dev_priv->front_pitch);
15288+
15289+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15290+ MGA_DMAPAD, 0x00000000,
15291+ MGA_PLNWT, 0xffffffff,
15292+ MGA_DWGCTL, MGA_DWGCTL_COPY);
15293+
15294+ for (i = 0; i < nbox; i++) {
15295+ struct drm_clip_rect *box = &pbox[i];
15296+ u32 height = box->y2 - box->y1;
15297+ u32 start = box->y1 * dev_priv->front_pitch;
15298+
15299+ DRM_DEBUG(" from=%d,%d to=%d,%d\n",
15300+ box->x1, box->y1, box->x2, box->y2);
15301+
15302+ DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
15303+ MGA_AR3, start + box->x1,
15304+ MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
15305+ MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
15306+ }
15307+
15308+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15309+ MGA_PLNWT, ctx->plnwt,
15310+ MGA_SRCORG, dev_priv->front_offset,
15311+ MGA_DWGCTL, ctx->dwgctl);
15312+
15313+ ADVANCE_DMA();
15314+
15315+ FLUSH_DMA();
15316+
15317+ DRM_DEBUG("%s... done.\n", __FUNCTION__);
15318+}
15319+
15320+static void mga_dma_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
15321+{
15322+ drm_mga_private_t *dev_priv = dev->dev_private;
15323+ drm_mga_buf_priv_t *buf_priv = buf->dev_private;
15324+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15325+ u32 address = (u32) buf->bus_address;
15326+ u32 length = (u32) buf->used;
15327+ int i = 0;
15328+ DMA_LOCALS;
15329+ DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
15330+
15331+ if (buf->used) {
15332+ buf_priv->dispatched = 1;
15333+
15334+ MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
15335+
15336+ do {
15337+ if (i < sarea_priv->nbox) {
15338+ mga_emit_clip_rect(dev_priv,
15339+ &sarea_priv->boxes[i]);
15340+ }
15341+
15342+ BEGIN_DMA(1);
15343+
15344+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15345+ MGA_DMAPAD, 0x00000000,
15346+ MGA_SECADDRESS, (address |
15347+ MGA_DMA_VERTEX),
15348+ MGA_SECEND, ((address + length) |
15349+ dev_priv->dma_access));
15350+
15351+ ADVANCE_DMA();
15352+ } while (++i < sarea_priv->nbox);
15353+ }
15354+
15355+ if (buf_priv->discard) {
15356+ AGE_BUFFER(buf_priv);
15357+ buf->pending = 0;
15358+ buf->used = 0;
15359+ buf_priv->dispatched = 0;
15360+
15361+ mga_freelist_put(dev, buf);
15362+ }
15363+
15364+ FLUSH_DMA();
15365+}
15366+
15367+static void mga_dma_dispatch_indices(struct drm_device * dev, struct drm_buf * buf,
15368+ unsigned int start, unsigned int end)
15369+{
15370+ drm_mga_private_t *dev_priv = dev->dev_private;
15371+ drm_mga_buf_priv_t *buf_priv = buf->dev_private;
15372+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15373+ u32 address = (u32) buf->bus_address;
15374+ int i = 0;
15375+ DMA_LOCALS;
15376+ DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
15377+
15378+ if (start != end) {
15379+ buf_priv->dispatched = 1;
15380+
15381+ MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
15382+
15383+ do {
15384+ if (i < sarea_priv->nbox) {
15385+ mga_emit_clip_rect(dev_priv,
15386+ &sarea_priv->boxes[i]);
15387+ }
15388+
15389+ BEGIN_DMA(1);
15390+
15391+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15392+ MGA_DMAPAD, 0x00000000,
15393+ MGA_SETUPADDRESS, address + start,
15394+ MGA_SETUPEND, ((address + end) |
15395+ dev_priv->dma_access));
15396+
15397+ ADVANCE_DMA();
15398+ } while (++i < sarea_priv->nbox);
15399+ }
15400+
15401+ if (buf_priv->discard) {
15402+ AGE_BUFFER(buf_priv);
15403+ buf->pending = 0;
15404+ buf->used = 0;
15405+ buf_priv->dispatched = 0;
15406+
15407+ mga_freelist_put(dev, buf);
15408+ }
15409+
15410+ FLUSH_DMA();
15411+}
15412+
15413+/* This copies a 64 byte aligned agp region to the frambuffer with a
15414+ * standard blit, the ioctl needs to do checking.
15415+ */
15416+static void mga_dma_dispatch_iload(struct drm_device * dev, struct drm_buf * buf,
15417+ unsigned int dstorg, unsigned int length)
15418+{
15419+ drm_mga_private_t *dev_priv = dev->dev_private;
15420+ drm_mga_buf_priv_t *buf_priv = buf->dev_private;
15421+ drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
15422+ u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
15423+ u32 y2;
15424+ DMA_LOCALS;
15425+ DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
15426+
15427+ y2 = length / 64;
15428+
15429+ BEGIN_DMA(5);
15430+
15431+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15432+ MGA_DMAPAD, 0x00000000,
15433+ MGA_DWGSYNC, 0x00007100,
15434+ MGA_DWGSYNC, 0x00007000);
15435+
15436+ DMA_BLOCK(MGA_DSTORG, dstorg,
15437+ MGA_MACCESS, 0x00000000,
15438+ MGA_SRCORG, srcorg,
15439+ MGA_AR5, 64);
15440+
15441+ DMA_BLOCK(MGA_PITCH, 64,
15442+ MGA_PLNWT, 0xffffffff,
15443+ MGA_DMAPAD, 0x00000000,
15444+ MGA_DWGCTL, MGA_DWGCTL_COPY);
15445+
15446+ DMA_BLOCK(MGA_AR0, 63,
15447+ MGA_AR3, 0,
15448+ MGA_FXBNDRY, (63 << 16) | 0,
15449+ MGA_YDSTLEN + MGA_EXEC, y2);
15450+
15451+ DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
15452+ MGA_SRCORG, dev_priv->front_offset,
15453+ MGA_PITCH, dev_priv->front_pitch,
15454+ MGA_DWGSYNC, 0x00007000);
15455+
15456+ ADVANCE_DMA();
15457+
15458+ AGE_BUFFER(buf_priv);
15459+
15460+ buf->pending = 0;
15461+ buf->used = 0;
15462+ buf_priv->dispatched = 0;
15463+
15464+ mga_freelist_put(dev, buf);
15465+
15466+ FLUSH_DMA();
15467+}
15468+
15469+static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
15470+{
15471+ drm_mga_private_t *dev_priv = dev->dev_private;
15472+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15473+ drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
15474+ struct drm_clip_rect *pbox = sarea_priv->boxes;
15475+ int nbox = sarea_priv->nbox;
15476+ u32 scandir = 0, i;
15477+ DMA_LOCALS;
15478+ DRM_DEBUG("\n");
15479+
15480+ BEGIN_DMA(4 + nbox);
15481+
15482+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15483+ MGA_DMAPAD, 0x00000000,
15484+ MGA_DWGSYNC, 0x00007100,
15485+ MGA_DWGSYNC, 0x00007000);
15486+
15487+ DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
15488+ MGA_PLNWT, blit->planemask,
15489+ MGA_SRCORG, blit->srcorg,
15490+ MGA_DSTORG, blit->dstorg);
15491+
15492+ DMA_BLOCK(MGA_SGN, scandir,
15493+ MGA_MACCESS, dev_priv->maccess,
15494+ MGA_AR5, blit->ydir * blit->src_pitch,
15495+ MGA_PITCH, blit->dst_pitch);
15496+
15497+ for (i = 0; i < nbox; i++) {
15498+ int srcx = pbox[i].x1 + blit->delta_sx;
15499+ int srcy = pbox[i].y1 + blit->delta_sy;
15500+ int dstx = pbox[i].x1 + blit->delta_dx;
15501+ int dsty = pbox[i].y1 + blit->delta_dy;
15502+ int h = pbox[i].y2 - pbox[i].y1;
15503+ int w = pbox[i].x2 - pbox[i].x1 - 1;
15504+ int start;
15505+
15506+ if (blit->ydir == -1) {
15507+ srcy = blit->height - srcy - 1;
15508+ }
15509+
15510+ start = srcy * blit->src_pitch + srcx;
15511+
15512+ DMA_BLOCK(MGA_AR0, start + w,
15513+ MGA_AR3, start,
15514+ MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
15515+ MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
15516+ }
15517+
15518+ /* Do something to flush AGP?
15519+ */
15520+
15521+ /* Force reset of DWGCTL */
15522+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15523+ MGA_PLNWT, ctx->plnwt,
15524+ MGA_PITCH, dev_priv->front_pitch,
15525+ MGA_DWGCTL, ctx->dwgctl);
15526+
15527+ ADVANCE_DMA();
15528+}
15529+
15530+/* ================================================================
15531+ *
15532+ */
15533+
15534+static int mga_dma_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
15535+{
15536+ drm_mga_private_t *dev_priv = dev->dev_private;
15537+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15538+ drm_mga_clear_t *clear = data;
15539+
15540+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15541+
15542+ if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
15543+ sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
15544+
15545+ WRAP_TEST_WITH_RETURN(dev_priv);
15546+
15547+ mga_dma_dispatch_clear(dev, clear);
15548+
15549+ /* Make sure we restore the 3D state next time.
15550+ */
15551+ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
15552+
15553+ return 0;
15554+}
15555+
15556+static int mga_dma_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
15557+{
15558+ drm_mga_private_t *dev_priv = dev->dev_private;
15559+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15560+
15561+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15562+
15563+ if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
15564+ sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
15565+
15566+ WRAP_TEST_WITH_RETURN(dev_priv);
15567+
15568+ mga_dma_dispatch_swap(dev);
15569+
15570+ /* Make sure we restore the 3D state next time.
15571+ */
15572+ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
15573+
15574+ return 0;
15575+}
15576+
15577+static int mga_dma_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
15578+{
15579+ drm_mga_private_t *dev_priv = dev->dev_private;
15580+ struct drm_device_dma *dma = dev->dma;
15581+ struct drm_buf *buf;
15582+ drm_mga_buf_priv_t *buf_priv;
15583+ drm_mga_vertex_t *vertex = data;
15584+
15585+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15586+
15587+ if (vertex->idx < 0 || vertex->idx > dma->buf_count)
15588+ return -EINVAL;
15589+ buf = dma->buflist[vertex->idx];
15590+ buf_priv = buf->dev_private;
15591+
15592+ buf->used = vertex->used;
15593+ buf_priv->discard = vertex->discard;
15594+
15595+ if (!mga_verify_state(dev_priv)) {
15596+ if (vertex->discard) {
15597+ if (buf_priv->dispatched == 1)
15598+ AGE_BUFFER(buf_priv);
15599+ buf_priv->dispatched = 0;
15600+ mga_freelist_put(dev, buf);
15601+ }
15602+ return -EINVAL;
15603+ }
15604+
15605+ WRAP_TEST_WITH_RETURN(dev_priv);
15606+
15607+ mga_dma_dispatch_vertex(dev, buf);
15608+
15609+ return 0;
15610+}
15611+
15612+static int mga_dma_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
15613+{
15614+ drm_mga_private_t *dev_priv = dev->dev_private;
15615+ struct drm_device_dma *dma = dev->dma;
15616+ struct drm_buf *buf;
15617+ drm_mga_buf_priv_t *buf_priv;
15618+ drm_mga_indices_t *indices = data;
15619+
15620+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15621+
15622+ if (indices->idx < 0 || indices->idx > dma->buf_count)
15623+ return -EINVAL;
15624+
15625+ buf = dma->buflist[indices->idx];
15626+ buf_priv = buf->dev_private;
15627+
15628+ buf_priv->discard = indices->discard;
15629+
15630+ if (!mga_verify_state(dev_priv)) {
15631+ if (indices->discard) {
15632+ if (buf_priv->dispatched == 1)
15633+ AGE_BUFFER(buf_priv);
15634+ buf_priv->dispatched = 0;
15635+ mga_freelist_put(dev, buf);
15636+ }
15637+ return -EINVAL;
15638+ }
15639+
15640+ WRAP_TEST_WITH_RETURN(dev_priv);
15641+
15642+ mga_dma_dispatch_indices(dev, buf, indices->start, indices->end);
15643+
15644+ return 0;
15645+}
15646+
15647+static int mga_dma_iload(struct drm_device *dev, void *data, struct drm_file *file_priv)
15648+{
15649+ struct drm_device_dma *dma = dev->dma;
15650+ drm_mga_private_t *dev_priv = dev->dev_private;
15651+ struct drm_buf *buf;
15652+ drm_mga_buf_priv_t *buf_priv;
15653+ drm_mga_iload_t *iload = data;
15654+ DRM_DEBUG("\n");
15655+
15656+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15657+
15658+#if 0
15659+ if (mga_do_wait_for_idle(dev_priv) < 0) {
15660+ if (MGA_DMA_DEBUG)
15661+ DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
15662+ return -EBUSY;
15663+ }
15664+#endif
15665+ if (iload->idx < 0 || iload->idx > dma->buf_count)
15666+ return -EINVAL;
15667+
15668+ buf = dma->buflist[iload->idx];
15669+ buf_priv = buf->dev_private;
15670+
15671+ if (mga_verify_iload(dev_priv, iload->dstorg, iload->length)) {
15672+ mga_freelist_put(dev, buf);
15673+ return -EINVAL;
15674+ }
15675+
15676+ WRAP_TEST_WITH_RETURN(dev_priv);
15677+
15678+ mga_dma_dispatch_iload(dev, buf, iload->dstorg, iload->length);
15679+
15680+ /* Make sure we restore the 3D state next time.
15681+ */
15682+ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
15683+
15684+ return 0;
15685+}
15686+
15687+static int mga_dma_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
15688+{
15689+ drm_mga_private_t *dev_priv = dev->dev_private;
15690+ drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
15691+ drm_mga_blit_t *blit = data;
15692+ DRM_DEBUG("\n");
15693+
15694+ LOCK_TEST_WITH_RETURN(dev, file_priv);
15695+
15696+ if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
15697+ sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
15698+
15699+ if (mga_verify_blit(dev_priv, blit->srcorg, blit->dstorg))
15700+ return -EINVAL;
15701+
15702+ WRAP_TEST_WITH_RETURN(dev_priv);
15703+
15704+ mga_dma_dispatch_blit(dev, blit);
15705+
15706+ /* Make sure we restore the 3D state next time.
15707+ */
15708+ dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
15709+
15710+ return 0;
15711+}
15712+
15713+static int mga_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
15714+{
15715+ drm_mga_private_t *dev_priv = dev->dev_private;
15716+ drm_mga_getparam_t *param = data;
15717+ int value;
15718+
15719+ if (!dev_priv) {
15720+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
15721+ return -EINVAL;
15722+ }
15723+
15724+ DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
15725+
15726+ switch (param->param) {
15727+ case MGA_PARAM_IRQ_NR:
15728+ value = dev->irq;
15729+ break;
15730+ case MGA_PARAM_CARD_TYPE:
15731+ value = dev_priv->chipset;
15732+ break;
15733+ default:
15734+ return -EINVAL;
15735+ }
15736+
15737+ if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
15738+ DRM_ERROR("copy_to_user\n");
15739+ return -EFAULT;
15740+ }
15741+
15742+ return 0;
15743+}
15744+
15745+static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
15746+{
15747+ drm_mga_private_t *dev_priv = dev->dev_private;
15748+ u32 *fence = data;
15749+ DMA_LOCALS;
15750+
15751+ if (!dev_priv) {
15752+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
15753+ return -EINVAL;
15754+ }
15755+
15756+ DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
15757+
15758+ /* I would normal do this assignment in the declaration of fence,
15759+ * but dev_priv may be NULL.
15760+ */
15761+
15762+ *fence = dev_priv->next_fence_to_post;
15763+ dev_priv->next_fence_to_post++;
15764+
15765+ BEGIN_DMA(1);
15766+ DMA_BLOCK(MGA_DMAPAD, 0x00000000,
15767+ MGA_DMAPAD, 0x00000000,
15768+ MGA_DMAPAD, 0x00000000,
15769+ MGA_SOFTRAP, 0x00000000);
15770+ ADVANCE_DMA();
15771+
15772+ return 0;
15773+}
15774+
15775+static int mga_wait_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
15776+{
15777+ drm_mga_private_t *dev_priv = dev->dev_private;
15778+ u32 *fence = data;
15779+
15780+ if (!dev_priv) {
15781+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
15782+ return -EINVAL;
15783+ }
15784+
15785+ DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
15786+
15787+ mga_driver_fence_wait(dev, fence);
15788+
15789+ return 0;
15790+}
15791+
15792+struct drm_ioctl_desc mga_ioctls[] = {
15793+ DRM_IOCTL_DEF(DRM_MGA_INIT, mga_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
15794+ DRM_IOCTL_DEF(DRM_MGA_FLUSH, mga_dma_flush, DRM_AUTH),
15795+ DRM_IOCTL_DEF(DRM_MGA_RESET, mga_dma_reset, DRM_AUTH),
15796+ DRM_IOCTL_DEF(DRM_MGA_SWAP, mga_dma_swap, DRM_AUTH),
15797+ DRM_IOCTL_DEF(DRM_MGA_CLEAR, mga_dma_clear, DRM_AUTH),
15798+ DRM_IOCTL_DEF(DRM_MGA_VERTEX, mga_dma_vertex, DRM_AUTH),
15799+ DRM_IOCTL_DEF(DRM_MGA_INDICES, mga_dma_indices, DRM_AUTH),
15800+ DRM_IOCTL_DEF(DRM_MGA_ILOAD, mga_dma_iload, DRM_AUTH),
15801+ DRM_IOCTL_DEF(DRM_MGA_BLIT, mga_dma_blit, DRM_AUTH),
15802+ DRM_IOCTL_DEF(DRM_MGA_GETPARAM, mga_getparam, DRM_AUTH),
15803+ DRM_IOCTL_DEF(DRM_MGA_SET_FENCE, mga_set_fence, DRM_AUTH),
15804+ DRM_IOCTL_DEF(DRM_MGA_WAIT_FENCE, mga_wait_fence, DRM_AUTH),
15805+ DRM_IOCTL_DEF(DRM_MGA_DMA_BOOTSTRAP, mga_dma_bootstrap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
15806+
15807+};
15808+
15809+int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);
15810Index: git/shared-core/mga_ucode.h
15811===================================================================
15812--- /dev/null 1970-01-01 00:00:00.000000000 +0000
15813+++ git/shared-core/mga_ucode.h 2008-12-12 17:35:22.000000000 +0000
15814@@ -0,0 +1,11645 @@
15815+/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*-
15816+ * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com
15817+ *
15818+ * Copyright 1999 Matrox Graphics Inc.
15819+ * All Rights Reserved.
15820+ *
15821+ * Permission is hereby granted, free of charge, to any person obtaining a
15822+ * copy of this software and associated documentation files (the "Software"),
15823+ * to deal in the Software without restriction, including without limitation
15824+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15825+ * and/or sell copies of the Software, and to permit persons to whom the
15826+ * Software is furnished to do so, subject to the following conditions:
15827+ *
15828+ * The above copyright notice and this permission notice shall be included
15829+ * in all copies or substantial portions of the Software.
15830+ *
15831+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15832+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15833+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15834+ * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
15835+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
15836+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
15837+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
15838+ *
15839+ * Kernel-based WARP engine management:
15840+ * Gareth Hughes <gareth@valinux.com>
15841+ */
15842+
15843+/*
15844+ * WARP pipes are named according to the functions they perform, where:
15845+ *
15846+ * - T stands for computation of texture stage 0
15847+ * - T2 stands for computation of both texture stage 0 and texture stage 1
15848+ * - G stands for computation of triangle intensity (Gouraud interpolation)
15849+ * - Z stands for computation of Z buffer interpolation
15850+ * - S stands for computation of specular highlight
15851+ * - A stands for computation of the alpha channel
15852+ * - F stands for computation of vertex fog interpolation
15853+ */
15854+
15855+static unsigned char warp_g200_tgz[] = {
15856+
15857+ 0x00, 0x80, 0x00, 0xE8,
15858+ 0x00, 0x80, 0x00, 0xE8,
15859+
15860+ 0x00, 0x80, 0x00, 0xE8,
15861+ 0x00, 0x80, 0x00, 0xE8,
15862+
15863+ 0x00, 0x80, 0x00, 0xE8,
15864+ 0x00, 0x80, 0x00, 0xE8,
15865+
15866+ 0x00, 0x80, 0x00, 0xE8,
15867+ 0x00, 0x80, 0x00, 0xE8,
15868+
15869+ 0x00, 0x80, 0x00, 0xE8,
15870+ 0x00, 0x80, 0x00, 0xE8,
15871+
15872+ 0x00, 0x98, 0xA0, 0xE9,
15873+ 0x40, 0x40, 0xD8, 0xEC,
15874+
15875+ 0xFF, 0x80, 0xC0, 0xE9,
15876+ 0x00, 0x80, 0x00, 0xE8,
15877+
15878+ 0x1F, 0xD7, 0x18, 0xBD,
15879+ 0x3F, 0xD7, 0x22, 0xBD,
15880+
15881+ 0x81, 0x04,
15882+ 0x89, 0x04,
15883+ 0x01, 0x04,
15884+ 0x09, 0x04,
15885+
15886+ 0xC9, 0x41, 0xC0, 0xEC,
15887+ 0x11, 0x04,
15888+ 0x00, 0xE0,
15889+
15890+ 0x41, 0xCC, 0x41, 0xCD,
15891+ 0x49, 0xCC, 0x49, 0xCD,
15892+
15893+ 0xD1, 0x41, 0xC0, 0xEC,
15894+ 0x51, 0xCC, 0x51, 0xCD,
15895+
15896+ 0x80, 0x04,
15897+ 0x10, 0x04,
15898+ 0x08, 0x04,
15899+ 0x00, 0xE0,
15900+
15901+ 0x00, 0xCC, 0xC0, 0xCD,
15902+ 0xD1, 0x49, 0xC0, 0xEC,
15903+
15904+ 0x8A, 0x1F, 0x20, 0xE9,
15905+ 0x8B, 0x3F, 0x20, 0xE9,
15906+
15907+ 0x41, 0x3C, 0x41, 0xAD,
15908+ 0x49, 0x3C, 0x49, 0xAD,
15909+
15910+ 0x10, 0xCC, 0x10, 0xCD,
15911+ 0x08, 0xCC, 0x08, 0xCD,
15912+
15913+ 0xB9, 0x41, 0x49, 0xBB,
15914+ 0x1F, 0xF0, 0x41, 0xCD,
15915+
15916+ 0x51, 0x3C, 0x51, 0xAD,
15917+ 0x00, 0x98, 0x80, 0xE9,
15918+
15919+ 0x72, 0x80, 0x07, 0xEA,
15920+ 0x24, 0x1F, 0x20, 0xE9,
15921+
15922+ 0x15, 0x41, 0x49, 0xBD,
15923+ 0x1D, 0x41, 0x51, 0xBD,
15924+
15925+ 0x2E, 0x41, 0x2A, 0xB8,
15926+ 0x34, 0x53, 0xA0, 0xE8,
15927+
15928+ 0x15, 0x30,
15929+ 0x1D, 0x30,
15930+ 0x58, 0xE3,
15931+ 0x00, 0xE0,
15932+
15933+ 0xB5, 0x40, 0x48, 0xBD,
15934+ 0x3D, 0x40, 0x50, 0xBD,
15935+
15936+ 0x24, 0x43, 0xA0, 0xE8,
15937+ 0x2C, 0x4B, 0xA0, 0xE8,
15938+
15939+ 0x15, 0x72,
15940+ 0x09, 0xE3,
15941+ 0x00, 0xE0,
15942+ 0x1D, 0x72,
15943+
15944+ 0x35, 0x30,
15945+ 0xB5, 0x30,
15946+ 0xBD, 0x30,
15947+ 0x3D, 0x30,
15948+
15949+ 0x9C, 0x97, 0x57, 0x9F,
15950+ 0x00, 0x80, 0x00, 0xE8,
15951+
15952+ 0x6C, 0x64, 0xC8, 0xEC,
15953+ 0x98, 0xE1,
15954+ 0xB5, 0x05,
15955+
15956+ 0xBD, 0x05,
15957+ 0x2E, 0x30,
15958+ 0x32, 0xC0, 0xA0, 0xE8,
15959+
15960+ 0x33, 0xC0, 0xA0, 0xE8,
15961+ 0x74, 0x64, 0xC8, 0xEC,
15962+
15963+ 0x40, 0x3C, 0x40, 0xAD,
15964+ 0x32, 0x6A,
15965+ 0x2A, 0x30,
15966+
15967+ 0x20, 0x73,
15968+ 0x33, 0x6A,
15969+ 0x00, 0xE0,
15970+ 0x28, 0x73,
15971+
15972+ 0x1C, 0x72,
15973+ 0x83, 0xE2,
15974+ 0x60, 0x80, 0x15, 0xEA,
15975+
15976+ 0xB8, 0x3D, 0x28, 0xDF,
15977+ 0x30, 0x35, 0x20, 0xDF,
15978+
15979+ 0x40, 0x30,
15980+ 0x00, 0xE0,
15981+ 0xCC, 0xE2,
15982+ 0x64, 0x72,
15983+
15984+ 0x25, 0x42, 0x52, 0xBF,
15985+ 0x2D, 0x42, 0x4A, 0xBF,
15986+
15987+ 0x30, 0x2E, 0x30, 0xDF,
15988+ 0x38, 0x2E, 0x38, 0xDF,
15989+
15990+ 0x18, 0x1D, 0x45, 0xE9,
15991+ 0x1E, 0x15, 0x45, 0xE9,
15992+
15993+ 0x2B, 0x49, 0x51, 0xBD,
15994+ 0x00, 0xE0,
15995+ 0x1F, 0x73,
15996+
15997+ 0x38, 0x38, 0x40, 0xAF,
15998+ 0x30, 0x30, 0x40, 0xAF,
15999+
16000+ 0x24, 0x1F, 0x24, 0xDF,
16001+ 0x1D, 0x32, 0x20, 0xE9,
16002+
16003+ 0x2C, 0x1F, 0x2C, 0xDF,
16004+ 0x1A, 0x33, 0x20, 0xE9,
16005+
16006+ 0xB0, 0x10,
16007+ 0x08, 0xE3,
16008+ 0x40, 0x10,
16009+ 0xB8, 0x10,
16010+
16011+ 0x26, 0xF0, 0x30, 0xCD,
16012+ 0x2F, 0xF0, 0x38, 0xCD,
16013+
16014+ 0x2B, 0x80, 0x20, 0xE9,
16015+ 0x2A, 0x80, 0x20, 0xE9,
16016+
16017+ 0xA6, 0x20,
16018+ 0x88, 0xE2,
16019+ 0x00, 0xE0,
16020+ 0xAF, 0x20,
16021+
16022+ 0x28, 0x2A, 0x26, 0xAF,
16023+ 0x20, 0x2A, 0xC0, 0xAF,
16024+
16025+ 0x34, 0x1F, 0x34, 0xDF,
16026+ 0x46, 0x24, 0x46, 0xDF,
16027+
16028+ 0x28, 0x30, 0x80, 0xBF,
16029+ 0x20, 0x38, 0x80, 0xBF,
16030+
16031+ 0x47, 0x24, 0x47, 0xDF,
16032+ 0x4E, 0x2C, 0x4E, 0xDF,
16033+
16034+ 0x4F, 0x2C, 0x4F, 0xDF,
16035+ 0x56, 0x34, 0x56, 0xDF,
16036+
16037+ 0x28, 0x15, 0x28, 0xDF,
16038+ 0x20, 0x1D, 0x20, 0xDF,
16039+
16040+ 0x57, 0x34, 0x57, 0xDF,
16041+ 0x00, 0xE0,
16042+ 0x1D, 0x05,
16043+
16044+ 0x04, 0x80, 0x10, 0xEA,
16045+ 0x89, 0xE2,
16046+ 0x2B, 0x30,
16047+
16048+ 0x3F, 0xC1, 0x1D, 0xBD,
16049+ 0x00, 0x80, 0x00, 0xE8,
16050+
16051+ 0x00, 0x80, 0x00, 0xE8,
16052+ 0x00, 0x80, 0x00, 0xE8,
16053+
16054+ 0xA0, 0x68,
16055+ 0xBF, 0x25,
16056+ 0x00, 0x80, 0x00, 0xE8,
16057+
16058+ 0x20, 0xC0, 0x20, 0xAF,
16059+ 0x28, 0x05,
16060+ 0x97, 0x74,
16061+
16062+ 0x00, 0xE0,
16063+ 0x2A, 0x10,
16064+ 0x16, 0xC0, 0x20, 0xE9,
16065+
16066+ 0x04, 0x80, 0x10, 0xEA,
16067+ 0x8C, 0xE2,
16068+ 0x95, 0x05,
16069+
16070+ 0x28, 0xC1, 0x28, 0xAD,
16071+ 0x1F, 0xC1, 0x15, 0xBD,
16072+
16073+ 0x00, 0x80, 0x00, 0xE8,
16074+ 0x00, 0x80, 0x00, 0xE8,
16075+
16076+ 0xA8, 0x67,
16077+ 0x9F, 0x6B,
16078+ 0x00, 0x80, 0x00, 0xE8,
16079+
16080+ 0x28, 0xC0, 0x28, 0xAD,
16081+ 0x1D, 0x25,
16082+ 0x20, 0x05,
16083+
16084+ 0x28, 0x32, 0x80, 0xAD,
16085+ 0x40, 0x2A, 0x40, 0xBD,
16086+
16087+ 0x1C, 0x80, 0x20, 0xE9,
16088+ 0x20, 0x33, 0x20, 0xAD,
16089+
16090+ 0x20, 0x73,
16091+ 0x00, 0xE0,
16092+ 0xB6, 0x49, 0x51, 0xBB,
16093+
16094+ 0x26, 0x2F, 0xB0, 0xE8,
16095+ 0x19, 0x20, 0x20, 0xE9,
16096+
16097+ 0x35, 0x20, 0x35, 0xDF,
16098+ 0x3D, 0x20, 0x3D, 0xDF,
16099+
16100+ 0x15, 0x20, 0x15, 0xDF,
16101+ 0x1D, 0x20, 0x1D, 0xDF,
16102+
16103+ 0x26, 0xD0, 0x26, 0xCD,
16104+ 0x29, 0x49, 0x2A, 0xB8,
16105+
16106+ 0x26, 0x40, 0x80, 0xBD,
16107+ 0x3B, 0x48, 0x50, 0xBD,
16108+
16109+ 0x3E, 0x54, 0x57, 0x9F,
16110+ 0x00, 0xE0,
16111+ 0x82, 0xE1,
16112+
16113+ 0x1E, 0xAF, 0x59, 0x9F,
16114+ 0x00, 0x80, 0x00, 0xE8,
16115+
16116+ 0x26, 0x30,
16117+ 0x29, 0x30,
16118+ 0x48, 0x3C, 0x48, 0xAD,
16119+
16120+ 0x2B, 0x72,
16121+ 0xC2, 0xE1,
16122+ 0x2C, 0xC0, 0x44, 0xC2,
16123+
16124+ 0x05, 0x24, 0x34, 0xBF,
16125+ 0x0D, 0x24, 0x2C, 0xBF,
16126+
16127+ 0x2D, 0x46, 0x4E, 0xBF,
16128+ 0x25, 0x46, 0x56, 0xBF,
16129+
16130+ 0x20, 0x1D, 0x6F, 0x8F,
16131+ 0x32, 0x3E, 0x5F, 0xE9,
16132+
16133+ 0x3E, 0x50, 0x56, 0x9F,
16134+ 0x00, 0xE0,
16135+ 0x3B, 0x30,
16136+
16137+ 0x1E, 0x8F, 0x51, 0x9F,
16138+ 0x33, 0x1E, 0x5F, 0xE9,
16139+
16140+ 0x05, 0x44, 0x54, 0xB2,
16141+ 0x0D, 0x44, 0x4C, 0xB2,
16142+
16143+ 0x19, 0xC0, 0xB0, 0xE8,
16144+ 0x34, 0xC0, 0x44, 0xC4,
16145+
16146+ 0x33, 0x73,
16147+ 0x00, 0xE0,
16148+ 0x3E, 0x62, 0x57, 0x9F,
16149+
16150+ 0x1E, 0xAF, 0x59, 0x9F,
16151+ 0x00, 0xE0,
16152+ 0x0D, 0x20,
16153+
16154+ 0x84, 0x3E, 0x58, 0xE9,
16155+ 0x28, 0x1D, 0x6F, 0x8F,
16156+
16157+ 0x05, 0x20,
16158+ 0x00, 0xE0,
16159+ 0x85, 0x1E, 0x58, 0xE9,
16160+
16161+ 0x9B, 0x3B, 0x33, 0xDF,
16162+ 0x20, 0x20, 0x42, 0xAF,
16163+
16164+ 0x30, 0x42, 0x56, 0x9F,
16165+ 0x80, 0x3E, 0x57, 0xE9,
16166+
16167+ 0x3F, 0x8F, 0x51, 0x9F,
16168+ 0x30, 0x80, 0x5F, 0xE9,
16169+
16170+ 0x28, 0x28, 0x24, 0xAF,
16171+ 0x81, 0x1E, 0x57, 0xE9,
16172+
16173+ 0x05, 0x47, 0x57, 0xBF,
16174+ 0x0D, 0x47, 0x4F, 0xBF,
16175+
16176+ 0x88, 0x80, 0x58, 0xE9,
16177+ 0x1B, 0x29, 0x1B, 0xDF,
16178+
16179+ 0x30, 0x1D, 0x6F, 0x8F,
16180+ 0x3A, 0x30, 0x4F, 0xE9,
16181+
16182+ 0x1C, 0x30, 0x26, 0xDF,
16183+ 0x09, 0xE3,
16184+ 0x3B, 0x05,
16185+
16186+ 0x3E, 0x50, 0x56, 0x9F,
16187+ 0x3B, 0x3F, 0x4F, 0xE9,
16188+
16189+ 0x1E, 0x8F, 0x51, 0x9F,
16190+ 0x00, 0xE0,
16191+ 0xAC, 0x20,
16192+
16193+ 0x2D, 0x44, 0x4C, 0xB4,
16194+ 0x2C, 0x1C, 0xC0, 0xAF,
16195+
16196+ 0x25, 0x44, 0x54, 0xB4,
16197+ 0x00, 0xE0,
16198+ 0xC8, 0x30,
16199+
16200+ 0x30, 0x46, 0x30, 0xAF,
16201+ 0x1B, 0x1B, 0x48, 0xAF,
16202+
16203+ 0x00, 0xE0,
16204+ 0x25, 0x20,
16205+ 0x38, 0x2C, 0x4F, 0xE9,
16206+
16207+ 0x86, 0x80, 0x57, 0xE9,
16208+ 0x38, 0x1D, 0x6F, 0x8F,
16209+
16210+ 0x28, 0x74,
16211+ 0x00, 0xE0,
16212+ 0x0D, 0x44, 0x4C, 0xB0,
16213+
16214+ 0x05, 0x44, 0x54, 0xB0,
16215+ 0x2D, 0x20,
16216+ 0x9B, 0x10,
16217+
16218+ 0x82, 0x3E, 0x57, 0xE9,
16219+ 0x32, 0xF0, 0x1B, 0xCD,
16220+
16221+ 0x1E, 0xBD, 0x59, 0x9F,
16222+ 0x83, 0x1E, 0x57, 0xE9,
16223+
16224+ 0x38, 0x47, 0x38, 0xAF,
16225+ 0x34, 0x20,
16226+ 0x2A, 0x30,
16227+
16228+ 0x00, 0xE0,
16229+ 0x0D, 0x20,
16230+ 0x32, 0x20,
16231+ 0x05, 0x20,
16232+
16233+ 0x87, 0x80, 0x57, 0xE9,
16234+ 0x1F, 0x54, 0x57, 0x9F,
16235+
16236+ 0x17, 0x42, 0x56, 0x9F,
16237+ 0x00, 0xE0,
16238+ 0x3B, 0x6A,
16239+
16240+ 0x3F, 0x8F, 0x51, 0x9F,
16241+ 0x37, 0x1E, 0x4F, 0xE9,
16242+
16243+ 0x37, 0x32, 0x2A, 0xAF,
16244+ 0x00, 0xE0,
16245+ 0x32, 0x00,
16246+
16247+ 0x00, 0x80, 0x00, 0xE8,
16248+ 0x27, 0xC0, 0x44, 0xC0,
16249+
16250+ 0x36, 0x1F, 0x4F, 0xE9,
16251+ 0x1F, 0x1F, 0x26, 0xDF,
16252+
16253+ 0x37, 0x1B, 0x37, 0xBF,
16254+ 0x17, 0x26, 0x17, 0xDF,
16255+
16256+ 0x3E, 0x17, 0x4F, 0xE9,
16257+ 0x3F, 0x3F, 0x4F, 0xE9,
16258+
16259+ 0x34, 0x1F, 0x34, 0xAF,
16260+ 0x2B, 0x05,
16261+ 0xA7, 0x20,
16262+
16263+ 0x33, 0x2B, 0x37, 0xDF,
16264+ 0x27, 0x17, 0xC0, 0xAF,
16265+
16266+ 0x34, 0x80, 0x4F, 0xE9,
16267+ 0x00, 0x80, 0x00, 0xE8,
16268+
16269+ 0x03, 0x80, 0x0A, 0xEA,
16270+ 0x17, 0xC1, 0x2B, 0xBD,
16271+
16272+ 0x00, 0x80, 0x00, 0xE8,
16273+ 0x00, 0x80, 0x00, 0xE8,
16274+
16275+ 0xB3, 0x68,
16276+ 0x97, 0x25,
16277+ 0x00, 0x80, 0x00, 0xE8,
16278+
16279+ 0x33, 0xC0, 0x33, 0xAF,
16280+ 0x3C, 0x27, 0x4F, 0xE9,
16281+
16282+ 0x57, 0x39, 0x20, 0xE9,
16283+ 0x28, 0x19, 0x60, 0xEC,
16284+
16285+ 0x2B, 0x32, 0x20, 0xE9,
16286+ 0x1D, 0x3B, 0x20, 0xE9,
16287+
16288+ 0xB3, 0x05,
16289+ 0x00, 0xE0,
16290+ 0x16, 0x28, 0x20, 0xE9,
16291+
16292+ 0x23, 0x3B, 0x33, 0xAD,
16293+ 0x1E, 0x2B, 0x20, 0xE9,
16294+
16295+ 0x1C, 0x80, 0x20, 0xE9,
16296+ 0x57, 0x36, 0x20, 0xE9,
16297+
16298+ 0x00, 0x80, 0xA0, 0xE9,
16299+ 0x40, 0x40, 0xD8, 0xEC,
16300+
16301+ 0xFF, 0x80, 0xC0, 0xE9,
16302+ 0x90, 0xE2,
16303+ 0x00, 0xE0,
16304+
16305+ 0x85, 0xFF, 0x20, 0xEA,
16306+ 0x19, 0xC8, 0xC1, 0xCD,
16307+
16308+ 0x1F, 0xD7, 0x18, 0xBD,
16309+ 0x3F, 0xD7, 0x22, 0xBD,
16310+
16311+ 0x9F, 0x41, 0x49, 0xBD,
16312+ 0x00, 0x80, 0x00, 0xE8,
16313+
16314+ 0x25, 0x41, 0x49, 0xBD,
16315+ 0x2D, 0x41, 0x51, 0xBD,
16316+
16317+ 0x0D, 0x80, 0x07, 0xEA,
16318+ 0x00, 0x80, 0x00, 0xE8,
16319+
16320+ 0x35, 0x40, 0x48, 0xBD,
16321+ 0x3D, 0x40, 0x50, 0xBD,
16322+
16323+ 0x00, 0x80, 0x00, 0xE8,
16324+ 0x25, 0x30,
16325+ 0x2D, 0x30,
16326+
16327+ 0x35, 0x30,
16328+ 0xB5, 0x30,
16329+ 0xBD, 0x30,
16330+ 0x3D, 0x30,
16331+
16332+ 0x9C, 0xA7, 0x5B, 0x9F,
16333+ 0x00, 0x80, 0x00, 0xE8,
16334+
16335+ 0x00, 0x80, 0x00, 0xE8,
16336+ 0x00, 0x80, 0x00, 0xE8,
16337+
16338+ 0x00, 0x80, 0x00, 0xE8,
16339+ 0x00, 0x80, 0x00, 0xE8,
16340+
16341+ 0x00, 0x80, 0x00, 0xE8,
16342+ 0x00, 0x80, 0x00, 0xE8,
16343+
16344+ 0x00, 0x80, 0x00, 0xE8,
16345+ 0x00, 0x80, 0x00, 0xE8,
16346+
16347+ 0x84, 0xFF, 0x0A, 0xEA,
16348+ 0x00, 0x80, 0x00, 0xE8,
16349+
16350+ 0xC9, 0x41, 0xC8, 0xEC,
16351+ 0x42, 0xE1,
16352+ 0x00, 0xE0,
16353+
16354+ 0x82, 0xFF, 0x20, 0xEA,
16355+ 0x00, 0x80, 0x00, 0xE8,
16356+
16357+ 0x00, 0x80, 0x00, 0xE8,
16358+ 0x00, 0x80, 0x00, 0xE8,
16359+
16360+ 0xC8, 0x40, 0xC0, 0xEC,
16361+ 0x00, 0x80, 0x00, 0xE8,
16362+
16363+ 0x7F, 0xFF, 0x20, 0xEA,
16364+ 0x00, 0x80, 0x00, 0xE8,
16365+
16366+ 0x00, 0x80, 0x00, 0xE8,
16367+ 0x00, 0x80, 0x00, 0xE8,
16368+
16369+};
16370+
16371+static unsigned char warp_g200_tgza[] = {
16372+
16373+ 0x00, 0x98, 0xA0, 0xE9,
16374+ 0x40, 0x40, 0xD8, 0xEC,
16375+
16376+ 0xFF, 0x80, 0xC0, 0xE9,
16377+ 0x00, 0x80, 0x00, 0xE8,
16378+
16379+ 0x1F, 0xD7, 0x18, 0xBD,
16380+ 0x3F, 0xD7, 0x22, 0xBD,
16381+
16382+ 0x81, 0x04,
16383+ 0x89, 0x04,
16384+ 0x01, 0x04,
16385+ 0x09, 0x04,
16386+
16387+ 0xC9, 0x41, 0xC0, 0xEC,
16388+ 0x11, 0x04,
16389+ 0x00, 0xE0,
16390+
16391+ 0x41, 0xCC, 0x41, 0xCD,
16392+ 0x49, 0xCC, 0x49, 0xCD,
16393+
16394+ 0xD1, 0x41, 0xC0, 0xEC,
16395+ 0x51, 0xCC, 0x51, 0xCD,
16396+
16397+ 0x80, 0x04,
16398+ 0x10, 0x04,
16399+ 0x08, 0x04,
16400+ 0x00, 0xE0,
16401+
16402+ 0x00, 0xCC, 0xC0, 0xCD,
16403+ 0xD1, 0x49, 0xC0, 0xEC,
16404+
16405+ 0x8A, 0x1F, 0x20, 0xE9,
16406+ 0x8B, 0x3F, 0x20, 0xE9,
16407+
16408+ 0x41, 0x3C, 0x41, 0xAD,
16409+ 0x49, 0x3C, 0x49, 0xAD,
16410+
16411+ 0x10, 0xCC, 0x10, 0xCD,
16412+ 0x08, 0xCC, 0x08, 0xCD,
16413+
16414+ 0xB9, 0x41, 0x49, 0xBB,
16415+ 0x1F, 0xF0, 0x41, 0xCD,
16416+
16417+ 0x51, 0x3C, 0x51, 0xAD,
16418+ 0x00, 0x98, 0x80, 0xE9,
16419+
16420+ 0x7D, 0x80, 0x07, 0xEA,
16421+ 0x24, 0x1F, 0x20, 0xE9,
16422+
16423+ 0x15, 0x41, 0x49, 0xBD,
16424+ 0x1D, 0x41, 0x51, 0xBD,
16425+
16426+ 0x2E, 0x41, 0x2A, 0xB8,
16427+ 0x34, 0x53, 0xA0, 0xE8,
16428+
16429+ 0x15, 0x30,
16430+ 0x1D, 0x30,
16431+ 0x58, 0xE3,
16432+ 0x00, 0xE0,
16433+
16434+ 0xB5, 0x40, 0x48, 0xBD,
16435+ 0x3D, 0x40, 0x50, 0xBD,
16436+
16437+ 0x24, 0x43, 0xA0, 0xE8,
16438+ 0x2C, 0x4B, 0xA0, 0xE8,
16439+
16440+ 0x15, 0x72,
16441+ 0x09, 0xE3,
16442+ 0x00, 0xE0,
16443+ 0x1D, 0x72,
16444+
16445+ 0x35, 0x30,
16446+ 0xB5, 0x30,
16447+ 0xBD, 0x30,
16448+ 0x3D, 0x30,
16449+
16450+ 0x9C, 0x97, 0x57, 0x9F,
16451+ 0x00, 0x80, 0x00, 0xE8,
16452+
16453+ 0x6C, 0x64, 0xC8, 0xEC,
16454+ 0x98, 0xE1,
16455+ 0xB5, 0x05,
16456+
16457+ 0xBD, 0x05,
16458+ 0x2E, 0x30,
16459+ 0x32, 0xC0, 0xA0, 0xE8,
16460+
16461+ 0x33, 0xC0, 0xA0, 0xE8,
16462+ 0x74, 0x64, 0xC8, 0xEC,
16463+
16464+ 0x40, 0x3C, 0x40, 0xAD,
16465+ 0x32, 0x6A,
16466+ 0x2A, 0x30,
16467+
16468+ 0x20, 0x73,
16469+ 0x33, 0x6A,
16470+ 0x00, 0xE0,
16471+ 0x28, 0x73,
16472+
16473+ 0x1C, 0x72,
16474+ 0x83, 0xE2,
16475+ 0x6B, 0x80, 0x15, 0xEA,
16476+
16477+ 0xB8, 0x3D, 0x28, 0xDF,
16478+ 0x30, 0x35, 0x20, 0xDF,
16479+
16480+ 0x40, 0x30,
16481+ 0x00, 0xE0,
16482+ 0xCC, 0xE2,
16483+ 0x64, 0x72,
16484+
16485+ 0x25, 0x42, 0x52, 0xBF,
16486+ 0x2D, 0x42, 0x4A, 0xBF,
16487+
16488+ 0x30, 0x2E, 0x30, 0xDF,
16489+ 0x38, 0x2E, 0x38, 0xDF,
16490+
16491+ 0x18, 0x1D, 0x45, 0xE9,
16492+ 0x1E, 0x15, 0x45, 0xE9,
16493+
16494+ 0x2B, 0x49, 0x51, 0xBD,
16495+ 0x00, 0xE0,
16496+ 0x1F, 0x73,
16497+
16498+ 0x38, 0x38, 0x40, 0xAF,
16499+ 0x30, 0x30, 0x40, 0xAF,
16500+
16501+ 0x24, 0x1F, 0x24, 0xDF,
16502+ 0x1D, 0x32, 0x20, 0xE9,
16503+
16504+ 0x2C, 0x1F, 0x2C, 0xDF,
16505+ 0x1A, 0x33, 0x20, 0xE9,
16506+
16507+ 0xB0, 0x10,
16508+ 0x08, 0xE3,
16509+ 0x40, 0x10,
16510+ 0xB8, 0x10,
16511+
16512+ 0x26, 0xF0, 0x30, 0xCD,
16513+ 0x2F, 0xF0, 0x38, 0xCD,
16514+
16515+ 0x2B, 0x80, 0x20, 0xE9,
16516+ 0x2A, 0x80, 0x20, 0xE9,
16517+
16518+ 0xA6, 0x20,
16519+ 0x88, 0xE2,
16520+ 0x00, 0xE0,
16521+ 0xAF, 0x20,
16522+
16523+ 0x28, 0x2A, 0x26, 0xAF,
16524+ 0x20, 0x2A, 0xC0, 0xAF,
16525+
16526+ 0x34, 0x1F, 0x34, 0xDF,
16527+ 0x46, 0x24, 0x46, 0xDF,
16528+
16529+ 0x28, 0x30, 0x80, 0xBF,
16530+ 0x20, 0x38, 0x80, 0xBF,
16531+
16532+ 0x47, 0x24, 0x47, 0xDF,
16533+ 0x4E, 0x2C, 0x4E, 0xDF,
16534+
16535+ 0x4F, 0x2C, 0x4F, 0xDF,
16536+ 0x56, 0x34, 0x56, 0xDF,
16537+
16538+ 0x28, 0x15, 0x28, 0xDF,
16539+ 0x20, 0x1D, 0x20, 0xDF,
16540+
16541+ 0x57, 0x34, 0x57, 0xDF,
16542+ 0x00, 0xE0,
16543+ 0x1D, 0x05,
16544+
16545+ 0x04, 0x80, 0x10, 0xEA,
16546+ 0x89, 0xE2,
16547+ 0x2B, 0x30,
16548+
16549+ 0x3F, 0xC1, 0x1D, 0xBD,
16550+ 0x00, 0x80, 0x00, 0xE8,
16551+
16552+ 0x00, 0x80, 0x00, 0xE8,
16553+ 0x00, 0x80, 0x00, 0xE8,
16554+
16555+ 0xA0, 0x68,
16556+ 0xBF, 0x25,
16557+ 0x00, 0x80, 0x00, 0xE8,
16558+
16559+ 0x20, 0xC0, 0x20, 0xAF,
16560+ 0x28, 0x05,
16561+ 0x97, 0x74,
16562+
16563+ 0x00, 0xE0,
16564+ 0x2A, 0x10,
16565+ 0x16, 0xC0, 0x20, 0xE9,
16566+
16567+ 0x04, 0x80, 0x10, 0xEA,
16568+ 0x8C, 0xE2,
16569+ 0x95, 0x05,
16570+
16571+ 0x28, 0xC1, 0x28, 0xAD,
16572+ 0x1F, 0xC1, 0x15, 0xBD,
16573+
16574+ 0x00, 0x80, 0x00, 0xE8,
16575+ 0x00, 0x80, 0x00, 0xE8,
16576+
16577+ 0xA8, 0x67,
16578+ 0x9F, 0x6B,
16579+ 0x00, 0x80, 0x00, 0xE8,
16580+
16581+ 0x28, 0xC0, 0x28, 0xAD,
16582+ 0x1D, 0x25,
16583+ 0x20, 0x05,
16584+
16585+ 0x28, 0x32, 0x80, 0xAD,
16586+ 0x40, 0x2A, 0x40, 0xBD,
16587+
16588+ 0x1C, 0x80, 0x20, 0xE9,
16589+ 0x20, 0x33, 0x20, 0xAD,
16590+
16591+ 0x20, 0x73,
16592+ 0x00, 0xE0,
16593+ 0xB6, 0x49, 0x51, 0xBB,
16594+
16595+ 0x26, 0x2F, 0xB0, 0xE8,
16596+ 0x19, 0x20, 0x20, 0xE9,
16597+
16598+ 0x35, 0x20, 0x35, 0xDF,
16599+ 0x3D, 0x20, 0x3D, 0xDF,
16600+
16601+ 0x15, 0x20, 0x15, 0xDF,
16602+ 0x1D, 0x20, 0x1D, 0xDF,
16603+
16604+ 0x26, 0xD0, 0x26, 0xCD,
16605+ 0x29, 0x49, 0x2A, 0xB8,
16606+
16607+ 0x26, 0x40, 0x80, 0xBD,
16608+ 0x3B, 0x48, 0x50, 0xBD,
16609+
16610+ 0x3E, 0x54, 0x57, 0x9F,
16611+ 0x00, 0xE0,
16612+ 0x82, 0xE1,
16613+
16614+ 0x1E, 0xAF, 0x59, 0x9F,
16615+ 0x00, 0x80, 0x00, 0xE8,
16616+
16617+ 0x26, 0x30,
16618+ 0x29, 0x30,
16619+ 0x48, 0x3C, 0x48, 0xAD,
16620+
16621+ 0x2B, 0x72,
16622+ 0xC2, 0xE1,
16623+ 0x2C, 0xC0, 0x44, 0xC2,
16624+
16625+ 0x05, 0x24, 0x34, 0xBF,
16626+ 0x0D, 0x24, 0x2C, 0xBF,
16627+
16628+ 0x2D, 0x46, 0x4E, 0xBF,
16629+ 0x25, 0x46, 0x56, 0xBF,
16630+
16631+ 0x20, 0x1D, 0x6F, 0x8F,
16632+ 0x32, 0x3E, 0x5F, 0xE9,
16633+
16634+ 0x3E, 0x50, 0x56, 0x9F,
16635+ 0x00, 0xE0,
16636+ 0x3B, 0x30,
16637+
16638+ 0x1E, 0x8F, 0x51, 0x9F,
16639+ 0x33, 0x1E, 0x5F, 0xE9,
16640+
16641+ 0x05, 0x44, 0x54, 0xB2,
16642+ 0x0D, 0x44, 0x4C, 0xB2,
16643+
16644+ 0x19, 0xC0, 0xB0, 0xE8,
16645+ 0x34, 0xC0, 0x44, 0xC4,
16646+
16647+ 0x33, 0x73,
16648+ 0x00, 0xE0,
16649+ 0x3E, 0x62, 0x57, 0x9F,
16650+
16651+ 0x1E, 0xAF, 0x59, 0x9F,
16652+ 0x00, 0xE0,
16653+ 0x0D, 0x20,
16654+
16655+ 0x84, 0x3E, 0x58, 0xE9,
16656+ 0x28, 0x1D, 0x6F, 0x8F,
16657+
16658+ 0x05, 0x20,
16659+ 0x00, 0xE0,
16660+ 0x85, 0x1E, 0x58, 0xE9,
16661+
16662+ 0x9B, 0x3B, 0x33, 0xDF,
16663+ 0x20, 0x20, 0x42, 0xAF,
16664+
16665+ 0x30, 0x42, 0x56, 0x9F,
16666+ 0x80, 0x3E, 0x57, 0xE9,
16667+
16668+ 0x3F, 0x8F, 0x51, 0x9F,
16669+ 0x30, 0x80, 0x5F, 0xE9,
16670+
16671+ 0x28, 0x28, 0x24, 0xAF,
16672+ 0x81, 0x1E, 0x57, 0xE9,
16673+
16674+ 0x05, 0x47, 0x57, 0xBF,
16675+ 0x0D, 0x47, 0x4F, 0xBF,
16676+
16677+ 0x88, 0x80, 0x58, 0xE9,
16678+ 0x1B, 0x29, 0x1B, 0xDF,
16679+
16680+ 0x30, 0x1D, 0x6F, 0x8F,
16681+ 0x3A, 0x30, 0x4F, 0xE9,
16682+
16683+ 0x1C, 0x30, 0x26, 0xDF,
16684+ 0x09, 0xE3,
16685+ 0x3B, 0x05,
16686+
16687+ 0x3E, 0x50, 0x56, 0x9F,
16688+ 0x3B, 0x3F, 0x4F, 0xE9,
16689+
16690+ 0x1E, 0x8F, 0x51, 0x9F,
16691+ 0x00, 0xE0,
16692+ 0xAC, 0x20,
16693+
16694+ 0x2D, 0x44, 0x4C, 0xB4,
16695+ 0x2C, 0x1C, 0xC0, 0xAF,
16696+
16697+ 0x25, 0x44, 0x54, 0xB4,
16698+ 0x00, 0xE0,
16699+ 0xC8, 0x30,
16700+
16701+ 0x30, 0x46, 0x30, 0xAF,
16702+ 0x1B, 0x1B, 0x48, 0xAF,
16703+
16704+ 0x00, 0xE0,
16705+ 0x25, 0x20,
16706+ 0x38, 0x2C, 0x4F, 0xE9,
16707+
16708+ 0x86, 0x80, 0x57, 0xE9,
16709+ 0x38, 0x1D, 0x6F, 0x8F,
16710+
16711+ 0x28, 0x74,
16712+ 0x00, 0xE0,
16713+ 0x0D, 0x44, 0x4C, 0xB0,
16714+
16715+ 0x05, 0x44, 0x54, 0xB0,
16716+ 0x2D, 0x20,
16717+ 0x9B, 0x10,
16718+
16719+ 0x82, 0x3E, 0x57, 0xE9,
16720+ 0x32, 0xF0, 0x1B, 0xCD,
16721+
16722+ 0x1E, 0xBD, 0x59, 0x9F,
16723+ 0x83, 0x1E, 0x57, 0xE9,
16724+
16725+ 0x38, 0x47, 0x38, 0xAF,
16726+ 0x34, 0x20,
16727+ 0x2A, 0x30,
16728+
16729+ 0x00, 0xE0,
16730+ 0x0D, 0x20,
16731+ 0x32, 0x20,
16732+ 0x05, 0x20,
16733+
16734+ 0x87, 0x80, 0x57, 0xE9,
16735+ 0x1F, 0x54, 0x57, 0x9F,
16736+
16737+ 0x17, 0x42, 0x56, 0x9F,
16738+ 0x00, 0xE0,
16739+ 0x3B, 0x6A,
16740+
16741+ 0x3F, 0x8F, 0x51, 0x9F,
16742+ 0x37, 0x1E, 0x4F, 0xE9,
16743+
16744+ 0x37, 0x32, 0x2A, 0xAF,
16745+ 0x00, 0xE0,
16746+ 0x32, 0x00,
16747+
16748+ 0x00, 0x80, 0x00, 0xE8,
16749+ 0x27, 0xC0, 0x44, 0xC0,
16750+
16751+ 0x36, 0x1F, 0x4F, 0xE9,
16752+ 0x1F, 0x1F, 0x26, 0xDF,
16753+
16754+ 0x37, 0x1B, 0x37, 0xBF,
16755+ 0x17, 0x26, 0x17, 0xDF,
16756+
16757+ 0x3E, 0x17, 0x4F, 0xE9,
16758+ 0x3F, 0x3F, 0x4F, 0xE9,
16759+
16760+ 0x34, 0x1F, 0x34, 0xAF,
16761+ 0x2B, 0x05,
16762+ 0xA7, 0x20,
16763+
16764+ 0x33, 0x2B, 0x37, 0xDF,
16765+ 0x27, 0x17, 0xC0, 0xAF,
16766+
16767+ 0x34, 0x80, 0x4F, 0xE9,
16768+ 0x00, 0x80, 0x00, 0xE8,
16769+
16770+ 0x2D, 0x44, 0x4C, 0xB6,
16771+ 0x25, 0x44, 0x54, 0xB6,
16772+
16773+ 0x03, 0x80, 0x2A, 0xEA,
16774+ 0x17, 0xC1, 0x2B, 0xBD,
16775+
16776+ 0x2D, 0x20,
16777+ 0x25, 0x20,
16778+ 0x07, 0xC0, 0x44, 0xC6,
16779+
16780+ 0xB3, 0x68,
16781+ 0x97, 0x25,
16782+ 0x00, 0x80, 0x00, 0xE8,
16783+
16784+ 0x33, 0xC0, 0x33, 0xAF,
16785+ 0x3C, 0x27, 0x4F, 0xE9,
16786+
16787+ 0x1F, 0x62, 0x57, 0x9F,
16788+ 0x00, 0x80, 0x00, 0xE8,
16789+
16790+ 0x3F, 0x3D, 0x5D, 0x9F,
16791+ 0x00, 0xE0,
16792+ 0x07, 0x20,
16793+
16794+ 0x00, 0x80, 0x00, 0xE8,
16795+ 0x28, 0x19, 0x60, 0xEC,
16796+
16797+ 0xB3, 0x05,
16798+ 0x00, 0xE0,
16799+ 0x00, 0x80, 0x00, 0xE8,
16800+
16801+ 0x23, 0x3B, 0x33, 0xAD,
16802+ 0x00, 0x80, 0x00, 0xE8,
16803+
16804+ 0x1F, 0x26, 0x1F, 0xDF,
16805+ 0x9D, 0x1F, 0x4F, 0xE9,
16806+
16807+ 0x00, 0x80, 0x00, 0xE8,
16808+ 0x00, 0x80, 0x00, 0xE8,
16809+
16810+ 0x00, 0x80, 0x00, 0xE8,
16811+ 0x9E, 0x3F, 0x4F, 0xE9,
16812+
16813+ 0x07, 0x07, 0x1F, 0xAF,
16814+ 0x00, 0x80, 0x00, 0xE8,
16815+
16816+ 0x00, 0x80, 0x00, 0xE8,
16817+ 0x00, 0x80, 0x00, 0xE8,
16818+
16819+ 0x9C, 0x80, 0x4F, 0xE9,
16820+ 0x00, 0x80, 0x00, 0xE8,
16821+
16822+ 0x00, 0x80, 0x00, 0xE8,
16823+ 0x57, 0x39, 0x20, 0xE9,
16824+
16825+ 0x16, 0x28, 0x20, 0xE9,
16826+ 0x1D, 0x3B, 0x20, 0xE9,
16827+
16828+ 0x1E, 0x2B, 0x20, 0xE9,
16829+ 0x2B, 0x32, 0x20, 0xE9,
16830+
16831+ 0x1C, 0x23, 0x20, 0xE9,
16832+ 0x57, 0x36, 0x20, 0xE9,
16833+
16834+ 0x00, 0x80, 0xA0, 0xE9,
16835+ 0x40, 0x40, 0xD8, 0xEC,
16836+
16837+ 0xFF, 0x80, 0xC0, 0xE9,
16838+ 0x90, 0xE2,
16839+ 0x00, 0xE0,
16840+
16841+ 0x7A, 0xFF, 0x20, 0xEA,
16842+ 0x19, 0xC8, 0xC1, 0xCD,
16843+
16844+ 0x1F, 0xD7, 0x18, 0xBD,
16845+ 0x3F, 0xD7, 0x22, 0xBD,
16846+
16847+ 0x9F, 0x41, 0x49, 0xBD,
16848+ 0x00, 0x80, 0x00, 0xE8,
16849+
16850+ 0x25, 0x41, 0x49, 0xBD,
16851+ 0x2D, 0x41, 0x51, 0xBD,
16852+
16853+ 0x0D, 0x80, 0x07, 0xEA,
16854+ 0x00, 0x80, 0x00, 0xE8,
16855+
16856+ 0x35, 0x40, 0x48, 0xBD,
16857+ 0x3D, 0x40, 0x50, 0xBD,
16858+
16859+ 0x00, 0x80, 0x00, 0xE8,
16860+ 0x25, 0x30,
16861+ 0x2D, 0x30,
16862+
16863+ 0x35, 0x30,
16864+ 0xB5, 0x30,
16865+ 0xBD, 0x30,
16866+ 0x3D, 0x30,
16867+
16868+ 0x9C, 0xA7, 0x5B, 0x9F,
16869+ 0x00, 0x80, 0x00, 0xE8,
16870+
16871+ 0x00, 0x80, 0x00, 0xE8,
16872+ 0x00, 0x80, 0x00, 0xE8,
16873+
16874+ 0x00, 0x80, 0x00, 0xE8,
16875+ 0x00, 0x80, 0x00, 0xE8,
16876+
16877+ 0x00, 0x80, 0x00, 0xE8,
16878+ 0x00, 0x80, 0x00, 0xE8,
16879+
16880+ 0x00, 0x80, 0x00, 0xE8,
16881+ 0x00, 0x80, 0x00, 0xE8,
16882+
16883+ 0x79, 0xFF, 0x0A, 0xEA,
16884+ 0x00, 0x80, 0x00, 0xE8,
16885+
16886+ 0xC9, 0x41, 0xC8, 0xEC,
16887+ 0x42, 0xE1,
16888+ 0x00, 0xE0,
16889+
16890+ 0x77, 0xFF, 0x20, 0xEA,
16891+ 0x00, 0x80, 0x00, 0xE8,
16892+
16893+ 0x00, 0x80, 0x00, 0xE8,
16894+ 0x00, 0x80, 0x00, 0xE8,
16895+
16896+ 0xC8, 0x40, 0xC0, 0xEC,
16897+ 0x00, 0x80, 0x00, 0xE8,
16898+
16899+ 0x74, 0xFF, 0x20, 0xEA,
16900+ 0x00, 0x80, 0x00, 0xE8,
16901+
16902+ 0x00, 0x80, 0x00, 0xE8,
16903+ 0x00, 0x80, 0x00, 0xE8,
16904+
16905+};
16906+
16907+static unsigned char warp_g200_tgzaf[] = {
16908+
16909+ 0x00, 0x80, 0x00, 0xE8,
16910+ 0x00, 0x80, 0x00, 0xE8,
16911+
16912+ 0x00, 0x80, 0x00, 0xE8,
16913+ 0x00, 0x80, 0x00, 0xE8,
16914+
16915+ 0x00, 0x80, 0x00, 0xE8,
16916+ 0x00, 0x80, 0x00, 0xE8,
16917+
16918+ 0x00, 0x80, 0x00, 0xE8,
16919+ 0x00, 0x80, 0x00, 0xE8,
16920+
16921+ 0x00, 0x80, 0x00, 0xE8,
16922+ 0x00, 0x80, 0x00, 0xE8,
16923+
16924+ 0x00, 0x80, 0x00, 0xE8,
16925+ 0x00, 0x80, 0x00, 0xE8,
16926+
16927+ 0x00, 0x80, 0x00, 0xE8,
16928+ 0x00, 0x80, 0x00, 0xE8,
16929+
16930+ 0x00, 0x80, 0x00, 0xE8,
16931+ 0x00, 0x80, 0x00, 0xE8,
16932+
16933+ 0x00, 0x80, 0x00, 0xE8,
16934+ 0x00, 0x80, 0x00, 0xE8,
16935+
16936+ 0x00, 0x80, 0x00, 0xE8,
16937+ 0x00, 0x80, 0x00, 0xE8,
16938+
16939+ 0x00, 0x98, 0xA0, 0xE9,
16940+ 0x40, 0x40, 0xD8, 0xEC,
16941+
16942+ 0xFF, 0x80, 0xC0, 0xE9,
16943+ 0x00, 0x80, 0x00, 0xE8,
16944+
16945+ 0x1F, 0xD7, 0x18, 0xBD,
16946+ 0x3F, 0xD7, 0x22, 0xBD,
16947+
16948+ 0x81, 0x04,
16949+ 0x89, 0x04,
16950+ 0x01, 0x04,
16951+ 0x09, 0x04,
16952+
16953+ 0xC9, 0x41, 0xC0, 0xEC,
16954+ 0x11, 0x04,
16955+ 0x00, 0xE0,
16956+
16957+ 0x41, 0xCC, 0x41, 0xCD,
16958+ 0x49, 0xCC, 0x49, 0xCD,
16959+
16960+ 0xD1, 0x41, 0xC0, 0xEC,
16961+ 0x51, 0xCC, 0x51, 0xCD,
16962+
16963+ 0x80, 0x04,
16964+ 0x10, 0x04,
16965+ 0x08, 0x04,
16966+ 0x00, 0xE0,
16967+
16968+ 0x00, 0xCC, 0xC0, 0xCD,
16969+ 0xD1, 0x49, 0xC0, 0xEC,
16970+
16971+ 0x8A, 0x1F, 0x20, 0xE9,
16972+ 0x8B, 0x3F, 0x20, 0xE9,
16973+
16974+ 0x41, 0x3C, 0x41, 0xAD,
16975+ 0x49, 0x3C, 0x49, 0xAD,
16976+
16977+ 0x10, 0xCC, 0x10, 0xCD,
16978+ 0x08, 0xCC, 0x08, 0xCD,
16979+
16980+ 0xB9, 0x41, 0x49, 0xBB,
16981+ 0x1F, 0xF0, 0x41, 0xCD,
16982+
16983+ 0x51, 0x3C, 0x51, 0xAD,
16984+ 0x00, 0x98, 0x80, 0xE9,
16985+
16986+ 0x83, 0x80, 0x07, 0xEA,
16987+ 0x24, 0x1F, 0x20, 0xE9,
16988+
16989+ 0x21, 0x45, 0x80, 0xE8,
16990+ 0x1A, 0x4D, 0x80, 0xE8,
16991+
16992+ 0x31, 0x55, 0x80, 0xE8,
16993+ 0x00, 0x80, 0x00, 0xE8,
16994+
16995+ 0x15, 0x41, 0x49, 0xBD,
16996+ 0x1D, 0x41, 0x51, 0xBD,
16997+
16998+ 0x2E, 0x41, 0x2A, 0xB8,
16999+ 0x34, 0x53, 0xA0, 0xE8,
17000+
17001+ 0x15, 0x30,
17002+ 0x1D, 0x30,
17003+ 0x58, 0xE3,
17004+ 0x00, 0xE0,
17005+
17006+ 0xB5, 0x40, 0x48, 0xBD,
17007+ 0x3D, 0x40, 0x50, 0xBD,
17008+
17009+ 0x24, 0x43, 0xA0, 0xE8,
17010+ 0x2C, 0x4B, 0xA0, 0xE8,
17011+
17012+ 0x15, 0x72,
17013+ 0x09, 0xE3,
17014+ 0x00, 0xE0,
17015+ 0x1D, 0x72,
17016+
17017+ 0x35, 0x30,
17018+ 0xB5, 0x30,
17019+ 0xBD, 0x30,
17020+ 0x3D, 0x30,
17021+
17022+ 0x9C, 0x97, 0x57, 0x9F,
17023+ 0x00, 0x80, 0x00, 0xE8,
17024+
17025+ 0x6C, 0x64, 0xC8, 0xEC,
17026+ 0x98, 0xE1,
17027+ 0xB5, 0x05,
17028+
17029+ 0xBD, 0x05,
17030+ 0x2E, 0x30,
17031+ 0x32, 0xC0, 0xA0, 0xE8,
17032+
17033+ 0x33, 0xC0, 0xA0, 0xE8,
17034+ 0x74, 0x64, 0xC8, 0xEC,
17035+
17036+ 0x40, 0x3C, 0x40, 0xAD,
17037+ 0x32, 0x6A,
17038+ 0x2A, 0x30,
17039+
17040+ 0x20, 0x73,
17041+ 0x33, 0x6A,
17042+ 0x00, 0xE0,
17043+ 0x28, 0x73,
17044+
17045+ 0x1C, 0x72,
17046+ 0x83, 0xE2,
17047+ 0x6F, 0x80, 0x15, 0xEA,
17048+
17049+ 0xB8, 0x3D, 0x28, 0xDF,
17050+ 0x30, 0x35, 0x20, 0xDF,
17051+
17052+ 0x40, 0x30,
17053+ 0x00, 0xE0,
17054+ 0xCC, 0xE2,
17055+ 0x64, 0x72,
17056+
17057+ 0x25, 0x42, 0x52, 0xBF,
17058+ 0x2D, 0x42, 0x4A, 0xBF,
17059+
17060+ 0x30, 0x2E, 0x30, 0xDF,
17061+ 0x38, 0x2E, 0x38, 0xDF,
17062+
17063+ 0x18, 0x1D, 0x45, 0xE9,
17064+ 0x1E, 0x15, 0x45, 0xE9,
17065+
17066+ 0x2B, 0x49, 0x51, 0xBD,
17067+ 0x00, 0xE0,
17068+ 0x1F, 0x73,
17069+
17070+ 0x38, 0x38, 0x40, 0xAF,
17071+ 0x30, 0x30, 0x40, 0xAF,
17072+
17073+ 0x24, 0x1F, 0x24, 0xDF,
17074+ 0x1D, 0x32, 0x20, 0xE9,
17075+
17076+ 0x2C, 0x1F, 0x2C, 0xDF,
17077+ 0x1A, 0x33, 0x20, 0xE9,
17078+
17079+ 0xB0, 0x10,
17080+ 0x08, 0xE3,
17081+ 0x40, 0x10,
17082+ 0xB8, 0x10,
17083+
17084+ 0x26, 0xF0, 0x30, 0xCD,
17085+ 0x2F, 0xF0, 0x38, 0xCD,
17086+
17087+ 0x2B, 0x80, 0x20, 0xE9,
17088+ 0x2A, 0x80, 0x20, 0xE9,
17089+
17090+ 0xA6, 0x20,
17091+ 0x88, 0xE2,
17092+ 0x00, 0xE0,
17093+ 0xAF, 0x20,
17094+
17095+ 0x28, 0x2A, 0x26, 0xAF,
17096+ 0x20, 0x2A, 0xC0, 0xAF,
17097+
17098+ 0x34, 0x1F, 0x34, 0xDF,
17099+ 0x46, 0x24, 0x46, 0xDF,
17100+
17101+ 0x28, 0x30, 0x80, 0xBF,
17102+ 0x20, 0x38, 0x80, 0xBF,
17103+
17104+ 0x47, 0x24, 0x47, 0xDF,
17105+ 0x4E, 0x2C, 0x4E, 0xDF,
17106+
17107+ 0x4F, 0x2C, 0x4F, 0xDF,
17108+ 0x56, 0x34, 0x56, 0xDF,
17109+
17110+ 0x28, 0x15, 0x28, 0xDF,
17111+ 0x20, 0x1D, 0x20, 0xDF,
17112+
17113+ 0x57, 0x34, 0x57, 0xDF,
17114+ 0x00, 0xE0,
17115+ 0x1D, 0x05,
17116+
17117+ 0x04, 0x80, 0x10, 0xEA,
17118+ 0x89, 0xE2,
17119+ 0x2B, 0x30,
17120+
17121+ 0x3F, 0xC1, 0x1D, 0xBD,
17122+ 0x00, 0x80, 0x00, 0xE8,
17123+
17124+ 0x00, 0x80, 0x00, 0xE8,
17125+ 0x00, 0x80, 0x00, 0xE8,
17126+
17127+ 0xA0, 0x68,
17128+ 0xBF, 0x25,
17129+ 0x00, 0x80, 0x00, 0xE8,
17130+
17131+ 0x20, 0xC0, 0x20, 0xAF,
17132+ 0x28, 0x05,
17133+ 0x97, 0x74,
17134+
17135+ 0x00, 0xE0,
17136+ 0x2A, 0x10,
17137+ 0x16, 0xC0, 0x20, 0xE9,
17138+
17139+ 0x04, 0x80, 0x10, 0xEA,
17140+ 0x8C, 0xE2,
17141+ 0x95, 0x05,
17142+
17143+ 0x28, 0xC1, 0x28, 0xAD,
17144+ 0x1F, 0xC1, 0x15, 0xBD,
17145+
17146+ 0x00, 0x80, 0x00, 0xE8,
17147+ 0x00, 0x80, 0x00, 0xE8,
17148+
17149+ 0xA8, 0x67,
17150+ 0x9F, 0x6B,
17151+ 0x00, 0x80, 0x00, 0xE8,
17152+
17153+ 0x28, 0xC0, 0x28, 0xAD,
17154+ 0x1D, 0x25,
17155+ 0x20, 0x05,
17156+
17157+ 0x28, 0x32, 0x80, 0xAD,
17158+ 0x40, 0x2A, 0x40, 0xBD,
17159+
17160+ 0x1C, 0x80, 0x20, 0xE9,
17161+ 0x20, 0x33, 0x20, 0xAD,
17162+
17163+ 0x20, 0x73,
17164+ 0x00, 0xE0,
17165+ 0xB6, 0x49, 0x51, 0xBB,
17166+
17167+ 0x26, 0x2F, 0xB0, 0xE8,
17168+ 0x19, 0x20, 0x20, 0xE9,
17169+
17170+ 0x35, 0x20, 0x35, 0xDF,
17171+ 0x3D, 0x20, 0x3D, 0xDF,
17172+
17173+ 0x15, 0x20, 0x15, 0xDF,
17174+ 0x1D, 0x20, 0x1D, 0xDF,
17175+
17176+ 0x26, 0xD0, 0x26, 0xCD,
17177+ 0x29, 0x49, 0x2A, 0xB8,
17178+
17179+ 0x26, 0x40, 0x80, 0xBD,
17180+ 0x3B, 0x48, 0x50, 0xBD,
17181+
17182+ 0x3E, 0x54, 0x57, 0x9F,
17183+ 0x00, 0xE0,
17184+ 0x82, 0xE1,
17185+
17186+ 0x1E, 0xAF, 0x59, 0x9F,
17187+ 0x00, 0x80, 0x00, 0xE8,
17188+
17189+ 0x26, 0x30,
17190+ 0x29, 0x30,
17191+ 0x48, 0x3C, 0x48, 0xAD,
17192+
17193+ 0x2B, 0x72,
17194+ 0xC2, 0xE1,
17195+ 0x2C, 0xC0, 0x44, 0xC2,
17196+
17197+ 0x05, 0x24, 0x34, 0xBF,
17198+ 0x0D, 0x24, 0x2C, 0xBF,
17199+
17200+ 0x2D, 0x46, 0x4E, 0xBF,
17201+ 0x25, 0x46, 0x56, 0xBF,
17202+
17203+ 0x20, 0x1D, 0x6F, 0x8F,
17204+ 0x32, 0x3E, 0x5F, 0xE9,
17205+
17206+ 0x3E, 0x50, 0x56, 0x9F,
17207+ 0x00, 0xE0,
17208+ 0x3B, 0x30,
17209+
17210+ 0x1E, 0x8F, 0x51, 0x9F,
17211+ 0x33, 0x1E, 0x5F, 0xE9,
17212+
17213+ 0x05, 0x44, 0x54, 0xB2,
17214+ 0x0D, 0x44, 0x4C, 0xB2,
17215+
17216+ 0x19, 0xC0, 0xB0, 0xE8,
17217+ 0x34, 0xC0, 0x44, 0xC4,
17218+
17219+ 0x33, 0x73,
17220+ 0x00, 0xE0,
17221+ 0x3E, 0x62, 0x57, 0x9F,
17222+
17223+ 0x1E, 0xAF, 0x59, 0x9F,
17224+ 0x00, 0xE0,
17225+ 0x0D, 0x20,
17226+
17227+ 0x84, 0x3E, 0x58, 0xE9,
17228+ 0x28, 0x1D, 0x6F, 0x8F,
17229+
17230+ 0x05, 0x20,
17231+ 0x00, 0xE0,
17232+ 0x85, 0x1E, 0x58, 0xE9,
17233+
17234+ 0x9B, 0x3B, 0x33, 0xDF,
17235+ 0x20, 0x20, 0x42, 0xAF,
17236+
17237+ 0x30, 0x42, 0x56, 0x9F,
17238+ 0x80, 0x3E, 0x57, 0xE9,
17239+
17240+ 0x3F, 0x8F, 0x51, 0x9F,
17241+ 0x30, 0x80, 0x5F, 0xE9,
17242+
17243+ 0x28, 0x28, 0x24, 0xAF,
17244+ 0x81, 0x1E, 0x57, 0xE9,
17245+
17246+ 0x05, 0x47, 0x57, 0xBF,
17247+ 0x0D, 0x47, 0x4F, 0xBF,
17248+
17249+ 0x88, 0x80, 0x58, 0xE9,
17250+ 0x1B, 0x29, 0x1B, 0xDF,
17251+
17252+ 0x30, 0x1D, 0x6F, 0x8F,
17253+ 0x3A, 0x30, 0x4F, 0xE9,
17254+
17255+ 0x1C, 0x30, 0x26, 0xDF,
17256+ 0x09, 0xE3,
17257+ 0x3B, 0x05,
17258+
17259+ 0x3E, 0x50, 0x56, 0x9F,
17260+ 0x3B, 0x3F, 0x4F, 0xE9,
17261+
17262+ 0x1E, 0x8F, 0x51, 0x9F,
17263+ 0x00, 0xE0,
17264+ 0xAC, 0x20,
17265+
17266+ 0x2D, 0x44, 0x4C, 0xB4,
17267+ 0x2C, 0x1C, 0xC0, 0xAF,
17268+
17269+ 0x25, 0x44, 0x54, 0xB4,
17270+ 0x00, 0xE0,
17271+ 0xC8, 0x30,
17272+
17273+ 0x30, 0x46, 0x30, 0xAF,
17274+ 0x1B, 0x1B, 0x48, 0xAF,
17275+
17276+ 0x00, 0xE0,
17277+ 0x25, 0x20,
17278+ 0x38, 0x2C, 0x4F, 0xE9,
17279+
17280+ 0x86, 0x80, 0x57, 0xE9,
17281+ 0x38, 0x1D, 0x6F, 0x8F,
17282+
17283+ 0x28, 0x74,
17284+ 0x00, 0xE0,
17285+ 0x0D, 0x44, 0x4C, 0xB0,
17286+
17287+ 0x05, 0x44, 0x54, 0xB0,
17288+ 0x2D, 0x20,
17289+ 0x9B, 0x10,
17290+
17291+ 0x82, 0x3E, 0x57, 0xE9,
17292+ 0x32, 0xF0, 0x1B, 0xCD,
17293+
17294+ 0x1E, 0xBD, 0x59, 0x9F,
17295+ 0x83, 0x1E, 0x57, 0xE9,
17296+
17297+ 0x38, 0x47, 0x38, 0xAF,
17298+ 0x34, 0x20,
17299+ 0x2A, 0x30,
17300+
17301+ 0x00, 0xE0,
17302+ 0x0D, 0x20,
17303+ 0x32, 0x20,
17304+ 0x05, 0x20,
17305+
17306+ 0x87, 0x80, 0x57, 0xE9,
17307+ 0x1F, 0x54, 0x57, 0x9F,
17308+
17309+ 0x17, 0x42, 0x56, 0x9F,
17310+ 0x00, 0xE0,
17311+ 0x3B, 0x6A,
17312+
17313+ 0x3F, 0x8F, 0x51, 0x9F,
17314+ 0x37, 0x1E, 0x4F, 0xE9,
17315+
17316+ 0x37, 0x32, 0x2A, 0xAF,
17317+ 0x00, 0xE0,
17318+ 0x32, 0x00,
17319+
17320+ 0x00, 0x80, 0x00, 0xE8,
17321+ 0x27, 0xC0, 0x44, 0xC0,
17322+
17323+ 0x36, 0x1F, 0x4F, 0xE9,
17324+ 0x1F, 0x1F, 0x26, 0xDF,
17325+
17326+ 0x37, 0x1B, 0x37, 0xBF,
17327+ 0x17, 0x26, 0x17, 0xDF,
17328+
17329+ 0x3E, 0x17, 0x4F, 0xE9,
17330+ 0x3F, 0x3F, 0x4F, 0xE9,
17331+
17332+ 0x34, 0x1F, 0x34, 0xAF,
17333+ 0x2B, 0x05,
17334+ 0xA7, 0x20,
17335+
17336+ 0x33, 0x2B, 0x37, 0xDF,
17337+ 0x27, 0x17, 0xC0, 0xAF,
17338+
17339+ 0x34, 0x80, 0x4F, 0xE9,
17340+ 0x00, 0x80, 0x00, 0xE8,
17341+
17342+ 0x0D, 0x21, 0x1A, 0xB6,
17343+ 0x05, 0x21, 0x31, 0xB6,
17344+
17345+ 0x2D, 0x44, 0x4C, 0xB6,
17346+ 0x25, 0x44, 0x54, 0xB6,
17347+
17348+ 0x03, 0x80, 0x2A, 0xEA,
17349+ 0x17, 0xC1, 0x2B, 0xBD,
17350+
17351+ 0x0D, 0x20,
17352+ 0x05, 0x20,
17353+ 0x2F, 0xC0, 0x21, 0xC6,
17354+
17355+ 0xB3, 0x68,
17356+ 0x97, 0x25,
17357+ 0x00, 0x80, 0x00, 0xE8,
17358+
17359+ 0x33, 0xC0, 0x33, 0xAF,
17360+ 0x3C, 0x27, 0x4F, 0xE9,
17361+
17362+ 0x00, 0xE0,
17363+ 0x25, 0x20,
17364+ 0x07, 0xC0, 0x44, 0xC6,
17365+
17366+ 0x17, 0x50, 0x56, 0x9F,
17367+ 0x00, 0xE0,
17368+ 0x2D, 0x20,
17369+
17370+ 0x37, 0x0F, 0x5C, 0x9F,
17371+ 0x00, 0xE0,
17372+ 0x2F, 0x20,
17373+
17374+ 0x1F, 0x62, 0x57, 0x9F,
17375+ 0x00, 0xE0,
17376+ 0x07, 0x20,
17377+
17378+ 0x3F, 0x3D, 0x5D, 0x9F,
17379+ 0x00, 0x80, 0x00, 0xE8,
17380+
17381+ 0x00, 0x80, 0x00, 0xE8,
17382+ 0x28, 0x19, 0x60, 0xEC,
17383+
17384+ 0xB3, 0x05,
17385+ 0x00, 0xE0,
17386+ 0x17, 0x26, 0x17, 0xDF,
17387+
17388+ 0x23, 0x3B, 0x33, 0xAD,
17389+ 0x35, 0x17, 0x4F, 0xE9,
17390+
17391+ 0x1F, 0x26, 0x1F, 0xDF,
17392+ 0x9D, 0x1F, 0x4F, 0xE9,
17393+
17394+ 0x9E, 0x3F, 0x4F, 0xE9,
17395+ 0x39, 0x37, 0x4F, 0xE9,
17396+
17397+ 0x2F, 0x2F, 0x17, 0xAF,
17398+ 0x00, 0x80, 0x00, 0xE8,
17399+
17400+ 0x07, 0x07, 0x1F, 0xAF,
17401+ 0x00, 0x80, 0x00, 0xE8,
17402+
17403+ 0x31, 0x80, 0x4F, 0xE9,
17404+ 0x00, 0x80, 0x00, 0xE8,
17405+
17406+ 0x9C, 0x80, 0x4F, 0xE9,
17407+ 0x00, 0x80, 0x00, 0xE8,
17408+
17409+ 0x00, 0x80, 0x00, 0xE8,
17410+ 0x57, 0x39, 0x20, 0xE9,
17411+
17412+ 0x16, 0x28, 0x20, 0xE9,
17413+ 0x1D, 0x3B, 0x20, 0xE9,
17414+
17415+ 0x1E, 0x2B, 0x20, 0xE9,
17416+ 0x2B, 0x32, 0x20, 0xE9,
17417+
17418+ 0x1C, 0x23, 0x20, 0xE9,
17419+ 0x57, 0x36, 0x20, 0xE9,
17420+
17421+ 0x00, 0x80, 0xA0, 0xE9,
17422+ 0x40, 0x40, 0xD8, 0xEC,
17423+
17424+ 0xFF, 0x80, 0xC0, 0xE9,
17425+ 0x90, 0xE2,
17426+ 0x00, 0xE0,
17427+
17428+ 0x74, 0xFF, 0x20, 0xEA,
17429+ 0x19, 0xC8, 0xC1, 0xCD,
17430+
17431+ 0x1F, 0xD7, 0x18, 0xBD,
17432+ 0x3F, 0xD7, 0x22, 0xBD,
17433+
17434+ 0x9F, 0x41, 0x49, 0xBD,
17435+ 0x00, 0x80, 0x00, 0xE8,
17436+
17437+ 0x25, 0x41, 0x49, 0xBD,
17438+ 0x2D, 0x41, 0x51, 0xBD,
17439+
17440+ 0x0D, 0x80, 0x07, 0xEA,
17441+ 0x00, 0x80, 0x00, 0xE8,
17442+
17443+ 0x35, 0x40, 0x48, 0xBD,
17444+ 0x3D, 0x40, 0x50, 0xBD,
17445+
17446+ 0x00, 0x80, 0x00, 0xE8,
17447+ 0x25, 0x30,
17448+ 0x2D, 0x30,
17449+
17450+ 0x35, 0x30,
17451+ 0xB5, 0x30,
17452+ 0xBD, 0x30,
17453+ 0x3D, 0x30,
17454+
17455+ 0x9C, 0xA7, 0x5B, 0x9F,
17456+ 0x00, 0x80, 0x00, 0xE8,
17457+
17458+ 0x00, 0x80, 0x00, 0xE8,
17459+ 0x00, 0x80, 0x00, 0xE8,
17460+
17461+ 0x00, 0x80, 0x00, 0xE8,
17462+ 0x00, 0x80, 0x00, 0xE8,
17463+
17464+ 0x00, 0x80, 0x00, 0xE8,
17465+ 0x00, 0x80, 0x00, 0xE8,
17466+
17467+ 0x00, 0x80, 0x00, 0xE8,
17468+ 0x00, 0x80, 0x00, 0xE8,
17469+
17470+ 0x73, 0xFF, 0x0A, 0xEA,
17471+ 0x00, 0x80, 0x00, 0xE8,
17472+
17473+ 0xC9, 0x41, 0xC8, 0xEC,
17474+ 0x42, 0xE1,
17475+ 0x00, 0xE0,
17476+
17477+ 0x71, 0xFF, 0x20, 0xEA,
17478+ 0x00, 0x80, 0x00, 0xE8,
17479+
17480+ 0x00, 0x80, 0x00, 0xE8,
17481+ 0x00, 0x80, 0x00, 0xE8,
17482+
17483+ 0xC8, 0x40, 0xC0, 0xEC,
17484+ 0x00, 0x80, 0x00, 0xE8,
17485+
17486+ 0x6E, 0xFF, 0x20, 0xEA,
17487+ 0x00, 0x80, 0x00, 0xE8,
17488+
17489+ 0x00, 0x80, 0x00, 0xE8,
17490+ 0x00, 0x80, 0x00, 0xE8,
17491+
17492+};
17493+
17494+static unsigned char warp_g200_tgzf[] = {
17495+
17496+ 0x00, 0x80, 0x00, 0xE8,
17497+ 0x00, 0x80, 0x00, 0xE8,
17498+
17499+ 0x00, 0x80, 0x00, 0xE8,
17500+ 0x00, 0x80, 0x00, 0xE8,
17501+
17502+ 0x00, 0x80, 0x00, 0xE8,
17503+ 0x00, 0x80, 0x00, 0xE8,
17504+
17505+ 0x00, 0x80, 0x00, 0xE8,
17506+ 0x00, 0x80, 0x00, 0xE8,
17507+
17508+ 0x00, 0x80, 0x00, 0xE8,
17509+ 0x00, 0x80, 0x00, 0xE8,
17510+
17511+ 0x00, 0x80, 0x00, 0xE8,
17512+ 0x00, 0x80, 0x00, 0xE8,
17513+
17514+ 0x00, 0x80, 0x00, 0xE8,
17515+ 0x00, 0x80, 0x00, 0xE8,
17516+
17517+ 0x00, 0x80, 0x00, 0xE8,
17518+ 0x00, 0x80, 0x00, 0xE8,
17519+
17520+ 0x00, 0x80, 0x00, 0xE8,
17521+ 0x00, 0x80, 0x00, 0xE8,
17522+
17523+ 0x00, 0x80, 0x00, 0xE8,
17524+ 0x00, 0x80, 0x00, 0xE8,
17525+
17526+ 0x00, 0x98, 0xA0, 0xE9,
17527+ 0x40, 0x40, 0xD8, 0xEC,
17528+
17529+ 0xFF, 0x80, 0xC0, 0xE9,
17530+ 0x00, 0x80, 0x00, 0xE8,
17531+
17532+ 0x1F, 0xD7, 0x18, 0xBD,
17533+ 0x3F, 0xD7, 0x22, 0xBD,
17534+
17535+ 0x81, 0x04,
17536+ 0x89, 0x04,
17537+ 0x01, 0x04,
17538+ 0x09, 0x04,
17539+
17540+ 0xC9, 0x41, 0xC0, 0xEC,
17541+ 0x11, 0x04,
17542+ 0x00, 0xE0,
17543+
17544+ 0x41, 0xCC, 0x41, 0xCD,
17545+ 0x49, 0xCC, 0x49, 0xCD,
17546+
17547+ 0xD1, 0x41, 0xC0, 0xEC,
17548+ 0x51, 0xCC, 0x51, 0xCD,
17549+
17550+ 0x80, 0x04,
17551+ 0x10, 0x04,
17552+ 0x08, 0x04,
17553+ 0x00, 0xE0,
17554+
17555+ 0x00, 0xCC, 0xC0, 0xCD,
17556+ 0xD1, 0x49, 0xC0, 0xEC,
17557+
17558+ 0x8A, 0x1F, 0x20, 0xE9,
17559+ 0x8B, 0x3F, 0x20, 0xE9,
17560+
17561+ 0x41, 0x3C, 0x41, 0xAD,
17562+ 0x49, 0x3C, 0x49, 0xAD,
17563+
17564+ 0x10, 0xCC, 0x10, 0xCD,
17565+ 0x08, 0xCC, 0x08, 0xCD,
17566+
17567+ 0xB9, 0x41, 0x49, 0xBB,
17568+ 0x1F, 0xF0, 0x41, 0xCD,
17569+
17570+ 0x51, 0x3C, 0x51, 0xAD,
17571+ 0x00, 0x98, 0x80, 0xE9,
17572+
17573+ 0x7F, 0x80, 0x07, 0xEA,
17574+ 0x24, 0x1F, 0x20, 0xE9,
17575+
17576+ 0x21, 0x45, 0x80, 0xE8,
17577+ 0x1A, 0x4D, 0x80, 0xE8,
17578+
17579+ 0x31, 0x55, 0x80, 0xE8,
17580+ 0x00, 0x80, 0x00, 0xE8,
17581+
17582+ 0x15, 0x41, 0x49, 0xBD,
17583+ 0x1D, 0x41, 0x51, 0xBD,
17584+
17585+ 0x2E, 0x41, 0x2A, 0xB8,
17586+ 0x34, 0x53, 0xA0, 0xE8,
17587+
17588+ 0x15, 0x30,
17589+ 0x1D, 0x30,
17590+ 0x58, 0xE3,
17591+ 0x00, 0xE0,
17592+
17593+ 0xB5, 0x40, 0x48, 0xBD,
17594+ 0x3D, 0x40, 0x50, 0xBD,
17595+
17596+ 0x24, 0x43, 0xA0, 0xE8,
17597+ 0x2C, 0x4B, 0xA0, 0xE8,
17598+
17599+ 0x15, 0x72,
17600+ 0x09, 0xE3,
17601+ 0x00, 0xE0,
17602+ 0x1D, 0x72,
17603+
17604+ 0x35, 0x30,
17605+ 0xB5, 0x30,
17606+ 0xBD, 0x30,
17607+ 0x3D, 0x30,
17608+
17609+ 0x9C, 0x97, 0x57, 0x9F,
17610+ 0x00, 0x80, 0x00, 0xE8,
17611+
17612+ 0x6C, 0x64, 0xC8, 0xEC,
17613+ 0x98, 0xE1,
17614+ 0xB5, 0x05,
17615+
17616+ 0xBD, 0x05,
17617+ 0x2E, 0x30,
17618+ 0x32, 0xC0, 0xA0, 0xE8,
17619+
17620+ 0x33, 0xC0, 0xA0, 0xE8,
17621+ 0x74, 0x64, 0xC8, 0xEC,
17622+
17623+ 0x40, 0x3C, 0x40, 0xAD,
17624+ 0x32, 0x6A,
17625+ 0x2A, 0x30,
17626+
17627+ 0x20, 0x73,
17628+ 0x33, 0x6A,
17629+ 0x00, 0xE0,
17630+ 0x28, 0x73,
17631+
17632+ 0x1C, 0x72,
17633+ 0x83, 0xE2,
17634+ 0x6B, 0x80, 0x15, 0xEA,
17635+
17636+ 0xB8, 0x3D, 0x28, 0xDF,
17637+ 0x30, 0x35, 0x20, 0xDF,
17638+
17639+ 0x40, 0x30,
17640+ 0x00, 0xE0,
17641+ 0xCC, 0xE2,
17642+ 0x64, 0x72,
17643+
17644+ 0x25, 0x42, 0x52, 0xBF,
17645+ 0x2D, 0x42, 0x4A, 0xBF,
17646+
17647+ 0x30, 0x2E, 0x30, 0xDF,
17648+ 0x38, 0x2E, 0x38, 0xDF,
17649+
17650+ 0x18, 0x1D, 0x45, 0xE9,
17651+ 0x1E, 0x15, 0x45, 0xE9,
17652+
17653+ 0x2B, 0x49, 0x51, 0xBD,
17654+ 0x00, 0xE0,
17655+ 0x1F, 0x73,
17656+
17657+ 0x38, 0x38, 0x40, 0xAF,
17658+ 0x30, 0x30, 0x40, 0xAF,
17659+
17660+ 0x24, 0x1F, 0x24, 0xDF,
17661+ 0x1D, 0x32, 0x20, 0xE9,
17662+
17663+ 0x2C, 0x1F, 0x2C, 0xDF,
17664+ 0x1A, 0x33, 0x20, 0xE9,
17665+
17666+ 0xB0, 0x10,
17667+ 0x08, 0xE3,
17668+ 0x40, 0x10,
17669+ 0xB8, 0x10,
17670+
17671+ 0x26, 0xF0, 0x30, 0xCD,
17672+ 0x2F, 0xF0, 0x38, 0xCD,
17673+
17674+ 0x2B, 0x80, 0x20, 0xE9,
17675+ 0x2A, 0x80, 0x20, 0xE9,
17676+
17677+ 0xA6, 0x20,
17678+ 0x88, 0xE2,
17679+ 0x00, 0xE0,
17680+ 0xAF, 0x20,
17681+
17682+ 0x28, 0x2A, 0x26, 0xAF,
17683+ 0x20, 0x2A, 0xC0, 0xAF,
17684+
17685+ 0x34, 0x1F, 0x34, 0xDF,
17686+ 0x46, 0x24, 0x46, 0xDF,
17687+
17688+ 0x28, 0x30, 0x80, 0xBF,
17689+ 0x20, 0x38, 0x80, 0xBF,
17690+
17691+ 0x47, 0x24, 0x47, 0xDF,
17692+ 0x4E, 0x2C, 0x4E, 0xDF,
17693+
17694+ 0x4F, 0x2C, 0x4F, 0xDF,
17695+ 0x56, 0x34, 0x56, 0xDF,
17696+
17697+ 0x28, 0x15, 0x28, 0xDF,
17698+ 0x20, 0x1D, 0x20, 0xDF,
17699+
17700+ 0x57, 0x34, 0x57, 0xDF,
17701+ 0x00, 0xE0,
17702+ 0x1D, 0x05,
17703+
17704+ 0x04, 0x80, 0x10, 0xEA,
17705+ 0x89, 0xE2,
17706+ 0x2B, 0x30,
17707+
17708+ 0x3F, 0xC1, 0x1D, 0xBD,
17709+ 0x00, 0x80, 0x00, 0xE8,
17710+
17711+ 0x00, 0x80, 0x00, 0xE8,
17712+ 0x00, 0x80, 0x00, 0xE8,
17713+
17714+ 0xA0, 0x68,
17715+ 0xBF, 0x25,
17716+ 0x00, 0x80, 0x00, 0xE8,
17717+
17718+ 0x20, 0xC0, 0x20, 0xAF,
17719+ 0x28, 0x05,
17720+ 0x97, 0x74,
17721+
17722+ 0x00, 0xE0,
17723+ 0x2A, 0x10,
17724+ 0x16, 0xC0, 0x20, 0xE9,
17725+
17726+ 0x04, 0x80, 0x10, 0xEA,
17727+ 0x8C, 0xE2,
17728+ 0x95, 0x05,
17729+
17730+ 0x28, 0xC1, 0x28, 0xAD,
17731+ 0x1F, 0xC1, 0x15, 0xBD,
17732+
17733+ 0x00, 0x80, 0x00, 0xE8,
17734+ 0x00, 0x80, 0x00, 0xE8,
17735+
17736+ 0xA8, 0x67,
17737+ 0x9F, 0x6B,
17738+ 0x00, 0x80, 0x00, 0xE8,
17739+
17740+ 0x28, 0xC0, 0x28, 0xAD,
17741+ 0x1D, 0x25,
17742+ 0x20, 0x05,
17743+
17744+ 0x28, 0x32, 0x80, 0xAD,
17745+ 0x40, 0x2A, 0x40, 0xBD,
17746+
17747+ 0x1C, 0x80, 0x20, 0xE9,
17748+ 0x20, 0x33, 0x20, 0xAD,
17749+
17750+ 0x20, 0x73,
17751+ 0x00, 0xE0,
17752+ 0xB6, 0x49, 0x51, 0xBB,
17753+
17754+ 0x26, 0x2F, 0xB0, 0xE8,
17755+ 0x19, 0x20, 0x20, 0xE9,
17756+
17757+ 0x35, 0x20, 0x35, 0xDF,
17758+ 0x3D, 0x20, 0x3D, 0xDF,
17759+
17760+ 0x15, 0x20, 0x15, 0xDF,
17761+ 0x1D, 0x20, 0x1D, 0xDF,
17762+
17763+ 0x26, 0xD0, 0x26, 0xCD,
17764+ 0x29, 0x49, 0x2A, 0xB8,
17765+
17766+ 0x26, 0x40, 0x80, 0xBD,
17767+ 0x3B, 0x48, 0x50, 0xBD,
17768+
17769+ 0x3E, 0x54, 0x57, 0x9F,
17770+ 0x00, 0xE0,
17771+ 0x82, 0xE1,
17772+
17773+ 0x1E, 0xAF, 0x59, 0x9F,
17774+ 0x00, 0x80, 0x00, 0xE8,
17775+
17776+ 0x26, 0x30,
17777+ 0x29, 0x30,
17778+ 0x48, 0x3C, 0x48, 0xAD,
17779+
17780+ 0x2B, 0x72,
17781+ 0xC2, 0xE1,
17782+ 0x2C, 0xC0, 0x44, 0xC2,
17783+
17784+ 0x05, 0x24, 0x34, 0xBF,
17785+ 0x0D, 0x24, 0x2C, 0xBF,
17786+
17787+ 0x2D, 0x46, 0x4E, 0xBF,
17788+ 0x25, 0x46, 0x56, 0xBF,
17789+
17790+ 0x20, 0x1D, 0x6F, 0x8F,
17791+ 0x32, 0x3E, 0x5F, 0xE9,
17792+
17793+ 0x3E, 0x50, 0x56, 0x9F,
17794+ 0x00, 0xE0,
17795+ 0x3B, 0x30,
17796+
17797+ 0x1E, 0x8F, 0x51, 0x9F,
17798+ 0x33, 0x1E, 0x5F, 0xE9,
17799+
17800+ 0x05, 0x44, 0x54, 0xB2,
17801+ 0x0D, 0x44, 0x4C, 0xB2,
17802+
17803+ 0x19, 0xC0, 0xB0, 0xE8,
17804+ 0x34, 0xC0, 0x44, 0xC4,
17805+
17806+ 0x33, 0x73,
17807+ 0x00, 0xE0,
17808+ 0x3E, 0x62, 0x57, 0x9F,
17809+
17810+ 0x1E, 0xAF, 0x59, 0x9F,
17811+ 0x00, 0xE0,
17812+ 0x0D, 0x20,
17813+
17814+ 0x84, 0x3E, 0x58, 0xE9,
17815+ 0x28, 0x1D, 0x6F, 0x8F,
17816+
17817+ 0x05, 0x20,
17818+ 0x00, 0xE0,
17819+ 0x85, 0x1E, 0x58, 0xE9,
17820+
17821+ 0x9B, 0x3B, 0x33, 0xDF,
17822+ 0x20, 0x20, 0x42, 0xAF,
17823+
17824+ 0x30, 0x42, 0x56, 0x9F,
17825+ 0x80, 0x3E, 0x57, 0xE9,
17826+
17827+ 0x3F, 0x8F, 0x51, 0x9F,
17828+ 0x30, 0x80, 0x5F, 0xE9,
17829+
17830+ 0x28, 0x28, 0x24, 0xAF,
17831+ 0x81, 0x1E, 0x57, 0xE9,
17832+
17833+ 0x05, 0x47, 0x57, 0xBF,
17834+ 0x0D, 0x47, 0x4F, 0xBF,
17835+
17836+ 0x88, 0x80, 0x58, 0xE9,
17837+ 0x1B, 0x29, 0x1B, 0xDF,
17838+
17839+ 0x30, 0x1D, 0x6F, 0x8F,
17840+ 0x3A, 0x30, 0x4F, 0xE9,
17841+
17842+ 0x1C, 0x30, 0x26, 0xDF,
17843+ 0x09, 0xE3,
17844+ 0x3B, 0x05,
17845+
17846+ 0x3E, 0x50, 0x56, 0x9F,
17847+ 0x3B, 0x3F, 0x4F, 0xE9,
17848+
17849+ 0x1E, 0x8F, 0x51, 0x9F,
17850+ 0x00, 0xE0,
17851+ 0xAC, 0x20,
17852+
17853+ 0x2D, 0x44, 0x4C, 0xB4,
17854+ 0x2C, 0x1C, 0xC0, 0xAF,
17855+
17856+ 0x25, 0x44, 0x54, 0xB4,
17857+ 0x00, 0xE0,
17858+ 0xC8, 0x30,
17859+
17860+ 0x30, 0x46, 0x30, 0xAF,
17861+ 0x1B, 0x1B, 0x48, 0xAF,
17862+
17863+ 0x00, 0xE0,
17864+ 0x25, 0x20,
17865+ 0x38, 0x2C, 0x4F, 0xE9,
17866+
17867+ 0x86, 0x80, 0x57, 0xE9,
17868+ 0x38, 0x1D, 0x6F, 0x8F,
17869+
17870+ 0x28, 0x74,
17871+ 0x00, 0xE0,
17872+ 0x0D, 0x44, 0x4C, 0xB0,
17873+
17874+ 0x05, 0x44, 0x54, 0xB0,
17875+ 0x2D, 0x20,
17876+ 0x9B, 0x10,
17877+
17878+ 0x82, 0x3E, 0x57, 0xE9,
17879+ 0x32, 0xF0, 0x1B, 0xCD,
17880+
17881+ 0x1E, 0xBD, 0x59, 0x9F,
17882+ 0x83, 0x1E, 0x57, 0xE9,
17883+
17884+ 0x38, 0x47, 0x38, 0xAF,
17885+ 0x34, 0x20,
17886+ 0x2A, 0x30,
17887+
17888+ 0x00, 0xE0,
17889+ 0x0D, 0x20,
17890+ 0x32, 0x20,
17891+ 0x05, 0x20,
17892+
17893+ 0x87, 0x80, 0x57, 0xE9,
17894+ 0x1F, 0x54, 0x57, 0x9F,
17895+
17896+ 0x17, 0x42, 0x56, 0x9F,
17897+ 0x00, 0xE0,
17898+ 0x3B, 0x6A,
17899+
17900+ 0x3F, 0x8F, 0x51, 0x9F,
17901+ 0x37, 0x1E, 0x4F, 0xE9,
17902+
17903+ 0x37, 0x32, 0x2A, 0xAF,
17904+ 0x00, 0xE0,
17905+ 0x32, 0x00,
17906+
17907+ 0x00, 0x80, 0x00, 0xE8,
17908+ 0x27, 0xC0, 0x44, 0xC0,
17909+
17910+ 0x36, 0x1F, 0x4F, 0xE9,
17911+ 0x1F, 0x1F, 0x26, 0xDF,
17912+
17913+ 0x37, 0x1B, 0x37, 0xBF,
17914+ 0x17, 0x26, 0x17, 0xDF,
17915+
17916+ 0x3E, 0x17, 0x4F, 0xE9,
17917+ 0x3F, 0x3F, 0x4F, 0xE9,
17918+
17919+ 0x34, 0x1F, 0x34, 0xAF,
17920+ 0x2B, 0x05,
17921+ 0xA7, 0x20,
17922+
17923+ 0x33, 0x2B, 0x37, 0xDF,
17924+ 0x27, 0x17, 0xC0, 0xAF,
17925+
17926+ 0x34, 0x80, 0x4F, 0xE9,
17927+ 0x00, 0x80, 0x00, 0xE8,
17928+
17929+ 0x0D, 0x21, 0x1A, 0xB6,
17930+ 0x05, 0x21, 0x31, 0xB6,
17931+
17932+ 0x03, 0x80, 0x2A, 0xEA,
17933+ 0x17, 0xC1, 0x2B, 0xBD,
17934+
17935+ 0x0D, 0x20,
17936+ 0x05, 0x20,
17937+ 0x2F, 0xC0, 0x21, 0xC6,
17938+
17939+ 0xB3, 0x68,
17940+ 0x97, 0x25,
17941+ 0x00, 0x80, 0x00, 0xE8,
17942+
17943+ 0x33, 0xC0, 0x33, 0xAF,
17944+ 0x3C, 0x27, 0x4F, 0xE9,
17945+
17946+ 0x17, 0x50, 0x56, 0x9F,
17947+ 0x00, 0x80, 0x00, 0xE8,
17948+
17949+ 0x37, 0x0F, 0x5C, 0x9F,
17950+ 0x00, 0xE0,
17951+ 0x2F, 0x20,
17952+
17953+ 0x00, 0x80, 0x00, 0xE8,
17954+ 0x28, 0x19, 0x60, 0xEC,
17955+
17956+ 0xB3, 0x05,
17957+ 0x00, 0xE0,
17958+ 0x00, 0x80, 0x00, 0xE8,
17959+
17960+ 0x23, 0x3B, 0x33, 0xAD,
17961+ 0x00, 0x80, 0x00, 0xE8,
17962+
17963+ 0x17, 0x26, 0x17, 0xDF,
17964+ 0x35, 0x17, 0x4F, 0xE9,
17965+
17966+ 0x00, 0x80, 0x00, 0xE8,
17967+ 0x00, 0x80, 0x00, 0xE8,
17968+
17969+ 0x00, 0x80, 0x00, 0xE8,
17970+ 0x39, 0x37, 0x4F, 0xE9,
17971+
17972+ 0x2F, 0x2F, 0x17, 0xAF,
17973+ 0x00, 0x80, 0x00, 0xE8,
17974+
17975+ 0x00, 0x80, 0x00, 0xE8,
17976+ 0x00, 0x80, 0x00, 0xE8,
17977+
17978+ 0x31, 0x80, 0x4F, 0xE9,
17979+ 0x00, 0x80, 0x00, 0xE8,
17980+
17981+ 0x00, 0x80, 0x00, 0xE8,
17982+ 0x57, 0x39, 0x20, 0xE9,
17983+
17984+ 0x16, 0x28, 0x20, 0xE9,
17985+ 0x1D, 0x3B, 0x20, 0xE9,
17986+
17987+ 0x1E, 0x2B, 0x20, 0xE9,
17988+ 0x2B, 0x32, 0x20, 0xE9,
17989+
17990+ 0x1C, 0x23, 0x20, 0xE9,
17991+ 0x57, 0x36, 0x20, 0xE9,
17992+
17993+ 0x00, 0x80, 0xA0, 0xE9,
17994+ 0x40, 0x40, 0xD8, 0xEC,
17995+
17996+ 0xFF, 0x80, 0xC0, 0xE9,
17997+ 0x90, 0xE2,
17998+ 0x00, 0xE0,
17999+
18000+ 0x78, 0xFF, 0x20, 0xEA,
18001+ 0x19, 0xC8, 0xC1, 0xCD,
18002+
18003+ 0x1F, 0xD7, 0x18, 0xBD,
18004+ 0x3F, 0xD7, 0x22, 0xBD,
18005+
18006+ 0x9F, 0x41, 0x49, 0xBD,
18007+ 0x00, 0x80, 0x00, 0xE8,
18008+
18009+ 0x25, 0x41, 0x49, 0xBD,
18010+ 0x2D, 0x41, 0x51, 0xBD,
18011+
18012+ 0x0D, 0x80, 0x07, 0xEA,
18013+ 0x00, 0x80, 0x00, 0xE8,
18014+
18015+ 0x35, 0x40, 0x48, 0xBD,
18016+ 0x3D, 0x40, 0x50, 0xBD,
18017+
18018+ 0x00, 0x80, 0x00, 0xE8,
18019+ 0x25, 0x30,
18020+ 0x2D, 0x30,
18021+
18022+ 0x35, 0x30,
18023+ 0xB5, 0x30,
18024+ 0xBD, 0x30,
18025+ 0x3D, 0x30,
18026+
18027+ 0x9C, 0xA7, 0x5B, 0x9F,
18028+ 0x00, 0x80, 0x00, 0xE8,
18029+
18030+ 0x00, 0x80, 0x00, 0xE8,
18031+ 0x00, 0x80, 0x00, 0xE8,
18032+
18033+ 0x00, 0x80, 0x00, 0xE8,
18034+ 0x00, 0x80, 0x00, 0xE8,
18035+
18036+ 0x00, 0x80, 0x00, 0xE8,
18037+ 0x00, 0x80, 0x00, 0xE8,
18038+
18039+ 0x00, 0x80, 0x00, 0xE8,
18040+ 0x00, 0x80, 0x00, 0xE8,
18041+
18042+ 0x77, 0xFF, 0x0A, 0xEA,
18043+ 0x00, 0x80, 0x00, 0xE8,
18044+
18045+ 0xC9, 0x41, 0xC8, 0xEC,
18046+ 0x42, 0xE1,
18047+ 0x00, 0xE0,
18048+
18049+ 0x75, 0xFF, 0x20, 0xEA,
18050+ 0x00, 0x80, 0x00, 0xE8,
18051+
18052+ 0x00, 0x80, 0x00, 0xE8,
18053+ 0x00, 0x80, 0x00, 0xE8,
18054+
18055+ 0xC8, 0x40, 0xC0, 0xEC,
18056+ 0x00, 0x80, 0x00, 0xE8,
18057+
18058+ 0x72, 0xFF, 0x20, 0xEA,
18059+ 0x00, 0x80, 0x00, 0xE8,
18060+
18061+ 0x00, 0x80, 0x00, 0xE8,
18062+ 0x00, 0x80, 0x00, 0xE8,
18063+
18064+};
18065+
18066+static unsigned char warp_g200_tgzs[] = {
18067+
18068+ 0x00, 0x80, 0x00, 0xE8,
18069+ 0x00, 0x80, 0x00, 0xE8,
18070+
18071+ 0x00, 0x80, 0x00, 0xE8,
18072+ 0x00, 0x80, 0x00, 0xE8,
18073+
18074+ 0x00, 0x80, 0x00, 0xE8,
18075+ 0x00, 0x80, 0x00, 0xE8,
18076+
18077+ 0x00, 0x80, 0x00, 0xE8,
18078+ 0x00, 0x80, 0x00, 0xE8,
18079+
18080+ 0x00, 0x80, 0x00, 0xE8,
18081+ 0x00, 0x80, 0x00, 0xE8,
18082+
18083+ 0x00, 0x80, 0x00, 0xE8,
18084+ 0x00, 0x80, 0x00, 0xE8,
18085+
18086+ 0x00, 0x80, 0x00, 0xE8,
18087+ 0x00, 0x80, 0x00, 0xE8,
18088+
18089+ 0x00, 0x80, 0x00, 0xE8,
18090+ 0x00, 0x80, 0x00, 0xE8,
18091+
18092+ 0x00, 0x80, 0x00, 0xE8,
18093+ 0x00, 0x80, 0x00, 0xE8,
18094+
18095+ 0x00, 0x80, 0x00, 0xE8,
18096+ 0x00, 0x80, 0x00, 0xE8,
18097+
18098+ 0x00, 0x80, 0x00, 0xE8,
18099+ 0x00, 0x80, 0x00, 0xE8,
18100+
18101+ 0x00, 0x80, 0x00, 0xE8,
18102+ 0x00, 0x80, 0x00, 0xE8,
18103+
18104+ 0x00, 0x80, 0x00, 0xE8,
18105+ 0x00, 0x80, 0x00, 0xE8,
18106+
18107+ 0x00, 0x98, 0xA0, 0xE9,
18108+ 0x40, 0x40, 0xD8, 0xEC,
18109+
18110+ 0xFF, 0x80, 0xC0, 0xE9,
18111+ 0x00, 0x80, 0x00, 0xE8,
18112+
18113+ 0x1F, 0xD7, 0x18, 0xBD,
18114+ 0x3F, 0xD7, 0x22, 0xBD,
18115+
18116+ 0x81, 0x04,
18117+ 0x89, 0x04,
18118+ 0x01, 0x04,
18119+ 0x09, 0x04,
18120+
18121+ 0xC9, 0x41, 0xC0, 0xEC,
18122+ 0x11, 0x04,
18123+ 0x00, 0xE0,
18124+
18125+ 0x41, 0xCC, 0x41, 0xCD,
18126+ 0x49, 0xCC, 0x49, 0xCD,
18127+
18128+ 0xD1, 0x41, 0xC0, 0xEC,
18129+ 0x51, 0xCC, 0x51, 0xCD,
18130+
18131+ 0x80, 0x04,
18132+ 0x10, 0x04,
18133+ 0x08, 0x04,
18134+ 0x00, 0xE0,
18135+
18136+ 0x00, 0xCC, 0xC0, 0xCD,
18137+ 0xD1, 0x49, 0xC0, 0xEC,
18138+
18139+ 0x8A, 0x1F, 0x20, 0xE9,
18140+ 0x8B, 0x3F, 0x20, 0xE9,
18141+
18142+ 0x41, 0x3C, 0x41, 0xAD,
18143+ 0x49, 0x3C, 0x49, 0xAD,
18144+
18145+ 0x10, 0xCC, 0x10, 0xCD,
18146+ 0x08, 0xCC, 0x08, 0xCD,
18147+
18148+ 0xB9, 0x41, 0x49, 0xBB,
18149+ 0x1F, 0xF0, 0x41, 0xCD,
18150+
18151+ 0x51, 0x3C, 0x51, 0xAD,
18152+ 0x00, 0x98, 0x80, 0xE9,
18153+
18154+ 0x8B, 0x80, 0x07, 0xEA,
18155+ 0x24, 0x1F, 0x20, 0xE9,
18156+
18157+ 0x21, 0x45, 0x80, 0xE8,
18158+ 0x1A, 0x4D, 0x80, 0xE8,
18159+
18160+ 0x31, 0x55, 0x80, 0xE8,
18161+ 0x00, 0x80, 0x00, 0xE8,
18162+
18163+ 0x15, 0x41, 0x49, 0xBD,
18164+ 0x1D, 0x41, 0x51, 0xBD,
18165+
18166+ 0x2E, 0x41, 0x2A, 0xB8,
18167+ 0x34, 0x53, 0xA0, 0xE8,
18168+
18169+ 0x15, 0x30,
18170+ 0x1D, 0x30,
18171+ 0x58, 0xE3,
18172+ 0x00, 0xE0,
18173+
18174+ 0xB5, 0x40, 0x48, 0xBD,
18175+ 0x3D, 0x40, 0x50, 0xBD,
18176+
18177+ 0x24, 0x43, 0xA0, 0xE8,
18178+ 0x2C, 0x4B, 0xA0, 0xE8,
18179+
18180+ 0x15, 0x72,
18181+ 0x09, 0xE3,
18182+ 0x00, 0xE0,
18183+ 0x1D, 0x72,
18184+
18185+ 0x35, 0x30,
18186+ 0xB5, 0x30,
18187+ 0xBD, 0x30,
18188+ 0x3D, 0x30,
18189+
18190+ 0x9C, 0x97, 0x57, 0x9F,
18191+ 0x00, 0x80, 0x00, 0xE8,
18192+
18193+ 0x6C, 0x64, 0xC8, 0xEC,
18194+ 0x98, 0xE1,
18195+ 0xB5, 0x05,
18196+
18197+ 0xBD, 0x05,
18198+ 0x2E, 0x30,
18199+ 0x32, 0xC0, 0xA0, 0xE8,
18200+
18201+ 0x33, 0xC0, 0xA0, 0xE8,
18202+ 0x74, 0x64, 0xC8, 0xEC,
18203+
18204+ 0x40, 0x3C, 0x40, 0xAD,
18205+ 0x32, 0x6A,
18206+ 0x2A, 0x30,
18207+
18208+ 0x20, 0x73,
18209+ 0x33, 0x6A,
18210+ 0x00, 0xE0,
18211+ 0x28, 0x73,
18212+
18213+ 0x1C, 0x72,
18214+ 0x83, 0xE2,
18215+ 0x77, 0x80, 0x15, 0xEA,
18216+
18217+ 0xB8, 0x3D, 0x28, 0xDF,
18218+ 0x30, 0x35, 0x20, 0xDF,
18219+
18220+ 0x40, 0x30,
18221+ 0x00, 0xE0,
18222+ 0xCC, 0xE2,
18223+ 0x64, 0x72,
18224+
18225+ 0x25, 0x42, 0x52, 0xBF,
18226+ 0x2D, 0x42, 0x4A, 0xBF,
18227+
18228+ 0x30, 0x2E, 0x30, 0xDF,
18229+ 0x38, 0x2E, 0x38, 0xDF,
18230+
18231+ 0x18, 0x1D, 0x45, 0xE9,
18232+ 0x1E, 0x15, 0x45, 0xE9,
18233+
18234+ 0x2B, 0x49, 0x51, 0xBD,
18235+ 0x00, 0xE0,
18236+ 0x1F, 0x73,
18237+
18238+ 0x38, 0x38, 0x40, 0xAF,
18239+ 0x30, 0x30, 0x40, 0xAF,
18240+
18241+ 0x24, 0x1F, 0x24, 0xDF,
18242+ 0x1D, 0x32, 0x20, 0xE9,
18243+
18244+ 0x2C, 0x1F, 0x2C, 0xDF,
18245+ 0x1A, 0x33, 0x20, 0xE9,
18246+
18247+ 0xB0, 0x10,
18248+ 0x08, 0xE3,
18249+ 0x40, 0x10,
18250+ 0xB8, 0x10,
18251+
18252+ 0x26, 0xF0, 0x30, 0xCD,
18253+ 0x2F, 0xF0, 0x38, 0xCD,
18254+
18255+ 0x2B, 0x80, 0x20, 0xE9,
18256+ 0x2A, 0x80, 0x20, 0xE9,
18257+
18258+ 0xA6, 0x20,
18259+ 0x88, 0xE2,
18260+ 0x00, 0xE0,
18261+ 0xAF, 0x20,
18262+
18263+ 0x28, 0x2A, 0x26, 0xAF,
18264+ 0x20, 0x2A, 0xC0, 0xAF,
18265+
18266+ 0x34, 0x1F, 0x34, 0xDF,
18267+ 0x46, 0x24, 0x46, 0xDF,
18268+
18269+ 0x28, 0x30, 0x80, 0xBF,
18270+ 0x20, 0x38, 0x80, 0xBF,
18271+
18272+ 0x47, 0x24, 0x47, 0xDF,
18273+ 0x4E, 0x2C, 0x4E, 0xDF,
18274+
18275+ 0x4F, 0x2C, 0x4F, 0xDF,
18276+ 0x56, 0x34, 0x56, 0xDF,
18277+
18278+ 0x28, 0x15, 0x28, 0xDF,
18279+ 0x20, 0x1D, 0x20, 0xDF,
18280+
18281+ 0x57, 0x34, 0x57, 0xDF,
18282+ 0x00, 0xE0,
18283+ 0x1D, 0x05,
18284+
18285+ 0x04, 0x80, 0x10, 0xEA,
18286+ 0x89, 0xE2,
18287+ 0x2B, 0x30,
18288+
18289+ 0x3F, 0xC1, 0x1D, 0xBD,
18290+ 0x00, 0x80, 0x00, 0xE8,
18291+
18292+ 0x00, 0x80, 0x00, 0xE8,
18293+ 0x00, 0x80, 0x00, 0xE8,
18294+
18295+ 0xA0, 0x68,
18296+ 0xBF, 0x25,
18297+ 0x00, 0x80, 0x00, 0xE8,
18298+
18299+ 0x20, 0xC0, 0x20, 0xAF,
18300+ 0x28, 0x05,
18301+ 0x97, 0x74,
18302+
18303+ 0x00, 0xE0,
18304+ 0x2A, 0x10,
18305+ 0x16, 0xC0, 0x20, 0xE9,
18306+
18307+ 0x04, 0x80, 0x10, 0xEA,
18308+ 0x8C, 0xE2,
18309+ 0x95, 0x05,
18310+
18311+ 0x28, 0xC1, 0x28, 0xAD,
18312+ 0x1F, 0xC1, 0x15, 0xBD,
18313+
18314+ 0x00, 0x80, 0x00, 0xE8,
18315+ 0x00, 0x80, 0x00, 0xE8,
18316+
18317+ 0xA8, 0x67,
18318+ 0x9F, 0x6B,
18319+ 0x00, 0x80, 0x00, 0xE8,
18320+
18321+ 0x28, 0xC0, 0x28, 0xAD,
18322+ 0x1D, 0x25,
18323+ 0x20, 0x05,
18324+
18325+ 0x28, 0x32, 0x80, 0xAD,
18326+ 0x40, 0x2A, 0x40, 0xBD,
18327+
18328+ 0x1C, 0x80, 0x20, 0xE9,
18329+ 0x20, 0x33, 0x20, 0xAD,
18330+
18331+ 0x20, 0x73,
18332+ 0x00, 0xE0,
18333+ 0xB6, 0x49, 0x51, 0xBB,
18334+
18335+ 0x26, 0x2F, 0xB0, 0xE8,
18336+ 0x19, 0x20, 0x20, 0xE9,
18337+
18338+ 0x35, 0x20, 0x35, 0xDF,
18339+ 0x3D, 0x20, 0x3D, 0xDF,
18340+
18341+ 0x15, 0x20, 0x15, 0xDF,
18342+ 0x1D, 0x20, 0x1D, 0xDF,
18343+
18344+ 0x26, 0xD0, 0x26, 0xCD,
18345+ 0x29, 0x49, 0x2A, 0xB8,
18346+
18347+ 0x26, 0x40, 0x80, 0xBD,
18348+ 0x3B, 0x48, 0x50, 0xBD,
18349+
18350+ 0x3E, 0x54, 0x57, 0x9F,
18351+ 0x00, 0xE0,
18352+ 0x82, 0xE1,
18353+
18354+ 0x1E, 0xAF, 0x59, 0x9F,
18355+ 0x00, 0x80, 0x00, 0xE8,
18356+
18357+ 0x26, 0x30,
18358+ 0x29, 0x30,
18359+ 0x48, 0x3C, 0x48, 0xAD,
18360+
18361+ 0x2B, 0x72,
18362+ 0xC2, 0xE1,
18363+ 0x2C, 0xC0, 0x44, 0xC2,
18364+
18365+ 0x05, 0x24, 0x34, 0xBF,
18366+ 0x0D, 0x24, 0x2C, 0xBF,
18367+
18368+ 0x2D, 0x46, 0x4E, 0xBF,
18369+ 0x25, 0x46, 0x56, 0xBF,
18370+
18371+ 0x20, 0x1D, 0x6F, 0x8F,
18372+ 0x32, 0x3E, 0x5F, 0xE9,
18373+
18374+ 0x3E, 0x50, 0x56, 0x9F,
18375+ 0x00, 0xE0,
18376+ 0x3B, 0x30,
18377+
18378+ 0x1E, 0x8F, 0x51, 0x9F,
18379+ 0x33, 0x1E, 0x5F, 0xE9,
18380+
18381+ 0x05, 0x44, 0x54, 0xB2,
18382+ 0x0D, 0x44, 0x4C, 0xB2,
18383+
18384+ 0x19, 0xC0, 0xB0, 0xE8,
18385+ 0x34, 0xC0, 0x44, 0xC4,
18386+
18387+ 0x33, 0x73,
18388+ 0x00, 0xE0,
18389+ 0x3E, 0x62, 0x57, 0x9F,
18390+
18391+ 0x1E, 0xAF, 0x59, 0x9F,
18392+ 0x00, 0xE0,
18393+ 0x0D, 0x20,
18394+
18395+ 0x84, 0x3E, 0x58, 0xE9,
18396+ 0x28, 0x1D, 0x6F, 0x8F,
18397+
18398+ 0x05, 0x20,
18399+ 0x00, 0xE0,
18400+ 0x85, 0x1E, 0x58, 0xE9,
18401+
18402+ 0x9B, 0x3B, 0x33, 0xDF,
18403+ 0x20, 0x20, 0x42, 0xAF,
18404+
18405+ 0x30, 0x42, 0x56, 0x9F,
18406+ 0x80, 0x3E, 0x57, 0xE9,
18407+
18408+ 0x3F, 0x8F, 0x51, 0x9F,
18409+ 0x30, 0x80, 0x5F, 0xE9,
18410+
18411+ 0x28, 0x28, 0x24, 0xAF,
18412+ 0x81, 0x1E, 0x57, 0xE9,
18413+
18414+ 0x05, 0x47, 0x57, 0xBF,
18415+ 0x0D, 0x47, 0x4F, 0xBF,
18416+
18417+ 0x88, 0x80, 0x58, 0xE9,
18418+ 0x1B, 0x29, 0x1B, 0xDF,
18419+
18420+ 0x30, 0x1D, 0x6F, 0x8F,
18421+ 0x3A, 0x30, 0x4F, 0xE9,
18422+
18423+ 0x1C, 0x30, 0x26, 0xDF,
18424+ 0x09, 0xE3,
18425+ 0x3B, 0x05,
18426+
18427+ 0x3E, 0x50, 0x56, 0x9F,
18428+ 0x3B, 0x3F, 0x4F, 0xE9,
18429+
18430+ 0x1E, 0x8F, 0x51, 0x9F,
18431+ 0x00, 0xE0,
18432+ 0xAC, 0x20,
18433+
18434+ 0x2D, 0x44, 0x4C, 0xB4,
18435+ 0x2C, 0x1C, 0xC0, 0xAF,
18436+
18437+ 0x25, 0x44, 0x54, 0xB4,
18438+ 0x00, 0xE0,
18439+ 0xC8, 0x30,
18440+
18441+ 0x30, 0x46, 0x30, 0xAF,
18442+ 0x1B, 0x1B, 0x48, 0xAF,
18443+
18444+ 0x00, 0xE0,
18445+ 0x25, 0x20,
18446+ 0x38, 0x2C, 0x4F, 0xE9,
18447+
18448+ 0x86, 0x80, 0x57, 0xE9,
18449+ 0x38, 0x1D, 0x6F, 0x8F,
18450+
18451+ 0x28, 0x74,
18452+ 0x00, 0xE0,
18453+ 0x0D, 0x44, 0x4C, 0xB0,
18454+
18455+ 0x05, 0x44, 0x54, 0xB0,
18456+ 0x2D, 0x20,
18457+ 0x9B, 0x10,
18458+
18459+ 0x82, 0x3E, 0x57, 0xE9,
18460+ 0x32, 0xF0, 0x1B, 0xCD,
18461+
18462+ 0x1E, 0xBD, 0x59, 0x9F,
18463+ 0x83, 0x1E, 0x57, 0xE9,
18464+
18465+ 0x38, 0x47, 0x38, 0xAF,
18466+ 0x34, 0x20,
18467+ 0x2A, 0x30,
18468+
18469+ 0x00, 0xE0,
18470+ 0x0D, 0x20,
18471+ 0x32, 0x20,
18472+ 0x05, 0x20,
18473+
18474+ 0x87, 0x80, 0x57, 0xE9,
18475+ 0x1F, 0x54, 0x57, 0x9F,
18476+
18477+ 0x17, 0x42, 0x56, 0x9F,
18478+ 0x00, 0xE0,
18479+ 0x3B, 0x6A,
18480+
18481+ 0x3F, 0x8F, 0x51, 0x9F,
18482+ 0x37, 0x1E, 0x4F, 0xE9,
18483+
18484+ 0x37, 0x32, 0x2A, 0xAF,
18485+ 0x00, 0xE0,
18486+ 0x32, 0x00,
18487+
18488+ 0x00, 0x80, 0x00, 0xE8,
18489+ 0x27, 0xC0, 0x44, 0xC0,
18490+
18491+ 0x36, 0x1F, 0x4F, 0xE9,
18492+ 0x1F, 0x1F, 0x26, 0xDF,
18493+
18494+ 0x37, 0x1B, 0x37, 0xBF,
18495+ 0x17, 0x26, 0x17, 0xDF,
18496+
18497+ 0x3E, 0x17, 0x4F, 0xE9,
18498+ 0x3F, 0x3F, 0x4F, 0xE9,
18499+
18500+ 0x34, 0x1F, 0x34, 0xAF,
18501+ 0x2B, 0x05,
18502+ 0xA7, 0x20,
18503+
18504+ 0x33, 0x2B, 0x37, 0xDF,
18505+ 0x27, 0x17, 0xC0, 0xAF,
18506+
18507+ 0x34, 0x80, 0x4F, 0xE9,
18508+ 0x00, 0x80, 0x00, 0xE8,
18509+
18510+ 0x2D, 0x21, 0x1A, 0xB0,
18511+ 0x25, 0x21, 0x31, 0xB0,
18512+
18513+ 0x0D, 0x21, 0x1A, 0xB2,
18514+ 0x05, 0x21, 0x31, 0xB2,
18515+
18516+ 0x03, 0x80, 0x2A, 0xEA,
18517+ 0x17, 0xC1, 0x2B, 0xBD,
18518+
18519+ 0x2D, 0x20,
18520+ 0x25, 0x20,
18521+ 0x05, 0x20,
18522+ 0x0D, 0x20,
18523+
18524+ 0xB3, 0x68,
18525+ 0x97, 0x25,
18526+ 0x00, 0x80, 0x00, 0xE8,
18527+
18528+ 0x33, 0xC0, 0x33, 0xAF,
18529+ 0x2F, 0xC0, 0x21, 0xC0,
18530+
18531+ 0x16, 0x42, 0x56, 0x9F,
18532+ 0x3C, 0x27, 0x4F, 0xE9,
18533+
18534+ 0x1E, 0x62, 0x57, 0x9F,
18535+ 0x00, 0x80, 0x00, 0xE8,
18536+
18537+ 0x25, 0x21, 0x31, 0xB4,
18538+ 0x2D, 0x21, 0x1A, 0xB4,
18539+
18540+ 0x3F, 0x2F, 0x5D, 0x9F,
18541+ 0x00, 0x80, 0x00, 0xE8,
18542+
18543+ 0x33, 0x05,
18544+ 0x00, 0xE0,
18545+ 0x28, 0x19, 0x60, 0xEC,
18546+
18547+ 0x37, 0x0F, 0x5C, 0x9F,
18548+ 0x00, 0xE0,
18549+ 0x2F, 0x20,
18550+
18551+ 0x23, 0x3B, 0x33, 0xAD,
18552+ 0x1E, 0x26, 0x1E, 0xDF,
18553+
18554+ 0xA7, 0x1E, 0x4F, 0xE9,
18555+ 0x17, 0x26, 0x16, 0xDF,
18556+
18557+ 0x2D, 0x20,
18558+ 0x00, 0xE0,
18559+ 0xA8, 0x3F, 0x4F, 0xE9,
18560+
18561+ 0x2F, 0x2F, 0x1E, 0xAF,
18562+ 0x25, 0x20,
18563+ 0x00, 0xE0,
18564+
18565+ 0xA4, 0x16, 0x4F, 0xE9,
18566+ 0x0F, 0xC0, 0x21, 0xC2,
18567+
18568+ 0xA6, 0x80, 0x4F, 0xE9,
18569+ 0x1F, 0x62, 0x57, 0x9F,
18570+
18571+ 0x3F, 0x2F, 0x5D, 0x9F,
18572+ 0x00, 0xE0,
18573+ 0x8F, 0x20,
18574+
18575+ 0xA5, 0x37, 0x4F, 0xE9,
18576+ 0x0F, 0x17, 0x0F, 0xAF,
18577+
18578+ 0x06, 0xC0, 0x21, 0xC4,
18579+ 0x00, 0x80, 0x00, 0xE8,
18580+
18581+ 0x00, 0x80, 0x00, 0xE8,
18582+ 0xA3, 0x80, 0x4F, 0xE9,
18583+
18584+ 0x06, 0x20,
18585+ 0x00, 0xE0,
18586+ 0x1F, 0x26, 0x1F, 0xDF,
18587+
18588+ 0xA1, 0x1F, 0x4F, 0xE9,
18589+ 0xA2, 0x3F, 0x4F, 0xE9,
18590+
18591+ 0x00, 0x80, 0x00, 0xE8,
18592+ 0x00, 0x80, 0x00, 0xE8,
18593+
18594+ 0x06, 0x06, 0x1F, 0xAF,
18595+ 0x00, 0x80, 0x00, 0xE8,
18596+
18597+ 0x00, 0x80, 0x00, 0xE8,
18598+ 0x00, 0x80, 0x00, 0xE8,
18599+
18600+ 0xA0, 0x80, 0x4F, 0xE9,
18601+ 0x00, 0x80, 0x00, 0xE8,
18602+
18603+ 0x00, 0x80, 0x00, 0xE8,
18604+ 0x57, 0x39, 0x20, 0xE9,
18605+
18606+ 0x16, 0x28, 0x20, 0xE9,
18607+ 0x1D, 0x3B, 0x20, 0xE9,
18608+
18609+ 0x1E, 0x2B, 0x20, 0xE9,
18610+ 0x2B, 0x32, 0x20, 0xE9,
18611+
18612+ 0x1C, 0x23, 0x20, 0xE9,
18613+ 0x57, 0x36, 0x20, 0xE9,
18614+
18615+ 0x00, 0x80, 0xA0, 0xE9,
18616+ 0x40, 0x40, 0xD8, 0xEC,
18617+
18618+ 0xFF, 0x80, 0xC0, 0xE9,
18619+ 0x90, 0xE2,
18620+ 0x00, 0xE0,
18621+
18622+ 0x6C, 0xFF, 0x20, 0xEA,
18623+ 0x19, 0xC8, 0xC1, 0xCD,
18624+
18625+ 0x1F, 0xD7, 0x18, 0xBD,
18626+ 0x3F, 0xD7, 0x22, 0xBD,
18627+
18628+ 0x9F, 0x41, 0x49, 0xBD,
18629+ 0x00, 0x80, 0x00, 0xE8,
18630+
18631+ 0x25, 0x41, 0x49, 0xBD,
18632+ 0x2D, 0x41, 0x51, 0xBD,
18633+
18634+ 0x0D, 0x80, 0x07, 0xEA,
18635+ 0x00, 0x80, 0x00, 0xE8,
18636+
18637+ 0x35, 0x40, 0x48, 0xBD,
18638+ 0x3D, 0x40, 0x50, 0xBD,
18639+
18640+ 0x00, 0x80, 0x00, 0xE8,
18641+ 0x25, 0x30,
18642+ 0x2D, 0x30,
18643+
18644+ 0x35, 0x30,
18645+ 0xB5, 0x30,
18646+ 0xBD, 0x30,
18647+ 0x3D, 0x30,
18648+
18649+ 0x9C, 0xA7, 0x5B, 0x9F,
18650+ 0x00, 0x80, 0x00, 0xE8,
18651+
18652+ 0x00, 0x80, 0x00, 0xE8,
18653+ 0x00, 0x80, 0x00, 0xE8,
18654+
18655+ 0x00, 0x80, 0x00, 0xE8,
18656+ 0x00, 0x80, 0x00, 0xE8,
18657+
18658+ 0x00, 0x80, 0x00, 0xE8,
18659+ 0x00, 0x80, 0x00, 0xE8,
18660+
18661+ 0x00, 0x80, 0x00, 0xE8,
18662+ 0x00, 0x80, 0x00, 0xE8,
18663+
18664+ 0x6B, 0xFF, 0x0A, 0xEA,
18665+ 0x00, 0x80, 0x00, 0xE8,
18666+
18667+ 0xC9, 0x41, 0xC8, 0xEC,
18668+ 0x42, 0xE1,
18669+ 0x00, 0xE0,
18670+
18671+ 0x69, 0xFF, 0x20, 0xEA,
18672+ 0x00, 0x80, 0x00, 0xE8,
18673+
18674+ 0x00, 0x80, 0x00, 0xE8,
18675+ 0x00, 0x80, 0x00, 0xE8,
18676+
18677+ 0xC8, 0x40, 0xC0, 0xEC,
18678+ 0x00, 0x80, 0x00, 0xE8,
18679+
18680+ 0x66, 0xFF, 0x20, 0xEA,
18681+ 0x00, 0x80, 0x00, 0xE8,
18682+
18683+ 0x00, 0x80, 0x00, 0xE8,
18684+ 0x00, 0x80, 0x00, 0xE8,
18685+
18686+};
18687+
18688+static unsigned char warp_g200_tgzsa[] = {
18689+
18690+ 0x00, 0x80, 0x00, 0xE8,
18691+ 0x00, 0x80, 0x00, 0xE8,
18692+
18693+ 0x00, 0x80, 0x00, 0xE8,
18694+ 0x00, 0x80, 0x00, 0xE8,
18695+
18696+ 0x00, 0x80, 0x00, 0xE8,
18697+ 0x00, 0x80, 0x00, 0xE8,
18698+
18699+ 0x00, 0x80, 0x00, 0xE8,
18700+ 0x00, 0x80, 0x00, 0xE8,
18701+
18702+ 0x00, 0x80, 0x00, 0xE8,
18703+ 0x00, 0x80, 0x00, 0xE8,
18704+
18705+ 0x00, 0x80, 0x00, 0xE8,
18706+ 0x00, 0x80, 0x00, 0xE8,
18707+
18708+ 0x00, 0x80, 0x00, 0xE8,
18709+ 0x00, 0x80, 0x00, 0xE8,
18710+
18711+ 0x00, 0x80, 0x00, 0xE8,
18712+ 0x00, 0x80, 0x00, 0xE8,
18713+
18714+ 0x00, 0x80, 0x00, 0xE8,
18715+ 0x00, 0x80, 0x00, 0xE8,
18716+
18717+ 0x00, 0x80, 0x00, 0xE8,
18718+ 0x00, 0x80, 0x00, 0xE8,
18719+
18720+ 0x00, 0x80, 0x00, 0xE8,
18721+ 0x00, 0x80, 0x00, 0xE8,
18722+
18723+ 0x00, 0x80, 0x00, 0xE8,
18724+ 0x00, 0x80, 0x00, 0xE8,
18725+
18726+ 0x00, 0x80, 0x00, 0xE8,
18727+ 0x00, 0x80, 0x00, 0xE8,
18728+
18729+ 0x00, 0x98, 0xA0, 0xE9,
18730+ 0x40, 0x40, 0xD8, 0xEC,
18731+
18732+ 0xFF, 0x80, 0xC0, 0xE9,
18733+ 0x00, 0x80, 0x00, 0xE8,
18734+
18735+ 0x1F, 0xD7, 0x18, 0xBD,
18736+ 0x3F, 0xD7, 0x22, 0xBD,
18737+
18738+ 0x81, 0x04,
18739+ 0x89, 0x04,
18740+ 0x01, 0x04,
18741+ 0x09, 0x04,
18742+
18743+ 0xC9, 0x41, 0xC0, 0xEC,
18744+ 0x11, 0x04,
18745+ 0x00, 0xE0,
18746+
18747+ 0x41, 0xCC, 0x41, 0xCD,
18748+ 0x49, 0xCC, 0x49, 0xCD,
18749+
18750+ 0xD1, 0x41, 0xC0, 0xEC,
18751+ 0x51, 0xCC, 0x51, 0xCD,
18752+
18753+ 0x80, 0x04,
18754+ 0x10, 0x04,
18755+ 0x08, 0x04,
18756+ 0x00, 0xE0,
18757+
18758+ 0x00, 0xCC, 0xC0, 0xCD,
18759+ 0xD1, 0x49, 0xC0, 0xEC,
18760+
18761+ 0x8A, 0x1F, 0x20, 0xE9,
18762+ 0x8B, 0x3F, 0x20, 0xE9,
18763+
18764+ 0x41, 0x3C, 0x41, 0xAD,
18765+ 0x49, 0x3C, 0x49, 0xAD,
18766+
18767+ 0x10, 0xCC, 0x10, 0xCD,
18768+ 0x08, 0xCC, 0x08, 0xCD,
18769+
18770+ 0xB9, 0x41, 0x49, 0xBB,
18771+ 0x1F, 0xF0, 0x41, 0xCD,
18772+
18773+ 0x51, 0x3C, 0x51, 0xAD,
18774+ 0x00, 0x98, 0x80, 0xE9,
18775+
18776+ 0x8F, 0x80, 0x07, 0xEA,
18777+ 0x24, 0x1F, 0x20, 0xE9,
18778+
18779+ 0x21, 0x45, 0x80, 0xE8,
18780+ 0x1A, 0x4D, 0x80, 0xE8,
18781+
18782+ 0x31, 0x55, 0x80, 0xE8,
18783+ 0x00, 0x80, 0x00, 0xE8,
18784+
18785+ 0x15, 0x41, 0x49, 0xBD,
18786+ 0x1D, 0x41, 0x51, 0xBD,
18787+
18788+ 0x2E, 0x41, 0x2A, 0xB8,
18789+ 0x34, 0x53, 0xA0, 0xE8,
18790+
18791+ 0x15, 0x30,
18792+ 0x1D, 0x30,
18793+ 0x58, 0xE3,
18794+ 0x00, 0xE0,
18795+
18796+ 0xB5, 0x40, 0x48, 0xBD,
18797+ 0x3D, 0x40, 0x50, 0xBD,
18798+
18799+ 0x24, 0x43, 0xA0, 0xE8,
18800+ 0x2C, 0x4B, 0xA0, 0xE8,
18801+
18802+ 0x15, 0x72,
18803+ 0x09, 0xE3,
18804+ 0x00, 0xE0,
18805+ 0x1D, 0x72,
18806+
18807+ 0x35, 0x30,
18808+ 0xB5, 0x30,
18809+ 0xBD, 0x30,
18810+ 0x3D, 0x30,
18811+
18812+ 0x9C, 0x97, 0x57, 0x9F,
18813+ 0x00, 0x80, 0x00, 0xE8,
18814+
18815+ 0x6C, 0x64, 0xC8, 0xEC,
18816+ 0x98, 0xE1,
18817+ 0xB5, 0x05,
18818+
18819+ 0xBD, 0x05,
18820+ 0x2E, 0x30,
18821+ 0x32, 0xC0, 0xA0, 0xE8,
18822+
18823+ 0x33, 0xC0, 0xA0, 0xE8,
18824+ 0x74, 0x64, 0xC8, 0xEC,
18825+
18826+ 0x40, 0x3C, 0x40, 0xAD,
18827+ 0x32, 0x6A,
18828+ 0x2A, 0x30,
18829+
18830+ 0x20, 0x73,
18831+ 0x33, 0x6A,
18832+ 0x00, 0xE0,
18833+ 0x28, 0x73,
18834+
18835+ 0x1C, 0x72,
18836+ 0x83, 0xE2,
18837+ 0x7B, 0x80, 0x15, 0xEA,
18838+
18839+ 0xB8, 0x3D, 0x28, 0xDF,
18840+ 0x30, 0x35, 0x20, 0xDF,
18841+
18842+ 0x40, 0x30,
18843+ 0x00, 0xE0,
18844+ 0xCC, 0xE2,
18845+ 0x64, 0x72,
18846+
18847+ 0x25, 0x42, 0x52, 0xBF,
18848+ 0x2D, 0x42, 0x4A, 0xBF,
18849+
18850+ 0x30, 0x2E, 0x30, 0xDF,
18851+ 0x38, 0x2E, 0x38, 0xDF,
18852+
18853+ 0x18, 0x1D, 0x45, 0xE9,
18854+ 0x1E, 0x15, 0x45, 0xE9,
18855+
18856+ 0x2B, 0x49, 0x51, 0xBD,
18857+ 0x00, 0xE0,
18858+ 0x1F, 0x73,
18859+
18860+ 0x38, 0x38, 0x40, 0xAF,
18861+ 0x30, 0x30, 0x40, 0xAF,
18862+
18863+ 0x24, 0x1F, 0x24, 0xDF,
18864+ 0x1D, 0x32, 0x20, 0xE9,
18865+
18866+ 0x2C, 0x1F, 0x2C, 0xDF,
18867+ 0x1A, 0x33, 0x20, 0xE9,
18868+
18869+ 0xB0, 0x10,
18870+ 0x08, 0xE3,
18871+ 0x40, 0x10,
18872+ 0xB8, 0x10,
18873+
18874+ 0x26, 0xF0, 0x30, 0xCD,
18875+ 0x2F, 0xF0, 0x38, 0xCD,
18876+
18877+ 0x2B, 0x80, 0x20, 0xE9,
18878+ 0x2A, 0x80, 0x20, 0xE9,
18879+
18880+ 0xA6, 0x20,
18881+ 0x88, 0xE2,
18882+ 0x00, 0xE0,
18883+ 0xAF, 0x20,
18884+
18885+ 0x28, 0x2A, 0x26, 0xAF,
18886+ 0x20, 0x2A, 0xC0, 0xAF,
18887+
18888+ 0x34, 0x1F, 0x34, 0xDF,
18889+ 0x46, 0x24, 0x46, 0xDF,
18890+
18891+ 0x28, 0x30, 0x80, 0xBF,
18892+ 0x20, 0x38, 0x80, 0xBF,
18893+
18894+ 0x47, 0x24, 0x47, 0xDF,
18895+ 0x4E, 0x2C, 0x4E, 0xDF,
18896+
18897+ 0x4F, 0x2C, 0x4F, 0xDF,
18898+ 0x56, 0x34, 0x56, 0xDF,
18899+
18900+ 0x28, 0x15, 0x28, 0xDF,
18901+ 0x20, 0x1D, 0x20, 0xDF,
18902+
18903+ 0x57, 0x34, 0x57, 0xDF,
18904+ 0x00, 0xE0,
18905+ 0x1D, 0x05,
18906+
18907+ 0x04, 0x80, 0x10, 0xEA,
18908+ 0x89, 0xE2,
18909+ 0x2B, 0x30,
18910+
18911+ 0x3F, 0xC1, 0x1D, 0xBD,
18912+ 0x00, 0x80, 0x00, 0xE8,
18913+
18914+ 0x00, 0x80, 0x00, 0xE8,
18915+ 0x00, 0x80, 0x00, 0xE8,
18916+
18917+ 0xA0, 0x68,
18918+ 0xBF, 0x25,
18919+ 0x00, 0x80, 0x00, 0xE8,
18920+
18921+ 0x20, 0xC0, 0x20, 0xAF,
18922+ 0x28, 0x05,
18923+ 0x97, 0x74,
18924+
18925+ 0x00, 0xE0,
18926+ 0x2A, 0x10,
18927+ 0x16, 0xC0, 0x20, 0xE9,
18928+
18929+ 0x04, 0x80, 0x10, 0xEA,
18930+ 0x8C, 0xE2,
18931+ 0x95, 0x05,
18932+
18933+ 0x28, 0xC1, 0x28, 0xAD,
18934+ 0x1F, 0xC1, 0x15, 0xBD,
18935+
18936+ 0x00, 0x80, 0x00, 0xE8,
18937+ 0x00, 0x80, 0x00, 0xE8,
18938+
18939+ 0xA8, 0x67,
18940+ 0x9F, 0x6B,
18941+ 0x00, 0x80, 0x00, 0xE8,
18942+
18943+ 0x28, 0xC0, 0x28, 0xAD,
18944+ 0x1D, 0x25,
18945+ 0x20, 0x05,
18946+
18947+ 0x28, 0x32, 0x80, 0xAD,
18948+ 0x40, 0x2A, 0x40, 0xBD,
18949+
18950+ 0x1C, 0x80, 0x20, 0xE9,
18951+ 0x20, 0x33, 0x20, 0xAD,
18952+
18953+ 0x20, 0x73,
18954+ 0x00, 0xE0,
18955+ 0xB6, 0x49, 0x51, 0xBB,
18956+
18957+ 0x26, 0x2F, 0xB0, 0xE8,
18958+ 0x19, 0x20, 0x20, 0xE9,
18959+
18960+ 0x35, 0x20, 0x35, 0xDF,
18961+ 0x3D, 0x20, 0x3D, 0xDF,
18962+
18963+ 0x15, 0x20, 0x15, 0xDF,
18964+ 0x1D, 0x20, 0x1D, 0xDF,
18965+
18966+ 0x26, 0xD0, 0x26, 0xCD,
18967+ 0x29, 0x49, 0x2A, 0xB8,
18968+
18969+ 0x26, 0x40, 0x80, 0xBD,
18970+ 0x3B, 0x48, 0x50, 0xBD,
18971+
18972+ 0x3E, 0x54, 0x57, 0x9F,
18973+ 0x00, 0xE0,
18974+ 0x82, 0xE1,
18975+
18976+ 0x1E, 0xAF, 0x59, 0x9F,
18977+ 0x00, 0x80, 0x00, 0xE8,
18978+
18979+ 0x26, 0x30,
18980+ 0x29, 0x30,
18981+ 0x48, 0x3C, 0x48, 0xAD,
18982+
18983+ 0x2B, 0x72,
18984+ 0xC2, 0xE1,
18985+ 0x2C, 0xC0, 0x44, 0xC2,
18986+
18987+ 0x05, 0x24, 0x34, 0xBF,
18988+ 0x0D, 0x24, 0x2C, 0xBF,
18989+
18990+ 0x2D, 0x46, 0x4E, 0xBF,
18991+ 0x25, 0x46, 0x56, 0xBF,
18992+
18993+ 0x20, 0x1D, 0x6F, 0x8F,
18994+ 0x32, 0x3E, 0x5F, 0xE9,
18995+
18996+ 0x3E, 0x50, 0x56, 0x9F,
18997+ 0x00, 0xE0,
18998+ 0x3B, 0x30,
18999+
19000+ 0x1E, 0x8F, 0x51, 0x9F,
19001+ 0x33, 0x1E, 0x5F, 0xE9,
19002+
19003+ 0x05, 0x44, 0x54, 0xB2,
19004+ 0x0D, 0x44, 0x4C, 0xB2,
19005+
19006+ 0x19, 0xC0, 0xB0, 0xE8,
19007+ 0x34, 0xC0, 0x44, 0xC4,
19008+
19009+ 0x33, 0x73,
19010+ 0x00, 0xE0,
19011+ 0x3E, 0x62, 0x57, 0x9F,
19012+
19013+ 0x1E, 0xAF, 0x59, 0x9F,
19014+ 0x00, 0xE0,
19015+ 0x0D, 0x20,
19016+
19017+ 0x84, 0x3E, 0x58, 0xE9,
19018+ 0x28, 0x1D, 0x6F, 0x8F,
19019+
19020+ 0x05, 0x20,
19021+ 0x00, 0xE0,
19022+ 0x85, 0x1E, 0x58, 0xE9,
19023+
19024+ 0x9B, 0x3B, 0x33, 0xDF,
19025+ 0x20, 0x20, 0x42, 0xAF,
19026+
19027+ 0x30, 0x42, 0x56, 0x9F,
19028+ 0x80, 0x3E, 0x57, 0xE9,
19029+
19030+ 0x3F, 0x8F, 0x51, 0x9F,
19031+ 0x30, 0x80, 0x5F, 0xE9,
19032+
19033+ 0x28, 0x28, 0x24, 0xAF,
19034+ 0x81, 0x1E, 0x57, 0xE9,
19035+
19036+ 0x05, 0x47, 0x57, 0xBF,
19037+ 0x0D, 0x47, 0x4F, 0xBF,
19038+
19039+ 0x88, 0x80, 0x58, 0xE9,
19040+ 0x1B, 0x29, 0x1B, 0xDF,
19041+
19042+ 0x30, 0x1D, 0x6F, 0x8F,
19043+ 0x3A, 0x30, 0x4F, 0xE9,
19044+
19045+ 0x1C, 0x30, 0x26, 0xDF,
19046+ 0x09, 0xE3,
19047+ 0x3B, 0x05,
19048+
19049+ 0x3E, 0x50, 0x56, 0x9F,
19050+ 0x3B, 0x3F, 0x4F, 0xE9,
19051+
19052+ 0x1E, 0x8F, 0x51, 0x9F,
19053+ 0x00, 0xE0,
19054+ 0xAC, 0x20,
19055+
19056+ 0x2D, 0x44, 0x4C, 0xB4,
19057+ 0x2C, 0x1C, 0xC0, 0xAF,
19058+
19059+ 0x25, 0x44, 0x54, 0xB4,
19060+ 0x00, 0xE0,
19061+ 0xC8, 0x30,
19062+
19063+ 0x30, 0x46, 0x30, 0xAF,
19064+ 0x1B, 0x1B, 0x48, 0xAF,
19065+
19066+ 0x00, 0xE0,
19067+ 0x25, 0x20,
19068+ 0x38, 0x2C, 0x4F, 0xE9,
19069+
19070+ 0x86, 0x80, 0x57, 0xE9,
19071+ 0x38, 0x1D, 0x6F, 0x8F,
19072+
19073+ 0x28, 0x74,
19074+ 0x00, 0xE0,
19075+ 0x0D, 0x44, 0x4C, 0xB0,
19076+
19077+ 0x05, 0x44, 0x54, 0xB0,
19078+ 0x2D, 0x20,
19079+ 0x9B, 0x10,
19080+
19081+ 0x82, 0x3E, 0x57, 0xE9,
19082+ 0x32, 0xF0, 0x1B, 0xCD,
19083+
19084+ 0x1E, 0xBD, 0x59, 0x9F,
19085+ 0x83, 0x1E, 0x57, 0xE9,
19086+
19087+ 0x38, 0x47, 0x38, 0xAF,
19088+ 0x34, 0x20,
19089+ 0x2A, 0x30,
19090+
19091+ 0x00, 0xE0,
19092+ 0x0D, 0x20,
19093+ 0x32, 0x20,
19094+ 0x05, 0x20,
19095+
19096+ 0x87, 0x80, 0x57, 0xE9,
19097+ 0x1F, 0x54, 0x57, 0x9F,
19098+
19099+ 0x17, 0x42, 0x56, 0x9F,
19100+ 0x00, 0xE0,
19101+ 0x3B, 0x6A,
19102+
19103+ 0x3F, 0x8F, 0x51, 0x9F,
19104+ 0x37, 0x1E, 0x4F, 0xE9,
19105+
19106+ 0x37, 0x32, 0x2A, 0xAF,
19107+ 0x00, 0xE0,
19108+ 0x32, 0x00,
19109+
19110+ 0x00, 0x80, 0x00, 0xE8,
19111+ 0x27, 0xC0, 0x44, 0xC0,
19112+
19113+ 0x36, 0x1F, 0x4F, 0xE9,
19114+ 0x1F, 0x1F, 0x26, 0xDF,
19115+
19116+ 0x37, 0x1B, 0x37, 0xBF,
19117+ 0x17, 0x26, 0x17, 0xDF,
19118+
19119+ 0x3E, 0x17, 0x4F, 0xE9,
19120+ 0x3F, 0x3F, 0x4F, 0xE9,
19121+
19122+ 0x34, 0x1F, 0x34, 0xAF,
19123+ 0x2B, 0x05,
19124+ 0xA7, 0x20,
19125+
19126+ 0x33, 0x2B, 0x37, 0xDF,
19127+ 0x27, 0x17, 0xC0, 0xAF,
19128+
19129+ 0x34, 0x80, 0x4F, 0xE9,
19130+ 0x00, 0x80, 0x00, 0xE8,
19131+
19132+ 0x2D, 0x21, 0x1A, 0xB0,
19133+ 0x25, 0x21, 0x31, 0xB0,
19134+
19135+ 0x0D, 0x21, 0x1A, 0xB2,
19136+ 0x05, 0x21, 0x31, 0xB2,
19137+
19138+ 0x03, 0x80, 0x2A, 0xEA,
19139+ 0x17, 0xC1, 0x2B, 0xBD,
19140+
19141+ 0x2D, 0x20,
19142+ 0x25, 0x20,
19143+ 0x05, 0x20,
19144+ 0x0D, 0x20,
19145+
19146+ 0xB3, 0x68,
19147+ 0x97, 0x25,
19148+ 0x00, 0x80, 0x00, 0xE8,
19149+
19150+ 0x33, 0xC0, 0x33, 0xAF,
19151+ 0x2F, 0xC0, 0x21, 0xC0,
19152+
19153+ 0x16, 0x42, 0x56, 0x9F,
19154+ 0x3C, 0x27, 0x4F, 0xE9,
19155+
19156+ 0x1E, 0x62, 0x57, 0x9F,
19157+ 0x00, 0x80, 0x00, 0xE8,
19158+
19159+ 0x25, 0x21, 0x31, 0xB4,
19160+ 0x2D, 0x21, 0x1A, 0xB4,
19161+
19162+ 0x3F, 0x2F, 0x5D, 0x9F,
19163+ 0x00, 0x80, 0x00, 0xE8,
19164+
19165+ 0x33, 0x05,
19166+ 0x00, 0xE0,
19167+ 0x28, 0x19, 0x60, 0xEC,
19168+
19169+ 0x0D, 0x44, 0x4C, 0xB6,
19170+ 0x05, 0x44, 0x54, 0xB6,
19171+
19172+ 0x37, 0x0F, 0x5C, 0x9F,
19173+ 0x00, 0xE0,
19174+ 0x2F, 0x20,
19175+
19176+ 0x23, 0x3B, 0x33, 0xAD,
19177+ 0x1E, 0x26, 0x1E, 0xDF,
19178+
19179+ 0xA7, 0x1E, 0x4F, 0xE9,
19180+ 0x17, 0x26, 0x16, 0xDF,
19181+
19182+ 0x2D, 0x20,
19183+ 0x00, 0xE0,
19184+ 0xA8, 0x3F, 0x4F, 0xE9,
19185+
19186+ 0x2F, 0x2F, 0x1E, 0xAF,
19187+ 0x25, 0x20,
19188+ 0x00, 0xE0,
19189+
19190+ 0xA4, 0x16, 0x4F, 0xE9,
19191+ 0x0F, 0xC0, 0x21, 0xC2,
19192+
19193+ 0xA6, 0x80, 0x4F, 0xE9,
19194+ 0x1F, 0x62, 0x57, 0x9F,
19195+
19196+ 0x0D, 0x20,
19197+ 0x05, 0x20,
19198+ 0x00, 0x80, 0x00, 0xE8,
19199+
19200+ 0x3F, 0x2F, 0x5D, 0x9F,
19201+ 0x00, 0xE0,
19202+ 0x0F, 0x20,
19203+
19204+ 0x17, 0x50, 0x56, 0x9F,
19205+ 0xA5, 0x37, 0x4F, 0xE9,
19206+
19207+ 0x06, 0xC0, 0x21, 0xC4,
19208+ 0x0F, 0x17, 0x0F, 0xAF,
19209+
19210+ 0x37, 0x0F, 0x5C, 0x9F,
19211+ 0x00, 0x80, 0x00, 0xE8,
19212+
19213+ 0x2F, 0xC0, 0x44, 0xC6,
19214+ 0xA3, 0x80, 0x4F, 0xE9,
19215+
19216+ 0x06, 0x20,
19217+ 0x00, 0xE0,
19218+ 0x1F, 0x26, 0x1F, 0xDF,
19219+
19220+ 0x17, 0x26, 0x17, 0xDF,
19221+ 0x9D, 0x17, 0x4F, 0xE9,
19222+
19223+ 0xA1, 0x1F, 0x4F, 0xE9,
19224+ 0xA2, 0x3F, 0x4F, 0xE9,
19225+
19226+ 0x06, 0x06, 0x1F, 0xAF,
19227+ 0x00, 0xE0,
19228+ 0xAF, 0x20,
19229+
19230+ 0x9E, 0x37, 0x4F, 0xE9,
19231+ 0x2F, 0x17, 0x2F, 0xAF,
19232+
19233+ 0xA0, 0x80, 0x4F, 0xE9,
19234+ 0x00, 0x80, 0x00, 0xE8,
19235+
19236+ 0x00, 0x80, 0x00, 0xE8,
19237+ 0x9C, 0x80, 0x4F, 0xE9,
19238+
19239+ 0x00, 0x80, 0x00, 0xE8,
19240+ 0x57, 0x39, 0x20, 0xE9,
19241+
19242+ 0x16, 0x28, 0x20, 0xE9,
19243+ 0x1D, 0x3B, 0x20, 0xE9,
19244+
19245+ 0x1E, 0x2B, 0x20, 0xE9,
19246+ 0x2B, 0x32, 0x20, 0xE9,
19247+
19248+ 0x1C, 0x23, 0x20, 0xE9,
19249+ 0x57, 0x36, 0x20, 0xE9,
19250+
19251+ 0x00, 0x80, 0xA0, 0xE9,
19252+ 0x40, 0x40, 0xD8, 0xEC,
19253+
19254+ 0xFF, 0x80, 0xC0, 0xE9,
19255+ 0x90, 0xE2,
19256+ 0x00, 0xE0,
19257+
19258+ 0x68, 0xFF, 0x20, 0xEA,
19259+ 0x19, 0xC8, 0xC1, 0xCD,
19260+
19261+ 0x1F, 0xD7, 0x18, 0xBD,
19262+ 0x3F, 0xD7, 0x22, 0xBD,
19263+
19264+ 0x9F, 0x41, 0x49, 0xBD,
19265+ 0x00, 0x80, 0x00, 0xE8,
19266+
19267+ 0x25, 0x41, 0x49, 0xBD,
19268+ 0x2D, 0x41, 0x51, 0xBD,
19269+
19270+ 0x0D, 0x80, 0x07, 0xEA,
19271+ 0x00, 0x80, 0x00, 0xE8,
19272+
19273+ 0x35, 0x40, 0x48, 0xBD,
19274+ 0x3D, 0x40, 0x50, 0xBD,
19275+
19276+ 0x00, 0x80, 0x00, 0xE8,
19277+ 0x25, 0x30,
19278+ 0x2D, 0x30,
19279+
19280+ 0x35, 0x30,
19281+ 0xB5, 0x30,
19282+ 0xBD, 0x30,
19283+ 0x3D, 0x30,
19284+
19285+ 0x9C, 0xA7, 0x5B, 0x9F,
19286+ 0x00, 0x80, 0x00, 0xE8,
19287+
19288+ 0x00, 0x80, 0x00, 0xE8,
19289+ 0x00, 0x80, 0x00, 0xE8,
19290+
19291+ 0x00, 0x80, 0x00, 0xE8,
19292+ 0x00, 0x80, 0x00, 0xE8,
19293+
19294+ 0x00, 0x80, 0x00, 0xE8,
19295+ 0x00, 0x80, 0x00, 0xE8,
19296+
19297+ 0x00, 0x80, 0x00, 0xE8,
19298+ 0x00, 0x80, 0x00, 0xE8,
19299+
19300+ 0x67, 0xFF, 0x0A, 0xEA,
19301+ 0x00, 0x80, 0x00, 0xE8,
19302+
19303+ 0xC9, 0x41, 0xC8, 0xEC,
19304+ 0x42, 0xE1,
19305+ 0x00, 0xE0,
19306+
19307+ 0x65, 0xFF, 0x20, 0xEA,
19308+ 0x00, 0x80, 0x00, 0xE8,
19309+
19310+ 0x00, 0x80, 0x00, 0xE8,
19311+ 0x00, 0x80, 0x00, 0xE8,
19312+
19313+ 0xC8, 0x40, 0xC0, 0xEC,
19314+ 0x00, 0x80, 0x00, 0xE8,
19315+
19316+ 0x62, 0xFF, 0x20, 0xEA,
19317+ 0x00, 0x80, 0x00, 0xE8,
19318+
19319+ 0x00, 0x80, 0x00, 0xE8,
19320+ 0x00, 0x80, 0x00, 0xE8,
19321+
19322+};
19323+
19324+static unsigned char warp_g200_tgzsaf[] = {
19325+
19326+ 0x00, 0x80, 0x00, 0xE8,
19327+ 0x00, 0x80, 0x00, 0xE8,
19328+
19329+ 0x00, 0x80, 0x00, 0xE8,
19330+ 0x00, 0x80, 0x00, 0xE8,
19331+
19332+ 0x00, 0x80, 0x00, 0xE8,
19333+ 0x00, 0x80, 0x00, 0xE8,
19334+
19335+ 0x00, 0x98, 0xA0, 0xE9,
19336+ 0x40, 0x40, 0xD8, 0xEC,
19337+
19338+ 0xFF, 0x80, 0xC0, 0xE9,
19339+ 0x00, 0x80, 0x00, 0xE8,
19340+
19341+ 0x1F, 0xD7, 0x18, 0xBD,
19342+ 0x3F, 0xD7, 0x22, 0xBD,
19343+
19344+ 0x81, 0x04,
19345+ 0x89, 0x04,
19346+ 0x01, 0x04,
19347+ 0x09, 0x04,
19348+
19349+ 0xC9, 0x41, 0xC0, 0xEC,
19350+ 0x11, 0x04,
19351+ 0x00, 0xE0,
19352+
19353+ 0x41, 0xCC, 0x41, 0xCD,
19354+ 0x49, 0xCC, 0x49, 0xCD,
19355+
19356+ 0xD1, 0x41, 0xC0, 0xEC,
19357+ 0x51, 0xCC, 0x51, 0xCD,
19358+
19359+ 0x80, 0x04,
19360+ 0x10, 0x04,
19361+ 0x08, 0x04,
19362+ 0x00, 0xE0,
19363+
19364+ 0x00, 0xCC, 0xC0, 0xCD,
19365+ 0xD1, 0x49, 0xC0, 0xEC,
19366+
19367+ 0x8A, 0x1F, 0x20, 0xE9,
19368+ 0x8B, 0x3F, 0x20, 0xE9,
19369+
19370+ 0x41, 0x3C, 0x41, 0xAD,
19371+ 0x49, 0x3C, 0x49, 0xAD,
19372+
19373+ 0x10, 0xCC, 0x10, 0xCD,
19374+ 0x08, 0xCC, 0x08, 0xCD,
19375+
19376+ 0xB9, 0x41, 0x49, 0xBB,
19377+ 0x1F, 0xF0, 0x41, 0xCD,
19378+
19379+ 0x51, 0x3C, 0x51, 0xAD,
19380+ 0x00, 0x98, 0x80, 0xE9,
19381+
19382+ 0x94, 0x80, 0x07, 0xEA,
19383+ 0x24, 0x1F, 0x20, 0xE9,
19384+
19385+ 0x21, 0x45, 0x80, 0xE8,
19386+ 0x1A, 0x4D, 0x80, 0xE8,
19387+
19388+ 0x31, 0x55, 0x80, 0xE8,
19389+ 0x00, 0x80, 0x00, 0xE8,
19390+
19391+ 0x15, 0x41, 0x49, 0xBD,
19392+ 0x1D, 0x41, 0x51, 0xBD,
19393+
19394+ 0x2E, 0x41, 0x2A, 0xB8,
19395+ 0x34, 0x53, 0xA0, 0xE8,
19396+
19397+ 0x15, 0x30,
19398+ 0x1D, 0x30,
19399+ 0x58, 0xE3,
19400+ 0x00, 0xE0,
19401+
19402+ 0xB5, 0x40, 0x48, 0xBD,
19403+ 0x3D, 0x40, 0x50, 0xBD,
19404+
19405+ 0x24, 0x43, 0xA0, 0xE8,
19406+ 0x2C, 0x4B, 0xA0, 0xE8,
19407+
19408+ 0x15, 0x72,
19409+ 0x09, 0xE3,
19410+ 0x00, 0xE0,
19411+ 0x1D, 0x72,
19412+
19413+ 0x35, 0x30,
19414+ 0xB5, 0x30,
19415+ 0xBD, 0x30,
19416+ 0x3D, 0x30,
19417+
19418+ 0x9C, 0x97, 0x57, 0x9F,
19419+ 0x00, 0x80, 0x00, 0xE8,
19420+
19421+ 0x6C, 0x64, 0xC8, 0xEC,
19422+ 0x98, 0xE1,
19423+ 0xB5, 0x05,
19424+
19425+ 0xBD, 0x05,
19426+ 0x2E, 0x30,
19427+ 0x32, 0xC0, 0xA0, 0xE8,
19428+
19429+ 0x33, 0xC0, 0xA0, 0xE8,
19430+ 0x74, 0x64, 0xC8, 0xEC,
19431+
19432+ 0x40, 0x3C, 0x40, 0xAD,
19433+ 0x32, 0x6A,
19434+ 0x2A, 0x30,
19435+
19436+ 0x20, 0x73,
19437+ 0x33, 0x6A,
19438+ 0x00, 0xE0,
19439+ 0x28, 0x73,
19440+
19441+ 0x1C, 0x72,
19442+ 0x83, 0xE2,
19443+ 0x80, 0x80, 0x15, 0xEA,
19444+
19445+ 0xB8, 0x3D, 0x28, 0xDF,
19446+ 0x30, 0x35, 0x20, 0xDF,
19447+
19448+ 0x40, 0x30,
19449+ 0x00, 0xE0,
19450+ 0xCC, 0xE2,
19451+ 0x64, 0x72,
19452+
19453+ 0x25, 0x42, 0x52, 0xBF,
19454+ 0x2D, 0x42, 0x4A, 0xBF,
19455+
19456+ 0x30, 0x2E, 0x30, 0xDF,
19457+ 0x38, 0x2E, 0x38, 0xDF,
19458+
19459+ 0x18, 0x1D, 0x45, 0xE9,
19460+ 0x1E, 0x15, 0x45, 0xE9,
19461+
19462+ 0x2B, 0x49, 0x51, 0xBD,
19463+ 0x00, 0xE0,
19464+ 0x1F, 0x73,
19465+
19466+ 0x38, 0x38, 0x40, 0xAF,
19467+ 0x30, 0x30, 0x40, 0xAF,
19468+
19469+ 0x24, 0x1F, 0x24, 0xDF,
19470+ 0x1D, 0x32, 0x20, 0xE9,
19471+
19472+ 0x2C, 0x1F, 0x2C, 0xDF,
19473+ 0x1A, 0x33, 0x20, 0xE9,
19474+
19475+ 0xB0, 0x10,
19476+ 0x08, 0xE3,
19477+ 0x40, 0x10,
19478+ 0xB8, 0x10,
19479+
19480+ 0x26, 0xF0, 0x30, 0xCD,
19481+ 0x2F, 0xF0, 0x38, 0xCD,
19482+
19483+ 0x2B, 0x80, 0x20, 0xE9,
19484+ 0x2A, 0x80, 0x20, 0xE9,
19485+
19486+ 0xA6, 0x20,
19487+ 0x88, 0xE2,
19488+ 0x00, 0xE0,
19489+ 0xAF, 0x20,
19490+
19491+ 0x28, 0x2A, 0x26, 0xAF,
19492+ 0x20, 0x2A, 0xC0, 0xAF,
19493+
19494+ 0x34, 0x1F, 0x34, 0xDF,
19495+ 0x46, 0x24, 0x46, 0xDF,
19496+
19497+ 0x28, 0x30, 0x80, 0xBF,
19498+ 0x20, 0x38, 0x80, 0xBF,
19499+
19500+ 0x47, 0x24, 0x47, 0xDF,
19501+ 0x4E, 0x2C, 0x4E, 0xDF,
19502+
19503+ 0x4F, 0x2C, 0x4F, 0xDF,
19504+ 0x56, 0x34, 0x56, 0xDF,
19505+
19506+ 0x28, 0x15, 0x28, 0xDF,
19507+ 0x20, 0x1D, 0x20, 0xDF,
19508+
19509+ 0x57, 0x34, 0x57, 0xDF,
19510+ 0x00, 0xE0,
19511+ 0x1D, 0x05,
19512+
19513+ 0x04, 0x80, 0x10, 0xEA,
19514+ 0x89, 0xE2,
19515+ 0x2B, 0x30,
19516+
19517+ 0x3F, 0xC1, 0x1D, 0xBD,
19518+ 0x00, 0x80, 0x00, 0xE8,
19519+
19520+ 0x00, 0x80, 0x00, 0xE8,
19521+ 0x00, 0x80, 0x00, 0xE8,
19522+
19523+ 0xA0, 0x68,
19524+ 0xBF, 0x25,
19525+ 0x00, 0x80, 0x00, 0xE8,
19526+
19527+ 0x20, 0xC0, 0x20, 0xAF,
19528+ 0x28, 0x05,
19529+ 0x97, 0x74,
19530+
19531+ 0x00, 0xE0,
19532+ 0x2A, 0x10,
19533+ 0x16, 0xC0, 0x20, 0xE9,
19534+
19535+ 0x04, 0x80, 0x10, 0xEA,
19536+ 0x8C, 0xE2,
19537+ 0x95, 0x05,
19538+
19539+ 0x28, 0xC1, 0x28, 0xAD,
19540+ 0x1F, 0xC1, 0x15, 0xBD,
19541+
19542+ 0x00, 0x80, 0x00, 0xE8,
19543+ 0x00, 0x80, 0x00, 0xE8,
19544+
19545+ 0xA8, 0x67,
19546+ 0x9F, 0x6B,
19547+ 0x00, 0x80, 0x00, 0xE8,
19548+
19549+ 0x28, 0xC0, 0x28, 0xAD,
19550+ 0x1D, 0x25,
19551+ 0x20, 0x05,
19552+
19553+ 0x28, 0x32, 0x80, 0xAD,
19554+ 0x40, 0x2A, 0x40, 0xBD,
19555+
19556+ 0x1C, 0x80, 0x20, 0xE9,
19557+ 0x20, 0x33, 0x20, 0xAD,
19558+
19559+ 0x20, 0x73,
19560+ 0x00, 0xE0,
19561+ 0xB6, 0x49, 0x51, 0xBB,
19562+
19563+ 0x26, 0x2F, 0xB0, 0xE8,
19564+ 0x19, 0x20, 0x20, 0xE9,
19565+
19566+ 0x35, 0x20, 0x35, 0xDF,
19567+ 0x3D, 0x20, 0x3D, 0xDF,
19568+
19569+ 0x15, 0x20, 0x15, 0xDF,
19570+ 0x1D, 0x20, 0x1D, 0xDF,
19571+
19572+ 0x26, 0xD0, 0x26, 0xCD,
19573+ 0x29, 0x49, 0x2A, 0xB8,
19574+
19575+ 0x26, 0x40, 0x80, 0xBD,
19576+ 0x3B, 0x48, 0x50, 0xBD,
19577+
19578+ 0x3E, 0x54, 0x57, 0x9F,
19579+ 0x00, 0xE0,
19580+ 0x82, 0xE1,
19581+
19582+ 0x1E, 0xAF, 0x59, 0x9F,
19583+ 0x00, 0x80, 0x00, 0xE8,
19584+
19585+ 0x26, 0x30,
19586+ 0x29, 0x30,
19587+ 0x48, 0x3C, 0x48, 0xAD,
19588+
19589+ 0x2B, 0x72,
19590+ 0xC2, 0xE1,
19591+ 0x2C, 0xC0, 0x44, 0xC2,
19592+
19593+ 0x05, 0x24, 0x34, 0xBF,
19594+ 0x0D, 0x24, 0x2C, 0xBF,
19595+
19596+ 0x2D, 0x46, 0x4E, 0xBF,
19597+ 0x25, 0x46, 0x56, 0xBF,
19598+
19599+ 0x20, 0x1D, 0x6F, 0x8F,
19600+ 0x32, 0x3E, 0x5F, 0xE9,
19601+
19602+ 0x3E, 0x50, 0x56, 0x9F,
19603+ 0x00, 0xE0,
19604+ 0x3B, 0x30,
19605+
19606+ 0x1E, 0x8F, 0x51, 0x9F,
19607+ 0x33, 0x1E, 0x5F, 0xE9,
19608+
19609+ 0x05, 0x44, 0x54, 0xB2,
19610+ 0x0D, 0x44, 0x4C, 0xB2,
19611+
19612+ 0x19, 0xC0, 0xB0, 0xE8,
19613+ 0x34, 0xC0, 0x44, 0xC4,
19614+
19615+ 0x33, 0x73,
19616+ 0x00, 0xE0,
19617+ 0x3E, 0x62, 0x57, 0x9F,
19618+
19619+ 0x1E, 0xAF, 0x59, 0x9F,
19620+ 0x00, 0xE0,
19621+ 0x0D, 0x20,
19622+
19623+ 0x84, 0x3E, 0x58, 0xE9,
19624+ 0x28, 0x1D, 0x6F, 0x8F,
19625+
19626+ 0x05, 0x20,
19627+ 0x00, 0xE0,
19628+ 0x85, 0x1E, 0x58, 0xE9,
19629+
19630+ 0x9B, 0x3B, 0x33, 0xDF,
19631+ 0x20, 0x20, 0x42, 0xAF,
19632+
19633+ 0x30, 0x42, 0x56, 0x9F,
19634+ 0x80, 0x3E, 0x57, 0xE9,
19635+
19636+ 0x3F, 0x8F, 0x51, 0x9F,
19637+ 0x30, 0x80, 0x5F, 0xE9,
19638+
19639+ 0x28, 0x28, 0x24, 0xAF,
19640+ 0x81, 0x1E, 0x57, 0xE9,
19641+
19642+ 0x05, 0x47, 0x57, 0xBF,
19643+ 0x0D, 0x47, 0x4F, 0xBF,
19644+
19645+ 0x88, 0x80, 0x58, 0xE9,
19646+ 0x1B, 0x29, 0x1B, 0xDF,
19647+
19648+ 0x30, 0x1D, 0x6F, 0x8F,
19649+ 0x3A, 0x30, 0x4F, 0xE9,
19650+
19651+ 0x1C, 0x30, 0x26, 0xDF,
19652+ 0x09, 0xE3,
19653+ 0x3B, 0x05,
19654+
19655+ 0x3E, 0x50, 0x56, 0x9F,
19656+ 0x3B, 0x3F, 0x4F, 0xE9,
19657+
19658+ 0x1E, 0x8F, 0x51, 0x9F,
19659+ 0x00, 0xE0,
19660+ 0xAC, 0x20,
19661+
19662+ 0x2D, 0x44, 0x4C, 0xB4,
19663+ 0x2C, 0x1C, 0xC0, 0xAF,
19664+
19665+ 0x25, 0x44, 0x54, 0xB4,
19666+ 0x00, 0xE0,
19667+ 0xC8, 0x30,
19668+
19669+ 0x30, 0x46, 0x30, 0xAF,
19670+ 0x1B, 0x1B, 0x48, 0xAF,
19671+
19672+ 0x00, 0xE0,
19673+ 0x25, 0x20,
19674+ 0x38, 0x2C, 0x4F, 0xE9,
19675+
19676+ 0x86, 0x80, 0x57, 0xE9,
19677+ 0x38, 0x1D, 0x6F, 0x8F,
19678+
19679+ 0x28, 0x74,
19680+ 0x00, 0xE0,
19681+ 0x0D, 0x44, 0x4C, 0xB0,
19682+
19683+ 0x05, 0x44, 0x54, 0xB0,
19684+ 0x2D, 0x20,
19685+ 0x9B, 0x10,
19686+
19687+ 0x82, 0x3E, 0x57, 0xE9,
19688+ 0x32, 0xF0, 0x1B, 0xCD,
19689+
19690+ 0x1E, 0xBD, 0x59, 0x9F,
19691+ 0x83, 0x1E, 0x57, 0xE9,
19692+
19693+ 0x38, 0x47, 0x38, 0xAF,
19694+ 0x34, 0x20,
19695+ 0x2A, 0x30,
19696+
19697+ 0x00, 0xE0,
19698+ 0x0D, 0x20,
19699+ 0x32, 0x20,
19700+ 0x05, 0x20,
19701+
19702+ 0x87, 0x80, 0x57, 0xE9,
19703+ 0x1F, 0x54, 0x57, 0x9F,
19704+
19705+ 0x17, 0x42, 0x56, 0x9F,
19706+ 0x00, 0xE0,
19707+ 0x3B, 0x6A,
19708+
19709+ 0x3F, 0x8F, 0x51, 0x9F,
19710+ 0x37, 0x1E, 0x4F, 0xE9,
19711+
19712+ 0x37, 0x32, 0x2A, 0xAF,
19713+ 0x00, 0xE0,
19714+ 0x32, 0x00,
19715+
19716+ 0x00, 0x80, 0x00, 0xE8,
19717+ 0x27, 0xC0, 0x44, 0xC0,
19718+
19719+ 0x36, 0x1F, 0x4F, 0xE9,
19720+ 0x1F, 0x1F, 0x26, 0xDF,
19721+
19722+ 0x37, 0x1B, 0x37, 0xBF,
19723+ 0x17, 0x26, 0x17, 0xDF,
19724+
19725+ 0x3E, 0x17, 0x4F, 0xE9,
19726+ 0x3F, 0x3F, 0x4F, 0xE9,
19727+
19728+ 0x34, 0x1F, 0x34, 0xAF,
19729+ 0x2B, 0x05,
19730+ 0xA7, 0x20,
19731+
19732+ 0x33, 0x2B, 0x37, 0xDF,
19733+ 0x27, 0x17, 0xC0, 0xAF,
19734+
19735+ 0x34, 0x80, 0x4F, 0xE9,
19736+ 0x00, 0x80, 0x00, 0xE8,
19737+
19738+ 0x2D, 0x21, 0x1A, 0xB0,
19739+ 0x25, 0x21, 0x31, 0xB0,
19740+
19741+ 0x0D, 0x21, 0x1A, 0xB2,
19742+ 0x05, 0x21, 0x31, 0xB2,
19743+
19744+ 0x03, 0x80, 0x2A, 0xEA,
19745+ 0x17, 0xC1, 0x2B, 0xBD,
19746+
19747+ 0x2D, 0x20,
19748+ 0x25, 0x20,
19749+ 0x05, 0x20,
19750+ 0x0D, 0x20,
19751+
19752+ 0xB3, 0x68,
19753+ 0x97, 0x25,
19754+ 0x00, 0x80, 0x00, 0xE8,
19755+
19756+ 0x33, 0xC0, 0x33, 0xAF,
19757+ 0x2F, 0xC0, 0x21, 0xC0,
19758+
19759+ 0x16, 0x42, 0x56, 0x9F,
19760+ 0x3C, 0x27, 0x4F, 0xE9,
19761+
19762+ 0x1E, 0x62, 0x57, 0x9F,
19763+ 0x00, 0x80, 0x00, 0xE8,
19764+
19765+ 0x25, 0x21, 0x31, 0xB4,
19766+ 0x2D, 0x21, 0x1A, 0xB4,
19767+
19768+ 0x3F, 0x2F, 0x5D, 0x9F,
19769+ 0x00, 0x80, 0x00, 0xE8,
19770+
19771+ 0x33, 0x05,
19772+ 0x00, 0xE0,
19773+ 0x28, 0x19, 0x60, 0xEC,
19774+
19775+ 0x0D, 0x21, 0x1A, 0xB6,
19776+ 0x05, 0x21, 0x31, 0xB6,
19777+
19778+ 0x37, 0x0F, 0x5C, 0x9F,
19779+ 0x00, 0xE0,
19780+ 0x2F, 0x20,
19781+
19782+ 0x23, 0x3B, 0x33, 0xAD,
19783+ 0x1E, 0x26, 0x1E, 0xDF,
19784+
19785+ 0xA7, 0x1E, 0x4F, 0xE9,
19786+ 0x17, 0x26, 0x16, 0xDF,
19787+
19788+ 0x2D, 0x20,
19789+ 0x00, 0xE0,
19790+ 0xA8, 0x3F, 0x4F, 0xE9,
19791+
19792+ 0x2F, 0x2F, 0x1E, 0xAF,
19793+ 0x25, 0x20,
19794+ 0x00, 0xE0,
19795+
19796+ 0xA4, 0x16, 0x4F, 0xE9,
19797+ 0x0F, 0xC0, 0x21, 0xC2,
19798+
19799+ 0xA6, 0x80, 0x4F, 0xE9,
19800+ 0x1F, 0x62, 0x57, 0x9F,
19801+
19802+ 0x0D, 0x20,
19803+ 0x05, 0x20,
19804+ 0x2F, 0xC0, 0x21, 0xC6,
19805+
19806+ 0x2D, 0x44, 0x4C, 0xB6,
19807+ 0x25, 0x44, 0x54, 0xB6,
19808+
19809+ 0x3F, 0x2F, 0x5D, 0x9F,
19810+ 0x00, 0xE0,
19811+ 0x0F, 0x20,
19812+
19813+ 0x2D, 0x20,
19814+ 0x25, 0x20,
19815+ 0x07, 0xC0, 0x44, 0xC6,
19816+
19817+ 0x17, 0x50, 0x56, 0x9F,
19818+ 0xA5, 0x37, 0x4F, 0xE9,
19819+
19820+ 0x06, 0xC0, 0x21, 0xC4,
19821+ 0x0F, 0x17, 0x0F, 0xAF,
19822+
19823+ 0x37, 0x0F, 0x5C, 0x9F,
19824+ 0x00, 0x80, 0x00, 0xE8,
19825+
19826+ 0x1E, 0x62, 0x57, 0x9F,
19827+ 0x00, 0x80, 0x00, 0xE8,
19828+
19829+ 0x3E, 0x3D, 0x5D, 0x9F,
19830+ 0x00, 0xE0,
19831+ 0x07, 0x20,
19832+
19833+ 0x2F, 0x20,
19834+ 0x00, 0xE0,
19835+ 0xA3, 0x0F, 0x4F, 0xE9,
19836+
19837+ 0x06, 0x20,
19838+ 0x00, 0xE0,
19839+ 0x1F, 0x26, 0x1F, 0xDF,
19840+
19841+ 0x17, 0x26, 0x17, 0xDF,
19842+ 0xA1, 0x1F, 0x4F, 0xE9,
19843+
19844+ 0x1E, 0x26, 0x1E, 0xDF,
19845+ 0x9D, 0x1E, 0x4F, 0xE9,
19846+
19847+ 0x35, 0x17, 0x4F, 0xE9,
19848+ 0xA2, 0x3F, 0x4F, 0xE9,
19849+
19850+ 0x06, 0x06, 0x1F, 0xAF,
19851+ 0x39, 0x37, 0x4F, 0xE9,
19852+
19853+ 0x2F, 0x2F, 0x17, 0xAF,
19854+ 0x07, 0x07, 0x1E, 0xAF,
19855+
19856+ 0xA0, 0x80, 0x4F, 0xE9,
19857+ 0x9E, 0x3E, 0x4F, 0xE9,
19858+
19859+ 0x31, 0x80, 0x4F, 0xE9,
19860+ 0x9C, 0x80, 0x4F, 0xE9,
19861+
19862+ 0x00, 0x80, 0x00, 0xE8,
19863+ 0x57, 0x39, 0x20, 0xE9,
19864+
19865+ 0x16, 0x28, 0x20, 0xE9,
19866+ 0x1D, 0x3B, 0x20, 0xE9,
19867+
19868+ 0x1E, 0x2B, 0x20, 0xE9,
19869+ 0x2B, 0x32, 0x20, 0xE9,
19870+
19871+ 0x1C, 0x23, 0x20, 0xE9,
19872+ 0x57, 0x36, 0x20, 0xE9,
19873+
19874+ 0x00, 0x80, 0xA0, 0xE9,
19875+ 0x40, 0x40, 0xD8, 0xEC,
19876+
19877+ 0xFF, 0x80, 0xC0, 0xE9,
19878+ 0x90, 0xE2,
19879+ 0x00, 0xE0,
19880+
19881+ 0x63, 0xFF, 0x20, 0xEA,
19882+ 0x19, 0xC8, 0xC1, 0xCD,
19883+
19884+ 0x1F, 0xD7, 0x18, 0xBD,
19885+ 0x3F, 0xD7, 0x22, 0xBD,
19886+
19887+ 0x9F, 0x41, 0x49, 0xBD,
19888+ 0x00, 0x80, 0x00, 0xE8,
19889+
19890+ 0x25, 0x41, 0x49, 0xBD,
19891+ 0x2D, 0x41, 0x51, 0xBD,
19892+
19893+ 0x0D, 0x80, 0x07, 0xEA,
19894+ 0x00, 0x80, 0x00, 0xE8,
19895+
19896+ 0x35, 0x40, 0x48, 0xBD,
19897+ 0x3D, 0x40, 0x50, 0xBD,
19898+
19899+ 0x00, 0x80, 0x00, 0xE8,
19900+ 0x25, 0x30,
19901+ 0x2D, 0x30,
19902+
19903+ 0x35, 0x30,
19904+ 0xB5, 0x30,
19905+ 0xBD, 0x30,
19906+ 0x3D, 0x30,
19907+
19908+ 0x9C, 0xA7, 0x5B, 0x9F,
19909+ 0x00, 0x80, 0x00, 0xE8,
19910+
19911+ 0x00, 0x80, 0x00, 0xE8,
19912+ 0x00, 0x80, 0x00, 0xE8,
19913+
19914+ 0x00, 0x80, 0x00, 0xE8,
19915+ 0x00, 0x80, 0x00, 0xE8,
19916+
19917+ 0x00, 0x80, 0x00, 0xE8,
19918+ 0x00, 0x80, 0x00, 0xE8,
19919+
19920+ 0x00, 0x80, 0x00, 0xE8,
19921+ 0x00, 0x80, 0x00, 0xE8,
19922+
19923+ 0x62, 0xFF, 0x0A, 0xEA,
19924+ 0x00, 0x80, 0x00, 0xE8,
19925+
19926+ 0xC9, 0x41, 0xC8, 0xEC,
19927+ 0x42, 0xE1,
19928+ 0x00, 0xE0,
19929+
19930+ 0x60, 0xFF, 0x20, 0xEA,
19931+ 0x00, 0x80, 0x00, 0xE8,
19932+
19933+ 0x00, 0x80, 0x00, 0xE8,
19934+ 0x00, 0x80, 0x00, 0xE8,
19935+
19936+ 0xC8, 0x40, 0xC0, 0xEC,
19937+ 0x00, 0x80, 0x00, 0xE8,
19938+
19939+ 0x5D, 0xFF, 0x20, 0xEA,
19940+ 0x00, 0x80, 0x00, 0xE8,
19941+
19942+ 0x00, 0x80, 0x00, 0xE8,
19943+ 0x00, 0x80, 0x00, 0xE8,
19944+
19945+};
19946+
19947+static unsigned char warp_g200_tgzsf[] = {
19948+
19949+ 0x00, 0x80, 0x00, 0xE8,
19950+ 0x00, 0x80, 0x00, 0xE8,
19951+
19952+ 0x00, 0x80, 0x00, 0xE8,
19953+ 0x00, 0x80, 0x00, 0xE8,
19954+
19955+ 0x00, 0x80, 0x00, 0xE8,
19956+ 0x00, 0x80, 0x00, 0xE8,
19957+
19958+ 0x00, 0x80, 0x00, 0xE8,
19959+ 0x00, 0x80, 0x00, 0xE8,
19960+
19961+ 0x00, 0x80, 0x00, 0xE8,
19962+ 0x00, 0x80, 0x00, 0xE8,
19963+
19964+ 0x00, 0x80, 0x00, 0xE8,
19965+ 0x00, 0x80, 0x00, 0xE8,
19966+
19967+ 0x00, 0x80, 0x00, 0xE8,
19968+ 0x00, 0x80, 0x00, 0xE8,
19969+
19970+ 0x00, 0x80, 0x00, 0xE8,
19971+ 0x00, 0x80, 0x00, 0xE8,
19972+
19973+ 0x00, 0x80, 0x00, 0xE8,
19974+ 0x00, 0x80, 0x00, 0xE8,
19975+
19976+ 0x00, 0x80, 0x00, 0xE8,
19977+ 0x00, 0x80, 0x00, 0xE8,
19978+
19979+ 0x00, 0x80, 0x00, 0xE8,
19980+ 0x00, 0x80, 0x00, 0xE8,
19981+
19982+ 0x00, 0x80, 0x00, 0xE8,
19983+ 0x00, 0x80, 0x00, 0xE8,
19984+
19985+ 0x00, 0x80, 0x00, 0xE8,
19986+ 0x00, 0x80, 0x00, 0xE8,
19987+
19988+ 0x00, 0x98, 0xA0, 0xE9,
19989+ 0x40, 0x40, 0xD8, 0xEC,
19990+
19991+ 0xFF, 0x80, 0xC0, 0xE9,
19992+ 0x00, 0x80, 0x00, 0xE8,
19993+
19994+ 0x1F, 0xD7, 0x18, 0xBD,
19995+ 0x3F, 0xD7, 0x22, 0xBD,
19996+
19997+ 0x81, 0x04,
19998+ 0x89, 0x04,
19999+ 0x01, 0x04,
20000+ 0x09, 0x04,
20001+
20002+ 0xC9, 0x41, 0xC0, 0xEC,
20003+ 0x11, 0x04,
20004+ 0x00, 0xE0,
20005+
20006+ 0x41, 0xCC, 0x41, 0xCD,
20007+ 0x49, 0xCC, 0x49, 0xCD,
20008+
20009+ 0xD1, 0x41, 0xC0, 0xEC,
20010+ 0x51, 0xCC, 0x51, 0xCD,
20011+
20012+ 0x80, 0x04,
20013+ 0x10, 0x04,
20014+ 0x08, 0x04,
20015+ 0x00, 0xE0,
20016+
20017+ 0x00, 0xCC, 0xC0, 0xCD,
20018+ 0xD1, 0x49, 0xC0, 0xEC,
20019+
20020+ 0x8A, 0x1F, 0x20, 0xE9,
20021+ 0x8B, 0x3F, 0x20, 0xE9,
20022+
20023+ 0x41, 0x3C, 0x41, 0xAD,
20024+ 0x49, 0x3C, 0x49, 0xAD,
20025+
20026+ 0x10, 0xCC, 0x10, 0xCD,
20027+ 0x08, 0xCC, 0x08, 0xCD,
20028+
20029+ 0xB9, 0x41, 0x49, 0xBB,
20030+ 0x1F, 0xF0, 0x41, 0xCD,
20031+
20032+ 0x51, 0x3C, 0x51, 0xAD,
20033+ 0x00, 0x98, 0x80, 0xE9,
20034+
20035+ 0x8F, 0x80, 0x07, 0xEA,
20036+ 0x24, 0x1F, 0x20, 0xE9,
20037+
20038+ 0x21, 0x45, 0x80, 0xE8,
20039+ 0x1A, 0x4D, 0x80, 0xE8,
20040+
20041+ 0x31, 0x55, 0x80, 0xE8,
20042+ 0x00, 0x80, 0x00, 0xE8,
20043+
20044+ 0x15, 0x41, 0x49, 0xBD,
20045+ 0x1D, 0x41, 0x51, 0xBD,
20046+
20047+ 0x2E, 0x41, 0x2A, 0xB8,
20048+ 0x34, 0x53, 0xA0, 0xE8,
20049+
20050+ 0x15, 0x30,
20051+ 0x1D, 0x30,
20052+ 0x58, 0xE3,
20053+ 0x00, 0xE0,
20054+
20055+ 0xB5, 0x40, 0x48, 0xBD,
20056+ 0x3D, 0x40, 0x50, 0xBD,
20057+
20058+ 0x24, 0x43, 0xA0, 0xE8,
20059+ 0x2C, 0x4B, 0xA0, 0xE8,
20060+
20061+ 0x15, 0x72,
20062+ 0x09, 0xE3,
20063+ 0x00, 0xE0,
20064+ 0x1D, 0x72,
20065+
20066+ 0x35, 0x30,
20067+ 0xB5, 0x30,
20068+ 0xBD, 0x30,
20069+ 0x3D, 0x30,
20070+
20071+ 0x9C, 0x97, 0x57, 0x9F,
20072+ 0x00, 0x80, 0x00, 0xE8,
20073+
20074+ 0x6C, 0x64, 0xC8, 0xEC,
20075+ 0x98, 0xE1,
20076+ 0xB5, 0x05,
20077+
20078+ 0xBD, 0x05,
20079+ 0x2E, 0x30,
20080+ 0x32, 0xC0, 0xA0, 0xE8,
20081+
20082+ 0x33, 0xC0, 0xA0, 0xE8,
20083+ 0x74, 0x64, 0xC8, 0xEC,
20084+
20085+ 0x40, 0x3C, 0x40, 0xAD,
20086+ 0x32, 0x6A,
20087+ 0x2A, 0x30,
20088+
20089+ 0x20, 0x73,
20090+ 0x33, 0x6A,
20091+ 0x00, 0xE0,
20092+ 0x28, 0x73,
20093+
20094+ 0x1C, 0x72,
20095+ 0x83, 0xE2,
20096+ 0x7B, 0x80, 0x15, 0xEA,
20097+
20098+ 0xB8, 0x3D, 0x28, 0xDF,
20099+ 0x30, 0x35, 0x20, 0xDF,
20100+
20101+ 0x40, 0x30,
20102+ 0x00, 0xE0,
20103+ 0xCC, 0xE2,
20104+ 0x64, 0x72,
20105+
20106+ 0x25, 0x42, 0x52, 0xBF,
20107+ 0x2D, 0x42, 0x4A, 0xBF,
20108+
20109+ 0x30, 0x2E, 0x30, 0xDF,
20110+ 0x38, 0x2E, 0x38, 0xDF,
20111+
20112+ 0x18, 0x1D, 0x45, 0xE9,
20113+ 0x1E, 0x15, 0x45, 0xE9,
20114+
20115+ 0x2B, 0x49, 0x51, 0xBD,
20116+ 0x00, 0xE0,
20117+ 0x1F, 0x73,
20118+
20119+ 0x38, 0x38, 0x40, 0xAF,
20120+ 0x30, 0x30, 0x40, 0xAF,
20121+
20122+ 0x24, 0x1F, 0x24, 0xDF,
20123+ 0x1D, 0x32, 0x20, 0xE9,
20124+
20125+ 0x2C, 0x1F, 0x2C, 0xDF,
20126+ 0x1A, 0x33, 0x20, 0xE9,
20127+
20128+ 0xB0, 0x10,
20129+ 0x08, 0xE3,
20130+ 0x40, 0x10,
20131+ 0xB8, 0x10,
20132+
20133+ 0x26, 0xF0, 0x30, 0xCD,
20134+ 0x2F, 0xF0, 0x38, 0xCD,
20135+
20136+ 0x2B, 0x80, 0x20, 0xE9,
20137+ 0x2A, 0x80, 0x20, 0xE9,
20138+
20139+ 0xA6, 0x20,
20140+ 0x88, 0xE2,
20141+ 0x00, 0xE0,
20142+ 0xAF, 0x20,
20143+
20144+ 0x28, 0x2A, 0x26, 0xAF,
20145+ 0x20, 0x2A, 0xC0, 0xAF,
20146+
20147+ 0x34, 0x1F, 0x34, 0xDF,
20148+ 0x46, 0x24, 0x46, 0xDF,
20149+
20150+ 0x28, 0x30, 0x80, 0xBF,
20151+ 0x20, 0x38, 0x80, 0xBF,
20152+
20153+ 0x47, 0x24, 0x47, 0xDF,
20154+ 0x4E, 0x2C, 0x4E, 0xDF,
20155+
20156+ 0x4F, 0x2C, 0x4F, 0xDF,
20157+ 0x56, 0x34, 0x56, 0xDF,
20158+
20159+ 0x28, 0x15, 0x28, 0xDF,
20160+ 0x20, 0x1D, 0x20, 0xDF,
20161+
20162+ 0x57, 0x34, 0x57, 0xDF,
20163+ 0x00, 0xE0,
20164+ 0x1D, 0x05,
20165+
20166+ 0x04, 0x80, 0x10, 0xEA,
20167+ 0x89, 0xE2,
20168+ 0x2B, 0x30,
20169+
20170+ 0x3F, 0xC1, 0x1D, 0xBD,
20171+ 0x00, 0x80, 0x00, 0xE8,
20172+
20173+ 0x00, 0x80, 0x00, 0xE8,
20174+ 0x00, 0x80, 0x00, 0xE8,
20175+
20176+ 0xA0, 0x68,
20177+ 0xBF, 0x25,
20178+ 0x00, 0x80, 0x00, 0xE8,
20179+
20180+ 0x20, 0xC0, 0x20, 0xAF,
20181+ 0x28, 0x05,
20182+ 0x97, 0x74,
20183+
20184+ 0x00, 0xE0,
20185+ 0x2A, 0x10,
20186+ 0x16, 0xC0, 0x20, 0xE9,
20187+
20188+ 0x04, 0x80, 0x10, 0xEA,
20189+ 0x8C, 0xE2,
20190+ 0x95, 0x05,
20191+
20192+ 0x28, 0xC1, 0x28, 0xAD,
20193+ 0x1F, 0xC1, 0x15, 0xBD,
20194+
20195+ 0x00, 0x80, 0x00, 0xE8,
20196+ 0x00, 0x80, 0x00, 0xE8,
20197+
20198+ 0xA8, 0x67,
20199+ 0x9F, 0x6B,
20200+ 0x00, 0x80, 0x00, 0xE8,
20201+
20202+ 0x28, 0xC0, 0x28, 0xAD,
20203+ 0x1D, 0x25,
20204+ 0x20, 0x05,
20205+
20206+ 0x28, 0x32, 0x80, 0xAD,
20207+ 0x40, 0x2A, 0x40, 0xBD,
20208+
20209+ 0x1C, 0x80, 0x20, 0xE9,
20210+ 0x20, 0x33, 0x20, 0xAD,
20211+
20212+ 0x20, 0x73,
20213+ 0x00, 0xE0,
20214+ 0xB6, 0x49, 0x51, 0xBB,
20215+
20216+ 0x26, 0x2F, 0xB0, 0xE8,
20217+ 0x19, 0x20, 0x20, 0xE9,
20218+
20219+ 0x35, 0x20, 0x35, 0xDF,
20220+ 0x3D, 0x20, 0x3D, 0xDF,
20221+
20222+ 0x15, 0x20, 0x15, 0xDF,
20223+ 0x1D, 0x20, 0x1D, 0xDF,
20224+
20225+ 0x26, 0xD0, 0x26, 0xCD,
20226+ 0x29, 0x49, 0x2A, 0xB8,
20227+
20228+ 0x26, 0x40, 0x80, 0xBD,
20229+ 0x3B, 0x48, 0x50, 0xBD,
20230+
20231+ 0x3E, 0x54, 0x57, 0x9F,
20232+ 0x00, 0xE0,
20233+ 0x82, 0xE1,
20234+
20235+ 0x1E, 0xAF, 0x59, 0x9F,
20236+ 0x00, 0x80, 0x00, 0xE8,
20237+
20238+ 0x26, 0x30,
20239+ 0x29, 0x30,
20240+ 0x48, 0x3C, 0x48, 0xAD,
20241+
20242+ 0x2B, 0x72,
20243+ 0xC2, 0xE1,
20244+ 0x2C, 0xC0, 0x44, 0xC2,
20245+
20246+ 0x05, 0x24, 0x34, 0xBF,
20247+ 0x0D, 0x24, 0x2C, 0xBF,
20248+
20249+ 0x2D, 0x46, 0x4E, 0xBF,
20250+ 0x25, 0x46, 0x56, 0xBF,
20251+
20252+ 0x20, 0x1D, 0x6F, 0x8F,
20253+ 0x32, 0x3E, 0x5F, 0xE9,
20254+
20255+ 0x3E, 0x50, 0x56, 0x9F,
20256+ 0x00, 0xE0,
20257+ 0x3B, 0x30,
20258+
20259+ 0x1E, 0x8F, 0x51, 0x9F,
20260+ 0x33, 0x1E, 0x5F, 0xE9,
20261+
20262+ 0x05, 0x44, 0x54, 0xB2,
20263+ 0x0D, 0x44, 0x4C, 0xB2,
20264+
20265+ 0x19, 0xC0, 0xB0, 0xE8,
20266+ 0x34, 0xC0, 0x44, 0xC4,
20267+
20268+ 0x33, 0x73,
20269+ 0x00, 0xE0,
20270+ 0x3E, 0x62, 0x57, 0x9F,
20271+
20272+ 0x1E, 0xAF, 0x59, 0x9F,
20273+ 0x00, 0xE0,
20274+ 0x0D, 0x20,
20275+
20276+ 0x84, 0x3E, 0x58, 0xE9,
20277+ 0x28, 0x1D, 0x6F, 0x8F,
20278+
20279+ 0x05, 0x20,
20280+ 0x00, 0xE0,
20281+ 0x85, 0x1E, 0x58, 0xE9,
20282+
20283+ 0x9B, 0x3B, 0x33, 0xDF,
20284+ 0x20, 0x20, 0x42, 0xAF,
20285+
20286+ 0x30, 0x42, 0x56, 0x9F,
20287+ 0x80, 0x3E, 0x57, 0xE9,
20288+
20289+ 0x3F, 0x8F, 0x51, 0x9F,
20290+ 0x30, 0x80, 0x5F, 0xE9,
20291+
20292+ 0x28, 0x28, 0x24, 0xAF,
20293+ 0x81, 0x1E, 0x57, 0xE9,
20294+
20295+ 0x05, 0x47, 0x57, 0xBF,
20296+ 0x0D, 0x47, 0x4F, 0xBF,
20297+
20298+ 0x88, 0x80, 0x58, 0xE9,
20299+ 0x1B, 0x29, 0x1B, 0xDF,
20300+
20301+ 0x30, 0x1D, 0x6F, 0x8F,
20302+ 0x3A, 0x30, 0x4F, 0xE9,
20303+
20304+ 0x1C, 0x30, 0x26, 0xDF,
20305+ 0x09, 0xE3,
20306+ 0x3B, 0x05,
20307+
20308+ 0x3E, 0x50, 0x56, 0x9F,
20309+ 0x3B, 0x3F, 0x4F, 0xE9,
20310+
20311+ 0x1E, 0x8F, 0x51, 0x9F,
20312+ 0x00, 0xE0,
20313+ 0xAC, 0x20,
20314+
20315+ 0x2D, 0x44, 0x4C, 0xB4,
20316+ 0x2C, 0x1C, 0xC0, 0xAF,
20317+
20318+ 0x25, 0x44, 0x54, 0xB4,
20319+ 0x00, 0xE0,
20320+ 0xC8, 0x30,
20321+
20322+ 0x30, 0x46, 0x30, 0xAF,
20323+ 0x1B, 0x1B, 0x48, 0xAF,
20324+
20325+ 0x00, 0xE0,
20326+ 0x25, 0x20,
20327+ 0x38, 0x2C, 0x4F, 0xE9,
20328+
20329+ 0x86, 0x80, 0x57, 0xE9,
20330+ 0x38, 0x1D, 0x6F, 0x8F,
20331+
20332+ 0x28, 0x74,
20333+ 0x00, 0xE0,
20334+ 0x0D, 0x44, 0x4C, 0xB0,
20335+
20336+ 0x05, 0x44, 0x54, 0xB0,
20337+ 0x2D, 0x20,
20338+ 0x9B, 0x10,
20339+
20340+ 0x82, 0x3E, 0x57, 0xE9,
20341+ 0x32, 0xF0, 0x1B, 0xCD,
20342+
20343+ 0x1E, 0xBD, 0x59, 0x9F,
20344+ 0x83, 0x1E, 0x57, 0xE9,
20345+
20346+ 0x38, 0x47, 0x38, 0xAF,
20347+ 0x34, 0x20,
20348+ 0x2A, 0x30,
20349+
20350+ 0x00, 0xE0,
20351+ 0x0D, 0x20,
20352+ 0x32, 0x20,
20353+ 0x05, 0x20,
20354+
20355+ 0x87, 0x80, 0x57, 0xE9,
20356+ 0x1F, 0x54, 0x57, 0x9F,
20357+
20358+ 0x17, 0x42, 0x56, 0x9F,
20359+ 0x00, 0xE0,
20360+ 0x3B, 0x6A,
20361+
20362+ 0x3F, 0x8F, 0x51, 0x9F,
20363+ 0x37, 0x1E, 0x4F, 0xE9,
20364+
20365+ 0x37, 0x32, 0x2A, 0xAF,
20366+ 0x00, 0xE0,
20367+ 0x32, 0x00,
20368+
20369+ 0x00, 0x80, 0x00, 0xE8,
20370+ 0x27, 0xC0, 0x44, 0xC0,
20371+
20372+ 0x36, 0x1F, 0x4F, 0xE9,
20373+ 0x1F, 0x1F, 0x26, 0xDF,
20374+
20375+ 0x37, 0x1B, 0x37, 0xBF,
20376+ 0x17, 0x26, 0x17, 0xDF,
20377+
20378+ 0x3E, 0x17, 0x4F, 0xE9,
20379+ 0x3F, 0x3F, 0x4F, 0xE9,
20380+
20381+ 0x34, 0x1F, 0x34, 0xAF,
20382+ 0x2B, 0x05,
20383+ 0xA7, 0x20,
20384+
20385+ 0x33, 0x2B, 0x37, 0xDF,
20386+ 0x27, 0x17, 0xC0, 0xAF,
20387+
20388+ 0x34, 0x80, 0x4F, 0xE9,
20389+ 0x00, 0x80, 0x00, 0xE8,
20390+
20391+ 0x2D, 0x21, 0x1A, 0xB0,
20392+ 0x25, 0x21, 0x31, 0xB0,
20393+
20394+ 0x0D, 0x21, 0x1A, 0xB2,
20395+ 0x05, 0x21, 0x31, 0xB2,
20396+
20397+ 0x03, 0x80, 0x2A, 0xEA,
20398+ 0x17, 0xC1, 0x2B, 0xBD,
20399+
20400+ 0x2D, 0x20,
20401+ 0x25, 0x20,
20402+ 0x05, 0x20,
20403+ 0x0D, 0x20,
20404+
20405+ 0xB3, 0x68,
20406+ 0x97, 0x25,
20407+ 0x00, 0x80, 0x00, 0xE8,
20408+
20409+ 0x33, 0xC0, 0x33, 0xAF,
20410+ 0x2F, 0xC0, 0x21, 0xC0,
20411+
20412+ 0x16, 0x42, 0x56, 0x9F,
20413+ 0x3C, 0x27, 0x4F, 0xE9,
20414+
20415+ 0x1E, 0x62, 0x57, 0x9F,
20416+ 0x00, 0x80, 0x00, 0xE8,
20417+
20418+ 0x25, 0x21, 0x31, 0xB4,
20419+ 0x2D, 0x21, 0x1A, 0xB4,
20420+
20421+ 0x3F, 0x2F, 0x5D, 0x9F,
20422+ 0x00, 0x80, 0x00, 0xE8,
20423+
20424+ 0x33, 0x05,
20425+ 0x00, 0xE0,
20426+ 0x28, 0x19, 0x60, 0xEC,
20427+
20428+ 0x0D, 0x21, 0x1A, 0xB6,
20429+ 0x05, 0x21, 0x31, 0xB6,
20430+
20431+ 0x37, 0x0F, 0x5C, 0x9F,
20432+ 0x00, 0xE0,
20433+ 0x2F, 0x20,
20434+
20435+ 0x23, 0x3B, 0x33, 0xAD,
20436+ 0x1E, 0x26, 0x1E, 0xDF,
20437+
20438+ 0xA7, 0x1E, 0x4F, 0xE9,
20439+ 0x17, 0x26, 0x16, 0xDF,
20440+
20441+ 0x2D, 0x20,
20442+ 0x00, 0xE0,
20443+ 0xA8, 0x3F, 0x4F, 0xE9,
20444+
20445+ 0x2F, 0x2F, 0x1E, 0xAF,
20446+ 0x25, 0x20,
20447+ 0x00, 0xE0,
20448+
20449+ 0xA4, 0x16, 0x4F, 0xE9,
20450+ 0x0F, 0xC0, 0x21, 0xC2,
20451+
20452+ 0xA6, 0x80, 0x4F, 0xE9,
20453+ 0x1F, 0x62, 0x57, 0x9F,
20454+
20455+ 0x0D, 0x20,
20456+ 0x05, 0x20,
20457+ 0x2F, 0xC0, 0x21, 0xC6,
20458+
20459+ 0x3F, 0x2F, 0x5D, 0x9F,
20460+ 0x00, 0xE0,
20461+ 0x0F, 0x20,
20462+
20463+ 0x17, 0x50, 0x56, 0x9F,
20464+ 0xA5, 0x37, 0x4F, 0xE9,
20465+
20466+ 0x06, 0xC0, 0x21, 0xC4,
20467+ 0x0F, 0x17, 0x0F, 0xAF,
20468+
20469+ 0x37, 0x0F, 0x5C, 0x9F,
20470+ 0x00, 0x80, 0x00, 0xE8,
20471+
20472+ 0x2F, 0x20,
20473+ 0x00, 0xE0,
20474+ 0xA3, 0x80, 0x4F, 0xE9,
20475+
20476+ 0x06, 0x20,
20477+ 0x00, 0xE0,
20478+ 0x1F, 0x26, 0x1F, 0xDF,
20479+
20480+ 0x17, 0x26, 0x17, 0xDF,
20481+ 0x35, 0x17, 0x4F, 0xE9,
20482+
20483+ 0xA1, 0x1F, 0x4F, 0xE9,
20484+ 0xA2, 0x3F, 0x4F, 0xE9,
20485+
20486+ 0x06, 0x06, 0x1F, 0xAF,
20487+ 0x39, 0x37, 0x4F, 0xE9,
20488+
20489+ 0x2F, 0x2F, 0x17, 0xAF,
20490+ 0x00, 0x80, 0x00, 0xE8,
20491+
20492+ 0xA0, 0x80, 0x4F, 0xE9,
20493+ 0x00, 0x80, 0x00, 0xE8,
20494+
20495+ 0x31, 0x80, 0x4F, 0xE9,
20496+ 0x00, 0x80, 0x00, 0xE8,
20497+
20498+ 0x00, 0x80, 0x00, 0xE8,
20499+ 0x57, 0x39, 0x20, 0xE9,
20500+
20501+ 0x16, 0x28, 0x20, 0xE9,
20502+ 0x1D, 0x3B, 0x20, 0xE9,
20503+
20504+ 0x1E, 0x2B, 0x20, 0xE9,
20505+ 0x2B, 0x32, 0x20, 0xE9,
20506+
20507+ 0x1C, 0x23, 0x20, 0xE9,
20508+ 0x57, 0x36, 0x20, 0xE9,
20509+
20510+ 0x00, 0x80, 0xA0, 0xE9,
20511+ 0x40, 0x40, 0xD8, 0xEC,
20512+
20513+ 0xFF, 0x80, 0xC0, 0xE9,
20514+ 0x90, 0xE2,
20515+ 0x00, 0xE0,
20516+
20517+ 0x68, 0xFF, 0x20, 0xEA,
20518+ 0x19, 0xC8, 0xC1, 0xCD,
20519+
20520+ 0x1F, 0xD7, 0x18, 0xBD,
20521+ 0x3F, 0xD7, 0x22, 0xBD,
20522+
20523+ 0x9F, 0x41, 0x49, 0xBD,
20524+ 0x00, 0x80, 0x00, 0xE8,
20525+
20526+ 0x25, 0x41, 0x49, 0xBD,
20527+ 0x2D, 0x41, 0x51, 0xBD,
20528+
20529+ 0x0D, 0x80, 0x07, 0xEA,
20530+ 0x00, 0x80, 0x00, 0xE8,
20531+
20532+ 0x35, 0x40, 0x48, 0xBD,
20533+ 0x3D, 0x40, 0x50, 0xBD,
20534+
20535+ 0x00, 0x80, 0x00, 0xE8,
20536+ 0x25, 0x30,
20537+ 0x2D, 0x30,
20538+
20539+ 0x35, 0x30,
20540+ 0xB5, 0x30,
20541+ 0xBD, 0x30,
20542+ 0x3D, 0x30,
20543+
20544+ 0x9C, 0xA7, 0x5B, 0x9F,
20545+ 0x00, 0x80, 0x00, 0xE8,
20546+
20547+ 0x00, 0x80, 0x00, 0xE8,
20548+ 0x00, 0x80, 0x00, 0xE8,
20549+
20550+ 0x00, 0x80, 0x00, 0xE8,
20551+ 0x00, 0x80, 0x00, 0xE8,
20552+
20553+ 0x00, 0x80, 0x00, 0xE8,
20554+ 0x00, 0x80, 0x00, 0xE8,
20555+
20556+ 0x00, 0x80, 0x00, 0xE8,
20557+ 0x00, 0x80, 0x00, 0xE8,
20558+
20559+ 0x67, 0xFF, 0x0A, 0xEA,
20560+ 0x00, 0x80, 0x00, 0xE8,
20561+
20562+ 0xC9, 0x41, 0xC8, 0xEC,
20563+ 0x42, 0xE1,
20564+ 0x00, 0xE0,
20565+
20566+ 0x65, 0xFF, 0x20, 0xEA,
20567+ 0x00, 0x80, 0x00, 0xE8,
20568+
20569+ 0x00, 0x80, 0x00, 0xE8,
20570+ 0x00, 0x80, 0x00, 0xE8,
20571+
20572+ 0xC8, 0x40, 0xC0, 0xEC,
20573+ 0x00, 0x80, 0x00, 0xE8,
20574+
20575+ 0x62, 0xFF, 0x20, 0xEA,
20576+ 0x00, 0x80, 0x00, 0xE8,
20577+
20578+ 0x00, 0x80, 0x00, 0xE8,
20579+ 0x00, 0x80, 0x00, 0xE8,
20580+
20581+};
20582+
20583+static unsigned char warp_g400_t2gz[] = {
20584+
20585+ 0x00, 0x8A, 0x98, 0xE9,
20586+ 0x00, 0x80, 0x00, 0xE8,
20587+
20588+ 0x00, 0x80, 0xA0, 0xE9,
20589+ 0x00, 0x00, 0xD8, 0xEC,
20590+
20591+ 0xFF, 0x80, 0xC0, 0xE9,
20592+ 0x00, 0x80, 0x00, 0xE8,
20593+
20594+ 0x0A, 0x40, 0x50, 0xBF,
20595+ 0x2A, 0x40, 0x60, 0xBF,
20596+
20597+ 0x32, 0x41, 0x51, 0xBF,
20598+ 0x3A, 0x41, 0x61, 0xBF,
20599+
20600+ 0xC3, 0x6B,
20601+ 0xD3, 0x6B,
20602+ 0x00, 0x8A, 0x98, 0xE9,
20603+
20604+ 0x73, 0x7B, 0xC8, 0xEC,
20605+ 0x96, 0xE2,
20606+ 0x41, 0x04,
20607+
20608+ 0x7B, 0x43, 0xA0, 0xE8,
20609+ 0x73, 0x53, 0xA0, 0xE8,
20610+
20611+ 0xAD, 0xEE, 0x23, 0x9F,
20612+ 0x00, 0xE0,
20613+ 0x51, 0x04,
20614+
20615+ 0x90, 0xE2,
20616+ 0x61, 0x04,
20617+ 0x31, 0x46, 0xB1, 0xE8,
20618+
20619+ 0x51, 0x41, 0xE0, 0xEC,
20620+ 0x39, 0x67, 0xB1, 0xE8,
20621+
20622+ 0x00, 0x04,
20623+ 0x46, 0xE2,
20624+ 0x73, 0x63, 0xA0, 0xE8,
20625+
20626+ 0x61, 0x41, 0xE0, 0xEC,
20627+ 0x31, 0x00,
20628+ 0x39, 0x00,
20629+
20630+ 0x78, 0x80, 0x15, 0xEA,
20631+ 0x10, 0x04,
20632+ 0x20, 0x04,
20633+
20634+ 0x61, 0x51, 0xE0, 0xEC,
20635+ 0x2F, 0x41, 0x60, 0xEA,
20636+
20637+ 0x31, 0x20,
20638+ 0x39, 0x20,
20639+ 0x1F, 0x42, 0xA0, 0xE8,
20640+
20641+ 0x2A, 0x42, 0x52, 0xBF,
20642+ 0x0F, 0x52, 0xA0, 0xE8,
20643+
20644+ 0x1A, 0x42, 0x62, 0xBF,
20645+ 0x1E, 0x51, 0x60, 0xEA,
20646+
20647+ 0x73, 0x7B, 0xC8, 0xEC,
20648+ 0x0E, 0x61, 0x60, 0xEA,
20649+
20650+ 0x32, 0x40, 0x50, 0xBD,
20651+ 0x22, 0x40, 0x60, 0xBD,
20652+
20653+ 0x12, 0x41, 0x51, 0xBD,
20654+ 0x3A, 0x41, 0x61, 0xBD,
20655+
20656+ 0xBF, 0x2F, 0x0E, 0xBD,
20657+ 0x97, 0xE2,
20658+ 0x7B, 0x72,
20659+
20660+ 0x32, 0x20,
20661+ 0x22, 0x20,
20662+ 0x12, 0x20,
20663+ 0x3A, 0x20,
20664+
20665+ 0x35, 0x48, 0xB1, 0xE8,
20666+ 0x3D, 0x59, 0xB1, 0xE8,
20667+
20668+ 0x46, 0x31, 0x46, 0xBF,
20669+ 0x56, 0x31, 0x56, 0xBF,
20670+
20671+ 0xB3, 0xE2, 0x2D, 0x9F,
20672+ 0x00, 0x80, 0x00, 0xE8,
20673+
20674+ 0x66, 0x31, 0x66, 0xBF,
20675+ 0x47, 0x39, 0x47, 0xBF,
20676+
20677+ 0x57, 0x39, 0x57, 0xBF,
20678+ 0x67, 0x39, 0x67, 0xBF,
20679+
20680+ 0x69, 0x80, 0x07, 0xEA,
20681+ 0x24, 0x41, 0x20, 0xE9,
20682+
20683+ 0x35, 0x00,
20684+ 0x3D, 0x00,
20685+ 0x00, 0xE0,
20686+ 0x2D, 0x73,
20687+
20688+ 0x33, 0x72,
20689+ 0x0C, 0xE3,
20690+ 0x8D, 0x2F, 0x1E, 0xBD,
20691+
20692+ 0x43, 0x75, 0xF8, 0xEC,
20693+ 0x35, 0x20,
20694+ 0x3D, 0x20,
20695+
20696+ 0x43, 0x43, 0x2D, 0xDF,
20697+ 0x53, 0x53, 0x2D, 0xDF,
20698+
20699+ 0xAE, 0x1E, 0x0E, 0xBD,
20700+ 0x58, 0xE3,
20701+ 0x33, 0x66,
20702+
20703+ 0x48, 0x35, 0x48, 0xBF,
20704+ 0x58, 0x35, 0x58, 0xBF,
20705+
20706+ 0x68, 0x35, 0x68, 0xBF,
20707+ 0x49, 0x3D, 0x49, 0xBF,
20708+
20709+ 0x59, 0x3D, 0x59, 0xBF,
20710+ 0x69, 0x3D, 0x69, 0xBF,
20711+
20712+ 0x63, 0x63, 0x2D, 0xDF,
20713+ 0x4D, 0x7D, 0xF8, 0xEC,
20714+
20715+ 0x59, 0xE3,
20716+ 0x00, 0xE0,
20717+ 0xB8, 0x38, 0x33, 0xBF,
20718+
20719+ 0x2D, 0x73,
20720+ 0x30, 0x76,
20721+ 0x18, 0x3A, 0x41, 0xE9,
20722+
20723+ 0x3F, 0x53, 0xA0, 0xE8,
20724+ 0x05, 0x80, 0x3D, 0xEA,
20725+
20726+ 0x37, 0x43, 0xA0, 0xE8,
20727+ 0x3D, 0x63, 0xA0, 0xE8,
20728+
20729+ 0x50, 0x70, 0xF8, 0xEC,
20730+ 0x2B, 0x50, 0x3C, 0xE9,
20731+
20732+ 0x1F, 0x0F, 0xBC, 0xE8,
20733+ 0x00, 0x80, 0x00, 0xE8,
20734+
20735+ 0x59, 0x78, 0xF8, 0xEC,
20736+ 0x00, 0x80, 0x00, 0xE8,
20737+
20738+ 0x15, 0xC0, 0x20, 0xE9,
20739+ 0x15, 0xC0, 0x20, 0xE9,
20740+
20741+ 0x15, 0xC0, 0x20, 0xE9,
20742+ 0x15, 0xC0, 0x20, 0xE9,
20743+
20744+ 0x1E, 0x12, 0x41, 0xE9,
20745+ 0x1A, 0x22, 0x41, 0xE9,
20746+
20747+ 0x46, 0x37, 0x46, 0xDF,
20748+ 0x56, 0x3F, 0x56, 0xDF,
20749+
20750+ 0x2B, 0x40, 0x3D, 0xE9,
20751+ 0x66, 0x3D, 0x66, 0xDF,
20752+
20753+ 0x1D, 0x32, 0x41, 0xE9,
20754+ 0x67, 0x3D, 0x67, 0xDF,
20755+
20756+ 0x47, 0x37, 0x47, 0xDF,
20757+ 0x57, 0x3F, 0x57, 0xDF,
20758+
20759+ 0x2A, 0x40, 0x20, 0xE9,
20760+ 0x59, 0x3F, 0x59, 0xDF,
20761+
20762+ 0x16, 0x30, 0x20, 0xE9,
20763+ 0x69, 0x3D, 0x69, 0xDF,
20764+
20765+ 0x48, 0x37, 0x48, 0xDF,
20766+ 0x58, 0x3F, 0x58, 0xDF,
20767+
20768+ 0x12, 0x12, 0x2D, 0xDF,
20769+ 0x22, 0x22, 0x2D, 0xDF,
20770+
20771+ 0x32, 0x32, 0x2D, 0xDF,
20772+ 0x3A, 0x3A, 0x2D, 0xDF,
20773+
20774+ 0x68, 0x3D, 0x68, 0xDF,
20775+ 0x49, 0x37, 0x49, 0xDF,
20776+
20777+ 0x3D, 0xCF, 0x74, 0xC0,
20778+ 0x37, 0xCF, 0x74, 0xC4,
20779+
20780+ 0x31, 0x53, 0x2F, 0x9F,
20781+ 0x34, 0x80, 0x20, 0xE9,
20782+
20783+ 0x39, 0xE5, 0x2C, 0x9F,
20784+ 0x3C, 0x3D, 0x20, 0xE9,
20785+
20786+ 0x0A, 0x44, 0x54, 0xB0,
20787+ 0x02, 0x44, 0x64, 0xB0,
20788+
20789+ 0x2A, 0x44, 0x54, 0xB2,
20790+ 0x1A, 0x44, 0x64, 0xB2,
20791+
20792+ 0x25, 0x80, 0x3A, 0xEA,
20793+ 0x0A, 0x20,
20794+ 0x02, 0x20,
20795+
20796+ 0x3D, 0xCF, 0x74, 0xC2,
20797+ 0x2A, 0x20,
20798+ 0x1A, 0x20,
20799+
20800+ 0x30, 0x50, 0x2E, 0x9F,
20801+ 0x32, 0x31, 0x5F, 0xE9,
20802+
20803+ 0x38, 0x21, 0x2C, 0x9F,
20804+ 0x33, 0x39, 0x5F, 0xE9,
20805+
20806+ 0x31, 0x53, 0x2F, 0x9F,
20807+ 0x00, 0x80, 0x00, 0xE8,
20808+
20809+ 0x2A, 0x44, 0x54, 0xB4,
20810+ 0x1A, 0x44, 0x64, 0xB4,
20811+
20812+ 0x39, 0xE5, 0x2C, 0x9F,
20813+ 0x38, 0x3D, 0x20, 0xE9,
20814+
20815+ 0x88, 0x73, 0x5E, 0xE9,
20816+ 0x2A, 0x20,
20817+ 0x1A, 0x20,
20818+
20819+ 0x2A, 0x46, 0x56, 0xBF,
20820+ 0x1A, 0x46, 0x66, 0xBF,
20821+
20822+ 0x31, 0x53, 0x2F, 0x9F,
20823+ 0x3E, 0x30, 0x4F, 0xE9,
20824+
20825+ 0x39, 0xE5, 0x2C, 0x9F,
20826+ 0x3F, 0x38, 0x4F, 0xE9,
20827+
20828+ 0x0A, 0x47, 0x57, 0xBF,
20829+ 0x02, 0x47, 0x67, 0xBF,
20830+
20831+ 0x31, 0x53, 0x2F, 0x9F,
20832+ 0x3A, 0x31, 0x4F, 0xE9,
20833+
20834+ 0x39, 0xE5, 0x2C, 0x9F,
20835+ 0x3B, 0x39, 0x4F, 0xE9,
20836+
20837+ 0x2A, 0x43, 0x53, 0xBF,
20838+ 0x1A, 0x43, 0x63, 0xBF,
20839+
20840+ 0x30, 0x50, 0x2E, 0x9F,
20841+ 0x36, 0x31, 0x4F, 0xE9,
20842+
20843+ 0x38, 0x21, 0x2C, 0x9F,
20844+ 0x37, 0x39, 0x4F, 0xE9,
20845+
20846+ 0x0A, 0x48, 0x58, 0xBF,
20847+ 0x02, 0x48, 0x68, 0xBF,
20848+
20849+ 0x31, 0x53, 0x2F, 0x9F,
20850+ 0x80, 0x31, 0x57, 0xE9,
20851+
20852+ 0x39, 0xE5, 0x2C, 0x9F,
20853+ 0x81, 0x39, 0x57, 0xE9,
20854+
20855+ 0x2A, 0x49, 0x59, 0xBF,
20856+ 0x1A, 0x49, 0x69, 0xBF,
20857+
20858+ 0x30, 0x50, 0x2E, 0x9F,
20859+ 0x82, 0x30, 0x57, 0xE9,
20860+
20861+ 0x38, 0x21, 0x2C, 0x9F,
20862+ 0x83, 0x38, 0x57, 0xE9,
20863+
20864+ 0x31, 0x53, 0x2F, 0x9F,
20865+ 0x84, 0x31, 0x5E, 0xE9,
20866+
20867+ 0x39, 0xE5, 0x2C, 0x9F,
20868+ 0x85, 0x39, 0x5E, 0xE9,
20869+
20870+ 0x86, 0x76, 0x57, 0xE9,
20871+ 0x8A, 0x36, 0x20, 0xE9,
20872+
20873+ 0x87, 0x77, 0x57, 0xE9,
20874+ 0x8B, 0x3E, 0xBF, 0xEA,
20875+
20876+ 0x80, 0x30, 0x57, 0xE9,
20877+ 0x81, 0x38, 0x57, 0xE9,
20878+
20879+ 0x82, 0x31, 0x57, 0xE9,
20880+ 0x86, 0x78, 0x57, 0xE9,
20881+
20882+ 0x83, 0x39, 0x57, 0xE9,
20883+ 0x87, 0x79, 0x57, 0xE9,
20884+
20885+ 0x30, 0x1F, 0x5F, 0xE9,
20886+ 0x8A, 0x34, 0x20, 0xE9,
20887+
20888+ 0x8B, 0x3C, 0x20, 0xE9,
20889+ 0x37, 0x50, 0x60, 0xBD,
20890+
20891+ 0x57, 0x0D, 0x20, 0xE9,
20892+ 0x35, 0x51, 0x61, 0xBD,
20893+
20894+ 0x2B, 0x50, 0x20, 0xE9,
20895+ 0x1D, 0x37, 0xE1, 0xEA,
20896+
20897+ 0x1E, 0x35, 0xE1, 0xEA,
20898+ 0x00, 0xE0,
20899+ 0x0E, 0x77,
20900+
20901+ 0x24, 0x51, 0x20, 0xE9,
20902+ 0x9F, 0xFF, 0x20, 0xEA,
20903+
20904+ 0x16, 0x0E, 0x20, 0xE9,
20905+ 0x57, 0x2E, 0xBF, 0xEA,
20906+
20907+ 0x0B, 0x46, 0xA0, 0xE8,
20908+ 0x1B, 0x56, 0xA0, 0xE8,
20909+
20910+ 0x2B, 0x66, 0xA0, 0xE8,
20911+ 0x0C, 0x47, 0xA0, 0xE8,
20912+
20913+ 0x1C, 0x57, 0xA0, 0xE8,
20914+ 0x2C, 0x67, 0xA0, 0xE8,
20915+
20916+ 0x0B, 0x00,
20917+ 0x1B, 0x00,
20918+ 0x2B, 0x00,
20919+ 0x00, 0xE0,
20920+
20921+ 0x0C, 0x00,
20922+ 0x1C, 0x00,
20923+ 0x2C, 0x00,
20924+ 0x00, 0xE0,
20925+
20926+ 0x0B, 0x65,
20927+ 0x1B, 0x65,
20928+ 0x2B, 0x65,
20929+ 0x00, 0xE0,
20930+
20931+ 0x0C, 0x65,
20932+ 0x1C, 0x65,
20933+ 0x2C, 0x65,
20934+ 0x00, 0xE0,
20935+
20936+ 0x0B, 0x1B, 0x60, 0xEC,
20937+ 0x36, 0xD7, 0x36, 0xAD,
20938+
20939+ 0x2B, 0x80, 0x60, 0xEC,
20940+ 0x0C, 0x1C, 0x60, 0xEC,
20941+
20942+ 0x3E, 0xD7, 0x3E, 0xAD,
20943+ 0x2C, 0x80, 0x60, 0xEC,
20944+
20945+ 0x0B, 0x2B, 0xDE, 0xE8,
20946+ 0x1B, 0x80, 0xDE, 0xE8,
20947+
20948+ 0x36, 0x80, 0x36, 0xBD,
20949+ 0x3E, 0x80, 0x3E, 0xBD,
20950+
20951+ 0x33, 0xD7, 0x0B, 0xBD,
20952+ 0x3B, 0xD7, 0x1B, 0xBD,
20953+
20954+ 0x46, 0x80, 0x46, 0xCF,
20955+ 0x57, 0x80, 0x57, 0xCF,
20956+
20957+ 0x66, 0x33, 0x66, 0xCF,
20958+ 0x47, 0x3B, 0x47, 0xCF,
20959+
20960+ 0x56, 0x33, 0x56, 0xCF,
20961+ 0x67, 0x3B, 0x67, 0xCF,
20962+
20963+ 0x0B, 0x48, 0xA0, 0xE8,
20964+ 0x1B, 0x58, 0xA0, 0xE8,
20965+
20966+ 0x2B, 0x68, 0xA0, 0xE8,
20967+ 0x0C, 0x49, 0xA0, 0xE8,
20968+
20969+ 0x1C, 0x59, 0xA0, 0xE8,
20970+ 0x2C, 0x69, 0xA0, 0xE8,
20971+
20972+ 0x0B, 0x00,
20973+ 0x1B, 0x00,
20974+ 0x2B, 0x00,
20975+ 0x00, 0xE0,
20976+
20977+ 0x0C, 0x00,
20978+ 0x1C, 0x00,
20979+ 0x2C, 0x00,
20980+ 0x00, 0xE0,
20981+
20982+ 0x0B, 0x65,
20983+ 0x1B, 0x65,
20984+ 0x2B, 0x65,
20985+ 0x00, 0xE0,
20986+
20987+ 0x0C, 0x65,
20988+ 0x1C, 0x65,
20989+ 0x2C, 0x65,
20990+ 0x00, 0xE0,
20991+
20992+ 0x0B, 0x1B, 0x60, 0xEC,
20993+ 0x34, 0xD7, 0x34, 0xAD,
20994+
20995+ 0x2B, 0x80, 0x60, 0xEC,
20996+ 0x0C, 0x1C, 0x60, 0xEC,
20997+
20998+ 0x3C, 0xD7, 0x3C, 0xAD,
20999+ 0x2C, 0x80, 0x60, 0xEC,
21000+
21001+ 0x0B, 0x2B, 0xDE, 0xE8,
21002+ 0x1B, 0x80, 0xDE, 0xE8,
21003+
21004+ 0x34, 0x80, 0x34, 0xBD,
21005+ 0x3C, 0x80, 0x3C, 0xBD,
21006+
21007+ 0x33, 0xD7, 0x0B, 0xBD,
21008+ 0x3B, 0xD7, 0x1B, 0xBD,
21009+
21010+ 0x48, 0x80, 0x48, 0xCF,
21011+ 0x59, 0x80, 0x59, 0xCF,
21012+
21013+ 0x68, 0x33, 0x68, 0xCF,
21014+ 0x49, 0x3B, 0x49, 0xCF,
21015+
21016+ 0xBE, 0xFF, 0x20, 0xEA,
21017+ 0x00, 0x80, 0x00, 0xE8,
21018+
21019+ 0x58, 0x33, 0x58, 0xCF,
21020+ 0x69, 0x3B, 0x69, 0xCF,
21021+
21022+ 0x7D, 0xFF, 0x20, 0xEA,
21023+ 0x57, 0xC0, 0xBF, 0xEA,
21024+
21025+ 0x00, 0x80, 0xA0, 0xE9,
21026+ 0x00, 0x00, 0xD8, 0xEC,
21027+
21028+};
21029+
21030+static unsigned char warp_g400_t2gza[] = {
21031+
21032+ 0x00, 0x8A, 0x98, 0xE9,
21033+ 0x00, 0x80, 0x00, 0xE8,
21034+
21035+ 0x00, 0x80, 0xA0, 0xE9,
21036+ 0x00, 0x00, 0xD8, 0xEC,
21037+
21038+ 0xFF, 0x80, 0xC0, 0xE9,
21039+ 0x00, 0x80, 0x00, 0xE8,
21040+
21041+ 0x0A, 0x40, 0x50, 0xBF,
21042+ 0x2A, 0x40, 0x60, 0xBF,
21043+
21044+ 0x32, 0x41, 0x51, 0xBF,
21045+ 0x3A, 0x41, 0x61, 0xBF,
21046+
21047+ 0xC3, 0x6B,
21048+ 0xD3, 0x6B,
21049+ 0x00, 0x8A, 0x98, 0xE9,
21050+
21051+ 0x73, 0x7B, 0xC8, 0xEC,
21052+ 0x96, 0xE2,
21053+ 0x41, 0x04,
21054+
21055+ 0x7B, 0x43, 0xA0, 0xE8,
21056+ 0x73, 0x53, 0xA0, 0xE8,
21057+
21058+ 0xAD, 0xEE, 0x23, 0x9F,
21059+ 0x00, 0xE0,
21060+ 0x51, 0x04,
21061+
21062+ 0x90, 0xE2,
21063+ 0x61, 0x04,
21064+ 0x31, 0x46, 0xB1, 0xE8,
21065+
21066+ 0x51, 0x41, 0xE0, 0xEC,
21067+ 0x39, 0x67, 0xB1, 0xE8,
21068+
21069+ 0x00, 0x04,
21070+ 0x46, 0xE2,
21071+ 0x73, 0x63, 0xA0, 0xE8,
21072+
21073+ 0x61, 0x41, 0xE0, 0xEC,
21074+ 0x31, 0x00,
21075+ 0x39, 0x00,
21076+
21077+ 0x7C, 0x80, 0x15, 0xEA,
21078+ 0x10, 0x04,
21079+ 0x20, 0x04,
21080+
21081+ 0x61, 0x51, 0xE0, 0xEC,
21082+ 0x2F, 0x41, 0x60, 0xEA,
21083+
21084+ 0x31, 0x20,
21085+ 0x39, 0x20,
21086+ 0x1F, 0x42, 0xA0, 0xE8,
21087+
21088+ 0x2A, 0x42, 0x52, 0xBF,
21089+ 0x0F, 0x52, 0xA0, 0xE8,
21090+
21091+ 0x1A, 0x42, 0x62, 0xBF,
21092+ 0x1E, 0x51, 0x60, 0xEA,
21093+
21094+ 0x73, 0x7B, 0xC8, 0xEC,
21095+ 0x0E, 0x61, 0x60, 0xEA,
21096+
21097+ 0x32, 0x40, 0x50, 0xBD,
21098+ 0x22, 0x40, 0x60, 0xBD,
21099+
21100+ 0x12, 0x41, 0x51, 0xBD,
21101+ 0x3A, 0x41, 0x61, 0xBD,
21102+
21103+ 0xBF, 0x2F, 0x0E, 0xBD,
21104+ 0x97, 0xE2,
21105+ 0x7B, 0x72,
21106+
21107+ 0x32, 0x20,
21108+ 0x22, 0x20,
21109+ 0x12, 0x20,
21110+ 0x3A, 0x20,
21111+
21112+ 0x35, 0x48, 0xB1, 0xE8,
21113+ 0x3D, 0x59, 0xB1, 0xE8,
21114+
21115+ 0x46, 0x31, 0x46, 0xBF,
21116+ 0x56, 0x31, 0x56, 0xBF,
21117+
21118+ 0xB3, 0xE2, 0x2D, 0x9F,
21119+ 0x00, 0x80, 0x00, 0xE8,
21120+
21121+ 0x66, 0x31, 0x66, 0xBF,
21122+ 0x47, 0x39, 0x47, 0xBF,
21123+
21124+ 0x57, 0x39, 0x57, 0xBF,
21125+ 0x67, 0x39, 0x67, 0xBF,
21126+
21127+ 0x6D, 0x80, 0x07, 0xEA,
21128+ 0x24, 0x41, 0x20, 0xE9,
21129+
21130+ 0x35, 0x00,
21131+ 0x3D, 0x00,
21132+ 0x00, 0xE0,
21133+ 0x2D, 0x73,
21134+
21135+ 0x33, 0x72,
21136+ 0x0C, 0xE3,
21137+ 0x8D, 0x2F, 0x1E, 0xBD,
21138+
21139+ 0x43, 0x75, 0xF8, 0xEC,
21140+ 0x35, 0x20,
21141+ 0x3D, 0x20,
21142+
21143+ 0x43, 0x43, 0x2D, 0xDF,
21144+ 0x53, 0x53, 0x2D, 0xDF,
21145+
21146+ 0xAE, 0x1E, 0x0E, 0xBD,
21147+ 0x58, 0xE3,
21148+ 0x33, 0x66,
21149+
21150+ 0x48, 0x35, 0x48, 0xBF,
21151+ 0x58, 0x35, 0x58, 0xBF,
21152+
21153+ 0x68, 0x35, 0x68, 0xBF,
21154+ 0x49, 0x3D, 0x49, 0xBF,
21155+
21156+ 0x59, 0x3D, 0x59, 0xBF,
21157+ 0x69, 0x3D, 0x69, 0xBF,
21158+
21159+ 0x63, 0x63, 0x2D, 0xDF,
21160+ 0x4D, 0x7D, 0xF8, 0xEC,
21161+
21162+ 0x59, 0xE3,
21163+ 0x00, 0xE0,
21164+ 0xB8, 0x38, 0x33, 0xBF,
21165+
21166+ 0x2D, 0x73,
21167+ 0x30, 0x76,
21168+ 0x18, 0x3A, 0x41, 0xE9,
21169+
21170+ 0x3F, 0x53, 0xA0, 0xE8,
21171+ 0x05, 0x80, 0x3D, 0xEA,
21172+
21173+ 0x37, 0x43, 0xA0, 0xE8,
21174+ 0x3D, 0x63, 0xA0, 0xE8,
21175+
21176+ 0x50, 0x70, 0xF8, 0xEC,
21177+ 0x2B, 0x50, 0x3C, 0xE9,
21178+
21179+ 0x1F, 0x0F, 0xBC, 0xE8,
21180+ 0x00, 0x80, 0x00, 0xE8,
21181+
21182+ 0x59, 0x78, 0xF8, 0xEC,
21183+ 0x00, 0x80, 0x00, 0xE8,
21184+
21185+ 0x15, 0xC0, 0x20, 0xE9,
21186+ 0x15, 0xC0, 0x20, 0xE9,
21187+
21188+ 0x15, 0xC0, 0x20, 0xE9,
21189+ 0x15, 0xC0, 0x20, 0xE9,
21190+
21191+ 0x1E, 0x12, 0x41, 0xE9,
21192+ 0x1A, 0x22, 0x41, 0xE9,
21193+
21194+ 0x46, 0x37, 0x46, 0xDF,
21195+ 0x56, 0x3F, 0x56, 0xDF,
21196+
21197+ 0x2B, 0x40, 0x3D, 0xE9,
21198+ 0x66, 0x3D, 0x66, 0xDF,
21199+
21200+ 0x1D, 0x32, 0x41, 0xE9,
21201+ 0x67, 0x3D, 0x67, 0xDF,
21202+
21203+ 0x47, 0x37, 0x47, 0xDF,
21204+ 0x57, 0x3F, 0x57, 0xDF,
21205+
21206+ 0x2A, 0x40, 0x20, 0xE9,
21207+ 0x59, 0x3F, 0x59, 0xDF,
21208+
21209+ 0x16, 0x30, 0x20, 0xE9,
21210+ 0x69, 0x3D, 0x69, 0xDF,
21211+
21212+ 0x48, 0x37, 0x48, 0xDF,
21213+ 0x58, 0x3F, 0x58, 0xDF,
21214+
21215+ 0x12, 0x12, 0x2D, 0xDF,
21216+ 0x22, 0x22, 0x2D, 0xDF,
21217+
21218+ 0x32, 0x32, 0x2D, 0xDF,
21219+ 0x3A, 0x3A, 0x2D, 0xDF,
21220+
21221+ 0x68, 0x3D, 0x68, 0xDF,
21222+ 0x49, 0x37, 0x49, 0xDF,
21223+
21224+ 0x3D, 0xCF, 0x74, 0xC0,
21225+ 0x37, 0xCF, 0x74, 0xC4,
21226+
21227+ 0x31, 0x53, 0x2F, 0x9F,
21228+ 0x34, 0x80, 0x20, 0xE9,
21229+
21230+ 0x39, 0xE5, 0x2C, 0x9F,
21231+ 0x3C, 0x3D, 0x20, 0xE9,
21232+
21233+ 0x0A, 0x44, 0x54, 0xB0,
21234+ 0x02, 0x44, 0x64, 0xB0,
21235+
21236+ 0x2A, 0x44, 0x54, 0xB2,
21237+ 0x1A, 0x44, 0x64, 0xB2,
21238+
21239+ 0x29, 0x80, 0x3A, 0xEA,
21240+ 0x0A, 0x20,
21241+ 0x02, 0x20,
21242+
21243+ 0x0F, 0xCF, 0x74, 0xC6,
21244+ 0x3D, 0xCF, 0x74, 0xC2,
21245+
21246+ 0x88, 0x73, 0x5E, 0xE9,
21247+ 0x2A, 0x20,
21248+ 0x1A, 0x20,
21249+
21250+ 0x30, 0x50, 0x2E, 0x9F,
21251+ 0x32, 0x31, 0x5F, 0xE9,
21252+
21253+ 0x38, 0x21, 0x2C, 0x9F,
21254+ 0x33, 0x39, 0x5F, 0xE9,
21255+
21256+ 0x31, 0x53, 0x2F, 0x9F,
21257+ 0x9C, 0x0F, 0x20, 0xE9,
21258+
21259+ 0x0A, 0x44, 0x54, 0xB4,
21260+ 0x02, 0x44, 0x64, 0xB4,
21261+
21262+ 0x2A, 0x44, 0x54, 0xB6,
21263+ 0x1A, 0x44, 0x64, 0xB6,
21264+
21265+ 0x39, 0xE5, 0x2C, 0x9F,
21266+ 0x38, 0x3D, 0x20, 0xE9,
21267+
21268+ 0x0A, 0x20,
21269+ 0x02, 0x20,
21270+ 0x2A, 0x20,
21271+ 0x1A, 0x20,
21272+
21273+ 0x0A, 0x47, 0x57, 0xBF,
21274+ 0x02, 0x47, 0x67, 0xBF,
21275+
21276+ 0x30, 0x50, 0x2E, 0x9F,
21277+ 0x3E, 0x30, 0x4F, 0xE9,
21278+
21279+ 0x38, 0x21, 0x2C, 0x9F,
21280+ 0x3F, 0x38, 0x4F, 0xE9,
21281+
21282+ 0x2A, 0x46, 0x56, 0xBF,
21283+ 0x1A, 0x46, 0x66, 0xBF,
21284+
21285+ 0x31, 0x53, 0x2F, 0x9F,
21286+ 0x3A, 0x31, 0x4F, 0xE9,
21287+
21288+ 0x39, 0xE5, 0x2C, 0x9F,
21289+ 0x3B, 0x39, 0x4F, 0xE9,
21290+
21291+ 0x31, 0x53, 0x2F, 0x9F,
21292+ 0x36, 0x30, 0x4F, 0xE9,
21293+
21294+ 0x39, 0xE5, 0x2C, 0x9F,
21295+ 0x37, 0x38, 0x4F, 0xE9,
21296+
21297+ 0x2A, 0x43, 0x53, 0xBF,
21298+ 0x1A, 0x43, 0x63, 0xBF,
21299+
21300+ 0x30, 0x50, 0x2E, 0x9F,
21301+ 0x9D, 0x31, 0x4F, 0xE9,
21302+
21303+ 0x38, 0x21, 0x2C, 0x9F,
21304+ 0x9E, 0x39, 0x4F, 0xE9,
21305+
21306+ 0x0A, 0x48, 0x58, 0xBF,
21307+ 0x02, 0x48, 0x68, 0xBF,
21308+
21309+ 0x31, 0x53, 0x2F, 0x9F,
21310+ 0x80, 0x31, 0x57, 0xE9,
21311+
21312+ 0x39, 0xE5, 0x2C, 0x9F,
21313+ 0x81, 0x39, 0x57, 0xE9,
21314+
21315+ 0x2A, 0x49, 0x59, 0xBF,
21316+ 0x1A, 0x49, 0x69, 0xBF,
21317+
21318+ 0x30, 0x50, 0x2E, 0x9F,
21319+ 0x82, 0x30, 0x57, 0xE9,
21320+
21321+ 0x38, 0x21, 0x2C, 0x9F,
21322+ 0x83, 0x38, 0x57, 0xE9,
21323+
21324+ 0x31, 0x53, 0x2F, 0x9F,
21325+ 0x84, 0x31, 0x5E, 0xE9,
21326+
21327+ 0x39, 0xE5, 0x2C, 0x9F,
21328+ 0x85, 0x39, 0x5E, 0xE9,
21329+
21330+ 0x86, 0x76, 0x57, 0xE9,
21331+ 0x8A, 0x36, 0x20, 0xE9,
21332+
21333+ 0x87, 0x77, 0x57, 0xE9,
21334+ 0x8B, 0x3E, 0xBF, 0xEA,
21335+
21336+ 0x80, 0x30, 0x57, 0xE9,
21337+ 0x81, 0x38, 0x57, 0xE9,
21338+
21339+ 0x82, 0x31, 0x57, 0xE9,
21340+ 0x86, 0x78, 0x57, 0xE9,
21341+
21342+ 0x83, 0x39, 0x57, 0xE9,
21343+ 0x87, 0x79, 0x57, 0xE9,
21344+
21345+ 0x30, 0x1F, 0x5F, 0xE9,
21346+ 0x8A, 0x34, 0x20, 0xE9,
21347+
21348+ 0x8B, 0x3C, 0x20, 0xE9,
21349+ 0x37, 0x50, 0x60, 0xBD,
21350+
21351+ 0x57, 0x0D, 0x20, 0xE9,
21352+ 0x35, 0x51, 0x61, 0xBD,
21353+
21354+ 0x2B, 0x50, 0x20, 0xE9,
21355+ 0x1D, 0x37, 0xE1, 0xEA,
21356+
21357+ 0x1E, 0x35, 0xE1, 0xEA,
21358+ 0x00, 0xE0,
21359+ 0x0E, 0x77,
21360+
21361+ 0x24, 0x51, 0x20, 0xE9,
21362+ 0x9B, 0xFF, 0x20, 0xEA,
21363+
21364+ 0x16, 0x0E, 0x20, 0xE9,
21365+ 0x57, 0x2E, 0xBF, 0xEA,
21366+
21367+ 0x0B, 0x46, 0xA0, 0xE8,
21368+ 0x1B, 0x56, 0xA0, 0xE8,
21369+
21370+ 0x2B, 0x66, 0xA0, 0xE8,
21371+ 0x0C, 0x47, 0xA0, 0xE8,
21372+
21373+ 0x1C, 0x57, 0xA0, 0xE8,
21374+ 0x2C, 0x67, 0xA0, 0xE8,
21375+
21376+ 0x0B, 0x00,
21377+ 0x1B, 0x00,
21378+ 0x2B, 0x00,
21379+ 0x00, 0xE0,
21380+
21381+ 0x0C, 0x00,
21382+ 0x1C, 0x00,
21383+ 0x2C, 0x00,
21384+ 0x00, 0xE0,
21385+
21386+ 0x0B, 0x65,
21387+ 0x1B, 0x65,
21388+ 0x2B, 0x65,
21389+ 0x00, 0xE0,
21390+
21391+ 0x0C, 0x65,
21392+ 0x1C, 0x65,
21393+ 0x2C, 0x65,
21394+ 0x00, 0xE0,
21395+
21396+ 0x0B, 0x1B, 0x60, 0xEC,
21397+ 0x36, 0xD7, 0x36, 0xAD,
21398+
21399+ 0x2B, 0x80, 0x60, 0xEC,
21400+ 0x0C, 0x1C, 0x60, 0xEC,
21401+
21402+ 0x3E, 0xD7, 0x3E, 0xAD,
21403+ 0x2C, 0x80, 0x60, 0xEC,
21404+
21405+ 0x0B, 0x2B, 0xDE, 0xE8,
21406+ 0x1B, 0x80, 0xDE, 0xE8,
21407+
21408+ 0x36, 0x80, 0x36, 0xBD,
21409+ 0x3E, 0x80, 0x3E, 0xBD,
21410+
21411+ 0x33, 0xD7, 0x0B, 0xBD,
21412+ 0x3B, 0xD7, 0x1B, 0xBD,
21413+
21414+ 0x46, 0x80, 0x46, 0xCF,
21415+ 0x57, 0x80, 0x57, 0xCF,
21416+
21417+ 0x66, 0x33, 0x66, 0xCF,
21418+ 0x47, 0x3B, 0x47, 0xCF,
21419+
21420+ 0x56, 0x33, 0x56, 0xCF,
21421+ 0x67, 0x3B, 0x67, 0xCF,
21422+
21423+ 0x0B, 0x48, 0xA0, 0xE8,
21424+ 0x1B, 0x58, 0xA0, 0xE8,
21425+
21426+ 0x2B, 0x68, 0xA0, 0xE8,
21427+ 0x0C, 0x49, 0xA0, 0xE8,
21428+
21429+ 0x1C, 0x59, 0xA0, 0xE8,
21430+ 0x2C, 0x69, 0xA0, 0xE8,
21431+
21432+ 0x0B, 0x00,
21433+ 0x1B, 0x00,
21434+ 0x2B, 0x00,
21435+ 0x00, 0xE0,
21436+
21437+ 0x0C, 0x00,
21438+ 0x1C, 0x00,
21439+ 0x2C, 0x00,
21440+ 0x00, 0xE0,
21441+
21442+ 0x0B, 0x65,
21443+ 0x1B, 0x65,
21444+ 0x2B, 0x65,
21445+ 0x00, 0xE0,
21446+
21447+ 0x0C, 0x65,
21448+ 0x1C, 0x65,
21449+ 0x2C, 0x65,
21450+ 0x00, 0xE0,
21451+
21452+ 0x0B, 0x1B, 0x60, 0xEC,
21453+ 0x34, 0xD7, 0x34, 0xAD,
21454+
21455+ 0x2B, 0x80, 0x60, 0xEC,
21456+ 0x0C, 0x1C, 0x60, 0xEC,
21457+
21458+ 0x3C, 0xD7, 0x3C, 0xAD,
21459+ 0x2C, 0x80, 0x60, 0xEC,
21460+
21461+ 0x0B, 0x2B, 0xDE, 0xE8,
21462+ 0x1B, 0x80, 0xDE, 0xE8,
21463+
21464+ 0x34, 0x80, 0x34, 0xBD,
21465+ 0x3C, 0x80, 0x3C, 0xBD,
21466+
21467+ 0x33, 0xD7, 0x0B, 0xBD,
21468+ 0x3B, 0xD7, 0x1B, 0xBD,
21469+
21470+ 0x48, 0x80, 0x48, 0xCF,
21471+ 0x59, 0x80, 0x59, 0xCF,
21472+
21473+ 0x68, 0x33, 0x68, 0xCF,
21474+ 0x49, 0x3B, 0x49, 0xCF,
21475+
21476+ 0xBA, 0xFF, 0x20, 0xEA,
21477+ 0x00, 0x80, 0x00, 0xE8,
21478+
21479+ 0x58, 0x33, 0x58, 0xCF,
21480+ 0x69, 0x3B, 0x69, 0xCF,
21481+
21482+ 0x79, 0xFF, 0x20, 0xEA,
21483+ 0x57, 0xC0, 0xBF, 0xEA,
21484+
21485+ 0x00, 0x80, 0xA0, 0xE9,
21486+ 0x00, 0x00, 0xD8, 0xEC,
21487+
21488+};
21489+
21490+static unsigned char warp_g400_t2gzaf[] = {
21491+
21492+ 0x00, 0x8A, 0x98, 0xE9,
21493+ 0x00, 0x80, 0x00, 0xE8,
21494+
21495+ 0x00, 0x80, 0xA0, 0xE9,
21496+ 0x00, 0x00, 0xD8, 0xEC,
21497+
21498+ 0xFF, 0x80, 0xC0, 0xE9,
21499+ 0x00, 0x80, 0x00, 0xE8,
21500+
21501+ 0x0A, 0x40, 0x50, 0xBF,
21502+ 0x2A, 0x40, 0x60, 0xBF,
21503+
21504+ 0x32, 0x41, 0x51, 0xBF,
21505+ 0x3A, 0x41, 0x61, 0xBF,
21506+
21507+ 0xC3, 0x6B,
21508+ 0xD3, 0x6B,
21509+ 0x00, 0x8A, 0x98, 0xE9,
21510+
21511+ 0x73, 0x7B, 0xC8, 0xEC,
21512+ 0x96, 0xE2,
21513+ 0x41, 0x04,
21514+
21515+ 0x7B, 0x43, 0xA0, 0xE8,
21516+ 0x73, 0x53, 0xA0, 0xE8,
21517+
21518+ 0xAD, 0xEE, 0x23, 0x9F,
21519+ 0x00, 0xE0,
21520+ 0x51, 0x04,
21521+
21522+ 0x90, 0xE2,
21523+ 0x61, 0x04,
21524+ 0x31, 0x46, 0xB1, 0xE8,
21525+
21526+ 0x51, 0x41, 0xE0, 0xEC,
21527+ 0x39, 0x67, 0xB1, 0xE8,
21528+
21529+ 0x00, 0x04,
21530+ 0x46, 0xE2,
21531+ 0x73, 0x63, 0xA0, 0xE8,
21532+
21533+ 0x61, 0x41, 0xE0, 0xEC,
21534+ 0x31, 0x00,
21535+ 0x39, 0x00,
21536+
21537+ 0x81, 0x80, 0x15, 0xEA,
21538+ 0x10, 0x04,
21539+ 0x20, 0x04,
21540+
21541+ 0x61, 0x51, 0xE0, 0xEC,
21542+ 0x2F, 0x41, 0x60, 0xEA,
21543+
21544+ 0x31, 0x20,
21545+ 0x39, 0x20,
21546+ 0x1F, 0x42, 0xA0, 0xE8,
21547+
21548+ 0x2A, 0x42, 0x52, 0xBF,
21549+ 0x0F, 0x52, 0xA0, 0xE8,
21550+
21551+ 0x1A, 0x42, 0x62, 0xBF,
21552+ 0x1E, 0x51, 0x60, 0xEA,
21553+
21554+ 0x73, 0x7B, 0xC8, 0xEC,
21555+ 0x0E, 0x61, 0x60, 0xEA,
21556+
21557+ 0x32, 0x40, 0x50, 0xBD,
21558+ 0x22, 0x40, 0x60, 0xBD,
21559+
21560+ 0x12, 0x41, 0x51, 0xBD,
21561+ 0x3A, 0x41, 0x61, 0xBD,
21562+
21563+ 0xBF, 0x2F, 0x0E, 0xBD,
21564+ 0x97, 0xE2,
21565+ 0x7B, 0x72,
21566+
21567+ 0x32, 0x20,
21568+ 0x22, 0x20,
21569+ 0x12, 0x20,
21570+ 0x3A, 0x20,
21571+
21572+ 0x35, 0x48, 0xB1, 0xE8,
21573+ 0x3D, 0x59, 0xB1, 0xE8,
21574+
21575+ 0x46, 0x31, 0x46, 0xBF,
21576+ 0x56, 0x31, 0x56, 0xBF,
21577+
21578+ 0xB3, 0xE2, 0x2D, 0x9F,
21579+ 0x00, 0x80, 0x00, 0xE8,
21580+
21581+ 0x66, 0x31, 0x66, 0xBF,
21582+ 0x47, 0x39, 0x47, 0xBF,
21583+
21584+ 0x57, 0x39, 0x57, 0xBF,
21585+ 0x67, 0x39, 0x67, 0xBF,
21586+
21587+ 0x72, 0x80, 0x07, 0xEA,
21588+ 0x24, 0x41, 0x20, 0xE9,
21589+
21590+ 0x35, 0x00,
21591+ 0x3D, 0x00,
21592+ 0x00, 0xE0,
21593+ 0x2D, 0x73,
21594+
21595+ 0x33, 0x72,
21596+ 0x0C, 0xE3,
21597+ 0x8D, 0x2F, 0x1E, 0xBD,
21598+
21599+ 0x43, 0x75, 0xF8, 0xEC,
21600+ 0x35, 0x20,
21601+ 0x3D, 0x20,
21602+
21603+ 0x43, 0x43, 0x2D, 0xDF,
21604+ 0x53, 0x53, 0x2D, 0xDF,
21605+
21606+ 0xAE, 0x1E, 0x0E, 0xBD,
21607+ 0x58, 0xE3,
21608+ 0x33, 0x66,
21609+
21610+ 0x48, 0x35, 0x48, 0xBF,
21611+ 0x58, 0x35, 0x58, 0xBF,
21612+
21613+ 0x68, 0x35, 0x68, 0xBF,
21614+ 0x49, 0x3D, 0x49, 0xBF,
21615+
21616+ 0x59, 0x3D, 0x59, 0xBF,
21617+ 0x69, 0x3D, 0x69, 0xBF,
21618+
21619+ 0x63, 0x63, 0x2D, 0xDF,
21620+ 0x4D, 0x7D, 0xF8, 0xEC,
21621+
21622+ 0x59, 0xE3,
21623+ 0x00, 0xE0,
21624+ 0xB8, 0x38, 0x33, 0xBF,
21625+
21626+ 0x2D, 0x73,
21627+ 0x30, 0x76,
21628+ 0x18, 0x3A, 0x41, 0xE9,
21629+
21630+ 0x3F, 0x53, 0xA0, 0xE8,
21631+ 0x05, 0x80, 0x3D, 0xEA,
21632+
21633+ 0x37, 0x43, 0xA0, 0xE8,
21634+ 0x3D, 0x63, 0xA0, 0xE8,
21635+
21636+ 0x50, 0x70, 0xF8, 0xEC,
21637+ 0x2B, 0x50, 0x3C, 0xE9,
21638+
21639+ 0x1F, 0x0F, 0xBC, 0xE8,
21640+ 0x00, 0x80, 0x00, 0xE8,
21641+
21642+ 0x59, 0x78, 0xF8, 0xEC,
21643+ 0x00, 0x80, 0x00, 0xE8,
21644+
21645+ 0x15, 0xC0, 0x20, 0xE9,
21646+ 0x15, 0xC0, 0x20, 0xE9,
21647+
21648+ 0x15, 0xC0, 0x20, 0xE9,
21649+ 0x15, 0xC0, 0x20, 0xE9,
21650+
21651+ 0x1E, 0x12, 0x41, 0xE9,
21652+ 0x1A, 0x22, 0x41, 0xE9,
21653+
21654+ 0x46, 0x37, 0x46, 0xDF,
21655+ 0x56, 0x3F, 0x56, 0xDF,
21656+
21657+ 0x2B, 0x40, 0x3D, 0xE9,
21658+ 0x66, 0x3D, 0x66, 0xDF,
21659+
21660+ 0x1D, 0x32, 0x41, 0xE9,
21661+ 0x67, 0x3D, 0x67, 0xDF,
21662+
21663+ 0x47, 0x37, 0x47, 0xDF,
21664+ 0x57, 0x3F, 0x57, 0xDF,
21665+
21666+ 0x2A, 0x40, 0x20, 0xE9,
21667+ 0x59, 0x3F, 0x59, 0xDF,
21668+
21669+ 0x16, 0x30, 0x20, 0xE9,
21670+ 0x69, 0x3D, 0x69, 0xDF,
21671+
21672+ 0x48, 0x37, 0x48, 0xDF,
21673+ 0x58, 0x3F, 0x58, 0xDF,
21674+
21675+ 0x12, 0x12, 0x2D, 0xDF,
21676+ 0x22, 0x22, 0x2D, 0xDF,
21677+
21678+ 0x32, 0x32, 0x2D, 0xDF,
21679+ 0x3A, 0x3A, 0x2D, 0xDF,
21680+
21681+ 0x68, 0x3D, 0x68, 0xDF,
21682+ 0x49, 0x37, 0x49, 0xDF,
21683+
21684+ 0x3D, 0xCF, 0x74, 0xC0,
21685+ 0x37, 0xCF, 0x74, 0xC4,
21686+
21687+ 0x0A, 0x44, 0x54, 0xB0,
21688+ 0x02, 0x44, 0x64, 0xB0,
21689+
21690+ 0x31, 0x53, 0x2F, 0x9F,
21691+ 0x34, 0x37, 0x20, 0xE9,
21692+
21693+ 0x39, 0xE5, 0x2C, 0x9F,
21694+ 0x3C, 0x3D, 0x20, 0xE9,
21695+
21696+ 0x2A, 0x44, 0x54, 0xB2,
21697+ 0x1A, 0x44, 0x64, 0xB2,
21698+
21699+ 0x2E, 0x80, 0x3A, 0xEA,
21700+ 0x0A, 0x20,
21701+ 0x02, 0x20,
21702+
21703+ 0x88, 0x73, 0x5E, 0xE9,
21704+ 0x2A, 0x20,
21705+ 0x1A, 0x20,
21706+
21707+ 0x3D, 0xCF, 0x74, 0xC2,
21708+ 0x0F, 0xCF, 0x74, 0xC6,
21709+
21710+ 0x30, 0x50, 0x2E, 0x9F,
21711+ 0x32, 0x31, 0x5F, 0xE9,
21712+
21713+ 0x38, 0x21, 0x2C, 0x9F,
21714+ 0x33, 0x39, 0x5F, 0xE9,
21715+
21716+ 0x31, 0x53, 0x2F, 0x9F,
21717+ 0x9C, 0x0F, 0x20, 0xE9,
21718+
21719+ 0x0A, 0x44, 0x54, 0xB4,
21720+ 0x02, 0x44, 0x64, 0xB4,
21721+
21722+ 0x2A, 0x44, 0x54, 0xB6,
21723+ 0x1A, 0x44, 0x64, 0xB6,
21724+
21725+ 0x39, 0xE5, 0x2C, 0x9F,
21726+ 0x38, 0x3D, 0x20, 0xE9,
21727+
21728+ 0x0A, 0x20,
21729+ 0x02, 0x20,
21730+ 0x2A, 0x20,
21731+ 0x1A, 0x20,
21732+
21733+ 0x3D, 0xCF, 0x75, 0xC6,
21734+ 0x00, 0x80, 0x00, 0xE8,
21735+
21736+ 0x30, 0x50, 0x2E, 0x9F,
21737+ 0x3E, 0x30, 0x4F, 0xE9,
21738+
21739+ 0x38, 0x21, 0x2C, 0x9F,
21740+ 0x3F, 0x38, 0x4F, 0xE9,
21741+
21742+ 0x0A, 0x45, 0x55, 0xB6,
21743+ 0x02, 0x45, 0x65, 0xB6,
21744+
21745+ 0x31, 0x53, 0x2F, 0x9F,
21746+ 0x3A, 0x31, 0x4F, 0xE9,
21747+
21748+ 0x39, 0xE5, 0x2C, 0x9F,
21749+ 0x3B, 0x39, 0x4F, 0xE9,
21750+
21751+ 0x31, 0x3D, 0x20, 0xE9,
21752+ 0x0A, 0x20,
21753+ 0x02, 0x20,
21754+
21755+ 0x2A, 0x46, 0x56, 0xBF,
21756+ 0x1A, 0x46, 0x66, 0xBF,
21757+
21758+ 0x0A, 0x47, 0x57, 0xBF,
21759+ 0x02, 0x47, 0x67, 0xBF,
21760+
21761+ 0x30, 0x50, 0x2E, 0x9F,
21762+ 0x36, 0x30, 0x4F, 0xE9,
21763+
21764+ 0x38, 0x21, 0x2C, 0x9F,
21765+ 0x37, 0x38, 0x4F, 0xE9,
21766+
21767+ 0x31, 0x53, 0x2F, 0x9F,
21768+ 0x9D, 0x31, 0x4F, 0xE9,
21769+
21770+ 0x39, 0xE5, 0x2C, 0x9F,
21771+ 0x9E, 0x39, 0x4F, 0xE9,
21772+
21773+ 0x2A, 0x43, 0x53, 0xBF,
21774+ 0x1A, 0x43, 0x63, 0xBF,
21775+
21776+ 0x30, 0x50, 0x2E, 0x9F,
21777+ 0x35, 0x30, 0x4F, 0xE9,
21778+
21779+ 0x38, 0x21, 0x2C, 0x9F,
21780+ 0x39, 0x38, 0x4F, 0xE9,
21781+
21782+ 0x0A, 0x48, 0x58, 0xBF,
21783+ 0x02, 0x48, 0x68, 0xBF,
21784+
21785+ 0x31, 0x53, 0x2F, 0x9F,
21786+ 0x80, 0x31, 0x57, 0xE9,
21787+
21788+ 0x39, 0xE5, 0x2C, 0x9F,
21789+ 0x81, 0x39, 0x57, 0xE9,
21790+
21791+ 0x2A, 0x49, 0x59, 0xBF,
21792+ 0x1A, 0x49, 0x69, 0xBF,
21793+
21794+ 0x30, 0x50, 0x2E, 0x9F,
21795+ 0x82, 0x30, 0x57, 0xE9,
21796+
21797+ 0x38, 0x21, 0x2C, 0x9F,
21798+ 0x83, 0x38, 0x57, 0xE9,
21799+
21800+ 0x31, 0x53, 0x2F, 0x9F,
21801+ 0x84, 0x31, 0x5E, 0xE9,
21802+
21803+ 0x39, 0xE5, 0x2C, 0x9F,
21804+ 0x85, 0x39, 0x5E, 0xE9,
21805+
21806+ 0x86, 0x76, 0x57, 0xE9,
21807+ 0x8A, 0x36, 0x20, 0xE9,
21808+
21809+ 0x87, 0x77, 0x57, 0xE9,
21810+ 0x8B, 0x3E, 0xBF, 0xEA,
21811+
21812+ 0x80, 0x30, 0x57, 0xE9,
21813+ 0x81, 0x38, 0x57, 0xE9,
21814+
21815+ 0x82, 0x31, 0x57, 0xE9,
21816+ 0x86, 0x78, 0x57, 0xE9,
21817+
21818+ 0x83, 0x39, 0x57, 0xE9,
21819+ 0x87, 0x79, 0x57, 0xE9,
21820+
21821+ 0x30, 0x1F, 0x5F, 0xE9,
21822+ 0x8A, 0x34, 0x20, 0xE9,
21823+
21824+ 0x8B, 0x3C, 0x20, 0xE9,
21825+ 0x37, 0x50, 0x60, 0xBD,
21826+
21827+ 0x57, 0x0D, 0x20, 0xE9,
21828+ 0x35, 0x51, 0x61, 0xBD,
21829+
21830+ 0x2B, 0x50, 0x20, 0xE9,
21831+ 0x1D, 0x37, 0xE1, 0xEA,
21832+
21833+ 0x1E, 0x35, 0xE1, 0xEA,
21834+ 0x00, 0xE0,
21835+ 0x0E, 0x77,
21836+
21837+ 0x24, 0x51, 0x20, 0xE9,
21838+ 0x96, 0xFF, 0x20, 0xEA,
21839+
21840+ 0x16, 0x0E, 0x20, 0xE9,
21841+ 0x57, 0x2E, 0xBF, 0xEA,
21842+
21843+ 0x0B, 0x46, 0xA0, 0xE8,
21844+ 0x1B, 0x56, 0xA0, 0xE8,
21845+
21846+ 0x2B, 0x66, 0xA0, 0xE8,
21847+ 0x0C, 0x47, 0xA0, 0xE8,
21848+
21849+ 0x1C, 0x57, 0xA0, 0xE8,
21850+ 0x2C, 0x67, 0xA0, 0xE8,
21851+
21852+ 0x0B, 0x00,
21853+ 0x1B, 0x00,
21854+ 0x2B, 0x00,
21855+ 0x00, 0xE0,
21856+
21857+ 0x0C, 0x00,
21858+ 0x1C, 0x00,
21859+ 0x2C, 0x00,
21860+ 0x00, 0xE0,
21861+
21862+ 0x0B, 0x65,
21863+ 0x1B, 0x65,
21864+ 0x2B, 0x65,
21865+ 0x00, 0xE0,
21866+
21867+ 0x0C, 0x65,
21868+ 0x1C, 0x65,
21869+ 0x2C, 0x65,
21870+ 0x00, 0xE0,
21871+
21872+ 0x0B, 0x1B, 0x60, 0xEC,
21873+ 0x36, 0xD7, 0x36, 0xAD,
21874+
21875+ 0x2B, 0x80, 0x60, 0xEC,
21876+ 0x0C, 0x1C, 0x60, 0xEC,
21877+
21878+ 0x3E, 0xD7, 0x3E, 0xAD,
21879+ 0x2C, 0x80, 0x60, 0xEC,
21880+
21881+ 0x0B, 0x2B, 0xDE, 0xE8,
21882+ 0x1B, 0x80, 0xDE, 0xE8,
21883+
21884+ 0x36, 0x80, 0x36, 0xBD,
21885+ 0x3E, 0x80, 0x3E, 0xBD,
21886+
21887+ 0x33, 0xD7, 0x0B, 0xBD,
21888+ 0x3B, 0xD7, 0x1B, 0xBD,
21889+
21890+ 0x46, 0x80, 0x46, 0xCF,
21891+ 0x57, 0x80, 0x57, 0xCF,
21892+
21893+ 0x66, 0x33, 0x66, 0xCF,
21894+ 0x47, 0x3B, 0x47, 0xCF,
21895+
21896+ 0x56, 0x33, 0x56, 0xCF,
21897+ 0x67, 0x3B, 0x67, 0xCF,
21898+
21899+ 0x0B, 0x48, 0xA0, 0xE8,
21900+ 0x1B, 0x58, 0xA0, 0xE8,
21901+
21902+ 0x2B, 0x68, 0xA0, 0xE8,
21903+ 0x0C, 0x49, 0xA0, 0xE8,
21904+
21905+ 0x1C, 0x59, 0xA0, 0xE8,
21906+ 0x2C, 0x69, 0xA0, 0xE8,
21907+
21908+ 0x0B, 0x00,
21909+ 0x1B, 0x00,
21910+ 0x2B, 0x00,
21911+ 0x00, 0xE0,
21912+
21913+ 0x0C, 0x00,
21914+ 0x1C, 0x00,
21915+ 0x2C, 0x00,
21916+ 0x00, 0xE0,
21917+
21918+ 0x0B, 0x65,
21919+ 0x1B, 0x65,
21920+ 0x2B, 0x65,
21921+ 0x00, 0xE0,
21922+
21923+ 0x0C, 0x65,
21924+ 0x1C, 0x65,
21925+ 0x2C, 0x65,
21926+ 0x00, 0xE0,
21927+
21928+ 0x0B, 0x1B, 0x60, 0xEC,
21929+ 0x34, 0xD7, 0x34, 0xAD,
21930+
21931+ 0x2B, 0x80, 0x60, 0xEC,
21932+ 0x0C, 0x1C, 0x60, 0xEC,
21933+
21934+ 0x3C, 0xD7, 0x3C, 0xAD,
21935+ 0x2C, 0x80, 0x60, 0xEC,
21936+
21937+ 0x0B, 0x2B, 0xDE, 0xE8,
21938+ 0x1B, 0x80, 0xDE, 0xE8,
21939+
21940+ 0x34, 0x80, 0x34, 0xBD,
21941+ 0x3C, 0x80, 0x3C, 0xBD,
21942+
21943+ 0x33, 0xD7, 0x0B, 0xBD,
21944+ 0x3B, 0xD7, 0x1B, 0xBD,
21945+
21946+ 0x48, 0x80, 0x48, 0xCF,
21947+ 0x59, 0x80, 0x59, 0xCF,
21948+
21949+ 0x68, 0x33, 0x68, 0xCF,
21950+ 0x49, 0x3B, 0x49, 0xCF,
21951+
21952+ 0xB5, 0xFF, 0x20, 0xEA,
21953+ 0x00, 0x80, 0x00, 0xE8,
21954+
21955+ 0x58, 0x33, 0x58, 0xCF,
21956+ 0x69, 0x3B, 0x69, 0xCF,
21957+
21958+ 0x74, 0xFF, 0x20, 0xEA,
21959+ 0x57, 0xC0, 0xBF, 0xEA,
21960+
21961+ 0x00, 0x80, 0xA0, 0xE9,
21962+ 0x00, 0x00, 0xD8, 0xEC,
21963+
21964+};
21965+
21966+static unsigned char warp_g400_t2gzf[] = {
21967+
21968+ 0x00, 0x8A, 0x98, 0xE9,
21969+ 0x00, 0x80, 0x00, 0xE8,
21970+
21971+ 0x00, 0x80, 0xA0, 0xE9,
21972+ 0x00, 0x00, 0xD8, 0xEC,
21973+
21974+ 0xFF, 0x80, 0xC0, 0xE9,
21975+ 0x00, 0x80, 0x00, 0xE8,
21976+
21977+ 0x0A, 0x40, 0x50, 0xBF,
21978+ 0x2A, 0x40, 0x60, 0xBF,
21979+
21980+ 0x32, 0x41, 0x51, 0xBF,
21981+ 0x3A, 0x41, 0x61, 0xBF,
21982+
21983+ 0xC3, 0x6B,
21984+ 0xD3, 0x6B,
21985+ 0x00, 0x8A, 0x98, 0xE9,
21986+
21987+ 0x73, 0x7B, 0xC8, 0xEC,
21988+ 0x96, 0xE2,
21989+ 0x41, 0x04,
21990+
21991+ 0x7B, 0x43, 0xA0, 0xE8,
21992+ 0x73, 0x53, 0xA0, 0xE8,
21993+
21994+ 0xAD, 0xEE, 0x23, 0x9F,
21995+ 0x00, 0xE0,
21996+ 0x51, 0x04,
21997+
21998+ 0x90, 0xE2,
21999+ 0x61, 0x04,
22000+ 0x31, 0x46, 0xB1, 0xE8,
22001+
22002+ 0x51, 0x41, 0xE0, 0xEC,
22003+ 0x39, 0x67, 0xB1, 0xE8,
22004+
22005+ 0x00, 0x04,
22006+ 0x46, 0xE2,
22007+ 0x73, 0x63, 0xA0, 0xE8,
22008+
22009+ 0x61, 0x41, 0xE0, 0xEC,
22010+ 0x31, 0x00,
22011+ 0x39, 0x00,
22012+
22013+ 0x7D, 0x80, 0x15, 0xEA,
22014+ 0x10, 0x04,
22015+ 0x20, 0x04,
22016+
22017+ 0x61, 0x51, 0xE0, 0xEC,
22018+ 0x2F, 0x41, 0x60, 0xEA,
22019+
22020+ 0x31, 0x20,
22021+ 0x39, 0x20,
22022+ 0x1F, 0x42, 0xA0, 0xE8,
22023+
22024+ 0x2A, 0x42, 0x52, 0xBF,
22025+ 0x0F, 0x52, 0xA0, 0xE8,
22026+
22027+ 0x1A, 0x42, 0x62, 0xBF,
22028+ 0x1E, 0x51, 0x60, 0xEA,
22029+
22030+ 0x73, 0x7B, 0xC8, 0xEC,
22031+ 0x0E, 0x61, 0x60, 0xEA,
22032+
22033+ 0x32, 0x40, 0x50, 0xBD,
22034+ 0x22, 0x40, 0x60, 0xBD,
22035+
22036+ 0x12, 0x41, 0x51, 0xBD,
22037+ 0x3A, 0x41, 0x61, 0xBD,
22038+
22039+ 0xBF, 0x2F, 0x0E, 0xBD,
22040+ 0x97, 0xE2,
22041+ 0x7B, 0x72,
22042+
22043+ 0x32, 0x20,
22044+ 0x22, 0x20,
22045+ 0x12, 0x20,
22046+ 0x3A, 0x20,
22047+
22048+ 0x35, 0x48, 0xB1, 0xE8,
22049+ 0x3D, 0x59, 0xB1, 0xE8,
22050+
22051+ 0x46, 0x31, 0x46, 0xBF,
22052+ 0x56, 0x31, 0x56, 0xBF,
22053+
22054+ 0xB3, 0xE2, 0x2D, 0x9F,
22055+ 0x00, 0x80, 0x00, 0xE8,
22056+
22057+ 0x66, 0x31, 0x66, 0xBF,
22058+ 0x47, 0x39, 0x47, 0xBF,
22059+
22060+ 0x57, 0x39, 0x57, 0xBF,
22061+ 0x67, 0x39, 0x67, 0xBF,
22062+
22063+ 0x6E, 0x80, 0x07, 0xEA,
22064+ 0x24, 0x41, 0x20, 0xE9,
22065+
22066+ 0x35, 0x00,
22067+ 0x3D, 0x00,
22068+ 0x00, 0xE0,
22069+ 0x2D, 0x73,
22070+
22071+ 0x33, 0x72,
22072+ 0x0C, 0xE3,
22073+ 0x8D, 0x2F, 0x1E, 0xBD,
22074+
22075+ 0x43, 0x75, 0xF8, 0xEC,
22076+ 0x35, 0x20,
22077+ 0x3D, 0x20,
22078+
22079+ 0x43, 0x43, 0x2D, 0xDF,
22080+ 0x53, 0x53, 0x2D, 0xDF,
22081+
22082+ 0xAE, 0x1E, 0x0E, 0xBD,
22083+ 0x58, 0xE3,
22084+ 0x33, 0x66,
22085+
22086+ 0x48, 0x35, 0x48, 0xBF,
22087+ 0x58, 0x35, 0x58, 0xBF,
22088+
22089+ 0x68, 0x35, 0x68, 0xBF,
22090+ 0x49, 0x3D, 0x49, 0xBF,
22091+
22092+ 0x59, 0x3D, 0x59, 0xBF,
22093+ 0x69, 0x3D, 0x69, 0xBF,
22094+
22095+ 0x63, 0x63, 0x2D, 0xDF,
22096+ 0x4D, 0x7D, 0xF8, 0xEC,
22097+
22098+ 0x59, 0xE3,
22099+ 0x00, 0xE0,
22100+ 0xB8, 0x38, 0x33, 0xBF,
22101+
22102+ 0x2D, 0x73,
22103+ 0x30, 0x76,
22104+ 0x18, 0x3A, 0x41, 0xE9,
22105+
22106+ 0x3F, 0x53, 0xA0, 0xE8,
22107+ 0x05, 0x80, 0x3D, 0xEA,
22108+
22109+ 0x37, 0x43, 0xA0, 0xE8,
22110+ 0x3D, 0x63, 0xA0, 0xE8,
22111+
22112+ 0x50, 0x70, 0xF8, 0xEC,
22113+ 0x2B, 0x50, 0x3C, 0xE9,
22114+
22115+ 0x1F, 0x0F, 0xBC, 0xE8,
22116+ 0x00, 0x80, 0x00, 0xE8,
22117+
22118+ 0x59, 0x78, 0xF8, 0xEC,
22119+ 0x00, 0x80, 0x00, 0xE8,
22120+
22121+ 0x15, 0xC0, 0x20, 0xE9,
22122+ 0x15, 0xC0, 0x20, 0xE9,
22123+
22124+ 0x15, 0xC0, 0x20, 0xE9,
22125+ 0x15, 0xC0, 0x20, 0xE9,
22126+
22127+ 0x1E, 0x12, 0x41, 0xE9,
22128+ 0x1A, 0x22, 0x41, 0xE9,
22129+
22130+ 0x46, 0x37, 0x46, 0xDF,
22131+ 0x56, 0x3F, 0x56, 0xDF,
22132+
22133+ 0x2B, 0x40, 0x3D, 0xE9,
22134+ 0x66, 0x3D, 0x66, 0xDF,
22135+
22136+ 0x1D, 0x32, 0x41, 0xE9,
22137+ 0x67, 0x3D, 0x67, 0xDF,
22138+
22139+ 0x47, 0x37, 0x47, 0xDF,
22140+ 0x57, 0x3F, 0x57, 0xDF,
22141+
22142+ 0x2A, 0x40, 0x20, 0xE9,
22143+ 0x59, 0x3F, 0x59, 0xDF,
22144+
22145+ 0x16, 0x30, 0x20, 0xE9,
22146+ 0x69, 0x3D, 0x69, 0xDF,
22147+
22148+ 0x48, 0x37, 0x48, 0xDF,
22149+ 0x58, 0x3F, 0x58, 0xDF,
22150+
22151+ 0x12, 0x12, 0x2D, 0xDF,
22152+ 0x22, 0x22, 0x2D, 0xDF,
22153+
22154+ 0x32, 0x32, 0x2D, 0xDF,
22155+ 0x3A, 0x3A, 0x2D, 0xDF,
22156+
22157+ 0x68, 0x3D, 0x68, 0xDF,
22158+ 0x49, 0x37, 0x49, 0xDF,
22159+
22160+ 0x3D, 0xCF, 0x74, 0xC0,
22161+ 0x37, 0xCF, 0x74, 0xC4,
22162+
22163+ 0x39, 0xE5, 0x2C, 0x9F,
22164+ 0x34, 0x80, 0x20, 0xE9,
22165+
22166+ 0x31, 0x53, 0x2F, 0x9F,
22167+ 0x00, 0x80, 0x00, 0xE8,
22168+
22169+ 0x88, 0x73, 0x5E, 0xE9,
22170+ 0x00, 0x80, 0x00, 0xE8,
22171+
22172+ 0x0F, 0xCF, 0x75, 0xC6,
22173+ 0x3C, 0x3D, 0x20, 0xE9,
22174+
22175+ 0x0A, 0x44, 0x54, 0xB0,
22176+ 0x02, 0x44, 0x64, 0xB0,
22177+
22178+ 0x2A, 0x44, 0x54, 0xB2,
22179+ 0x1A, 0x44, 0x64, 0xB2,
22180+
22181+ 0x28, 0x80, 0x3A, 0xEA,
22182+ 0x0A, 0x20,
22183+ 0x02, 0x20,
22184+
22185+ 0x3D, 0xCF, 0x74, 0xC2,
22186+ 0x2A, 0x20,
22187+ 0x1A, 0x20,
22188+
22189+ 0x30, 0x50, 0x2E, 0x9F,
22190+ 0x32, 0x31, 0x5F, 0xE9,
22191+
22192+ 0x38, 0x21, 0x2C, 0x9F,
22193+ 0x33, 0x39, 0x5F, 0xE9,
22194+
22195+ 0x31, 0x53, 0x2F, 0x9F,
22196+ 0x31, 0x0F, 0x20, 0xE9,
22197+
22198+ 0x0A, 0x44, 0x54, 0xB4,
22199+ 0x02, 0x44, 0x64, 0xB4,
22200+
22201+ 0x2A, 0x45, 0x55, 0xB6,
22202+ 0x1A, 0x45, 0x65, 0xB6,
22203+
22204+ 0x39, 0xE5, 0x2C, 0x9F,
22205+ 0x38, 0x3D, 0x20, 0xE9,
22206+
22207+ 0x0A, 0x20,
22208+ 0x02, 0x20,
22209+ 0x2A, 0x20,
22210+ 0x1A, 0x20,
22211+
22212+ 0x0A, 0x47, 0x57, 0xBF,
22213+ 0x02, 0x47, 0x67, 0xBF,
22214+
22215+ 0x30, 0x50, 0x2E, 0x9F,
22216+ 0x3E, 0x30, 0x4F, 0xE9,
22217+
22218+ 0x38, 0x21, 0x2C, 0x9F,
22219+ 0x3F, 0x38, 0x4F, 0xE9,
22220+
22221+ 0x2A, 0x46, 0x56, 0xBF,
22222+ 0x1A, 0x46, 0x66, 0xBF,
22223+
22224+ 0x31, 0x53, 0x2F, 0x9F,
22225+ 0x3A, 0x31, 0x4F, 0xE9,
22226+
22227+ 0x39, 0xE5, 0x2C, 0x9F,
22228+ 0x3B, 0x39, 0x4F, 0xE9,
22229+
22230+ 0x31, 0x53, 0x2F, 0x9F,
22231+ 0x36, 0x30, 0x4F, 0xE9,
22232+
22233+ 0x39, 0xE5, 0x2C, 0x9F,
22234+ 0x37, 0x38, 0x4F, 0xE9,
22235+
22236+ 0x2A, 0x43, 0x53, 0xBF,
22237+ 0x1A, 0x43, 0x63, 0xBF,
22238+
22239+ 0x30, 0x50, 0x2E, 0x9F,
22240+ 0x35, 0x31, 0x4F, 0xE9,
22241+
22242+ 0x38, 0x21, 0x2C, 0x9F,
22243+ 0x39, 0x39, 0x4F, 0xE9,
22244+
22245+ 0x0A, 0x48, 0x58, 0xBF,
22246+ 0x02, 0x48, 0x68, 0xBF,
22247+
22248+ 0x31, 0x53, 0x2F, 0x9F,
22249+ 0x80, 0x31, 0x57, 0xE9,
22250+
22251+ 0x39, 0xE5, 0x2C, 0x9F,
22252+ 0x81, 0x39, 0x57, 0xE9,
22253+
22254+ 0x2A, 0x49, 0x59, 0xBF,
22255+ 0x1A, 0x49, 0x69, 0xBF,
22256+
22257+ 0x30, 0x50, 0x2E, 0x9F,
22258+ 0x82, 0x30, 0x57, 0xE9,
22259+
22260+ 0x38, 0x21, 0x2C, 0x9F,
22261+ 0x83, 0x38, 0x57, 0xE9,
22262+
22263+ 0x31, 0x53, 0x2F, 0x9F,
22264+ 0x84, 0x31, 0x5E, 0xE9,
22265+
22266+ 0x39, 0xE5, 0x2C, 0x9F,
22267+ 0x85, 0x39, 0x5E, 0xE9,
22268+
22269+ 0x86, 0x76, 0x57, 0xE9,
22270+ 0x8A, 0x36, 0x20, 0xE9,
22271+
22272+ 0x87, 0x77, 0x57, 0xE9,
22273+ 0x8B, 0x3E, 0xBF, 0xEA,
22274+
22275+ 0x80, 0x30, 0x57, 0xE9,
22276+ 0x81, 0x38, 0x57, 0xE9,
22277+
22278+ 0x82, 0x31, 0x57, 0xE9,
22279+ 0x86, 0x78, 0x57, 0xE9,
22280+
22281+ 0x83, 0x39, 0x57, 0xE9,
22282+ 0x87, 0x79, 0x57, 0xE9,
22283+
22284+ 0x30, 0x1F, 0x5F, 0xE9,
22285+ 0x8A, 0x34, 0x20, 0xE9,
22286+
22287+ 0x8B, 0x3C, 0x20, 0xE9,
22288+ 0x37, 0x50, 0x60, 0xBD,
22289+
22290+ 0x57, 0x0D, 0x20, 0xE9,
22291+ 0x35, 0x51, 0x61, 0xBD,
22292+
22293+ 0x2B, 0x50, 0x20, 0xE9,
22294+ 0x1D, 0x37, 0xE1, 0xEA,
22295+
22296+ 0x1E, 0x35, 0xE1, 0xEA,
22297+ 0x00, 0xE0,
22298+ 0x0E, 0x77,
22299+
22300+ 0x24, 0x51, 0x20, 0xE9,
22301+ 0x9A, 0xFF, 0x20, 0xEA,
22302+
22303+ 0x16, 0x0E, 0x20, 0xE9,
22304+ 0x57, 0x2E, 0xBF, 0xEA,
22305+
22306+ 0x0B, 0x46, 0xA0, 0xE8,
22307+ 0x1B, 0x56, 0xA0, 0xE8,
22308+
22309+ 0x2B, 0x66, 0xA0, 0xE8,
22310+ 0x0C, 0x47, 0xA0, 0xE8,
22311+
22312+ 0x1C, 0x57, 0xA0, 0xE8,
22313+ 0x2C, 0x67, 0xA0, 0xE8,
22314+
22315+ 0x0B, 0x00,
22316+ 0x1B, 0x00,
22317+ 0x2B, 0x00,
22318+ 0x00, 0xE0,
22319+
22320+ 0x0C, 0x00,
22321+ 0x1C, 0x00,
22322+ 0x2C, 0x00,
22323+ 0x00, 0xE0,
22324+
22325+ 0x0B, 0x65,
22326+ 0x1B, 0x65,
22327+ 0x2B, 0x65,
22328+ 0x00, 0xE0,
22329+
22330+ 0x0C, 0x65,
22331+ 0x1C, 0x65,
22332+ 0x2C, 0x65,
22333+ 0x00, 0xE0,
22334+
22335+ 0x0B, 0x1B, 0x60, 0xEC,
22336+ 0x36, 0xD7, 0x36, 0xAD,
22337+
22338+ 0x2B, 0x80, 0x60, 0xEC,
22339+ 0x0C, 0x1C, 0x60, 0xEC,
22340+
22341+ 0x3E, 0xD7, 0x3E, 0xAD,
22342+ 0x2C, 0x80, 0x60, 0xEC,
22343+
22344+ 0x0B, 0x2B, 0xDE, 0xE8,
22345+ 0x1B, 0x80, 0xDE, 0xE8,
22346+
22347+ 0x36, 0x80, 0x36, 0xBD,
22348+ 0x3E, 0x80, 0x3E, 0xBD,
22349+
22350+ 0x33, 0xD7, 0x0B, 0xBD,
22351+ 0x3B, 0xD7, 0x1B, 0xBD,
22352+
22353+ 0x46, 0x80, 0x46, 0xCF,
22354+ 0x57, 0x80, 0x57, 0xCF,
22355+
22356+ 0x66, 0x33, 0x66, 0xCF,
22357+ 0x47, 0x3B, 0x47, 0xCF,
22358+
22359+ 0x56, 0x33, 0x56, 0xCF,
22360+ 0x67, 0x3B, 0x67, 0xCF,
22361+
22362+ 0x0B, 0x48, 0xA0, 0xE8,
22363+ 0x1B, 0x58, 0xA0, 0xE8,
22364+
22365+ 0x2B, 0x68, 0xA0, 0xE8,
22366+ 0x0C, 0x49, 0xA0, 0xE8,
22367+
22368+ 0x1C, 0x59, 0xA0, 0xE8,
22369+ 0x2C, 0x69, 0xA0, 0xE8,
22370+
22371+ 0x0B, 0x00,
22372+ 0x1B, 0x00,
22373+ 0x2B, 0x00,
22374+ 0x00, 0xE0,
22375+
22376+ 0x0C, 0x00,
22377+ 0x1C, 0x00,
22378+ 0x2C, 0x00,
22379+ 0x00, 0xE0,
22380+
22381+ 0x0B, 0x65,
22382+ 0x1B, 0x65,
22383+ 0x2B, 0x65,
22384+ 0x00, 0xE0,
22385+
22386+ 0x0C, 0x65,
22387+ 0x1C, 0x65,
22388+ 0x2C, 0x65,
22389+ 0x00, 0xE0,
22390+
22391+ 0x0B, 0x1B, 0x60, 0xEC,
22392+ 0x34, 0xD7, 0x34, 0xAD,
22393+
22394+ 0x2B, 0x80, 0x60, 0xEC,
22395+ 0x0C, 0x1C, 0x60, 0xEC,
22396+
22397+ 0x3C, 0xD7, 0x3C, 0xAD,
22398+ 0x2C, 0x80, 0x60, 0xEC,
22399+
22400+ 0x0B, 0x2B, 0xDE, 0xE8,
22401+ 0x1B, 0x80, 0xDE, 0xE8,
22402+
22403+ 0x34, 0x80, 0x34, 0xBD,
22404+ 0x3C, 0x80, 0x3C, 0xBD,
22405+
22406+ 0x33, 0xD7, 0x0B, 0xBD,
22407+ 0x3B, 0xD7, 0x1B, 0xBD,
22408+
22409+ 0x48, 0x80, 0x48, 0xCF,
22410+ 0x59, 0x80, 0x59, 0xCF,
22411+
22412+ 0x68, 0x33, 0x68, 0xCF,
22413+ 0x49, 0x3B, 0x49, 0xCF,
22414+
22415+ 0xBB, 0xFF, 0x20, 0xEA,
22416+ 0x00, 0x80, 0x00, 0xE8,
22417+
22418+ 0x58, 0x33, 0x58, 0xCF,
22419+ 0x69, 0x3B, 0x69, 0xCF,
22420+
22421+ 0x78, 0xFF, 0x20, 0xEA,
22422+ 0x57, 0xC0, 0xBF, 0xEA,
22423+
22424+ 0x00, 0x80, 0xA0, 0xE9,
22425+ 0x00, 0x00, 0xD8, 0xEC,
22426+
22427+};
22428+
22429+static unsigned char warp_g400_t2gzs[] = {
22430+
22431+ 0x00, 0x8A, 0x98, 0xE9,
22432+ 0x00, 0x80, 0x00, 0xE8,
22433+
22434+ 0x00, 0x80, 0xA0, 0xE9,
22435+ 0x00, 0x00, 0xD8, 0xEC,
22436+
22437+ 0xFF, 0x80, 0xC0, 0xE9,
22438+ 0x00, 0x80, 0x00, 0xE8,
22439+
22440+ 0x0A, 0x40, 0x50, 0xBF,
22441+ 0x2A, 0x40, 0x60, 0xBF,
22442+
22443+ 0x32, 0x41, 0x51, 0xBF,
22444+ 0x3A, 0x41, 0x61, 0xBF,
22445+
22446+ 0xC3, 0x6B,
22447+ 0xD3, 0x6B,
22448+ 0x00, 0x8A, 0x98, 0xE9,
22449+
22450+ 0x73, 0x7B, 0xC8, 0xEC,
22451+ 0x96, 0xE2,
22452+ 0x41, 0x04,
22453+
22454+ 0x7B, 0x43, 0xA0, 0xE8,
22455+ 0x73, 0x53, 0xA0, 0xE8,
22456+
22457+ 0xAD, 0xEE, 0x23, 0x9F,
22458+ 0x00, 0xE0,
22459+ 0x51, 0x04,
22460+
22461+ 0x90, 0xE2,
22462+ 0x61, 0x04,
22463+ 0x31, 0x46, 0xB1, 0xE8,
22464+
22465+ 0x51, 0x41, 0xE0, 0xEC,
22466+ 0x39, 0x67, 0xB1, 0xE8,
22467+
22468+ 0x00, 0x04,
22469+ 0x46, 0xE2,
22470+ 0x73, 0x63, 0xA0, 0xE8,
22471+
22472+ 0x61, 0x41, 0xE0, 0xEC,
22473+ 0x31, 0x00,
22474+ 0x39, 0x00,
22475+
22476+ 0x85, 0x80, 0x15, 0xEA,
22477+ 0x10, 0x04,
22478+ 0x20, 0x04,
22479+
22480+ 0x61, 0x51, 0xE0, 0xEC,
22481+ 0x2F, 0x41, 0x60, 0xEA,
22482+
22483+ 0x31, 0x20,
22484+ 0x39, 0x20,
22485+ 0x1F, 0x42, 0xA0, 0xE8,
22486+
22487+ 0x2A, 0x42, 0x52, 0xBF,
22488+ 0x0F, 0x52, 0xA0, 0xE8,
22489+
22490+ 0x1A, 0x42, 0x62, 0xBF,
22491+ 0x1E, 0x51, 0x60, 0xEA,
22492+
22493+ 0x73, 0x7B, 0xC8, 0xEC,
22494+ 0x0E, 0x61, 0x60, 0xEA,
22495+
22496+ 0x32, 0x40, 0x50, 0xBD,
22497+ 0x22, 0x40, 0x60, 0xBD,
22498+
22499+ 0x12, 0x41, 0x51, 0xBD,
22500+ 0x3A, 0x41, 0x61, 0xBD,
22501+
22502+ 0xBF, 0x2F, 0x0E, 0xBD,
22503+ 0x97, 0xE2,
22504+ 0x7B, 0x72,
22505+
22506+ 0x32, 0x20,
22507+ 0x22, 0x20,
22508+ 0x12, 0x20,
22509+ 0x3A, 0x20,
22510+
22511+ 0x35, 0x48, 0xB1, 0xE8,
22512+ 0x3D, 0x59, 0xB1, 0xE8,
22513+
22514+ 0x46, 0x31, 0x46, 0xBF,
22515+ 0x56, 0x31, 0x56, 0xBF,
22516+
22517+ 0xB3, 0xE2, 0x2D, 0x9F,
22518+ 0x00, 0x80, 0x00, 0xE8,
22519+
22520+ 0x66, 0x31, 0x66, 0xBF,
22521+ 0x47, 0x39, 0x47, 0xBF,
22522+
22523+ 0x57, 0x39, 0x57, 0xBF,
22524+ 0x67, 0x39, 0x67, 0xBF,
22525+
22526+ 0x76, 0x80, 0x07, 0xEA,
22527+ 0x24, 0x41, 0x20, 0xE9,
22528+
22529+ 0x35, 0x00,
22530+ 0x3D, 0x00,
22531+ 0x00, 0xE0,
22532+ 0x2D, 0x73,
22533+
22534+ 0x33, 0x72,
22535+ 0x0C, 0xE3,
22536+ 0x8D, 0x2F, 0x1E, 0xBD,
22537+
22538+ 0x43, 0x75, 0xF8, 0xEC,
22539+ 0x35, 0x20,
22540+ 0x3D, 0x20,
22541+
22542+ 0x43, 0x43, 0x2D, 0xDF,
22543+ 0x53, 0x53, 0x2D, 0xDF,
22544+
22545+ 0xAE, 0x1E, 0x0E, 0xBD,
22546+ 0x58, 0xE3,
22547+ 0x33, 0x66,
22548+
22549+ 0x48, 0x35, 0x48, 0xBF,
22550+ 0x58, 0x35, 0x58, 0xBF,
22551+
22552+ 0x68, 0x35, 0x68, 0xBF,
22553+ 0x49, 0x3D, 0x49, 0xBF,
22554+
22555+ 0x59, 0x3D, 0x59, 0xBF,
22556+ 0x69, 0x3D, 0x69, 0xBF,
22557+
22558+ 0x63, 0x63, 0x2D, 0xDF,
22559+ 0x4D, 0x7D, 0xF8, 0xEC,
22560+
22561+ 0x59, 0xE3,
22562+ 0x00, 0xE0,
22563+ 0xB8, 0x38, 0x33, 0xBF,
22564+
22565+ 0x2D, 0x73,
22566+ 0x30, 0x76,
22567+ 0x18, 0x3A, 0x41, 0xE9,
22568+
22569+ 0x3F, 0x53, 0xA0, 0xE8,
22570+ 0x05, 0x80, 0x3D, 0xEA,
22571+
22572+ 0x37, 0x43, 0xA0, 0xE8,
22573+ 0x3D, 0x63, 0xA0, 0xE8,
22574+
22575+ 0x50, 0x70, 0xF8, 0xEC,
22576+ 0x2B, 0x50, 0x3C, 0xE9,
22577+
22578+ 0x1F, 0x0F, 0xBC, 0xE8,
22579+ 0x00, 0x80, 0x00, 0xE8,
22580+
22581+ 0x59, 0x78, 0xF8, 0xEC,
22582+ 0x00, 0x80, 0x00, 0xE8,
22583+
22584+ 0x15, 0xC0, 0x20, 0xE9,
22585+ 0x15, 0xC0, 0x20, 0xE9,
22586+
22587+ 0x15, 0xC0, 0x20, 0xE9,
22588+ 0x15, 0xC0, 0x20, 0xE9,
22589+
22590+ 0x1E, 0x12, 0x41, 0xE9,
22591+ 0x1A, 0x22, 0x41, 0xE9,
22592+
22593+ 0x46, 0x37, 0x46, 0xDF,
22594+ 0x56, 0x3F, 0x56, 0xDF,
22595+
22596+ 0x2B, 0x40, 0x3D, 0xE9,
22597+ 0x66, 0x3D, 0x66, 0xDF,
22598+
22599+ 0x1D, 0x32, 0x41, 0xE9,
22600+ 0x67, 0x3D, 0x67, 0xDF,
22601+
22602+ 0x47, 0x37, 0x47, 0xDF,
22603+ 0x57, 0x3F, 0x57, 0xDF,
22604+
22605+ 0x2A, 0x40, 0x20, 0xE9,
22606+ 0x59, 0x3F, 0x59, 0xDF,
22607+
22608+ 0x16, 0x30, 0x20, 0xE9,
22609+ 0x69, 0x3D, 0x69, 0xDF,
22610+
22611+ 0x48, 0x37, 0x48, 0xDF,
22612+ 0x58, 0x3F, 0x58, 0xDF,
22613+
22614+ 0x68, 0x3D, 0x68, 0xDF,
22615+ 0x49, 0x37, 0x49, 0xDF,
22616+
22617+ 0x32, 0x32, 0x2D, 0xDF,
22618+ 0x22, 0x22, 0x2D, 0xDF,
22619+
22620+ 0x12, 0x12, 0x2D, 0xDF,
22621+ 0x3A, 0x3A, 0x2D, 0xDF,
22622+
22623+ 0x0F, 0xCF, 0x74, 0xC2,
22624+ 0x37, 0xCF, 0x74, 0xC4,
22625+
22626+ 0x0A, 0x44, 0x54, 0xB0,
22627+ 0x02, 0x44, 0x64, 0xB0,
22628+
22629+ 0x3D, 0xCF, 0x74, 0xC0,
22630+ 0x34, 0x37, 0x20, 0xE9,
22631+
22632+ 0x31, 0x53, 0x2F, 0x9F,
22633+ 0x38, 0x0F, 0x20, 0xE9,
22634+
22635+ 0x39, 0xE5, 0x2C, 0x9F,
22636+ 0x3C, 0x3D, 0x20, 0xE9,
22637+
22638+ 0x2A, 0x44, 0x54, 0xB2,
22639+ 0x1A, 0x44, 0x64, 0xB2,
22640+
22641+ 0x31, 0x80, 0x3A, 0xEA,
22642+ 0x0A, 0x20,
22643+ 0x02, 0x20,
22644+
22645+ 0x0F, 0xCF, 0x75, 0xC0,
22646+ 0x2A, 0x20,
22647+ 0x1A, 0x20,
22648+
22649+ 0x30, 0x50, 0x2E, 0x9F,
22650+ 0x32, 0x31, 0x5F, 0xE9,
22651+
22652+ 0x38, 0x21, 0x2C, 0x9F,
22653+ 0x33, 0x39, 0x5F, 0xE9,
22654+
22655+ 0x3D, 0xCF, 0x75, 0xC2,
22656+ 0x37, 0xCF, 0x75, 0xC4,
22657+
22658+ 0x31, 0x53, 0x2F, 0x9F,
22659+ 0xA6, 0x0F, 0x20, 0xE9,
22660+
22661+ 0x39, 0xE5, 0x2C, 0x9F,
22662+ 0xA3, 0x3D, 0x20, 0xE9,
22663+
22664+ 0x2A, 0x44, 0x54, 0xB4,
22665+ 0x1A, 0x44, 0x64, 0xB4,
22666+
22667+ 0x0A, 0x45, 0x55, 0xB0,
22668+ 0x02, 0x45, 0x65, 0xB0,
22669+
22670+ 0x88, 0x73, 0x5E, 0xE9,
22671+ 0x2A, 0x20,
22672+ 0x1A, 0x20,
22673+
22674+ 0xA0, 0x37, 0x20, 0xE9,
22675+ 0x0A, 0x20,
22676+ 0x02, 0x20,
22677+
22678+ 0x31, 0x53, 0x2F, 0x9F,
22679+ 0x3E, 0x30, 0x4F, 0xE9,
22680+
22681+ 0x39, 0xE5, 0x2C, 0x9F,
22682+ 0x3F, 0x38, 0x4F, 0xE9,
22683+
22684+ 0x30, 0x50, 0x2E, 0x9F,
22685+ 0x3A, 0x31, 0x4F, 0xE9,
22686+
22687+ 0x2A, 0x45, 0x55, 0xB2,
22688+ 0x1A, 0x45, 0x65, 0xB2,
22689+
22690+ 0x0A, 0x45, 0x55, 0xB4,
22691+ 0x02, 0x45, 0x65, 0xB4,
22692+
22693+ 0x38, 0x21, 0x2C, 0x9F,
22694+ 0x3B, 0x39, 0x4F, 0xE9,
22695+
22696+ 0x2A, 0x20,
22697+ 0x1A, 0x20,
22698+ 0x0A, 0x20,
22699+ 0x02, 0x20,
22700+
22701+ 0x2A, 0x46, 0x56, 0xBF,
22702+ 0x1A, 0x46, 0x66, 0xBF,
22703+
22704+ 0x31, 0x53, 0x2F, 0x9F,
22705+ 0x36, 0x31, 0x4F, 0xE9,
22706+
22707+ 0x39, 0xE5, 0x2C, 0x9F,
22708+ 0x37, 0x39, 0x4F, 0xE9,
22709+
22710+ 0x30, 0x50, 0x2E, 0x9F,
22711+ 0xA7, 0x30, 0x4F, 0xE9,
22712+
22713+ 0x38, 0x21, 0x2C, 0x9F,
22714+ 0xA8, 0x38, 0x4F, 0xE9,
22715+
22716+ 0x0A, 0x47, 0x57, 0xBF,
22717+ 0x02, 0x47, 0x67, 0xBF,
22718+
22719+ 0x31, 0x53, 0x2F, 0x9F,
22720+ 0xA4, 0x31, 0x4F, 0xE9,
22721+
22722+ 0x39, 0xE5, 0x2C, 0x9F,
22723+ 0xA5, 0x39, 0x4F, 0xE9,
22724+
22725+ 0x2A, 0x43, 0x53, 0xBF,
22726+ 0x1A, 0x43, 0x63, 0xBF,
22727+
22728+ 0x30, 0x50, 0x2E, 0x9F,
22729+ 0xA1, 0x30, 0x4F, 0xE9,
22730+
22731+ 0x38, 0x21, 0x2C, 0x9F,
22732+ 0xA2, 0x38, 0x4F, 0xE9,
22733+
22734+ 0x0A, 0x48, 0x58, 0xBF,
22735+ 0x02, 0x48, 0x68, 0xBF,
22736+
22737+ 0x31, 0x53, 0x2F, 0x9F,
22738+ 0x80, 0x31, 0x57, 0xE9,
22739+
22740+ 0x39, 0xE5, 0x2C, 0x9F,
22741+ 0x81, 0x39, 0x57, 0xE9,
22742+
22743+ 0x2A, 0x49, 0x59, 0xBF,
22744+ 0x1A, 0x49, 0x69, 0xBF,
22745+
22746+ 0x30, 0x50, 0x2E, 0x9F,
22747+ 0x82, 0x30, 0x57, 0xE9,
22748+
22749+ 0x38, 0x21, 0x2C, 0x9F,
22750+ 0x83, 0x38, 0x57, 0xE9,
22751+
22752+ 0x31, 0x53, 0x2F, 0x9F,
22753+ 0x84, 0x31, 0x5E, 0xE9,
22754+
22755+ 0x39, 0xE5, 0x2C, 0x9F,
22756+ 0x85, 0x39, 0x5E, 0xE9,
22757+
22758+ 0x86, 0x76, 0x57, 0xE9,
22759+ 0x8A, 0x36, 0x20, 0xE9,
22760+
22761+ 0x87, 0x77, 0x57, 0xE9,
22762+ 0x8B, 0x3E, 0xBF, 0xEA,
22763+
22764+ 0x80, 0x30, 0x57, 0xE9,
22765+ 0x81, 0x38, 0x57, 0xE9,
22766+
22767+ 0x82, 0x31, 0x57, 0xE9,
22768+ 0x86, 0x78, 0x57, 0xE9,
22769+
22770+ 0x83, 0x39, 0x57, 0xE9,
22771+ 0x87, 0x79, 0x57, 0xE9,
22772+
22773+ 0x30, 0x1F, 0x5F, 0xE9,
22774+ 0x8A, 0x34, 0x20, 0xE9,
22775+
22776+ 0x8B, 0x3C, 0x20, 0xE9,
22777+ 0x37, 0x50, 0x60, 0xBD,
22778+
22779+ 0x57, 0x0D, 0x20, 0xE9,
22780+ 0x35, 0x51, 0x61, 0xBD,
22781+
22782+ 0x2B, 0x50, 0x20, 0xE9,
22783+ 0x1D, 0x37, 0xE1, 0xEA,
22784+
22785+ 0x1E, 0x35, 0xE1, 0xEA,
22786+ 0x00, 0xE0,
22787+ 0x0E, 0x77,
22788+
22789+ 0x24, 0x51, 0x20, 0xE9,
22790+ 0x92, 0xFF, 0x20, 0xEA,
22791+
22792+ 0x16, 0x0E, 0x20, 0xE9,
22793+ 0x57, 0x2E, 0xBF, 0xEA,
22794+
22795+ 0x0B, 0x46, 0xA0, 0xE8,
22796+ 0x1B, 0x56, 0xA0, 0xE8,
22797+
22798+ 0x2B, 0x66, 0xA0, 0xE8,
22799+ 0x0C, 0x47, 0xA0, 0xE8,
22800+
22801+ 0x1C, 0x57, 0xA0, 0xE8,
22802+ 0x2C, 0x67, 0xA0, 0xE8,
22803+
22804+ 0x0B, 0x00,
22805+ 0x1B, 0x00,
22806+ 0x2B, 0x00,
22807+ 0x00, 0xE0,
22808+
22809+ 0x0C, 0x00,
22810+ 0x1C, 0x00,
22811+ 0x2C, 0x00,
22812+ 0x00, 0xE0,
22813+
22814+ 0x0B, 0x65,
22815+ 0x1B, 0x65,
22816+ 0x2B, 0x65,
22817+ 0x00, 0xE0,
22818+
22819+ 0x0C, 0x65,
22820+ 0x1C, 0x65,
22821+ 0x2C, 0x65,
22822+ 0x00, 0xE0,
22823+
22824+ 0x0B, 0x1B, 0x60, 0xEC,
22825+ 0x36, 0xD7, 0x36, 0xAD,
22826+
22827+ 0x2B, 0x80, 0x60, 0xEC,
22828+ 0x0C, 0x1C, 0x60, 0xEC,
22829+
22830+ 0x3E, 0xD7, 0x3E, 0xAD,
22831+ 0x2C, 0x80, 0x60, 0xEC,
22832+
22833+ 0x0B, 0x2B, 0xDE, 0xE8,
22834+ 0x1B, 0x80, 0xDE, 0xE8,
22835+
22836+ 0x36, 0x80, 0x36, 0xBD,
22837+ 0x3E, 0x80, 0x3E, 0xBD,
22838+
22839+ 0x33, 0xD7, 0x0B, 0xBD,
22840+ 0x3B, 0xD7, 0x1B, 0xBD,
22841+
22842+ 0x46, 0x80, 0x46, 0xCF,
22843+ 0x57, 0x80, 0x57, 0xCF,
22844+
22845+ 0x66, 0x33, 0x66, 0xCF,
22846+ 0x47, 0x3B, 0x47, 0xCF,
22847+
22848+ 0x56, 0x33, 0x56, 0xCF,
22849+ 0x67, 0x3B, 0x67, 0xCF,
22850+
22851+ 0x0B, 0x48, 0xA0, 0xE8,
22852+ 0x1B, 0x58, 0xA0, 0xE8,
22853+
22854+ 0x2B, 0x68, 0xA0, 0xE8,
22855+ 0x0C, 0x49, 0xA0, 0xE8,
22856+
22857+ 0x1C, 0x59, 0xA0, 0xE8,
22858+ 0x2C, 0x69, 0xA0, 0xE8,
22859+
22860+ 0x0B, 0x00,
22861+ 0x1B, 0x00,
22862+ 0x2B, 0x00,
22863+ 0x00, 0xE0,
22864+
22865+ 0x0C, 0x00,
22866+ 0x1C, 0x00,
22867+ 0x2C, 0x00,
22868+ 0x00, 0xE0,
22869+
22870+ 0x0B, 0x65,
22871+ 0x1B, 0x65,
22872+ 0x2B, 0x65,
22873+ 0x00, 0xE0,
22874+
22875+ 0x0C, 0x65,
22876+ 0x1C, 0x65,
22877+ 0x2C, 0x65,
22878+ 0x00, 0xE0,
22879+
22880+ 0x0B, 0x1B, 0x60, 0xEC,
22881+ 0x34, 0xD7, 0x34, 0xAD,
22882+
22883+ 0x2B, 0x80, 0x60, 0xEC,
22884+ 0x0C, 0x1C, 0x60, 0xEC,
22885+
22886+ 0x3C, 0xD7, 0x3C, 0xAD,
22887+ 0x2C, 0x80, 0x60, 0xEC,
22888+
22889+ 0x0B, 0x2B, 0xDE, 0xE8,
22890+ 0x1B, 0x80, 0xDE, 0xE8,
22891+
22892+ 0x34, 0x80, 0x34, 0xBD,
22893+ 0x3C, 0x80, 0x3C, 0xBD,
22894+
22895+ 0x33, 0xD7, 0x0B, 0xBD,
22896+ 0x3B, 0xD7, 0x1B, 0xBD,
22897+
22898+ 0x48, 0x80, 0x48, 0xCF,
22899+ 0x59, 0x80, 0x59, 0xCF,
22900+
22901+ 0x68, 0x33, 0x68, 0xCF,
22902+ 0x49, 0x3B, 0x49, 0xCF,
22903+
22904+ 0xB2, 0xFF, 0x20, 0xEA,
22905+ 0x00, 0x80, 0x00, 0xE8,
22906+
22907+ 0x58, 0x33, 0x58, 0xCF,
22908+ 0x69, 0x3B, 0x69, 0xCF,
22909+
22910+ 0x70, 0xFF, 0x20, 0xEA,
22911+ 0x57, 0xC0, 0xBF, 0xEA,
22912+
22913+ 0x00, 0x80, 0xA0, 0xE9,
22914+ 0x00, 0x00, 0xD8, 0xEC,
22915+
22916+};
22917+
22918+static unsigned char warp_g400_t2gzsa[] = {
22919+
22920+ 0x00, 0x8A, 0x98, 0xE9,
22921+ 0x00, 0x80, 0x00, 0xE8,
22922+
22923+ 0x00, 0x80, 0xA0, 0xE9,
22924+ 0x00, 0x00, 0xD8, 0xEC,
22925+
22926+ 0xFF, 0x80, 0xC0, 0xE9,
22927+ 0x00, 0x80, 0x00, 0xE8,
22928+
22929+ 0x0A, 0x40, 0x50, 0xBF,
22930+ 0x2A, 0x40, 0x60, 0xBF,
22931+
22932+ 0x32, 0x41, 0x51, 0xBF,
22933+ 0x3A, 0x41, 0x61, 0xBF,
22934+
22935+ 0xC3, 0x6B,
22936+ 0xD3, 0x6B,
22937+ 0x00, 0x8A, 0x98, 0xE9,
22938+
22939+ 0x73, 0x7B, 0xC8, 0xEC,
22940+ 0x96, 0xE2,
22941+ 0x41, 0x04,
22942+
22943+ 0x7B, 0x43, 0xA0, 0xE8,
22944+ 0x73, 0x53, 0xA0, 0xE8,
22945+
22946+ 0xAD, 0xEE, 0x23, 0x9F,
22947+ 0x00, 0xE0,
22948+ 0x51, 0x04,
22949+
22950+ 0x90, 0xE2,
22951+ 0x61, 0x04,
22952+ 0x31, 0x46, 0xB1, 0xE8,
22953+
22954+ 0x51, 0x41, 0xE0, 0xEC,
22955+ 0x39, 0x67, 0xB1, 0xE8,
22956+
22957+ 0x00, 0x04,
22958+ 0x46, 0xE2,
22959+ 0x73, 0x63, 0xA0, 0xE8,
22960+
22961+ 0x61, 0x41, 0xE0, 0xEC,
22962+ 0x31, 0x00,
22963+ 0x39, 0x00,
22964+
22965+ 0x8A, 0x80, 0x15, 0xEA,
22966+ 0x10, 0x04,
22967+ 0x20, 0x04,
22968+
22969+ 0x61, 0x51, 0xE0, 0xEC,
22970+ 0x2F, 0x41, 0x60, 0xEA,
22971+
22972+ 0x31, 0x20,
22973+ 0x39, 0x20,
22974+ 0x1F, 0x42, 0xA0, 0xE8,
22975+
22976+ 0x2A, 0x42, 0x52, 0xBF,
22977+ 0x0F, 0x52, 0xA0, 0xE8,
22978+
22979+ 0x1A, 0x42, 0x62, 0xBF,
22980+ 0x1E, 0x51, 0x60, 0xEA,
22981+
22982+ 0x73, 0x7B, 0xC8, 0xEC,
22983+ 0x0E, 0x61, 0x60, 0xEA,
22984+
22985+ 0x32, 0x40, 0x50, 0xBD,
22986+ 0x22, 0x40, 0x60, 0xBD,
22987+
22988+ 0x12, 0x41, 0x51, 0xBD,
22989+ 0x3A, 0x41, 0x61, 0xBD,
22990+
22991+ 0xBF, 0x2F, 0x0E, 0xBD,
22992+ 0x97, 0xE2,
22993+ 0x7B, 0x72,
22994+
22995+ 0x32, 0x20,
22996+ 0x22, 0x20,
22997+ 0x12, 0x20,
22998+ 0x3A, 0x20,
22999+
23000+ 0x35, 0x48, 0xB1, 0xE8,
23001+ 0x3D, 0x59, 0xB1, 0xE8,
23002+
23003+ 0x46, 0x31, 0x46, 0xBF,
23004+ 0x56, 0x31, 0x56, 0xBF,
23005+
23006+ 0xB3, 0xE2, 0x2D, 0x9F,
23007+ 0x00, 0x80, 0x00, 0xE8,
23008+
23009+ 0x66, 0x31, 0x66, 0xBF,
23010+ 0x47, 0x39, 0x47, 0xBF,
23011+
23012+ 0x57, 0x39, 0x57, 0xBF,
23013+ 0x67, 0x39, 0x67, 0xBF,
23014+
23015+ 0x7B, 0x80, 0x07, 0xEA,
23016+ 0x24, 0x41, 0x20, 0xE9,
23017+
23018+ 0x35, 0x00,
23019+ 0x3D, 0x00,
23020+ 0x00, 0xE0,
23021+ 0x2D, 0x73,
23022+
23023+ 0x33, 0x72,
23024+ 0x0C, 0xE3,
23025+ 0x8D, 0x2F, 0x1E, 0xBD,
23026+
23027+ 0x43, 0x75, 0xF8, 0xEC,
23028+ 0x35, 0x20,
23029+ 0x3D, 0x20,
23030+
23031+ 0x43, 0x43, 0x2D, 0xDF,
23032+ 0x53, 0x53, 0x2D, 0xDF,
23033+
23034+ 0xAE, 0x1E, 0x0E, 0xBD,
23035+ 0x58, 0xE3,
23036+ 0x33, 0x66,
23037+
23038+ 0x48, 0x35, 0x48, 0xBF,
23039+ 0x58, 0x35, 0x58, 0xBF,
23040+
23041+ 0x68, 0x35, 0x68, 0xBF,
23042+ 0x49, 0x3D, 0x49, 0xBF,
23043+
23044+ 0x59, 0x3D, 0x59, 0xBF,
23045+ 0x69, 0x3D, 0x69, 0xBF,
23046+
23047+ 0x63, 0x63, 0x2D, 0xDF,
23048+ 0x4D, 0x7D, 0xF8, 0xEC,
23049+
23050+ 0x59, 0xE3,
23051+ 0x00, 0xE0,
23052+ 0xB8, 0x38, 0x33, 0xBF,
23053+
23054+ 0x2D, 0x73,
23055+ 0x30, 0x76,
23056+ 0x18, 0x3A, 0x41, 0xE9,
23057+
23058+ 0x3F, 0x53, 0xA0, 0xE8,
23059+ 0x05, 0x80, 0x3D, 0xEA,
23060+
23061+ 0x37, 0x43, 0xA0, 0xE8,
23062+ 0x3D, 0x63, 0xA0, 0xE8,
23063+
23064+ 0x50, 0x70, 0xF8, 0xEC,
23065+ 0x2B, 0x50, 0x3C, 0xE9,
23066+
23067+ 0x1F, 0x0F, 0xBC, 0xE8,
23068+ 0x00, 0x80, 0x00, 0xE8,
23069+
23070+ 0x59, 0x78, 0xF8, 0xEC,
23071+ 0x00, 0x80, 0x00, 0xE8,
23072+
23073+ 0x15, 0xC0, 0x20, 0xE9,
23074+ 0x15, 0xC0, 0x20, 0xE9,
23075+
23076+ 0x15, 0xC0, 0x20, 0xE9,
23077+ 0x15, 0xC0, 0x20, 0xE9,
23078+
23079+ 0x1E, 0x12, 0x41, 0xE9,
23080+ 0x1A, 0x22, 0x41, 0xE9,
23081+
23082+ 0x46, 0x37, 0x46, 0xDF,
23083+ 0x56, 0x3F, 0x56, 0xDF,
23084+
23085+ 0x2B, 0x40, 0x3D, 0xE9,
23086+ 0x66, 0x3D, 0x66, 0xDF,
23087+
23088+ 0x1D, 0x32, 0x41, 0xE9,
23089+ 0x67, 0x3D, 0x67, 0xDF,
23090+
23091+ 0x47, 0x37, 0x47, 0xDF,
23092+ 0x57, 0x3F, 0x57, 0xDF,
23093+
23094+ 0x2A, 0x40, 0x20, 0xE9,
23095+ 0x59, 0x3F, 0x59, 0xDF,
23096+
23097+ 0x16, 0x30, 0x20, 0xE9,
23098+ 0x69, 0x3D, 0x69, 0xDF,
23099+
23100+ 0x48, 0x37, 0x48, 0xDF,
23101+ 0x58, 0x3F, 0x58, 0xDF,
23102+
23103+ 0x68, 0x3D, 0x68, 0xDF,
23104+ 0x49, 0x37, 0x49, 0xDF,
23105+
23106+ 0x32, 0x32, 0x2D, 0xDF,
23107+ 0x22, 0x22, 0x2D, 0xDF,
23108+
23109+ 0x12, 0x12, 0x2D, 0xDF,
23110+ 0x3A, 0x3A, 0x2D, 0xDF,
23111+
23112+ 0x0F, 0xCF, 0x74, 0xC2,
23113+ 0x37, 0xCF, 0x74, 0xC4,
23114+
23115+ 0x0A, 0x44, 0x54, 0xB0,
23116+ 0x02, 0x44, 0x64, 0xB0,
23117+
23118+ 0x3D, 0xCF, 0x74, 0xC0,
23119+ 0x34, 0x37, 0x20, 0xE9,
23120+
23121+ 0x31, 0x53, 0x2F, 0x9F,
23122+ 0x38, 0x0F, 0x20, 0xE9,
23123+
23124+ 0x39, 0xE5, 0x2C, 0x9F,
23125+ 0x3C, 0x3D, 0x20, 0xE9,
23126+
23127+ 0x2A, 0x44, 0x54, 0xB2,
23128+ 0x1A, 0x44, 0x64, 0xB2,
23129+
23130+ 0x36, 0x80, 0x3A, 0xEA,
23131+ 0x0A, 0x20,
23132+ 0x02, 0x20,
23133+
23134+ 0x0F, 0xCF, 0x75, 0xC0,
23135+ 0x2A, 0x20,
23136+ 0x1A, 0x20,
23137+
23138+ 0x30, 0x50, 0x2E, 0x9F,
23139+ 0x32, 0x31, 0x5F, 0xE9,
23140+
23141+ 0x38, 0x21, 0x2C, 0x9F,
23142+ 0x33, 0x39, 0x5F, 0xE9,
23143+
23144+ 0x3D, 0xCF, 0x75, 0xC2,
23145+ 0x37, 0xCF, 0x75, 0xC4,
23146+
23147+ 0x31, 0x53, 0x2F, 0x9F,
23148+ 0xA6, 0x0F, 0x20, 0xE9,
23149+
23150+ 0x39, 0xE5, 0x2C, 0x9F,
23151+ 0xA3, 0x3D, 0x20, 0xE9,
23152+
23153+ 0x2A, 0x44, 0x54, 0xB4,
23154+ 0x1A, 0x44, 0x64, 0xB4,
23155+
23156+ 0x0A, 0x45, 0x55, 0xB0,
23157+ 0x02, 0x45, 0x65, 0xB0,
23158+
23159+ 0x88, 0x73, 0x5E, 0xE9,
23160+ 0x2A, 0x20,
23161+ 0x1A, 0x20,
23162+
23163+ 0xA0, 0x37, 0x20, 0xE9,
23164+ 0x0A, 0x20,
23165+ 0x02, 0x20,
23166+
23167+ 0x31, 0x53, 0x2F, 0x9F,
23168+ 0x3E, 0x30, 0x4F, 0xE9,
23169+
23170+ 0x39, 0xE5, 0x2C, 0x9F,
23171+ 0x3F, 0x38, 0x4F, 0xE9,
23172+
23173+ 0x30, 0x50, 0x2E, 0x9F,
23174+ 0x3A, 0x31, 0x4F, 0xE9,
23175+
23176+ 0x38, 0x21, 0x2C, 0x9F,
23177+ 0x3B, 0x39, 0x4F, 0xE9,
23178+
23179+ 0x2A, 0x45, 0x55, 0xB2,
23180+ 0x1A, 0x45, 0x65, 0xB2,
23181+
23182+ 0x0A, 0x45, 0x55, 0xB4,
23183+ 0x02, 0x45, 0x65, 0xB4,
23184+
23185+ 0x0F, 0xCF, 0x74, 0xC6,
23186+ 0x2A, 0x20,
23187+ 0x1A, 0x20,
23188+
23189+ 0xA7, 0x30, 0x4F, 0xE9,
23190+ 0x0A, 0x20,
23191+ 0x02, 0x20,
23192+
23193+ 0x31, 0x53, 0x2F, 0x9F,
23194+ 0x9C, 0x0F, 0x20, 0xE9,
23195+
23196+ 0x39, 0xE5, 0x2C, 0x9F,
23197+ 0xA8, 0x38, 0x4F, 0xE9,
23198+
23199+ 0x2A, 0x44, 0x54, 0xB6,
23200+ 0x1A, 0x44, 0x64, 0xB6,
23201+
23202+ 0x30, 0x50, 0x2E, 0x9F,
23203+ 0x36, 0x31, 0x4F, 0xE9,
23204+
23205+ 0x38, 0x21, 0x2C, 0x9F,
23206+ 0x37, 0x39, 0x4F, 0xE9,
23207+
23208+ 0x00, 0x80, 0x00, 0xE8,
23209+ 0x2A, 0x20,
23210+ 0x1A, 0x20,
23211+
23212+ 0x2A, 0x46, 0x56, 0xBF,
23213+ 0x1A, 0x46, 0x66, 0xBF,
23214+
23215+ 0x31, 0x53, 0x2F, 0x9F,
23216+ 0xA4, 0x31, 0x4F, 0xE9,
23217+
23218+ 0x39, 0xE5, 0x2C, 0x9F,
23219+ 0xA5, 0x39, 0x4F, 0xE9,
23220+
23221+ 0x0A, 0x47, 0x57, 0xBF,
23222+ 0x02, 0x47, 0x67, 0xBF,
23223+
23224+ 0x31, 0x53, 0x2F, 0x9F,
23225+ 0xA1, 0x30, 0x4F, 0xE9,
23226+
23227+ 0x39, 0xE5, 0x2C, 0x9F,
23228+ 0xA2, 0x38, 0x4F, 0xE9,
23229+
23230+ 0x2A, 0x43, 0x53, 0xBF,
23231+ 0x1A, 0x43, 0x63, 0xBF,
23232+
23233+ 0x30, 0x50, 0x2E, 0x9F,
23234+ 0x9D, 0x31, 0x4F, 0xE9,
23235+
23236+ 0x38, 0x21, 0x2C, 0x9F,
23237+ 0x9E, 0x39, 0x4F, 0xE9,
23238+
23239+ 0x0A, 0x48, 0x58, 0xBF,
23240+ 0x02, 0x48, 0x68, 0xBF,
23241+
23242+ 0x31, 0x53, 0x2F, 0x9F,
23243+ 0x80, 0x31, 0x57, 0xE9,
23244+
23245+ 0x39, 0xE5, 0x2C, 0x9F,
23246+ 0x81, 0x39, 0x57, 0xE9,
23247+
23248+ 0x2A, 0x49, 0x59, 0xBF,
23249+ 0x1A, 0x49, 0x69, 0xBF,
23250+
23251+ 0x30, 0x50, 0x2E, 0x9F,
23252+ 0x82, 0x30, 0x57, 0xE9,
23253+
23254+ 0x38, 0x21, 0x2C, 0x9F,
23255+ 0x83, 0x38, 0x57, 0xE9,
23256+
23257+ 0x31, 0x53, 0x2F, 0x9F,
23258+ 0x84, 0x31, 0x5E, 0xE9,
23259+
23260+ 0x39, 0xE5, 0x2C, 0x9F,
23261+ 0x85, 0x39, 0x5E, 0xE9,
23262+
23263+ 0x86, 0x76, 0x57, 0xE9,
23264+ 0x8A, 0x36, 0x20, 0xE9,
23265+
23266+ 0x87, 0x77, 0x57, 0xE9,
23267+ 0x8B, 0x3E, 0xBF, 0xEA,
23268+
23269+ 0x80, 0x30, 0x57, 0xE9,
23270+ 0x81, 0x38, 0x57, 0xE9,
23271+
23272+ 0x82, 0x31, 0x57, 0xE9,
23273+ 0x86, 0x78, 0x57, 0xE9,
23274+
23275+ 0x83, 0x39, 0x57, 0xE9,
23276+ 0x87, 0x79, 0x57, 0xE9,
23277+
23278+ 0x30, 0x1F, 0x5F, 0xE9,
23279+ 0x8A, 0x34, 0x20, 0xE9,
23280+
23281+ 0x8B, 0x3C, 0x20, 0xE9,
23282+ 0x37, 0x50, 0x60, 0xBD,
23283+
23284+ 0x57, 0x0D, 0x20, 0xE9,
23285+ 0x35, 0x51, 0x61, 0xBD,
23286+
23287+ 0x2B, 0x50, 0x20, 0xE9,
23288+ 0x1D, 0x37, 0xE1, 0xEA,
23289+
23290+ 0x1E, 0x35, 0xE1, 0xEA,
23291+ 0x00, 0xE0,
23292+ 0x0E, 0x77,
23293+
23294+ 0x24, 0x51, 0x20, 0xE9,
23295+ 0x8D, 0xFF, 0x20, 0xEA,
23296+
23297+ 0x16, 0x0E, 0x20, 0xE9,
23298+ 0x57, 0x2E, 0xBF, 0xEA,
23299+
23300+ 0x0B, 0x46, 0xA0, 0xE8,
23301+ 0x1B, 0x56, 0xA0, 0xE8,
23302+
23303+ 0x2B, 0x66, 0xA0, 0xE8,
23304+ 0x0C, 0x47, 0xA0, 0xE8,
23305+
23306+ 0x1C, 0x57, 0xA0, 0xE8,
23307+ 0x2C, 0x67, 0xA0, 0xE8,
23308+
23309+ 0x0B, 0x00,
23310+ 0x1B, 0x00,
23311+ 0x2B, 0x00,
23312+ 0x00, 0xE0,
23313+
23314+ 0x0C, 0x00,
23315+ 0x1C, 0x00,
23316+ 0x2C, 0x00,
23317+ 0x00, 0xE0,
23318+
23319+ 0x0B, 0x65,
23320+ 0x1B, 0x65,
23321+ 0x2B, 0x65,
23322+ 0x00, 0xE0,
23323+
23324+ 0x0C, 0x65,
23325+ 0x1C, 0x65,
23326+ 0x2C, 0x65,
23327+ 0x00, 0xE0,
23328+
23329+ 0x0B, 0x1B, 0x60, 0xEC,
23330+ 0x36, 0xD7, 0x36, 0xAD,
23331+
23332+ 0x2B, 0x80, 0x60, 0xEC,
23333+ 0x0C, 0x1C, 0x60, 0xEC,
23334+
23335+ 0x3E, 0xD7, 0x3E, 0xAD,
23336+ 0x2C, 0x80, 0x60, 0xEC,
23337+
23338+ 0x0B, 0x2B, 0xDE, 0xE8,
23339+ 0x1B, 0x80, 0xDE, 0xE8,
23340+
23341+ 0x36, 0x80, 0x36, 0xBD,
23342+ 0x3E, 0x80, 0x3E, 0xBD,
23343+
23344+ 0x33, 0xD7, 0x0B, 0xBD,
23345+ 0x3B, 0xD7, 0x1B, 0xBD,
23346+
23347+ 0x46, 0x80, 0x46, 0xCF,
23348+ 0x57, 0x80, 0x57, 0xCF,
23349+
23350+ 0x66, 0x33, 0x66, 0xCF,
23351+ 0x47, 0x3B, 0x47, 0xCF,
23352+
23353+ 0x56, 0x33, 0x56, 0xCF,
23354+ 0x67, 0x3B, 0x67, 0xCF,
23355+
23356+ 0x0B, 0x48, 0xA0, 0xE8,
23357+ 0x1B, 0x58, 0xA0, 0xE8,
23358+
23359+ 0x2B, 0x68, 0xA0, 0xE8,
23360+ 0x0C, 0x49, 0xA0, 0xE8,
23361+
23362+ 0x1C, 0x59, 0xA0, 0xE8,
23363+ 0x2C, 0x69, 0xA0, 0xE8,
23364+
23365+ 0x0B, 0x00,
23366+ 0x1B, 0x00,
23367+ 0x2B, 0x00,
23368+ 0x00, 0xE0,
23369+
23370+ 0x0C, 0x00,
23371+ 0x1C, 0x00,
23372+ 0x2C, 0x00,
23373+ 0x00, 0xE0,
23374+
23375+ 0x0B, 0x65,
23376+ 0x1B, 0x65,
23377+ 0x2B, 0x65,
23378+ 0x00, 0xE0,
23379+
23380+ 0x0C, 0x65,
23381+ 0x1C, 0x65,
23382+ 0x2C, 0x65,
23383+ 0x00, 0xE0,
23384+
23385+ 0x0B, 0x1B, 0x60, 0xEC,
23386+ 0x34, 0xD7, 0x34, 0xAD,
23387+
23388+ 0x2B, 0x80, 0x60, 0xEC,
23389+ 0x0C, 0x1C, 0x60, 0xEC,
23390+
23391+ 0x3C, 0xD7, 0x3C, 0xAD,
23392+ 0x2C, 0x80, 0x60, 0xEC,
23393+
23394+ 0x0B, 0x2B, 0xDE, 0xE8,
23395+ 0x1B, 0x80, 0xDE, 0xE8,
23396+
23397+ 0x34, 0x80, 0x34, 0xBD,
23398+ 0x3C, 0x80, 0x3C, 0xBD,
23399+
23400+ 0x33, 0xD7, 0x0B, 0xBD,
23401+ 0x3B, 0xD7, 0x1B, 0xBD,
23402+
23403+ 0x48, 0x80, 0x48, 0xCF,
23404+ 0x59, 0x80, 0x59, 0xCF,
23405+
23406+ 0x68, 0x33, 0x68, 0xCF,
23407+ 0x49, 0x3B, 0x49, 0xCF,
23408+
23409+ 0xAD, 0xFF, 0x20, 0xEA,
23410+ 0x00, 0x80, 0x00, 0xE8,
23411+
23412+ 0x58, 0x33, 0x58, 0xCF,
23413+ 0x69, 0x3B, 0x69, 0xCF,
23414+
23415+ 0x6B, 0xFF, 0x20, 0xEA,
23416+ 0x57, 0xC0, 0xBF, 0xEA,
23417+
23418+ 0x00, 0x80, 0xA0, 0xE9,
23419+ 0x00, 0x00, 0xD8, 0xEC,
23420+
23421+};
23422+
23423+static unsigned char warp_g400_t2gzsaf[] = {
23424+
23425+ 0x00, 0x8A, 0x98, 0xE9,
23426+ 0x00, 0x80, 0x00, 0xE8,
23427+
23428+ 0x00, 0x80, 0xA0, 0xE9,
23429+ 0x00, 0x00, 0xD8, 0xEC,
23430+
23431+ 0xFF, 0x80, 0xC0, 0xE9,
23432+ 0x00, 0x80, 0x00, 0xE8,
23433+
23434+ 0x0A, 0x40, 0x50, 0xBF,
23435+ 0x2A, 0x40, 0x60, 0xBF,
23436+
23437+ 0x32, 0x41, 0x51, 0xBF,
23438+ 0x3A, 0x41, 0x61, 0xBF,
23439+
23440+ 0xC3, 0x6B,
23441+ 0xD3, 0x6B,
23442+ 0x00, 0x8A, 0x98, 0xE9,
23443+
23444+ 0x73, 0x7B, 0xC8, 0xEC,
23445+ 0x96, 0xE2,
23446+ 0x41, 0x04,
23447+
23448+ 0x7B, 0x43, 0xA0, 0xE8,
23449+ 0x73, 0x53, 0xA0, 0xE8,
23450+
23451+ 0xAD, 0xEE, 0x23, 0x9F,
23452+ 0x00, 0xE0,
23453+ 0x51, 0x04,
23454+
23455+ 0x90, 0xE2,
23456+ 0x61, 0x04,
23457+ 0x31, 0x46, 0xB1, 0xE8,
23458+
23459+ 0x51, 0x41, 0xE0, 0xEC,
23460+ 0x39, 0x67, 0xB1, 0xE8,
23461+
23462+ 0x00, 0x04,
23463+ 0x46, 0xE2,
23464+ 0x73, 0x63, 0xA0, 0xE8,
23465+
23466+ 0x61, 0x41, 0xE0, 0xEC,
23467+ 0x31, 0x00,
23468+ 0x39, 0x00,
23469+
23470+ 0x8E, 0x80, 0x15, 0xEA,
23471+ 0x10, 0x04,
23472+ 0x20, 0x04,
23473+
23474+ 0x61, 0x51, 0xE0, 0xEC,
23475+ 0x2F, 0x41, 0x60, 0xEA,
23476+
23477+ 0x31, 0x20,
23478+ 0x39, 0x20,
23479+ 0x1F, 0x42, 0xA0, 0xE8,
23480+
23481+ 0x2A, 0x42, 0x52, 0xBF,
23482+ 0x0F, 0x52, 0xA0, 0xE8,
23483+
23484+ 0x1A, 0x42, 0x62, 0xBF,
23485+ 0x1E, 0x51, 0x60, 0xEA,
23486+
23487+ 0x73, 0x7B, 0xC8, 0xEC,
23488+ 0x0E, 0x61, 0x60, 0xEA,
23489+
23490+ 0x32, 0x40, 0x50, 0xBD,
23491+ 0x22, 0x40, 0x60, 0xBD,
23492+
23493+ 0x12, 0x41, 0x51, 0xBD,
23494+ 0x3A, 0x41, 0x61, 0xBD,
23495+
23496+ 0xBF, 0x2F, 0x0E, 0xBD,
23497+ 0x97, 0xE2,
23498+ 0x7B, 0x72,
23499+
23500+ 0x32, 0x20,
23501+ 0x22, 0x20,
23502+ 0x12, 0x20,
23503+ 0x3A, 0x20,
23504+
23505+ 0x35, 0x48, 0xB1, 0xE8,
23506+ 0x3D, 0x59, 0xB1, 0xE8,
23507+
23508+ 0x46, 0x31, 0x46, 0xBF,
23509+ 0x56, 0x31, 0x56, 0xBF,
23510+
23511+ 0xB3, 0xE2, 0x2D, 0x9F,
23512+ 0x00, 0x80, 0x00, 0xE8,
23513+
23514+ 0x66, 0x31, 0x66, 0xBF,
23515+ 0x47, 0x39, 0x47, 0xBF,
23516+
23517+ 0x57, 0x39, 0x57, 0xBF,
23518+ 0x67, 0x39, 0x67, 0xBF,
23519+
23520+ 0x7F, 0x80, 0x07, 0xEA,
23521+ 0x24, 0x41, 0x20, 0xE9,
23522+
23523+ 0x35, 0x00,
23524+ 0x3D, 0x00,
23525+ 0x00, 0xE0,
23526+ 0x2D, 0x73,
23527+
23528+ 0x33, 0x72,
23529+ 0x0C, 0xE3,
23530+ 0x8D, 0x2F, 0x1E, 0xBD,
23531+
23532+ 0x43, 0x75, 0xF8, 0xEC,
23533+ 0x35, 0x20,
23534+ 0x3D, 0x20,
23535+
23536+ 0x43, 0x43, 0x2D, 0xDF,
23537+ 0x53, 0x53, 0x2D, 0xDF,
23538+
23539+ 0xAE, 0x1E, 0x0E, 0xBD,
23540+ 0x58, 0xE3,
23541+ 0x33, 0x66,
23542+
23543+ 0x48, 0x35, 0x48, 0xBF,
23544+ 0x58, 0x35, 0x58, 0xBF,
23545+
23546+ 0x68, 0x35, 0x68, 0xBF,
23547+ 0x49, 0x3D, 0x49, 0xBF,
23548+
23549+ 0x59, 0x3D, 0x59, 0xBF,
23550+ 0x69, 0x3D, 0x69, 0xBF,
23551+
23552+ 0x63, 0x63, 0x2D, 0xDF,
23553+ 0x4D, 0x7D, 0xF8, 0xEC,
23554+
23555+ 0x59, 0xE3,
23556+ 0x00, 0xE0,
23557+ 0xB8, 0x38, 0x33, 0xBF,
23558+
23559+ 0x2D, 0x73,
23560+ 0x30, 0x76,
23561+ 0x18, 0x3A, 0x41, 0xE9,
23562+
23563+ 0x3F, 0x53, 0xA0, 0xE8,
23564+ 0x05, 0x80, 0x3D, 0xEA,
23565+
23566+ 0x37, 0x43, 0xA0, 0xE8,
23567+ 0x3D, 0x63, 0xA0, 0xE8,
23568+
23569+ 0x50, 0x70, 0xF8, 0xEC,
23570+ 0x2B, 0x50, 0x3C, 0xE9,
23571+
23572+ 0x1F, 0x0F, 0xBC, 0xE8,
23573+ 0x00, 0x80, 0x00, 0xE8,
23574+
23575+ 0x59, 0x78, 0xF8, 0xEC,
23576+ 0x00, 0x80, 0x00, 0xE8,
23577+
23578+ 0x15, 0xC0, 0x20, 0xE9,
23579+ 0x15, 0xC0, 0x20, 0xE9,
23580+
23581+ 0x15, 0xC0, 0x20, 0xE9,
23582+ 0x15, 0xC0, 0x20, 0xE9,
23583+
23584+ 0x1E, 0x12, 0x41, 0xE9,
23585+ 0x1A, 0x22, 0x41, 0xE9,
23586+
23587+ 0x46, 0x37, 0x46, 0xDF,
23588+ 0x56, 0x3F, 0x56, 0xDF,
23589+
23590+ 0x2B, 0x40, 0x3D, 0xE9,
23591+ 0x66, 0x3D, 0x66, 0xDF,
23592+
23593+ 0x1D, 0x32, 0x41, 0xE9,
23594+ 0x67, 0x3D, 0x67, 0xDF,
23595+
23596+ 0x47, 0x37, 0x47, 0xDF,
23597+ 0x57, 0x3F, 0x57, 0xDF,
23598+
23599+ 0x2A, 0x40, 0x20, 0xE9,
23600+ 0x59, 0x3F, 0x59, 0xDF,
23601+
23602+ 0x16, 0x30, 0x20, 0xE9,
23603+ 0x69, 0x3D, 0x69, 0xDF,
23604+
23605+ 0x48, 0x37, 0x48, 0xDF,
23606+ 0x58, 0x3F, 0x58, 0xDF,
23607+
23608+ 0x68, 0x3D, 0x68, 0xDF,
23609+ 0x49, 0x37, 0x49, 0xDF,
23610+
23611+ 0x32, 0x32, 0x2D, 0xDF,
23612+ 0x22, 0x22, 0x2D, 0xDF,
23613+
23614+ 0x12, 0x12, 0x2D, 0xDF,
23615+ 0x3A, 0x3A, 0x2D, 0xDF,
23616+
23617+ 0x0F, 0xCF, 0x74, 0xC2,
23618+ 0x37, 0xCF, 0x74, 0xC4,
23619+
23620+ 0x0A, 0x44, 0x54, 0xB0,
23621+ 0x02, 0x44, 0x64, 0xB0,
23622+
23623+ 0x3D, 0xCF, 0x74, 0xC0,
23624+ 0x34, 0x37, 0x20, 0xE9,
23625+
23626+ 0x31, 0x53, 0x2F, 0x9F,
23627+ 0x38, 0x0F, 0x20, 0xE9,
23628+
23629+ 0x39, 0xE5, 0x2C, 0x9F,
23630+ 0x3C, 0x3D, 0x20, 0xE9,
23631+
23632+ 0x2A, 0x44, 0x54, 0xB2,
23633+ 0x1A, 0x44, 0x64, 0xB2,
23634+
23635+ 0x3A, 0x80, 0x3A, 0xEA,
23636+ 0x0A, 0x20,
23637+ 0x02, 0x20,
23638+
23639+ 0x0F, 0xCF, 0x75, 0xC0,
23640+ 0x2A, 0x20,
23641+ 0x1A, 0x20,
23642+
23643+ 0x30, 0x50, 0x2E, 0x9F,
23644+ 0x32, 0x31, 0x5F, 0xE9,
23645+
23646+ 0x38, 0x21, 0x2C, 0x9F,
23647+ 0x33, 0x39, 0x5F, 0xE9,
23648+
23649+ 0x3D, 0xCF, 0x75, 0xC2,
23650+ 0x37, 0xCF, 0x75, 0xC4,
23651+
23652+ 0x31, 0x53, 0x2F, 0x9F,
23653+ 0xA6, 0x0F, 0x20, 0xE9,
23654+
23655+ 0x39, 0xE5, 0x2C, 0x9F,
23656+ 0xA3, 0x3D, 0x20, 0xE9,
23657+
23658+ 0x2A, 0x44, 0x54, 0xB4,
23659+ 0x1A, 0x44, 0x64, 0xB4,
23660+
23661+ 0x0A, 0x45, 0x55, 0xB0,
23662+ 0x02, 0x45, 0x65, 0xB0,
23663+
23664+ 0x88, 0x73, 0x5E, 0xE9,
23665+ 0x2A, 0x20,
23666+ 0x1A, 0x20,
23667+
23668+ 0xA0, 0x37, 0x20, 0xE9,
23669+ 0x0A, 0x20,
23670+ 0x02, 0x20,
23671+
23672+ 0x31, 0x53, 0x2F, 0x9F,
23673+ 0x3E, 0x30, 0x4F, 0xE9,
23674+
23675+ 0x39, 0xE5, 0x2C, 0x9F,
23676+ 0x3F, 0x38, 0x4F, 0xE9,
23677+
23678+ 0x30, 0x50, 0x2E, 0x9F,
23679+ 0x3A, 0x31, 0x4F, 0xE9,
23680+
23681+ 0x38, 0x21, 0x2C, 0x9F,
23682+ 0x3B, 0x39, 0x4F, 0xE9,
23683+
23684+ 0x2A, 0x45, 0x55, 0xB2,
23685+ 0x1A, 0x45, 0x65, 0xB2,
23686+
23687+ 0x0A, 0x45, 0x55, 0xB4,
23688+ 0x02, 0x45, 0x65, 0xB4,
23689+
23690+ 0x0F, 0xCF, 0x74, 0xC6,
23691+ 0x2A, 0x20,
23692+ 0x1A, 0x20,
23693+
23694+ 0xA7, 0x30, 0x4F, 0xE9,
23695+ 0x0A, 0x20,
23696+ 0x02, 0x20,
23697+
23698+ 0x31, 0x53, 0x2F, 0x9F,
23699+ 0x9C, 0x0F, 0x20, 0xE9,
23700+
23701+ 0x39, 0xE5, 0x2C, 0x9F,
23702+ 0xA8, 0x38, 0x4F, 0xE9,
23703+
23704+ 0x2A, 0x44, 0x54, 0xB6,
23705+ 0x1A, 0x44, 0x64, 0xB6,
23706+
23707+ 0x30, 0x50, 0x2E, 0x9F,
23708+ 0x36, 0x31, 0x4F, 0xE9,
23709+
23710+ 0x38, 0x21, 0x2C, 0x9F,
23711+ 0x37, 0x39, 0x4F, 0xE9,
23712+
23713+ 0x0A, 0x45, 0x55, 0xB6,
23714+ 0x02, 0x45, 0x65, 0xB6,
23715+
23716+ 0x3D, 0xCF, 0x75, 0xC6,
23717+ 0x2A, 0x20,
23718+ 0x1A, 0x20,
23719+
23720+ 0x2A, 0x46, 0x56, 0xBF,
23721+ 0x1A, 0x46, 0x66, 0xBF,
23722+
23723+ 0x31, 0x53, 0x2F, 0x9F,
23724+ 0xA4, 0x31, 0x4F, 0xE9,
23725+
23726+ 0x39, 0xE5, 0x2C, 0x9F,
23727+ 0xA5, 0x39, 0x4F, 0xE9,
23728+
23729+ 0x31, 0x3D, 0x20, 0xE9,
23730+ 0x0A, 0x20,
23731+ 0x02, 0x20,
23732+
23733+ 0x0A, 0x47, 0x57, 0xBF,
23734+ 0x02, 0x47, 0x67, 0xBF,
23735+
23736+ 0x30, 0x50, 0x2E, 0x9F,
23737+ 0xA1, 0x30, 0x4F, 0xE9,
23738+
23739+ 0x38, 0x21, 0x2C, 0x9F,
23740+ 0xA2, 0x38, 0x4F, 0xE9,
23741+
23742+ 0x31, 0x53, 0x2F, 0x9F,
23743+ 0x9D, 0x31, 0x4F, 0xE9,
23744+
23745+ 0x39, 0xE5, 0x2C, 0x9F,
23746+ 0x9E, 0x39, 0x4F, 0xE9,
23747+
23748+ 0x2A, 0x43, 0x53, 0xBF,
23749+ 0x1A, 0x43, 0x63, 0xBF,
23750+
23751+ 0x30, 0x50, 0x2E, 0x9F,
23752+ 0x35, 0x30, 0x4F, 0xE9,
23753+
23754+ 0x38, 0x21, 0x2C, 0x9F,
23755+ 0x39, 0x38, 0x4F, 0xE9,
23756+
23757+ 0x0A, 0x48, 0x58, 0xBF,
23758+ 0x02, 0x48, 0x68, 0xBF,
23759+
23760+ 0x31, 0x53, 0x2F, 0x9F,
23761+ 0x80, 0x31, 0x57, 0xE9,
23762+
23763+ 0x39, 0xE5, 0x2C, 0x9F,
23764+ 0x81, 0x39, 0x57, 0xE9,
23765+
23766+ 0x2A, 0x49, 0x59, 0xBF,
23767+ 0x1A, 0x49, 0x69, 0xBF,
23768+
23769+ 0x30, 0x50, 0x2E, 0x9F,
23770+ 0x82, 0x30, 0x57, 0xE9,
23771+
23772+ 0x38, 0x21, 0x2C, 0x9F,
23773+ 0x83, 0x38, 0x57, 0xE9,
23774+
23775+ 0x31, 0x53, 0x2F, 0x9F,
23776+ 0x84, 0x31, 0x5E, 0xE9,
23777+
23778+ 0x39, 0xE5, 0x2C, 0x9F,
23779+ 0x85, 0x39, 0x5E, 0xE9,
23780+
23781+ 0x86, 0x76, 0x57, 0xE9,
23782+ 0x8A, 0x36, 0x20, 0xE9,
23783+
23784+ 0x87, 0x77, 0x57, 0xE9,
23785+ 0x8B, 0x3E, 0xBF, 0xEA,
23786+
23787+ 0x80, 0x30, 0x57, 0xE9,
23788+ 0x81, 0x38, 0x57, 0xE9,
23789+
23790+ 0x82, 0x31, 0x57, 0xE9,
23791+ 0x86, 0x78, 0x57, 0xE9,
23792+
23793+ 0x83, 0x39, 0x57, 0xE9,
23794+ 0x87, 0x79, 0x57, 0xE9,
23795+
23796+ 0x30, 0x1F, 0x5F, 0xE9,
23797+ 0x8A, 0x34, 0x20, 0xE9,
23798+
23799+ 0x8B, 0x3C, 0x20, 0xE9,
23800+ 0x37, 0x50, 0x60, 0xBD,
23801+
23802+ 0x57, 0x0D, 0x20, 0xE9,
23803+ 0x35, 0x51, 0x61, 0xBD,
23804+
23805+ 0x2B, 0x50, 0x20, 0xE9,
23806+ 0x1D, 0x37, 0xE1, 0xEA,
23807+
23808+ 0x1E, 0x35, 0xE1, 0xEA,
23809+ 0x00, 0xE0,
23810+ 0x0E, 0x77,
23811+
23812+ 0x24, 0x51, 0x20, 0xE9,
23813+ 0x89, 0xFF, 0x20, 0xEA,
23814+
23815+ 0x16, 0x0E, 0x20, 0xE9,
23816+ 0x57, 0x2E, 0xBF, 0xEA,
23817+
23818+ 0x0B, 0x46, 0xA0, 0xE8,
23819+ 0x1B, 0x56, 0xA0, 0xE8,
23820+
23821+ 0x2B, 0x66, 0xA0, 0xE8,
23822+ 0x0C, 0x47, 0xA0, 0xE8,
23823+
23824+ 0x1C, 0x57, 0xA0, 0xE8,
23825+ 0x2C, 0x67, 0xA0, 0xE8,
23826+
23827+ 0x0B, 0x00,
23828+ 0x1B, 0x00,
23829+ 0x2B, 0x00,
23830+ 0x00, 0xE0,
23831+
23832+ 0x0C, 0x00,
23833+ 0x1C, 0x00,
23834+ 0x2C, 0x00,
23835+ 0x00, 0xE0,
23836+
23837+ 0x0B, 0x65,
23838+ 0x1B, 0x65,
23839+ 0x2B, 0x65,
23840+ 0x00, 0xE0,
23841+
23842+ 0x0C, 0x65,
23843+ 0x1C, 0x65,
23844+ 0x2C, 0x65,
23845+ 0x00, 0xE0,
23846+
23847+ 0x0B, 0x1B, 0x60, 0xEC,
23848+ 0x36, 0xD7, 0x36, 0xAD,
23849+
23850+ 0x2B, 0x80, 0x60, 0xEC,
23851+ 0x0C, 0x1C, 0x60, 0xEC,
23852+
23853+ 0x3E, 0xD7, 0x3E, 0xAD,
23854+ 0x2C, 0x80, 0x60, 0xEC,
23855+
23856+ 0x0B, 0x2B, 0xDE, 0xE8,
23857+ 0x1B, 0x80, 0xDE, 0xE8,
23858+
23859+ 0x36, 0x80, 0x36, 0xBD,
23860+ 0x3E, 0x80, 0x3E, 0xBD,
23861+
23862+ 0x33, 0xD7, 0x0B, 0xBD,
23863+ 0x3B, 0xD7, 0x1B, 0xBD,
23864+
23865+ 0x46, 0x80, 0x46, 0xCF,
23866+ 0x57, 0x80, 0x57, 0xCF,
23867+
23868+ 0x66, 0x33, 0x66, 0xCF,
23869+ 0x47, 0x3B, 0x47, 0xCF,
23870+
23871+ 0x56, 0x33, 0x56, 0xCF,
23872+ 0x67, 0x3B, 0x67, 0xCF,
23873+
23874+ 0x0B, 0x48, 0xA0, 0xE8,
23875+ 0x1B, 0x58, 0xA0, 0xE8,
23876+
23877+ 0x2B, 0x68, 0xA0, 0xE8,
23878+ 0x0C, 0x49, 0xA0, 0xE8,
23879+
23880+ 0x1C, 0x59, 0xA0, 0xE8,
23881+ 0x2C, 0x69, 0xA0, 0xE8,
23882+
23883+ 0x0B, 0x00,
23884+ 0x1B, 0x00,
23885+ 0x2B, 0x00,
23886+ 0x00, 0xE0,
23887+
23888+ 0x0C, 0x00,
23889+ 0x1C, 0x00,
23890+ 0x2C, 0x00,
23891+ 0x00, 0xE0,
23892+
23893+ 0x0B, 0x65,
23894+ 0x1B, 0x65,
23895+ 0x2B, 0x65,
23896+ 0x00, 0xE0,
23897+
23898+ 0x0C, 0x65,
23899+ 0x1C, 0x65,
23900+ 0x2C, 0x65,
23901+ 0x00, 0xE0,
23902+
23903+ 0x0B, 0x1B, 0x60, 0xEC,
23904+ 0x34, 0xD7, 0x34, 0xAD,
23905+
23906+ 0x2B, 0x80, 0x60, 0xEC,
23907+ 0x0C, 0x1C, 0x60, 0xEC,
23908+
23909+ 0x3C, 0xD7, 0x3C, 0xAD,
23910+ 0x2C, 0x80, 0x60, 0xEC,
23911+
23912+ 0x0B, 0x2B, 0xDE, 0xE8,
23913+ 0x1B, 0x80, 0xDE, 0xE8,
23914+
23915+ 0x34, 0x80, 0x34, 0xBD,
23916+ 0x3C, 0x80, 0x3C, 0xBD,
23917+
23918+ 0x33, 0xD7, 0x0B, 0xBD,
23919+ 0x3B, 0xD7, 0x1B, 0xBD,
23920+
23921+ 0x48, 0x80, 0x48, 0xCF,
23922+ 0x59, 0x80, 0x59, 0xCF,
23923+
23924+ 0x68, 0x33, 0x68, 0xCF,
23925+ 0x49, 0x3B, 0x49, 0xCF,
23926+
23927+ 0xA9, 0xFF, 0x20, 0xEA,
23928+ 0x00, 0x80, 0x00, 0xE8,
23929+
23930+ 0x58, 0x33, 0x58, 0xCF,
23931+ 0x69, 0x3B, 0x69, 0xCF,
23932+
23933+ 0x67, 0xFF, 0x20, 0xEA,
23934+ 0x57, 0xC0, 0xBF, 0xEA,
23935+
23936+ 0x00, 0x80, 0xA0, 0xE9,
23937+ 0x00, 0x00, 0xD8, 0xEC,
23938+
23939+};
23940+
23941+static unsigned char warp_g400_t2gzsf[] = {
23942+
23943+ 0x00, 0x8A, 0x98, 0xE9,
23944+ 0x00, 0x80, 0x00, 0xE8,
23945+
23946+ 0x00, 0x80, 0xA0, 0xE9,
23947+ 0x00, 0x00, 0xD8, 0xEC,
23948+
23949+ 0xFF, 0x80, 0xC0, 0xE9,
23950+ 0x00, 0x80, 0x00, 0xE8,
23951+
23952+ 0x0A, 0x40, 0x50, 0xBF,
23953+ 0x2A, 0x40, 0x60, 0xBF,
23954+
23955+ 0x32, 0x41, 0x51, 0xBF,
23956+ 0x3A, 0x41, 0x61, 0xBF,
23957+
23958+ 0xC3, 0x6B,
23959+ 0xD3, 0x6B,
23960+ 0x00, 0x8A, 0x98, 0xE9,
23961+
23962+ 0x73, 0x7B, 0xC8, 0xEC,
23963+ 0x96, 0xE2,
23964+ 0x41, 0x04,
23965+
23966+ 0x7B, 0x43, 0xA0, 0xE8,
23967+ 0x73, 0x53, 0xA0, 0xE8,
23968+
23969+ 0xAD, 0xEE, 0x23, 0x9F,
23970+ 0x00, 0xE0,
23971+ 0x51, 0x04,
23972+
23973+ 0x90, 0xE2,
23974+ 0x61, 0x04,
23975+ 0x31, 0x46, 0xB1, 0xE8,
23976+
23977+ 0x51, 0x41, 0xE0, 0xEC,
23978+ 0x39, 0x67, 0xB1, 0xE8,
23979+
23980+ 0x00, 0x04,
23981+ 0x46, 0xE2,
23982+ 0x73, 0x63, 0xA0, 0xE8,
23983+
23984+ 0x61, 0x41, 0xE0, 0xEC,
23985+ 0x31, 0x00,
23986+ 0x39, 0x00,
23987+
23988+ 0x8A, 0x80, 0x15, 0xEA,
23989+ 0x10, 0x04,
23990+ 0x20, 0x04,
23991+
23992+ 0x61, 0x51, 0xE0, 0xEC,
23993+ 0x2F, 0x41, 0x60, 0xEA,
23994+
23995+ 0x31, 0x20,
23996+ 0x39, 0x20,
23997+ 0x1F, 0x42, 0xA0, 0xE8,
23998+
23999+ 0x2A, 0x42, 0x52, 0xBF,
24000+ 0x0F, 0x52, 0xA0, 0xE8,
24001+
24002+ 0x1A, 0x42, 0x62, 0xBF,
24003+ 0x1E, 0x51, 0x60, 0xEA,
24004+
24005+ 0x73, 0x7B, 0xC8, 0xEC,
24006+ 0x0E, 0x61, 0x60, 0xEA,
24007+
24008+ 0x32, 0x40, 0x50, 0xBD,
24009+ 0x22, 0x40, 0x60, 0xBD,
24010+
24011+ 0x12, 0x41, 0x51, 0xBD,
24012+ 0x3A, 0x41, 0x61, 0xBD,
24013+
24014+ 0xBF, 0x2F, 0x0E, 0xBD,
24015+ 0x97, 0xE2,
24016+ 0x7B, 0x72,
24017+
24018+ 0x32, 0x20,
24019+ 0x22, 0x20,
24020+ 0x12, 0x20,
24021+ 0x3A, 0x20,
24022+
24023+ 0x35, 0x48, 0xB1, 0xE8,
24024+ 0x3D, 0x59, 0xB1, 0xE8,
24025+
24026+ 0x46, 0x31, 0x46, 0xBF,
24027+ 0x56, 0x31, 0x56, 0xBF,
24028+
24029+ 0xB3, 0xE2, 0x2D, 0x9F,
24030+ 0x00, 0x80, 0x00, 0xE8,
24031+
24032+ 0x66, 0x31, 0x66, 0xBF,
24033+ 0x47, 0x39, 0x47, 0xBF,
24034+
24035+ 0x57, 0x39, 0x57, 0xBF,
24036+ 0x67, 0x39, 0x67, 0xBF,
24037+
24038+ 0x7B, 0x80, 0x07, 0xEA,
24039+ 0x24, 0x41, 0x20, 0xE9,
24040+
24041+ 0x35, 0x00,
24042+ 0x3D, 0x00,
24043+ 0x00, 0xE0,
24044+ 0x2D, 0x73,
24045+
24046+ 0x33, 0x72,
24047+ 0x0C, 0xE3,
24048+ 0x8D, 0x2F, 0x1E, 0xBD,
24049+
24050+ 0x43, 0x75, 0xF8, 0xEC,
24051+ 0x35, 0x20,
24052+ 0x3D, 0x20,
24053+
24054+ 0x43, 0x43, 0x2D, 0xDF,
24055+ 0x53, 0x53, 0x2D, 0xDF,
24056+
24057+ 0xAE, 0x1E, 0x0E, 0xBD,
24058+ 0x58, 0xE3,
24059+ 0x33, 0x66,
24060+
24061+ 0x48, 0x35, 0x48, 0xBF,
24062+ 0x58, 0x35, 0x58, 0xBF,
24063+
24064+ 0x68, 0x35, 0x68, 0xBF,
24065+ 0x49, 0x3D, 0x49, 0xBF,
24066+
24067+ 0x59, 0x3D, 0x59, 0xBF,
24068+ 0x69, 0x3D, 0x69, 0xBF,
24069+
24070+ 0x63, 0x63, 0x2D, 0xDF,
24071+ 0x4D, 0x7D, 0xF8, 0xEC,
24072+
24073+ 0x59, 0xE3,
24074+ 0x00, 0xE0,
24075+ 0xB8, 0x38, 0x33, 0xBF,
24076+
24077+ 0x2D, 0x73,
24078+ 0x30, 0x76,
24079+ 0x18, 0x3A, 0x41, 0xE9,
24080+
24081+ 0x3F, 0x53, 0xA0, 0xE8,
24082+ 0x05, 0x80, 0x3D, 0xEA,
24083+
24084+ 0x37, 0x43, 0xA0, 0xE8,
24085+ 0x3D, 0x63, 0xA0, 0xE8,
24086+
24087+ 0x50, 0x70, 0xF8, 0xEC,
24088+ 0x2B, 0x50, 0x3C, 0xE9,
24089+
24090+ 0x1F, 0x0F, 0xBC, 0xE8,
24091+ 0x00, 0x80, 0x00, 0xE8,
24092+
24093+ 0x59, 0x78, 0xF8, 0xEC,
24094+ 0x00, 0x80, 0x00, 0xE8,
24095+
24096+ 0x15, 0xC0, 0x20, 0xE9,
24097+ 0x15, 0xC0, 0x20, 0xE9,
24098+
24099+ 0x15, 0xC0, 0x20, 0xE9,
24100+ 0x15, 0xC0, 0x20, 0xE9,
24101+
24102+ 0x1E, 0x12, 0x41, 0xE9,
24103+ 0x1A, 0x22, 0x41, 0xE9,
24104+
24105+ 0x46, 0x37, 0x46, 0xDF,
24106+ 0x56, 0x3F, 0x56, 0xDF,
24107+
24108+ 0x2B, 0x40, 0x3D, 0xE9,
24109+ 0x66, 0x3D, 0x66, 0xDF,
24110+
24111+ 0x1D, 0x32, 0x41, 0xE9,
24112+ 0x67, 0x3D, 0x67, 0xDF,
24113+
24114+ 0x47, 0x37, 0x47, 0xDF,
24115+ 0x57, 0x3F, 0x57, 0xDF,
24116+
24117+ 0x2A, 0x40, 0x20, 0xE9,
24118+ 0x59, 0x3F, 0x59, 0xDF,
24119+
24120+ 0x16, 0x30, 0x20, 0xE9,
24121+ 0x69, 0x3D, 0x69, 0xDF,
24122+
24123+ 0x48, 0x37, 0x48, 0xDF,
24124+ 0x58, 0x3F, 0x58, 0xDF,
24125+
24126+ 0x68, 0x3D, 0x68, 0xDF,
24127+ 0x49, 0x37, 0x49, 0xDF,
24128+
24129+ 0x32, 0x32, 0x2D, 0xDF,
24130+ 0x22, 0x22, 0x2D, 0xDF,
24131+
24132+ 0x12, 0x12, 0x2D, 0xDF,
24133+ 0x3A, 0x3A, 0x2D, 0xDF,
24134+
24135+ 0x0F, 0xCF, 0x74, 0xC2,
24136+ 0x37, 0xCF, 0x74, 0xC4,
24137+
24138+ 0x0A, 0x44, 0x54, 0xB0,
24139+ 0x02, 0x44, 0x64, 0xB0,
24140+
24141+ 0x3D, 0xCF, 0x74, 0xC0,
24142+ 0x34, 0x37, 0x20, 0xE9,
24143+
24144+ 0x31, 0x53, 0x2F, 0x9F,
24145+ 0x38, 0x0F, 0x20, 0xE9,
24146+
24147+ 0x39, 0xE5, 0x2C, 0x9F,
24148+ 0x3C, 0x3D, 0x20, 0xE9,
24149+
24150+ 0x2A, 0x44, 0x54, 0xB2,
24151+ 0x1A, 0x44, 0x64, 0xB2,
24152+
24153+ 0x36, 0x80, 0x3A, 0xEA,
24154+ 0x0A, 0x20,
24155+ 0x02, 0x20,
24156+
24157+ 0x0F, 0xCF, 0x75, 0xC0,
24158+ 0x2A, 0x20,
24159+ 0x1A, 0x20,
24160+
24161+ 0x30, 0x50, 0x2E, 0x9F,
24162+ 0x32, 0x31, 0x5F, 0xE9,
24163+
24164+ 0x38, 0x21, 0x2C, 0x9F,
24165+ 0x33, 0x39, 0x5F, 0xE9,
24166+
24167+ 0x3D, 0xCF, 0x75, 0xC2,
24168+ 0x37, 0xCF, 0x75, 0xC4,
24169+
24170+ 0x31, 0x53, 0x2F, 0x9F,
24171+ 0xA6, 0x0F, 0x20, 0xE9,
24172+
24173+ 0x39, 0xE5, 0x2C, 0x9F,
24174+ 0xA3, 0x3D, 0x20, 0xE9,
24175+
24176+ 0x2A, 0x44, 0x54, 0xB4,
24177+ 0x1A, 0x44, 0x64, 0xB4,
24178+
24179+ 0x0A, 0x45, 0x55, 0xB0,
24180+ 0x02, 0x45, 0x65, 0xB0,
24181+
24182+ 0x88, 0x73, 0x5E, 0xE9,
24183+ 0x2A, 0x20,
24184+ 0x1A, 0x20,
24185+
24186+ 0xA0, 0x37, 0x20, 0xE9,
24187+ 0x0A, 0x20,
24188+ 0x02, 0x20,
24189+
24190+ 0x31, 0x53, 0x2F, 0x9F,
24191+ 0x3E, 0x30, 0x4F, 0xE9,
24192+
24193+ 0x39, 0xE5, 0x2C, 0x9F,
24194+ 0x3F, 0x38, 0x4F, 0xE9,
24195+
24196+ 0x30, 0x50, 0x2E, 0x9F,
24197+ 0x3A, 0x31, 0x4F, 0xE9,
24198+
24199+ 0x38, 0x21, 0x2C, 0x9F,
24200+ 0x3B, 0x39, 0x4F, 0xE9,
24201+
24202+ 0x2A, 0x45, 0x55, 0xB2,
24203+ 0x1A, 0x45, 0x65, 0xB2,
24204+
24205+ 0x0A, 0x45, 0x55, 0xB4,
24206+ 0x02, 0x45, 0x65, 0xB4,
24207+
24208+ 0x0F, 0xCF, 0x75, 0xC6,
24209+ 0x2A, 0x20,
24210+ 0x1A, 0x20,
24211+
24212+ 0xA7, 0x30, 0x4F, 0xE9,
24213+ 0x0A, 0x20,
24214+ 0x02, 0x20,
24215+
24216+ 0x31, 0x53, 0x2F, 0x9F,
24217+ 0x31, 0x0F, 0x20, 0xE9,
24218+
24219+ 0x39, 0xE5, 0x2C, 0x9F,
24220+ 0xA8, 0x38, 0x4F, 0xE9,
24221+
24222+ 0x2A, 0x45, 0x55, 0xB6,
24223+ 0x1A, 0x45, 0x65, 0xB6,
24224+
24225+ 0x30, 0x50, 0x2E, 0x9F,
24226+ 0x36, 0x31, 0x4F, 0xE9,
24227+
24228+ 0x38, 0x21, 0x2C, 0x9F,
24229+ 0x37, 0x39, 0x4F, 0xE9,
24230+
24231+ 0x00, 0x80, 0x00, 0xE8,
24232+ 0x2A, 0x20,
24233+ 0x1A, 0x20,
24234+
24235+ 0x2A, 0x46, 0x56, 0xBF,
24236+ 0x1A, 0x46, 0x66, 0xBF,
24237+
24238+ 0x31, 0x53, 0x2F, 0x9F,
24239+ 0xA4, 0x31, 0x4F, 0xE9,
24240+
24241+ 0x39, 0xE5, 0x2C, 0x9F,
24242+ 0xA5, 0x39, 0x4F, 0xE9,
24243+
24244+ 0x0A, 0x47, 0x57, 0xBF,
24245+ 0x02, 0x47, 0x67, 0xBF,
24246+
24247+ 0x31, 0x53, 0x2F, 0x9F,
24248+ 0xA1, 0x30, 0x4F, 0xE9,
24249+
24250+ 0x39, 0xE5, 0x2C, 0x9F,
24251+ 0xA2, 0x38, 0x4F, 0xE9,
24252+
24253+ 0x2A, 0x43, 0x53, 0xBF,
24254+ 0x1A, 0x43, 0x63, 0xBF,
24255+
24256+ 0x30, 0x50, 0x2E, 0x9F,
24257+ 0x35, 0x31, 0x4F, 0xE9,
24258+
24259+ 0x38, 0x21, 0x2C, 0x9F,
24260+ 0x39, 0x39, 0x4F, 0xE9,
24261+
24262+ 0x0A, 0x48, 0x58, 0xBF,
24263+ 0x02, 0x48, 0x68, 0xBF,
24264+
24265+ 0x31, 0x53, 0x2F, 0x9F,
24266+ 0x80, 0x31, 0x57, 0xE9,
24267+
24268+ 0x39, 0xE5, 0x2C, 0x9F,
24269+ 0x81, 0x39, 0x57, 0xE9,
24270+
24271+ 0x2A, 0x49, 0x59, 0xBF,
24272+ 0x1A, 0x49, 0x69, 0xBF,
24273+
24274+ 0x30, 0x50, 0x2E, 0x9F,
24275+ 0x82, 0x30, 0x57, 0xE9,
24276+
24277+ 0x38, 0x21, 0x2C, 0x9F,
24278+ 0x83, 0x38, 0x57, 0xE9,
24279+
24280+ 0x31, 0x53, 0x2F, 0x9F,
24281+ 0x84, 0x31, 0x5E, 0xE9,
24282+
24283+ 0x39, 0xE5, 0x2C, 0x9F,
24284+ 0x85, 0x39, 0x5E, 0xE9,
24285+
24286+ 0x86, 0x76, 0x57, 0xE9,
24287+ 0x8A, 0x36, 0x20, 0xE9,
24288+
24289+ 0x87, 0x77, 0x57, 0xE9,
24290+ 0x8B, 0x3E, 0xBF, 0xEA,
24291+
24292+ 0x80, 0x30, 0x57, 0xE9,
24293+ 0x81, 0x38, 0x57, 0xE9,
24294+
24295+ 0x82, 0x31, 0x57, 0xE9,
24296+ 0x86, 0x78, 0x57, 0xE9,
24297+
24298+ 0x83, 0x39, 0x57, 0xE9,
24299+ 0x87, 0x79, 0x57, 0xE9,
24300+
24301+ 0x30, 0x1F, 0x5F, 0xE9,
24302+ 0x8A, 0x34, 0x20, 0xE9,
24303+
24304+ 0x8B, 0x3C, 0x20, 0xE9,
24305+ 0x37, 0x50, 0x60, 0xBD,
24306+
24307+ 0x57, 0x0D, 0x20, 0xE9,
24308+ 0x35, 0x51, 0x61, 0xBD,
24309+
24310+ 0x2B, 0x50, 0x20, 0xE9,
24311+ 0x1D, 0x37, 0xE1, 0xEA,
24312+
24313+ 0x1E, 0x35, 0xE1, 0xEA,
24314+ 0x00, 0xE0,
24315+ 0x0E, 0x77,
24316+
24317+ 0x24, 0x51, 0x20, 0xE9,
24318+ 0x8D, 0xFF, 0x20, 0xEA,
24319+
24320+ 0x16, 0x0E, 0x20, 0xE9,
24321+ 0x57, 0x2E, 0xBF, 0xEA,
24322+
24323+ 0x0B, 0x46, 0xA0, 0xE8,
24324+ 0x1B, 0x56, 0xA0, 0xE8,
24325+
24326+ 0x2B, 0x66, 0xA0, 0xE8,
24327+ 0x0C, 0x47, 0xA0, 0xE8,
24328+
24329+ 0x1C, 0x57, 0xA0, 0xE8,
24330+ 0x2C, 0x67, 0xA0, 0xE8,
24331+
24332+ 0x0B, 0x00,
24333+ 0x1B, 0x00,
24334+ 0x2B, 0x00,
24335+ 0x00, 0xE0,
24336+
24337+ 0x0C, 0x00,
24338+ 0x1C, 0x00,
24339+ 0x2C, 0x00,
24340+ 0x00, 0xE0,
24341+
24342+ 0x0B, 0x65,
24343+ 0x1B, 0x65,
24344+ 0x2B, 0x65,
24345+ 0x00, 0xE0,
24346+
24347+ 0x0C, 0x65,
24348+ 0x1C, 0x65,
24349+ 0x2C, 0x65,
24350+ 0x00, 0xE0,
24351+
24352+ 0x0B, 0x1B, 0x60, 0xEC,
24353+ 0x36, 0xD7, 0x36, 0xAD,
24354+
24355+ 0x2B, 0x80, 0x60, 0xEC,
24356+ 0x0C, 0x1C, 0x60, 0xEC,
24357+
24358+ 0x3E, 0xD7, 0x3E, 0xAD,
24359+ 0x2C, 0x80, 0x60, 0xEC,
24360+
24361+ 0x0B, 0x2B, 0xDE, 0xE8,
24362+ 0x1B, 0x80, 0xDE, 0xE8,
24363+
24364+ 0x36, 0x80, 0x36, 0xBD,
24365+ 0x3E, 0x80, 0x3E, 0xBD,
24366+
24367+ 0x33, 0xD7, 0x0B, 0xBD,
24368+ 0x3B, 0xD7, 0x1B, 0xBD,
24369+
24370+ 0x46, 0x80, 0x46, 0xCF,
24371+ 0x57, 0x80, 0x57, 0xCF,
24372+
24373+ 0x66, 0x33, 0x66, 0xCF,
24374+ 0x47, 0x3B, 0x47, 0xCF,
24375+
24376+ 0x56, 0x33, 0x56, 0xCF,
24377+ 0x67, 0x3B, 0x67, 0xCF,
24378+
24379+ 0x0B, 0x48, 0xA0, 0xE8,
24380+ 0x1B, 0x58, 0xA0, 0xE8,
24381+
24382+ 0x2B, 0x68, 0xA0, 0xE8,
24383+ 0x0C, 0x49, 0xA0, 0xE8,
24384+
24385+ 0x1C, 0x59, 0xA0, 0xE8,
24386+ 0x2C, 0x69, 0xA0, 0xE8,
24387+
24388+ 0x0B, 0x00,
24389+ 0x1B, 0x00,
24390+ 0x2B, 0x00,
24391+ 0x00, 0xE0,
24392+
24393+ 0x0C, 0x00,
24394+ 0x1C, 0x00,
24395+ 0x2C, 0x00,
24396+ 0x00, 0xE0,
24397+
24398+ 0x0B, 0x65,
24399+ 0x1B, 0x65,
24400+ 0x2B, 0x65,
24401+ 0x00, 0xE0,
24402+
24403+ 0x0C, 0x65,
24404+ 0x1C, 0x65,
24405+ 0x2C, 0x65,
24406+ 0x00, 0xE0,
24407+
24408+ 0x0B, 0x1B, 0x60, 0xEC,
24409+ 0x34, 0xD7, 0x34, 0xAD,
24410+
24411+ 0x2B, 0x80, 0x60, 0xEC,
24412+ 0x0C, 0x1C, 0x60, 0xEC,
24413+
24414+ 0x3C, 0xD7, 0x3C, 0xAD,
24415+ 0x2C, 0x80, 0x60, 0xEC,
24416+
24417+ 0x0B, 0x2B, 0xDE, 0xE8,
24418+ 0x1B, 0x80, 0xDE, 0xE8,
24419+
24420+ 0x34, 0x80, 0x34, 0xBD,
24421+ 0x3C, 0x80, 0x3C, 0xBD,
24422+
24423+ 0x33, 0xD7, 0x0B, 0xBD,
24424+ 0x3B, 0xD7, 0x1B, 0xBD,
24425+
24426+ 0x48, 0x80, 0x48, 0xCF,
24427+ 0x59, 0x80, 0x59, 0xCF,
24428+
24429+ 0x68, 0x33, 0x68, 0xCF,
24430+ 0x49, 0x3B, 0x49, 0xCF,
24431+
24432+ 0xAD, 0xFF, 0x20, 0xEA,
24433+ 0x00, 0x80, 0x00, 0xE8,
24434+
24435+ 0x58, 0x33, 0x58, 0xCF,
24436+ 0x69, 0x3B, 0x69, 0xCF,
24437+
24438+ 0x6B, 0xFF, 0x20, 0xEA,
24439+ 0x57, 0xC0, 0xBF, 0xEA,
24440+
24441+ 0x00, 0x80, 0xA0, 0xE9,
24442+ 0x00, 0x00, 0xD8, 0xEC,
24443+
24444+};
24445+
24446+static unsigned char warp_g400_tgz[] = {
24447+
24448+ 0x00, 0x88, 0x98, 0xE9,
24449+ 0x00, 0x80, 0x00, 0xE8,
24450+
24451+ 0x00, 0x80, 0xA0, 0xE9,
24452+ 0x00, 0x00, 0xD8, 0xEC,
24453+
24454+ 0xFF, 0x80, 0xC0, 0xE9,
24455+ 0x00, 0x80, 0x00, 0xE8,
24456+
24457+ 0x22, 0x40, 0x48, 0xBF,
24458+ 0x2A, 0x40, 0x50, 0xBF,
24459+
24460+ 0x32, 0x41, 0x49, 0xBF,
24461+ 0x3A, 0x41, 0x51, 0xBF,
24462+
24463+ 0xC3, 0x6B,
24464+ 0xCB, 0x6B,
24465+ 0x00, 0x88, 0x98, 0xE9,
24466+
24467+ 0x73, 0x7B, 0xC8, 0xEC,
24468+ 0x96, 0xE2,
24469+ 0x41, 0x04,
24470+
24471+ 0x7B, 0x43, 0xA0, 0xE8,
24472+ 0x73, 0x4B, 0xA0, 0xE8,
24473+
24474+ 0xAD, 0xEE, 0x29, 0x9F,
24475+ 0x00, 0xE0,
24476+ 0x49, 0x04,
24477+
24478+ 0x90, 0xE2,
24479+ 0x51, 0x04,
24480+ 0x31, 0x46, 0xB1, 0xE8,
24481+
24482+ 0x49, 0x41, 0xC0, 0xEC,
24483+ 0x39, 0x57, 0xB1, 0xE8,
24484+
24485+ 0x00, 0x04,
24486+ 0x46, 0xE2,
24487+ 0x73, 0x53, 0xA0, 0xE8,
24488+
24489+ 0x51, 0x41, 0xC0, 0xEC,
24490+ 0x31, 0x00,
24491+ 0x39, 0x00,
24492+
24493+ 0x58, 0x80, 0x15, 0xEA,
24494+ 0x08, 0x04,
24495+ 0x10, 0x04,
24496+
24497+ 0x51, 0x49, 0xC0, 0xEC,
24498+ 0x2F, 0x41, 0x60, 0xEA,
24499+
24500+ 0x31, 0x20,
24501+ 0x39, 0x20,
24502+ 0x1F, 0x42, 0xA0, 0xE8,
24503+
24504+ 0x2A, 0x42, 0x4A, 0xBF,
24505+ 0x27, 0x4A, 0xA0, 0xE8,
24506+
24507+ 0x1A, 0x42, 0x52, 0xBF,
24508+ 0x1E, 0x49, 0x60, 0xEA,
24509+
24510+ 0x73, 0x7B, 0xC8, 0xEC,
24511+ 0x26, 0x51, 0x60, 0xEA,
24512+
24513+ 0x32, 0x40, 0x48, 0xBD,
24514+ 0x22, 0x40, 0x50, 0xBD,
24515+
24516+ 0x12, 0x41, 0x49, 0xBD,
24517+ 0x3A, 0x41, 0x51, 0xBD,
24518+
24519+ 0xBF, 0x2F, 0x26, 0xBD,
24520+ 0x00, 0xE0,
24521+ 0x7B, 0x72,
24522+
24523+ 0x32, 0x20,
24524+ 0x22, 0x20,
24525+ 0x12, 0x20,
24526+ 0x3A, 0x20,
24527+
24528+ 0x46, 0x31, 0x46, 0xBF,
24529+ 0x4E, 0x31, 0x4E, 0xBF,
24530+
24531+ 0xB3, 0xE2, 0x2D, 0x9F,
24532+ 0x00, 0x80, 0x00, 0xE8,
24533+
24534+ 0x56, 0x31, 0x56, 0xBF,
24535+ 0x47, 0x39, 0x47, 0xBF,
24536+
24537+ 0x4F, 0x39, 0x4F, 0xBF,
24538+ 0x57, 0x39, 0x57, 0xBF,
24539+
24540+ 0x4A, 0x80, 0x07, 0xEA,
24541+ 0x24, 0x41, 0x20, 0xE9,
24542+
24543+ 0x42, 0x73, 0xF8, 0xEC,
24544+ 0x00, 0xE0,
24545+ 0x2D, 0x73,
24546+
24547+ 0x33, 0x72,
24548+ 0x0C, 0xE3,
24549+ 0xA5, 0x2F, 0x1E, 0xBD,
24550+
24551+ 0x43, 0x43, 0x2D, 0xDF,
24552+ 0x4B, 0x4B, 0x2D, 0xDF,
24553+
24554+ 0xAE, 0x1E, 0x26, 0xBD,
24555+ 0x58, 0xE3,
24556+ 0x33, 0x66,
24557+
24558+ 0x53, 0x53, 0x2D, 0xDF,
24559+ 0x00, 0x80, 0x00, 0xE8,
24560+
24561+ 0xB8, 0x38, 0x33, 0xBF,
24562+ 0x00, 0xE0,
24563+ 0x59, 0xE3,
24564+
24565+ 0x1E, 0x12, 0x41, 0xE9,
24566+ 0x1A, 0x22, 0x41, 0xE9,
24567+
24568+ 0x2B, 0x40, 0x3D, 0xE9,
24569+ 0x3F, 0x4B, 0xA0, 0xE8,
24570+
24571+ 0x2D, 0x73,
24572+ 0x30, 0x76,
24573+ 0x05, 0x80, 0x3D, 0xEA,
24574+
24575+ 0x37, 0x43, 0xA0, 0xE8,
24576+ 0x3D, 0x53, 0xA0, 0xE8,
24577+
24578+ 0x48, 0x70, 0xF8, 0xEC,
24579+ 0x2B, 0x48, 0x3C, 0xE9,
24580+
24581+ 0x1F, 0x27, 0xBC, 0xE8,
24582+ 0x00, 0x80, 0x00, 0xE8,
24583+
24584+ 0x00, 0x80, 0x00, 0xE8,
24585+ 0x00, 0x80, 0x00, 0xE8,
24586+
24587+ 0x15, 0xC0, 0x20, 0xE9,
24588+ 0x15, 0xC0, 0x20, 0xE9,
24589+
24590+ 0x15, 0xC0, 0x20, 0xE9,
24591+ 0x15, 0xC0, 0x20, 0xE9,
24592+
24593+ 0x18, 0x3A, 0x41, 0xE9,
24594+ 0x1D, 0x32, 0x41, 0xE9,
24595+
24596+ 0x2A, 0x40, 0x20, 0xE9,
24597+ 0x56, 0x3D, 0x56, 0xDF,
24598+
24599+ 0x46, 0x37, 0x46, 0xDF,
24600+ 0x4E, 0x3F, 0x4E, 0xDF,
24601+
24602+ 0x16, 0x30, 0x20, 0xE9,
24603+ 0x4F, 0x3F, 0x4F, 0xDF,
24604+
24605+ 0x32, 0x32, 0x2D, 0xDF,
24606+ 0x22, 0x22, 0x2D, 0xDF,
24607+
24608+ 0x12, 0x12, 0x2D, 0xDF,
24609+ 0x3A, 0x3A, 0x2D, 0xDF,
24610+
24611+ 0x47, 0x37, 0x47, 0xDF,
24612+ 0x57, 0x3D, 0x57, 0xDF,
24613+
24614+ 0x3D, 0xCF, 0x74, 0xC0,
24615+ 0x37, 0xCF, 0x74, 0xC4,
24616+
24617+ 0x31, 0x53, 0x2F, 0x9F,
24618+ 0x34, 0x80, 0x20, 0xE9,
24619+
24620+ 0x39, 0xE5, 0x2C, 0x9F,
24621+ 0x3C, 0x3D, 0x20, 0xE9,
24622+
24623+ 0x0A, 0x44, 0x4C, 0xB0,
24624+ 0x02, 0x44, 0x54, 0xB0,
24625+
24626+ 0x2A, 0x44, 0x4C, 0xB2,
24627+ 0x1A, 0x44, 0x54, 0xB2,
24628+
24629+ 0x1D, 0x80, 0x3A, 0xEA,
24630+ 0x0A, 0x20,
24631+ 0x02, 0x20,
24632+
24633+ 0x3D, 0xCF, 0x74, 0xC2,
24634+ 0x2A, 0x20,
24635+ 0x1A, 0x20,
24636+
24637+ 0x30, 0x50, 0x2E, 0x9F,
24638+ 0x32, 0x31, 0x5F, 0xE9,
24639+
24640+ 0x38, 0x21, 0x2C, 0x9F,
24641+ 0x33, 0x39, 0x5F, 0xE9,
24642+
24643+ 0x31, 0x53, 0x2F, 0x9F,
24644+ 0x00, 0x80, 0x00, 0xE8,
24645+
24646+ 0x2A, 0x44, 0x4C, 0xB4,
24647+ 0x1A, 0x44, 0x54, 0xB4,
24648+
24649+ 0x39, 0xE5, 0x2C, 0x9F,
24650+ 0x38, 0x3D, 0x20, 0xE9,
24651+
24652+ 0x88, 0x73, 0x5E, 0xE9,
24653+ 0x2A, 0x20,
24654+ 0x1A, 0x20,
24655+
24656+ 0x2A, 0x46, 0x4E, 0xBF,
24657+ 0x1A, 0x46, 0x56, 0xBF,
24658+
24659+ 0x31, 0x53, 0x2F, 0x9F,
24660+ 0x3E, 0x30, 0x4F, 0xE9,
24661+
24662+ 0x39, 0xE5, 0x2C, 0x9F,
24663+ 0x3F, 0x38, 0x4F, 0xE9,
24664+
24665+ 0x0A, 0x47, 0x4F, 0xBF,
24666+ 0x02, 0x47, 0x57, 0xBF,
24667+
24668+ 0x31, 0x53, 0x2F, 0x9F,
24669+ 0x3A, 0x31, 0x4F, 0xE9,
24670+
24671+ 0x39, 0xE5, 0x2C, 0x9F,
24672+ 0x3B, 0x39, 0x4F, 0xE9,
24673+
24674+ 0x2A, 0x43, 0x4B, 0xBF,
24675+ 0x1A, 0x43, 0x53, 0xBF,
24676+
24677+ 0x30, 0x50, 0x2E, 0x9F,
24678+ 0x36, 0x31, 0x4F, 0xE9,
24679+
24680+ 0x38, 0x21, 0x2C, 0x9F,
24681+ 0x37, 0x39, 0x4F, 0xE9,
24682+
24683+ 0x31, 0x53, 0x2F, 0x9F,
24684+ 0x80, 0x31, 0x57, 0xE9,
24685+
24686+ 0x39, 0xE5, 0x2C, 0x9F,
24687+ 0x81, 0x39, 0x57, 0xE9,
24688+
24689+ 0x37, 0x48, 0x50, 0xBD,
24690+ 0x8A, 0x36, 0x20, 0xE9,
24691+
24692+ 0x86, 0x76, 0x57, 0xE9,
24693+ 0x8B, 0x3E, 0x20, 0xE9,
24694+
24695+ 0x82, 0x30, 0x57, 0xE9,
24696+ 0x87, 0x77, 0x57, 0xE9,
24697+
24698+ 0x83, 0x38, 0x57, 0xE9,
24699+ 0x35, 0x49, 0x51, 0xBD,
24700+
24701+ 0x84, 0x31, 0x5E, 0xE9,
24702+ 0x30, 0x1F, 0x5F, 0xE9,
24703+
24704+ 0x85, 0x39, 0x5E, 0xE9,
24705+ 0x57, 0x25, 0x20, 0xE9,
24706+
24707+ 0x2B, 0x48, 0x20, 0xE9,
24708+ 0x1D, 0x37, 0xE1, 0xEA,
24709+
24710+ 0x1E, 0x35, 0xE1, 0xEA,
24711+ 0x00, 0xE0,
24712+ 0x26, 0x77,
24713+
24714+ 0x24, 0x49, 0x20, 0xE9,
24715+ 0xAF, 0xFF, 0x20, 0xEA,
24716+
24717+ 0x16, 0x26, 0x20, 0xE9,
24718+ 0x57, 0x2E, 0xBF, 0xEA,
24719+
24720+ 0x1C, 0x46, 0xA0, 0xE8,
24721+ 0x23, 0x4E, 0xA0, 0xE8,
24722+
24723+ 0x2B, 0x56, 0xA0, 0xE8,
24724+ 0x1D, 0x47, 0xA0, 0xE8,
24725+
24726+ 0x24, 0x4F, 0xA0, 0xE8,
24727+ 0x2C, 0x57, 0xA0, 0xE8,
24728+
24729+ 0x1C, 0x00,
24730+ 0x23, 0x00,
24731+ 0x2B, 0x00,
24732+ 0x00, 0xE0,
24733+
24734+ 0x1D, 0x00,
24735+ 0x24, 0x00,
24736+ 0x2C, 0x00,
24737+ 0x00, 0xE0,
24738+
24739+ 0x1C, 0x65,
24740+ 0x23, 0x65,
24741+ 0x2B, 0x65,
24742+ 0x00, 0xE0,
24743+
24744+ 0x1D, 0x65,
24745+ 0x24, 0x65,
24746+ 0x2C, 0x65,
24747+ 0x00, 0xE0,
24748+
24749+ 0x1C, 0x23, 0x60, 0xEC,
24750+ 0x36, 0xD7, 0x36, 0xAD,
24751+
24752+ 0x2B, 0x80, 0x60, 0xEC,
24753+ 0x1D, 0x24, 0x60, 0xEC,
24754+
24755+ 0x3E, 0xD7, 0x3E, 0xAD,
24756+ 0x2C, 0x80, 0x60, 0xEC,
24757+
24758+ 0x1C, 0x2B, 0xDE, 0xE8,
24759+ 0x23, 0x80, 0xDE, 0xE8,
24760+
24761+ 0x36, 0x80, 0x36, 0xBD,
24762+ 0x3E, 0x80, 0x3E, 0xBD,
24763+
24764+ 0x33, 0xD7, 0x1C, 0xBD,
24765+ 0x3B, 0xD7, 0x23, 0xBD,
24766+
24767+ 0x46, 0x80, 0x46, 0xCF,
24768+ 0x4F, 0x80, 0x4F, 0xCF,
24769+
24770+ 0x56, 0x33, 0x56, 0xCF,
24771+ 0x47, 0x3B, 0x47, 0xCF,
24772+
24773+ 0xD6, 0xFF, 0x20, 0xEA,
24774+ 0x00, 0x80, 0x00, 0xE8,
24775+
24776+ 0x4E, 0x33, 0x4E, 0xCF,
24777+ 0x57, 0x3B, 0x57, 0xCF,
24778+
24779+ 0x9D, 0xFF, 0x20, 0xEA,
24780+ 0x57, 0xC0, 0xBF, 0xEA,
24781+
24782+ 0x00, 0x80, 0xA0, 0xE9,
24783+ 0x00, 0x00, 0xD8, 0xEC,
24784+
24785+};
24786+
24787+static unsigned char warp_g400_tgza[] = {
24788+
24789+ 0x00, 0x88, 0x98, 0xE9,
24790+ 0x00, 0x80, 0x00, 0xE8,
24791+
24792+ 0x00, 0x80, 0xA0, 0xE9,
24793+ 0x00, 0x00, 0xD8, 0xEC,
24794+
24795+ 0xFF, 0x80, 0xC0, 0xE9,
24796+ 0x00, 0x80, 0x00, 0xE8,
24797+
24798+ 0x22, 0x40, 0x48, 0xBF,
24799+ 0x2A, 0x40, 0x50, 0xBF,
24800+
24801+ 0x32, 0x41, 0x49, 0xBF,
24802+ 0x3A, 0x41, 0x51, 0xBF,
24803+
24804+ 0xC3, 0x6B,
24805+ 0xCB, 0x6B,
24806+ 0x00, 0x88, 0x98, 0xE9,
24807+
24808+ 0x73, 0x7B, 0xC8, 0xEC,
24809+ 0x96, 0xE2,
24810+ 0x41, 0x04,
24811+
24812+ 0x7B, 0x43, 0xA0, 0xE8,
24813+ 0x73, 0x4B, 0xA0, 0xE8,
24814+
24815+ 0xAD, 0xEE, 0x29, 0x9F,
24816+ 0x00, 0xE0,
24817+ 0x49, 0x04,
24818+
24819+ 0x90, 0xE2,
24820+ 0x51, 0x04,
24821+ 0x31, 0x46, 0xB1, 0xE8,
24822+
24823+ 0x49, 0x41, 0xC0, 0xEC,
24824+ 0x39, 0x57, 0xB1, 0xE8,
24825+
24826+ 0x00, 0x04,
24827+ 0x46, 0xE2,
24828+ 0x73, 0x53, 0xA0, 0xE8,
24829+
24830+ 0x51, 0x41, 0xC0, 0xEC,
24831+ 0x31, 0x00,
24832+ 0x39, 0x00,
24833+
24834+ 0x5C, 0x80, 0x15, 0xEA,
24835+ 0x08, 0x04,
24836+ 0x10, 0x04,
24837+
24838+ 0x51, 0x49, 0xC0, 0xEC,
24839+ 0x2F, 0x41, 0x60, 0xEA,
24840+
24841+ 0x31, 0x20,
24842+ 0x39, 0x20,
24843+ 0x1F, 0x42, 0xA0, 0xE8,
24844+
24845+ 0x2A, 0x42, 0x4A, 0xBF,
24846+ 0x27, 0x4A, 0xA0, 0xE8,
24847+
24848+ 0x1A, 0x42, 0x52, 0xBF,
24849+ 0x1E, 0x49, 0x60, 0xEA,
24850+
24851+ 0x73, 0x7B, 0xC8, 0xEC,
24852+ 0x26, 0x51, 0x60, 0xEA,
24853+
24854+ 0x32, 0x40, 0x48, 0xBD,
24855+ 0x22, 0x40, 0x50, 0xBD,
24856+
24857+ 0x12, 0x41, 0x49, 0xBD,
24858+ 0x3A, 0x41, 0x51, 0xBD,
24859+
24860+ 0xBF, 0x2F, 0x26, 0xBD,
24861+ 0x00, 0xE0,
24862+ 0x7B, 0x72,
24863+
24864+ 0x32, 0x20,
24865+ 0x22, 0x20,
24866+ 0x12, 0x20,
24867+ 0x3A, 0x20,
24868+
24869+ 0x46, 0x31, 0x46, 0xBF,
24870+ 0x4E, 0x31, 0x4E, 0xBF,
24871+
24872+ 0xB3, 0xE2, 0x2D, 0x9F,
24873+ 0x00, 0x80, 0x00, 0xE8,
24874+
24875+ 0x56, 0x31, 0x56, 0xBF,
24876+ 0x47, 0x39, 0x47, 0xBF,
24877+
24878+ 0x4F, 0x39, 0x4F, 0xBF,
24879+ 0x57, 0x39, 0x57, 0xBF,
24880+
24881+ 0x4E, 0x80, 0x07, 0xEA,
24882+ 0x24, 0x41, 0x20, 0xE9,
24883+
24884+ 0x42, 0x73, 0xF8, 0xEC,
24885+ 0x00, 0xE0,
24886+ 0x2D, 0x73,
24887+
24888+ 0x33, 0x72,
24889+ 0x0C, 0xE3,
24890+ 0xA5, 0x2F, 0x1E, 0xBD,
24891+
24892+ 0x43, 0x43, 0x2D, 0xDF,
24893+ 0x4B, 0x4B, 0x2D, 0xDF,
24894+
24895+ 0xAE, 0x1E, 0x26, 0xBD,
24896+ 0x58, 0xE3,
24897+ 0x33, 0x66,
24898+
24899+ 0x53, 0x53, 0x2D, 0xDF,
24900+ 0x00, 0x80, 0x00, 0xE8,
24901+
24902+ 0xB8, 0x38, 0x33, 0xBF,
24903+ 0x00, 0xE0,
24904+ 0x59, 0xE3,
24905+
24906+ 0x1E, 0x12, 0x41, 0xE9,
24907+ 0x1A, 0x22, 0x41, 0xE9,
24908+
24909+ 0x2B, 0x40, 0x3D, 0xE9,
24910+ 0x3F, 0x4B, 0xA0, 0xE8,
24911+
24912+ 0x2D, 0x73,
24913+ 0x30, 0x76,
24914+ 0x05, 0x80, 0x3D, 0xEA,
24915+
24916+ 0x37, 0x43, 0xA0, 0xE8,
24917+ 0x3D, 0x53, 0xA0, 0xE8,
24918+
24919+ 0x48, 0x70, 0xF8, 0xEC,
24920+ 0x2B, 0x48, 0x3C, 0xE9,
24921+
24922+ 0x1F, 0x27, 0xBC, 0xE8,
24923+ 0x00, 0x80, 0x00, 0xE8,
24924+
24925+ 0x00, 0x80, 0x00, 0xE8,
24926+ 0x00, 0x80, 0x00, 0xE8,
24927+
24928+ 0x15, 0xC0, 0x20, 0xE9,
24929+ 0x15, 0xC0, 0x20, 0xE9,
24930+
24931+ 0x15, 0xC0, 0x20, 0xE9,
24932+ 0x15, 0xC0, 0x20, 0xE9,
24933+
24934+ 0x18, 0x3A, 0x41, 0xE9,
24935+ 0x1D, 0x32, 0x41, 0xE9,
24936+
24937+ 0x2A, 0x40, 0x20, 0xE9,
24938+ 0x56, 0x3D, 0x56, 0xDF,
24939+
24940+ 0x46, 0x37, 0x46, 0xDF,
24941+ 0x4E, 0x3F, 0x4E, 0xDF,
24942+
24943+ 0x16, 0x30, 0x20, 0xE9,
24944+ 0x4F, 0x3F, 0x4F, 0xDF,
24945+
24946+ 0x32, 0x32, 0x2D, 0xDF,
24947+ 0x22, 0x22, 0x2D, 0xDF,
24948+
24949+ 0x12, 0x12, 0x2D, 0xDF,
24950+ 0x3A, 0x3A, 0x2D, 0xDF,
24951+
24952+ 0x47, 0x37, 0x47, 0xDF,
24953+ 0x57, 0x3D, 0x57, 0xDF,
24954+
24955+ 0x3D, 0xCF, 0x74, 0xC0,
24956+ 0x37, 0xCF, 0x74, 0xC4,
24957+
24958+ 0x31, 0x53, 0x2F, 0x9F,
24959+ 0x34, 0x80, 0x20, 0xE9,
24960+
24961+ 0x39, 0xE5, 0x2C, 0x9F,
24962+ 0x3C, 0x3D, 0x20, 0xE9,
24963+
24964+ 0x27, 0xCF, 0x74, 0xC6,
24965+ 0x3D, 0xCF, 0x74, 0xC2,
24966+
24967+ 0x0A, 0x44, 0x4C, 0xB0,
24968+ 0x02, 0x44, 0x54, 0xB0,
24969+
24970+ 0x2A, 0x44, 0x4C, 0xB2,
24971+ 0x1A, 0x44, 0x54, 0xB2,
24972+
24973+ 0x20, 0x80, 0x3A, 0xEA,
24974+ 0x0A, 0x20,
24975+ 0x02, 0x20,
24976+
24977+ 0x88, 0x73, 0x5E, 0xE9,
24978+ 0x2A, 0x20,
24979+ 0x1A, 0x20,
24980+
24981+ 0x30, 0x50, 0x2E, 0x9F,
24982+ 0x32, 0x31, 0x5F, 0xE9,
24983+
24984+ 0x38, 0x21, 0x2C, 0x9F,
24985+ 0x33, 0x39, 0x5F, 0xE9,
24986+
24987+ 0x31, 0x53, 0x2F, 0x9F,
24988+ 0x9C, 0x27, 0x20, 0xE9,
24989+
24990+ 0x0A, 0x44, 0x4C, 0xB4,
24991+ 0x02, 0x44, 0x54, 0xB4,
24992+
24993+ 0x2A, 0x44, 0x4C, 0xB6,
24994+ 0x1A, 0x44, 0x54, 0xB6,
24995+
24996+ 0x39, 0xE5, 0x2C, 0x9F,
24997+ 0x38, 0x3D, 0x20, 0xE9,
24998+
24999+ 0x0A, 0x20,
25000+ 0x02, 0x20,
25001+ 0x2A, 0x20,
25002+ 0x1A, 0x20,
25003+
25004+ 0x0A, 0x47, 0x4F, 0xBF,
25005+ 0x02, 0x47, 0x57, 0xBF,
25006+
25007+ 0x30, 0x50, 0x2E, 0x9F,
25008+ 0x3E, 0x30, 0x4F, 0xE9,
25009+
25010+ 0x38, 0x21, 0x2C, 0x9F,
25011+ 0x3F, 0x38, 0x4F, 0xE9,
25012+
25013+ 0x2A, 0x46, 0x4E, 0xBF,
25014+ 0x1A, 0x46, 0x56, 0xBF,
25015+
25016+ 0x31, 0x53, 0x2F, 0x9F,
25017+ 0x3A, 0x31, 0x4F, 0xE9,
25018+
25019+ 0x39, 0xE5, 0x2C, 0x9F,
25020+ 0x3B, 0x39, 0x4F, 0xE9,
25021+
25022+ 0x31, 0x53, 0x2F, 0x9F,
25023+ 0x36, 0x30, 0x4F, 0xE9,
25024+
25025+ 0x39, 0xE5, 0x2C, 0x9F,
25026+ 0x37, 0x38, 0x4F, 0xE9,
25027+
25028+ 0x2A, 0x43, 0x4B, 0xBF,
25029+ 0x1A, 0x43, 0x53, 0xBF,
25030+
25031+ 0x30, 0x50, 0x2E, 0x9F,
25032+ 0x9D, 0x31, 0x4F, 0xE9,
25033+
25034+ 0x38, 0x21, 0x2C, 0x9F,
25035+ 0x9E, 0x39, 0x4F, 0xE9,
25036+
25037+ 0x31, 0x53, 0x2F, 0x9F,
25038+ 0x80, 0x31, 0x57, 0xE9,
25039+
25040+ 0x39, 0xE5, 0x2C, 0x9F,
25041+ 0x81, 0x39, 0x57, 0xE9,
25042+
25043+ 0x37, 0x48, 0x50, 0xBD,
25044+ 0x8A, 0x36, 0x20, 0xE9,
25045+
25046+ 0x86, 0x76, 0x57, 0xE9,
25047+ 0x8B, 0x3E, 0x20, 0xE9,
25048+
25049+ 0x82, 0x30, 0x57, 0xE9,
25050+ 0x87, 0x77, 0x57, 0xE9,
25051+
25052+ 0x83, 0x38, 0x57, 0xE9,
25053+ 0x35, 0x49, 0x51, 0xBD,
25054+
25055+ 0x84, 0x31, 0x5E, 0xE9,
25056+ 0x30, 0x1F, 0x5F, 0xE9,
25057+
25058+ 0x85, 0x39, 0x5E, 0xE9,
25059+ 0x57, 0x25, 0x20, 0xE9,
25060+
25061+ 0x2B, 0x48, 0x20, 0xE9,
25062+ 0x1D, 0x37, 0xE1, 0xEA,
25063+
25064+ 0x1E, 0x35, 0xE1, 0xEA,
25065+ 0x00, 0xE0,
25066+ 0x26, 0x77,
25067+
25068+ 0x24, 0x49, 0x20, 0xE9,
25069+ 0xAB, 0xFF, 0x20, 0xEA,
25070+
25071+ 0x16, 0x26, 0x20, 0xE9,
25072+ 0x57, 0x2E, 0xBF, 0xEA,
25073+
25074+ 0x1C, 0x46, 0xA0, 0xE8,
25075+ 0x23, 0x4E, 0xA0, 0xE8,
25076+
25077+ 0x2B, 0x56, 0xA0, 0xE8,
25078+ 0x1D, 0x47, 0xA0, 0xE8,
25079+
25080+ 0x24, 0x4F, 0xA0, 0xE8,
25081+ 0x2C, 0x57, 0xA0, 0xE8,
25082+
25083+ 0x1C, 0x00,
25084+ 0x23, 0x00,
25085+ 0x2B, 0x00,
25086+ 0x00, 0xE0,
25087+
25088+ 0x1D, 0x00,
25089+ 0x24, 0x00,
25090+ 0x2C, 0x00,
25091+ 0x00, 0xE0,
25092+
25093+ 0x1C, 0x65,
25094+ 0x23, 0x65,
25095+ 0x2B, 0x65,
25096+ 0x00, 0xE0,
25097+
25098+ 0x1D, 0x65,
25099+ 0x24, 0x65,
25100+ 0x2C, 0x65,
25101+ 0x00, 0xE0,
25102+
25103+ 0x1C, 0x23, 0x60, 0xEC,
25104+ 0x36, 0xD7, 0x36, 0xAD,
25105+
25106+ 0x2B, 0x80, 0x60, 0xEC,
25107+ 0x1D, 0x24, 0x60, 0xEC,
25108+
25109+ 0x3E, 0xD7, 0x3E, 0xAD,
25110+ 0x2C, 0x80, 0x60, 0xEC,
25111+
25112+ 0x1C, 0x2B, 0xDE, 0xE8,
25113+ 0x23, 0x80, 0xDE, 0xE8,
25114+
25115+ 0x36, 0x80, 0x36, 0xBD,
25116+ 0x3E, 0x80, 0x3E, 0xBD,
25117+
25118+ 0x33, 0xD7, 0x1C, 0xBD,
25119+ 0x3B, 0xD7, 0x23, 0xBD,
25120+
25121+ 0x46, 0x80, 0x46, 0xCF,
25122+ 0x4F, 0x80, 0x4F, 0xCF,
25123+
25124+ 0x56, 0x33, 0x56, 0xCF,
25125+ 0x47, 0x3B, 0x47, 0xCF,
25126+
25127+ 0xD3, 0xFF, 0x20, 0xEA,
25128+ 0x00, 0x80, 0x00, 0xE8,
25129+
25130+ 0x4E, 0x33, 0x4E, 0xCF,
25131+ 0x57, 0x3B, 0x57, 0xCF,
25132+
25133+ 0x99, 0xFF, 0x20, 0xEA,
25134+ 0x57, 0xC0, 0xBF, 0xEA,
25135+
25136+ 0x00, 0x80, 0xA0, 0xE9,
25137+ 0x00, 0x00, 0xD8, 0xEC,
25138+
25139+};
25140+
25141+static unsigned char warp_g400_tgzaf[] = {
25142+
25143+ 0x00, 0x88, 0x98, 0xE9,
25144+ 0x00, 0x80, 0x00, 0xE8,
25145+
25146+ 0x00, 0x80, 0xA0, 0xE9,
25147+ 0x00, 0x00, 0xD8, 0xEC,
25148+
25149+ 0xFF, 0x80, 0xC0, 0xE9,
25150+ 0x00, 0x80, 0x00, 0xE8,
25151+
25152+ 0x22, 0x40, 0x48, 0xBF,
25153+ 0x2A, 0x40, 0x50, 0xBF,
25154+
25155+ 0x32, 0x41, 0x49, 0xBF,
25156+ 0x3A, 0x41, 0x51, 0xBF,
25157+
25158+ 0xC3, 0x6B,
25159+ 0xCB, 0x6B,
25160+ 0x00, 0x88, 0x98, 0xE9,
25161+
25162+ 0x73, 0x7B, 0xC8, 0xEC,
25163+ 0x96, 0xE2,
25164+ 0x41, 0x04,
25165+
25166+ 0x7B, 0x43, 0xA0, 0xE8,
25167+ 0x73, 0x4B, 0xA0, 0xE8,
25168+
25169+ 0xAD, 0xEE, 0x29, 0x9F,
25170+ 0x00, 0xE0,
25171+ 0x49, 0x04,
25172+
25173+ 0x90, 0xE2,
25174+ 0x51, 0x04,
25175+ 0x31, 0x46, 0xB1, 0xE8,
25176+
25177+ 0x49, 0x41, 0xC0, 0xEC,
25178+ 0x39, 0x57, 0xB1, 0xE8,
25179+
25180+ 0x00, 0x04,
25181+ 0x46, 0xE2,
25182+ 0x73, 0x53, 0xA0, 0xE8,
25183+
25184+ 0x51, 0x41, 0xC0, 0xEC,
25185+ 0x31, 0x00,
25186+ 0x39, 0x00,
25187+
25188+ 0x61, 0x80, 0x15, 0xEA,
25189+ 0x08, 0x04,
25190+ 0x10, 0x04,
25191+
25192+ 0x51, 0x49, 0xC0, 0xEC,
25193+ 0x2F, 0x41, 0x60, 0xEA,
25194+
25195+ 0x31, 0x20,
25196+ 0x39, 0x20,
25197+ 0x1F, 0x42, 0xA0, 0xE8,
25198+
25199+ 0x2A, 0x42, 0x4A, 0xBF,
25200+ 0x27, 0x4A, 0xA0, 0xE8,
25201+
25202+ 0x1A, 0x42, 0x52, 0xBF,
25203+ 0x1E, 0x49, 0x60, 0xEA,
25204+
25205+ 0x73, 0x7B, 0xC8, 0xEC,
25206+ 0x26, 0x51, 0x60, 0xEA,
25207+
25208+ 0x32, 0x40, 0x48, 0xBD,
25209+ 0x22, 0x40, 0x50, 0xBD,
25210+
25211+ 0x12, 0x41, 0x49, 0xBD,
25212+ 0x3A, 0x41, 0x51, 0xBD,
25213+
25214+ 0xBF, 0x2F, 0x26, 0xBD,
25215+ 0x00, 0xE0,
25216+ 0x7B, 0x72,
25217+
25218+ 0x32, 0x20,
25219+ 0x22, 0x20,
25220+ 0x12, 0x20,
25221+ 0x3A, 0x20,
25222+
25223+ 0x46, 0x31, 0x46, 0xBF,
25224+ 0x4E, 0x31, 0x4E, 0xBF,
25225+
25226+ 0xB3, 0xE2, 0x2D, 0x9F,
25227+ 0x00, 0x80, 0x00, 0xE8,
25228+
25229+ 0x56, 0x31, 0x56, 0xBF,
25230+ 0x47, 0x39, 0x47, 0xBF,
25231+
25232+ 0x4F, 0x39, 0x4F, 0xBF,
25233+ 0x57, 0x39, 0x57, 0xBF,
25234+
25235+ 0x53, 0x80, 0x07, 0xEA,
25236+ 0x24, 0x41, 0x20, 0xE9,
25237+
25238+ 0x42, 0x73, 0xF8, 0xEC,
25239+ 0x00, 0xE0,
25240+ 0x2D, 0x73,
25241+
25242+ 0x33, 0x72,
25243+ 0x0C, 0xE3,
25244+ 0xA5, 0x2F, 0x1E, 0xBD,
25245+
25246+ 0x43, 0x43, 0x2D, 0xDF,
25247+ 0x4B, 0x4B, 0x2D, 0xDF,
25248+
25249+ 0xAE, 0x1E, 0x26, 0xBD,
25250+ 0x58, 0xE3,
25251+ 0x33, 0x66,
25252+
25253+ 0x53, 0x53, 0x2D, 0xDF,
25254+ 0x00, 0x80, 0x00, 0xE8,
25255+
25256+ 0xB8, 0x38, 0x33, 0xBF,
25257+ 0x00, 0xE0,
25258+ 0x59, 0xE3,
25259+
25260+ 0x1E, 0x12, 0x41, 0xE9,
25261+ 0x1A, 0x22, 0x41, 0xE9,
25262+
25263+ 0x2B, 0x40, 0x3D, 0xE9,
25264+ 0x3F, 0x4B, 0xA0, 0xE8,
25265+
25266+ 0x2D, 0x73,
25267+ 0x30, 0x76,
25268+ 0x05, 0x80, 0x3D, 0xEA,
25269+
25270+ 0x37, 0x43, 0xA0, 0xE8,
25271+ 0x3D, 0x53, 0xA0, 0xE8,
25272+
25273+ 0x48, 0x70, 0xF8, 0xEC,
25274+ 0x2B, 0x48, 0x3C, 0xE9,
25275+
25276+ 0x1F, 0x27, 0xBC, 0xE8,
25277+ 0x00, 0x80, 0x00, 0xE8,
25278+
25279+ 0x00, 0x80, 0x00, 0xE8,
25280+ 0x00, 0x80, 0x00, 0xE8,
25281+
25282+ 0x15, 0xC0, 0x20, 0xE9,
25283+ 0x15, 0xC0, 0x20, 0xE9,
25284+
25285+ 0x15, 0xC0, 0x20, 0xE9,
25286+ 0x15, 0xC0, 0x20, 0xE9,
25287+
25288+ 0x18, 0x3A, 0x41, 0xE9,
25289+ 0x1D, 0x32, 0x41, 0xE9,
25290+
25291+ 0x2A, 0x40, 0x20, 0xE9,
25292+ 0x56, 0x3D, 0x56, 0xDF,
25293+
25294+ 0x46, 0x37, 0x46, 0xDF,
25295+ 0x4E, 0x3F, 0x4E, 0xDF,
25296+
25297+ 0x16, 0x30, 0x20, 0xE9,
25298+ 0x4F, 0x3F, 0x4F, 0xDF,
25299+
25300+ 0x32, 0x32, 0x2D, 0xDF,
25301+ 0x22, 0x22, 0x2D, 0xDF,
25302+
25303+ 0x12, 0x12, 0x2D, 0xDF,
25304+ 0x3A, 0x3A, 0x2D, 0xDF,
25305+
25306+ 0x47, 0x37, 0x47, 0xDF,
25307+ 0x57, 0x3D, 0x57, 0xDF,
25308+
25309+ 0x3D, 0xCF, 0x74, 0xC0,
25310+ 0x37, 0xCF, 0x74, 0xC4,
25311+
25312+ 0x0A, 0x44, 0x4C, 0xB0,
25313+ 0x02, 0x44, 0x54, 0xB0,
25314+
25315+ 0x31, 0x53, 0x2F, 0x9F,
25316+ 0x34, 0x37, 0x20, 0xE9,
25317+
25318+ 0x39, 0xE5, 0x2C, 0x9F,
25319+ 0x3C, 0x3D, 0x20, 0xE9,
25320+
25321+ 0x2A, 0x44, 0x4C, 0xB2,
25322+ 0x1A, 0x44, 0x54, 0xB2,
25323+
25324+ 0x26, 0x80, 0x3A, 0xEA,
25325+ 0x0A, 0x20,
25326+ 0x02, 0x20,
25327+
25328+ 0x88, 0x73, 0x5E, 0xE9,
25329+ 0x2A, 0x20,
25330+ 0x1A, 0x20,
25331+
25332+ 0x3D, 0xCF, 0x74, 0xC2,
25333+ 0x27, 0xCF, 0x74, 0xC6,
25334+
25335+ 0x30, 0x50, 0x2E, 0x9F,
25336+ 0x32, 0x31, 0x5F, 0xE9,
25337+
25338+ 0x38, 0x21, 0x2C, 0x9F,
25339+ 0x33, 0x39, 0x5F, 0xE9,
25340+
25341+ 0x31, 0x53, 0x2F, 0x9F,
25342+ 0x9C, 0x27, 0x20, 0xE9,
25343+
25344+ 0x0A, 0x44, 0x4C, 0xB4,
25345+ 0x02, 0x44, 0x54, 0xB4,
25346+
25347+ 0x2A, 0x44, 0x4C, 0xB6,
25348+ 0x1A, 0x44, 0x54, 0xB6,
25349+
25350+ 0x39, 0xE5, 0x2C, 0x9F,
25351+ 0x38, 0x3D, 0x20, 0xE9,
25352+
25353+ 0x0A, 0x20,
25354+ 0x02, 0x20,
25355+ 0x2A, 0x20,
25356+ 0x1A, 0x20,
25357+
25358+ 0x3D, 0xCF, 0x75, 0xC6,
25359+ 0x00, 0x80, 0x00, 0xE8,
25360+
25361+ 0x30, 0x50, 0x2E, 0x9F,
25362+ 0x3E, 0x30, 0x4F, 0xE9,
25363+
25364+ 0x38, 0x21, 0x2C, 0x9F,
25365+ 0x3F, 0x38, 0x4F, 0xE9,
25366+
25367+ 0x0A, 0x45, 0x4D, 0xB6,
25368+ 0x02, 0x45, 0x55, 0xB6,
25369+
25370+ 0x31, 0x53, 0x2F, 0x9F,
25371+ 0x3A, 0x31, 0x4F, 0xE9,
25372+
25373+ 0x39, 0xE5, 0x2C, 0x9F,
25374+ 0x3B, 0x39, 0x4F, 0xE9,
25375+
25376+ 0x31, 0x3D, 0x20, 0xE9,
25377+ 0x0A, 0x20,
25378+ 0x02, 0x20,
25379+
25380+ 0x2A, 0x46, 0x4E, 0xBF,
25381+ 0x1A, 0x46, 0x56, 0xBF,
25382+
25383+ 0x0A, 0x47, 0x4F, 0xBF,
25384+ 0x02, 0x47, 0x57, 0xBF,
25385+
25386+ 0x30, 0x50, 0x2E, 0x9F,
25387+ 0x36, 0x30, 0x4F, 0xE9,
25388+
25389+ 0x38, 0x21, 0x2C, 0x9F,
25390+ 0x37, 0x38, 0x4F, 0xE9,
25391+
25392+ 0x31, 0x53, 0x2F, 0x9F,
25393+ 0x9D, 0x31, 0x4F, 0xE9,
25394+
25395+ 0x39, 0xE5, 0x2C, 0x9F,
25396+ 0x9E, 0x39, 0x4F, 0xE9,
25397+
25398+ 0x2A, 0x43, 0x4B, 0xBF,
25399+ 0x1A, 0x43, 0x53, 0xBF,
25400+
25401+ 0x30, 0x50, 0x2E, 0x9F,
25402+ 0x35, 0x30, 0x4F, 0xE9,
25403+
25404+ 0x38, 0x21, 0x2C, 0x9F,
25405+ 0x39, 0x38, 0x4F, 0xE9,
25406+
25407+ 0x31, 0x53, 0x2F, 0x9F,
25408+ 0x80, 0x31, 0x57, 0xE9,
25409+
25410+ 0x39, 0xE5, 0x2C, 0x9F,
25411+ 0x81, 0x39, 0x57, 0xE9,
25412+
25413+ 0x37, 0x48, 0x50, 0xBD,
25414+ 0x8A, 0x36, 0x20, 0xE9,
25415+
25416+ 0x86, 0x76, 0x57, 0xE9,
25417+ 0x8B, 0x3E, 0x20, 0xE9,
25418+
25419+ 0x82, 0x30, 0x57, 0xE9,
25420+ 0x87, 0x77, 0x57, 0xE9,
25421+
25422+ 0x83, 0x38, 0x57, 0xE9,
25423+ 0x35, 0x49, 0x51, 0xBD,
25424+
25425+ 0x84, 0x31, 0x5E, 0xE9,
25426+ 0x30, 0x1F, 0x5F, 0xE9,
25427+
25428+ 0x85, 0x39, 0x5E, 0xE9,
25429+ 0x57, 0x25, 0x20, 0xE9,
25430+
25431+ 0x2B, 0x48, 0x20, 0xE9,
25432+ 0x1D, 0x37, 0xE1, 0xEA,
25433+
25434+ 0x1E, 0x35, 0xE1, 0xEA,
25435+ 0x00, 0xE0,
25436+ 0x26, 0x77,
25437+
25438+ 0x24, 0x49, 0x20, 0xE9,
25439+ 0xA6, 0xFF, 0x20, 0xEA,
25440+
25441+ 0x16, 0x26, 0x20, 0xE9,
25442+ 0x57, 0x2E, 0xBF, 0xEA,
25443+
25444+ 0x1C, 0x46, 0xA0, 0xE8,
25445+ 0x23, 0x4E, 0xA0, 0xE8,
25446+
25447+ 0x2B, 0x56, 0xA0, 0xE8,
25448+ 0x1D, 0x47, 0xA0, 0xE8,
25449+
25450+ 0x24, 0x4F, 0xA0, 0xE8,
25451+ 0x2C, 0x57, 0xA0, 0xE8,
25452+
25453+ 0x1C, 0x00,
25454+ 0x23, 0x00,
25455+ 0x2B, 0x00,
25456+ 0x00, 0xE0,
25457+
25458+ 0x1D, 0x00,
25459+ 0x24, 0x00,
25460+ 0x2C, 0x00,
25461+ 0x00, 0xE0,
25462+
25463+ 0x1C, 0x65,
25464+ 0x23, 0x65,
25465+ 0x2B, 0x65,
25466+ 0x00, 0xE0,
25467+
25468+ 0x1D, 0x65,
25469+ 0x24, 0x65,
25470+ 0x2C, 0x65,
25471+ 0x00, 0xE0,
25472+
25473+ 0x1C, 0x23, 0x60, 0xEC,
25474+ 0x36, 0xD7, 0x36, 0xAD,
25475+
25476+ 0x2B, 0x80, 0x60, 0xEC,
25477+ 0x1D, 0x24, 0x60, 0xEC,
25478+
25479+ 0x3E, 0xD7, 0x3E, 0xAD,
25480+ 0x2C, 0x80, 0x60, 0xEC,
25481+
25482+ 0x1C, 0x2B, 0xDE, 0xE8,
25483+ 0x23, 0x80, 0xDE, 0xE8,
25484+
25485+ 0x36, 0x80, 0x36, 0xBD,
25486+ 0x3E, 0x80, 0x3E, 0xBD,
25487+
25488+ 0x33, 0xD7, 0x1C, 0xBD,
25489+ 0x3B, 0xD7, 0x23, 0xBD,
25490+
25491+ 0x46, 0x80, 0x46, 0xCF,
25492+ 0x4F, 0x80, 0x4F, 0xCF,
25493+
25494+ 0x56, 0x33, 0x56, 0xCF,
25495+ 0x47, 0x3B, 0x47, 0xCF,
25496+
25497+ 0xCD, 0xFF, 0x20, 0xEA,
25498+ 0x00, 0x80, 0x00, 0xE8,
25499+
25500+ 0x4E, 0x33, 0x4E, 0xCF,
25501+ 0x57, 0x3B, 0x57, 0xCF,
25502+
25503+ 0x94, 0xFF, 0x20, 0xEA,
25504+ 0x57, 0xC0, 0xBF, 0xEA,
25505+
25506+ 0x00, 0x80, 0xA0, 0xE9,
25507+ 0x00, 0x00, 0xD8, 0xEC,
25508+
25509+};
25510+
25511+static unsigned char warp_g400_tgzf[] = {
25512+
25513+ 0x00, 0x88, 0x98, 0xE9,
25514+ 0x00, 0x80, 0x00, 0xE8,
25515+
25516+ 0x00, 0x80, 0xA0, 0xE9,
25517+ 0x00, 0x00, 0xD8, 0xEC,
25518+
25519+ 0xFF, 0x80, 0xC0, 0xE9,
25520+ 0x00, 0x80, 0x00, 0xE8,
25521+
25522+ 0x22, 0x40, 0x48, 0xBF,
25523+ 0x2A, 0x40, 0x50, 0xBF,
25524+
25525+ 0x32, 0x41, 0x49, 0xBF,
25526+ 0x3A, 0x41, 0x51, 0xBF,
25527+
25528+ 0xC3, 0x6B,
25529+ 0xCB, 0x6B,
25530+ 0x00, 0x88, 0x98, 0xE9,
25531+
25532+ 0x73, 0x7B, 0xC8, 0xEC,
25533+ 0x96, 0xE2,
25534+ 0x41, 0x04,
25535+
25536+ 0x7B, 0x43, 0xA0, 0xE8,
25537+ 0x73, 0x4B, 0xA0, 0xE8,
25538+
25539+ 0xAD, 0xEE, 0x29, 0x9F,
25540+ 0x00, 0xE0,
25541+ 0x49, 0x04,
25542+
25543+ 0x90, 0xE2,
25544+ 0x51, 0x04,
25545+ 0x31, 0x46, 0xB1, 0xE8,
25546+
25547+ 0x49, 0x41, 0xC0, 0xEC,
25548+ 0x39, 0x57, 0xB1, 0xE8,
25549+
25550+ 0x00, 0x04,
25551+ 0x46, 0xE2,
25552+ 0x73, 0x53, 0xA0, 0xE8,
25553+
25554+ 0x51, 0x41, 0xC0, 0xEC,
25555+ 0x31, 0x00,
25556+ 0x39, 0x00,
25557+
25558+ 0x5D, 0x80, 0x15, 0xEA,
25559+ 0x08, 0x04,
25560+ 0x10, 0x04,
25561+
25562+ 0x51, 0x49, 0xC0, 0xEC,
25563+ 0x2F, 0x41, 0x60, 0xEA,
25564+
25565+ 0x31, 0x20,
25566+ 0x39, 0x20,
25567+ 0x1F, 0x42, 0xA0, 0xE8,
25568+
25569+ 0x2A, 0x42, 0x4A, 0xBF,
25570+ 0x27, 0x4A, 0xA0, 0xE8,
25571+
25572+ 0x1A, 0x42, 0x52, 0xBF,
25573+ 0x1E, 0x49, 0x60, 0xEA,
25574+
25575+ 0x73, 0x7B, 0xC8, 0xEC,
25576+ 0x26, 0x51, 0x60, 0xEA,
25577+
25578+ 0x32, 0x40, 0x48, 0xBD,
25579+ 0x22, 0x40, 0x50, 0xBD,
25580+
25581+ 0x12, 0x41, 0x49, 0xBD,
25582+ 0x3A, 0x41, 0x51, 0xBD,
25583+
25584+ 0xBF, 0x2F, 0x26, 0xBD,
25585+ 0x00, 0xE0,
25586+ 0x7B, 0x72,
25587+
25588+ 0x32, 0x20,
25589+ 0x22, 0x20,
25590+ 0x12, 0x20,
25591+ 0x3A, 0x20,
25592+
25593+ 0x46, 0x31, 0x46, 0xBF,
25594+ 0x4E, 0x31, 0x4E, 0xBF,
25595+
25596+ 0xB3, 0xE2, 0x2D, 0x9F,
25597+ 0x00, 0x80, 0x00, 0xE8,
25598+
25599+ 0x56, 0x31, 0x56, 0xBF,
25600+ 0x47, 0x39, 0x47, 0xBF,
25601+
25602+ 0x4F, 0x39, 0x4F, 0xBF,
25603+ 0x57, 0x39, 0x57, 0xBF,
25604+
25605+ 0x4F, 0x80, 0x07, 0xEA,
25606+ 0x24, 0x41, 0x20, 0xE9,
25607+
25608+ 0x42, 0x73, 0xF8, 0xEC,
25609+ 0x00, 0xE0,
25610+ 0x2D, 0x73,
25611+
25612+ 0x33, 0x72,
25613+ 0x0C, 0xE3,
25614+ 0xA5, 0x2F, 0x1E, 0xBD,
25615+
25616+ 0x43, 0x43, 0x2D, 0xDF,
25617+ 0x4B, 0x4B, 0x2D, 0xDF,
25618+
25619+ 0xAE, 0x1E, 0x26, 0xBD,
25620+ 0x58, 0xE3,
25621+ 0x33, 0x66,
25622+
25623+ 0x53, 0x53, 0x2D, 0xDF,
25624+ 0x00, 0x80, 0x00, 0xE8,
25625+
25626+ 0xB8, 0x38, 0x33, 0xBF,
25627+ 0x00, 0xE0,
25628+ 0x59, 0xE3,
25629+
25630+ 0x1E, 0x12, 0x41, 0xE9,
25631+ 0x1A, 0x22, 0x41, 0xE9,
25632+
25633+ 0x2B, 0x40, 0x3D, 0xE9,
25634+ 0x3F, 0x4B, 0xA0, 0xE8,
25635+
25636+ 0x2D, 0x73,
25637+ 0x30, 0x76,
25638+ 0x05, 0x80, 0x3D, 0xEA,
25639+
25640+ 0x37, 0x43, 0xA0, 0xE8,
25641+ 0x3D, 0x53, 0xA0, 0xE8,
25642+
25643+ 0x48, 0x70, 0xF8, 0xEC,
25644+ 0x2B, 0x48, 0x3C, 0xE9,
25645+
25646+ 0x1F, 0x27, 0xBC, 0xE8,
25647+ 0x00, 0x80, 0x00, 0xE8,
25648+
25649+ 0x00, 0x80, 0x00, 0xE8,
25650+ 0x00, 0x80, 0x00, 0xE8,
25651+
25652+ 0x15, 0xC0, 0x20, 0xE9,
25653+ 0x15, 0xC0, 0x20, 0xE9,
25654+
25655+ 0x15, 0xC0, 0x20, 0xE9,
25656+ 0x15, 0xC0, 0x20, 0xE9,
25657+
25658+ 0x18, 0x3A, 0x41, 0xE9,
25659+ 0x1D, 0x32, 0x41, 0xE9,
25660+
25661+ 0x2A, 0x40, 0x20, 0xE9,
25662+ 0x56, 0x3D, 0x56, 0xDF,
25663+
25664+ 0x46, 0x37, 0x46, 0xDF,
25665+ 0x4E, 0x3F, 0x4E, 0xDF,
25666+
25667+ 0x16, 0x30, 0x20, 0xE9,
25668+ 0x4F, 0x3F, 0x4F, 0xDF,
25669+
25670+ 0x32, 0x32, 0x2D, 0xDF,
25671+ 0x22, 0x22, 0x2D, 0xDF,
25672+
25673+ 0x12, 0x12, 0x2D, 0xDF,
25674+ 0x3A, 0x3A, 0x2D, 0xDF,
25675+
25676+ 0x47, 0x37, 0x47, 0xDF,
25677+ 0x57, 0x3D, 0x57, 0xDF,
25678+
25679+ 0x3D, 0xCF, 0x74, 0xC0,
25680+ 0x37, 0xCF, 0x74, 0xC4,
25681+
25682+ 0x39, 0xE5, 0x2C, 0x9F,
25683+ 0x34, 0x80, 0x20, 0xE9,
25684+
25685+ 0x31, 0x53, 0x2F, 0x9F,
25686+ 0x00, 0x80, 0x00, 0xE8,
25687+
25688+ 0x88, 0x73, 0x5E, 0xE9,
25689+ 0x00, 0x80, 0x00, 0xE8,
25690+
25691+ 0x27, 0xCF, 0x75, 0xC6,
25692+ 0x3C, 0x3D, 0x20, 0xE9,
25693+
25694+ 0x0A, 0x44, 0x4C, 0xB0,
25695+ 0x02, 0x44, 0x54, 0xB0,
25696+
25697+ 0x2A, 0x44, 0x4C, 0xB2,
25698+ 0x1A, 0x44, 0x54, 0xB2,
25699+
25700+ 0x20, 0x80, 0x3A, 0xEA,
25701+ 0x0A, 0x20,
25702+ 0x02, 0x20,
25703+
25704+ 0x3D, 0xCF, 0x74, 0xC2,
25705+ 0x2A, 0x20,
25706+ 0x1A, 0x20,
25707+
25708+ 0x30, 0x50, 0x2E, 0x9F,
25709+ 0x32, 0x31, 0x5F, 0xE9,
25710+
25711+ 0x38, 0x21, 0x2C, 0x9F,
25712+ 0x33, 0x39, 0x5F, 0xE9,
25713+
25714+ 0x31, 0x53, 0x2F, 0x9F,
25715+ 0x31, 0x27, 0x20, 0xE9,
25716+
25717+ 0x0A, 0x44, 0x4C, 0xB4,
25718+ 0x02, 0x44, 0x54, 0xB4,
25719+
25720+ 0x2A, 0x45, 0x4D, 0xB6,
25721+ 0x1A, 0x45, 0x55, 0xB6,
25722+
25723+ 0x39, 0xE5, 0x2C, 0x9F,
25724+ 0x38, 0x3D, 0x20, 0xE9,
25725+
25726+ 0x0A, 0x20,
25727+ 0x02, 0x20,
25728+ 0x2A, 0x20,
25729+ 0x1A, 0x20,
25730+
25731+ 0x0A, 0x47, 0x4F, 0xBF,
25732+ 0x02, 0x47, 0x57, 0xBF,
25733+
25734+ 0x30, 0x50, 0x2E, 0x9F,
25735+ 0x3E, 0x30, 0x4F, 0xE9,
25736+
25737+ 0x38, 0x21, 0x2C, 0x9F,
25738+ 0x3F, 0x38, 0x4F, 0xE9,
25739+
25740+ 0x2A, 0x46, 0x4E, 0xBF,
25741+ 0x1A, 0x46, 0x56, 0xBF,
25742+
25743+ 0x31, 0x53, 0x2F, 0x9F,
25744+ 0x3A, 0x31, 0x4F, 0xE9,
25745+
25746+ 0x39, 0xE5, 0x2C, 0x9F,
25747+ 0x3B, 0x39, 0x4F, 0xE9,
25748+
25749+ 0x31, 0x53, 0x2F, 0x9F,
25750+ 0x36, 0x30, 0x4F, 0xE9,
25751+
25752+ 0x39, 0xE5, 0x2C, 0x9F,
25753+ 0x37, 0x38, 0x4F, 0xE9,
25754+
25755+ 0x2A, 0x43, 0x4B, 0xBF,
25756+ 0x1A, 0x43, 0x53, 0xBF,
25757+
25758+ 0x30, 0x50, 0x2E, 0x9F,
25759+ 0x35, 0x31, 0x4F, 0xE9,
25760+
25761+ 0x38, 0x21, 0x2C, 0x9F,
25762+ 0x39, 0x39, 0x4F, 0xE9,
25763+
25764+ 0x31, 0x53, 0x2F, 0x9F,
25765+ 0x80, 0x31, 0x57, 0xE9,
25766+
25767+ 0x39, 0xE5, 0x2C, 0x9F,
25768+ 0x81, 0x39, 0x57, 0xE9,
25769+
25770+ 0x37, 0x48, 0x50, 0xBD,
25771+ 0x8A, 0x36, 0x20, 0xE9,
25772+
25773+ 0x86, 0x76, 0x57, 0xE9,
25774+ 0x8B, 0x3E, 0x20, 0xE9,
25775+
25776+ 0x82, 0x30, 0x57, 0xE9,
25777+ 0x87, 0x77, 0x57, 0xE9,
25778+
25779+ 0x83, 0x38, 0x57, 0xE9,
25780+ 0x35, 0x49, 0x51, 0xBD,
25781+
25782+ 0x84, 0x31, 0x5E, 0xE9,
25783+ 0x30, 0x1F, 0x5F, 0xE9,
25784+
25785+ 0x85, 0x39, 0x5E, 0xE9,
25786+ 0x57, 0x25, 0x20, 0xE9,
25787+
25788+ 0x2B, 0x48, 0x20, 0xE9,
25789+ 0x1D, 0x37, 0xE1, 0xEA,
25790+
25791+ 0x1E, 0x35, 0xE1, 0xEA,
25792+ 0x00, 0xE0,
25793+ 0x26, 0x77,
25794+
25795+ 0x24, 0x49, 0x20, 0xE9,
25796+ 0xAA, 0xFF, 0x20, 0xEA,
25797+
25798+ 0x16, 0x26, 0x20, 0xE9,
25799+ 0x57, 0x2E, 0xBF, 0xEA,
25800+
25801+ 0x1C, 0x46, 0xA0, 0xE8,
25802+ 0x23, 0x4E, 0xA0, 0xE8,
25803+
25804+ 0x2B, 0x56, 0xA0, 0xE8,
25805+ 0x1D, 0x47, 0xA0, 0xE8,
25806+
25807+ 0x24, 0x4F, 0xA0, 0xE8,
25808+ 0x2C, 0x57, 0xA0, 0xE8,
25809+
25810+ 0x1C, 0x00,
25811+ 0x23, 0x00,
25812+ 0x2B, 0x00,
25813+ 0x00, 0xE0,
25814+
25815+ 0x1D, 0x00,
25816+ 0x24, 0x00,
25817+ 0x2C, 0x00,
25818+ 0x00, 0xE0,
25819+
25820+ 0x1C, 0x65,
25821+ 0x23, 0x65,
25822+ 0x2B, 0x65,
25823+ 0x00, 0xE0,
25824+
25825+ 0x1D, 0x65,
25826+ 0x24, 0x65,
25827+ 0x2C, 0x65,
25828+ 0x00, 0xE0,
25829+
25830+ 0x1C, 0x23, 0x60, 0xEC,
25831+ 0x36, 0xD7, 0x36, 0xAD,
25832+
25833+ 0x2B, 0x80, 0x60, 0xEC,
25834+ 0x1D, 0x24, 0x60, 0xEC,
25835+
25836+ 0x3E, 0xD7, 0x3E, 0xAD,
25837+ 0x2C, 0x80, 0x60, 0xEC,
25838+
25839+ 0x1C, 0x2B, 0xDE, 0xE8,
25840+ 0x23, 0x80, 0xDE, 0xE8,
25841+
25842+ 0x36, 0x80, 0x36, 0xBD,
25843+ 0x3E, 0x80, 0x3E, 0xBD,
25844+
25845+ 0x33, 0xD7, 0x1C, 0xBD,
25846+ 0x3B, 0xD7, 0x23, 0xBD,
25847+
25848+ 0x46, 0x80, 0x46, 0xCF,
25849+ 0x4F, 0x80, 0x4F, 0xCF,
25850+
25851+ 0x56, 0x33, 0x56, 0xCF,
25852+ 0x47, 0x3B, 0x47, 0xCF,
25853+
25854+ 0xD3, 0xFF, 0x20, 0xEA,
25855+ 0x00, 0x80, 0x00, 0xE8,
25856+
25857+ 0x4E, 0x33, 0x4E, 0xCF,
25858+ 0x57, 0x3B, 0x57, 0xCF,
25859+
25860+ 0x98, 0xFF, 0x20, 0xEA,
25861+ 0x57, 0xC0, 0xBF, 0xEA,
25862+
25863+ 0x00, 0x80, 0xA0, 0xE9,
25864+ 0x00, 0x00, 0xD8, 0xEC,
25865+
25866+};
25867+
25868+static unsigned char warp_g400_tgzs[] = {
25869+
25870+ 0x00, 0x88, 0x98, 0xE9,
25871+ 0x00, 0x80, 0x00, 0xE8,
25872+
25873+ 0x00, 0x80, 0xA0, 0xE9,
25874+ 0x00, 0x00, 0xD8, 0xEC,
25875+
25876+ 0xFF, 0x80, 0xC0, 0xE9,
25877+ 0x00, 0x80, 0x00, 0xE8,
25878+
25879+ 0x22, 0x40, 0x48, 0xBF,
25880+ 0x2A, 0x40, 0x50, 0xBF,
25881+
25882+ 0x32, 0x41, 0x49, 0xBF,
25883+ 0x3A, 0x41, 0x51, 0xBF,
25884+
25885+ 0xC3, 0x6B,
25886+ 0xCB, 0x6B,
25887+ 0x00, 0x88, 0x98, 0xE9,
25888+
25889+ 0x73, 0x7B, 0xC8, 0xEC,
25890+ 0x96, 0xE2,
25891+ 0x41, 0x04,
25892+
25893+ 0x7B, 0x43, 0xA0, 0xE8,
25894+ 0x73, 0x4B, 0xA0, 0xE8,
25895+
25896+ 0xAD, 0xEE, 0x29, 0x9F,
25897+ 0x00, 0xE0,
25898+ 0x49, 0x04,
25899+
25900+ 0x90, 0xE2,
25901+ 0x51, 0x04,
25902+ 0x31, 0x46, 0xB1, 0xE8,
25903+
25904+ 0x49, 0x41, 0xC0, 0xEC,
25905+ 0x39, 0x57, 0xB1, 0xE8,
25906+
25907+ 0x00, 0x04,
25908+ 0x46, 0xE2,
25909+ 0x73, 0x53, 0xA0, 0xE8,
25910+
25911+ 0x51, 0x41, 0xC0, 0xEC,
25912+ 0x31, 0x00,
25913+ 0x39, 0x00,
25914+
25915+ 0x65, 0x80, 0x15, 0xEA,
25916+ 0x08, 0x04,
25917+ 0x10, 0x04,
25918+
25919+ 0x51, 0x49, 0xC0, 0xEC,
25920+ 0x2F, 0x41, 0x60, 0xEA,
25921+
25922+ 0x31, 0x20,
25923+ 0x39, 0x20,
25924+ 0x1F, 0x42, 0xA0, 0xE8,
25925+
25926+ 0x2A, 0x42, 0x4A, 0xBF,
25927+ 0x27, 0x4A, 0xA0, 0xE8,
25928+
25929+ 0x1A, 0x42, 0x52, 0xBF,
25930+ 0x1E, 0x49, 0x60, 0xEA,
25931+
25932+ 0x73, 0x7B, 0xC8, 0xEC,
25933+ 0x26, 0x51, 0x60, 0xEA,
25934+
25935+ 0x32, 0x40, 0x48, 0xBD,
25936+ 0x22, 0x40, 0x50, 0xBD,
25937+
25938+ 0x12, 0x41, 0x49, 0xBD,
25939+ 0x3A, 0x41, 0x51, 0xBD,
25940+
25941+ 0xBF, 0x2F, 0x26, 0xBD,
25942+ 0x00, 0xE0,
25943+ 0x7B, 0x72,
25944+
25945+ 0x32, 0x20,
25946+ 0x22, 0x20,
25947+ 0x12, 0x20,
25948+ 0x3A, 0x20,
25949+
25950+ 0x46, 0x31, 0x46, 0xBF,
25951+ 0x4E, 0x31, 0x4E, 0xBF,
25952+
25953+ 0xB3, 0xE2, 0x2D, 0x9F,
25954+ 0x00, 0x80, 0x00, 0xE8,
25955+
25956+ 0x56, 0x31, 0x56, 0xBF,
25957+ 0x47, 0x39, 0x47, 0xBF,
25958+
25959+ 0x4F, 0x39, 0x4F, 0xBF,
25960+ 0x57, 0x39, 0x57, 0xBF,
25961+
25962+ 0x57, 0x80, 0x07, 0xEA,
25963+ 0x24, 0x41, 0x20, 0xE9,
25964+
25965+ 0x42, 0x73, 0xF8, 0xEC,
25966+ 0x00, 0xE0,
25967+ 0x2D, 0x73,
25968+
25969+ 0x33, 0x72,
25970+ 0x0C, 0xE3,
25971+ 0xA5, 0x2F, 0x1E, 0xBD,
25972+
25973+ 0x43, 0x43, 0x2D, 0xDF,
25974+ 0x4B, 0x4B, 0x2D, 0xDF,
25975+
25976+ 0xAE, 0x1E, 0x26, 0xBD,
25977+ 0x58, 0xE3,
25978+ 0x33, 0x66,
25979+
25980+ 0x53, 0x53, 0x2D, 0xDF,
25981+ 0x00, 0x80, 0x00, 0xE8,
25982+
25983+ 0xB8, 0x38, 0x33, 0xBF,
25984+ 0x00, 0xE0,
25985+ 0x59, 0xE3,
25986+
25987+ 0x1E, 0x12, 0x41, 0xE9,
25988+ 0x1A, 0x22, 0x41, 0xE9,
25989+
25990+ 0x2B, 0x40, 0x3D, 0xE9,
25991+ 0x3F, 0x4B, 0xA0, 0xE8,
25992+
25993+ 0x2D, 0x73,
25994+ 0x30, 0x76,
25995+ 0x05, 0x80, 0x3D, 0xEA,
25996+
25997+ 0x37, 0x43, 0xA0, 0xE8,
25998+ 0x3D, 0x53, 0xA0, 0xE8,
25999+
26000+ 0x48, 0x70, 0xF8, 0xEC,
26001+ 0x2B, 0x48, 0x3C, 0xE9,
26002+
26003+ 0x1F, 0x27, 0xBC, 0xE8,
26004+ 0x00, 0x80, 0x00, 0xE8,
26005+
26006+ 0x00, 0x80, 0x00, 0xE8,
26007+ 0x00, 0x80, 0x00, 0xE8,
26008+
26009+ 0x15, 0xC0, 0x20, 0xE9,
26010+ 0x15, 0xC0, 0x20, 0xE9,
26011+
26012+ 0x15, 0xC0, 0x20, 0xE9,
26013+ 0x15, 0xC0, 0x20, 0xE9,
26014+
26015+ 0x18, 0x3A, 0x41, 0xE9,
26016+ 0x1D, 0x32, 0x41, 0xE9,
26017+
26018+ 0x2A, 0x40, 0x20, 0xE9,
26019+ 0x56, 0x3D, 0x56, 0xDF,
26020+
26021+ 0x46, 0x37, 0x46, 0xDF,
26022+ 0x4E, 0x3F, 0x4E, 0xDF,
26023+
26024+ 0x16, 0x30, 0x20, 0xE9,
26025+ 0x4F, 0x3F, 0x4F, 0xDF,
26026+
26027+ 0x47, 0x37, 0x47, 0xDF,
26028+ 0x57, 0x3D, 0x57, 0xDF,
26029+
26030+ 0x32, 0x32, 0x2D, 0xDF,
26031+ 0x22, 0x22, 0x2D, 0xDF,
26032+
26033+ 0x12, 0x12, 0x2D, 0xDF,
26034+ 0x3A, 0x3A, 0x2D, 0xDF,
26035+
26036+ 0x27, 0xCF, 0x74, 0xC2,
26037+ 0x37, 0xCF, 0x74, 0xC4,
26038+
26039+ 0x0A, 0x44, 0x4C, 0xB0,
26040+ 0x02, 0x44, 0x54, 0xB0,
26041+
26042+ 0x3D, 0xCF, 0x74, 0xC0,
26043+ 0x34, 0x37, 0x20, 0xE9,
26044+
26045+ 0x31, 0x53, 0x2F, 0x9F,
26046+ 0x38, 0x27, 0x20, 0xE9,
26047+
26048+ 0x39, 0xE5, 0x2C, 0x9F,
26049+ 0x3C, 0x3D, 0x20, 0xE9,
26050+
26051+ 0x2A, 0x44, 0x4C, 0xB2,
26052+ 0x1A, 0x44, 0x54, 0xB2,
26053+
26054+ 0x29, 0x80, 0x3A, 0xEA,
26055+ 0x0A, 0x20,
26056+ 0x02, 0x20,
26057+
26058+ 0x27, 0xCF, 0x75, 0xC0,
26059+ 0x2A, 0x20,
26060+ 0x1A, 0x20,
26061+
26062+ 0x30, 0x50, 0x2E, 0x9F,
26063+ 0x32, 0x31, 0x5F, 0xE9,
26064+
26065+ 0x38, 0x21, 0x2C, 0x9F,
26066+ 0x33, 0x39, 0x5F, 0xE9,
26067+
26068+ 0x3D, 0xCF, 0x75, 0xC2,
26069+ 0x37, 0xCF, 0x75, 0xC4,
26070+
26071+ 0x31, 0x53, 0x2F, 0x9F,
26072+ 0xA6, 0x27, 0x20, 0xE9,
26073+
26074+ 0x39, 0xE5, 0x2C, 0x9F,
26075+ 0xA3, 0x3D, 0x20, 0xE9,
26076+
26077+ 0x2A, 0x44, 0x4C, 0xB4,
26078+ 0x1A, 0x44, 0x54, 0xB4,
26079+
26080+ 0x0A, 0x45, 0x4D, 0xB0,
26081+ 0x02, 0x45, 0x55, 0xB0,
26082+
26083+ 0x88, 0x73, 0x5E, 0xE9,
26084+ 0x2A, 0x20,
26085+ 0x1A, 0x20,
26086+
26087+ 0xA0, 0x37, 0x20, 0xE9,
26088+ 0x0A, 0x20,
26089+ 0x02, 0x20,
26090+
26091+ 0x31, 0x53, 0x2F, 0x9F,
26092+ 0x3E, 0x30, 0x4F, 0xE9,
26093+
26094+ 0x39, 0xE5, 0x2C, 0x9F,
26095+ 0x3F, 0x38, 0x4F, 0xE9,
26096+
26097+ 0x30, 0x50, 0x2E, 0x9F,
26098+ 0x3A, 0x31, 0x4F, 0xE9,
26099+
26100+ 0x2A, 0x45, 0x4D, 0xB2,
26101+ 0x1A, 0x45, 0x55, 0xB2,
26102+
26103+ 0x0A, 0x45, 0x4D, 0xB4,
26104+ 0x02, 0x45, 0x55, 0xB4,
26105+
26106+ 0x38, 0x21, 0x2C, 0x9F,
26107+ 0x3B, 0x39, 0x4F, 0xE9,
26108+
26109+ 0x0A, 0x20,
26110+ 0x02, 0x20,
26111+ 0x2A, 0x20,
26112+ 0x1A, 0x20,
26113+
26114+ 0x2A, 0x46, 0x4E, 0xBF,
26115+ 0x1A, 0x46, 0x56, 0xBF,
26116+
26117+ 0x31, 0x53, 0x2F, 0x9F,
26118+ 0x36, 0x31, 0x4F, 0xE9,
26119+
26120+ 0x39, 0xE5, 0x2C, 0x9F,
26121+ 0x37, 0x39, 0x4F, 0xE9,
26122+
26123+ 0x30, 0x50, 0x2E, 0x9F,
26124+ 0xA7, 0x30, 0x4F, 0xE9,
26125+
26126+ 0x38, 0x21, 0x2C, 0x9F,
26127+ 0xA8, 0x38, 0x4F, 0xE9,
26128+
26129+ 0x0A, 0x47, 0x4F, 0xBF,
26130+ 0x02, 0x47, 0x57, 0xBF,
26131+
26132+ 0x31, 0x53, 0x2F, 0x9F,
26133+ 0xA4, 0x31, 0x4F, 0xE9,
26134+
26135+ 0x39, 0xE5, 0x2C, 0x9F,
26136+ 0xA5, 0x39, 0x4F, 0xE9,
26137+
26138+ 0x2A, 0x43, 0x4B, 0xBF,
26139+ 0x1A, 0x43, 0x53, 0xBF,
26140+
26141+ 0x30, 0x50, 0x2E, 0x9F,
26142+ 0xA1, 0x30, 0x4F, 0xE9,
26143+
26144+ 0x38, 0x21, 0x2C, 0x9F,
26145+ 0xA2, 0x38, 0x4F, 0xE9,
26146+
26147+ 0x31, 0x53, 0x2F, 0x9F,
26148+ 0x80, 0x31, 0x57, 0xE9,
26149+
26150+ 0x39, 0xE5, 0x2C, 0x9F,
26151+ 0x81, 0x39, 0x57, 0xE9,
26152+
26153+ 0x37, 0x48, 0x50, 0xBD,
26154+ 0x8A, 0x36, 0x20, 0xE9,
26155+
26156+ 0x86, 0x76, 0x57, 0xE9,
26157+ 0x8B, 0x3E, 0x20, 0xE9,
26158+
26159+ 0x82, 0x30, 0x57, 0xE9,
26160+ 0x87, 0x77, 0x57, 0xE9,
26161+
26162+ 0x83, 0x38, 0x57, 0xE9,
26163+ 0x35, 0x49, 0x51, 0xBD,
26164+
26165+ 0x84, 0x31, 0x5E, 0xE9,
26166+ 0x30, 0x1F, 0x5F, 0xE9,
26167+
26168+ 0x85, 0x39, 0x5E, 0xE9,
26169+ 0x57, 0x25, 0x20, 0xE9,
26170+
26171+ 0x2B, 0x48, 0x20, 0xE9,
26172+ 0x1D, 0x37, 0xE1, 0xEA,
26173+
26174+ 0x1E, 0x35, 0xE1, 0xEA,
26175+ 0x00, 0xE0,
26176+ 0x26, 0x77,
26177+
26178+ 0x24, 0x49, 0x20, 0xE9,
26179+ 0xA2, 0xFF, 0x20, 0xEA,
26180+
26181+ 0x16, 0x26, 0x20, 0xE9,
26182+ 0x57, 0x2E, 0xBF, 0xEA,
26183+
26184+ 0x1C, 0x46, 0xA0, 0xE8,
26185+ 0x23, 0x4E, 0xA0, 0xE8,
26186+
26187+ 0x2B, 0x56, 0xA0, 0xE8,
26188+ 0x1D, 0x47, 0xA0, 0xE8,
26189+
26190+ 0x24, 0x4F, 0xA0, 0xE8,
26191+ 0x2C, 0x57, 0xA0, 0xE8,
26192+
26193+ 0x1C, 0x00,
26194+ 0x23, 0x00,
26195+ 0x2B, 0x00,
26196+ 0x00, 0xE0,
26197+
26198+ 0x1D, 0x00,
26199+ 0x24, 0x00,
26200+ 0x2C, 0x00,
26201+ 0x00, 0xE0,
26202+
26203+ 0x1C, 0x65,
26204+ 0x23, 0x65,
26205+ 0x2B, 0x65,
26206+ 0x00, 0xE0,
26207+
26208+ 0x1D, 0x65,
26209+ 0x24, 0x65,
26210+ 0x2C, 0x65,
26211+ 0x00, 0xE0,
26212+
26213+ 0x1C, 0x23, 0x60, 0xEC,
26214+ 0x36, 0xD7, 0x36, 0xAD,
26215+
26216+ 0x2B, 0x80, 0x60, 0xEC,
26217+ 0x1D, 0x24, 0x60, 0xEC,
26218+
26219+ 0x3E, 0xD7, 0x3E, 0xAD,
26220+ 0x2C, 0x80, 0x60, 0xEC,
26221+
26222+ 0x1C, 0x2B, 0xDE, 0xE8,
26223+ 0x23, 0x80, 0xDE, 0xE8,
26224+
26225+ 0x36, 0x80, 0x36, 0xBD,
26226+ 0x3E, 0x80, 0x3E, 0xBD,
26227+
26228+ 0x33, 0xD7, 0x1C, 0xBD,
26229+ 0x3B, 0xD7, 0x23, 0xBD,
26230+
26231+ 0x46, 0x80, 0x46, 0xCF,
26232+ 0x4F, 0x80, 0x4F, 0xCF,
26233+
26234+ 0x56, 0x33, 0x56, 0xCF,
26235+ 0x47, 0x3B, 0x47, 0xCF,
26236+
26237+ 0xCA, 0xFF, 0x20, 0xEA,
26238+ 0x00, 0x80, 0x00, 0xE8,
26239+
26240+ 0x4E, 0x33, 0x4E, 0xCF,
26241+ 0x57, 0x3B, 0x57, 0xCF,
26242+
26243+ 0x90, 0xFF, 0x20, 0xEA,
26244+ 0x57, 0xC0, 0xBF, 0xEA,
26245+
26246+ 0x00, 0x80, 0xA0, 0xE9,
26247+ 0x00, 0x00, 0xD8, 0xEC,
26248+
26249+};
26250+
26251+static unsigned char warp_g400_tgzsa[] = {
26252+
26253+ 0x00, 0x88, 0x98, 0xE9,
26254+ 0x00, 0x80, 0x00, 0xE8,
26255+
26256+ 0x00, 0x80, 0xA0, 0xE9,
26257+ 0x00, 0x00, 0xD8, 0xEC,
26258+
26259+ 0xFF, 0x80, 0xC0, 0xE9,
26260+ 0x00, 0x80, 0x00, 0xE8,
26261+
26262+ 0x22, 0x40, 0x48, 0xBF,
26263+ 0x2A, 0x40, 0x50, 0xBF,
26264+
26265+ 0x32, 0x41, 0x49, 0xBF,
26266+ 0x3A, 0x41, 0x51, 0xBF,
26267+
26268+ 0xC3, 0x6B,
26269+ 0xCB, 0x6B,
26270+ 0x00, 0x88, 0x98, 0xE9,
26271+
26272+ 0x73, 0x7B, 0xC8, 0xEC,
26273+ 0x96, 0xE2,
26274+ 0x41, 0x04,
26275+
26276+ 0x7B, 0x43, 0xA0, 0xE8,
26277+ 0x73, 0x4B, 0xA0, 0xE8,
26278+
26279+ 0xAD, 0xEE, 0x29, 0x9F,
26280+ 0x00, 0xE0,
26281+ 0x49, 0x04,
26282+
26283+ 0x90, 0xE2,
26284+ 0x51, 0x04,
26285+ 0x31, 0x46, 0xB1, 0xE8,
26286+
26287+ 0x49, 0x41, 0xC0, 0xEC,
26288+ 0x39, 0x57, 0xB1, 0xE8,
26289+
26290+ 0x00, 0x04,
26291+ 0x46, 0xE2,
26292+ 0x73, 0x53, 0xA0, 0xE8,
26293+
26294+ 0x51, 0x41, 0xC0, 0xEC,
26295+ 0x31, 0x00,
26296+ 0x39, 0x00,
26297+
26298+ 0x6A, 0x80, 0x15, 0xEA,
26299+ 0x08, 0x04,
26300+ 0x10, 0x04,
26301+
26302+ 0x51, 0x49, 0xC0, 0xEC,
26303+ 0x2F, 0x41, 0x60, 0xEA,
26304+
26305+ 0x31, 0x20,
26306+ 0x39, 0x20,
26307+ 0x1F, 0x42, 0xA0, 0xE8,
26308+
26309+ 0x2A, 0x42, 0x4A, 0xBF,
26310+ 0x27, 0x4A, 0xA0, 0xE8,
26311+
26312+ 0x1A, 0x42, 0x52, 0xBF,
26313+ 0x1E, 0x49, 0x60, 0xEA,
26314+
26315+ 0x73, 0x7B, 0xC8, 0xEC,
26316+ 0x26, 0x51, 0x60, 0xEA,
26317+
26318+ 0x32, 0x40, 0x48, 0xBD,
26319+ 0x22, 0x40, 0x50, 0xBD,
26320+
26321+ 0x12, 0x41, 0x49, 0xBD,
26322+ 0x3A, 0x41, 0x51, 0xBD,
26323+
26324+ 0xBF, 0x2F, 0x26, 0xBD,
26325+ 0x00, 0xE0,
26326+ 0x7B, 0x72,
26327+
26328+ 0x32, 0x20,
26329+ 0x22, 0x20,
26330+ 0x12, 0x20,
26331+ 0x3A, 0x20,
26332+
26333+ 0x46, 0x31, 0x46, 0xBF,
26334+ 0x4E, 0x31, 0x4E, 0xBF,
26335+
26336+ 0xB3, 0xE2, 0x2D, 0x9F,
26337+ 0x00, 0x80, 0x00, 0xE8,
26338+
26339+ 0x56, 0x31, 0x56, 0xBF,
26340+ 0x47, 0x39, 0x47, 0xBF,
26341+
26342+ 0x4F, 0x39, 0x4F, 0xBF,
26343+ 0x57, 0x39, 0x57, 0xBF,
26344+
26345+ 0x5C, 0x80, 0x07, 0xEA,
26346+ 0x24, 0x41, 0x20, 0xE9,
26347+
26348+ 0x42, 0x73, 0xF8, 0xEC,
26349+ 0x00, 0xE0,
26350+ 0x2D, 0x73,
26351+
26352+ 0x33, 0x72,
26353+ 0x0C, 0xE3,
26354+ 0xA5, 0x2F, 0x1E, 0xBD,
26355+
26356+ 0x43, 0x43, 0x2D, 0xDF,
26357+ 0x4B, 0x4B, 0x2D, 0xDF,
26358+
26359+ 0xAE, 0x1E, 0x26, 0xBD,
26360+ 0x58, 0xE3,
26361+ 0x33, 0x66,
26362+
26363+ 0x53, 0x53, 0x2D, 0xDF,
26364+ 0x00, 0x80, 0x00, 0xE8,
26365+
26366+ 0xB8, 0x38, 0x33, 0xBF,
26367+ 0x00, 0xE0,
26368+ 0x59, 0xE3,
26369+
26370+ 0x1E, 0x12, 0x41, 0xE9,
26371+ 0x1A, 0x22, 0x41, 0xE9,
26372+
26373+ 0x2B, 0x40, 0x3D, 0xE9,
26374+ 0x3F, 0x4B, 0xA0, 0xE8,
26375+
26376+ 0x2D, 0x73,
26377+ 0x30, 0x76,
26378+ 0x05, 0x80, 0x3D, 0xEA,
26379+
26380+ 0x37, 0x43, 0xA0, 0xE8,
26381+ 0x3D, 0x53, 0xA0, 0xE8,
26382+
26383+ 0x48, 0x70, 0xF8, 0xEC,
26384+ 0x2B, 0x48, 0x3C, 0xE9,
26385+
26386+ 0x1F, 0x27, 0xBC, 0xE8,
26387+ 0x00, 0x80, 0x00, 0xE8,
26388+
26389+ 0x00, 0x80, 0x00, 0xE8,
26390+ 0x00, 0x80, 0x00, 0xE8,
26391+
26392+ 0x15, 0xC0, 0x20, 0xE9,
26393+ 0x15, 0xC0, 0x20, 0xE9,
26394+
26395+ 0x15, 0xC0, 0x20, 0xE9,
26396+ 0x15, 0xC0, 0x20, 0xE9,
26397+
26398+ 0x18, 0x3A, 0x41, 0xE9,
26399+ 0x1D, 0x32, 0x41, 0xE9,
26400+
26401+ 0x2A, 0x40, 0x20, 0xE9,
26402+ 0x56, 0x3D, 0x56, 0xDF,
26403+
26404+ 0x46, 0x37, 0x46, 0xDF,
26405+ 0x4E, 0x3F, 0x4E, 0xDF,
26406+
26407+ 0x16, 0x30, 0x20, 0xE9,
26408+ 0x4F, 0x3F, 0x4F, 0xDF,
26409+
26410+ 0x47, 0x37, 0x47, 0xDF,
26411+ 0x57, 0x3D, 0x57, 0xDF,
26412+
26413+ 0x32, 0x32, 0x2D, 0xDF,
26414+ 0x22, 0x22, 0x2D, 0xDF,
26415+
26416+ 0x12, 0x12, 0x2D, 0xDF,
26417+ 0x3A, 0x3A, 0x2D, 0xDF,
26418+
26419+ 0x27, 0xCF, 0x74, 0xC2,
26420+ 0x37, 0xCF, 0x74, 0xC4,
26421+
26422+ 0x0A, 0x44, 0x4C, 0xB0,
26423+ 0x02, 0x44, 0x54, 0xB0,
26424+
26425+ 0x3D, 0xCF, 0x74, 0xC0,
26426+ 0x34, 0x37, 0x20, 0xE9,
26427+
26428+ 0x31, 0x53, 0x2F, 0x9F,
26429+ 0x38, 0x27, 0x20, 0xE9,
26430+
26431+ 0x39, 0xE5, 0x2C, 0x9F,
26432+ 0x3C, 0x3D, 0x20, 0xE9,
26433+
26434+ 0x2A, 0x44, 0x4C, 0xB2,
26435+ 0x1A, 0x44, 0x54, 0xB2,
26436+
26437+ 0x2E, 0x80, 0x3A, 0xEA,
26438+ 0x0A, 0x20,
26439+ 0x02, 0x20,
26440+
26441+ 0x27, 0xCF, 0x75, 0xC0,
26442+ 0x2A, 0x20,
26443+ 0x1A, 0x20,
26444+
26445+ 0x30, 0x50, 0x2E, 0x9F,
26446+ 0x32, 0x31, 0x5F, 0xE9,
26447+
26448+ 0x38, 0x21, 0x2C, 0x9F,
26449+ 0x33, 0x39, 0x5F, 0xE9,
26450+
26451+ 0x3D, 0xCF, 0x75, 0xC2,
26452+ 0x37, 0xCF, 0x75, 0xC4,
26453+
26454+ 0x31, 0x53, 0x2F, 0x9F,
26455+ 0xA6, 0x27, 0x20, 0xE9,
26456+
26457+ 0x39, 0xE5, 0x2C, 0x9F,
26458+ 0xA3, 0x3D, 0x20, 0xE9,
26459+
26460+ 0x2A, 0x44, 0x4C, 0xB4,
26461+ 0x1A, 0x44, 0x54, 0xB4,
26462+
26463+ 0x0A, 0x45, 0x4D, 0xB0,
26464+ 0x02, 0x45, 0x55, 0xB0,
26465+
26466+ 0x88, 0x73, 0x5E, 0xE9,
26467+ 0x2A, 0x20,
26468+ 0x1A, 0x20,
26469+
26470+ 0xA0, 0x37, 0x20, 0xE9,
26471+ 0x0A, 0x20,
26472+ 0x02, 0x20,
26473+
26474+ 0x31, 0x53, 0x2F, 0x9F,
26475+ 0x3E, 0x30, 0x4F, 0xE9,
26476+
26477+ 0x39, 0xE5, 0x2C, 0x9F,
26478+ 0x3F, 0x38, 0x4F, 0xE9,
26479+
26480+ 0x30, 0x50, 0x2E, 0x9F,
26481+ 0x3A, 0x31, 0x4F, 0xE9,
26482+
26483+ 0x38, 0x21, 0x2C, 0x9F,
26484+ 0x3B, 0x39, 0x4F, 0xE9,
26485+
26486+ 0x2A, 0x45, 0x4D, 0xB2,
26487+ 0x1A, 0x45, 0x55, 0xB2,
26488+
26489+ 0x0A, 0x45, 0x4D, 0xB4,
26490+ 0x02, 0x45, 0x55, 0xB4,
26491+
26492+ 0x27, 0xCF, 0x74, 0xC6,
26493+ 0x2A, 0x20,
26494+ 0x1A, 0x20,
26495+
26496+ 0xA7, 0x30, 0x4F, 0xE9,
26497+ 0x0A, 0x20,
26498+ 0x02, 0x20,
26499+
26500+ 0x31, 0x53, 0x2F, 0x9F,
26501+ 0x9C, 0x27, 0x20, 0xE9,
26502+
26503+ 0x39, 0xE5, 0x2C, 0x9F,
26504+ 0xA8, 0x38, 0x4F, 0xE9,
26505+
26506+ 0x2A, 0x44, 0x4C, 0xB6,
26507+ 0x1A, 0x44, 0x54, 0xB6,
26508+
26509+ 0x30, 0x50, 0x2E, 0x9F,
26510+ 0x36, 0x31, 0x4F, 0xE9,
26511+
26512+ 0x38, 0x21, 0x2C, 0x9F,
26513+ 0x37, 0x39, 0x4F, 0xE9,
26514+
26515+ 0x00, 0x80, 0x00, 0xE8,
26516+ 0x2A, 0x20,
26517+ 0x1A, 0x20,
26518+
26519+ 0x2A, 0x46, 0x4E, 0xBF,
26520+ 0x1A, 0x46, 0x56, 0xBF,
26521+
26522+ 0x31, 0x53, 0x2F, 0x9F,
26523+ 0xA4, 0x31, 0x4F, 0xE9,
26524+
26525+ 0x39, 0xE5, 0x2C, 0x9F,
26526+ 0xA5, 0x39, 0x4F, 0xE9,
26527+
26528+ 0x0A, 0x47, 0x4F, 0xBF,
26529+ 0x02, 0x47, 0x57, 0xBF,
26530+
26531+ 0x31, 0x53, 0x2F, 0x9F,
26532+ 0xA1, 0x30, 0x4F, 0xE9,
26533+
26534+ 0x39, 0xE5, 0x2C, 0x9F,
26535+ 0xA2, 0x38, 0x4F, 0xE9,
26536+
26537+ 0x2A, 0x43, 0x4B, 0xBF,
26538+ 0x1A, 0x43, 0x53, 0xBF,
26539+
26540+ 0x30, 0x50, 0x2E, 0x9F,
26541+ 0x9D, 0x31, 0x4F, 0xE9,
26542+
26543+ 0x38, 0x21, 0x2C, 0x9F,
26544+ 0x9E, 0x39, 0x4F, 0xE9,
26545+
26546+ 0x31, 0x53, 0x2F, 0x9F,
26547+ 0x80, 0x31, 0x57, 0xE9,
26548+
26549+ 0x39, 0xE5, 0x2C, 0x9F,
26550+ 0x81, 0x39, 0x57, 0xE9,
26551+
26552+ 0x37, 0x48, 0x50, 0xBD,
26553+ 0x8A, 0x36, 0x20, 0xE9,
26554+
26555+ 0x86, 0x76, 0x57, 0xE9,
26556+ 0x8B, 0x3E, 0x20, 0xE9,
26557+
26558+ 0x82, 0x30, 0x57, 0xE9,
26559+ 0x87, 0x77, 0x57, 0xE9,
26560+
26561+ 0x83, 0x38, 0x57, 0xE9,
26562+ 0x35, 0x49, 0x51, 0xBD,
26563+
26564+ 0x84, 0x31, 0x5E, 0xE9,
26565+ 0x30, 0x1F, 0x5F, 0xE9,
26566+
26567+ 0x85, 0x39, 0x5E, 0xE9,
26568+ 0x57, 0x25, 0x20, 0xE9,
26569+
26570+ 0x2B, 0x48, 0x20, 0xE9,
26571+ 0x1D, 0x37, 0xE1, 0xEA,
26572+
26573+ 0x1E, 0x35, 0xE1, 0xEA,
26574+ 0x00, 0xE0,
26575+ 0x26, 0x77,
26576+
26577+ 0x24, 0x49, 0x20, 0xE9,
26578+ 0x9D, 0xFF, 0x20, 0xEA,
26579+
26580+ 0x16, 0x26, 0x20, 0xE9,
26581+ 0x57, 0x2E, 0xBF, 0xEA,
26582+
26583+ 0x1C, 0x46, 0xA0, 0xE8,
26584+ 0x23, 0x4E, 0xA0, 0xE8,
26585+
26586+ 0x2B, 0x56, 0xA0, 0xE8,
26587+ 0x1D, 0x47, 0xA0, 0xE8,
26588+
26589+ 0x24, 0x4F, 0xA0, 0xE8,
26590+ 0x2C, 0x57, 0xA0, 0xE8,
26591+
26592+ 0x1C, 0x00,
26593+ 0x23, 0x00,
26594+ 0x2B, 0x00,
26595+ 0x00, 0xE0,
26596+
26597+ 0x1D, 0x00,
26598+ 0x24, 0x00,
26599+ 0x2C, 0x00,
26600+ 0x00, 0xE0,
26601+
26602+ 0x1C, 0x65,
26603+ 0x23, 0x65,
26604+ 0x2B, 0x65,
26605+ 0x00, 0xE0,
26606+
26607+ 0x1D, 0x65,
26608+ 0x24, 0x65,
26609+ 0x2C, 0x65,
26610+ 0x00, 0xE0,
26611+
26612+ 0x1C, 0x23, 0x60, 0xEC,
26613+ 0x36, 0xD7, 0x36, 0xAD,
26614+
26615+ 0x2B, 0x80, 0x60, 0xEC,
26616+ 0x1D, 0x24, 0x60, 0xEC,
26617+
26618+ 0x3E, 0xD7, 0x3E, 0xAD,
26619+ 0x2C, 0x80, 0x60, 0xEC,
26620+
26621+ 0x1C, 0x2B, 0xDE, 0xE8,
26622+ 0x23, 0x80, 0xDE, 0xE8,
26623+
26624+ 0x36, 0x80, 0x36, 0xBD,
26625+ 0x3E, 0x80, 0x3E, 0xBD,
26626+
26627+ 0x33, 0xD7, 0x1C, 0xBD,
26628+ 0x3B, 0xD7, 0x23, 0xBD,
26629+
26630+ 0x46, 0x80, 0x46, 0xCF,
26631+ 0x4F, 0x80, 0x4F, 0xCF,
26632+
26633+ 0x56, 0x33, 0x56, 0xCF,
26634+ 0x47, 0x3B, 0x47, 0xCF,
26635+
26636+ 0xC5, 0xFF, 0x20, 0xEA,
26637+ 0x00, 0x80, 0x00, 0xE8,
26638+
26639+ 0x4E, 0x33, 0x4E, 0xCF,
26640+ 0x57, 0x3B, 0x57, 0xCF,
26641+
26642+ 0x8B, 0xFF, 0x20, 0xEA,
26643+ 0x57, 0xC0, 0xBF, 0xEA,
26644+
26645+ 0x00, 0x80, 0xA0, 0xE9,
26646+ 0x00, 0x00, 0xD8, 0xEC,
26647+
26648+};
26649+
26650+static unsigned char warp_g400_tgzsaf[] = {
26651+
26652+ 0x00, 0x88, 0x98, 0xE9,
26653+ 0x00, 0x80, 0x00, 0xE8,
26654+
26655+ 0x00, 0x80, 0xA0, 0xE9,
26656+ 0x00, 0x00, 0xD8, 0xEC,
26657+
26658+ 0xFF, 0x80, 0xC0, 0xE9,
26659+ 0x00, 0x80, 0x00, 0xE8,
26660+
26661+ 0x22, 0x40, 0x48, 0xBF,
26662+ 0x2A, 0x40, 0x50, 0xBF,
26663+
26664+ 0x32, 0x41, 0x49, 0xBF,
26665+ 0x3A, 0x41, 0x51, 0xBF,
26666+
26667+ 0xC3, 0x6B,
26668+ 0xCB, 0x6B,
26669+ 0x00, 0x88, 0x98, 0xE9,
26670+
26671+ 0x73, 0x7B, 0xC8, 0xEC,
26672+ 0x96, 0xE2,
26673+ 0x41, 0x04,
26674+
26675+ 0x7B, 0x43, 0xA0, 0xE8,
26676+ 0x73, 0x4B, 0xA0, 0xE8,
26677+
26678+ 0xAD, 0xEE, 0x29, 0x9F,
26679+ 0x00, 0xE0,
26680+ 0x49, 0x04,
26681+
26682+ 0x90, 0xE2,
26683+ 0x51, 0x04,
26684+ 0x31, 0x46, 0xB1, 0xE8,
26685+
26686+ 0x49, 0x41, 0xC0, 0xEC,
26687+ 0x39, 0x57, 0xB1, 0xE8,
26688+
26689+ 0x00, 0x04,
26690+ 0x46, 0xE2,
26691+ 0x73, 0x53, 0xA0, 0xE8,
26692+
26693+ 0x51, 0x41, 0xC0, 0xEC,
26694+ 0x31, 0x00,
26695+ 0x39, 0x00,
26696+
26697+ 0x6E, 0x80, 0x15, 0xEA,
26698+ 0x08, 0x04,
26699+ 0x10, 0x04,
26700+
26701+ 0x51, 0x49, 0xC0, 0xEC,
26702+ 0x2F, 0x41, 0x60, 0xEA,
26703+
26704+ 0x31, 0x20,
26705+ 0x39, 0x20,
26706+ 0x1F, 0x42, 0xA0, 0xE8,
26707+
26708+ 0x2A, 0x42, 0x4A, 0xBF,
26709+ 0x27, 0x4A, 0xA0, 0xE8,
26710+
26711+ 0x1A, 0x42, 0x52, 0xBF,
26712+ 0x1E, 0x49, 0x60, 0xEA,
26713+
26714+ 0x73, 0x7B, 0xC8, 0xEC,
26715+ 0x26, 0x51, 0x60, 0xEA,
26716+
26717+ 0x32, 0x40, 0x48, 0xBD,
26718+ 0x22, 0x40, 0x50, 0xBD,
26719+
26720+ 0x12, 0x41, 0x49, 0xBD,
26721+ 0x3A, 0x41, 0x51, 0xBD,
26722+
26723+ 0xBF, 0x2F, 0x26, 0xBD,
26724+ 0x00, 0xE0,
26725+ 0x7B, 0x72,
26726+
26727+ 0x32, 0x20,
26728+ 0x22, 0x20,
26729+ 0x12, 0x20,
26730+ 0x3A, 0x20,
26731+
26732+ 0x46, 0x31, 0x46, 0xBF,
26733+ 0x4E, 0x31, 0x4E, 0xBF,
26734+
26735+ 0xB3, 0xE2, 0x2D, 0x9F,
26736+ 0x00, 0x80, 0x00, 0xE8,
26737+
26738+ 0x56, 0x31, 0x56, 0xBF,
26739+ 0x47, 0x39, 0x47, 0xBF,
26740+
26741+ 0x4F, 0x39, 0x4F, 0xBF,
26742+ 0x57, 0x39, 0x57, 0xBF,
26743+
26744+ 0x60, 0x80, 0x07, 0xEA,
26745+ 0x24, 0x41, 0x20, 0xE9,
26746+
26747+ 0x42, 0x73, 0xF8, 0xEC,
26748+ 0x00, 0xE0,
26749+ 0x2D, 0x73,
26750+
26751+ 0x33, 0x72,
26752+ 0x0C, 0xE3,
26753+ 0xA5, 0x2F, 0x1E, 0xBD,
26754+
26755+ 0x43, 0x43, 0x2D, 0xDF,
26756+ 0x4B, 0x4B, 0x2D, 0xDF,
26757+
26758+ 0xAE, 0x1E, 0x26, 0xBD,
26759+ 0x58, 0xE3,
26760+ 0x33, 0x66,
26761+
26762+ 0x53, 0x53, 0x2D, 0xDF,
26763+ 0x00, 0x80, 0x00, 0xE8,
26764+
26765+ 0xB8, 0x38, 0x33, 0xBF,
26766+ 0x00, 0xE0,
26767+ 0x59, 0xE3,
26768+
26769+ 0x1E, 0x12, 0x41, 0xE9,
26770+ 0x1A, 0x22, 0x41, 0xE9,
26771+
26772+ 0x2B, 0x40, 0x3D, 0xE9,
26773+ 0x3F, 0x4B, 0xA0, 0xE8,
26774+
26775+ 0x2D, 0x73,
26776+ 0x30, 0x76,
26777+ 0x05, 0x80, 0x3D, 0xEA,
26778+
26779+ 0x37, 0x43, 0xA0, 0xE8,
26780+ 0x3D, 0x53, 0xA0, 0xE8,
26781+
26782+ 0x48, 0x70, 0xF8, 0xEC,
26783+ 0x2B, 0x48, 0x3C, 0xE9,
26784+
26785+ 0x1F, 0x27, 0xBC, 0xE8,
26786+ 0x00, 0x80, 0x00, 0xE8,
26787+
26788+ 0x00, 0x80, 0x00, 0xE8,
26789+ 0x00, 0x80, 0x00, 0xE8,
26790+
26791+ 0x15, 0xC0, 0x20, 0xE9,
26792+ 0x15, 0xC0, 0x20, 0xE9,
26793+
26794+ 0x15, 0xC0, 0x20, 0xE9,
26795+ 0x15, 0xC0, 0x20, 0xE9,
26796+
26797+ 0x18, 0x3A, 0x41, 0xE9,
26798+ 0x1D, 0x32, 0x41, 0xE9,
26799+
26800+ 0x2A, 0x40, 0x20, 0xE9,
26801+ 0x56, 0x3D, 0x56, 0xDF,
26802+
26803+ 0x46, 0x37, 0x46, 0xDF,
26804+ 0x4E, 0x3F, 0x4E, 0xDF,
26805+
26806+ 0x16, 0x30, 0x20, 0xE9,
26807+ 0x4F, 0x3F, 0x4F, 0xDF,
26808+
26809+ 0x47, 0x37, 0x47, 0xDF,
26810+ 0x57, 0x3D, 0x57, 0xDF,
26811+
26812+ 0x32, 0x32, 0x2D, 0xDF,
26813+ 0x22, 0x22, 0x2D, 0xDF,
26814+
26815+ 0x12, 0x12, 0x2D, 0xDF,
26816+ 0x3A, 0x3A, 0x2D, 0xDF,
26817+
26818+ 0x27, 0xCF, 0x74, 0xC2,
26819+ 0x37, 0xCF, 0x74, 0xC4,
26820+
26821+ 0x0A, 0x44, 0x4C, 0xB0,
26822+ 0x02, 0x44, 0x54, 0xB0,
26823+
26824+ 0x3D, 0xCF, 0x74, 0xC0,
26825+ 0x34, 0x37, 0x20, 0xE9,
26826+
26827+ 0x31, 0x53, 0x2F, 0x9F,
26828+ 0x38, 0x27, 0x20, 0xE9,
26829+
26830+ 0x39, 0xE5, 0x2C, 0x9F,
26831+ 0x3C, 0x3D, 0x20, 0xE9,
26832+
26833+ 0x2A, 0x44, 0x4C, 0xB2,
26834+ 0x1A, 0x44, 0x54, 0xB2,
26835+
26836+ 0x32, 0x80, 0x3A, 0xEA,
26837+ 0x0A, 0x20,
26838+ 0x02, 0x20,
26839+
26840+ 0x27, 0xCF, 0x75, 0xC0,
26841+ 0x2A, 0x20,
26842+ 0x1A, 0x20,
26843+
26844+ 0x30, 0x50, 0x2E, 0x9F,
26845+ 0x32, 0x31, 0x5F, 0xE9,
26846+
26847+ 0x38, 0x21, 0x2C, 0x9F,
26848+ 0x33, 0x39, 0x5F, 0xE9,
26849+
26850+ 0x3D, 0xCF, 0x75, 0xC2,
26851+ 0x37, 0xCF, 0x75, 0xC4,
26852+
26853+ 0x31, 0x53, 0x2F, 0x9F,
26854+ 0xA6, 0x27, 0x20, 0xE9,
26855+
26856+ 0x39, 0xE5, 0x2C, 0x9F,
26857+ 0xA3, 0x3D, 0x20, 0xE9,
26858+
26859+ 0x2A, 0x44, 0x4C, 0xB4,
26860+ 0x1A, 0x44, 0x54, 0xB4,
26861+
26862+ 0x0A, 0x45, 0x4D, 0xB0,
26863+ 0x02, 0x45, 0x55, 0xB0,
26864+
26865+ 0x88, 0x73, 0x5E, 0xE9,
26866+ 0x2A, 0x20,
26867+ 0x1A, 0x20,
26868+
26869+ 0xA0, 0x37, 0x20, 0xE9,
26870+ 0x0A, 0x20,
26871+ 0x02, 0x20,
26872+
26873+ 0x31, 0x53, 0x2F, 0x9F,
26874+ 0x3E, 0x30, 0x4F, 0xE9,
26875+
26876+ 0x39, 0xE5, 0x2C, 0x9F,
26877+ 0x3F, 0x38, 0x4F, 0xE9,
26878+
26879+ 0x30, 0x50, 0x2E, 0x9F,
26880+ 0x3A, 0x31, 0x4F, 0xE9,
26881+
26882+ 0x38, 0x21, 0x2C, 0x9F,
26883+ 0x3B, 0x39, 0x4F, 0xE9,
26884+
26885+ 0x2A, 0x45, 0x4D, 0xB2,
26886+ 0x1A, 0x45, 0x55, 0xB2,
26887+
26888+ 0x0A, 0x45, 0x4D, 0xB4,
26889+ 0x02, 0x45, 0x55, 0xB4,
26890+
26891+ 0x27, 0xCF, 0x74, 0xC6,
26892+ 0x2A, 0x20,
26893+ 0x1A, 0x20,
26894+
26895+ 0xA7, 0x30, 0x4F, 0xE9,
26896+ 0x0A, 0x20,
26897+ 0x02, 0x20,
26898+
26899+ 0x31, 0x53, 0x2F, 0x9F,
26900+ 0x9C, 0x27, 0x20, 0xE9,
26901+
26902+ 0x39, 0xE5, 0x2C, 0x9F,
26903+ 0xA8, 0x38, 0x4F, 0xE9,
26904+
26905+ 0x2A, 0x44, 0x4C, 0xB6,
26906+ 0x1A, 0x44, 0x54, 0xB6,
26907+
26908+ 0x30, 0x50, 0x2E, 0x9F,
26909+ 0x36, 0x31, 0x4F, 0xE9,
26910+
26911+ 0x38, 0x21, 0x2C, 0x9F,
26912+ 0x37, 0x39, 0x4F, 0xE9,
26913+
26914+ 0x0A, 0x45, 0x4D, 0xB6,
26915+ 0x02, 0x45, 0x55, 0xB6,
26916+
26917+ 0x3D, 0xCF, 0x75, 0xC6,
26918+ 0x2A, 0x20,
26919+ 0x1A, 0x20,
26920+
26921+ 0x2A, 0x46, 0x4E, 0xBF,
26922+ 0x1A, 0x46, 0x56, 0xBF,
26923+
26924+ 0x31, 0x53, 0x2F, 0x9F,
26925+ 0xA4, 0x31, 0x4F, 0xE9,
26926+
26927+ 0x39, 0xE5, 0x2C, 0x9F,
26928+ 0xA5, 0x39, 0x4F, 0xE9,
26929+
26930+ 0x31, 0x3D, 0x20, 0xE9,
26931+ 0x0A, 0x20,
26932+ 0x02, 0x20,
26933+
26934+ 0x0A, 0x47, 0x4F, 0xBF,
26935+ 0x02, 0x47, 0x57, 0xBF,
26936+
26937+ 0x30, 0x50, 0x2E, 0x9F,
26938+ 0xA1, 0x30, 0x4F, 0xE9,
26939+
26940+ 0x38, 0x21, 0x2C, 0x9F,
26941+ 0xA2, 0x38, 0x4F, 0xE9,
26942+
26943+ 0x31, 0x53, 0x2F, 0x9F,
26944+ 0x9D, 0x31, 0x4F, 0xE9,
26945+
26946+ 0x39, 0xE5, 0x2C, 0x9F,
26947+ 0x9E, 0x39, 0x4F, 0xE9,
26948+
26949+ 0x2A, 0x43, 0x4B, 0xBF,
26950+ 0x1A, 0x43, 0x53, 0xBF,
26951+
26952+ 0x30, 0x50, 0x2E, 0x9F,
26953+ 0x35, 0x30, 0x4F, 0xE9,
26954+
26955+ 0x38, 0x21, 0x2C, 0x9F,
26956+ 0x39, 0x38, 0x4F, 0xE9,
26957+
26958+ 0x31, 0x53, 0x2F, 0x9F,
26959+ 0x80, 0x31, 0x57, 0xE9,
26960+
26961+ 0x39, 0xE5, 0x2C, 0x9F,
26962+ 0x81, 0x39, 0x57, 0xE9,
26963+
26964+ 0x37, 0x48, 0x50, 0xBD,
26965+ 0x8A, 0x36, 0x20, 0xE9,
26966+
26967+ 0x86, 0x76, 0x57, 0xE9,
26968+ 0x8B, 0x3E, 0x20, 0xE9,
26969+
26970+ 0x82, 0x30, 0x57, 0xE9,
26971+ 0x87, 0x77, 0x57, 0xE9,
26972+
26973+ 0x83, 0x38, 0x57, 0xE9,
26974+ 0x35, 0x49, 0x51, 0xBD,
26975+
26976+ 0x84, 0x31, 0x5E, 0xE9,
26977+ 0x30, 0x1F, 0x5F, 0xE9,
26978+
26979+ 0x85, 0x39, 0x5E, 0xE9,
26980+ 0x57, 0x25, 0x20, 0xE9,
26981+
26982+ 0x2B, 0x48, 0x20, 0xE9,
26983+ 0x1D, 0x37, 0xE1, 0xEA,
26984+
26985+ 0x1E, 0x35, 0xE1, 0xEA,
26986+ 0x00, 0xE0,
26987+ 0x26, 0x77,
26988+
26989+ 0x24, 0x49, 0x20, 0xE9,
26990+ 0x99, 0xFF, 0x20, 0xEA,
26991+
26992+ 0x16, 0x26, 0x20, 0xE9,
26993+ 0x57, 0x2E, 0xBF, 0xEA,
26994+
26995+ 0x1C, 0x46, 0xA0, 0xE8,
26996+ 0x23, 0x4E, 0xA0, 0xE8,
26997+
26998+ 0x2B, 0x56, 0xA0, 0xE8,
26999+ 0x1D, 0x47, 0xA0, 0xE8,
27000+
27001+ 0x24, 0x4F, 0xA0, 0xE8,
27002+ 0x2C, 0x57, 0xA0, 0xE8,
27003+
27004+ 0x1C, 0x00,
27005+ 0x23, 0x00,
27006+ 0x2B, 0x00,
27007+ 0x00, 0xE0,
27008+
27009+ 0x1D, 0x00,
27010+ 0x24, 0x00,
27011+ 0x2C, 0x00,
27012+ 0x00, 0xE0,
27013+
27014+ 0x1C, 0x65,
27015+ 0x23, 0x65,
27016+ 0x2B, 0x65,
27017+ 0x00, 0xE0,
27018+
27019+ 0x1D, 0x65,
27020+ 0x24, 0x65,
27021+ 0x2C, 0x65,
27022+ 0x00, 0xE0,
27023+
27024+ 0x1C, 0x23, 0x60, 0xEC,
27025+ 0x36, 0xD7, 0x36, 0xAD,
27026+
27027+ 0x2B, 0x80, 0x60, 0xEC,
27028+ 0x1D, 0x24, 0x60, 0xEC,
27029+
27030+ 0x3E, 0xD7, 0x3E, 0xAD,
27031+ 0x2C, 0x80, 0x60, 0xEC,
27032+
27033+ 0x1C, 0x2B, 0xDE, 0xE8,
27034+ 0x23, 0x80, 0xDE, 0xE8,
27035+
27036+ 0x36, 0x80, 0x36, 0xBD,
27037+ 0x3E, 0x80, 0x3E, 0xBD,
27038+
27039+ 0x33, 0xD7, 0x1C, 0xBD,
27040+ 0x3B, 0xD7, 0x23, 0xBD,
27041+
27042+ 0x46, 0x80, 0x46, 0xCF,
27043+ 0x4F, 0x80, 0x4F, 0xCF,
27044+
27045+ 0x56, 0x33, 0x56, 0xCF,
27046+ 0x47, 0x3B, 0x47, 0xCF,
27047+
27048+ 0xC1, 0xFF, 0x20, 0xEA,
27049+ 0x00, 0x80, 0x00, 0xE8,
27050+
27051+ 0x4E, 0x33, 0x4E, 0xCF,
27052+ 0x57, 0x3B, 0x57, 0xCF,
27053+
27054+ 0x87, 0xFF, 0x20, 0xEA,
27055+ 0x57, 0xC0, 0xBF, 0xEA,
27056+
27057+ 0x00, 0x80, 0xA0, 0xE9,
27058+ 0x00, 0x00, 0xD8, 0xEC,
27059+
27060+};
27061+
27062+static unsigned char warp_g400_tgzsf[] = {
27063+
27064+ 0x00, 0x88, 0x98, 0xE9,
27065+ 0x00, 0x80, 0x00, 0xE8,
27066+
27067+ 0x00, 0x80, 0xA0, 0xE9,
27068+ 0x00, 0x00, 0xD8, 0xEC,
27069+
27070+ 0xFF, 0x80, 0xC0, 0xE9,
27071+ 0x00, 0x80, 0x00, 0xE8,
27072+
27073+ 0x22, 0x40, 0x48, 0xBF,
27074+ 0x2A, 0x40, 0x50, 0xBF,
27075+
27076+ 0x32, 0x41, 0x49, 0xBF,
27077+ 0x3A, 0x41, 0x51, 0xBF,
27078+
27079+ 0xC3, 0x6B,
27080+ 0xCB, 0x6B,
27081+ 0x00, 0x88, 0x98, 0xE9,
27082+
27083+ 0x73, 0x7B, 0xC8, 0xEC,
27084+ 0x96, 0xE2,
27085+ 0x41, 0x04,
27086+
27087+ 0x7B, 0x43, 0xA0, 0xE8,
27088+ 0x73, 0x4B, 0xA0, 0xE8,
27089+
27090+ 0xAD, 0xEE, 0x29, 0x9F,
27091+ 0x00, 0xE0,
27092+ 0x49, 0x04,
27093+
27094+ 0x90, 0xE2,
27095+ 0x51, 0x04,
27096+ 0x31, 0x46, 0xB1, 0xE8,
27097+
27098+ 0x49, 0x41, 0xC0, 0xEC,
27099+ 0x39, 0x57, 0xB1, 0xE8,
27100+
27101+ 0x00, 0x04,
27102+ 0x46, 0xE2,
27103+ 0x73, 0x53, 0xA0, 0xE8,
27104+
27105+ 0x51, 0x41, 0xC0, 0xEC,
27106+ 0x31, 0x00,
27107+ 0x39, 0x00,
27108+
27109+ 0x6A, 0x80, 0x15, 0xEA,
27110+ 0x08, 0x04,
27111+ 0x10, 0x04,
27112+
27113+ 0x51, 0x49, 0xC0, 0xEC,
27114+ 0x2F, 0x41, 0x60, 0xEA,
27115+
27116+ 0x31, 0x20,
27117+ 0x39, 0x20,
27118+ 0x1F, 0x42, 0xA0, 0xE8,
27119+
27120+ 0x2A, 0x42, 0x4A, 0xBF,
27121+ 0x27, 0x4A, 0xA0, 0xE8,
27122+
27123+ 0x1A, 0x42, 0x52, 0xBF,
27124+ 0x1E, 0x49, 0x60, 0xEA,
27125+
27126+ 0x73, 0x7B, 0xC8, 0xEC,
27127+ 0x26, 0x51, 0x60, 0xEA,
27128+
27129+ 0x32, 0x40, 0x48, 0xBD,
27130+ 0x22, 0x40, 0x50, 0xBD,
27131+
27132+ 0x12, 0x41, 0x49, 0xBD,
27133+ 0x3A, 0x41, 0x51, 0xBD,
27134+
27135+ 0xBF, 0x2F, 0x26, 0xBD,
27136+ 0x00, 0xE0,
27137+ 0x7B, 0x72,
27138+
27139+ 0x32, 0x20,
27140+ 0x22, 0x20,
27141+ 0x12, 0x20,
27142+ 0x3A, 0x20,
27143+
27144+ 0x46, 0x31, 0x46, 0xBF,
27145+ 0x4E, 0x31, 0x4E, 0xBF,
27146+
27147+ 0xB3, 0xE2, 0x2D, 0x9F,
27148+ 0x00, 0x80, 0x00, 0xE8,
27149+
27150+ 0x56, 0x31, 0x56, 0xBF,
27151+ 0x47, 0x39, 0x47, 0xBF,
27152+
27153+ 0x4F, 0x39, 0x4F, 0xBF,
27154+ 0x57, 0x39, 0x57, 0xBF,
27155+
27156+ 0x5C, 0x80, 0x07, 0xEA,
27157+ 0x24, 0x41, 0x20, 0xE9,
27158+
27159+ 0x42, 0x73, 0xF8, 0xEC,
27160+ 0x00, 0xE0,
27161+ 0x2D, 0x73,
27162+
27163+ 0x33, 0x72,
27164+ 0x0C, 0xE3,
27165+ 0xA5, 0x2F, 0x1E, 0xBD,
27166+
27167+ 0x43, 0x43, 0x2D, 0xDF,
27168+ 0x4B, 0x4B, 0x2D, 0xDF,
27169+
27170+ 0xAE, 0x1E, 0x26, 0xBD,
27171+ 0x58, 0xE3,
27172+ 0x33, 0x66,
27173+
27174+ 0x53, 0x53, 0x2D, 0xDF,
27175+ 0x00, 0x80, 0x00, 0xE8,
27176+
27177+ 0xB8, 0x38, 0x33, 0xBF,
27178+ 0x00, 0xE0,
27179+ 0x59, 0xE3,
27180+
27181+ 0x1E, 0x12, 0x41, 0xE9,
27182+ 0x1A, 0x22, 0x41, 0xE9,
27183+
27184+ 0x2B, 0x40, 0x3D, 0xE9,
27185+ 0x3F, 0x4B, 0xA0, 0xE8,
27186+
27187+ 0x2D, 0x73,
27188+ 0x30, 0x76,
27189+ 0x05, 0x80, 0x3D, 0xEA,
27190+
27191+ 0x37, 0x43, 0xA0, 0xE8,
27192+ 0x3D, 0x53, 0xA0, 0xE8,
27193+
27194+ 0x48, 0x70, 0xF8, 0xEC,
27195+ 0x2B, 0x48, 0x3C, 0xE9,
27196+
27197+ 0x1F, 0x27, 0xBC, 0xE8,
27198+ 0x00, 0x80, 0x00, 0xE8,
27199+
27200+ 0x00, 0x80, 0x00, 0xE8,
27201+ 0x00, 0x80, 0x00, 0xE8,
27202+
27203+ 0x15, 0xC0, 0x20, 0xE9,
27204+ 0x15, 0xC0, 0x20, 0xE9,
27205+
27206+ 0x15, 0xC0, 0x20, 0xE9,
27207+ 0x15, 0xC0, 0x20, 0xE9,
27208+
27209+ 0x18, 0x3A, 0x41, 0xE9,
27210+ 0x1D, 0x32, 0x41, 0xE9,
27211+
27212+ 0x2A, 0x40, 0x20, 0xE9,
27213+ 0x56, 0x3D, 0x56, 0xDF,
27214+
27215+ 0x46, 0x37, 0x46, 0xDF,
27216+ 0x4E, 0x3F, 0x4E, 0xDF,
27217+
27218+ 0x16, 0x30, 0x20, 0xE9,
27219+ 0x4F, 0x3F, 0x4F, 0xDF,
27220+
27221+ 0x47, 0x37, 0x47, 0xDF,
27222+ 0x57, 0x3D, 0x57, 0xDF,
27223+
27224+ 0x32, 0x32, 0x2D, 0xDF,
27225+ 0x22, 0x22, 0x2D, 0xDF,
27226+
27227+ 0x12, 0x12, 0x2D, 0xDF,
27228+ 0x3A, 0x3A, 0x2D, 0xDF,
27229+
27230+ 0x27, 0xCF, 0x74, 0xC2,
27231+ 0x37, 0xCF, 0x74, 0xC4,
27232+
27233+ 0x0A, 0x44, 0x4C, 0xB0,
27234+ 0x02, 0x44, 0x54, 0xB0,
27235+
27236+ 0x3D, 0xCF, 0x74, 0xC0,
27237+ 0x34, 0x37, 0x20, 0xE9,
27238+
27239+ 0x31, 0x53, 0x2F, 0x9F,
27240+ 0x38, 0x27, 0x20, 0xE9,
27241+
27242+ 0x39, 0xE5, 0x2C, 0x9F,
27243+ 0x3C, 0x3D, 0x20, 0xE9,
27244+
27245+ 0x2A, 0x44, 0x4C, 0xB2,
27246+ 0x1A, 0x44, 0x54, 0xB2,
27247+
27248+ 0x2E, 0x80, 0x3A, 0xEA,
27249+ 0x0A, 0x20,
27250+ 0x02, 0x20,
27251+
27252+ 0x27, 0xCF, 0x75, 0xC0,
27253+ 0x2A, 0x20,
27254+ 0x1A, 0x20,
27255+
27256+ 0x30, 0x50, 0x2E, 0x9F,
27257+ 0x32, 0x31, 0x5F, 0xE9,
27258+
27259+ 0x38, 0x21, 0x2C, 0x9F,
27260+ 0x33, 0x39, 0x5F, 0xE9,
27261+
27262+ 0x3D, 0xCF, 0x75, 0xC2,
27263+ 0x37, 0xCF, 0x75, 0xC4,
27264+
27265+ 0x31, 0x53, 0x2F, 0x9F,
27266+ 0xA6, 0x27, 0x20, 0xE9,
27267+
27268+ 0x39, 0xE5, 0x2C, 0x9F,
27269+ 0xA3, 0x3D, 0x20, 0xE9,
27270+
27271+ 0x2A, 0x44, 0x4C, 0xB4,
27272+ 0x1A, 0x44, 0x54, 0xB4,
27273+
27274+ 0x0A, 0x45, 0x4D, 0xB0,
27275+ 0x02, 0x45, 0x55, 0xB0,
27276+
27277+ 0x88, 0x73, 0x5E, 0xE9,
27278+ 0x2A, 0x20,
27279+ 0x1A, 0x20,
27280+
27281+ 0xA0, 0x37, 0x20, 0xE9,
27282+ 0x0A, 0x20,
27283+ 0x02, 0x20,
27284+
27285+ 0x31, 0x53, 0x2F, 0x9F,
27286+ 0x3E, 0x30, 0x4F, 0xE9,
27287+
27288+ 0x39, 0xE5, 0x2C, 0x9F,
27289+ 0x3F, 0x38, 0x4F, 0xE9,
27290+
27291+ 0x30, 0x50, 0x2E, 0x9F,
27292+ 0x3A, 0x31, 0x4F, 0xE9,
27293+
27294+ 0x38, 0x21, 0x2C, 0x9F,
27295+ 0x3B, 0x39, 0x4F, 0xE9,
27296+
27297+ 0x2A, 0x45, 0x4D, 0xB2,
27298+ 0x1A, 0x45, 0x55, 0xB2,
27299+
27300+ 0x0A, 0x45, 0x4D, 0xB4,
27301+ 0x02, 0x45, 0x55, 0xB4,
27302+
27303+ 0x27, 0xCF, 0x75, 0xC6,
27304+ 0x2A, 0x20,
27305+ 0x1A, 0x20,
27306+
27307+ 0xA7, 0x30, 0x4F, 0xE9,
27308+ 0x0A, 0x20,
27309+ 0x02, 0x20,
27310+
27311+ 0x31, 0x53, 0x2F, 0x9F,
27312+ 0x31, 0x27, 0x20, 0xE9,
27313+
27314+ 0x39, 0xE5, 0x2C, 0x9F,
27315+ 0xA8, 0x38, 0x4F, 0xE9,
27316+
27317+ 0x2A, 0x45, 0x4D, 0xB6,
27318+ 0x1A, 0x45, 0x55, 0xB6,
27319+
27320+ 0x30, 0x50, 0x2E, 0x9F,
27321+ 0x36, 0x31, 0x4F, 0xE9,
27322+
27323+ 0x38, 0x21, 0x2C, 0x9F,
27324+ 0x37, 0x39, 0x4F, 0xE9,
27325+
27326+ 0x00, 0x80, 0x00, 0xE8,
27327+ 0x2A, 0x20,
27328+ 0x1A, 0x20,
27329+
27330+ 0x2A, 0x46, 0x4E, 0xBF,
27331+ 0x1A, 0x46, 0x56, 0xBF,
27332+
27333+ 0x31, 0x53, 0x2F, 0x9F,
27334+ 0xA4, 0x31, 0x4F, 0xE9,
27335+
27336+ 0x39, 0xE5, 0x2C, 0x9F,
27337+ 0xA5, 0x39, 0x4F, 0xE9,
27338+
27339+ 0x0A, 0x47, 0x4F, 0xBF,
27340+ 0x02, 0x47, 0x57, 0xBF,
27341+
27342+ 0x31, 0x53, 0x2F, 0x9F,
27343+ 0xA1, 0x30, 0x4F, 0xE9,
27344+
27345+ 0x39, 0xE5, 0x2C, 0x9F,
27346+ 0xA2, 0x38, 0x4F, 0xE9,
27347+
27348+ 0x2A, 0x43, 0x4B, 0xBF,
27349+ 0x1A, 0x43, 0x53, 0xBF,
27350+
27351+ 0x30, 0x50, 0x2E, 0x9F,
27352+ 0x35, 0x31, 0x4F, 0xE9,
27353+
27354+ 0x38, 0x21, 0x2C, 0x9F,
27355+ 0x39, 0x39, 0x4F, 0xE9,
27356+
27357+ 0x31, 0x53, 0x2F, 0x9F,
27358+ 0x80, 0x31, 0x57, 0xE9,
27359+
27360+ 0x39, 0xE5, 0x2C, 0x9F,
27361+ 0x81, 0x39, 0x57, 0xE9,
27362+
27363+ 0x37, 0x48, 0x50, 0xBD,
27364+ 0x8A, 0x36, 0x20, 0xE9,
27365+
27366+ 0x86, 0x76, 0x57, 0xE9,
27367+ 0x8B, 0x3E, 0x20, 0xE9,
27368+
27369+ 0x82, 0x30, 0x57, 0xE9,
27370+ 0x87, 0x77, 0x57, 0xE9,
27371+
27372+ 0x83, 0x38, 0x57, 0xE9,
27373+ 0x35, 0x49, 0x51, 0xBD,
27374+
27375+ 0x84, 0x31, 0x5E, 0xE9,
27376+ 0x30, 0x1F, 0x5F, 0xE9,
27377+
27378+ 0x85, 0x39, 0x5E, 0xE9,
27379+ 0x57, 0x25, 0x20, 0xE9,
27380+
27381+ 0x2B, 0x48, 0x20, 0xE9,
27382+ 0x1D, 0x37, 0xE1, 0xEA,
27383+
27384+ 0x1E, 0x35, 0xE1, 0xEA,
27385+ 0x00, 0xE0,
27386+ 0x26, 0x77,
27387+
27388+ 0x24, 0x49, 0x20, 0xE9,
27389+ 0x9D, 0xFF, 0x20, 0xEA,
27390+
27391+ 0x16, 0x26, 0x20, 0xE9,
27392+ 0x57, 0x2E, 0xBF, 0xEA,
27393+
27394+ 0x1C, 0x46, 0xA0, 0xE8,
27395+ 0x23, 0x4E, 0xA0, 0xE8,
27396+
27397+ 0x2B, 0x56, 0xA0, 0xE8,
27398+ 0x1D, 0x47, 0xA0, 0xE8,
27399+
27400+ 0x24, 0x4F, 0xA0, 0xE8,
27401+ 0x2C, 0x57, 0xA0, 0xE8,
27402+
27403+ 0x1C, 0x00,
27404+ 0x23, 0x00,
27405+ 0x2B, 0x00,
27406+ 0x00, 0xE0,
27407+
27408+ 0x1D, 0x00,
27409+ 0x24, 0x00,
27410+ 0x2C, 0x00,
27411+ 0x00, 0xE0,
27412+
27413+ 0x1C, 0x65,
27414+ 0x23, 0x65,
27415+ 0x2B, 0x65,
27416+ 0x00, 0xE0,
27417+
27418+ 0x1D, 0x65,
27419+ 0x24, 0x65,
27420+ 0x2C, 0x65,
27421+ 0x00, 0xE0,
27422+
27423+ 0x1C, 0x23, 0x60, 0xEC,
27424+ 0x36, 0xD7, 0x36, 0xAD,
27425+
27426+ 0x2B, 0x80, 0x60, 0xEC,
27427+ 0x1D, 0x24, 0x60, 0xEC,
27428+
27429+ 0x3E, 0xD7, 0x3E, 0xAD,
27430+ 0x2C, 0x80, 0x60, 0xEC,
27431+
27432+ 0x1C, 0x2B, 0xDE, 0xE8,
27433+ 0x23, 0x80, 0xDE, 0xE8,
27434+
27435+ 0x36, 0x80, 0x36, 0xBD,
27436+ 0x3E, 0x80, 0x3E, 0xBD,
27437+
27438+ 0x33, 0xD7, 0x1C, 0xBD,
27439+ 0x3B, 0xD7, 0x23, 0xBD,
27440+
27441+ 0x46, 0x80, 0x46, 0xCF,
27442+ 0x4F, 0x80, 0x4F, 0xCF,
27443+
27444+ 0x56, 0x33, 0x56, 0xCF,
27445+ 0x47, 0x3B, 0x47, 0xCF,
27446+
27447+ 0xC5, 0xFF, 0x20, 0xEA,
27448+ 0x00, 0x80, 0x00, 0xE8,
27449+
27450+ 0x4E, 0x33, 0x4E, 0xCF,
27451+ 0x57, 0x3B, 0x57, 0xCF,
27452+
27453+ 0x8B, 0xFF, 0x20, 0xEA,
27454+ 0x57, 0xC0, 0xBF, 0xEA,
27455+
27456+ 0x00, 0x80, 0xA0, 0xE9,
27457+ 0x00, 0x00, 0xD8, 0xEC,
27458+
27459+};
27460Index: git/shared-core/mga_warp.c
27461===================================================================
27462--- /dev/null 1970-01-01 00:00:00.000000000 +0000
27463+++ git/shared-core/mga_warp.c 2008-12-12 17:35:22.000000000 +0000
27464@@ -0,0 +1,198 @@
27465+/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
27466+ * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
27467+ */
27468+/*
27469+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
27470+ * All Rights Reserved.
27471+ *
27472+ * Permission is hereby granted, free of charge, to any person obtaining a
27473+ * copy of this software and associated documentation files (the "Software"),
27474+ * to deal in the Software without restriction, including without limitation
27475+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
27476+ * and/or sell copies of the Software, and to permit persons to whom the
27477+ * Software is furnished to do so, subject to the following conditions:
27478+ *
27479+ * The above copyright notice and this permission notice (including the next
27480+ * paragraph) shall be included in all copies or substantial portions of the
27481+ * Software.
27482+ *
27483+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27484+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27485+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27486+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27487+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27488+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27489+ * OTHER DEALINGS IN THE SOFTWARE.
27490+ *
27491+ * Authors:
27492+ * Gareth Hughes <gareth@valinux.com>
27493+ */
27494+
27495+#include "drmP.h"
27496+#include "drm.h"
27497+#include "mga_drm.h"
27498+#include "mga_drv.h"
27499+#include "mga_ucode.h"
27500+
27501+#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
27502+
27503+#define WARP_UCODE_SIZE( which ) \
27504+ ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
27505+
27506+#define WARP_UCODE_INSTALL( which, where ) \
27507+do { \
27508+ DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\
27509+ dev_priv->warp_pipe_phys[where] = pcbase; \
27510+ memcpy( vcbase, which, sizeof(which) ); \
27511+ pcbase += WARP_UCODE_SIZE( which ); \
27512+ vcbase += WARP_UCODE_SIZE( which ); \
27513+} while (0)
27514+
27515+static const unsigned int mga_warp_g400_microcode_size =
27516+ (WARP_UCODE_SIZE(warp_g400_tgz) +
27517+ WARP_UCODE_SIZE(warp_g400_tgza) +
27518+ WARP_UCODE_SIZE(warp_g400_tgzaf) +
27519+ WARP_UCODE_SIZE(warp_g400_tgzf) +
27520+ WARP_UCODE_SIZE(warp_g400_tgzs) +
27521+ WARP_UCODE_SIZE(warp_g400_tgzsa) +
27522+ WARP_UCODE_SIZE(warp_g400_tgzsaf) +
27523+ WARP_UCODE_SIZE(warp_g400_tgzsf) +
27524+ WARP_UCODE_SIZE(warp_g400_t2gz) +
27525+ WARP_UCODE_SIZE(warp_g400_t2gza) +
27526+ WARP_UCODE_SIZE(warp_g400_t2gzaf) +
27527+ WARP_UCODE_SIZE(warp_g400_t2gzf) +
27528+ WARP_UCODE_SIZE(warp_g400_t2gzs) +
27529+ WARP_UCODE_SIZE(warp_g400_t2gzsa) +
27530+ WARP_UCODE_SIZE(warp_g400_t2gzsaf) +
27531+ WARP_UCODE_SIZE(warp_g400_t2gzsf));
27532+
27533+static const unsigned int mga_warp_g200_microcode_size =
27534+ (WARP_UCODE_SIZE(warp_g200_tgz) +
27535+ WARP_UCODE_SIZE(warp_g200_tgza) +
27536+ WARP_UCODE_SIZE(warp_g200_tgzaf) +
27537+ WARP_UCODE_SIZE(warp_g200_tgzf) +
27538+ WARP_UCODE_SIZE(warp_g200_tgzs) +
27539+ WARP_UCODE_SIZE(warp_g200_tgzsa) +
27540+ WARP_UCODE_SIZE(warp_g200_tgzsaf) +
27541+ WARP_UCODE_SIZE(warp_g200_tgzsf));
27542+
27543+
27544+unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
27545+{
27546+ switch (dev_priv->chipset) {
27547+ case MGA_CARD_TYPE_G400:
27548+ case MGA_CARD_TYPE_G550:
27549+ return PAGE_ALIGN(mga_warp_g400_microcode_size);
27550+ case MGA_CARD_TYPE_G200:
27551+ return PAGE_ALIGN(mga_warp_g200_microcode_size);
27552+ default:
27553+ DRM_ERROR("Unknown chipset value: 0x%x\n", dev_priv->chipset);
27554+ return 0;
27555+ }
27556+}
27557+
27558+static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
27559+{
27560+ unsigned char *vcbase = dev_priv->warp->handle;
27561+ unsigned long pcbase = dev_priv->warp->offset;
27562+
27563+ memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
27564+
27565+ WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
27566+ WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
27567+ WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
27568+ WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
27569+ WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
27570+ WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
27571+ WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
27572+ WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
27573+
27574+ WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
27575+ WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
27576+ WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
27577+ WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
27578+ WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
27579+ WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
27580+ WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
27581+ WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
27582+
27583+ return 0;
27584+}
27585+
27586+static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
27587+{
27588+ unsigned char *vcbase = dev_priv->warp->handle;
27589+ unsigned long pcbase = dev_priv->warp->offset;
27590+
27591+ memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
27592+
27593+ WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ);
27594+ WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF);
27595+ WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA);
27596+ WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF);
27597+ WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS);
27598+ WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF);
27599+ WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA);
27600+ WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF);
27601+
27602+ return 0;
27603+}
27604+
27605+int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
27606+{
27607+ const unsigned int size = mga_warp_microcode_size(dev_priv);
27608+
27609+ DRM_DEBUG("MGA ucode size = %d bytes\n", size);
27610+ if (size > dev_priv->warp->size) {
27611+ DRM_ERROR("microcode too large! (%u > %lu)\n",
27612+ size, dev_priv->warp->size);
27613+ return -ENOMEM;
27614+ }
27615+
27616+ switch (dev_priv->chipset) {
27617+ case MGA_CARD_TYPE_G400:
27618+ case MGA_CARD_TYPE_G550:
27619+ return mga_warp_install_g400_microcode(dev_priv);
27620+ case MGA_CARD_TYPE_G200:
27621+ return mga_warp_install_g200_microcode(dev_priv);
27622+ default:
27623+ return -EINVAL;
27624+ }
27625+}
27626+
27627+#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
27628+
27629+int mga_warp_init(drm_mga_private_t * dev_priv)
27630+{
27631+ u32 wmisc;
27632+
27633+ /* FIXME: Get rid of these damned magic numbers...
27634+ */
27635+ switch (dev_priv->chipset) {
27636+ case MGA_CARD_TYPE_G400:
27637+ case MGA_CARD_TYPE_G550:
27638+ MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND);
27639+ MGA_WRITE(MGA_WGETMSB, 0x00000E00);
27640+ MGA_WRITE(MGA_WVRTXSZ, 0x00001807);
27641+ MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000);
27642+ break;
27643+ case MGA_CARD_TYPE_G200:
27644+ MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND);
27645+ MGA_WRITE(MGA_WGETMSB, 0x1606);
27646+ MGA_WRITE(MGA_WVRTXSZ, 7);
27647+ break;
27648+ default:
27649+ return -EINVAL;
27650+ }
27651+
27652+ MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
27653+ MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE));
27654+ wmisc = MGA_READ(MGA_WMISC);
27655+ if (wmisc != WMISC_EXPECTED) {
27656+ DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n",
27657+ wmisc, WMISC_EXPECTED);
27658+ return -EINVAL;
27659+ }
27660+
27661+ return 0;
27662+}
27663Index: git/shared-core/nouveau_drm.h
27664===================================================================
27665--- /dev/null 1970-01-01 00:00:00.000000000 +0000
27666+++ git/shared-core/nouveau_drm.h 2008-12-12 17:35:22.000000000 +0000
27667@@ -0,0 +1,164 @@
27668+/*
27669+ * Copyright 2005 Stephane Marchesin.
27670+ * All Rights Reserved.
27671+ *
27672+ * Permission is hereby granted, free of charge, to any person obtaining a
27673+ * copy of this software and associated documentation files (the "Software"),
27674+ * to deal in the Software without restriction, including without limitation
27675+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
27676+ * and/or sell copies of the Software, and to permit persons to whom the
27677+ * Software is furnished to do so, subject to the following conditions:
27678+ *
27679+ * The above copyright notice and this permission notice (including the next
27680+ * paragraph) shall be included in all copies or substantial portions of the
27681+ * Software.
27682+ *
27683+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27684+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27685+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27686+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27687+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27688+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27689+ * OTHER DEALINGS IN THE SOFTWARE.
27690+ */
27691+
27692+#ifndef __NOUVEAU_DRM_H__
27693+#define __NOUVEAU_DRM_H__
27694+
27695+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 10
27696+
27697+struct drm_nouveau_channel_alloc {
27698+ uint32_t fb_ctxdma_handle;
27699+ uint32_t tt_ctxdma_handle;
27700+
27701+ int channel;
27702+ uint32_t put_base;
27703+ /* FIFO control regs */
27704+ drm_handle_t ctrl;
27705+ int ctrl_size;
27706+ /* DMA command buffer */
27707+ drm_handle_t cmdbuf;
27708+ int cmdbuf_size;
27709+ /* Notifier memory */
27710+ drm_handle_t notifier;
27711+ int notifier_size;
27712+};
27713+
27714+struct drm_nouveau_channel_free {
27715+ int channel;
27716+};
27717+
27718+struct drm_nouveau_grobj_alloc {
27719+ int channel;
27720+ uint32_t handle;
27721+ int class;
27722+};
27723+
27724+#define NOUVEAU_MEM_ACCESS_RO 1
27725+#define NOUVEAU_MEM_ACCESS_WO 2
27726+#define NOUVEAU_MEM_ACCESS_RW 3
27727+struct drm_nouveau_notifierobj_alloc {
27728+ int channel;
27729+ uint32_t handle;
27730+ int count;
27731+
27732+ uint32_t offset;
27733+};
27734+
27735+struct drm_nouveau_gpuobj_free {
27736+ int channel;
27737+ uint32_t handle;
27738+};
27739+
27740+#define NOUVEAU_MEM_FB 0x00000001
27741+#define NOUVEAU_MEM_AGP 0x00000002
27742+#define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004
27743+#define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008
27744+#define NOUVEAU_MEM_PCI 0x00000010
27745+#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020
27746+#define NOUVEAU_MEM_PINNED 0x00000040
27747+#define NOUVEAU_MEM_USER_BACKED 0x00000080
27748+#define NOUVEAU_MEM_MAPPED 0x00000100
27749+#define NOUVEAU_MEM_INSTANCE 0x00000200 /* internal */
27750+#define NOUVEAU_MEM_NOTIFIER 0x00000400 /* internal */
27751+
27752+struct drm_nouveau_mem_alloc {
27753+ int flags;
27754+ int alignment;
27755+ uint64_t size; // in bytes
27756+ uint64_t offset;
27757+ drm_handle_t map_handle;
27758+};
27759+
27760+struct drm_nouveau_mem_free {
27761+ uint64_t offset;
27762+ int flags;
27763+};
27764+
27765+/* FIXME : maybe unify {GET,SET}PARAMs */
27766+#define NOUVEAU_GETPARAM_PCI_VENDOR 3
27767+#define NOUVEAU_GETPARAM_PCI_DEVICE 4
27768+#define NOUVEAU_GETPARAM_BUS_TYPE 5
27769+#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
27770+#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
27771+#define NOUVEAU_GETPARAM_FB_SIZE 8
27772+#define NOUVEAU_GETPARAM_AGP_SIZE 9
27773+#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
27774+#define NOUVEAU_GETPARAM_CHIPSET_ID 11
27775+struct drm_nouveau_getparam {
27776+ uint64_t param;
27777+ uint64_t value;
27778+};
27779+
27780+#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
27781+#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2
27782+struct drm_nouveau_setparam {
27783+ uint64_t param;
27784+ uint64_t value;
27785+};
27786+
27787+enum nouveau_card_type {
27788+ NV_UNKNOWN =0,
27789+ NV_04 =4,
27790+ NV_05 =5,
27791+ NV_10 =10,
27792+ NV_11 =11,
27793+ NV_15 =11,
27794+ NV_17 =17,
27795+ NV_20 =20,
27796+ NV_25 =20,
27797+ NV_30 =30,
27798+ NV_34 =30,
27799+ NV_40 =40,
27800+ NV_44 =44,
27801+ NV_50 =50,
27802+ NV_LAST =0xffff,
27803+};
27804+
27805+enum nouveau_bus_type {
27806+ NV_AGP =0,
27807+ NV_PCI =1,
27808+ NV_PCIE =2,
27809+};
27810+
27811+#define NOUVEAU_MAX_SAREA_CLIPRECTS 16
27812+
27813+struct drm_nouveau_sarea {
27814+ /* the cliprects */
27815+ struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
27816+ unsigned int nbox;
27817+};
27818+
27819+#define DRM_NOUVEAU_CARD_INIT 0x00
27820+#define DRM_NOUVEAU_GETPARAM 0x01
27821+#define DRM_NOUVEAU_SETPARAM 0x02
27822+#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
27823+#define DRM_NOUVEAU_CHANNEL_FREE 0x04
27824+#define DRM_NOUVEAU_GROBJ_ALLOC 0x05
27825+#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
27826+#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
27827+#define DRM_NOUVEAU_MEM_ALLOC 0x08
27828+#define DRM_NOUVEAU_MEM_FREE 0x09
27829+
27830+#endif /* __NOUVEAU_DRM_H__ */
27831+
27832Index: git/shared-core/nouveau_drv.h
27833===================================================================
27834--- /dev/null 1970-01-01 00:00:00.000000000 +0000
27835+++ git/shared-core/nouveau_drv.h 2008-12-12 17:35:22.000000000 +0000
27836@@ -0,0 +1,584 @@
27837+/*
27838+ * Copyright 2005 Stephane Marchesin.
27839+ * All Rights Reserved.
27840+ *
27841+ * Permission is hereby granted, free of charge, to any person obtaining a
27842+ * copy of this software and associated documentation files (the "Software"),
27843+ * to deal in the Software without restriction, including without limitation
27844+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
27845+ * and/or sell copies of the Software, and to permit persons to whom the
27846+ * Software is furnished to do so, subject to the following conditions:
27847+ *
27848+ * The above copyright notice and this permission notice (including the next
27849+ * paragraph) shall be included in all copies or substantial portions of the
27850+ * Software.
27851+ *
27852+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27853+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27854+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27855+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27856+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27857+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27858+ * OTHER DEALINGS IN THE SOFTWARE.
27859+ */
27860+
27861+#ifndef __NOUVEAU_DRV_H__
27862+#define __NOUVEAU_DRV_H__
27863+
27864+#define DRIVER_AUTHOR "Stephane Marchesin"
27865+#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
27866+
27867+#define DRIVER_NAME "nouveau"
27868+#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
27869+#define DRIVER_DATE "20060213"
27870+
27871+#define DRIVER_MAJOR 0
27872+#define DRIVER_MINOR 0
27873+#define DRIVER_PATCHLEVEL 10
27874+
27875+#define NOUVEAU_FAMILY 0x0000FFFF
27876+#define NOUVEAU_FLAGS 0xFFFF0000
27877+
27878+#include "nouveau_drm.h"
27879+#include "nouveau_reg.h"
27880+
27881+struct mem_block {
27882+ struct mem_block *next;
27883+ struct mem_block *prev;
27884+ uint64_t start;
27885+ uint64_t size;
27886+ struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
27887+ int flags;
27888+ drm_local_map_t *map;
27889+ drm_handle_t map_handle;
27890+};
27891+
27892+enum nouveau_flags {
27893+ NV_NFORCE =0x10000000,
27894+ NV_NFORCE2 =0x20000000
27895+};
27896+
27897+#define NVOBJ_ENGINE_SW 0
27898+#define NVOBJ_ENGINE_GR 1
27899+#define NVOBJ_ENGINE_INT 0xdeadbeef
27900+
27901+#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
27902+#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
27903+#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
27904+#define NVOBJ_FLAG_FAKE (1 << 3)
27905+struct nouveau_gpuobj {
27906+ struct list_head list;
27907+
27908+ int im_channel;
27909+ struct mem_block *im_pramin;
27910+ struct mem_block *im_backing;
27911+ int im_bound;
27912+
27913+ uint32_t flags;
27914+ int refcount;
27915+
27916+ uint32_t engine;
27917+ uint32_t class;
27918+
27919+ void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
27920+ void *priv;
27921+};
27922+
27923+struct nouveau_gpuobj_ref {
27924+ struct list_head list;
27925+
27926+ struct nouveau_gpuobj *gpuobj;
27927+ uint32_t instance;
27928+
27929+ int channel;
27930+ int handle;
27931+};
27932+
27933+struct nouveau_channel
27934+{
27935+ struct drm_device *dev;
27936+ int id;
27937+
27938+ /* owner of this fifo */
27939+ struct drm_file *file_priv;
27940+ /* mapping of the fifo itself */
27941+ drm_local_map_t *map;
27942+ /* mapping of the regs controling the fifo */
27943+ drm_local_map_t *regs;
27944+
27945+ /* DMA push buffer */
27946+ struct nouveau_gpuobj_ref *pushbuf;
27947+ struct mem_block *pushbuf_mem;
27948+ uint32_t pushbuf_base;
27949+
27950+ /* Notifier memory */
27951+ struct mem_block *notifier_block;
27952+ struct mem_block *notifier_heap;
27953+ drm_local_map_t *notifier_map;
27954+
27955+ /* PFIFO context */
27956+ struct nouveau_gpuobj_ref *ramfc;
27957+
27958+ /* PGRAPH context */
27959+ struct nouveau_gpuobj_ref *ramin_grctx;
27960+ uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */
27961+
27962+ /* NV50 VM */
27963+ struct nouveau_gpuobj *vm_pd;
27964+ struct nouveau_gpuobj_ref *vm_gart_pt;
27965+
27966+ /* Objects */
27967+ struct nouveau_gpuobj_ref *ramin; /* Private instmem */
27968+ struct mem_block *ramin_heap; /* Private PRAMIN heap */
27969+ struct nouveau_gpuobj_ref *ramht; /* Hash table */
27970+ struct list_head ramht_refs; /* Objects referenced by RAMHT */
27971+};
27972+
27973+struct nouveau_drm_channel {
27974+ struct nouveau_channel *chan;
27975+
27976+ /* DMA state */
27977+ int max, put, cur, free;
27978+ int push_free;
27979+ volatile uint32_t *pushbuf;
27980+
27981+ /* Notifiers */
27982+ uint32_t notify0_offset;
27983+
27984+ /* Buffer moves */
27985+ uint32_t m2mf_dma_source;
27986+ uint32_t m2mf_dma_destin;
27987+};
27988+
27989+struct nouveau_config {
27990+ struct {
27991+ int location;
27992+ int size;
27993+ } cmdbuf;
27994+};
27995+
27996+struct nouveau_instmem_engine {
27997+ void *priv;
27998+
27999+ int (*init)(struct drm_device *dev);
28000+ void (*takedown)(struct drm_device *dev);
28001+
28002+ int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
28003+ uint32_t *size);
28004+ void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
28005+ int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
28006+ int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
28007+};
28008+
28009+struct nouveau_mc_engine {
28010+ int (*init)(struct drm_device *dev);
28011+ void (*takedown)(struct drm_device *dev);
28012+};
28013+
28014+struct nouveau_timer_engine {
28015+ int (*init)(struct drm_device *dev);
28016+ void (*takedown)(struct drm_device *dev);
28017+ uint64_t (*read)(struct drm_device *dev);
28018+};
28019+
28020+struct nouveau_fb_engine {
28021+ int (*init)(struct drm_device *dev);
28022+ void (*takedown)(struct drm_device *dev);
28023+};
28024+
28025+struct nouveau_fifo_engine {
28026+ void *priv;
28027+
28028+ int (*init)(struct drm_device *);
28029+ void (*takedown)(struct drm_device *);
28030+
28031+ int (*create_context)(struct nouveau_channel *);
28032+ void (*destroy_context)(struct nouveau_channel *);
28033+ int (*load_context)(struct nouveau_channel *);
28034+ int (*save_context)(struct nouveau_channel *);
28035+};
28036+
28037+struct nouveau_pgraph_engine {
28038+ int (*init)(struct drm_device *);
28039+ void (*takedown)(struct drm_device *);
28040+
28041+ int (*create_context)(struct nouveau_channel *);
28042+ void (*destroy_context)(struct nouveau_channel *);
28043+ int (*load_context)(struct nouveau_channel *);
28044+ int (*save_context)(struct nouveau_channel *);
28045+};
28046+
28047+struct nouveau_engine {
28048+ struct nouveau_instmem_engine instmem;
28049+ struct nouveau_mc_engine mc;
28050+ struct nouveau_timer_engine timer;
28051+ struct nouveau_fb_engine fb;
28052+ struct nouveau_pgraph_engine graph;
28053+ struct nouveau_fifo_engine fifo;
28054+};
28055+
28056+struct drm_nouveau_private {
28057+ enum {
28058+ NOUVEAU_CARD_INIT_DOWN,
28059+ NOUVEAU_CARD_INIT_DONE,
28060+ NOUVEAU_CARD_INIT_FAILED
28061+ } init_state;
28062+
28063+ /* the card type, takes NV_* as values */
28064+ int card_type;
28065+ /* exact chipset, derived from NV_PMC_BOOT_0 */
28066+ int chipset;
28067+ int flags;
28068+
28069+ drm_local_map_t *mmio;
28070+ drm_local_map_t *fb;
28071+ drm_local_map_t *ramin; /* NV40 onwards */
28072+
28073+ int fifo_alloc_count;
28074+ struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
28075+
28076+ struct nouveau_engine Engine;
28077+ struct nouveau_drm_channel channel;
28078+
28079+ /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
28080+ struct nouveau_gpuobj *ramht;
28081+ uint32_t ramin_rsvd_vram;
28082+ uint32_t ramht_offset;
28083+ uint32_t ramht_size;
28084+ uint32_t ramht_bits;
28085+ uint32_t ramfc_offset;
28086+ uint32_t ramfc_size;
28087+ uint32_t ramro_offset;
28088+ uint32_t ramro_size;
28089+
28090+ /* base physical adresses */
28091+ uint64_t fb_phys;
28092+ uint64_t fb_available_size;
28093+
28094+ struct {
28095+ enum {
28096+ NOUVEAU_GART_NONE = 0,
28097+ NOUVEAU_GART_AGP,
28098+ NOUVEAU_GART_SGDMA
28099+ } type;
28100+ uint64_t aper_base;
28101+ uint64_t aper_size;
28102+
28103+ struct nouveau_gpuobj *sg_ctxdma;
28104+ struct page *sg_dummy_page;
28105+ dma_addr_t sg_dummy_bus;
28106+
28107+ /* nottm hack */
28108+ struct drm_ttm_backend *sg_be;
28109+ unsigned long sg_handle;
28110+ } gart_info;
28111+
28112+ /* the mtrr covering the FB */
28113+ int fb_mtrr;
28114+
28115+ struct mem_block *agp_heap;
28116+ struct mem_block *fb_heap;
28117+ struct mem_block *fb_nomap_heap;
28118+ struct mem_block *ramin_heap;
28119+ struct mem_block *pci_heap;
28120+
28121+ /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
28122+ uint32_t ctx_table_size;
28123+ struct nouveau_gpuobj_ref *ctx_table;
28124+
28125+ struct nouveau_config config;
28126+
28127+ struct list_head gpuobj_list;
28128+};
28129+
28130+#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
28131+ struct drm_nouveau_private *nv = dev->dev_private; \
28132+ if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
28133+ DRM_ERROR("called without init\n"); \
28134+ return -EINVAL; \
28135+ } \
28136+} while(0)
28137+
28138+#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
28139+ struct drm_nouveau_private *nv = dev->dev_private; \
28140+ if (!nouveau_fifo_owner(dev, (cl), (id))) { \
28141+ DRM_ERROR("pid %d doesn't own channel %d\n", \
28142+ DRM_CURRENTPID, (id)); \
28143+ return -EPERM; \
28144+ } \
28145+ (ch) = nv->fifos[(id)]; \
28146+} while(0)
28147+
28148+/* nouveau_state.c */
28149+extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
28150+extern int nouveau_load(struct drm_device *, unsigned long flags);
28151+extern int nouveau_firstopen(struct drm_device *);
28152+extern void nouveau_lastclose(struct drm_device *);
28153+extern int nouveau_unload(struct drm_device *);
28154+extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
28155+ struct drm_file *);
28156+extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
28157+ struct drm_file *);
28158+extern void nouveau_wait_for_idle(struct drm_device *);
28159+extern int nouveau_card_init(struct drm_device *);
28160+extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
28161+ struct drm_file *);
28162+
28163+/* nouveau_mem.c */
28164+extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
28165+ uint64_t size);
28166+extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
28167+ uint64_t size, int align2,
28168+ struct drm_file *);
28169+extern void nouveau_mem_takedown(struct mem_block **heap);
28170+extern void nouveau_mem_free_block(struct mem_block *);
28171+extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
28172+extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
28173+extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
28174+ struct drm_file *);
28175+extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
28176+ struct drm_file *);
28177+extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
28178+ int alignment, uint64_t size,
28179+ int flags, struct drm_file *);
28180+extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
28181+extern int nouveau_mem_init(struct drm_device *);
28182+extern void nouveau_mem_close(struct drm_device *);
28183+
28184+/* nouveau_notifier.c */
28185+extern int nouveau_notifier_init_channel(struct nouveau_channel *);
28186+extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
28187+extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
28188+ int cout, uint32_t *offset);
28189+extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
28190+ struct drm_file *);
28191+extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
28192+ struct drm_file *);
28193+
28194+/* nouveau_fifo.c */
28195+extern int nouveau_fifo_init(struct drm_device *);
28196+extern int nouveau_fifo_number(struct drm_device *);
28197+extern int nouveau_fifo_ctx_size(struct drm_device *);
28198+extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
28199+extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
28200+ int channel);
28201+extern int nouveau_fifo_alloc(struct drm_device *dev,
28202+ struct nouveau_channel **chan,
28203+ struct drm_file *file_priv,
28204+ struct mem_block *pushbuf,
28205+ uint32_t fb_ctxdma, uint32_t tt_ctxdma);
28206+extern void nouveau_fifo_free(struct nouveau_channel *);
28207+
28208+/* nouveau_object.c */
28209+extern int nouveau_gpuobj_early_init(struct drm_device *);
28210+extern int nouveau_gpuobj_init(struct drm_device *);
28211+extern void nouveau_gpuobj_takedown(struct drm_device *);
28212+extern void nouveau_gpuobj_late_takedown(struct drm_device *);
28213+extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
28214+ uint32_t vram_h, uint32_t tt_h);
28215+extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
28216+extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
28217+ int size, int align, uint32_t flags,
28218+ struct nouveau_gpuobj **);
28219+extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
28220+extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
28221+ uint32_t handle, struct nouveau_gpuobj *,
28222+ struct nouveau_gpuobj_ref **);
28223+extern int nouveau_gpuobj_ref_del(struct drm_device *,
28224+ struct nouveau_gpuobj_ref **);
28225+extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
28226+ struct nouveau_gpuobj_ref **ref_ret);
28227+extern int nouveau_gpuobj_new_ref(struct drm_device *,
28228+ struct nouveau_channel *alloc_chan,
28229+ struct nouveau_channel *ref_chan,
28230+ uint32_t handle, int size, int align,
28231+ uint32_t flags, struct nouveau_gpuobj_ref **);
28232+extern int nouveau_gpuobj_new_fake(struct drm_device *,
28233+ uint32_t p_offset, uint32_t b_offset,
28234+ uint32_t size, uint32_t flags,
28235+ struct nouveau_gpuobj **,
28236+ struct nouveau_gpuobj_ref**);
28237+extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
28238+ uint64_t offset, uint64_t size, int access,
28239+ int target, struct nouveau_gpuobj **);
28240+extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
28241+ uint64_t offset, uint64_t size,
28242+ int access, struct nouveau_gpuobj **,
28243+ uint32_t *o_ret);
28244+extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
28245+ struct nouveau_gpuobj **);
28246+extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
28247+ struct drm_file *);
28248+extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
28249+ struct drm_file *);
28250+
28251+/* nouveau_irq.c */
28252+extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
28253+extern void nouveau_irq_preinstall(struct drm_device *);
28254+extern void nouveau_irq_postinstall(struct drm_device *);
28255+extern void nouveau_irq_uninstall(struct drm_device *);
28256+
28257+/* nouveau_sgdma.c */
28258+extern int nouveau_sgdma_init(struct drm_device *);
28259+extern void nouveau_sgdma_takedown(struct drm_device *);
28260+extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
28261+ uint32_t *page);
28262+extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
28263+extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
28264+extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
28265+
28266+/* nouveau_dma.c */
28267+extern int nouveau_dma_channel_init(struct drm_device *);
28268+extern void nouveau_dma_channel_takedown(struct drm_device *);
28269+extern int nouveau_dma_wait(struct drm_device *, int size);
28270+
28271+/* nv04_fb.c */
28272+extern int nv04_fb_init(struct drm_device *);
28273+extern void nv04_fb_takedown(struct drm_device *);
28274+
28275+/* nv10_fb.c */
28276+extern int nv10_fb_init(struct drm_device *);
28277+extern void nv10_fb_takedown(struct drm_device *);
28278+
28279+/* nv40_fb.c */
28280+extern int nv40_fb_init(struct drm_device *);
28281+extern void nv40_fb_takedown(struct drm_device *);
28282+
28283+/* nv04_fifo.c */
28284+extern int nv04_fifo_create_context(struct nouveau_channel *);
28285+extern void nv04_fifo_destroy_context(struct nouveau_channel *);
28286+extern int nv04_fifo_load_context(struct nouveau_channel *);
28287+extern int nv04_fifo_save_context(struct nouveau_channel *);
28288+
28289+/* nv10_fifo.c */
28290+extern int nv10_fifo_create_context(struct nouveau_channel *);
28291+extern void nv10_fifo_destroy_context(struct nouveau_channel *);
28292+extern int nv10_fifo_load_context(struct nouveau_channel *);
28293+extern int nv10_fifo_save_context(struct nouveau_channel *);
28294+
28295+/* nv40_fifo.c */
28296+extern int nv40_fifo_init(struct drm_device *);
28297+extern int nv40_fifo_create_context(struct nouveau_channel *);
28298+extern void nv40_fifo_destroy_context(struct nouveau_channel *);
28299+extern int nv40_fifo_load_context(struct nouveau_channel *);
28300+extern int nv40_fifo_save_context(struct nouveau_channel *);
28301+
28302+/* nv50_fifo.c */
28303+extern int nv50_fifo_init(struct drm_device *);
28304+extern void nv50_fifo_takedown(struct drm_device *);
28305+extern int nv50_fifo_create_context(struct nouveau_channel *);
28306+extern void nv50_fifo_destroy_context(struct nouveau_channel *);
28307+extern int nv50_fifo_load_context(struct nouveau_channel *);
28308+extern int nv50_fifo_save_context(struct nouveau_channel *);
28309+
28310+/* nv04_graph.c */
28311+extern void nouveau_nv04_context_switch(struct drm_device *);
28312+extern int nv04_graph_init(struct drm_device *);
28313+extern void nv04_graph_takedown(struct drm_device *);
28314+extern int nv04_graph_create_context(struct nouveau_channel *);
28315+extern void nv04_graph_destroy_context(struct nouveau_channel *);
28316+extern int nv04_graph_load_context(struct nouveau_channel *);
28317+extern int nv04_graph_save_context(struct nouveau_channel *);
28318+
28319+/* nv10_graph.c */
28320+extern void nouveau_nv10_context_switch(struct drm_device *);
28321+extern int nv10_graph_init(struct drm_device *);
28322+extern void nv10_graph_takedown(struct drm_device *);
28323+extern int nv10_graph_create_context(struct nouveau_channel *);
28324+extern void nv10_graph_destroy_context(struct nouveau_channel *);
28325+extern int nv10_graph_load_context(struct nouveau_channel *);
28326+extern int nv10_graph_save_context(struct nouveau_channel *);
28327+
28328+/* nv20_graph.c */
28329+extern void nouveau_nv20_context_switch(struct drm_device *);
28330+extern int nv20_graph_init(struct drm_device *);
28331+extern void nv20_graph_takedown(struct drm_device *);
28332+extern int nv20_graph_create_context(struct nouveau_channel *);
28333+extern void nv20_graph_destroy_context(struct nouveau_channel *);
28334+extern int nv20_graph_load_context(struct nouveau_channel *);
28335+extern int nv20_graph_save_context(struct nouveau_channel *);
28336+
28337+/* nv30_graph.c */
28338+extern int nv30_graph_init(struct drm_device *);
28339+extern void nv30_graph_takedown(struct drm_device *);
28340+extern int nv30_graph_create_context(struct nouveau_channel *);
28341+extern void nv30_graph_destroy_context(struct nouveau_channel *);
28342+extern int nv30_graph_load_context(struct nouveau_channel *);
28343+extern int nv30_graph_save_context(struct nouveau_channel *);
28344+
28345+/* nv40_graph.c */
28346+extern int nv40_graph_init(struct drm_device *);
28347+extern void nv40_graph_takedown(struct drm_device *);
28348+extern int nv40_graph_create_context(struct nouveau_channel *);
28349+extern void nv40_graph_destroy_context(struct nouveau_channel *);
28350+extern int nv40_graph_load_context(struct nouveau_channel *);
28351+extern int nv40_graph_save_context(struct nouveau_channel *);
28352+
28353+/* nv50_graph.c */
28354+extern int nv50_graph_init(struct drm_device *);
28355+extern void nv50_graph_takedown(struct drm_device *);
28356+extern int nv50_graph_create_context(struct nouveau_channel *);
28357+extern void nv50_graph_destroy_context(struct nouveau_channel *);
28358+extern int nv50_graph_load_context(struct nouveau_channel *);
28359+extern int nv50_graph_save_context(struct nouveau_channel *);
28360+
28361+/* nv04_instmem.c */
28362+extern int nv04_instmem_init(struct drm_device *);
28363+extern void nv04_instmem_takedown(struct drm_device *);
28364+extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
28365+ uint32_t *size);
28366+extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
28367+extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
28368+extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
28369+
28370+/* nv50_instmem.c */
28371+extern int nv50_instmem_init(struct drm_device *);
28372+extern void nv50_instmem_takedown(struct drm_device *);
28373+extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
28374+ uint32_t *size);
28375+extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
28376+extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
28377+extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
28378+
28379+/* nv04_mc.c */
28380+extern int nv04_mc_init(struct drm_device *);
28381+extern void nv04_mc_takedown(struct drm_device *);
28382+
28383+/* nv40_mc.c */
28384+extern int nv40_mc_init(struct drm_device *);
28385+extern void nv40_mc_takedown(struct drm_device *);
28386+
28387+/* nv50_mc.c */
28388+extern int nv50_mc_init(struct drm_device *);
28389+extern void nv50_mc_takedown(struct drm_device *);
28390+
28391+/* nv04_timer.c */
28392+extern int nv04_timer_init(struct drm_device *);
28393+extern uint64_t nv04_timer_read(struct drm_device *);
28394+extern void nv04_timer_takedown(struct drm_device *);
28395+
28396+extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
28397+ unsigned long arg);
28398+
28399+#if defined(__powerpc__)
28400+#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
28401+#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
28402+#else
28403+#define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
28404+#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
28405+#endif
28406+
28407+/* PRAMIN access */
28408+#if defined(__powerpc__)
28409+#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
28410+#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
28411+#else
28412+#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
28413+#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
28414+#endif
28415+
28416+#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
28417+#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
28418+
28419+#endif /* __NOUVEAU_DRV_H__ */
28420+
28421Index: git/shared-core/nouveau_fifo.c
28422===================================================================
28423--- /dev/null 1970-01-01 00:00:00.000000000 +0000
28424+++ git/shared-core/nouveau_fifo.c 2008-12-12 17:35:22.000000000 +0000
28425@@ -0,0 +1,554 @@
28426+/*
28427+ * Copyright 2005-2006 Stephane Marchesin
28428+ * All Rights Reserved.
28429+ *
28430+ * Permission is hereby granted, free of charge, to any person obtaining a
28431+ * copy of this software and associated documentation files (the "Software"),
28432+ * to deal in the Software without restriction, including without limitation
28433+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
28434+ * and/or sell copies of the Software, and to permit persons to whom the
28435+ * Software is furnished to do so, subject to the following conditions:
28436+ *
28437+ * The above copyright notice and this permission notice (including the next
28438+ * paragraph) shall be included in all copies or substantial portions of the
28439+ * Software.
28440+ *
28441+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28442+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
28443+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28444+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
28445+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28446+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28447+ * DEALINGS IN THE SOFTWARE.
28448+ */
28449+
28450+#include "drmP.h"
28451+#include "drm.h"
28452+#include "nouveau_drv.h"
28453+#include "nouveau_drm.h"
28454+
28455+
28456+/* returns the number of hw fifos */
28457+int nouveau_fifo_number(struct drm_device *dev)
28458+{
28459+ struct drm_nouveau_private *dev_priv=dev->dev_private;
28460+ switch(dev_priv->card_type)
28461+ {
28462+ case NV_04:
28463+ case NV_05:
28464+ return 16;
28465+ case NV_50:
28466+ return 128;
28467+ default:
28468+ return 32;
28469+ }
28470+}
28471+
28472+/* returns the size of fifo context */
28473+int nouveau_fifo_ctx_size(struct drm_device *dev)
28474+{
28475+ struct drm_nouveau_private *dev_priv=dev->dev_private;
28476+
28477+ if (dev_priv->card_type >= NV_40)
28478+ return 128;
28479+ else if (dev_priv->card_type >= NV_17)
28480+ return 64;
28481+ else
28482+ return 32;
28483+}
28484+
28485+/***********************************
28486+ * functions doing the actual work
28487+ ***********************************/
28488+
28489+/* voir nv_xaa.c : NVResetGraphics
28490+ * mémoire mappée par nv_driver.c : NVMapMem
28491+ * voir nv_driver.c : NVPreInit
28492+ */
28493+
28494+static int nouveau_fifo_instmem_configure(struct drm_device *dev)
28495+{
28496+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28497+
28498+ NV_WRITE(NV03_PFIFO_RAMHT,
28499+ (0x03 << 24) /* search 128 */ |
28500+ ((dev_priv->ramht_bits - 9) << 16) |
28501+ (dev_priv->ramht_offset >> 8)
28502+ );
28503+
28504+ NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
28505+
28506+ switch(dev_priv->card_type)
28507+ {
28508+ case NV_50:
28509+ case NV_40:
28510+ switch (dev_priv->chipset) {
28511+ case 0x47:
28512+ case 0x49:
28513+ case 0x4b:
28514+ NV_WRITE(0x2230, 1);
28515+ break;
28516+ default:
28517+ break;
28518+ }
28519+ NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
28520+ break;
28521+ case NV_44:
28522+ NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
28523+ (2 << 16));
28524+ break;
28525+ case NV_30:
28526+ case NV_20:
28527+ case NV_17:
28528+ NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
28529+ (1 << 16) /* 64 Bytes entry*/);
28530+ /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
28531+ break;
28532+ case NV_11:
28533+ case NV_10:
28534+ case NV_04:
28535+ NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
28536+ break;
28537+ }
28538+
28539+ return 0;
28540+}
28541+
28542+int nouveau_fifo_init(struct drm_device *dev)
28543+{
28544+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28545+ int ret;
28546+
28547+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
28548+ ~NV_PMC_ENABLE_PFIFO);
28549+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
28550+ NV_PMC_ENABLE_PFIFO);
28551+
28552+ /* Enable PFIFO error reporting */
28553+ NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
28554+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
28555+
28556+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
28557+
28558+ ret = nouveau_fifo_instmem_configure(dev);
28559+ if (ret) {
28560+ DRM_ERROR("Failed to configure instance memory\n");
28561+ return ret;
28562+ }
28563+
28564+ /* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
28565+
28566+ DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
28567+
28568+ /* All channels into PIO mode */
28569+ NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
28570+
28571+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
28572+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
28573+ /* Channel 0 active, PIO mode */
28574+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
28575+ /* PUT and GET to 0 */
28576+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
28577+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
28578+ /* No cmdbuf object */
28579+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
28580+ NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
28581+ NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
28582+ NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
28583+ NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
28584+ NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
28585+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
28586+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
28587+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
28588+
28589+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
28590+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
28591+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
28592+#ifdef __BIG_ENDIAN
28593+ NV_PFIFO_CACHE1_BIG_ENDIAN |
28594+#endif
28595+ 0x00000000);
28596+
28597+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
28598+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
28599+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
28600+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
28601+
28602+ /* FIXME on NV04 */
28603+ if (dev_priv->card_type >= NV_10) {
28604+ NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
28605+ NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
28606+ if (dev_priv->card_type >= NV_40)
28607+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
28608+ else
28609+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
28610+ } else {
28611+ NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
28612+ NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
28613+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
28614+ }
28615+
28616+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
28617+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
28618+ return 0;
28619+}
28620+
28621+static int
28622+nouveau_fifo_pushbuf_ctxdma_init(struct nouveau_channel *chan)
28623+{
28624+ struct drm_device *dev = chan->dev;
28625+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28626+ struct mem_block *pb = chan->pushbuf_mem;
28627+ struct nouveau_gpuobj *pushbuf = NULL;
28628+ int ret;
28629+
28630+ if (pb->flags & NOUVEAU_MEM_AGP) {
28631+ ret = nouveau_gpuobj_gart_dma_new(chan, pb->start, pb->size,
28632+ NV_DMA_ACCESS_RO,
28633+ &pushbuf,
28634+ &chan->pushbuf_base);
28635+ } else
28636+ if (pb->flags & NOUVEAU_MEM_PCI) {
28637+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
28638+ pb->start, pb->size,
28639+ NV_DMA_ACCESS_RO,
28640+ NV_DMA_TARGET_PCI_NONLINEAR,
28641+ &pushbuf);
28642+ chan->pushbuf_base = 0;
28643+ } else if (dev_priv->card_type != NV_04) {
28644+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
28645+ pb->start, pb->size,
28646+ NV_DMA_ACCESS_RO,
28647+ NV_DMA_TARGET_VIDMEM, &pushbuf);
28648+ chan->pushbuf_base = 0;
28649+ } else {
28650+ /* NV04 cmdbuf hack, from original ddx.. not sure of it's
28651+ * exact reason for existing :) PCI access to cmdbuf in
28652+ * VRAM.
28653+ */
28654+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
28655+ pb->start +
28656+ drm_get_resource_start(dev, 1),
28657+ pb->size, NV_DMA_ACCESS_RO,
28658+ NV_DMA_TARGET_PCI, &pushbuf);
28659+ chan->pushbuf_base = 0;
28660+ }
28661+
28662+ if ((ret = nouveau_gpuobj_ref_add(dev, chan, 0, pushbuf,
28663+ &chan->pushbuf))) {
28664+ DRM_ERROR("Error referencing push buffer ctxdma: %d\n", ret);
28665+ if (pushbuf != dev_priv->gart_info.sg_ctxdma)
28666+ nouveau_gpuobj_del(dev, &pushbuf);
28667+ return ret;
28668+ }
28669+
28670+ return 0;
28671+}
28672+
28673+static struct mem_block *
28674+nouveau_fifo_user_pushbuf_alloc(struct drm_device *dev)
28675+{
28676+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28677+ struct nouveau_config *config = &dev_priv->config;
28678+ struct mem_block *pb;
28679+ int pb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
28680+
28681+ /* Defaults for unconfigured values */
28682+ if (!config->cmdbuf.location)
28683+ config->cmdbuf.location = NOUVEAU_MEM_FB;
28684+ if (!config->cmdbuf.size || config->cmdbuf.size < pb_min_size)
28685+ config->cmdbuf.size = pb_min_size;
28686+
28687+ pb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
28688+ config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
28689+ (struct drm_file *)-2);
28690+ if (!pb)
28691+ DRM_ERROR("Couldn't allocate DMA push buffer.\n");
28692+
28693+ return pb;
28694+}
28695+
28696+/* allocates and initializes a fifo for user space consumption */
28697+int
28698+nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
28699+ struct drm_file *file_priv, struct mem_block *pushbuf,
28700+ uint32_t vram_handle, uint32_t tt_handle)
28701+{
28702+ int ret;
28703+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28704+ struct nouveau_engine *engine = &dev_priv->Engine;
28705+ struct nouveau_channel *chan;
28706+ int channel;
28707+
28708+ /*
28709+ * Alright, here is the full story
28710+ * Nvidia cards have multiple hw fifo contexts (praise them for that,
28711+ * no complicated crash-prone context switches)
28712+ * We allocate a new context for each app and let it write to it directly
28713+ * (woo, full userspace command submission !)
28714+ * When there are no more contexts, you lost
28715+ */
28716+ for(channel=0; channel<nouveau_fifo_number(dev); channel++) {
28717+ if (dev_priv->fifos[channel] == NULL)
28718+ break;
28719+ }
28720+ /* no more fifos. you lost. */
28721+ if (channel==nouveau_fifo_number(dev))
28722+ return -EINVAL;
28723+
28724+ dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
28725+ DRM_MEM_DRIVER);
28726+ if (!dev_priv->fifos[channel])
28727+ return -ENOMEM;
28728+ dev_priv->fifo_alloc_count++;
28729+ chan = dev_priv->fifos[channel];
28730+ chan->dev = dev;
28731+ chan->id = channel;
28732+ chan->file_priv = file_priv;
28733+ chan->pushbuf_mem = pushbuf;
28734+
28735+ DRM_INFO("Allocating FIFO number %d\n", channel);
28736+
28737+ /* Allocate space for per-channel fixed notifier memory */
28738+ ret = nouveau_notifier_init_channel(chan);
28739+ if (ret) {
28740+ nouveau_fifo_free(chan);
28741+ return ret;
28742+ }
28743+
28744+ /* Setup channel's default objects */
28745+ ret = nouveau_gpuobj_channel_init(chan, vram_handle, tt_handle);
28746+ if (ret) {
28747+ nouveau_fifo_free(chan);
28748+ return ret;
28749+ }
28750+
28751+ /* Create a dma object for the push buffer */
28752+ ret = nouveau_fifo_pushbuf_ctxdma_init(chan);
28753+ if (ret) {
28754+ nouveau_fifo_free(chan);
28755+ return ret;
28756+ }
28757+
28758+ nouveau_wait_for_idle(dev);
28759+
28760+ /* disable the fifo caches */
28761+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
28762+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
28763+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
28764+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
28765+
28766+ /* Create a graphics context for new channel */
28767+ ret = engine->graph.create_context(chan);
28768+ if (ret) {
28769+ nouveau_fifo_free(chan);
28770+ return ret;
28771+ }
28772+
28773+ /* Construct inital RAMFC for new channel */
28774+ ret = engine->fifo.create_context(chan);
28775+ if (ret) {
28776+ nouveau_fifo_free(chan);
28777+ return ret;
28778+ }
28779+
28780+ /* setup channel's default get/put values */
28781+ if (dev_priv->card_type < NV_50) {
28782+ NV_WRITE(NV03_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
28783+ NV_WRITE(NV03_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
28784+ } else {
28785+ NV_WRITE(NV50_FIFO_REGS_DMAPUT(channel), chan->pushbuf_base);
28786+ NV_WRITE(NV50_FIFO_REGS_DMAGET(channel), chan->pushbuf_base);
28787+ }
28788+
28789+ /* If this is the first channel, setup PFIFO ourselves. For any
28790+ * other case, the GPU will handle this when it switches contexts.
28791+ */
28792+ if (dev_priv->fifo_alloc_count == 1) {
28793+ ret = engine->fifo.load_context(chan);
28794+ if (ret) {
28795+ nouveau_fifo_free(chan);
28796+ return ret;
28797+ }
28798+
28799+ ret = engine->graph.load_context(chan);
28800+ if (ret) {
28801+ nouveau_fifo_free(chan);
28802+ return ret;
28803+ }
28804+ }
28805+
28806+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH,
28807+ NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
28808+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
28809+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
28810+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
28811+
28812+ /* reenable the fifo caches */
28813+ NV_WRITE(NV03_PFIFO_CACHES, 1);
28814+
28815+ DRM_INFO("%s: initialised FIFO %d\n", __func__, channel);
28816+ *chan_ret = chan;
28817+ return 0;
28818+}
28819+
28820+/* stops a fifo */
28821+void nouveau_fifo_free(struct nouveau_channel *chan)
28822+{
28823+ struct drm_device *dev = chan->dev;
28824+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28825+ struct nouveau_engine *engine = &dev_priv->Engine;
28826+
28827+ DRM_INFO("%s: freeing fifo %d\n", __func__, chan->id);
28828+
28829+ /* disable the fifo caches */
28830+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
28831+
28832+ // FIXME XXX needs more code
28833+
28834+ engine->fifo.destroy_context(chan);
28835+
28836+ /* Cleanup PGRAPH state */
28837+ engine->graph.destroy_context(chan);
28838+
28839+ /* reenable the fifo caches */
28840+ NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
28841+
28842+ /* Deallocate push buffer */
28843+ nouveau_gpuobj_ref_del(dev, &chan->pushbuf);
28844+ if (chan->pushbuf_mem) {
28845+ nouveau_mem_free(dev, chan->pushbuf_mem);
28846+ chan->pushbuf_mem = NULL;
28847+ }
28848+
28849+ /* Destroy objects belonging to the channel */
28850+ nouveau_gpuobj_channel_takedown(chan);
28851+
28852+ nouveau_notifier_takedown_channel(chan);
28853+
28854+ dev_priv->fifos[chan->id] = NULL;
28855+ dev_priv->fifo_alloc_count--;
28856+ drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
28857+}
28858+
28859+/* cleanups all the fifos from file_priv */
28860+void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
28861+{
28862+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28863+ int i;
28864+
28865+ DRM_DEBUG("clearing FIFO enables from file_priv\n");
28866+ for(i = 0; i < nouveau_fifo_number(dev); i++) {
28867+ struct nouveau_channel *chan = dev_priv->fifos[i];
28868+
28869+ if (chan && chan->file_priv == file_priv)
28870+ nouveau_fifo_free(chan);
28871+ }
28872+}
28873+
28874+int
28875+nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv,
28876+ int channel)
28877+{
28878+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28879+
28880+ if (channel >= nouveau_fifo_number(dev))
28881+ return 0;
28882+ if (dev_priv->fifos[channel] == NULL)
28883+ return 0;
28884+ return (dev_priv->fifos[channel]->file_priv == file_priv);
28885+}
28886+
28887+/***********************************
28888+ * ioctls wrapping the functions
28889+ ***********************************/
28890+
28891+static int nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
28892+ struct drm_file *file_priv)
28893+{
28894+ struct drm_nouveau_private *dev_priv = dev->dev_private;
28895+ struct drm_nouveau_channel_alloc *init = data;
28896+ struct drm_map_list *entry;
28897+ struct nouveau_channel *chan;
28898+ struct mem_block *pushbuf;
28899+ int res;
28900+
28901+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
28902+
28903+ if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
28904+ return -EINVAL;
28905+
28906+ pushbuf = nouveau_fifo_user_pushbuf_alloc(dev);
28907+ if (!pushbuf)
28908+ return -ENOMEM;
28909+
28910+ res = nouveau_fifo_alloc(dev, &chan, file_priv, pushbuf,
28911+ init->fb_ctxdma_handle,
28912+ init->tt_ctxdma_handle);
28913+ if (res)
28914+ return res;
28915+ init->channel = chan->id;
28916+ init->put_base = chan->pushbuf_base;
28917+
28918+ /* make the fifo available to user space */
28919+ /* first, the fifo control regs */
28920+ init->ctrl = dev_priv->mmio->offset;
28921+ if (dev_priv->card_type < NV_50) {
28922+ init->ctrl += NV03_FIFO_REGS(init->channel);
28923+ init->ctrl_size = NV03_FIFO_REGS_SIZE;
28924+ } else {
28925+ init->ctrl += NV50_FIFO_REGS(init->channel);
28926+ init->ctrl_size = NV50_FIFO_REGS_SIZE;
28927+ }
28928+ res = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
28929+ 0, &chan->regs);
28930+ if (res != 0)
28931+ return res;
28932+
28933+ entry = drm_find_matching_map(dev, chan->regs);
28934+ if (!entry)
28935+ return -EINVAL;
28936+ init->ctrl = entry->user_token;
28937+
28938+ /* pass back FIFO map info to the caller */
28939+ init->cmdbuf = chan->pushbuf_mem->map_handle;
28940+ init->cmdbuf_size = chan->pushbuf_mem->size;
28941+
28942+ /* and the notifier block */
28943+ init->notifier = chan->notifier_block->map_handle;
28944+ init->notifier_size = chan->notifier_block->size;
28945+
28946+ return 0;
28947+}
28948+
28949+static int nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
28950+ struct drm_file *file_priv)
28951+{
28952+ struct drm_nouveau_channel_free *cfree = data;
28953+ struct nouveau_channel *chan;
28954+
28955+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
28956+ NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(cfree->channel, file_priv, chan);
28957+
28958+ nouveau_fifo_free(chan);
28959+ return 0;
28960+}
28961+
28962+/***********************************
28963+ * finally, the ioctl table
28964+ ***********************************/
28965+
28966+struct drm_ioctl_desc nouveau_ioctls[] = {
28967+ DRM_IOCTL_DEF(DRM_NOUVEAU_CARD_INIT, nouveau_ioctl_card_init, DRM_AUTH),
28968+ DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
28969+ DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
28970+ DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
28971+ DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
28972+ DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
28973+ DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
28974+ DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
28975+ DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_ALLOC, nouveau_ioctl_mem_alloc, DRM_AUTH),
28976+ DRM_IOCTL_DEF(DRM_NOUVEAU_MEM_FREE, nouveau_ioctl_mem_free, DRM_AUTH),
28977+};
28978+
28979+int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
28980Index: git/shared-core/nouveau_irq.c
28981===================================================================
28982--- /dev/null 1970-01-01 00:00:00.000000000 +0000
28983+++ git/shared-core/nouveau_irq.c 2008-12-12 17:35:22.000000000 +0000
28984@@ -0,0 +1,430 @@
28985+/*
28986+ * Copyright (C) 2006 Ben Skeggs.
28987+ *
28988+ * All Rights Reserved.
28989+ *
28990+ * Permission is hereby granted, free of charge, to any person obtaining
28991+ * a copy of this software and associated documentation files (the
28992+ * "Software"), to deal in the Software without restriction, including
28993+ * without limitation the rights to use, copy, modify, merge, publish,
28994+ * distribute, sublicense, and/or sell copies of the Software, and to
28995+ * permit persons to whom the Software is furnished to do so, subject to
28996+ * the following conditions:
28997+ *
28998+ * The above copyright notice and this permission notice (including the
28999+ * next paragraph) shall be included in all copies or substantial
29000+ * portions of the Software.
29001+ *
29002+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29003+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29004+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
29005+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29006+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
29007+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
29008+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29009+ *
29010+ */
29011+
29012+/*
29013+ * Authors:
29014+ * Ben Skeggs <darktama@iinet.net.au>
29015+ */
29016+
29017+#include "drmP.h"
29018+#include "drm.h"
29019+#include "nouveau_drm.h"
29020+#include "nouveau_drv.h"
29021+#include "nouveau_reg.h"
29022+
29023+void nouveau_irq_preinstall(struct drm_device *dev)
29024+{
29025+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29026+
29027+ /* Master disable */
29028+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
29029+}
29030+
29031+void nouveau_irq_postinstall(struct drm_device *dev)
29032+{
29033+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29034+
29035+ /* Master enable */
29036+ NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
29037+}
29038+
29039+void nouveau_irq_uninstall(struct drm_device *dev)
29040+{
29041+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29042+
29043+ /* Master disable */
29044+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
29045+}
29046+
29047+static void nouveau_fifo_irq_handler(struct drm_device *dev)
29048+{
29049+ uint32_t status, chmode, chstat, channel;
29050+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29051+
29052+ status = NV_READ(NV03_PFIFO_INTR_0);
29053+ if (!status)
29054+ return;
29055+ chmode = NV_READ(NV04_PFIFO_MODE);
29056+ chstat = NV_READ(NV04_PFIFO_DMA);
29057+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
29058+
29059+ if (status & NV_PFIFO_INTR_CACHE_ERROR) {
29060+ uint32_t c1get, c1method, c1data;
29061+
29062+ DRM_ERROR("PFIFO error interrupt\n");
29063+
29064+ c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
29065+ if (dev_priv->card_type < NV_40) {
29066+ /* Untested, so it may not work.. */
29067+ c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
29068+ c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
29069+ } else {
29070+ c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
29071+ c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
29072+ }
29073+
29074+ DRM_ERROR("Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
29075+ channel, (c1method >> 13) & 7, c1method & 0x1ffc,
29076+ c1data);
29077+
29078+ status &= ~NV_PFIFO_INTR_CACHE_ERROR;
29079+ NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
29080+ }
29081+
29082+ if (status & NV_PFIFO_INTR_DMA_PUSHER) {
29083+ DRM_ERROR("PFIFO DMA pusher interrupt: ch%d, 0x%08x\n",
29084+ channel, NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
29085+
29086+ status &= ~NV_PFIFO_INTR_DMA_PUSHER;
29087+ NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
29088+
29089+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
29090+ if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
29091+ {
29092+ uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
29093+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
29094+ }
29095+ }
29096+
29097+ if (status) {
29098+ DRM_ERROR("Unhandled PFIFO interrupt: status=0x%08x\n", status);
29099+
29100+ NV_WRITE(NV03_PFIFO_INTR_0, status);
29101+ }
29102+
29103+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
29104+}
29105+
29106+#if 0
29107+static void nouveau_nv04_context_switch(struct drm_device *dev)
29108+{
29109+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29110+ uint32_t channel,i;
29111+ uint32_t max=0;
29112+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
29113+ channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
29114+ //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
29115+ //DRM_INFO("currently on channel %d\n",channel);
29116+ for (i=0;i<nouveau_fifo_number(dev);i++)
29117+ if ((dev_priv->fifos[i].used)&&(i!=channel)) {
29118+ uint32_t put,get,pending;
29119+ //put=NV_READ(dev_priv->ramfc_offset+i*32);
29120+ //get=NV_READ(dev_priv->ramfc_offset+4+i*32);
29121+ put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
29122+ get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
29123+ pending=NV_READ(NV04_PFIFO_DMA);
29124+ //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
29125+ /* mark all pending channels as such */
29126+ if ((put!=get)&!(pending&(1<<i)))
29127+ {
29128+ pending|=(1<<i);
29129+ NV_WRITE(NV04_PFIFO_DMA,pending);
29130+ }
29131+ max++;
29132+ }
29133+ nouveau_wait_for_idle(dev);
29134+
29135+#if 1
29136+ /* 2-channel commute */
29137+ // NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
29138+ if (channel==0)
29139+ channel=1;
29140+ else
29141+ channel=0;
29142+ // dev_priv->cur_fifo=channel;
29143+ NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
29144+#endif
29145+ //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
29146+ //NV_WRITE(0x2050,max|0x100);
29147+
29148+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
29149+
29150+}
29151+#endif
29152+
29153+
29154+struct nouveau_bitfield_names
29155+{
29156+ uint32_t mask;
29157+ const char * name;
29158+};
29159+
29160+static struct nouveau_bitfield_names nouveau_nstatus_names[] =
29161+{
29162+ { NV03_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
29163+ { NV03_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
29164+ { NV03_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
29165+ { NV03_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
29166+};
29167+
29168+static struct nouveau_bitfield_names nouveau_nsource_names[] =
29169+{
29170+ { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
29171+ { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
29172+ { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
29173+ { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
29174+ { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
29175+ { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
29176+ { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
29177+ { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
29178+ { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
29179+ { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
29180+ { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
29181+ { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
29182+ { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
29183+ { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
29184+ { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
29185+ { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
29186+ { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
29187+ { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
29188+ { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
29189+};
29190+
29191+static void
29192+nouveau_print_bitfield_names(uint32_t value,
29193+ const struct nouveau_bitfield_names *namelist,
29194+ const int namelist_len)
29195+{
29196+ int i;
29197+ for(i=0; i<namelist_len; ++i) {
29198+ uint32_t mask = namelist[i].mask;
29199+ if(value & mask) {
29200+ printk(" %s", namelist[i].name);
29201+ value &= ~mask;
29202+ }
29203+ }
29204+ if(value)
29205+ printk(" (unknown bits 0x%08x)", value);
29206+}
29207+
29208+static int
29209+nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
29210+{
29211+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29212+ int channel;
29213+
29214+ if (dev_priv->card_type < NV_10) {
29215+ channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
29216+ } else if (dev_priv->card_type < NV_40) {
29217+ channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
29218+ } else
29219+ if (dev_priv->card_type < NV_50) {
29220+ uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;
29221+
29222+ /* 0x400704 *sometimes* contains a sensible channel ID, but
29223+ * mostly not.. for now lookup which channel owns the active
29224+ * PGRAPH context. Probably a better way, but this'll do
29225+ * for now.
29226+ */
29227+ for (channel = 0; channel < 32; channel++) {
29228+ if (dev_priv->fifos[channel] == NULL)
29229+ continue;
29230+ if (cur_grctx ==
29231+ dev_priv->fifos[channel]->ramin_grctx->instance)
29232+ break;
29233+ }
29234+ if (channel == 32) {
29235+ DRM_ERROR("AIII, unable to determine active channel "
29236+ "from PGRAPH context 0x%08x\n", cur_grctx);
29237+ return -EINVAL;
29238+ }
29239+ } else {
29240+ uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12;
29241+
29242+ for (channel = 0; channel < 128; channel++) {
29243+ if (dev_priv->fifos[channel] == NULL)
29244+ continue;
29245+ if (cur_grctx ==
29246+ dev_priv->fifos[channel]->ramin_grctx->instance)
29247+ break;
29248+ }
29249+ if (channel == 128) {
29250+ DRM_ERROR("AIII, unable to determine active channel "
29251+ "from PGRAPH context 0x%08x\n", cur_grctx);
29252+ return -EINVAL;
29253+ }
29254+ }
29255+
29256+ if (channel > nouveau_fifo_number(dev) ||
29257+ dev_priv->fifos[channel] == NULL) {
29258+ DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
29259+ return -EINVAL;
29260+ }
29261+
29262+ *channel_ret = channel;
29263+ return 0;
29264+}
29265+
29266+static void
29267+nouveau_graph_dump_trap_info(struct drm_device *dev)
29268+{
29269+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29270+ uint32_t address;
29271+ uint32_t channel, class;
29272+ uint32_t method, subc, data, data2;
29273+ uint32_t nsource, nstatus;
29274+
29275+ if (nouveau_graph_trapped_channel(dev, &channel))
29276+ channel = -1;
29277+
29278+ data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
29279+ address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
29280+ method = address & 0x1FFC;
29281+ if (dev_priv->card_type < NV_10) {
29282+ subc = (address >> 13) & 0x7;
29283+ data2= 0;
29284+ } else {
29285+ subc = (address >> 16) & 0x7;
29286+ data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
29287+ }
29288+ nsource = NV_READ(NV03_PGRAPH_NSOURCE);
29289+ nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
29290+ if (dev_priv->card_type < NV_50) {
29291+ class = NV_READ(0x400160 + subc*4) & 0xFFFF;
29292+ } else {
29293+ class = NV_READ(0x400814);
29294+ }
29295+
29296+ DRM_ERROR("nSource:");
29297+ nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
29298+ ARRAY_SIZE(nouveau_nsource_names));
29299+ printk(", nStatus:");
29300+ nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
29301+ ARRAY_SIZE(nouveau_nstatus_names));
29302+ printk("\n");
29303+
29304+ DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n",
29305+ channel, subc, class, method, data2, data);
29306+}
29307+
29308+static void nouveau_pgraph_irq_handler(struct drm_device *dev)
29309+{
29310+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29311+ uint32_t status, nsource;
29312+
29313+ status = NV_READ(NV03_PGRAPH_INTR);
29314+ if (!status)
29315+ return;
29316+ nsource = NV_READ(NV03_PGRAPH_NSOURCE);
29317+
29318+ if (status & NV_PGRAPH_INTR_NOTIFY) {
29319+ DRM_DEBUG("PGRAPH notify interrupt\n");
29320+
29321+ nouveau_graph_dump_trap_info(dev);
29322+
29323+ status &= ~NV_PGRAPH_INTR_NOTIFY;
29324+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
29325+ }
29326+
29327+ if (status & NV_PGRAPH_INTR_ERROR) {
29328+ DRM_ERROR("PGRAPH error interrupt\n");
29329+
29330+ nouveau_graph_dump_trap_info(dev);
29331+
29332+ status &= ~NV_PGRAPH_INTR_ERROR;
29333+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
29334+ }
29335+
29336+ if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
29337+ uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
29338+ DRM_DEBUG("PGRAPH context switch interrupt channel %x\n",channel);
29339+ switch(dev_priv->card_type)
29340+ {
29341+ case NV_04:
29342+ case NV_05:
29343+ nouveau_nv04_context_switch(dev);
29344+ break;
29345+ case NV_10:
29346+ case NV_11:
29347+ case NV_17:
29348+ nouveau_nv10_context_switch(dev);
29349+ break;
29350+ case NV_20:
29351+ case NV_30:
29352+ nouveau_nv20_context_switch(dev);
29353+ break;
29354+ default:
29355+ DRM_ERROR("Context switch not implemented\n");
29356+ break;
29357+ }
29358+
29359+ status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
29360+ NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
29361+ }
29362+
29363+ if (status) {
29364+ DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status);
29365+ NV_WRITE(NV03_PGRAPH_INTR, status);
29366+ }
29367+
29368+ NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
29369+}
29370+
29371+static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
29372+{
29373+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29374+
29375+ if (crtc&1) {
29376+ NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
29377+ }
29378+
29379+ if (crtc&2) {
29380+ NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
29381+ }
29382+}
29383+
29384+irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
29385+{
29386+ struct drm_device *dev = (struct drm_device*)arg;
29387+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29388+ uint32_t status;
29389+
29390+ status = NV_READ(NV03_PMC_INTR_0);
29391+ if (!status)
29392+ return IRQ_NONE;
29393+
29394+ if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
29395+ nouveau_fifo_irq_handler(dev);
29396+ status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
29397+ }
29398+
29399+ if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
29400+ nouveau_pgraph_irq_handler(dev);
29401+ status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
29402+ }
29403+
29404+ if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
29405+ nouveau_crtc_irq_handler(dev, (status>>24)&3);
29406+ status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
29407+ }
29408+
29409+ if (status)
29410+ DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
29411+
29412+ return IRQ_HANDLED;
29413+}
29414+
29415Index: git/shared-core/nouveau_mem.c
29416===================================================================
29417--- /dev/null 1970-01-01 00:00:00.000000000 +0000
29418+++ git/shared-core/nouveau_mem.c 2008-12-12 17:35:22.000000000 +0000
29419@@ -0,0 +1,608 @@
29420+/*
29421+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
29422+ * Copyright 2005 Stephane Marchesin
29423+ *
29424+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
29425+ * initial release of the Radeon 8500 driver under the XFree86 license.
29426+ * This notice must be preserved.
29427+ *
29428+ * Permission is hereby granted, free of charge, to any person obtaining a
29429+ * copy of this software and associated documentation files (the "Software"),
29430+ * to deal in the Software without restriction, including without limitation
29431+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
29432+ * and/or sell copies of the Software, and to permit persons to whom the
29433+ * Software is furnished to do so, subject to the following conditions:
29434+ *
29435+ * The above copyright notice and this permission notice (including the next
29436+ * paragraph) shall be included in all copies or substantial portions of the
29437+ * Software.
29438+ *
29439+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
29440+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29441+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
29442+ * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29443+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
29444+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
29445+ * DEALINGS IN THE SOFTWARE.
29446+ *
29447+ * Authors:
29448+ * Keith Whitwell <keith@tungstengraphics.com>
29449+ */
29450+
29451+
29452+#include "drmP.h"
29453+#include "drm.h"
29454+#include "drm_sarea.h"
29455+#include "nouveau_drv.h"
29456+
29457+static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64_t size,
29458+ struct drm_file *file_priv)
29459+{
29460+ /* Maybe cut off the start of an existing block */
29461+ if (start > p->start) {
29462+ struct mem_block *newblock =
29463+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
29464+ if (!newblock)
29465+ goto out;
29466+ newblock->start = start;
29467+ newblock->size = p->size - (start - p->start);
29468+ newblock->file_priv = NULL;
29469+ newblock->next = p->next;
29470+ newblock->prev = p;
29471+ p->next->prev = newblock;
29472+ p->next = newblock;
29473+ p->size -= newblock->size;
29474+ p = newblock;
29475+ }
29476+
29477+ /* Maybe cut off the end of an existing block */
29478+ if (size < p->size) {
29479+ struct mem_block *newblock =
29480+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
29481+ if (!newblock)
29482+ goto out;
29483+ newblock->start = start + size;
29484+ newblock->size = p->size - size;
29485+ newblock->file_priv = NULL;
29486+ newblock->next = p->next;
29487+ newblock->prev = p;
29488+ p->next->prev = newblock;
29489+ p->next = newblock;
29490+ p->size = size;
29491+ }
29492+
29493+out:
29494+ /* Our block is in the middle */
29495+ p->file_priv = file_priv;
29496+ return p;
29497+}
29498+
29499+struct mem_block *nouveau_mem_alloc_block(struct mem_block *heap,
29500+ uint64_t size,
29501+ int align2,
29502+ struct drm_file *file_priv)
29503+{
29504+ struct mem_block *p;
29505+ uint64_t mask = (1 << align2) - 1;
29506+
29507+ if (!heap)
29508+ return NULL;
29509+
29510+ list_for_each(p, heap) {
29511+ uint64_t start = (p->start + mask) & ~mask;
29512+ if (p->file_priv == 0 && start + size <= p->start + p->size)
29513+ return split_block(p, start, size, file_priv);
29514+ }
29515+
29516+ return NULL;
29517+}
29518+
29519+static struct mem_block *find_block(struct mem_block *heap, uint64_t start)
29520+{
29521+ struct mem_block *p;
29522+
29523+ list_for_each(p, heap)
29524+ if (p->start == start)
29525+ return p;
29526+
29527+ return NULL;
29528+}
29529+
29530+void nouveau_mem_free_block(struct mem_block *p)
29531+{
29532+ p->file_priv = NULL;
29533+
29534+ /* Assumes a single contiguous range. Needs a special file_priv in
29535+ * 'heap' to stop it being subsumed.
29536+ */
29537+ if (p->next->file_priv == 0) {
29538+ struct mem_block *q = p->next;
29539+ p->size += q->size;
29540+ p->next = q->next;
29541+ p->next->prev = p;
29542+ drm_free(q, sizeof(*q), DRM_MEM_BUFS);
29543+ }
29544+
29545+ if (p->prev->file_priv == 0) {
29546+ struct mem_block *q = p->prev;
29547+ q->size += p->size;
29548+ q->next = p->next;
29549+ q->next->prev = q;
29550+ drm_free(p, sizeof(*q), DRM_MEM_BUFS);
29551+ }
29552+}
29553+
29554+/* Initialize. How to check for an uninitialized heap?
29555+ */
29556+int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
29557+ uint64_t size)
29558+{
29559+ struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS);
29560+
29561+ if (!blocks)
29562+ return -ENOMEM;
29563+
29564+ *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS);
29565+ if (!*heap) {
29566+ drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS);
29567+ return -ENOMEM;
29568+ }
29569+
29570+ blocks->start = start;
29571+ blocks->size = size;
29572+ blocks->file_priv = NULL;
29573+ blocks->next = blocks->prev = *heap;
29574+
29575+ memset(*heap, 0, sizeof(**heap));
29576+ (*heap)->file_priv = (struct drm_file *) - 1;
29577+ (*heap)->next = (*heap)->prev = blocks;
29578+ return 0;
29579+}
29580+
29581+/*
29582+ * Free all blocks associated with the releasing file_priv
29583+ */
29584+void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
29585+{
29586+ struct mem_block *p;
29587+
29588+ if (!heap || !heap->next)
29589+ return;
29590+
29591+ list_for_each(p, heap) {
29592+ if (p->file_priv == file_priv)
29593+ p->file_priv = NULL;
29594+ }
29595+
29596+ /* Assumes a single contiguous range. Needs a special file_priv in
29597+ * 'heap' to stop it being subsumed.
29598+ */
29599+ list_for_each(p, heap) {
29600+ while ((p->file_priv == 0) && (p->next->file_priv == 0) &&
29601+ (p->next!=heap)) {
29602+ struct mem_block *q = p->next;
29603+ p->size += q->size;
29604+ p->next = q->next;
29605+ p->next->prev = p;
29606+ drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
29607+ }
29608+ }
29609+}
29610+
29611+/*
29612+ * Cleanup everything
29613+ */
29614+void nouveau_mem_takedown(struct mem_block **heap)
29615+{
29616+ struct mem_block *p;
29617+
29618+ if (!*heap)
29619+ return;
29620+
29621+ for (p = (*heap)->next; p != *heap;) {
29622+ struct mem_block *q = p;
29623+ p = p->next;
29624+ drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
29625+ }
29626+
29627+ drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER);
29628+ *heap = NULL;
29629+}
29630+
29631+void nouveau_mem_close(struct drm_device *dev)
29632+{
29633+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29634+
29635+ nouveau_mem_takedown(&dev_priv->agp_heap);
29636+ nouveau_mem_takedown(&dev_priv->fb_heap);
29637+ if (dev_priv->pci_heap)
29638+ nouveau_mem_takedown(&dev_priv->pci_heap);
29639+}
29640+
29641+/*XXX won't work on BSD because of pci_read_config_dword */
29642+static uint32_t
29643+nouveau_mem_fb_amount_igp(struct drm_device *dev)
29644+{
29645+#if defined(LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19))
29646+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29647+ struct pci_dev *bridge;
29648+ uint32_t mem;
29649+
29650+ bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0,1));
29651+ if (!bridge) {
29652+ DRM_ERROR("no bridge device\n");
29653+ return 0;
29654+ }
29655+
29656+ if (dev_priv->flags&NV_NFORCE) {
29657+ pci_read_config_dword(bridge, 0x7C, &mem);
29658+ return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
29659+ } else
29660+ if(dev_priv->flags&NV_NFORCE2) {
29661+ pci_read_config_dword(bridge, 0x84, &mem);
29662+ return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
29663+ }
29664+
29665+ DRM_ERROR("impossible!\n");
29666+#else
29667+ DRM_ERROR("Linux kernel >= 2.6.19 required to check for igp memory amount\n");
29668+#endif
29669+
29670+ return 0;
29671+}
29672+
29673+/* returns the amount of FB ram in bytes */
29674+uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
29675+{
29676+ struct drm_nouveau_private *dev_priv=dev->dev_private;
29677+ switch(dev_priv->card_type)
29678+ {
29679+ case NV_04:
29680+ case NV_05:
29681+ if (NV_READ(NV03_BOOT_0) & 0x00000100) {
29682+ return (((NV_READ(NV03_BOOT_0) >> 12) & 0xf)*2+2)*1024*1024;
29683+ } else
29684+ switch(NV_READ(NV03_BOOT_0)&NV03_BOOT_0_RAM_AMOUNT)
29685+ {
29686+ case NV04_BOOT_0_RAM_AMOUNT_32MB:
29687+ return 32*1024*1024;
29688+ case NV04_BOOT_0_RAM_AMOUNT_16MB:
29689+ return 16*1024*1024;
29690+ case NV04_BOOT_0_RAM_AMOUNT_8MB:
29691+ return 8*1024*1024;
29692+ case NV04_BOOT_0_RAM_AMOUNT_4MB:
29693+ return 4*1024*1024;
29694+ }
29695+ break;
29696+ case NV_10:
29697+ case NV_11:
29698+ case NV_17:
29699+ case NV_20:
29700+ case NV_30:
29701+ case NV_40:
29702+ case NV_44:
29703+ case NV_50:
29704+ default:
29705+ if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
29706+ return nouveau_mem_fb_amount_igp(dev);
29707+ } else {
29708+ uint64_t mem;
29709+
29710+ mem = (NV_READ(NV04_FIFO_DATA) &
29711+ NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
29712+ NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
29713+ return mem*1024*1024;
29714+ }
29715+ break;
29716+ }
29717+
29718+ DRM_ERROR("Unable to detect video ram size. Please report your setup to " DRIVER_EMAIL "\n");
29719+ return 0;
29720+}
29721+
29722+static int
29723+nouveau_mem_init_agp(struct drm_device *dev)
29724+{
29725+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29726+ struct drm_agp_info info;
29727+ struct drm_agp_mode mode;
29728+ struct drm_agp_buffer agp_req;
29729+ struct drm_agp_binding bind_req;
29730+ int ret;
29731+
29732+ ret = drm_agp_acquire(dev);
29733+ if (ret) {
29734+ DRM_ERROR("Unable to acquire AGP: %d\n", ret);
29735+ return ret;
29736+ }
29737+
29738+ ret = drm_agp_info(dev, &info);
29739+ if (ret) {
29740+ DRM_ERROR("Unable to get AGP info: %d\n", ret);
29741+ return ret;
29742+ }
29743+
29744+ /* see agp.h for the AGPSTAT_* modes available */
29745+ mode.mode = info.mode;
29746+ ret = drm_agp_enable(dev, mode);
29747+ if (ret) {
29748+ DRM_ERROR("Unable to enable AGP: %d\n", ret);
29749+ return ret;
29750+ }
29751+
29752+ agp_req.size = info.aperture_size;
29753+ agp_req.type = 0;
29754+ ret = drm_agp_alloc(dev, &agp_req);
29755+ if (ret) {
29756+ DRM_ERROR("Unable to alloc AGP: %d\n", ret);
29757+ return ret;
29758+ }
29759+
29760+ bind_req.handle = agp_req.handle;
29761+ bind_req.offset = 0;
29762+ ret = drm_agp_bind(dev, &bind_req);
29763+ if (ret) {
29764+ DRM_ERROR("Unable to bind AGP: %d\n", ret);
29765+ return ret;
29766+ }
29767+
29768+ dev_priv->gart_info.type = NOUVEAU_GART_AGP;
29769+ dev_priv->gart_info.aper_base = info.aperture_base;
29770+ dev_priv->gart_info.aper_size = info.aperture_size;
29771+ return 0;
29772+}
29773+
29774+int nouveau_mem_init(struct drm_device *dev)
29775+{
29776+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29777+ uint32_t fb_size;
29778+ int ret = 0;
29779+
29780+ dev_priv->agp_heap = dev_priv->pci_heap = dev_priv->fb_heap = NULL;
29781+ dev_priv->fb_phys = 0;
29782+ dev_priv->gart_info.type = NOUVEAU_GART_NONE;
29783+
29784+ /* setup a mtrr over the FB */
29785+ dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1),
29786+ nouveau_mem_fb_amount(dev),
29787+ DRM_MTRR_WC);
29788+
29789+ /* Init FB */
29790+ dev_priv->fb_phys=drm_get_resource_start(dev,1);
29791+ fb_size = nouveau_mem_fb_amount(dev);
29792+ /* On at least NV40, RAMIN is actually at the end of vram.
29793+ * We don't want to allocate this... */
29794+ if (dev_priv->card_type >= NV_40)
29795+ fb_size -= dev_priv->ramin_rsvd_vram;
29796+ dev_priv->fb_available_size = fb_size;
29797+ DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10);
29798+
29799+ if (fb_size>256*1024*1024) {
29800+ /* On cards with > 256Mb, you can't map everything.
29801+ * So we create a second FB heap for that type of memory */
29802+ if (nouveau_mem_init_heap(&dev_priv->fb_heap,
29803+ 0, 256*1024*1024))
29804+ return -ENOMEM;
29805+ if (nouveau_mem_init_heap(&dev_priv->fb_nomap_heap,
29806+ 256*1024*1024, fb_size-256*1024*1024))
29807+ return -ENOMEM;
29808+ } else {
29809+ if (nouveau_mem_init_heap(&dev_priv->fb_heap, 0, fb_size))
29810+ return -ENOMEM;
29811+ dev_priv->fb_nomap_heap=NULL;
29812+ }
29813+
29814+ /* Init AGP / NV50 PCIEGART */
29815+ if (drm_device_is_agp(dev) && dev->agp) {
29816+ if ((ret = nouveau_mem_init_agp(dev)))
29817+ DRM_ERROR("Error initialising AGP: %d\n", ret);
29818+ }
29819+
29820+ /*Note: this is *not* just NV50 code, but only used on NV50 for now */
29821+ if (dev_priv->gart_info.type == NOUVEAU_GART_NONE &&
29822+ dev_priv->card_type >= NV_50) {
29823+ ret = nouveau_sgdma_init(dev);
29824+ if (!ret) {
29825+ ret = nouveau_sgdma_nottm_hack_init(dev);
29826+ if (ret)
29827+ nouveau_sgdma_takedown(dev);
29828+ }
29829+
29830+ if (ret)
29831+ DRM_ERROR("Error initialising SG DMA: %d\n", ret);
29832+ }
29833+
29834+ if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
29835+ if (nouveau_mem_init_heap(&dev_priv->agp_heap,
29836+ 0, dev_priv->gart_info.aper_size)) {
29837+ if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
29838+ nouveau_sgdma_nottm_hack_takedown(dev);
29839+ nouveau_sgdma_takedown(dev);
29840+ }
29841+ }
29842+ }
29843+
29844+ /* NV04-NV40 PCIEGART */
29845+ if (!dev_priv->agp_heap && dev_priv->card_type < NV_50) {
29846+ struct drm_scatter_gather sgreq;
29847+
29848+ DRM_DEBUG("Allocating sg memory for PCI DMA\n");
29849+ sgreq.size = 16 << 20; //16MB of PCI scatter-gather zone
29850+
29851+ if (drm_sg_alloc(dev, &sgreq)) {
29852+ DRM_ERROR("Unable to allocate %dMB of scatter-gather"
29853+ " pages for PCI DMA!",sgreq.size>>20);
29854+ } else {
29855+ if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0,
29856+ dev->sg->pages * PAGE_SIZE)) {
29857+ DRM_ERROR("Unable to initialize pci_heap!");
29858+ }
29859+ }
29860+ }
29861+
29862+ return 0;
29863+}
29864+
29865+struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment,
29866+ uint64_t size, int flags,
29867+ struct drm_file *file_priv)
29868+{
29869+ struct mem_block *block;
29870+ int type;
29871+ struct drm_nouveau_private *dev_priv = dev->dev_private;
29872+
29873+ /*
29874+ * Make things easier on ourselves: all allocations are page-aligned.
29875+ * We need that to map allocated regions into the user space
29876+ */
29877+ if (alignment < PAGE_SHIFT)
29878+ alignment = PAGE_SHIFT;
29879+
29880+ /*
29881+ * Warn about 0 sized allocations, but let it go through. It'll return 1 page
29882+ */
29883+ if (size == 0)
29884+ DRM_INFO("warning : 0 byte allocation\n");
29885+
29886+ /*
29887+ * Keep alloc size a multiple of the page size to keep drm_addmap() happy
29888+ */
29889+ if (size & (~PAGE_MASK))
29890+ size = ((size/PAGE_SIZE) + 1) * PAGE_SIZE;
29891+
29892+
29893+#define NOUVEAU_MEM_ALLOC_AGP {\
29894+ type=NOUVEAU_MEM_AGP;\
29895+ block = nouveau_mem_alloc_block(dev_priv->agp_heap, size,\
29896+ alignment, file_priv); \
29897+ if (block) goto alloc_ok;\
29898+ }
29899+
29900+#define NOUVEAU_MEM_ALLOC_PCI {\
29901+ type = NOUVEAU_MEM_PCI;\
29902+ block = nouveau_mem_alloc_block(dev_priv->pci_heap, size, \
29903+ alignment, file_priv); \
29904+ if ( block ) goto alloc_ok;\
29905+ }
29906+
29907+#define NOUVEAU_MEM_ALLOC_FB {\
29908+ type=NOUVEAU_MEM_FB;\
29909+ if (!(flags&NOUVEAU_MEM_MAPPED)) {\
29910+ block = nouveau_mem_alloc_block(dev_priv->fb_nomap_heap,\
29911+ size, alignment, \
29912+ file_priv); \
29913+ if (block) goto alloc_ok;\
29914+ }\
29915+ block = nouveau_mem_alloc_block(dev_priv->fb_heap, size,\
29916+ alignment, file_priv);\
29917+ if (block) goto alloc_ok;\
29918+ }
29919+
29920+
29921+ if (flags&NOUVEAU_MEM_FB) NOUVEAU_MEM_ALLOC_FB
29922+ if (flags&NOUVEAU_MEM_AGP) NOUVEAU_MEM_ALLOC_AGP
29923+ if (flags&NOUVEAU_MEM_PCI) NOUVEAU_MEM_ALLOC_PCI
29924+ if (flags&NOUVEAU_MEM_FB_ACCEPTABLE) NOUVEAU_MEM_ALLOC_FB
29925+ if (flags&NOUVEAU_MEM_AGP_ACCEPTABLE) NOUVEAU_MEM_ALLOC_AGP
29926+ if (flags&NOUVEAU_MEM_PCI_ACCEPTABLE) NOUVEAU_MEM_ALLOC_PCI
29927+
29928+
29929+ return NULL;
29930+
29931+alloc_ok:
29932+ block->flags=type;
29933+
29934+ if (flags&NOUVEAU_MEM_MAPPED)
29935+ {
29936+ struct drm_map_list *entry;
29937+ int ret = 0;
29938+ block->flags|=NOUVEAU_MEM_MAPPED;
29939+
29940+ if (type == NOUVEAU_MEM_AGP) {
29941+ if (dev_priv->gart_info.type != NOUVEAU_GART_SGDMA)
29942+ ret = drm_addmap(dev, block->start, block->size,
29943+ _DRM_AGP, 0, &block->map);
29944+ else
29945+ ret = drm_addmap(dev, block->start, block->size,
29946+ _DRM_SCATTER_GATHER, 0, &block->map);
29947+ }
29948+ else if (type == NOUVEAU_MEM_FB)
29949+ ret = drm_addmap(dev, block->start + dev_priv->fb_phys,
29950+ block->size, _DRM_FRAME_BUFFER,
29951+ 0, &block->map);
29952+ else if (type == NOUVEAU_MEM_PCI)
29953+ ret = drm_addmap(dev, block->start, block->size,
29954+ _DRM_SCATTER_GATHER, 0, &block->map);
29955+
29956+ if (ret) {
29957+ nouveau_mem_free_block(block);
29958+ return NULL;
29959+ }
29960+
29961+ entry = drm_find_matching_map(dev, block->map);
29962+ if (!entry) {
29963+ nouveau_mem_free_block(block);
29964+ return NULL;
29965+ }
29966+ block->map_handle = entry->user_token;
29967+ }
29968+
29969+ DRM_DEBUG("allocated 0x%llx type=0x%08x\n", block->start, block->flags);
29970+ return block;
29971+}
29972+
29973+void nouveau_mem_free(struct drm_device* dev, struct mem_block* block)
29974+{
29975+ DRM_DEBUG("freeing 0x%llx type=0x%08x\n", block->start, block->flags);
29976+ if (block->flags&NOUVEAU_MEM_MAPPED)
29977+ drm_rmmap(dev, block->map);
29978+ nouveau_mem_free_block(block);
29979+}
29980+
29981+/*
29982+ * Ioctls
29983+ */
29984+
29985+int nouveau_ioctl_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
29986+{
29987+ struct drm_nouveau_mem_alloc *alloc = data;
29988+ struct mem_block *block;
29989+
29990+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
29991+
29992+ block=nouveau_mem_alloc(dev, alloc->alignment, alloc->size,
29993+ alloc->flags, file_priv);
29994+ if (!block)
29995+ return -ENOMEM;
29996+ alloc->map_handle=block->map_handle;
29997+ alloc->offset=block->start;
29998+ alloc->flags=block->flags;
29999+
30000+ return 0;
30001+}
30002+
30003+int nouveau_ioctl_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
30004+{
30005+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30006+ struct drm_nouveau_mem_free *memfree = data;
30007+ struct mem_block *block;
30008+
30009+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
30010+
30011+ block=NULL;
30012+ if (memfree->flags & NOUVEAU_MEM_FB)
30013+ block = find_block(dev_priv->fb_heap, memfree->offset);
30014+ else if (memfree->flags & NOUVEAU_MEM_AGP)
30015+ block = find_block(dev_priv->agp_heap, memfree->offset);
30016+ else if (memfree->flags & NOUVEAU_MEM_PCI)
30017+ block = find_block(dev_priv->pci_heap, memfree->offset);
30018+ if (!block)
30019+ return -EFAULT;
30020+ if (block->file_priv != file_priv)
30021+ return -EPERM;
30022+
30023+ nouveau_mem_free(dev, block);
30024+ return 0;
30025+}
30026+
30027+
30028Index: git/shared-core/nouveau_notifier.c
30029===================================================================
30030--- /dev/null 1970-01-01 00:00:00.000000000 +0000
30031+++ git/shared-core/nouveau_notifier.c 2008-12-12 17:35:22.000000000 +0000
30032@@ -0,0 +1,173 @@
30033+/*
30034+ * Copyright (C) 2007 Ben Skeggs.
30035+ *
30036+ * All Rights Reserved.
30037+ *
30038+ * Permission is hereby granted, free of charge, to any person obtaining
30039+ * a copy of this software and associated documentation files (the
30040+ * "Software"), to deal in the Software without restriction, including
30041+ * without limitation the rights to use, copy, modify, merge, publish,
30042+ * distribute, sublicense, and/or sell copies of the Software, and to
30043+ * permit persons to whom the Software is furnished to do so, subject to
30044+ * the following conditions:
30045+ *
30046+ * The above copyright notice and this permission notice (including the
30047+ * next paragraph) shall be included in all copies or substantial
30048+ * portions of the Software.
30049+ *
30050+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30051+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
30052+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
30053+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
30054+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30055+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
30056+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30057+ *
30058+ */
30059+
30060+#include "drmP.h"
30061+#include "drm.h"
30062+#include "nouveau_drv.h"
30063+
30064+int
30065+nouveau_notifier_init_channel(struct nouveau_channel *chan)
30066+{
30067+ struct drm_device *dev = chan->dev;
30068+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30069+ int flags, ret;
30070+
30071+ /*TODO: PCI notifier blocks */
30072+ if (dev_priv->agp_heap)
30073+ flags = NOUVEAU_MEM_AGP;
30074+ else if (dev_priv->pci_heap)
30075+ flags = NOUVEAU_MEM_PCI;
30076+ else
30077+ flags = NOUVEAU_MEM_FB;
30078+ flags |= (NOUVEAU_MEM_MAPPED | NOUVEAU_MEM_FB_ACCEPTABLE);
30079+
30080+ chan->notifier_block = nouveau_mem_alloc(dev, 0, PAGE_SIZE, flags,
30081+ (struct drm_file *)-2);
30082+ if (!chan->notifier_block)
30083+ return -ENOMEM;
30084+ DRM_DEBUG("Allocated notifier block in 0x%08x\n",
30085+ chan->notifier_block->flags);
30086+
30087+ ret = nouveau_mem_init_heap(&chan->notifier_heap,
30088+ 0, chan->notifier_block->size);
30089+ if (ret)
30090+ return ret;
30091+
30092+ return 0;
30093+}
30094+
30095+void
30096+nouveau_notifier_takedown_channel(struct nouveau_channel *chan)
30097+{
30098+ struct drm_device *dev = chan->dev;
30099+
30100+ if (chan->notifier_block) {
30101+ nouveau_mem_free(dev, chan->notifier_block);
30102+ chan->notifier_block = NULL;
30103+ }
30104+
30105+ nouveau_mem_takedown(&chan->notifier_heap);
30106+}
30107+
30108+static void
30109+nouveau_notifier_gpuobj_dtor(struct drm_device *dev,
30110+ struct nouveau_gpuobj *gpuobj)
30111+{
30112+ DRM_DEBUG("\n");
30113+
30114+ if (gpuobj->priv)
30115+ nouveau_mem_free_block(gpuobj->priv);
30116+}
30117+
30118+int
30119+nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
30120+ int count, uint32_t *b_offset)
30121+{
30122+ struct drm_device *dev = chan->dev;
30123+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30124+ struct nouveau_gpuobj *nobj = NULL;
30125+ struct mem_block *mem;
30126+ uint32_t offset;
30127+ int target, ret;
30128+
30129+ if (!chan->notifier_heap) {
30130+ DRM_ERROR("Channel %d doesn't have a notifier heap!\n",
30131+ chan->id);
30132+ return -EINVAL;
30133+ }
30134+
30135+ mem = nouveau_mem_alloc_block(chan->notifier_heap, count*32, 0,
30136+ (struct drm_file *)-2);
30137+ if (!mem) {
30138+ DRM_ERROR("Channel %d notifier block full\n", chan->id);
30139+ return -ENOMEM;
30140+ }
30141+ mem->flags = NOUVEAU_MEM_NOTIFIER;
30142+
30143+ offset = chan->notifier_block->start;
30144+ if (chan->notifier_block->flags & NOUVEAU_MEM_FB) {
30145+ target = NV_DMA_TARGET_VIDMEM;
30146+ } else
30147+ if (chan->notifier_block->flags & NOUVEAU_MEM_AGP) {
30148+ if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA &&
30149+ dev_priv->card_type < NV_50) {
30150+ ret = nouveau_sgdma_get_page(dev, offset, &offset);
30151+ if (ret)
30152+ return ret;
30153+ target = NV_DMA_TARGET_PCI;
30154+ } else {
30155+ target = NV_DMA_TARGET_AGP;
30156+ }
30157+ } else
30158+ if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) {
30159+ target = NV_DMA_TARGET_PCI_NONLINEAR;
30160+ } else {
30161+ DRM_ERROR("Bad DMA target, flags 0x%08x!\n",
30162+ chan->notifier_block->flags);
30163+ return -EINVAL;
30164+ }
30165+ offset += mem->start;
30166+
30167+ if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
30168+ offset, mem->size,
30169+ NV_DMA_ACCESS_RW, target, &nobj))) {
30170+ nouveau_mem_free_block(mem);
30171+ DRM_ERROR("Error creating notifier ctxdma: %d\n", ret);
30172+ return ret;
30173+ }
30174+ nobj->dtor = nouveau_notifier_gpuobj_dtor;
30175+ nobj->priv = mem;
30176+
30177+ if ((ret = nouveau_gpuobj_ref_add(dev, chan, handle, nobj, NULL))) {
30178+ nouveau_gpuobj_del(dev, &nobj);
30179+ nouveau_mem_free_block(mem);
30180+ DRM_ERROR("Error referencing notifier ctxdma: %d\n", ret);
30181+ return ret;
30182+ }
30183+
30184+ *b_offset = mem->start;
30185+ return 0;
30186+}
30187+
30188+int
30189+nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
30190+ struct drm_file *file_priv)
30191+{
30192+ struct drm_nouveau_notifierobj_alloc *na = data;
30193+ struct nouveau_channel *chan;
30194+ int ret;
30195+
30196+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
30197+ NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(na->channel, file_priv, chan);
30198+
30199+ ret = nouveau_notifier_alloc(chan, na->handle, na->count, &na->offset);
30200+ if (ret)
30201+ return ret;
30202+
30203+ return 0;
30204+}
30205+
30206Index: git/shared-core/nouveau_object.c
30207===================================================================
30208--- /dev/null 1970-01-01 00:00:00.000000000 +0000
30209+++ git/shared-core/nouveau_object.c 2008-12-12 17:35:22.000000000 +0000
30210@@ -0,0 +1,1148 @@
30211+/*
30212+ * Copyright (C) 2006 Ben Skeggs.
30213+ *
30214+ * All Rights Reserved.
30215+ *
30216+ * Permission is hereby granted, free of charge, to any person obtaining
30217+ * a copy of this software and associated documentation files (the
30218+ * "Software"), to deal in the Software without restriction, including
30219+ * without limitation the rights to use, copy, modify, merge, publish,
30220+ * distribute, sublicense, and/or sell copies of the Software, and to
30221+ * permit persons to whom the Software is furnished to do so, subject to
30222+ * the following conditions:
30223+ *
30224+ * The above copyright notice and this permission notice (including the
30225+ * next paragraph) shall be included in all copies or substantial
30226+ * portions of the Software.
30227+ *
30228+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
30229+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
30230+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
30231+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
30232+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30233+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
30234+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30235+ *
30236+ */
30237+
30238+/*
30239+ * Authors:
30240+ * Ben Skeggs <darktama@iinet.net.au>
30241+ */
30242+
30243+#include "drmP.h"
30244+#include "drm.h"
30245+#include "nouveau_drv.h"
30246+#include "nouveau_drm.h"
30247+
30248+/* NVidia uses context objects to drive drawing operations.
30249+
30250+ Context objects can be selected into 8 subchannels in the FIFO,
30251+ and then used via DMA command buffers.
30252+
30253+ A context object is referenced by a user defined handle (CARD32). The HW
30254+ looks up graphics objects in a hash table in the instance RAM.
30255+
30256+ An entry in the hash table consists of 2 CARD32. The first CARD32 contains
30257+ the handle, the second one a bitfield, that contains the address of the
30258+ object in instance RAM.
30259+
30260+ The format of the second CARD32 seems to be:
30261+
30262+ NV4 to NV30:
30263+
30264+ 15: 0 instance_addr >> 4
30265+ 17:16 engine (here uses 1 = graphics)
30266+ 28:24 channel id (here uses 0)
30267+ 31 valid (use 1)
30268+
30269+ NV40:
30270+
30271+ 15: 0 instance_addr >> 4 (maybe 19-0)
30272+ 21:20 engine (here uses 1 = graphics)
30273+ I'm unsure about the other bits, but using 0 seems to work.
30274+
30275+ The key into the hash table depends on the object handle and channel id and
30276+ is given as:
30277+*/
30278+static uint32_t
30279+nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle)
30280+{
30281+ struct drm_nouveau_private *dev_priv=dev->dev_private;
30282+ uint32_t hash = 0;
30283+ int i;
30284+
30285+ DRM_DEBUG("ch%d handle=0x%08x\n", channel, handle);
30286+
30287+ for (i=32;i>0;i-=dev_priv->ramht_bits) {
30288+ hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
30289+ handle >>= dev_priv->ramht_bits;
30290+ }
30291+ if (dev_priv->card_type < NV_50)
30292+ hash ^= channel << (dev_priv->ramht_bits - 4);
30293+ hash <<= 3;
30294+
30295+ DRM_DEBUG("hash=0x%08x\n", hash);
30296+ return hash;
30297+}
30298+
30299+static int
30300+nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht,
30301+ uint32_t offset)
30302+{
30303+ struct drm_nouveau_private *dev_priv=dev->dev_private;
30304+ uint32_t ctx = INSTANCE_RD(ramht, (offset + 4)/4);
30305+
30306+ if (dev_priv->card_type < NV_40)
30307+ return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0);
30308+ return (ctx != 0);
30309+}
30310+
30311+static int
30312+nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
30313+{
30314+ struct drm_nouveau_private *dev_priv=dev->dev_private;
30315+ struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
30316+ struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
30317+ struct nouveau_gpuobj *gpuobj = ref->gpuobj;
30318+ uint32_t ctx, co, ho;
30319+
30320+ if (!ramht) {
30321+ DRM_ERROR("No hash table!\n");
30322+ return -EINVAL;
30323+ }
30324+
30325+ if (dev_priv->card_type < NV_40) {
30326+ ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) |
30327+ (ref->channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
30328+ (gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT);
30329+ } else
30330+ if (dev_priv->card_type < NV_50) {
30331+ ctx = (ref->instance >> 4) |
30332+ (ref->channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
30333+ (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
30334+ } else {
30335+ ctx = (ref->instance >> 4) |
30336+ (gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT);
30337+ }
30338+
30339+ co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle);
30340+ do {
30341+ if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
30342+ DRM_DEBUG("insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
30343+ ref->channel, co, ref->handle, ctx);
30344+ INSTANCE_WR(ramht, (co + 0)/4, ref->handle);
30345+ INSTANCE_WR(ramht, (co + 4)/4, ctx);
30346+
30347+ list_add_tail(&ref->list, &chan->ramht_refs);
30348+ return 0;
30349+ }
30350+ DRM_DEBUG("collision ch%d 0x%08x: h=0x%08x\n",
30351+ ref->channel, co, INSTANCE_RD(ramht, co/4));
30352+
30353+ co += 8;
30354+ if (co >= dev_priv->ramht_size) {
30355+ DRM_INFO("no space left after collision\n");
30356+ co = 0;
30357+ /* exit as it seems to cause crash with nouveau_demo and
30358+ * 0xdead0001 object */
30359+ break;
30360+ }
30361+ } while (co != ho);
30362+
30363+ DRM_ERROR("RAMHT space exhausted. ch=%d\n", ref->channel);
30364+ return -ENOMEM;
30365+}
30366+
30367+static void
30368+nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref)
30369+{
30370+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30371+ struct nouveau_channel *chan = dev_priv->fifos[ref->channel];
30372+ struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL;
30373+ uint32_t co, ho;
30374+
30375+ if (!ramht) {
30376+ DRM_ERROR("No hash table!\n");
30377+ return;
30378+ }
30379+
30380+ co = ho = nouveau_ramht_hash_handle(dev, ref->channel, ref->handle);
30381+ do {
30382+ if (nouveau_ramht_entry_valid(dev, ramht, co) &&
30383+ (ref->handle == INSTANCE_RD(ramht, (co/4)))) {
30384+ DRM_DEBUG("remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n",
30385+ ref->channel, co, ref->handle,
30386+ INSTANCE_RD(ramht, (co + 4)));
30387+ INSTANCE_WR(ramht, (co + 0)/4, 0x00000000);
30388+ INSTANCE_WR(ramht, (co + 4)/4, 0x00000000);
30389+
30390+ list_del(&ref->list);
30391+ return;
30392+ }
30393+
30394+ co += 8;
30395+ if (co >= dev_priv->ramht_size)
30396+ co = 0;
30397+ } while (co != ho);
30398+
30399+ DRM_ERROR("RAMHT entry not found. ch=%d, handle=0x%08x\n",
30400+ ref->channel, ref->handle);
30401+}
30402+
30403+int
30404+nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
30405+ int size, int align, uint32_t flags,
30406+ struct nouveau_gpuobj **gpuobj_ret)
30407+{
30408+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30409+ struct nouveau_engine *engine = &dev_priv->Engine;
30410+ struct nouveau_gpuobj *gpuobj;
30411+ struct mem_block *pramin = NULL;
30412+ int ret;
30413+
30414+ DRM_DEBUG("ch%d size=%d align=%d flags=0x%08x\n",
30415+ chan ? chan->id : -1, size, align, flags);
30416+
30417+ if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL)
30418+ return -EINVAL;
30419+
30420+ gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
30421+ if (!gpuobj)
30422+ return -ENOMEM;
30423+ DRM_DEBUG("gpuobj %p\n", gpuobj);
30424+ gpuobj->flags = flags;
30425+ gpuobj->im_channel = chan ? chan->id : -1;
30426+
30427+ list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
30428+
30429+ /* Choose between global instmem heap, and per-channel private
30430+ * instmem heap. On <NV50 allow requests for private instmem
30431+ * to be satisfied from global heap if no per-channel area
30432+ * available.
30433+ */
30434+ if (chan) {
30435+ if (chan->ramin_heap) {
30436+ DRM_DEBUG("private heap\n");
30437+ pramin = chan->ramin_heap;
30438+ } else
30439+ if (dev_priv->card_type < NV_50) {
30440+ DRM_DEBUG("global heap fallback\n");
30441+ pramin = dev_priv->ramin_heap;
30442+ }
30443+ } else {
30444+ DRM_DEBUG("global heap\n");
30445+ pramin = dev_priv->ramin_heap;
30446+ }
30447+
30448+ if (!pramin) {
30449+ DRM_ERROR("No PRAMIN heap!\n");
30450+ return -EINVAL;
30451+ }
30452+
30453+ if (!chan && (ret = engine->instmem.populate(dev, gpuobj, &size))) {
30454+ nouveau_gpuobj_del(dev, &gpuobj);
30455+ return ret;
30456+ }
30457+
30458+ /* Allocate a chunk of the PRAMIN aperture */
30459+ gpuobj->im_pramin = nouveau_mem_alloc_block(pramin, size,
30460+ drm_order(align),
30461+ (struct drm_file *)-2);
30462+ if (!gpuobj->im_pramin) {
30463+ nouveau_gpuobj_del(dev, &gpuobj);
30464+ return -ENOMEM;
30465+ }
30466+ gpuobj->im_pramin->flags = NOUVEAU_MEM_INSTANCE;
30467+
30468+ if (!chan && (ret = engine->instmem.bind(dev, gpuobj))) {
30469+ nouveau_gpuobj_del(dev, &gpuobj);
30470+ return ret;
30471+ }
30472+
30473+ if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
30474+ int i;
30475+
30476+ for (i = 0; i < gpuobj->im_pramin->size; i += 4)
30477+ INSTANCE_WR(gpuobj, i/4, 0);
30478+ }
30479+
30480+ *gpuobj_ret = gpuobj;
30481+ return 0;
30482+}
30483+
30484+int
30485+nouveau_gpuobj_early_init(struct drm_device *dev)
30486+{
30487+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30488+
30489+ DRM_DEBUG("\n");
30490+
30491+ INIT_LIST_HEAD(&dev_priv->gpuobj_list);
30492+
30493+ return 0;
30494+}
30495+
30496+int
30497+nouveau_gpuobj_init(struct drm_device *dev)
30498+{
30499+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30500+ int ret;
30501+
30502+ DRM_DEBUG("\n");
30503+
30504+ if (dev_priv->card_type < NV_50) {
30505+ if ((ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramht_offset,
30506+ ~0, dev_priv->ramht_size,
30507+ NVOBJ_FLAG_ZERO_ALLOC |
30508+ NVOBJ_FLAG_ALLOW_NO_REFS,
30509+ &dev_priv->ramht, NULL)))
30510+ return ret;
30511+ }
30512+
30513+ return 0;
30514+}
30515+
30516+void
30517+nouveau_gpuobj_takedown(struct drm_device *dev)
30518+{
30519+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30520+
30521+ DRM_DEBUG("\n");
30522+
30523+ nouveau_gpuobj_del(dev, &dev_priv->ramht);
30524+}
30525+
30526+void
30527+nouveau_gpuobj_late_takedown(struct drm_device *dev)
30528+{
30529+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30530+ struct nouveau_gpuobj *gpuobj = NULL;
30531+ struct list_head *entry, *tmp;
30532+
30533+ DRM_DEBUG("\n");
30534+
30535+ list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) {
30536+ gpuobj = list_entry(entry, struct nouveau_gpuobj, list);
30537+
30538+ DRM_ERROR("gpuobj %p still exists at takedown, refs=%d\n",
30539+ gpuobj, gpuobj->refcount);
30540+ gpuobj->refcount = 0;
30541+ nouveau_gpuobj_del(dev, &gpuobj);
30542+ }
30543+}
30544+
30545+int
30546+nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj)
30547+{
30548+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30549+ struct nouveau_engine *engine = &dev_priv->Engine;
30550+ struct nouveau_gpuobj *gpuobj;
30551+
30552+ DRM_DEBUG("gpuobj %p\n", pgpuobj ? *pgpuobj : NULL);
30553+
30554+ if (!dev_priv || !pgpuobj || !(*pgpuobj))
30555+ return -EINVAL;
30556+ gpuobj = *pgpuobj;
30557+
30558+ if (gpuobj->refcount != 0) {
30559+ DRM_ERROR("gpuobj refcount is %d\n", gpuobj->refcount);
30560+ return -EINVAL;
30561+ }
30562+
30563+ if (gpuobj->dtor)
30564+ gpuobj->dtor(dev, gpuobj);
30565+
30566+ if (gpuobj->im_backing) {
30567+ if (gpuobj->flags & NVOBJ_FLAG_FAKE)
30568+ drm_free(gpuobj->im_backing,
30569+ sizeof(*gpuobj->im_backing), DRM_MEM_DRIVER);
30570+ else
30571+ engine->instmem.clear(dev, gpuobj);
30572+ }
30573+
30574+ if (gpuobj->im_pramin) {
30575+ if (gpuobj->flags & NVOBJ_FLAG_FAKE)
30576+ drm_free(gpuobj->im_pramin, sizeof(*gpuobj->im_pramin),
30577+ DRM_MEM_DRIVER);
30578+ else
30579+ nouveau_mem_free_block(gpuobj->im_pramin);
30580+ }
30581+
30582+ list_del(&gpuobj->list);
30583+
30584+ *pgpuobj = NULL;
30585+ drm_free(gpuobj, sizeof(*gpuobj), DRM_MEM_DRIVER);
30586+ return 0;
30587+}
30588+
30589+static int
30590+nouveau_gpuobj_instance_get(struct drm_device *dev,
30591+ struct nouveau_channel *chan,
30592+ struct nouveau_gpuobj *gpuobj, uint32_t *inst)
30593+{
30594+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30595+ struct nouveau_gpuobj *cpramin;
30596+
30597+ /* <NV50 use PRAMIN address everywhere */
30598+ if (dev_priv->card_type < NV_50) {
30599+ *inst = gpuobj->im_pramin->start;
30600+ return 0;
30601+ }
30602+
30603+ if (chan && gpuobj->im_channel != chan->id) {
30604+ DRM_ERROR("Channel mismatch: obj %d, ref %d\n",
30605+ gpuobj->im_channel, chan->id);
30606+ return -EINVAL;
30607+ }
30608+
30609+ /* NV50 channel-local instance */
30610+ if (chan > 0) {
30611+ cpramin = chan->ramin->gpuobj;
30612+ *inst = gpuobj->im_pramin->start - cpramin->im_pramin->start;
30613+ return 0;
30614+ }
30615+
30616+ /* NV50 global (VRAM) instance */
30617+ if (gpuobj->im_channel < 0) {
30618+ /* ...from global heap */
30619+ if (!gpuobj->im_backing) {
30620+ DRM_ERROR("AII, no VRAM backing gpuobj\n");
30621+ return -EINVAL;
30622+ }
30623+ *inst = gpuobj->im_backing->start;
30624+ return 0;
30625+ } else {
30626+ /* ...from local heap */
30627+ cpramin = dev_priv->fifos[gpuobj->im_channel]->ramin->gpuobj;
30628+ *inst = cpramin->im_backing->start +
30629+ (gpuobj->im_pramin->start - cpramin->im_pramin->start);
30630+ return 0;
30631+ }
30632+
30633+ return -EINVAL;
30634+}
30635+
30636+int
30637+nouveau_gpuobj_ref_add(struct drm_device *dev, struct nouveau_channel *chan,
30638+ uint32_t handle, struct nouveau_gpuobj *gpuobj,
30639+ struct nouveau_gpuobj_ref **ref_ret)
30640+{
30641+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30642+ struct nouveau_gpuobj_ref *ref;
30643+ uint32_t instance;
30644+ int ret;
30645+
30646+ DRM_DEBUG("ch%d h=0x%08x gpuobj=%p\n",
30647+ chan ? chan->id : -1, handle, gpuobj);
30648+
30649+ if (!dev_priv || !gpuobj || (ref_ret && *ref_ret != NULL))
30650+ return -EINVAL;
30651+
30652+ if (!chan && !ref_ret)
30653+ return -EINVAL;
30654+
30655+ ret = nouveau_gpuobj_instance_get(dev, chan, gpuobj, &instance);
30656+ if (ret)
30657+ return ret;
30658+
30659+ ref = drm_calloc(1, sizeof(*ref), DRM_MEM_DRIVER);
30660+ if (!ref)
30661+ return -ENOMEM;
30662+ ref->gpuobj = gpuobj;
30663+ ref->channel = chan ? chan->id : -1;
30664+ ref->instance = instance;
30665+
30666+ if (!ref_ret) {
30667+ ref->handle = handle;
30668+
30669+ ret = nouveau_ramht_insert(dev, ref);
30670+ if (ret) {
30671+ drm_free(ref, sizeof(*ref), DRM_MEM_DRIVER);
30672+ return ret;
30673+ }
30674+ } else {
30675+ ref->handle = ~0;
30676+ *ref_ret = ref;
30677+ }
30678+
30679+ ref->gpuobj->refcount++;
30680+ return 0;
30681+}
30682+
30683+int nouveau_gpuobj_ref_del(struct drm_device *dev, struct nouveau_gpuobj_ref **pref)
30684+{
30685+ struct nouveau_gpuobj_ref *ref;
30686+
30687+ DRM_DEBUG("ref %p\n", pref ? *pref : NULL);
30688+
30689+ if (!dev || !pref || *pref == NULL)
30690+ return -EINVAL;
30691+ ref = *pref;
30692+
30693+ if (ref->handle != ~0)
30694+ nouveau_ramht_remove(dev, ref);
30695+
30696+ if (ref->gpuobj) {
30697+ ref->gpuobj->refcount--;
30698+
30699+ if (ref->gpuobj->refcount == 0) {
30700+ if (!(ref->gpuobj->flags & NVOBJ_FLAG_ALLOW_NO_REFS))
30701+ nouveau_gpuobj_del(dev, &ref->gpuobj);
30702+ }
30703+ }
30704+
30705+ *pref = NULL;
30706+ drm_free(ref, sizeof(ref), DRM_MEM_DRIVER);
30707+ return 0;
30708+}
30709+
30710+int
30711+nouveau_gpuobj_new_ref(struct drm_device *dev,
30712+ struct nouveau_channel *oc, struct nouveau_channel *rc,
30713+ uint32_t handle, int size, int align, uint32_t flags,
30714+ struct nouveau_gpuobj_ref **ref)
30715+{
30716+ struct nouveau_gpuobj *gpuobj = NULL;
30717+ int ret;
30718+
30719+ if ((ret = nouveau_gpuobj_new(dev, oc, size, align, flags, &gpuobj)))
30720+ return ret;
30721+
30722+ if ((ret = nouveau_gpuobj_ref_add(dev, rc, handle, gpuobj, ref))) {
30723+ nouveau_gpuobj_del(dev, &gpuobj);
30724+ return ret;
30725+ }
30726+
30727+ return 0;
30728+}
30729+
30730+int
30731+nouveau_gpuobj_ref_find(struct nouveau_channel *chan, uint32_t handle,
30732+ struct nouveau_gpuobj_ref **ref_ret)
30733+{
30734+ struct nouveau_gpuobj_ref *ref;
30735+ struct list_head *entry, *tmp;
30736+
30737+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
30738+ ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
30739+
30740+ if (ref->handle == handle) {
30741+ if (ref_ret)
30742+ *ref_ret = ref;
30743+ return 0;
30744+ }
30745+ }
30746+
30747+ return -EINVAL;
30748+}
30749+
30750+int
30751+nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset,
30752+ uint32_t b_offset, uint32_t size,
30753+ uint32_t flags, struct nouveau_gpuobj **pgpuobj,
30754+ struct nouveau_gpuobj_ref **pref)
30755+{
30756+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30757+ struct nouveau_gpuobj *gpuobj = NULL;
30758+ int i;
30759+
30760+ DRM_DEBUG("p_offset=0x%08x b_offset=0x%08x size=0x%08x flags=0x%08x\n",
30761+ p_offset, b_offset, size, flags);
30762+
30763+ gpuobj = drm_calloc(1, sizeof(*gpuobj), DRM_MEM_DRIVER);
30764+ if (!gpuobj)
30765+ return -ENOMEM;
30766+ DRM_DEBUG("gpuobj %p\n", gpuobj);
30767+ gpuobj->im_channel = -1;
30768+ gpuobj->flags = flags | NVOBJ_FLAG_FAKE;
30769+
30770+ list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
30771+
30772+ if (p_offset != ~0) {
30773+ gpuobj->im_pramin = drm_calloc(1, sizeof(struct mem_block),
30774+ DRM_MEM_DRIVER);
30775+ if (!gpuobj->im_pramin) {
30776+ nouveau_gpuobj_del(dev, &gpuobj);
30777+ return -ENOMEM;
30778+ }
30779+ gpuobj->im_pramin->start = p_offset;
30780+ gpuobj->im_pramin->size = size;
30781+ }
30782+
30783+ if (b_offset != ~0) {
30784+ gpuobj->im_backing = drm_calloc(1, sizeof(struct mem_block),
30785+ DRM_MEM_DRIVER);
30786+ if (!gpuobj->im_backing) {
30787+ nouveau_gpuobj_del(dev, &gpuobj);
30788+ return -ENOMEM;
30789+ }
30790+ gpuobj->im_backing->start = b_offset;
30791+ gpuobj->im_backing->size = size;
30792+ }
30793+
30794+ if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
30795+ for (i = 0; i < gpuobj->im_pramin->size; i += 4)
30796+ INSTANCE_WR(gpuobj, i/4, 0);
30797+ }
30798+
30799+ if (pref) {
30800+ if ((i = nouveau_gpuobj_ref_add(dev, NULL, 0, gpuobj, pref))) {
30801+ nouveau_gpuobj_del(dev, &gpuobj);
30802+ return i;
30803+ }
30804+ }
30805+
30806+ if (pgpuobj)
30807+ *pgpuobj = gpuobj;
30808+ return 0;
30809+}
30810+
30811+
30812+static int
30813+nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
30814+{
30815+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30816+
30817+ /*XXX: dodgy hack for now */
30818+ if (dev_priv->card_type >= NV_50)
30819+ return 24;
30820+ if (dev_priv->card_type >= NV_40)
30821+ return 32;
30822+ return 16;
30823+}
30824+
30825+/*
30826+ DMA objects are used to reference a piece of memory in the
30827+ framebuffer, PCI or AGP address space. Each object is 16 bytes big
30828+ and looks as follows:
30829+
30830+ entry[0]
30831+ 11:0 class (seems like I can always use 0 here)
30832+ 12 page table present?
30833+ 13 page entry linear?
30834+ 15:14 access: 0 rw, 1 ro, 2 wo
30835+ 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
30836+ 31:20 dma adjust (bits 0-11 of the address)
30837+ entry[1]
30838+ dma limit (size of transfer)
30839+ entry[X]
30840+ 1 0 readonly, 1 readwrite
30841+ 31:12 dma frame address of the page (bits 12-31 of the address)
30842+ entry[N]
30843+ page table terminator, same value as the first pte, as does nvidia
30844+ rivatv uses 0xffffffff
30845+
30846+ Non linear page tables need a list of frame addresses afterwards,
30847+ the rivatv project has some info on this.
30848+
30849+ The method below creates a DMA object in instance RAM and returns a handle
30850+ to it that can be used to set up context objects.
30851+*/
30852+int
30853+nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class,
30854+ uint64_t offset, uint64_t size, int access,
30855+ int target, struct nouveau_gpuobj **gpuobj)
30856+{
30857+ struct drm_device *dev = chan->dev;
30858+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30859+ int ret;
30860+ uint32_t is_scatter_gather = 0;
30861+
30862+ /* Total number of pages covered by the request.
30863+ */
30864+ const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE;
30865+
30866+
30867+ DRM_DEBUG("ch%d class=0x%04x offset=0x%llx size=0x%llx\n",
30868+ chan->id, class, offset, size);
30869+ DRM_DEBUG("access=%d target=%d\n", access, target);
30870+
30871+ switch (target) {
30872+ case NV_DMA_TARGET_AGP:
30873+ offset += dev_priv->gart_info.aper_base;
30874+ break;
30875+ case NV_DMA_TARGET_PCI_NONLINEAR:
30876+ /*assume the "offset" is a virtual memory address*/
30877+ is_scatter_gather = 1;
30878+ /*put back the right value*/
30879+ target = NV_DMA_TARGET_PCI;
30880+ break;
30881+ default:
30882+ break;
30883+ }
30884+
30885+ ret = nouveau_gpuobj_new(dev, chan,
30886+ is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class),
30887+ 16,
30888+ NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
30889+ gpuobj);
30890+ if (ret) {
30891+ DRM_ERROR("Error creating gpuobj: %d\n", ret);
30892+ return ret;
30893+ }
30894+
30895+ if (dev_priv->card_type < NV_50) {
30896+ uint32_t frame, adjust, pte_flags = 0;
30897+ adjust = offset & 0x00000fff;
30898+ if (access != NV_DMA_ACCESS_RO)
30899+ pte_flags |= (1<<1);
30900+
30901+ if ( ! is_scatter_gather )
30902+ {
30903+ frame = offset & ~0x00000fff;
30904+
30905+ INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) |
30906+ (adjust << 20) |
30907+ (access << 14) |
30908+ (target << 16) |
30909+ class));
30910+ INSTANCE_WR(*gpuobj, 1, size - 1);
30911+ INSTANCE_WR(*gpuobj, 2, frame | pte_flags);
30912+ INSTANCE_WR(*gpuobj, 3, frame | pte_flags);
30913+ }
30914+ else
30915+ {
30916+ /* Intial page entry in the scatter-gather area that
30917+ * corresponds to the base offset
30918+ */
30919+ unsigned int idx = offset / PAGE_SIZE;
30920+
30921+ uint32_t instance_offset;
30922+ unsigned int i;
30923+
30924+ if ((idx + page_count) > dev->sg->pages) {
30925+ DRM_ERROR("Requested page range exceedes "
30926+ "allocated scatter-gather range!");
30927+ return -E2BIG;
30928+ }
30929+
30930+ DRM_DEBUG("Creating PCI DMA object using virtual zone starting at %#llx, size %d\n", offset, (uint32_t)size);
30931+ INSTANCE_WR(*gpuobj, 0, ((1<<12) | (0<<13) |
30932+ (adjust << 20) |
30933+ (access << 14) |
30934+ (target << 16) |
30935+ class));
30936+ INSTANCE_WR(*gpuobj, 1, (uint32_t) size-1);
30937+
30938+
30939+ /*write starting at the third dword*/
30940+ instance_offset = 2;
30941+
30942+ /*for each PAGE, get its bus address, fill in the page table entry, and advance*/
30943+ for (i = 0; i < page_count; i++) {
30944+ if (dev->sg->busaddr[idx] == 0) {
30945+ dev->sg->busaddr[idx] =
30946+ pci_map_page(dev->pdev,
30947+ dev->sg->pagelist[idx],
30948+ 0,
30949+ PAGE_SIZE,
30950+ DMA_BIDIRECTIONAL);
30951+
30952+ if (dma_mapping_error(dev->sg->busaddr[idx])) {
30953+ return -ENOMEM;
30954+ }
30955+ }
30956+
30957+ frame = (uint32_t) dev->sg->busaddr[idx];
30958+ INSTANCE_WR(*gpuobj, instance_offset,
30959+ frame | pte_flags);
30960+
30961+ idx++;
30962+ instance_offset ++;
30963+ }
30964+ }
30965+ } else {
30966+ uint32_t flags0, flags5;
30967+
30968+ if (target == NV_DMA_TARGET_VIDMEM) {
30969+ flags0 = 0x00190000;
30970+ flags5 = 0x00010000;
30971+ } else {
30972+ flags0 = 0x7fc00000;
30973+ flags5 = 0x00080000;
30974+ }
30975+
30976+ INSTANCE_WR(*gpuobj, 0, flags0 | class);
30977+ INSTANCE_WR(*gpuobj, 1, offset + size - 1);
30978+ INSTANCE_WR(*gpuobj, 2, offset);
30979+ INSTANCE_WR(*gpuobj, 5, flags5);
30980+ }
30981+
30982+ (*gpuobj)->engine = NVOBJ_ENGINE_SW;
30983+ (*gpuobj)->class = class;
30984+ return 0;
30985+}
30986+
30987+int
30988+nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan,
30989+ uint64_t offset, uint64_t size, int access,
30990+ struct nouveau_gpuobj **gpuobj,
30991+ uint32_t *o_ret)
30992+{
30993+ struct drm_device *dev = chan->dev;
30994+ struct drm_nouveau_private *dev_priv = dev->dev_private;
30995+ int ret;
30996+
30997+ if (dev_priv->gart_info.type == NOUVEAU_GART_AGP ||
30998+ (dev_priv->card_type >= NV_50 &&
30999+ dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) {
31000+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
31001+ offset, size, access,
31002+ NV_DMA_TARGET_AGP, gpuobj);
31003+ if (o_ret)
31004+ *o_ret = 0;
31005+ } else
31006+ if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
31007+ *gpuobj = dev_priv->gart_info.sg_ctxdma;
31008+ if (offset & ~0xffffffffULL) {
31009+ DRM_ERROR("obj offset exceeds 32-bits\n");
31010+ return -EINVAL;
31011+ }
31012+ if (o_ret)
31013+ *o_ret = (uint32_t)offset;
31014+ ret = (*gpuobj != NULL) ? 0 : -EINVAL;
31015+ } else {
31016+ DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type);
31017+ return -EINVAL;
31018+ }
31019+
31020+ return ret;
31021+}
31022+
31023+/* Context objects in the instance RAM have the following structure.
31024+ * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
31025+
31026+ NV4 - NV30:
31027+
31028+ entry[0]
31029+ 11:0 class
31030+ 12 chroma key enable
31031+ 13 user clip enable
31032+ 14 swizzle enable
31033+ 17:15 patch config:
31034+ scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
31035+ 18 synchronize enable
31036+ 19 endian: 1 big, 0 little
31037+ 21:20 dither mode
31038+ 23 single step enable
31039+ 24 patch status: 0 invalid, 1 valid
31040+ 25 context_surface 0: 1 valid
31041+ 26 context surface 1: 1 valid
31042+ 27 context pattern: 1 valid
31043+ 28 context rop: 1 valid
31044+ 29,30 context beta, beta4
31045+ entry[1]
31046+ 7:0 mono format
31047+ 15:8 color format
31048+ 31:16 notify instance address
31049+ entry[2]
31050+ 15:0 dma 0 instance address
31051+ 31:16 dma 1 instance address
31052+ entry[3]
31053+ dma method traps
31054+
31055+ NV40:
31056+ No idea what the exact format is. Here's what can be deducted:
31057+
31058+ entry[0]:
31059+ 11:0 class (maybe uses more bits here?)
31060+ 17 user clip enable
31061+ 21:19 patch config
31062+ 25 patch status valid ?
31063+ entry[1]:
31064+ 15:0 DMA notifier (maybe 20:0)
31065+ entry[2]:
31066+ 15:0 DMA 0 instance (maybe 20:0)
31067+ 24 big endian
31068+ entry[3]:
31069+ 15:0 DMA 1 instance (maybe 20:0)
31070+ entry[4]:
31071+ entry[5]:
31072+ set to 0?
31073+*/
31074+int
31075+nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class,
31076+ struct nouveau_gpuobj **gpuobj)
31077+{
31078+ struct drm_device *dev = chan->dev;
31079+ struct drm_nouveau_private *dev_priv = dev->dev_private;
31080+ int ret;
31081+
31082+ DRM_DEBUG("ch%d class=0x%04x\n", chan->id, class);
31083+
31084+ ret = nouveau_gpuobj_new(dev, chan,
31085+ nouveau_gpuobj_class_instmem_size(dev, class),
31086+ 16,
31087+ NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
31088+ gpuobj);
31089+ if (ret) {
31090+ DRM_ERROR("Error creating gpuobj: %d\n", ret);
31091+ return ret;
31092+ }
31093+
31094+ if (dev_priv->card_type >= NV_50) {
31095+ INSTANCE_WR(*gpuobj, 0, class);
31096+ INSTANCE_WR(*gpuobj, 5, 0x00010000);
31097+ } else {
31098+ switch (class) {
31099+ case NV_CLASS_NULL:
31100+ INSTANCE_WR(*gpuobj, 0, 0x00001030);
31101+ INSTANCE_WR(*gpuobj, 1, 0xFFFFFFFF);
31102+ break;
31103+ default:
31104+ if (dev_priv->card_type >= NV_40) {
31105+ INSTANCE_WR(*gpuobj, 0, class);
31106+#ifdef __BIG_ENDIAN
31107+ INSTANCE_WR(*gpuobj, 2, 0x01000000);
31108+#endif
31109+ } else {
31110+#ifdef __BIG_ENDIAN
31111+ INSTANCE_WR(*gpuobj, 0, class | 0x00080000);
31112+#else
31113+ INSTANCE_WR(*gpuobj, 0, class);
31114+#endif
31115+ }
31116+ }
31117+ }
31118+
31119+ (*gpuobj)->engine = NVOBJ_ENGINE_GR;
31120+ (*gpuobj)->class = class;
31121+ return 0;
31122+}
31123+
31124+static int
31125+nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
31126+{
31127+ struct drm_device *dev = chan->dev;
31128+ struct drm_nouveau_private *dev_priv = dev->dev_private;
31129+ struct nouveau_gpuobj *pramin = NULL;
31130+ int size, base, ret;
31131+
31132+ DRM_DEBUG("ch%d\n", chan->id);
31133+
31134+ /* Base amount for object storage (4KiB enough?) */
31135+ size = 0x1000;
31136+ base = 0;
31137+
31138+ /* PGRAPH context */
31139+
31140+ if (dev_priv->card_type == NV_50) {
31141+ /* Various fixed table thingos */
31142+ size += 0x1400; /* mostly unknown stuff */
31143+ size += 0x4000; /* vm pd */
31144+ base = 0x6000;
31145+ /* RAMHT, not sure about setting size yet, 32KiB to be safe */
31146+ size += 0x8000;
31147+ /* RAMFC */
31148+ size += 0x1000;
31149+ /* PGRAPH context */
31150+ size += 0x60000;
31151+ }
31152+
31153+ DRM_DEBUG("ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n",
31154+ chan->id, size, base);
31155+ ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0,
31156+ &chan->ramin);
31157+ if (ret) {
31158+ DRM_ERROR("Error allocating channel PRAMIN: %d\n", ret);
31159+ return ret;
31160+ }
31161+ pramin = chan->ramin->gpuobj;
31162+
31163+ ret = nouveau_mem_init_heap(&chan->ramin_heap,
31164+ pramin->im_pramin->start + base, size);
31165+ if (ret) {
31166+ DRM_ERROR("Error creating PRAMIN heap: %d\n", ret);
31167+ nouveau_gpuobj_ref_del(dev, &chan->ramin);
31168+ return ret;
31169+ }
31170+
31171+ return 0;
31172+}
31173+
31174+int
31175+nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
31176+ uint32_t vram_h, uint32_t tt_h)
31177+{
31178+ struct drm_device *dev = chan->dev;
31179+ struct drm_nouveau_private *dev_priv = dev->dev_private;
31180+ struct nouveau_gpuobj *vram = NULL, *tt = NULL;
31181+ int ret, i;
31182+
31183+ INIT_LIST_HEAD(&chan->ramht_refs);
31184+
31185+ DRM_DEBUG("ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
31186+
31187+ /* Reserve a block of PRAMIN for the channel
31188+ *XXX: maybe on <NV50 too at some point
31189+ */
31190+ if (0 || dev_priv->card_type == NV_50) {
31191+ ret = nouveau_gpuobj_channel_init_pramin(chan);
31192+ if (ret)
31193+ return ret;
31194+ }
31195+
31196+ /* NV50 VM, point offset 0-512MiB at shared PCIEGART table */
31197+ if (dev_priv->card_type >= NV_50) {
31198+ uint32_t vm_offset;
31199+
31200+ vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
31201+ vm_offset += chan->ramin->gpuobj->im_pramin->start;
31202+ if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,
31203+ 0, &chan->vm_pd, NULL)))
31204+ return ret;
31205+ for (i=0; i<0x4000; i+=8) {
31206+ INSTANCE_WR(chan->vm_pd, (i+0)/4, 0x00000000);
31207+ INSTANCE_WR(chan->vm_pd, (i+4)/4, 0xdeadcafe);
31208+ }
31209+
31210+ if ((ret = nouveau_gpuobj_ref_add(dev, NULL, 0,
31211+ dev_priv->gart_info.sg_ctxdma,
31212+ &chan->vm_gart_pt)))
31213+ return ret;
31214+ INSTANCE_WR(chan->vm_pd, (0+0)/4,
31215+ chan->vm_gart_pt->instance | 0x03);
31216+ INSTANCE_WR(chan->vm_pd, (0+4)/4, 0x00000000);
31217+ }
31218+
31219+ /* RAMHT */
31220+ if (dev_priv->card_type < NV_50) {
31221+ ret = nouveau_gpuobj_ref_add(dev, NULL, 0, dev_priv->ramht,
31222+ &chan->ramht);
31223+ if (ret)
31224+ return ret;
31225+ } else {
31226+ ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0,
31227+ 0x8000, 16,
31228+ NVOBJ_FLAG_ZERO_ALLOC,
31229+ &chan->ramht);
31230+ if (ret)
31231+ return ret;
31232+ }
31233+
31234+ /* VRAM ctxdma */
31235+ if ((ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
31236+ 0, dev_priv->fb_available_size,
31237+ NV_DMA_ACCESS_RW,
31238+ NV_DMA_TARGET_VIDMEM, &vram))) {
31239+ DRM_ERROR("Error creating VRAM ctxdma: %d\n", ret);
31240+ return ret;
31241+ }
31242+
31243+ if ((ret = nouveau_gpuobj_ref_add(dev, chan, vram_h, vram, NULL))) {
31244+ DRM_ERROR("Error referencing VRAM ctxdma: %d\n", ret);
31245+ return ret;
31246+ }
31247+
31248+ /* TT memory ctxdma */
31249+ if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) {
31250+ ret = nouveau_gpuobj_gart_dma_new(chan, 0,
31251+ dev_priv->gart_info.aper_size,
31252+ NV_DMA_ACCESS_RW, &tt, NULL);
31253+ } else
31254+ if (dev_priv->pci_heap) {
31255+ ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
31256+ 0, dev->sg->pages * PAGE_SIZE,
31257+ NV_DMA_ACCESS_RW,
31258+ NV_DMA_TARGET_PCI_NONLINEAR, &tt);
31259+ } else {
31260+ DRM_ERROR("Invalid GART type %d\n", dev_priv->gart_info.type);
31261+ ret = -EINVAL;
31262+ }
31263+
31264+ if (ret) {
31265+ DRM_ERROR("Error creating TT ctxdma: %d\n", ret);
31266+ return ret;
31267+ }
31268+
31269+ ret = nouveau_gpuobj_ref_add(dev, chan, tt_h, tt, NULL);
31270+ if (ret) {
31271+ DRM_ERROR("Error referencing TT ctxdma: %d\n", ret);
31272+ return ret;
31273+ }
31274+
31275+ return 0;
31276+}
31277+
31278+void
31279+nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
31280+{
31281+ struct drm_device *dev = chan->dev;
31282+ struct list_head *entry, *tmp;
31283+ struct nouveau_gpuobj_ref *ref;
31284+
31285+ DRM_DEBUG("ch%d\n", chan->id);
31286+
31287+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
31288+ ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
31289+
31290+ nouveau_gpuobj_ref_del(dev, &ref);
31291+ }
31292+
31293+ nouveau_gpuobj_ref_del(dev, &chan->ramht);
31294+
31295+ nouveau_gpuobj_del(dev, &chan->vm_pd);
31296+ nouveau_gpuobj_ref_del(dev, &chan->vm_gart_pt);
31297+
31298+ if (chan->ramin_heap)
31299+ nouveau_mem_takedown(&chan->ramin_heap);
31300+ if (chan->ramin)
31301+ nouveau_gpuobj_ref_del(dev, &chan->ramin);
31302+
31303+}
31304+
31305+int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
31306+ struct drm_file *file_priv)
31307+{
31308+ struct nouveau_channel *chan;
31309+ struct drm_nouveau_grobj_alloc *init = data;
31310+ struct nouveau_gpuobj *gr = NULL;
31311+ int ret;
31312+
31313+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
31314+ NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
31315+
31316+ //FIXME: check args, only allow trusted objects to be created
31317+
31318+ if (init->handle == ~0)
31319+ return -EINVAL;
31320+
31321+ if (nouveau_gpuobj_ref_find(chan, init->handle, NULL) == 0)
31322+ return -EEXIST;
31323+
31324+ ret = nouveau_gpuobj_gr_new(chan, init->class, &gr);
31325+ if (ret) {
31326+ DRM_ERROR("Error creating gr object: %d (%d/0x%08x)\n",
31327+ ret, init->channel, init->handle);
31328+ return ret;
31329+ }
31330+
31331+ if ((ret = nouveau_gpuobj_ref_add(dev, chan, init->handle, gr, NULL))) {
31332+ DRM_ERROR("Error referencing gr object: %d (%d/0x%08x\n)",
31333+ ret, init->channel, init->handle);
31334+ nouveau_gpuobj_del(dev, &gr);
31335+ return ret;
31336+ }
31337+
31338+ return 0;
31339+}
31340+
31341+int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
31342+ struct drm_file *file_priv)
31343+{
31344+ struct drm_nouveau_gpuobj_free *objfree = data;
31345+ struct nouveau_gpuobj_ref *ref;
31346+ struct nouveau_channel *chan;
31347+ int ret;
31348+
31349+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
31350+ NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan);
31351+
31352+ if ((ret = nouveau_gpuobj_ref_find(chan, objfree->handle, &ref)))
31353+ return ret;
31354+ nouveau_gpuobj_ref_del(dev, &ref);
31355+
31356+ return 0;
31357+}
31358+
31359Index: git/shared-core/nouveau_reg.h
31360===================================================================
31361--- /dev/null 1970-01-01 00:00:00.000000000 +0000
31362+++ git/shared-core/nouveau_reg.h 2008-12-12 17:35:22.000000000 +0000
31363@@ -0,0 +1,550 @@
31364+
31365+
31366+#define NV03_BOOT_0 0x00100000
31367+# define NV03_BOOT_0_RAM_AMOUNT 0x00000003
31368+# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
31369+# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
31370+# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
31371+# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
31372+# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
31373+# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
31374+# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
31375+# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
31376+
31377+#define NV04_FIFO_DATA 0x0010020c
31378+# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
31379+# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
31380+
31381+#define NV_RAMIN 0x00700000
31382+
31383+#define NV_RAMHT_HANDLE_OFFSET 0
31384+#define NV_RAMHT_CONTEXT_OFFSET 4
31385+# define NV_RAMHT_CONTEXT_VALID (1<<31)
31386+# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
31387+# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
31388+# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
31389+# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
31390+# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
31391+# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
31392+# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
31393+# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
31394+
31395+/* DMA object defines */
31396+#define NV_DMA_ACCESS_RW 0
31397+#define NV_DMA_ACCESS_RO 1
31398+#define NV_DMA_ACCESS_WO 2
31399+#define NV_DMA_TARGET_VIDMEM 0
31400+#define NV_DMA_TARGET_PCI 2
31401+#define NV_DMA_TARGET_AGP 3
31402+/*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/
31403+#define NV_DMA_TARGET_PCI_NONLINEAR 8
31404+
31405+/* Some object classes we care about in the drm */
31406+#define NV_CLASS_DMA_FROM_MEMORY 0x00000002
31407+#define NV_CLASS_DMA_TO_MEMORY 0x00000003
31408+#define NV_CLASS_NULL 0x00000030
31409+#define NV_CLASS_DMA_IN_MEMORY 0x0000003D
31410+
31411+#define NV03_FIFO_SIZE 0x8000UL
31412+#define NV_MAX_FIFO_NUMBER 128
31413+#define NV03_FIFO_REGS_SIZE 0x10000
31414+#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
31415+# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
31416+# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
31417+#define NV50_FIFO_REGS_SIZE 0x2000
31418+#define NV50_FIFO_REGS(i) (0x00c00000+i*NV50_FIFO_REGS_SIZE)
31419+# define NV50_FIFO_REGS_DMAPUT(i) (NV50_FIFO_REGS(i)+0x40)
31420+# define NV50_FIFO_REGS_DMAGET(i) (NV50_FIFO_REGS(i)+0x44)
31421+
31422+#define NV03_PMC_BOOT_0 0x00000000
31423+#define NV03_PMC_INTR_0 0x00000100
31424+# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
31425+# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
31426+# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
31427+# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
31428+# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
31429+#define NV03_PMC_INTR_EN_0 0x00000140
31430+# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
31431+#define NV03_PMC_ENABLE 0x00000200
31432+# define NV_PMC_ENABLE_PFIFO (1<< 8)
31433+# define NV_PMC_ENABLE_PGRAPH (1<<12)
31434+/* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
31435+ * the card will hang early on in the X init process.
31436+ */
31437+# define NV_PMC_ENABLE_UNK13 (1<<13)
31438+#define NV40_PMC_1700 0x00001700
31439+#define NV40_PMC_1704 0x00001704
31440+#define NV40_PMC_1708 0x00001708
31441+#define NV40_PMC_170C 0x0000170C
31442+
31443+/* probably PMC ? */
31444+#define NV50_PUNK_BAR0_PRAMIN 0x00001700
31445+#define NV50_PUNK_BAR_CFG_BASE 0x00001704
31446+#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30)
31447+#define NV50_PUNK_BAR1_CTXDMA 0x00001708
31448+#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31)
31449+#define NV50_PUNK_BAR3_CTXDMA 0x0000170C
31450+#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31)
31451+#define NV50_PUNK_UNK1710 0x00001710
31452+
31453+#define NV04_PTIMER_INTR_0 0x00009100
31454+#define NV04_PTIMER_INTR_EN_0 0x00009140
31455+#define NV04_PTIMER_NUMERATOR 0x00009200
31456+#define NV04_PTIMER_DENOMINATOR 0x00009210
31457+#define NV04_PTIMER_TIME_0 0x00009400
31458+#define NV04_PTIMER_TIME_1 0x00009410
31459+#define NV04_PTIMER_ALARM_0 0x00009420
31460+
31461+#define NV04_PFB_CFG0 0x00100200
31462+#define NV04_PFB_CFG1 0x00100204
31463+#define NV40_PFB_020C 0x0010020C
31464+#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
31465+#define NV10_PFB_TILE__SIZE 8
31466+#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
31467+#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
31468+#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
31469+#define NV10_PFB_CLOSE_PAGE2 0x0010033C
31470+#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
31471+#define NV40_PFB_TILE__SIZE_0 12
31472+#define NV40_PFB_TILE__SIZE_1 15
31473+#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
31474+#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
31475+#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
31476+
31477+#define NV04_PGRAPH_DEBUG_0 0x00400080
31478+#define NV04_PGRAPH_DEBUG_1 0x00400084
31479+#define NV04_PGRAPH_DEBUG_2 0x00400088
31480+#define NV04_PGRAPH_DEBUG_3 0x0040008c
31481+#define NV10_PGRAPH_DEBUG_4 0x00400090
31482+#define NV03_PGRAPH_INTR 0x00400100
31483+#define NV03_PGRAPH_NSTATUS 0x00400104
31484+# define NV03_PGRAPH_NSTATUS_STATE_IN_USE (1<<23)
31485+# define NV03_PGRAPH_NSTATUS_INVALID_STATE (1<<24)
31486+# define NV03_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25)
31487+# define NV03_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26)
31488+#define NV03_PGRAPH_NSOURCE 0x00400108
31489+# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0)
31490+# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1)
31491+# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2)
31492+# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3)
31493+# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4)
31494+# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5)
31495+# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6)
31496+# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7)
31497+# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8)
31498+# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9)
31499+# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10)
31500+# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11)
31501+# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12)
31502+# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13)
31503+# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14)
31504+# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15)
31505+# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16)
31506+# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17)
31507+# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18)
31508+#define NV03_PGRAPH_INTR_EN 0x00400140
31509+#define NV40_PGRAPH_INTR_EN 0x0040013C
31510+# define NV_PGRAPH_INTR_NOTIFY (1<< 0)
31511+# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
31512+# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
31513+# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
31514+# define NV_PGRAPH_INTR_ERROR (1<<20)
31515+#define NV10_PGRAPH_CTX_CONTROL 0x00400144
31516+#define NV10_PGRAPH_CTX_USER 0x00400148
31517+#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
31518+#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
31519+#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
31520+#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
31521+#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
31522+#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
31523+#define NV10_PGRAPH_CTX_CACHE1 0x00400160
31524+#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
31525+#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
31526+#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
31527+#define NV04_PGRAPH_CTX_CONTROL 0x00400170
31528+#define NV04_PGRAPH_CTX_USER 0x00400174
31529+#define NV04_PGRAPH_CTX_CACHE1 0x00400180
31530+#define NV10_PGRAPH_CTX_CACHE2 0x00400180
31531+#define NV03_PGRAPH_CTX_CONTROL 0x00400190
31532+#define NV03_PGRAPH_CTX_USER 0x00400194
31533+#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
31534+#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
31535+#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
31536+#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
31537+#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
31538+#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
31539+#define NV40_PGRAPH_CTXCTL_0304 0x00400304
31540+#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001
31541+#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308
31542+#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000
31543+#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24
31544+#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff
31545+#define NV40_PGRAPH_CTXCTL_0310 0x00400310
31546+#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020
31547+#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040
31548+#define NV40_PGRAPH_CTXCTL_030C 0x0040030c
31549+#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324
31550+#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328
31551+#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c
31552+#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000
31553+#define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF
31554+#define NV03_PGRAPH_ABS_X_RAM 0x00400400
31555+#define NV03_PGRAPH_ABS_Y_RAM 0x00400480
31556+#define NV03_PGRAPH_X_MISC 0x00400500
31557+#define NV03_PGRAPH_Y_MISC 0x00400504
31558+#define NV04_PGRAPH_VALID1 0x00400508
31559+#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
31560+#define NV04_PGRAPH_MISC24_0 0x00400510
31561+#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
31562+#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
31563+#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
31564+#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
31565+#define NV03_PGRAPH_CLIPX_0 0x00400524
31566+#define NV03_PGRAPH_CLIPX_1 0x00400528
31567+#define NV03_PGRAPH_CLIPY_0 0x0040052C
31568+#define NV03_PGRAPH_CLIPY_1 0x00400530
31569+#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
31570+#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
31571+#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
31572+#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
31573+#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
31574+#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
31575+#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
31576+#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
31577+#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
31578+#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
31579+#define NV04_PGRAPH_MISC24_1 0x00400570
31580+#define NV04_PGRAPH_MISC24_2 0x00400574
31581+#define NV04_PGRAPH_VALID2 0x00400578
31582+#define NV04_PGRAPH_PASSTHRU_0 0x0040057C
31583+#define NV04_PGRAPH_PASSTHRU_1 0x00400580
31584+#define NV04_PGRAPH_PASSTHRU_2 0x00400584
31585+#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
31586+#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
31587+#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
31588+#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
31589+#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
31590+#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C
31591+#define NV04_PGRAPH_FORMAT_0 0x004005A8
31592+#define NV04_PGRAPH_FORMAT_1 0x004005AC
31593+#define NV04_PGRAPH_FILTER_0 0x004005B0
31594+#define NV04_PGRAPH_FILTER_1 0x004005B4
31595+#define NV03_PGRAPH_MONO_COLOR0 0x00400600
31596+#define NV04_PGRAPH_ROP3 0x00400604
31597+#define NV04_PGRAPH_BETA_AND 0x00400608
31598+#define NV04_PGRAPH_BETA_PREMULT 0x0040060C
31599+#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610
31600+#define NV04_PGRAPH_FORMATS 0x00400618
31601+#define NV10_PGRAPH_DEBUG_2 0x00400620
31602+#define NV04_PGRAPH_BOFFSET0 0x00400640
31603+#define NV04_PGRAPH_BOFFSET1 0x00400644
31604+#define NV04_PGRAPH_BOFFSET2 0x00400648
31605+#define NV04_PGRAPH_BOFFSET3 0x0040064C
31606+#define NV04_PGRAPH_BOFFSET4 0x00400650
31607+#define NV04_PGRAPH_BOFFSET5 0x00400654
31608+#define NV04_PGRAPH_BBASE0 0x00400658
31609+#define NV04_PGRAPH_BBASE1 0x0040065C
31610+#define NV04_PGRAPH_BBASE2 0x00400660
31611+#define NV04_PGRAPH_BBASE3 0x00400664
31612+#define NV04_PGRAPH_BBASE4 0x00400668
31613+#define NV04_PGRAPH_BBASE5 0x0040066C
31614+#define NV04_PGRAPH_BPITCH0 0x00400670
31615+#define NV04_PGRAPH_BPITCH1 0x00400674
31616+#define NV04_PGRAPH_BPITCH2 0x00400678
31617+#define NV04_PGRAPH_BPITCH3 0x0040067C
31618+#define NV04_PGRAPH_BPITCH4 0x00400680
31619+#define NV04_PGRAPH_BLIMIT0 0x00400684
31620+#define NV04_PGRAPH_BLIMIT1 0x00400688
31621+#define NV04_PGRAPH_BLIMIT2 0x0040068C
31622+#define NV04_PGRAPH_BLIMIT3 0x00400690
31623+#define NV04_PGRAPH_BLIMIT4 0x00400694
31624+#define NV04_PGRAPH_BLIMIT5 0x00400698
31625+#define NV04_PGRAPH_BSWIZZLE2 0x0040069C
31626+#define NV04_PGRAPH_BSWIZZLE5 0x004006A0
31627+#define NV03_PGRAPH_STATUS 0x004006B0
31628+#define NV04_PGRAPH_STATUS 0x00400700
31629+#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704
31630+#define NV04_PGRAPH_TRAPPED_DATA 0x00400708
31631+#define NV04_PGRAPH_SURFACE 0x0040070C
31632+#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C
31633+#define NV04_PGRAPH_STATE 0x00400710
31634+#define NV10_PGRAPH_SURFACE 0x00400710
31635+#define NV04_PGRAPH_NOTIFY 0x00400714
31636+#define NV10_PGRAPH_STATE 0x00400714
31637+#define NV10_PGRAPH_NOTIFY 0x00400718
31638+
31639+#define NV04_PGRAPH_FIFO 0x00400720
31640+
31641+#define NV04_PGRAPH_BPIXEL 0x00400724
31642+#define NV10_PGRAPH_RDI_INDEX 0x00400750
31643+#define NV04_PGRAPH_FFINTFC_ST2 0x00400754
31644+#define NV10_PGRAPH_RDI_DATA 0x00400754
31645+#define NV04_PGRAPH_DMA_PITCH 0x00400760
31646+#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
31647+#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
31648+#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
31649+#define NV10_PGRAPH_DMA_PITCH 0x00400770
31650+#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
31651+#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
31652+#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
31653+#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
31654+#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784
31655+#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
31656+#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788
31657+#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001
31658+#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002
31659+#define NV04_PGRAPH_PATT_COLOR0 0x00400800
31660+#define NV04_PGRAPH_PATT_COLOR1 0x00400804
31661+#define NV04_PGRAPH_PATTERN 0x00400808
31662+#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
31663+#define NV04_PGRAPH_CHROMA 0x00400814
31664+#define NV04_PGRAPH_CONTROL0 0x00400818
31665+#define NV04_PGRAPH_CONTROL1 0x0040081C
31666+#define NV04_PGRAPH_CONTROL2 0x00400820
31667+#define NV04_PGRAPH_BLEND 0x00400824
31668+#define NV04_PGRAPH_STORED_FMT 0x00400830
31669+#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
31670+#define NV40_PGRAPH_TILE0(i) 0x00400900
31671+#define NV40_PGRAPH_TLIMIT0(i) 0x00400904
31672+#define NV40_PGRAPH_TSIZE0(i) 0x00400908
31673+#define NV40_PGRAPH_TSTATUS0(i) 0x0040090C
31674+#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
31675+#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
31676+#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
31677+#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
31678+#define NV04_PGRAPH_U_RAM 0x00400D00
31679+#define NV47_PGRAPH_TILE0(i) 0x00400D00
31680+#define NV47_PGRAPH_TLIMIT0(i) 0x00400D04
31681+#define NV47_PGRAPH_TSIZE0(i) 0x00400D08
31682+#define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C
31683+#define NV04_PGRAPH_V_RAM 0x00400D40
31684+#define NV04_PGRAPH_W_RAM 0x00400D80
31685+#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40
31686+#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44
31687+#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48
31688+#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C
31689+#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50
31690+#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54
31691+#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58
31692+#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C
31693+#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60
31694+#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64
31695+#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68
31696+#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C
31697+#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
31698+#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
31699+#define NV10_PGRAPH_XFMODE0 0x00400F40
31700+#define NV10_PGRAPH_XFMODE1 0x00400F44
31701+#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
31702+#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
31703+#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
31704+#define NV10_PGRAPH_PIPE_DATA 0x00400F54
31705+#define NV04_PGRAPH_DMA_START_0 0x00401000
31706+#define NV04_PGRAPH_DMA_START_1 0x00401004
31707+#define NV04_PGRAPH_DMA_LENGTH 0x00401008
31708+#define NV04_PGRAPH_DMA_MISC 0x0040100C
31709+#define NV04_PGRAPH_DMA_DATA_0 0x00401020
31710+#define NV04_PGRAPH_DMA_DATA_1 0x00401024
31711+#define NV04_PGRAPH_DMA_RM 0x00401030
31712+#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
31713+#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
31714+#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
31715+#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
31716+#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
31717+#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
31718+#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
31719+#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
31720+#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
31721+#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
31722+#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
31723+#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
31724+#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
31725+#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
31726+#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
31727+#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
31728+#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
31729+#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
31730+#define NV40_PGRAPH_TILE1(i) 0x00406900
31731+#define NV40_PGRAPH_TLIMIT1(i) 0x00406904
31732+#define NV40_PGRAPH_TSIZE1(i) 0x00406908
31733+#define NV40_PGRAPH_TSTATUS1(i) 0x0040690C
31734+
31735+
31736+/* It's a guess that this works on NV03. Confirmed on NV04, though */
31737+#define NV04_PFIFO_DELAY_0 0x00002040
31738+#define NV04_PFIFO_DMA_TIMESLICE 0x00002044
31739+#define NV04_PFIFO_NEXT_CHANNEL 0x00002050
31740+#define NV03_PFIFO_INTR_0 0x00002100
31741+#define NV03_PFIFO_INTR_EN_0 0x00002140
31742+# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
31743+# define NV_PFIFO_INTR_RUNOUT (1<< 4)
31744+# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
31745+# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
31746+# define NV_PFIFO_INTR_DMA_PT (1<<16)
31747+# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
31748+# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
31749+#define NV03_PFIFO_RAMHT 0x00002210
31750+#define NV03_PFIFO_RAMFC 0x00002214
31751+#define NV03_PFIFO_RAMRO 0x00002218
31752+#define NV40_PFIFO_RAMFC 0x00002220
31753+#define NV03_PFIFO_CACHES 0x00002500
31754+#define NV04_PFIFO_MODE 0x00002504
31755+#define NV04_PFIFO_DMA 0x00002508
31756+#define NV04_PFIFO_SIZE 0x0000250c
31757+#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)
31758+#define NV50_PFIFO_CTX_TABLE__SIZE 128
31759+#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31)
31760+#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30)
31761+#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF
31762+#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF
31763+#define NV03_PFIFO_CACHE0_PUSH0 0x00003000
31764+#define NV03_PFIFO_CACHE0_PULL0 0x00003040
31765+#define NV04_PFIFO_CACHE0_PULL0 0x00003050
31766+#define NV04_PFIFO_CACHE0_PULL1 0x00003054
31767+#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
31768+#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
31769+#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
31770+#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
31771+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
31772+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
31773+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
31774+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
31775+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
31776+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
31777+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
31778+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
31779+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
31780+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
31781+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
31782+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
31783+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
31784+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
31785+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
31786+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
31787+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
31788+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
31789+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
31790+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
31791+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
31792+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
31793+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
31794+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
31795+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
31796+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
31797+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
31798+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
31799+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
31800+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
31801+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
31802+# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
31803+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
31804+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
31805+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
31806+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
31807+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
31808+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
31809+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
31810+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
31811+# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
31812+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
31813+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
31814+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
31815+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
31816+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
31817+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
31818+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
31819+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
31820+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
31821+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
31822+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
31823+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
31824+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
31825+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
31826+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
31827+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
31828+# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
31829+# define NV_PFIFO_CACHE1_ENDIAN 0x80000000
31830+# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
31831+# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
31832+#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
31833+#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
31834+#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
31835+#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
31836+#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
31837+#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
31838+#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
31839+#define NV03_PFIFO_CACHE1_PULL0 0x00003240
31840+#define NV04_PFIFO_CACHE1_PULL0 0x00003250
31841+#define NV03_PFIFO_CACHE1_PULL1 0x00003250
31842+#define NV04_PFIFO_CACHE1_PULL1 0x00003254
31843+#define NV04_PFIFO_CACHE1_HASH 0x00003258
31844+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
31845+#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
31846+#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
31847+#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
31848+#define NV03_PFIFO_CACHE1_GET 0x00003270
31849+#define NV04_PFIFO_CACHE1_ENGINE 0x00003280
31850+#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
31851+#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
31852+#define NV40_PFIFO_UNK32E4 0x000032E4
31853+#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
31854+#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
31855+#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
31856+#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
31857+
31858+#define NV_CRTC0_INTSTAT 0x00600100
31859+#define NV_CRTC0_INTEN 0x00600140
31860+#define NV_CRTC1_INTSTAT 0x00602100
31861+#define NV_CRTC1_INTEN 0x00602140
31862+# define NV_CRTC_INTR_VBLANK (1<<0)
31863+
31864+/* Fifo commands. These are not regs, neither masks */
31865+#define NV03_FIFO_CMD_JUMP 0x20000000
31866+#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
31867+#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
31868+
31869+/* RAMFC offsets */
31870+#define NV04_RAMFC_DMA_PUT 0x00
31871+#define NV04_RAMFC_DMA_GET 0x04
31872+#define NV04_RAMFC_DMA_INSTANCE 0x08
31873+#define NV04_RAMFC_DMA_STATE 0x0C
31874+#define NV04_RAMFC_DMA_FETCH 0x10
31875+#define NV04_RAMFC_ENGINE 0x14
31876+#define NV04_RAMFC_PULL1_ENGINE 0x18
31877+
31878+#define NV10_RAMFC_DMA_PUT 0x00
31879+#define NV10_RAMFC_DMA_GET 0x04
31880+#define NV10_RAMFC_REF_CNT 0x08
31881+#define NV10_RAMFC_DMA_INSTANCE 0x0C
31882+#define NV10_RAMFC_DMA_STATE 0x10
31883+#define NV10_RAMFC_DMA_FETCH 0x14
31884+#define NV10_RAMFC_ENGINE 0x18
31885+#define NV10_RAMFC_PULL1_ENGINE 0x1C
31886+#define NV10_RAMFC_ACQUIRE_VALUE 0x20
31887+#define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24
31888+#define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28
31889+#define NV10_RAMFC_SEMAPHORE 0x2C
31890+#define NV10_RAMFC_DMA_SUBROUTINE 0x30
31891+
31892+#define NV40_RAMFC_DMA_PUT 0x00
31893+#define NV40_RAMFC_DMA_GET 0x04
31894+#define NV40_RAMFC_REF_CNT 0x08
31895+#define NV40_RAMFC_DMA_INSTANCE 0x0C
31896+#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
31897+#define NV40_RAMFC_DMA_STATE 0x14
31898+#define NV40_RAMFC_DMA_FETCH 0x18
31899+#define NV40_RAMFC_ENGINE 0x1C
31900+#define NV40_RAMFC_PULL1_ENGINE 0x20
31901+#define NV40_RAMFC_ACQUIRE_VALUE 0x24
31902+#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
31903+#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
31904+#define NV40_RAMFC_SEMAPHORE 0x30
31905+#define NV40_RAMFC_DMA_SUBROUTINE 0x34
31906+#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
31907+#define NV40_RAMFC_DMA_TIMESLICE 0x3C
31908+#define NV40_RAMFC_UNK_40 0x40
31909+#define NV40_RAMFC_UNK_44 0x44
31910+#define NV40_RAMFC_UNK_48 0x48
31911+#define NV40_RAMFC_UNK_4C 0x4C
31912+#define NV40_RAMFC_UNK_50 0x50
31913+
31914Index: git/shared-core/nouveau_state.c
31915===================================================================
31916--- /dev/null 1970-01-01 00:00:00.000000000 +0000
31917+++ git/shared-core/nouveau_state.c 2008-12-12 17:35:22.000000000 +0000
31918@@ -0,0 +1,566 @@
31919+/*
31920+ * Copyright 2005 Stephane Marchesin
31921+ * All Rights Reserved.
31922+ *
31923+ * Permission is hereby granted, free of charge, to any person obtaining a
31924+ * copy of this software and associated documentation files (the "Software"),
31925+ * to deal in the Software without restriction, including without limitation
31926+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
31927+ * and/or sell copies of the Software, and to permit persons to whom the
31928+ * Software is furnished to do so, subject to the following conditions:
31929+ *
31930+ * The above copyright notice and this permission notice (including the next
31931+ * paragraph) shall be included in all copies or substantial portions of the
31932+ * Software.
31933+ *
31934+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
31935+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
31936+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
31937+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31938+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
31939+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31940+ * DEALINGS IN THE SOFTWARE.
31941+ */
31942+
31943+#include "drmP.h"
31944+#include "drm.h"
31945+#include "drm_sarea.h"
31946+#include "nouveau_drv.h"
31947+#include "nouveau_drm.h"
31948+
31949+static int nouveau_init_card_mappings(struct drm_device *dev)
31950+{
31951+ struct drm_nouveau_private *dev_priv = dev->dev_private;
31952+ int ret;
31953+
31954+ /* resource 0 is mmio regs */
31955+ /* resource 1 is linear FB */
31956+ /* resource 2 is RAMIN (mmio regs + 0x1000000) */
31957+ /* resource 6 is bios */
31958+
31959+ /* map the mmio regs */
31960+ ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
31961+ drm_get_resource_len(dev, 0),
31962+ _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
31963+ if (ret) {
31964+ DRM_ERROR("Unable to initialize the mmio mapping (%d). "
31965+ "Please report your setup to " DRIVER_EMAIL "\n",
31966+ ret);
31967+ return 1;
31968+ }
31969+ DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);
31970+
31971+ /* map larger RAMIN aperture on NV40 cards */
31972+ dev_priv->ramin = NULL;
31973+ if (dev_priv->card_type >= NV_40) {
31974+ int ramin_resource = 2;
31975+ if (drm_get_resource_len(dev, ramin_resource) == 0)
31976+ ramin_resource = 3;
31977+
31978+ ret = drm_addmap(dev,
31979+ drm_get_resource_start(dev, ramin_resource),
31980+ drm_get_resource_len(dev, ramin_resource),
31981+ _DRM_REGISTERS, _DRM_READ_ONLY,
31982+ &dev_priv->ramin);
31983+ if (ret) {
31984+ DRM_ERROR("Failed to init RAMIN mapping, "
31985+ "limited instance memory available\n");
31986+ dev_priv->ramin = NULL;
31987+ }
31988+ }
31989+
31990+ /* On older cards (or if the above failed), create a map covering
31991+ * the BAR0 PRAMIN aperture */
31992+ if (!dev_priv->ramin) {
31993+ ret = drm_addmap(dev,
31994+ drm_get_resource_start(dev, 0) + NV_RAMIN,
31995+ (1*1024*1024),
31996+ _DRM_REGISTERS, _DRM_READ_ONLY,
31997+ &dev_priv->ramin);
31998+ if (ret) {
31999+ DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
32000+ return ret;
32001+ }
32002+ }
32003+
32004+ return 0;
32005+}
32006+
32007+static int nouveau_stub_init(struct drm_device *dev) { return 0; }
32008+static void nouveau_stub_takedown(struct drm_device *dev) {}
32009+static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
32010+
32011+static int nouveau_init_engine_ptrs(struct drm_device *dev)
32012+{
32013+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32014+ struct nouveau_engine *engine = &dev_priv->Engine;
32015+
32016+ switch (dev_priv->chipset & 0xf0) {
32017+ case 0x00:
32018+ engine->instmem.init = nv04_instmem_init;
32019+ engine->instmem.takedown= nv04_instmem_takedown;
32020+ engine->instmem.populate = nv04_instmem_populate;
32021+ engine->instmem.clear = nv04_instmem_clear;
32022+ engine->instmem.bind = nv04_instmem_bind;
32023+ engine->instmem.unbind = nv04_instmem_unbind;
32024+ engine->mc.init = nv04_mc_init;
32025+ engine->mc.takedown = nv04_mc_takedown;
32026+ engine->timer.init = nv04_timer_init;
32027+ engine->timer.read = nv04_timer_read;
32028+ engine->timer.takedown = nv04_timer_takedown;
32029+ engine->fb.init = nv04_fb_init;
32030+ engine->fb.takedown = nv04_fb_takedown;
32031+ engine->graph.init = nv04_graph_init;
32032+ engine->graph.takedown = nv04_graph_takedown;
32033+ engine->graph.create_context = nv04_graph_create_context;
32034+ engine->graph.destroy_context = nv04_graph_destroy_context;
32035+ engine->graph.load_context = nv04_graph_load_context;
32036+ engine->graph.save_context = nv04_graph_save_context;
32037+ engine->fifo.init = nouveau_fifo_init;
32038+ engine->fifo.takedown = nouveau_stub_takedown;
32039+ engine->fifo.create_context = nv04_fifo_create_context;
32040+ engine->fifo.destroy_context = nv04_fifo_destroy_context;
32041+ engine->fifo.load_context = nv04_fifo_load_context;
32042+ engine->fifo.save_context = nv04_fifo_save_context;
32043+ break;
32044+ case 0x10:
32045+ engine->instmem.init = nv04_instmem_init;
32046+ engine->instmem.takedown= nv04_instmem_takedown;
32047+ engine->instmem.populate = nv04_instmem_populate;
32048+ engine->instmem.clear = nv04_instmem_clear;
32049+ engine->instmem.bind = nv04_instmem_bind;
32050+ engine->instmem.unbind = nv04_instmem_unbind;
32051+ engine->mc.init = nv04_mc_init;
32052+ engine->mc.takedown = nv04_mc_takedown;
32053+ engine->timer.init = nv04_timer_init;
32054+ engine->timer.read = nv04_timer_read;
32055+ engine->timer.takedown = nv04_timer_takedown;
32056+ engine->fb.init = nv10_fb_init;
32057+ engine->fb.takedown = nv10_fb_takedown;
32058+ engine->graph.init = nv10_graph_init;
32059+ engine->graph.takedown = nv10_graph_takedown;
32060+ engine->graph.create_context = nv10_graph_create_context;
32061+ engine->graph.destroy_context = nv10_graph_destroy_context;
32062+ engine->graph.load_context = nv10_graph_load_context;
32063+ engine->graph.save_context = nv10_graph_save_context;
32064+ engine->fifo.init = nouveau_fifo_init;
32065+ engine->fifo.takedown = nouveau_stub_takedown;
32066+ engine->fifo.create_context = nv10_fifo_create_context;
32067+ engine->fifo.destroy_context = nv10_fifo_destroy_context;
32068+ engine->fifo.load_context = nv10_fifo_load_context;
32069+ engine->fifo.save_context = nv10_fifo_save_context;
32070+ break;
32071+ case 0x20:
32072+ engine->instmem.init = nv04_instmem_init;
32073+ engine->instmem.takedown= nv04_instmem_takedown;
32074+ engine->instmem.populate = nv04_instmem_populate;
32075+ engine->instmem.clear = nv04_instmem_clear;
32076+ engine->instmem.bind = nv04_instmem_bind;
32077+ engine->instmem.unbind = nv04_instmem_unbind;
32078+ engine->mc.init = nv04_mc_init;
32079+ engine->mc.takedown = nv04_mc_takedown;
32080+ engine->timer.init = nv04_timer_init;
32081+ engine->timer.read = nv04_timer_read;
32082+ engine->timer.takedown = nv04_timer_takedown;
32083+ engine->fb.init = nv10_fb_init;
32084+ engine->fb.takedown = nv10_fb_takedown;
32085+ engine->graph.init = nv20_graph_init;
32086+ engine->graph.takedown = nv20_graph_takedown;
32087+ engine->graph.create_context = nv20_graph_create_context;
32088+ engine->graph.destroy_context = nv20_graph_destroy_context;
32089+ engine->graph.load_context = nv20_graph_load_context;
32090+ engine->graph.save_context = nv20_graph_save_context;
32091+ engine->fifo.init = nouveau_fifo_init;
32092+ engine->fifo.takedown = nouveau_stub_takedown;
32093+ engine->fifo.create_context = nv10_fifo_create_context;
32094+ engine->fifo.destroy_context = nv10_fifo_destroy_context;
32095+ engine->fifo.load_context = nv10_fifo_load_context;
32096+ engine->fifo.save_context = nv10_fifo_save_context;
32097+ break;
32098+ case 0x30:
32099+ engine->instmem.init = nv04_instmem_init;
32100+ engine->instmem.takedown= nv04_instmem_takedown;
32101+ engine->instmem.populate = nv04_instmem_populate;
32102+ engine->instmem.clear = nv04_instmem_clear;
32103+ engine->instmem.bind = nv04_instmem_bind;
32104+ engine->instmem.unbind = nv04_instmem_unbind;
32105+ engine->mc.init = nv04_mc_init;
32106+ engine->mc.takedown = nv04_mc_takedown;
32107+ engine->timer.init = nv04_timer_init;
32108+ engine->timer.read = nv04_timer_read;
32109+ engine->timer.takedown = nv04_timer_takedown;
32110+ engine->fb.init = nv10_fb_init;
32111+ engine->fb.takedown = nv10_fb_takedown;
32112+ engine->graph.init = nv30_graph_init;
32113+ engine->graph.takedown = nv30_graph_takedown;
32114+ engine->graph.create_context = nv30_graph_create_context;
32115+ engine->graph.destroy_context = nv30_graph_destroy_context;
32116+ engine->graph.load_context = nv30_graph_load_context;
32117+ engine->graph.save_context = nv30_graph_save_context;
32118+ engine->fifo.init = nouveau_fifo_init;
32119+ engine->fifo.takedown = nouveau_stub_takedown;
32120+ engine->fifo.create_context = nv10_fifo_create_context;
32121+ engine->fifo.destroy_context = nv10_fifo_destroy_context;
32122+ engine->fifo.load_context = nv10_fifo_load_context;
32123+ engine->fifo.save_context = nv10_fifo_save_context;
32124+ break;
32125+ case 0x40:
32126+ engine->instmem.init = nv04_instmem_init;
32127+ engine->instmem.takedown= nv04_instmem_takedown;
32128+ engine->instmem.populate = nv04_instmem_populate;
32129+ engine->instmem.clear = nv04_instmem_clear;
32130+ engine->instmem.bind = nv04_instmem_bind;
32131+ engine->instmem.unbind = nv04_instmem_unbind;
32132+ engine->mc.init = nv40_mc_init;
32133+ engine->mc.takedown = nv40_mc_takedown;
32134+ engine->timer.init = nv04_timer_init;
32135+ engine->timer.read = nv04_timer_read;
32136+ engine->timer.takedown = nv04_timer_takedown;
32137+ engine->fb.init = nv40_fb_init;
32138+ engine->fb.takedown = nv40_fb_takedown;
32139+ engine->graph.init = nv40_graph_init;
32140+ engine->graph.takedown = nv40_graph_takedown;
32141+ engine->graph.create_context = nv40_graph_create_context;
32142+ engine->graph.destroy_context = nv40_graph_destroy_context;
32143+ engine->graph.load_context = nv40_graph_load_context;
32144+ engine->graph.save_context = nv40_graph_save_context;
32145+ engine->fifo.init = nv40_fifo_init;
32146+ engine->fifo.takedown = nouveau_stub_takedown;
32147+ engine->fifo.create_context = nv40_fifo_create_context;
32148+ engine->fifo.destroy_context = nv40_fifo_destroy_context;
32149+ engine->fifo.load_context = nv40_fifo_load_context;
32150+ engine->fifo.save_context = nv40_fifo_save_context;
32151+ break;
32152+ case 0x50:
32153+ case 0x80: /* gotta love NVIDIA's consistency.. */
32154+ engine->instmem.init = nv50_instmem_init;
32155+ engine->instmem.takedown= nv50_instmem_takedown;
32156+ engine->instmem.populate = nv50_instmem_populate;
32157+ engine->instmem.clear = nv50_instmem_clear;
32158+ engine->instmem.bind = nv50_instmem_bind;
32159+ engine->instmem.unbind = nv50_instmem_unbind;
32160+ engine->mc.init = nv50_mc_init;
32161+ engine->mc.takedown = nv50_mc_takedown;
32162+ engine->timer.init = nouveau_stub_init;
32163+ engine->timer.read = nouveau_stub_timer_read;
32164+ engine->timer.takedown = nouveau_stub_takedown;
32165+ engine->fb.init = nouveau_stub_init;
32166+ engine->fb.takedown = nouveau_stub_takedown;
32167+ engine->graph.init = nv50_graph_init;
32168+ engine->graph.takedown = nv50_graph_takedown;
32169+ engine->graph.create_context = nv50_graph_create_context;
32170+ engine->graph.destroy_context = nv50_graph_destroy_context;
32171+ engine->graph.load_context = nv50_graph_load_context;
32172+ engine->graph.save_context = nv50_graph_save_context;
32173+ engine->fifo.init = nv50_fifo_init;
32174+ engine->fifo.takedown = nv50_fifo_takedown;
32175+ engine->fifo.create_context = nv50_fifo_create_context;
32176+ engine->fifo.destroy_context = nv50_fifo_destroy_context;
32177+ engine->fifo.load_context = nv50_fifo_load_context;
32178+ engine->fifo.save_context = nv50_fifo_save_context;
32179+ break;
32180+ default:
32181+ DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
32182+ return 1;
32183+ }
32184+
32185+ return 0;
32186+}
32187+
32188+int
32189+nouveau_card_init(struct drm_device *dev)
32190+{
32191+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32192+ struct nouveau_engine *engine;
32193+ int ret;
32194+
32195+ DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
32196+
32197+ if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
32198+ return 0;
32199+
32200+ /* Map any PCI resources we need on the card */
32201+ ret = nouveau_init_card_mappings(dev);
32202+ if (ret) return ret;
32203+
32204+ /* Determine exact chipset we're running on */
32205+ if (dev_priv->card_type < NV_10)
32206+ dev_priv->chipset = dev_priv->card_type;
32207+ else
32208+ dev_priv->chipset =
32209+ (NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
32210+
32211+ /* Initialise internal driver API hooks */
32212+ ret = nouveau_init_engine_ptrs(dev);
32213+ if (ret) return ret;
32214+ engine = &dev_priv->Engine;
32215+ dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
32216+
32217+ ret = nouveau_gpuobj_early_init(dev);
32218+ if (ret) return ret;
32219+
32220+ /* Initialise instance memory, must happen before mem_init so we
32221+ * know exactly how much VRAM we're able to use for "normal"
32222+ * purposes.
32223+ */
32224+ ret = engine->instmem.init(dev);
32225+ if (ret) return ret;
32226+
32227+ /* Setup the memory manager */
32228+ ret = nouveau_mem_init(dev);
32229+ if (ret) return ret;
32230+
32231+ ret = nouveau_gpuobj_init(dev);
32232+ if (ret) return ret;
32233+
32234+ /* Parse BIOS tables / Run init tables? */
32235+
32236+ /* PMC */
32237+ ret = engine->mc.init(dev);
32238+ if (ret) return ret;
32239+
32240+ /* PTIMER */
32241+ ret = engine->timer.init(dev);
32242+ if (ret) return ret;
32243+
32244+ /* PFB */
32245+ ret = engine->fb.init(dev);
32246+ if (ret) return ret;
32247+
32248+ /* PGRAPH */
32249+ ret = engine->graph.init(dev);
32250+ if (ret) return ret;
32251+
32252+ /* PFIFO */
32253+ ret = engine->fifo.init(dev);
32254+ if (ret) return ret;
32255+
32256+ /* this call irq_preinstall, register irq handler and
32257+ * call irq_postinstall
32258+ */
32259+ ret = drm_irq_install(dev);
32260+ if (ret) return ret;
32261+
32262+ /* what about PVIDEO/PCRTC/PRAMDAC etc? */
32263+
32264+ ret = nouveau_dma_channel_init(dev);
32265+ if (ret) return ret;
32266+
32267+ dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
32268+ return 0;
32269+}
32270+
32271+static void nouveau_card_takedown(struct drm_device *dev)
32272+{
32273+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32274+ struct nouveau_engine *engine = &dev_priv->Engine;
32275+
32276+ DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
32277+
32278+ if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
32279+ nouveau_dma_channel_takedown(dev);
32280+
32281+ engine->fifo.takedown(dev);
32282+ engine->graph.takedown(dev);
32283+ engine->fb.takedown(dev);
32284+ engine->timer.takedown(dev);
32285+ engine->mc.takedown(dev);
32286+
32287+ nouveau_sgdma_nottm_hack_takedown(dev);
32288+ nouveau_sgdma_takedown(dev);
32289+
32290+ nouveau_gpuobj_takedown(dev);
32291+
32292+ nouveau_mem_close(dev);
32293+ engine->instmem.takedown(dev);
32294+
32295+ drm_irq_uninstall(dev);
32296+
32297+ nouveau_gpuobj_late_takedown(dev);
32298+
32299+ dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
32300+ }
32301+}
32302+
32303+/* here a client dies, release the stuff that was allocated for its
32304+ * file_priv */
32305+void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
32306+{
32307+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32308+
32309+ nouveau_fifo_cleanup(dev, file_priv);
32310+ nouveau_mem_release(file_priv,dev_priv->fb_heap);
32311+ nouveau_mem_release(file_priv,dev_priv->agp_heap);
32312+ nouveau_mem_release(file_priv,dev_priv->pci_heap);
32313+}
32314+
32315+/* first module load, setup the mmio/fb mapping */
32316+int nouveau_firstopen(struct drm_device *dev)
32317+{
32318+ return 0;
32319+}
32320+
32321+int nouveau_load(struct drm_device *dev, unsigned long flags)
32322+{
32323+ struct drm_nouveau_private *dev_priv;
32324+
32325+ if (flags==NV_UNKNOWN)
32326+ return -EINVAL;
32327+
32328+ dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
32329+ if (!dev_priv)
32330+ return -ENOMEM;
32331+
32332+ dev_priv->card_type=flags&NOUVEAU_FAMILY;
32333+ dev_priv->flags=flags&NOUVEAU_FLAGS;
32334+ dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
32335+
32336+ dev->dev_private = (void *)dev_priv;
32337+ return 0;
32338+}
32339+
32340+void nouveau_lastclose(struct drm_device *dev)
32341+{
32342+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32343+
32344+ nouveau_card_takedown(dev);
32345+
32346+ if(dev_priv->fb_mtrr>0)
32347+ {
32348+ drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
32349+ dev_priv->fb_mtrr=0;
32350+ }
32351+}
32352+
32353+int nouveau_unload(struct drm_device *dev)
32354+{
32355+ drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER);
32356+ dev->dev_private = NULL;
32357+ return 0;
32358+}
32359+
32360+int
32361+nouveau_ioctl_card_init(struct drm_device *dev, void *data,
32362+ struct drm_file *file_priv)
32363+{
32364+ return nouveau_card_init(dev);
32365+}
32366+
32367+int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
32368+{
32369+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32370+ struct drm_nouveau_getparam *getparam = data;
32371+
32372+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
32373+
32374+ switch (getparam->param) {
32375+ case NOUVEAU_GETPARAM_CHIPSET_ID:
32376+ getparam->value = dev_priv->chipset;
32377+ break;
32378+ case NOUVEAU_GETPARAM_PCI_VENDOR:
32379+ getparam->value=dev->pci_vendor;
32380+ break;
32381+ case NOUVEAU_GETPARAM_PCI_DEVICE:
32382+ getparam->value=dev->pci_device;
32383+ break;
32384+ case NOUVEAU_GETPARAM_BUS_TYPE:
32385+ if (drm_device_is_agp(dev))
32386+ getparam->value=NV_AGP;
32387+ else if (drm_device_is_pcie(dev))
32388+ getparam->value=NV_PCIE;
32389+ else
32390+ getparam->value=NV_PCI;
32391+ break;
32392+ case NOUVEAU_GETPARAM_FB_PHYSICAL:
32393+ getparam->value=dev_priv->fb_phys;
32394+ break;
32395+ case NOUVEAU_GETPARAM_AGP_PHYSICAL:
32396+ getparam->value=dev_priv->gart_info.aper_base;
32397+ break;
32398+ case NOUVEAU_GETPARAM_PCI_PHYSICAL:
32399+ if ( dev -> sg )
32400+ getparam->value=(uint64_t) dev->sg->virtual;
32401+ else
32402+ {
32403+ DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
32404+ return -EINVAL;
32405+ }
32406+ break;
32407+ case NOUVEAU_GETPARAM_FB_SIZE:
32408+ getparam->value=dev_priv->fb_available_size;
32409+ break;
32410+ case NOUVEAU_GETPARAM_AGP_SIZE:
32411+ getparam->value=dev_priv->gart_info.aper_size;
32412+ break;
32413+ default:
32414+ DRM_ERROR("unknown parameter %lld\n", getparam->param);
32415+ return -EINVAL;
32416+ }
32417+
32418+ return 0;
32419+}
32420+
32421+int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
32422+{
32423+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32424+ struct drm_nouveau_setparam *setparam = data;
32425+
32426+ NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
32427+
32428+ switch (setparam->param) {
32429+ case NOUVEAU_SETPARAM_CMDBUF_LOCATION:
32430+ switch (setparam->value) {
32431+ case NOUVEAU_MEM_AGP:
32432+ case NOUVEAU_MEM_FB:
32433+ case NOUVEAU_MEM_PCI:
32434+ case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE:
32435+ break;
32436+ default:
32437+ DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n",
32438+ setparam->value);
32439+ return -EINVAL;
32440+ }
32441+ dev_priv->config.cmdbuf.location = setparam->value;
32442+ break;
32443+ case NOUVEAU_SETPARAM_CMDBUF_SIZE:
32444+ dev_priv->config.cmdbuf.size = setparam->value;
32445+ break;
32446+ default:
32447+ DRM_ERROR("unknown parameter %lld\n", setparam->param);
32448+ return -EINVAL;
32449+ }
32450+
32451+ return 0;
32452+}
32453+
32454+/* waits for idle */
32455+void nouveau_wait_for_idle(struct drm_device *dev)
32456+{
32457+ struct drm_nouveau_private *dev_priv=dev->dev_private;
32458+ switch(dev_priv->card_type) {
32459+ case NV_50:
32460+ break;
32461+ default: {
32462+ /* This stuff is more or less a copy of what is seen
32463+ * in nv28 kmmio dump.
32464+ */
32465+ uint64_t started = dev_priv->Engine.timer.read(dev);
32466+ uint64_t stopped = started;
32467+ uint32_t status;
32468+ do {
32469+ uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
32470+ (void)pmc_e;
32471+ status = NV_READ(NV04_PGRAPH_STATUS);
32472+ if (!status)
32473+ break;
32474+ stopped = dev_priv->Engine.timer.read(dev);
32475+ /* It'll never wrap anyway... */
32476+ } while (stopped - started < 1000000000ULL);
32477+ if (status)
32478+ DRM_ERROR("timed out with status 0x%08x\n",
32479+ status);
32480+ }
32481+ }
32482+}
32483+
32484+
32485Index: git/shared-core/nv04_fb.c
32486===================================================================
32487--- /dev/null 1970-01-01 00:00:00.000000000 +0000
32488+++ git/shared-core/nv04_fb.c 2008-12-12 17:35:22.000000000 +0000
32489@@ -0,0 +1,24 @@
32490+#include "drmP.h"
32491+#include "drm.h"
32492+#include "nouveau_drv.h"
32493+#include "nouveau_drm.h"
32494+
32495+int
32496+nv04_fb_init(struct drm_device *dev)
32497+{
32498+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32499+
32500+ /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
32501+ * nvidia reading PFB_CFG_0, then writing back its original value.
32502+ * (which was 0x701114 in this case)
32503+ */
32504+ NV_WRITE(NV04_PFB_CFG0, 0x1114);
32505+
32506+ return 0;
32507+}
32508+
32509+void
32510+nv04_fb_takedown(struct drm_device *dev)
32511+{
32512+}
32513+
32514Index: git/shared-core/nv04_fifo.c
32515===================================================================
32516--- /dev/null 1970-01-01 00:00:00.000000000 +0000
32517+++ git/shared-core/nv04_fifo.c 2008-12-12 17:35:22.000000000 +0000
32518@@ -0,0 +1,129 @@
32519+/*
32520+ * Copyright (C) 2007 Ben Skeggs.
32521+ * All Rights Reserved.
32522+ *
32523+ * Permission is hereby granted, free of charge, to any person obtaining
32524+ * a copy of this software and associated documentation files (the
32525+ * "Software"), to deal in the Software without restriction, including
32526+ * without limitation the rights to use, copy, modify, merge, publish,
32527+ * distribute, sublicense, and/or sell copies of the Software, and to
32528+ * permit persons to whom the Software is furnished to do so, subject to
32529+ * the following conditions:
32530+ *
32531+ * The above copyright notice and this permission notice (including the
32532+ * next paragraph) shall be included in all copies or substantial
32533+ * portions of the Software.
32534+ *
32535+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32536+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
32537+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
32538+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
32539+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
32540+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
32541+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32542+ *
32543+ */
32544+
32545+#include "drmP.h"
32546+#include "drm.h"
32547+#include "nouveau_drv.h"
32548+
32549+#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
32550+ NV04_RAMFC_##offset/4, (val))
32551+#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
32552+ NV04_RAMFC_##offset/4)
32553+#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
32554+#define NV04_RAMFC__SIZE 32
32555+
32556+int
32557+nv04_fifo_create_context(struct nouveau_channel *chan)
32558+{
32559+ struct drm_device *dev = chan->dev;
32560+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32561+ int ret;
32562+
32563+ if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
32564+ NV04_RAMFC__SIZE,
32565+ NVOBJ_FLAG_ZERO_ALLOC |
32566+ NVOBJ_FLAG_ZERO_FREE,
32567+ NULL, &chan->ramfc)))
32568+ return ret;
32569+
32570+ /* Setup initial state */
32571+ RAMFC_WR(DMA_PUT, chan->pushbuf_base);
32572+ RAMFC_WR(DMA_GET, chan->pushbuf_base);
32573+ RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);
32574+ RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
32575+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
32576+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
32577+#ifdef __BIG_ENDIAN
32578+ NV_PFIFO_CACHE1_BIG_ENDIAN |
32579+#endif
32580+ 0));
32581+
32582+ /* enable the fifo dma operation */
32583+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id));
32584+ return 0;
32585+}
32586+
32587+void
32588+nv04_fifo_destroy_context(struct nouveau_channel *chan)
32589+{
32590+ struct drm_device *dev = chan->dev;
32591+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32592+
32593+ NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
32594+
32595+ nouveau_gpuobj_ref_del(dev, &chan->ramfc);
32596+}
32597+
32598+int
32599+nv04_fifo_load_context(struct nouveau_channel *chan)
32600+{
32601+ struct drm_device *dev = chan->dev;
32602+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32603+ uint32_t tmp;
32604+
32605+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id);
32606+
32607+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
32608+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
32609+
32610+ tmp = RAMFC_RD(DMA_INSTANCE);
32611+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
32612+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
32613+
32614+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
32615+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
32616+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
32617+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
32618+
32619+ /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
32620+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
32621+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
32622+
32623+ return 0;
32624+}
32625+
32626+int
32627+nv04_fifo_save_context(struct nouveau_channel *chan)
32628+{
32629+ struct drm_device *dev = chan->dev;
32630+ struct drm_nouveau_private *dev_priv = dev->dev_private;
32631+ uint32_t tmp;
32632+
32633+ RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
32634+ RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET);
32635+
32636+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
32637+ tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);
32638+ RAMFC_WR(DMA_INSTANCE, tmp);
32639+
32640+ RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
32641+ RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
32642+ RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
32643+ RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
32644+
32645+ return 0;
32646+}
32647+
32648Index: git/shared-core/nv04_graph.c
32649===================================================================
32650--- /dev/null 1970-01-01 00:00:00.000000000 +0000
32651+++ git/shared-core/nv04_graph.c 2008-12-12 17:35:22.000000000 +0000
32652@@ -0,0 +1,474 @@
32653+/*
32654+ * Copyright 2007 Stephane Marchesin
32655+ * All Rights Reserved.
32656+ *
32657+ * Permission is hereby granted, free of charge, to any person obtaining a
32658+ * copy of this software and associated documentation files (the "Software"),
32659+ * to deal in the Software without restriction, including without limitation
32660+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
32661+ * and/or sell copies of the Software, and to permit persons to whom the
32662+ * Software is furnished to do so, subject to the following conditions:
32663+ *
32664+ * The above copyright notice and this permission notice (including the next
32665+ * paragraph) shall be included in all copies or substantial portions of the
32666+ * Software.
32667+ *
32668+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32669+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
32670+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
32671+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
32672+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32673+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
32674+ * DEALINGS IN THE SOFTWARE.
32675+ */
32676+
32677+#include "drmP.h"
32678+#include "drm.h"
32679+#include "nouveau_drm.h"
32680+#include "nouveau_drv.h"
32681+
32682+static uint32_t nv04_graph_ctx_regs [] = {
32683+ NV04_PGRAPH_CTX_SWITCH1,
32684+ NV04_PGRAPH_CTX_SWITCH2,
32685+ NV04_PGRAPH_CTX_SWITCH3,
32686+ NV04_PGRAPH_CTX_SWITCH4,
32687+ NV04_PGRAPH_CTX_CACHE1,
32688+ NV04_PGRAPH_CTX_CACHE2,
32689+ NV04_PGRAPH_CTX_CACHE3,
32690+ NV04_PGRAPH_CTX_CACHE4,
32691+ 0x00400184,
32692+ 0x004001a4,
32693+ 0x004001c4,
32694+ 0x004001e4,
32695+ 0x00400188,
32696+ 0x004001a8,
32697+ 0x004001c8,
32698+ 0x004001e8,
32699+ 0x0040018c,
32700+ 0x004001ac,
32701+ 0x004001cc,
32702+ 0x004001ec,
32703+ 0x00400190,
32704+ 0x004001b0,
32705+ 0x004001d0,
32706+ 0x004001f0,
32707+ 0x00400194,
32708+ 0x004001b4,
32709+ 0x004001d4,
32710+ 0x004001f4,
32711+ 0x00400198,
32712+ 0x004001b8,
32713+ 0x004001d8,
32714+ 0x004001f8,
32715+ 0x0040019c,
32716+ 0x004001bc,
32717+ 0x004001dc,
32718+ 0x004001fc,
32719+ 0x00400174,
32720+ NV04_PGRAPH_DMA_START_0,
32721+ NV04_PGRAPH_DMA_START_1,
32722+ NV04_PGRAPH_DMA_LENGTH,
32723+ NV04_PGRAPH_DMA_MISC,
32724+ NV04_PGRAPH_DMA_PITCH,
32725+ NV04_PGRAPH_BOFFSET0,
32726+ NV04_PGRAPH_BBASE0,
32727+ NV04_PGRAPH_BLIMIT0,
32728+ NV04_PGRAPH_BOFFSET1,
32729+ NV04_PGRAPH_BBASE1,
32730+ NV04_PGRAPH_BLIMIT1,
32731+ NV04_PGRAPH_BOFFSET2,
32732+ NV04_PGRAPH_BBASE2,
32733+ NV04_PGRAPH_BLIMIT2,
32734+ NV04_PGRAPH_BOFFSET3,
32735+ NV04_PGRAPH_BBASE3,
32736+ NV04_PGRAPH_BLIMIT3,
32737+ NV04_PGRAPH_BOFFSET4,
32738+ NV04_PGRAPH_BBASE4,
32739+ NV04_PGRAPH_BLIMIT4,
32740+ NV04_PGRAPH_BOFFSET5,
32741+ NV04_PGRAPH_BBASE5,
32742+ NV04_PGRAPH_BLIMIT5,
32743+ NV04_PGRAPH_BPITCH0,
32744+ NV04_PGRAPH_BPITCH1,
32745+ NV04_PGRAPH_BPITCH2,
32746+ NV04_PGRAPH_BPITCH3,
32747+ NV04_PGRAPH_BPITCH4,
32748+ NV04_PGRAPH_SURFACE,
32749+ NV04_PGRAPH_STATE,
32750+ NV04_PGRAPH_BSWIZZLE2,
32751+ NV04_PGRAPH_BSWIZZLE5,
32752+ NV04_PGRAPH_BPIXEL,
32753+ NV04_PGRAPH_NOTIFY,
32754+ NV04_PGRAPH_PATT_COLOR0,
32755+ NV04_PGRAPH_PATT_COLOR1,
32756+ NV04_PGRAPH_PATT_COLORRAM+0x00,
32757+ NV04_PGRAPH_PATT_COLORRAM+0x01,
32758+ NV04_PGRAPH_PATT_COLORRAM+0x02,
32759+ NV04_PGRAPH_PATT_COLORRAM+0x03,
32760+ NV04_PGRAPH_PATT_COLORRAM+0x04,
32761+ NV04_PGRAPH_PATT_COLORRAM+0x05,
32762+ NV04_PGRAPH_PATT_COLORRAM+0x06,
32763+ NV04_PGRAPH_PATT_COLORRAM+0x07,
32764+ NV04_PGRAPH_PATT_COLORRAM+0x08,
32765+ NV04_PGRAPH_PATT_COLORRAM+0x09,
32766+ NV04_PGRAPH_PATT_COLORRAM+0x0A,
32767+ NV04_PGRAPH_PATT_COLORRAM+0x0B,
32768+ NV04_PGRAPH_PATT_COLORRAM+0x0C,
32769+ NV04_PGRAPH_PATT_COLORRAM+0x0D,
32770+ NV04_PGRAPH_PATT_COLORRAM+0x0E,
32771+ NV04_PGRAPH_PATT_COLORRAM+0x0F,
32772+ NV04_PGRAPH_PATT_COLORRAM+0x10,
32773+ NV04_PGRAPH_PATT_COLORRAM+0x11,
32774+ NV04_PGRAPH_PATT_COLORRAM+0x12,
32775+ NV04_PGRAPH_PATT_COLORRAM+0x13,
32776+ NV04_PGRAPH_PATT_COLORRAM+0x14,
32777+ NV04_PGRAPH_PATT_COLORRAM+0x15,
32778+ NV04_PGRAPH_PATT_COLORRAM+0x16,
32779+ NV04_PGRAPH_PATT_COLORRAM+0x17,
32780+ NV04_PGRAPH_PATT_COLORRAM+0x18,
32781+ NV04_PGRAPH_PATT_COLORRAM+0x19,
32782+ NV04_PGRAPH_PATT_COLORRAM+0x1A,
32783+ NV04_PGRAPH_PATT_COLORRAM+0x1B,
32784+ NV04_PGRAPH_PATT_COLORRAM+0x1C,
32785+ NV04_PGRAPH_PATT_COLORRAM+0x1D,
32786+ NV04_PGRAPH_PATT_COLORRAM+0x1E,
32787+ NV04_PGRAPH_PATT_COLORRAM+0x1F,
32788+ NV04_PGRAPH_PATT_COLORRAM+0x20,
32789+ NV04_PGRAPH_PATT_COLORRAM+0x21,
32790+ NV04_PGRAPH_PATT_COLORRAM+0x22,
32791+ NV04_PGRAPH_PATT_COLORRAM+0x23,
32792+ NV04_PGRAPH_PATT_COLORRAM+0x24,
32793+ NV04_PGRAPH_PATT_COLORRAM+0x25,
32794+ NV04_PGRAPH_PATT_COLORRAM+0x26,
32795+ NV04_PGRAPH_PATT_COLORRAM+0x27,
32796+ NV04_PGRAPH_PATT_COLORRAM+0x28,
32797+ NV04_PGRAPH_PATT_COLORRAM+0x29,
32798+ NV04_PGRAPH_PATT_COLORRAM+0x2A,
32799+ NV04_PGRAPH_PATT_COLORRAM+0x2B,
32800+ NV04_PGRAPH_PATT_COLORRAM+0x2C,
32801+ NV04_PGRAPH_PATT_COLORRAM+0x2D,
32802+ NV04_PGRAPH_PATT_COLORRAM+0x2E,
32803+ NV04_PGRAPH_PATT_COLORRAM+0x2F,
32804+ NV04_PGRAPH_PATT_COLORRAM+0x30,
32805+ NV04_PGRAPH_PATT_COLORRAM+0x31,
32806+ NV04_PGRAPH_PATT_COLORRAM+0x32,
32807+ NV04_PGRAPH_PATT_COLORRAM+0x33,
32808+ NV04_PGRAPH_PATT_COLORRAM+0x34,
32809+ NV04_PGRAPH_PATT_COLORRAM+0x35,
32810+ NV04_PGRAPH_PATT_COLORRAM+0x36,
32811+ NV04_PGRAPH_PATT_COLORRAM+0x37,
32812+ NV04_PGRAPH_PATT_COLORRAM+0x38,
32813+ NV04_PGRAPH_PATT_COLORRAM+0x39,
32814+ NV04_PGRAPH_PATT_COLORRAM+0x3A,
32815+ NV04_PGRAPH_PATT_COLORRAM+0x3B,
32816+ NV04_PGRAPH_PATT_COLORRAM+0x3C,
32817+ NV04_PGRAPH_PATT_COLORRAM+0x3D,
32818+ NV04_PGRAPH_PATT_COLORRAM+0x3E,
32819+ NV04_PGRAPH_PATT_COLORRAM+0x3F,
32820+ NV04_PGRAPH_PATTERN,
32821+ 0x0040080c,
32822+ NV04_PGRAPH_PATTERN_SHAPE,
32823+ 0x00400600,
32824+ NV04_PGRAPH_ROP3,
32825+ NV04_PGRAPH_CHROMA,
32826+ NV04_PGRAPH_BETA_AND,
32827+ NV04_PGRAPH_BETA_PREMULT,
32828+ NV04_PGRAPH_CONTROL0,
32829+ NV04_PGRAPH_CONTROL1,
32830+ NV04_PGRAPH_CONTROL2,
32831+ NV04_PGRAPH_BLEND,
32832+ NV04_PGRAPH_STORED_FMT,
32833+ NV04_PGRAPH_SOURCE_COLOR,
32834+ 0x00400560,
32835+ 0x00400568,
32836+ 0x00400564,
32837+ 0x0040056c,
32838+ 0x00400400,
32839+ 0x00400480,
32840+ 0x00400404,
32841+ 0x00400484,
32842+ 0x00400408,
32843+ 0x00400488,
32844+ 0x0040040c,
32845+ 0x0040048c,
32846+ 0x00400410,
32847+ 0x00400490,
32848+ 0x00400414,
32849+ 0x00400494,
32850+ 0x00400418,
32851+ 0x00400498,
32852+ 0x0040041c,
32853+ 0x0040049c,
32854+ 0x00400420,
32855+ 0x004004a0,
32856+ 0x00400424,
32857+ 0x004004a4,
32858+ 0x00400428,
32859+ 0x004004a8,
32860+ 0x0040042c,
32861+ 0x004004ac,
32862+ 0x00400430,
32863+ 0x004004b0,
32864+ 0x00400434,
32865+ 0x004004b4,
32866+ 0x00400438,
32867+ 0x004004b8,
32868+ 0x0040043c,
32869+ 0x004004bc,
32870+ 0x00400440,
32871+ 0x004004c0,
32872+ 0x00400444,
32873+ 0x004004c4,
32874+ 0x00400448,
32875+ 0x004004c8,
32876+ 0x0040044c,
32877+ 0x004004cc,
32878+ 0x00400450,
32879+ 0x004004d0,
32880+ 0x00400454,
32881+ 0x004004d4,
32882+ 0x00400458,
32883+ 0x004004d8,
32884+ 0x0040045c,
32885+ 0x004004dc,
32886+ 0x00400460,
32887+ 0x004004e0,
32888+ 0x00400464,
32889+ 0x004004e4,
32890+ 0x00400468,
32891+ 0x004004e8,
32892+ 0x0040046c,
32893+ 0x004004ec,
32894+ 0x00400470,
32895+ 0x004004f0,
32896+ 0x00400474,
32897+ 0x004004f4,
32898+ 0x00400478,
32899+ 0x004004f8,
32900+ 0x0040047c,
32901+ 0x004004fc,
32902+ 0x0040053c,
32903+ 0x00400544,
32904+ 0x00400540,
32905+ 0x00400548,
32906+ 0x00400560,
32907+ 0x00400568,
32908+ 0x00400564,
32909+ 0x0040056c,
32910+ 0x00400534,
32911+ 0x00400538,
32912+ 0x00400514,
32913+ 0x00400518,
32914+ 0x0040051c,
32915+ 0x00400520,
32916+ 0x00400524,
32917+ 0x00400528,
32918+ 0x0040052c,
32919+ 0x00400530,
32920+ 0x00400d00,
32921+ 0x00400d40,
32922+ 0x00400d80,
32923+ 0x00400d04,
32924+ 0x00400d44,
32925+ 0x00400d84,
32926+ 0x00400d08,
32927+ 0x00400d48,
32928+ 0x00400d88,
32929+ 0x00400d0c,
32930+ 0x00400d4c,
32931+ 0x00400d8c,
32932+ 0x00400d10,
32933+ 0x00400d50,
32934+ 0x00400d90,
32935+ 0x00400d14,
32936+ 0x00400d54,
32937+ 0x00400d94,
32938+ 0x00400d18,
32939+ 0x00400d58,
32940+ 0x00400d98,
32941+ 0x00400d1c,
32942+ 0x00400d5c,
32943+ 0x00400d9c,
32944+ 0x00400d20,
32945+ 0x00400d60,
32946+ 0x00400da0,
32947+ 0x00400d24,
32948+ 0x00400d64,
32949+ 0x00400da4,
32950+ 0x00400d28,
32951+ 0x00400d68,
32952+ 0x00400da8,
32953+ 0x00400d2c,
32954+ 0x00400d6c,
32955+ 0x00400dac,
32956+ 0x00400d30,
32957+ 0x00400d70,
32958+ 0x00400db0,
32959+ 0x00400d34,
32960+ 0x00400d74,
32961+ 0x00400db4,
32962+ 0x00400d38,
32963+ 0x00400d78,
32964+ 0x00400db8,
32965+ 0x00400d3c,
32966+ 0x00400d7c,
32967+ 0x00400dbc,
32968+ 0x00400590,
32969+ 0x00400594,
32970+ 0x00400598,
32971+ 0x0040059c,
32972+ 0x004005a8,
32973+ 0x004005ac,
32974+ 0x004005b0,
32975+ 0x004005b4,
32976+ 0x004005c0,
32977+ 0x004005c4,
32978+ 0x004005c8,
32979+ 0x004005cc,
32980+ 0x004005d0,
32981+ 0x004005d4,
32982+ 0x004005d8,
32983+ 0x004005dc,
32984+ 0x004005e0,
32985+ NV04_PGRAPH_PASSTHRU_0,
32986+ NV04_PGRAPH_PASSTHRU_1,
32987+ NV04_PGRAPH_PASSTHRU_2,
32988+ NV04_PGRAPH_DVD_COLORFMT,
32989+ NV04_PGRAPH_SCALED_FORMAT,
32990+ NV04_PGRAPH_MISC24_0,
32991+ NV04_PGRAPH_MISC24_1,
32992+ NV04_PGRAPH_MISC24_2,
32993+ 0x00400500,
32994+ 0x00400504,
32995+ NV04_PGRAPH_VALID1,
32996+ NV04_PGRAPH_VALID2
32997+
32998+
32999+};
33000+
33001+void nouveau_nv04_context_switch(struct drm_device *dev)
33002+{
33003+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33004+ struct nouveau_channel *next, *last;
33005+ int chid;
33006+
33007+ chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
33008+ next = dev_priv->fifos[chid];
33009+
33010+ chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
33011+ last = dev_priv->fifos[chid];
33012+
33013+ DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id);
33014+
33015+/* NV_WRITE(NV03_PFIFO_CACHES, 0x0);
33016+ NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
33017+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/
33018+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
33019+
33020+ if (last)
33021+ nv04_graph_save_context(last);
33022+
33023+ nouveau_wait_for_idle(dev);
33024+
33025+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
33026+ NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
33027+
33028+ nouveau_wait_for_idle(dev);
33029+
33030+ nv04_graph_load_context(next);
33031+
33032+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
33033+ NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24);
33034+ NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
33035+
33036+/* NV_WRITE(NV04_PGRAPH_FIFO,0x0);
33037+ NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
33038+ NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
33039+ NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/
33040+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
33041+}
33042+
33043+int nv04_graph_create_context(struct nouveau_channel *chan) {
33044+ DRM_DEBUG("nv04_graph_context_create %d\n", chan->id);
33045+
33046+ memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx));
33047+
33048+ //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
33049+ chan->pgraph_ctx[0] = 0x0001ffff;
33050+ /* is it really needed ??? */
33051+ //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
33052+ //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
33053+
33054+ return 0;
33055+}
33056+
33057+void nv04_graph_destroy_context(struct nouveau_channel *chan)
33058+{
33059+}
33060+
33061+int nv04_graph_load_context(struct nouveau_channel *chan)
33062+{
33063+ struct drm_device *dev = chan->dev;
33064+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33065+ int i;
33066+
33067+ for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
33068+ NV_WRITE(nv04_graph_ctx_regs[i], chan->pgraph_ctx[i]);
33069+
33070+ return 0;
33071+}
33072+
33073+int nv04_graph_save_context(struct nouveau_channel *chan)
33074+{
33075+ struct drm_device *dev = chan->dev;
33076+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33077+ int i;
33078+
33079+ for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
33080+ chan->pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]);
33081+
33082+ return 0;
33083+}
33084+
33085+int nv04_graph_init(struct drm_device *dev) {
33086+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33087+
33088+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
33089+ ~NV_PMC_ENABLE_PGRAPH);
33090+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
33091+ NV_PMC_ENABLE_PGRAPH);
33092+
33093+ /* Enable PGRAPH interrupts */
33094+ NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
33095+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
33096+
33097+ // check the context is big enough
33098+ if ( sizeof(nv04_graph_ctx_regs)>sizeof(dev_priv->fifos[0]->pgraph_ctx) )
33099+ DRM_ERROR("pgraph_ctx too small\n");
33100+
33101+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
33102+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000);
33103+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);
33104+ NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);
33105+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31);
33106+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 |
33107+ (0x00D00000) |
33108+ (1<<29) |
33109+ (1<<31));
33110+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);
33111+
33112+ NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF);
33113+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100);
33114+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
33115+
33116+ /* These don't belong here, they're part of a per-channel context */
33117+ NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
33118+ NV_WRITE(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
33119+
33120+ return 0;
33121+}
33122+
33123+void nv04_graph_takedown(struct drm_device *dev)
33124+{
33125+}
33126+
33127Index: git/shared-core/nv04_mc.c
33128===================================================================
33129--- /dev/null 1970-01-01 00:00:00.000000000 +0000
33130+++ git/shared-core/nv04_mc.c 2008-12-12 17:35:22.000000000 +0000
33131@@ -0,0 +1,23 @@
33132+#include "drmP.h"
33133+#include "drm.h"
33134+#include "nouveau_drv.h"
33135+#include "nouveau_drm.h"
33136+
33137+int
33138+nv04_mc_init(struct drm_device *dev)
33139+{
33140+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33141+
33142+ /* Power up everything, resetting each individual unit will
33143+ * be done later if needed.
33144+ */
33145+ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
33146+
33147+ return 0;
33148+}
33149+
33150+void
33151+nv04_mc_takedown(struct drm_device *dev)
33152+{
33153+}
33154+
33155Index: git/shared-core/nv04_timer.c
33156===================================================================
33157--- /dev/null 1970-01-01 00:00:00.000000000 +0000
33158+++ git/shared-core/nv04_timer.c 2008-12-12 17:35:22.000000000 +0000
33159@@ -0,0 +1,45 @@
33160+#include "drmP.h"
33161+#include "drm.h"
33162+#include "nouveau_drv.h"
33163+#include "nouveau_drm.h"
33164+
33165+int
33166+nv04_timer_init(struct drm_device *dev)
33167+{
33168+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33169+
33170+ NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
33171+ NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
33172+
33173+ NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
33174+ NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
33175+
33176+ return 0;
33177+}
33178+
33179+uint64_t
33180+nv04_timer_read(struct drm_device *dev)
33181+{
33182+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33183+ uint32_t low;
33184+ /* From kmmio dumps on nv28 this looks like how the blob does this.
33185+ * It reads the high dword twice, before and after.
33186+ * The only explanation seems to be that the 64-bit timer counter
33187+ * advances between high and low dword reads and may corrupt the
33188+ * result. Not confirmed.
33189+ */
33190+ uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
33191+ uint32_t high1;
33192+ do {
33193+ high1 = high2;
33194+ low = NV_READ(NV04_PTIMER_TIME_0);
33195+ high2 = NV_READ(NV04_PTIMER_TIME_1);
33196+ } while(high1 != high2);
33197+ return (((uint64_t)high2) << 32) | (uint64_t)low;
33198+}
33199+
33200+void
33201+nv04_timer_takedown(struct drm_device *dev)
33202+{
33203+}
33204+
33205Index: git/shared-core/nv10_fb.c
33206===================================================================
33207--- /dev/null 1970-01-01 00:00:00.000000000 +0000
33208+++ git/shared-core/nv10_fb.c 2008-12-12 17:35:22.000000000 +0000
33209@@ -0,0 +1,26 @@
33210+#include "drmP.h"
33211+#include "drm.h"
33212+#include "nouveau_drv.h"
33213+#include "nouveau_drm.h"
33214+
33215+int
33216+nv10_fb_init(struct drm_device *dev)
33217+{
33218+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33219+ uint32_t fb_bar_size;
33220+ int i;
33221+
33222+ fb_bar_size = drm_get_resource_len(dev, 0) - 1;
33223+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
33224+ NV_WRITE(NV10_PFB_TILE(i), 0);
33225+ NV_WRITE(NV10_PFB_TLIMIT(i), fb_bar_size);
33226+ }
33227+
33228+ return 0;
33229+}
33230+
33231+void
33232+nv10_fb_takedown(struct drm_device *dev)
33233+{
33234+}
33235+
33236Index: git/shared-core/nv10_fifo.c
33237===================================================================
33238--- /dev/null 1970-01-01 00:00:00.000000000 +0000
33239+++ git/shared-core/nv10_fifo.c 2008-12-12 17:35:22.000000000 +0000
33240@@ -0,0 +1,160 @@
33241+/*
33242+ * Copyright (C) 2007 Ben Skeggs.
33243+ * All Rights Reserved.
33244+ *
33245+ * Permission is hereby granted, free of charge, to any person obtaining
33246+ * a copy of this software and associated documentation files (the
33247+ * "Software"), to deal in the Software without restriction, including
33248+ * without limitation the rights to use, copy, modify, merge, publish,
33249+ * distribute, sublicense, and/or sell copies of the Software, and to
33250+ * permit persons to whom the Software is furnished to do so, subject to
33251+ * the following conditions:
33252+ *
33253+ * The above copyright notice and this permission notice (including the
33254+ * next paragraph) shall be included in all copies or substantial
33255+ * portions of the Software.
33256+ *
33257+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33258+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33259+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
33260+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
33261+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
33262+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
33263+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33264+ *
33265+ */
33266+
33267+#include "drmP.h"
33268+#include "drm.h"
33269+#include "nouveau_drv.h"
33270+
33271+
33272+#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
33273+ NV10_RAMFC_##offset/4, (val))
33274+#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
33275+ NV10_RAMFC_##offset/4)
33276+#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
33277+#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
33278+
33279+int
33280+nv10_fifo_create_context(struct nouveau_channel *chan)
33281+{
33282+ struct drm_device *dev = chan->dev;
33283+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33284+ int ret;
33285+
33286+ if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
33287+ NV10_RAMFC__SIZE,
33288+ NVOBJ_FLAG_ZERO_ALLOC |
33289+ NVOBJ_FLAG_ZERO_FREE,
33290+ NULL, &chan->ramfc)))
33291+ return ret;
33292+
33293+ /* Fill entries that are seen filled in dumps of nvidia driver just
33294+ * after channel's is put into DMA mode
33295+ */
33296+ RAMFC_WR(DMA_PUT , chan->pushbuf_base);
33297+ RAMFC_WR(DMA_GET , chan->pushbuf_base);
33298+ RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4);
33299+ RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
33300+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
33301+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
33302+#ifdef __BIG_ENDIAN
33303+ NV_PFIFO_CACHE1_BIG_ENDIAN |
33304+#endif
33305+ 0);
33306+
33307+ /* enable the fifo dma operation */
33308+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
33309+ return 0;
33310+}
33311+
33312+void
33313+nv10_fifo_destroy_context(struct nouveau_channel *chan)
33314+{
33315+ struct drm_device *dev = chan->dev;
33316+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33317+
33318+ NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
33319+
33320+ nouveau_gpuobj_ref_del(dev, &chan->ramfc);
33321+}
33322+
33323+int
33324+nv10_fifo_load_context(struct nouveau_channel *chan)
33325+{
33326+ struct drm_device *dev = chan->dev;
33327+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33328+ uint32_t tmp;
33329+
33330+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | chan->id);
33331+
33332+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
33333+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
33334+ NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT));
33335+
33336+ tmp = RAMFC_RD(DMA_INSTANCE);
33337+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , tmp & 0xFFFF);
33338+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , tmp >> 16);
33339+
33340+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE));
33341+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , RAMFC_RD(DMA_FETCH));
33342+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE));
33343+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE));
33344+
33345+ if (dev_priv->chipset >= 0x17) {
33346+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
33347+ RAMFC_RD(ACQUIRE_VALUE));
33348+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
33349+ RAMFC_RD(ACQUIRE_TIMESTAMP));
33350+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
33351+ RAMFC_RD(ACQUIRE_TIMEOUT));
33352+ NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
33353+ RAMFC_RD(SEMAPHORE));
33354+ NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
33355+ RAMFC_RD(DMA_SUBROUTINE));
33356+ }
33357+
33358+ /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
33359+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
33360+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
33361+
33362+ return 0;
33363+}
33364+
33365+int
33366+nv10_fifo_save_context(struct nouveau_channel *chan)
33367+{
33368+ struct drm_device *dev = chan->dev;
33369+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33370+ uint32_t tmp;
33371+
33372+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
33373+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
33374+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
33375+
33376+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
33377+ tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
33378+ RAMFC_WR(DMA_INSTANCE , tmp);
33379+
33380+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
33381+ RAMFC_WR(DMA_FETCH , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
33382+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
33383+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
33384+
33385+ if (dev_priv->chipset >= 0x17) {
33386+ RAMFC_WR(ACQUIRE_VALUE,
33387+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
33388+ RAMFC_WR(ACQUIRE_TIMESTAMP,
33389+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
33390+ RAMFC_WR(ACQUIRE_TIMEOUT,
33391+ NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
33392+ RAMFC_WR(SEMAPHORE,
33393+ NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
33394+ RAMFC_WR(DMA_SUBROUTINE,
33395+ NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
33396+ }
33397+
33398+ return 0;
33399+}
33400+
33401Index: git/shared-core/nv10_graph.c
33402===================================================================
33403--- /dev/null 1970-01-01 00:00:00.000000000 +0000
33404+++ git/shared-core/nv10_graph.c 2008-12-12 17:35:22.000000000 +0000
33405@@ -0,0 +1,872 @@
33406+/*
33407+ * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
33408+ * All Rights Reserved.
33409+ *
33410+ * Permission is hereby granted, free of charge, to any person obtaining a
33411+ * copy of this software and associated documentation files (the "Software"),
33412+ * to deal in the Software without restriction, including without limitation
33413+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
33414+ * and/or sell copies of the Software, and to permit persons to whom the
33415+ * Software is furnished to do so, subject to the following conditions:
33416+ *
33417+ * The above copyright notice and this permission notice (including the next
33418+ * paragraph) shall be included in all copies or substantial portions of the
33419+ * Software.
33420+ *
33421+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
33422+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33423+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33424+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
33425+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
33426+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
33427+ * DEALINGS IN THE SOFTWARE.
33428+ */
33429+
33430+#include "drmP.h"
33431+#include "drm.h"
33432+#include "nouveau_drm.h"
33433+#include "nouveau_drv.h"
33434+
33435+#define NV10_FIFO_NUMBER 32
33436+
33437+struct pipe_state {
33438+ uint32_t pipe_0x0000[0x040/4];
33439+ uint32_t pipe_0x0040[0x010/4];
33440+ uint32_t pipe_0x0200[0x0c0/4];
33441+ uint32_t pipe_0x4400[0x080/4];
33442+ uint32_t pipe_0x6400[0x3b0/4];
33443+ uint32_t pipe_0x6800[0x2f0/4];
33444+ uint32_t pipe_0x6c00[0x030/4];
33445+ uint32_t pipe_0x7000[0x130/4];
33446+ uint32_t pipe_0x7400[0x0c0/4];
33447+ uint32_t pipe_0x7800[0x0c0/4];
33448+};
33449+
33450+/* TODO dynamic allocation ??? */
33451+static struct pipe_state pipe_state[NV10_FIFO_NUMBER];
33452+
33453+static void nv10_graph_save_pipe(struct nouveau_channel *chan) {
33454+ struct drm_device *dev = chan->dev;
33455+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33456+ struct pipe_state *fifo_pipe_state = pipe_state + chan->id;
33457+ int i;
33458+#define PIPE_SAVE(addr) \
33459+ do { \
33460+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
33461+ for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
33462+ fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \
33463+ } while (0)
33464+
33465+ PIPE_SAVE(0x4400);
33466+ PIPE_SAVE(0x0200);
33467+ PIPE_SAVE(0x6400);
33468+ PIPE_SAVE(0x6800);
33469+ PIPE_SAVE(0x6c00);
33470+ PIPE_SAVE(0x7000);
33471+ PIPE_SAVE(0x7400);
33472+ PIPE_SAVE(0x7800);
33473+ PIPE_SAVE(0x0040);
33474+ PIPE_SAVE(0x0000);
33475+
33476+#undef PIPE_SAVE
33477+}
33478+
33479+static void nv10_graph_load_pipe(struct nouveau_channel *chan) {
33480+ struct drm_device *dev = chan->dev;
33481+ struct drm_nouveau_private *dev_priv = dev->dev_private;
33482+ struct pipe_state *fifo_pipe_state = pipe_state + chan->id;
33483+ int i;
33484+ uint32_t xfmode0, xfmode1;
33485+#define PIPE_RESTORE(addr) \
33486+ do { \
33487+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
33488+ for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
33489+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
33490+ } while (0)
33491+
33492+
33493+ nouveau_wait_for_idle(dev);
33494+ /* XXX check haiku comments */
33495+ xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0);
33496+ xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1);
33497+ NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
33498+ NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
33499+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
33500+ for (i = 0; i < 4; i++)
33501+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
33502+ for (i = 0; i < 4; i++)
33503+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
33504+
33505+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
33506+ for (i = 0; i < 3; i++)
33507+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
33508+
33509+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
33510+ for (i = 0; i < 3; i++)
33511+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
33512+
33513+ NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
33514+ NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
33515+
33516+
33517+ PIPE_RESTORE(0x0200);
33518+ nouveau_wait_for_idle(dev);
33519+
33520+ /* restore XFMODE */
33521+ NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0);
33522+ NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1);
33523+ PIPE_RESTORE(0x6400);
33524+ PIPE_RESTORE(0x6800);
33525+ PIPE_RESTORE(0x6c00);
33526+ PIPE_RESTORE(0x7000);
33527+ PIPE_RESTORE(0x7400);
33528+ PIPE_RESTORE(0x7800);
33529+ PIPE_RESTORE(0x4400);
33530+ PIPE_RESTORE(0x0000);
33531+ PIPE_RESTORE(0x0040);
33532+ nouveau_wait_for_idle(dev);
33533+
33534+#undef PIPE_RESTORE
33535+}
33536+
33537+static void nv10_graph_create_pipe(struct nouveau_channel *chan) {
33538+ struct pipe_state *fifo_pipe_state = pipe_state + chan->id;
33539+ uint32_t *fifo_pipe_state_addr;
33540+ int i;
33541+#define PIPE_INIT(addr) \
33542+ do { \
33543+ fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \
33544+ } while (0)
33545+#define PIPE_INIT_END(addr) \
33546+ do { \
33547+ if (fifo_pipe_state_addr != \
33548+ sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \
33549+ DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \
33550+ sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \
33551+ } while (0)
33552+#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value
33553+
33554+ PIPE_INIT(0x0200);
33555+ for (i = 0; i < 48; i++)
33556+ NV_WRITE_PIPE_INIT(0x00000000);
33557+ PIPE_INIT_END(0x0200);
33558+
33559+ PIPE_INIT(0x6400);
33560+ for (i = 0; i < 211; i++)
33561+ NV_WRITE_PIPE_INIT(0x00000000);
33562+ NV_WRITE_PIPE_INIT(0x3f800000);
33563+ NV_WRITE_PIPE_INIT(0x40000000);
33564+ NV_WRITE_PIPE_INIT(0x40000000);
33565+ NV_WRITE_PIPE_INIT(0x40000000);
33566+ NV_WRITE_PIPE_INIT(0x40000000);
33567+ NV_WRITE_PIPE_INIT(0x00000000);
33568+ NV_WRITE_PIPE_INIT(0x00000000);
33569+ NV_WRITE_PIPE_INIT(0x3f800000);
33570+ NV_WRITE_PIPE_INIT(0x00000000);
33571+ NV_WRITE_PIPE_INIT(0x3f000000);
33572+ NV_WRITE_PIPE_INIT(0x3f000000);
33573+ NV_WRITE_PIPE_INIT(0x00000000);
33574+ NV_WRITE_PIPE_INIT(0x00000000);
33575+ NV_WRITE_PIPE_INIT(0x00000000);
33576+ NV_WRITE_PIPE_INIT(0x00000000);
33577+ NV_WRITE_PIPE_INIT(0x3f800000);
33578+ NV_WRITE_PIPE_INIT(0x00000000);
33579+ NV_WRITE_PIPE_INIT(0x00000000);
33580+ NV_WRITE_PIPE_INIT(0x00000000);
33581+ NV_WRITE_PIPE_INIT(0x00000000);
33582+ NV_WRITE_PIPE_INIT(0x00000000);
33583+ NV_WRITE_PIPE_INIT(0x3f800000);
33584+ NV_WRITE_PIPE_INIT(0x3f800000);
33585+ NV_WRITE_PIPE_INIT(0x3f800000);
33586+ NV_WRITE_PIPE_INIT(0x3f800000);
33587+ PIPE_INIT_END(0x6400);
33588+
33589+ PIPE_INIT(0x6800);
33590+ for (i = 0; i < 162; i++)
33591+ NV_WRITE_PIPE_INIT(0x00000000);
33592+ NV_WRITE_PIPE_INIT(0x3f800000);
33593+ for (i = 0; i < 25; i++)
33594+ NV_WRITE_PIPE_INIT(0x00000000);
33595+ PIPE_INIT_END(0x6800);
33596+
33597+ PIPE_INIT(0x6c00);
33598+ NV_WRITE_PIPE_INIT(0x00000000);
33599+ NV_WRITE_PIPE_INIT(0x00000000);
33600+ NV_WRITE_PIPE_INIT(0x00000000);
33601+ NV_WRITE_PIPE_INIT(0x00000000);
33602+ NV_WRITE_PIPE_INIT(0xbf800000);
33603+ NV_WRITE_PIPE_INIT(0x00000000);
33604+ NV_WRITE_PIPE_INIT(0x00000000);
33605+ NV_WRITE_PIPE_INIT(0x00000000);
33606+ NV_WRITE_PIPE_INIT(0x00000000);
33607+ NV_WRITE_PIPE_INIT(0x00000000);
33608+ NV_WRITE_PIPE_INIT(0x00000000);
33609+ NV_WRITE_PIPE_INIT(0x00000000);
33610+ PIPE_INIT_END(0x6c00);
33611+
33612+ PIPE_INIT(0x7000);
33613+ NV_WRITE_PIPE_INIT(0x00000000);
33614+ NV_WRITE_PIPE_INIT(0x00000000);
33615+ NV_WRITE_PIPE_INIT(0x00000000);
33616+ NV_WRITE_PIPE_INIT(0x00000000);
33617+ NV_WRITE_PIPE_INIT(0x00000000);
33618+ NV_WRITE_PIPE_INIT(0x00000000);
33619+ NV_WRITE_PIPE_INIT(0x00000000);
33620+ NV_WRITE_PIPE_INIT(0x00000000);
33621+ NV_WRITE_PIPE_INIT(0x00000000);
33622+ NV_WRITE_PIPE_INIT(0x00000000);
33623+ NV_WRITE_PIPE_INIT(0x00000000);
33624+ NV_WRITE_PIPE_INIT(0x00000000);
33625+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33626+ NV_WRITE_PIPE_INIT(0x00000000);
33627+ NV_WRITE_PIPE_INIT(0x00000000);
33628+ NV_WRITE_PIPE_INIT(0x00000000);
33629+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33630+ NV_WRITE_PIPE_INIT(0x00000000);
33631+ NV_WRITE_PIPE_INIT(0x00000000);
33632+ NV_WRITE_PIPE_INIT(0x00000000);
33633+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33634+ NV_WRITE_PIPE_INIT(0x00000000);
33635+ NV_WRITE_PIPE_INIT(0x00000000);
33636+ NV_WRITE_PIPE_INIT(0x00000000);
33637+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33638+ NV_WRITE_PIPE_INIT(0x00000000);
33639+ NV_WRITE_PIPE_INIT(0x00000000);
33640+ NV_WRITE_PIPE_INIT(0x00000000);
33641+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33642+ NV_WRITE_PIPE_INIT(0x00000000);
33643+ NV_WRITE_PIPE_INIT(0x00000000);
33644+ NV_WRITE_PIPE_INIT(0x00000000);
33645+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33646+ NV_WRITE_PIPE_INIT(0x00000000);
33647+ NV_WRITE_PIPE_INIT(0x00000000);
33648+ NV_WRITE_PIPE_INIT(0x00000000);
33649+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33650+ NV_WRITE_PIPE_INIT(0x00000000);
33651+ NV_WRITE_PIPE_INIT(0x00000000);
33652+ NV_WRITE_PIPE_INIT(0x00000000);
33653+ NV_WRITE_PIPE_INIT(0x7149f2ca);
33654+ for (i = 0; i < 35; i++)
33655+ NV_WRITE_PIPE_INIT(0x00000000);
33656+ PIPE_INIT_END(0x7000);
33657+
33658+ PIPE_INIT(0x7400);
33659+ for (i = 0; i < 48; i++)
33660+ NV_WRITE_PIPE_INIT(0x00000000);
33661+ PIPE_INIT_END(0x7400);
33662+
33663+ PIPE_INIT(0x7800);
33664+ for (i = 0; i < 48; i++)
33665+ NV_WRITE_PIPE_INIT(0x00000000);
33666+ PIPE_INIT_END(0x7800);
33667+
33668+ PIPE_INIT(0x4400);
33669+ for (i = 0; i < 32; i++)
33670+ NV_WRITE_PIPE_INIT(0x00000000);
33671+ PIPE_INIT_END(0x4400);
33672+
33673+ PIPE_INIT(0x0000);
33674+ for (i = 0; i < 16; i++)
33675+ NV_WRITE_PIPE_INIT(0x00000000);
33676+ PIPE_INIT_END(0x0000);
33677+
33678+ PIPE_INIT(0x0040);
33679+ for (i = 0; i < 4; i++)
33680+ NV_WRITE_PIPE_INIT(0x00000000);
33681+ PIPE_INIT_END(0x0040);
33682+
33683+#undef PIPE_INIT
33684+#undef PIPE_INIT_END
33685+#undef NV_WRITE_PIPE_INIT
33686+}
33687+
33688+static int nv10_graph_ctx_regs [] = {
33689+NV10_PGRAPH_CTX_SWITCH1,
33690+NV10_PGRAPH_CTX_SWITCH2,
33691+NV10_PGRAPH_CTX_SWITCH3,
33692+NV10_PGRAPH_CTX_SWITCH4,
33693+NV10_PGRAPH_CTX_SWITCH5,
33694+NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
33695+NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
33696+NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
33697+NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
33698+NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
33699+0x00400164,
33700+0x00400184,
33701+0x004001a4,
33702+0x004001c4,
33703+0x004001e4,
33704+0x00400168,
33705+0x00400188,
33706+0x004001a8,
33707+0x004001c8,
33708+0x004001e8,
33709+0x0040016c,
33710+0x0040018c,
33711+0x004001ac,
33712+0x004001cc,
33713+0x004001ec,
33714+0x00400170,
33715+0x00400190,
33716+0x004001b0,
33717+0x004001d0,
33718+0x004001f0,
33719+0x00400174,
33720+0x00400194,
33721+0x004001b4,
33722+0x004001d4,
33723+0x004001f4,
33724+0x00400178,
33725+0x00400198,
33726+0x004001b8,
33727+0x004001d8,
33728+0x004001f8,
33729+0x0040017c,
33730+0x0040019c,
33731+0x004001bc,
33732+0x004001dc,
33733+0x004001fc,
33734+NV10_PGRAPH_CTX_USER,
33735+NV04_PGRAPH_DMA_START_0,
33736+NV04_PGRAPH_DMA_START_1,
33737+NV04_PGRAPH_DMA_LENGTH,
33738+NV04_PGRAPH_DMA_MISC,
33739+NV10_PGRAPH_DMA_PITCH,
33740+NV04_PGRAPH_BOFFSET0,
33741+NV04_PGRAPH_BBASE0,
33742+NV04_PGRAPH_BLIMIT0,
33743+NV04_PGRAPH_BOFFSET1,
33744+NV04_PGRAPH_BBASE1,
33745+NV04_PGRAPH_BLIMIT1,
33746+NV04_PGRAPH_BOFFSET2,
33747+NV04_PGRAPH_BBASE2,
33748+NV04_PGRAPH_BLIMIT2,
33749+NV04_PGRAPH_BOFFSET3,
33750+NV04_PGRAPH_BBASE3,
33751+NV04_PGRAPH_BLIMIT3,
33752+NV04_PGRAPH_BOFFSET4,
33753+NV04_PGRAPH_BBASE4,
33754+NV04_PGRAPH_BLIMIT4,
33755+NV04_PGRAPH_BOFFSET5,
33756+NV04_PGRAPH_BBASE5,
33757+NV04_PGRAPH_BLIMIT5,
33758+NV04_PGRAPH_BPITCH0,
33759+NV04_PGRAPH_BPITCH1,
33760+NV04_PGRAPH_BPITCH2,
33761+NV04_PGRAPH_BPITCH3,
33762+NV04_PGRAPH_BPITCH4,
33763+NV10_PGRAPH_SURFACE,
33764+NV10_PGRAPH_STATE,
33765+NV04_PGRAPH_BSWIZZLE2,
33766+NV04_PGRAPH_BSWIZZLE5,
33767+NV04_PGRAPH_BPIXEL,
33768+NV10_PGRAPH_NOTIFY,
33769+NV04_PGRAPH_PATT_COLOR0,
33770+NV04_PGRAPH_PATT_COLOR1,
33771+NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
33772+0x00400904,
33773+0x00400908,
33774+0x0040090c,
33775+0x00400910,
33776+0x00400914,
33777+0x00400918,
33778+0x0040091c,
33779+0x00400920,
33780+0x00400924,
33781+0x00400928,
33782+0x0040092c,
33783+0x00400930,
33784+0x00400934,
33785+0x00400938,
33786+0x0040093c,
33787+0x00400940,
33788+0x00400944,
33789+0x00400948,
33790+0x0040094c,
33791+0x00400950,
33792+0x00400954,
33793+0x00400958,
33794+0x0040095c,
33795+0x00400960,
33796+0x00400964,
33797+0x00400968,
33798+0x0040096c,
33799+0x00400970,
33800+0x00400974,
33801+0x00400978,
33802+0x0040097c,
33803+0x00400980,
33804+0x00400984,
33805+0x00400988,
33806+0x0040098c,
33807+0x00400990,
33808+0x00400994,
33809+0x00400998,
33810+0x0040099c,
33811+0x004009a0,
33812+0x004009a4,
33813+0x004009a8,
33814+0x004009ac,
33815+0x004009b0,
33816+0x004009b4,
33817+0x004009b8,
33818+0x004009bc,
33819+0x004009c0,
33820+0x004009c4,
33821+0x004009c8,
33822+0x004009cc,
33823+0x004009d0,
33824+0x004009d4,
33825+0x004009d8,
33826+0x004009dc,
33827+0x004009e0,
33828+0x004009e4,
33829+0x004009e8,
33830+0x004009ec,
33831+0x004009f0,
33832+0x004009f4,
33833+0x004009f8,
33834+0x004009fc,
33835+NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
33836+0x0040080c,
33837+NV04_PGRAPH_PATTERN_SHAPE,
33838+NV03_PGRAPH_MONO_COLOR0,
33839+NV04_PGRAPH_ROP3,
33840+NV04_PGRAPH_CHROMA,
33841+NV04_PGRAPH_BETA_AND,
33842+NV04_PGRAPH_BETA_PREMULT,
33843+0x00400e70,
33844+0x00400e74,
33845+0x00400e78,
33846+0x00400e7c,
33847+0x00400e80,
33848+0x00400e84,
33849+0x00400e88,
33850+0x00400e8c,
33851+0x00400ea0,
33852+0x00400ea4,
33853+0x00400ea8,
33854+0x00400e90,
33855+0x00400e94,
33856+0x00400e98,
33857+0x00400e9c,
33858+NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */
33859+NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
33860+0x00400f04,
33861+0x00400f24,
33862+0x00400f08,
33863+0x00400f28,
33864+0x00400f0c,
33865+0x00400f2c,
33866+0x00400f10,
33867+0x00400f30,
33868+0x00400f14,
33869+0x00400f34,
33870+0x00400f18,
33871+0x00400f38,
33872+0x00400f1c,
33873+0x00400f3c,
33874+NV10_PGRAPH_XFMODE0,
33875+NV10_PGRAPH_XFMODE1,
33876+NV10_PGRAPH_GLOBALSTATE0,
33877+NV10_PGRAPH_GLOBALSTATE1,
33878+NV04_PGRAPH_STORED_FMT,
33879+NV04_PGRAPH_SOURCE_COLOR,
33880+NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
33881+NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
33882+0x00400404,
33883+0x00400484,
33884+0x00400408,
33885+0x00400488,
33886+0x0040040c,
33887+0x0040048c,
33888+0x00400410,
33889+0x00400490,
33890+0x00400414,
33891+0x00400494,
33892+0x00400418,
33893+0x00400498,
33894+0x0040041c,
33895+0x0040049c,
33896+0x00400420,
33897+0x004004a0,
33898+0x00400424,
33899+0x004004a4,
33900+0x00400428,
33901+0x004004a8,
33902+0x0040042c,
33903+0x004004ac,
33904+0x00400430,
33905+0x004004b0,
33906+0x00400434,
33907+0x004004b4,
33908+0x00400438,
33909+0x004004b8,
33910+0x0040043c,
33911+0x004004bc,
33912+0x00400440,
33913+0x004004c0,
33914+0x00400444,
33915+0x004004c4,
33916+0x00400448,
33917+0x004004c8,
33918+0x0040044c,
33919+0x004004cc,
33920+0x00400450,
33921+0x004004d0,
33922+0x00400454,
33923+0x004004d4,
33924+0x00400458,
33925+0x004004d8,
33926+0x0040045c,
33927+0x004004dc,
33928+0x00400460,
33929+0x004004e0,
33930+0x00400464,
33931+0x004004e4,
33932+0x00400468,
33933+0x004004e8,
33934+0x0040046c,
33935+0x004004ec,
33936+0x00400470,
33937+0x004004f0,
33938+0x00400474,
33939+0x004004f4,
33940+0x00400478,
33941+0x004004f8,
33942+0x0040047c,
33943+0x004004fc,
33944+NV03_PGRAPH_ABS_UCLIP_XMIN,
33945+NV03_PGRAPH_ABS_UCLIP_XMAX,
33946+NV03_PGRAPH_ABS_UCLIP_YMIN,
33947+NV03_PGRAPH_ABS_UCLIP_YMAX,
33948+0x00400550,
33949+0x00400558,
33950+0x00400554,
33951+0x0040055c,
33952+NV03_PGRAPH_ABS_UCLIPA_XMIN,
33953+NV03_PGRAPH_ABS_UCLIPA_XMAX,
33954+NV03_PGRAPH_ABS_UCLIPA_YMIN,
33955+NV03_PGRAPH_ABS_UCLIPA_YMAX,
33956+NV03_PGRAPH_ABS_ICLIP_XMAX,
33957+NV03_PGRAPH_ABS_ICLIP_YMAX,
33958+NV03_PGRAPH_XY_LOGIC_MISC0,
33959+NV03_PGRAPH_XY_LOGIC_MISC1,
33960+NV03_PGRAPH_XY_LOGIC_MISC2,
33961+NV03_PGRAPH_XY_LOGIC_MISC3,
33962+NV03_PGRAPH_CLIPX_0,
33963+NV03_PGRAPH_CLIPX_1,
33964+NV03_PGRAPH_CLIPY_0,
33965+NV03_PGRAPH_CLIPY_1,
33966+NV10_PGRAPH_COMBINER0_IN_ALPHA,
33967+NV10_PGRAPH_COMBINER1_IN_ALPHA,
33968+NV10_PGRAPH_COMBINER0_IN_RGB,
33969+NV10_PGRAPH_COMBINER1_IN_RGB,
33970+NV10_PGRAPH_COMBINER_COLOR0,
33971+NV10_PGRAPH_COMBINER_COLOR1,
33972+NV10_PGRAPH_COMBINER0_OUT_ALPHA,
33973+NV10_PGRAPH_COMBINER1_OUT_ALPHA,
33974+NV10_PGRAPH_COMBINER0_OUT_RGB,
33975+NV10_PGRAPH_COMBINER1_OUT_RGB,
33976+NV10_PGRAPH_COMBINER_FINAL0,
33977+NV10_PGRAPH_COMBINER_FINAL1,
33978+0x00400e00,
33979+0x00400e04,
33980+0x00400e08,
33981+0x00400e0c,
33982+0x00400e10,
33983+0x00400e14,
33984+0x00400e18,
33985+0x00400e1c,
33986+0x00400e20,
33987+0x00400e24,
33988+0x00400e28,
33989+0x00400e2c,
33990+0x00400e30,
33991+0x00400e34,
33992+0x00400e38,
33993+0x00400e3c,
33994+NV04_PGRAPH_PASSTHRU_0,
33995+NV04_PGRAPH_PASSTHRU_1,
33996+NV04_PGRAPH_PASSTHRU_2,
33997+NV10_PGRAPH_DIMX_TEXTURE,
33998+NV10_PGRAPH_WDIMX_TEXTURE,
33999+NV10_PGRAPH_DVD_COLORFMT,
34000+NV10_PGRAPH_SCALED_FORMAT,
34001+NV04_PGRAPH_MISC24_0,
34002+NV04_PGRAPH_MISC24_1,
34003+NV04_PGRAPH_MISC24_2,
34004+NV03_PGRAPH_X_MISC,
34005+NV03_PGRAPH_Y_MISC,
34006+NV04_PGRAPH_VALID1,
34007+NV04_PGRAPH_VALID2,
34008+};
34009+
34010+static int nv17_graph_ctx_regs [] = {
34011+NV10_PGRAPH_DEBUG_4,
34012+0x004006b0,
34013+0x00400eac,
34014+0x00400eb0,
34015+0x00400eb4,
34016+0x00400eb8,
34017+0x00400ebc,
34018+0x00400ec0,
34019+0x00400ec4,
34020+0x00400ec8,
34021+0x00400ecc,
34022+0x00400ed0,
34023+0x00400ed4,
34024+0x00400ed8,
34025+0x00400edc,
34026+0x00400ee0,
34027+0x00400a00,
34028+0x00400a04,
34029+};
34030+
34031+static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
34032+{
34033+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34034+ int i, j;
34035+ for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) {
34036+ if (nv10_graph_ctx_regs[i] == reg)
34037+ return i;
34038+ }
34039+ if (dev_priv->chipset>=0x17) {
34040+ for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) {
34041+ if (nv17_graph_ctx_regs[j] == reg)
34042+ return i;
34043+ }
34044+ }
34045+ return -1;
34046+}
34047+
34048+int nv10_graph_load_context(struct nouveau_channel *chan)
34049+{
34050+ struct drm_device *dev = chan->dev;
34051+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34052+ int i, j;
34053+
34054+ for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
34055+ NV_WRITE(nv10_graph_ctx_regs[i], chan->pgraph_ctx[i]);
34056+ if (dev_priv->chipset>=0x17) {
34057+ for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
34058+ NV_WRITE(nv17_graph_ctx_regs[j], chan->pgraph_ctx[i]);
34059+ }
34060+
34061+ nv10_graph_load_pipe(chan);
34062+
34063+ return 0;
34064+}
34065+
34066+int nv10_graph_save_context(struct nouveau_channel *chan)
34067+{
34068+ struct drm_device *dev = chan->dev;
34069+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34070+ int i, j;
34071+
34072+ for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
34073+ chan->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
34074+ if (dev_priv->chipset>=0x17) {
34075+ for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
34076+ chan->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
34077+ }
34078+
34079+ nv10_graph_save_pipe(chan);
34080+
34081+ return 0;
34082+}
34083+
34084+void nouveau_nv10_context_switch(struct drm_device *dev)
34085+{
34086+ struct drm_nouveau_private *dev_priv;
34087+ struct nouveau_channel *next, *last;
34088+ int chid;
34089+
34090+ if (!dev) {
34091+ DRM_DEBUG("Invalid drm_device\n");
34092+ return;
34093+ }
34094+ dev_priv = dev->dev_private;
34095+ if (!dev_priv) {
34096+ DRM_DEBUG("Invalid drm_nouveau_private\n");
34097+ return;
34098+ }
34099+ if (!dev_priv->fifos) {
34100+ DRM_DEBUG("Invalid drm_nouveau_private->fifos\n");
34101+ return;
34102+ }
34103+
34104+ chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1);
34105+ next = dev_priv->fifos[chid];
34106+
34107+ if (!next) {
34108+ DRM_DEBUG("Invalid next channel\n");
34109+ return;
34110+ }
34111+
34112+ chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
34113+ last = dev_priv->fifos[chid];
34114+
34115+ if (!last) {
34116+ DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n",
34117+ next->id);
34118+ } else {
34119+ DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",
34120+ last->id, next->id);
34121+ }
34122+
34123+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
34124+ if (last) {
34125+ nouveau_wait_for_idle(dev);
34126+ nv10_graph_save_context(last);
34127+ }
34128+
34129+ nouveau_wait_for_idle(dev);
34130+
34131+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
34132+
34133+ nouveau_wait_for_idle(dev);
34134+
34135+ nv10_graph_load_context(next);
34136+
34137+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
34138+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
34139+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
34140+}
34141+
34142+#define NV_WRITE_CTX(reg, val) do { \
34143+ int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
34144+ if (offset > 0) \
34145+ chan->pgraph_ctx[offset] = val; \
34146+ } while (0)
34147+
34148+int nv10_graph_create_context(struct nouveau_channel *chan) {
34149+ struct drm_device *dev = chan->dev;
34150+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34151+
34152+ DRM_DEBUG("nv10_graph_context_create %d\n", chan->id);
34153+
34154+ memset(chan->pgraph_ctx, 0, sizeof(chan->pgraph_ctx));
34155+
34156+ /* mmio trace suggest that should be done in ddx with methods/objects */
34157+#if 0
34158+ uint32_t tmp, vramsz;
34159+ /* per channel init from ddx */
34160+ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
34161+ /*XXX the original ddx code, does this in 2 steps :
34162+ * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
34163+ * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
34164+ * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
34165+ * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
34166+ */
34167+ tmp |= 0x00020100;
34168+ NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp);
34169+
34170+ vramsz = drm_get_resource_len(dev, 0) - 1;
34171+ NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0);
34172+ NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0);
34173+ NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz);
34174+ NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz);
34175+
34176+ NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
34177+ NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
34178+
34179+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
34180+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
34181+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
34182+ NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
34183+#endif
34184+
34185+ NV_WRITE_CTX(0x00400e88, 0x08000000);
34186+ NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
34187+ NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
34188+ NV_WRITE_CTX(0x00400e10, 0x00001000);
34189+ NV_WRITE_CTX(0x00400e14, 0x00001000);
34190+ NV_WRITE_CTX(0x00400e30, 0x00080008);
34191+ NV_WRITE_CTX(0x00400e34, 0x00080008);
34192+ if (dev_priv->chipset>=0x17) {
34193+ /* is it really needed ??? */
34194+ NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4));
34195+ NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0));
34196+ NV_WRITE_CTX(0x00400eac, 0x0fff0000);
34197+ NV_WRITE_CTX(0x00400eb0, 0x0fff0000);
34198+ NV_WRITE_CTX(0x00400ec0, 0x00000080);
34199+ NV_WRITE_CTX(0x00400ed0, 0x00000080);
34200+ }
34201+ NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24);
34202+
34203+ nv10_graph_create_pipe(chan);
34204+ return 0;
34205+}
34206+
34207+void nv10_graph_destroy_context(struct nouveau_channel *chan)
34208+{
34209+ struct drm_device *dev = chan->dev;
34210+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34211+ int chid;
34212+ chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
34213+
34214+ /* does this avoid a potential context switch while we are written graph
34215+ * reg, or we should mask graph interrupt ???
34216+ */
34217+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
34218+ if (chid == chan->id) {
34219+ DRM_INFO("cleanning a channel with graph in current context\n");
34220+ nouveau_wait_for_idle(dev);
34221+ DRM_INFO("reseting current graph context\n");
34222+ nv10_graph_create_context(chan);
34223+ nv10_graph_load_context(chan);
34224+ }
34225+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
34226+}
34227+
34228+int nv10_graph_init(struct drm_device *dev) {
34229+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34230+ int i;
34231+
34232+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
34233+ ~NV_PMC_ENABLE_PGRAPH);
34234+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
34235+ NV_PMC_ENABLE_PGRAPH);
34236+
34237+ NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
34238+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
34239+
34240+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
34241+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
34242+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
34243+ //NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */
34244+ NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
34245+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
34246+ (1<<29) |
34247+ (1<<31));
34248+ if (dev_priv->chipset>=0x17) {
34249+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000);
34250+ NV_WRITE(0x004006b0, 0x40000020);
34251+ }
34252+ else
34253+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
34254+
34255+ /* copy tile info from PFB */
34256+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
34257+ NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
34258+ NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
34259+ NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
34260+ NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
34261+ }
34262+
34263+ NV_WRITE(NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
34264+ NV_WRITE(NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
34265+ NV_WRITE(NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
34266+ NV_WRITE(NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
34267+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
34268+ NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
34269+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
34270+
34271+ return 0;
34272+}
34273+
34274+void nv10_graph_takedown(struct drm_device *dev)
34275+{
34276+}
34277+
34278Index: git/shared-core/nv20_graph.c
34279===================================================================
34280--- /dev/null 1970-01-01 00:00:00.000000000 +0000
34281+++ git/shared-core/nv20_graph.c 2008-12-12 17:35:22.000000000 +0000
34282@@ -0,0 +1,249 @@
34283+/*
34284+ * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
34285+ * All Rights Reserved.
34286+ *
34287+ * Permission is hereby granted, free of charge, to any person obtaining a
34288+ * copy of this software and associated documentation files (the "Software"),
34289+ * to deal in the Software without restriction, including without limitation
34290+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
34291+ * and/or sell copies of the Software, and to permit persons to whom the
34292+ * Software is furnished to do so, subject to the following conditions:
34293+ *
34294+ * The above copyright notice and this permission notice (including the next
34295+ * paragraph) shall be included in all copies or substantial portions of the
34296+ * Software.
34297+ *
34298+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
34299+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
34300+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
34301+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
34302+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
34303+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
34304+ * DEALINGS IN THE SOFTWARE.
34305+ */
34306+
34307+#include "drmP.h"
34308+#include "drm.h"
34309+#include "nouveau_drv.h"
34310+#include "nouveau_drm.h"
34311+
34312+#define NV20_GRCTX_SIZE (3529*4)
34313+
34314+int nv20_graph_create_context(struct nouveau_channel *chan) {
34315+ struct drm_device *dev = chan->dev;
34316+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34317+ unsigned int ctx_size = NV20_GRCTX_SIZE;
34318+ int ret;
34319+
34320+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
34321+ NVOBJ_FLAG_ZERO_ALLOC,
34322+ &chan->ramin_grctx)))
34323+ return ret;
34324+
34325+ /* Initialise default context values */
34326+ INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); /* CTX_USER */
34327+
34328+ INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
34329+ chan->ramin_grctx->instance >> 4);
34330+ return 0;
34331+}
34332+
34333+void nv20_graph_destroy_context(struct nouveau_channel *chan) {
34334+ struct drm_device *dev = chan->dev;
34335+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34336+
34337+ nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
34338+
34339+ INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
34340+}
34341+
34342+static void nv20_graph_rdi(struct drm_device *dev) {
34343+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34344+ int i;
34345+
34346+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x2c80000);
34347+ for (i = 0; i < 32; i++)
34348+ NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
34349+
34350+ nouveau_wait_for_idle(dev);
34351+}
34352+
34353+/* Save current context (from PGRAPH) into the channel's context
34354+ */
34355+int nv20_graph_save_context(struct nouveau_channel *chan) {
34356+ struct drm_device *dev = chan->dev;
34357+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34358+ uint32_t instance;
34359+
34360+ instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id);
34361+ if (!instance) {
34362+ return -EINVAL;
34363+ }
34364+ if (instance != (chan->ramin_grctx->instance >> 4))
34365+ DRM_ERROR("nv20_graph_save_context : bad instance\n");
34366+
34367+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
34368+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 2 /* save ctx */);
34369+ return 0;
34370+}
34371+
34372+
34373+/* Restore the context for a specific channel into PGRAPH
34374+ */
34375+int nv20_graph_load_context(struct nouveau_channel *chan) {
34376+ struct drm_device *dev = chan->dev;
34377+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34378+ uint32_t instance;
34379+
34380+ instance = INSTANCE_RD(dev_priv->ctx_table->gpuobj, chan->id);
34381+ if (!instance) {
34382+ return -EINVAL;
34383+ }
34384+ if (instance != (chan->ramin_grctx->instance >> 4))
34385+ DRM_ERROR("nv20_graph_load_context_current : bad instance\n");
34386+
34387+ NV_WRITE(NV10_PGRAPH_CTX_USER, chan->id << 24);
34388+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, instance);
34389+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_POINTER, 1 /* restore ctx */);
34390+ return 0;
34391+}
34392+
34393+void nouveau_nv20_context_switch(struct drm_device *dev)
34394+{
34395+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34396+ struct nouveau_channel *next, *last;
34397+ int chid;
34398+
34399+ chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
34400+ next = dev_priv->fifos[chid];
34401+
34402+ chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
34403+ last = dev_priv->fifos[chid];
34404+
34405+ DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",
34406+ last->id, next->id);
34407+
34408+ NV_WRITE(NV04_PGRAPH_FIFO,0x0);
34409+
34410+ nv20_graph_save_context(last);
34411+
34412+ nouveau_wait_for_idle(dev);
34413+
34414+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
34415+
34416+ nv20_graph_load_context(next);
34417+
34418+ nouveau_wait_for_idle(dev);
34419+
34420+ if ((NV_READ(NV10_PGRAPH_CTX_USER) >> 24) != next->id)
34421+ DRM_ERROR("nouveau_nv20_context_switch : wrong channel restored %x %x!!!\n", next->id, NV_READ(NV10_PGRAPH_CTX_USER) >> 24);
34422+
34423+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
34424+ NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
34425+
34426+ NV_WRITE(NV04_PGRAPH_FIFO,0x1);
34427+}
34428+
34429+int nv20_graph_init(struct drm_device *dev) {
34430+ struct drm_nouveau_private *dev_priv =
34431+ (struct drm_nouveau_private *)dev->dev_private;
34432+ uint32_t tmp, vramsz;
34433+ int ret, i;
34434+
34435+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
34436+ ~NV_PMC_ENABLE_PGRAPH);
34437+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
34438+ NV_PMC_ENABLE_PGRAPH);
34439+
34440+ /* Create Context Pointer Table */
34441+ dev_priv->ctx_table_size = 32 * 4;
34442+ if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
34443+ dev_priv->ctx_table_size, 16,
34444+ NVOBJ_FLAG_ZERO_ALLOC,
34445+ &dev_priv->ctx_table)))
34446+ return ret;
34447+
34448+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE,
34449+ dev_priv->ctx_table->instance >> 4);
34450+
34451+ //XXX need to be done and save/restore for each fifo ???
34452+ nv20_graph_rdi(dev);
34453+
34454+ NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
34455+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
34456+
34457+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
34458+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
34459+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
34460+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0431);
34461+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
34462+ NV_WRITE(0x40009C , 0x00000040);
34463+
34464+ if (dev_priv->chipset >= 0x25) {
34465+ NV_WRITE(0x400890, 0x00080000);
34466+ NV_WRITE(0x400610, 0x304B1FB6);
34467+ NV_WRITE(0x400B80, 0x18B82880);
34468+ NV_WRITE(0x400B84, 0x44000000);
34469+ NV_WRITE(0x400098, 0x40000080);
34470+ NV_WRITE(0x400B88, 0x000000ff);
34471+ } else {
34472+ NV_WRITE(0x400880, 0x00080000);
34473+ NV_WRITE(0x400094, 0x00000005);
34474+ NV_WRITE(0x400B80, 0x45CAA208);
34475+ NV_WRITE(0x400B84, 0x24000000);
34476+ NV_WRITE(0x400098, 0x00000040);
34477+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
34478+ NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
34479+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038);
34480+ NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
34481+ }
34482+
34483+ /* copy tile info from PFB */
34484+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
34485+ NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
34486+ NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
34487+ NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
34488+ NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
34489+ }
34490+
34491+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
34492+ NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
34493+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
34494+
34495+ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
34496+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
34497+ tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
34498+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
34499+
34500+ /* begin RAM config */
34501+ vramsz = drm_get_resource_len(dev, 0) - 1;
34502+ NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
34503+ NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
34504+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
34505+ NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0));
34506+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
34507+ NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1));
34508+ NV_WRITE(0x400820, 0);
34509+ NV_WRITE(0x400824, 0);
34510+ NV_WRITE(0x400864, vramsz-1);
34511+ NV_WRITE(0x400868, vramsz-1);
34512+
34513+ /* interesting.. the below overwrites some of the tile setup above.. */
34514+ NV_WRITE(0x400B20, 0x00000000);
34515+ NV_WRITE(0x400B04, 0xFFFFFFFF);
34516+
34517+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
34518+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
34519+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
34520+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
34521+
34522+ return 0;
34523+}
34524+
34525+void nv20_graph_takedown(struct drm_device *dev)
34526+{
34527+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34528+
34529+ nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table);
34530+}
34531+
34532Index: git/shared-core/nv30_graph.c
34533===================================================================
34534--- /dev/null 1970-01-01 00:00:00.000000000 +0000
34535+++ git/shared-core/nv30_graph.c 2008-12-12 17:35:22.000000000 +0000
34536@@ -0,0 +1,2912 @@
34537+/*
34538+ * Based on nv40_graph.c
34539+ * Someday this will all go away...
34540+ */
34541+#include "drmP.h"
34542+#include "drm.h"
34543+#include "nouveau_drv.h"
34544+#include "nouveau_drm.h"
34545+
34546+/*
34547+ * There are 3 families :
34548+ * NV30 is 0x10de:0x030*
34549+ * NV31 is 0x10de:0x031*
34550+ *
34551+ * NV34 is 0x10de:0x032*
34552+ *
34553+ * NV35 is 0x10de:0x033* (NV35 and NV36 are the same)
34554+ * NV36 is 0x10de:0x034*
34555+ *
34556+ * Not seen in the wild, no dumps (probably NV35) :
34557+ * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
34558+ * NV38 is 0x10de:0x0333, 0x10de:0x00fe
34559+ *
34560+ */
34561+
34562+
34563+#define NV30_31_GRCTX_SIZE (22392)
34564+#define NV34_GRCTX_SIZE (18140)
34565+#define NV35_36_GRCTX_SIZE (22396)
34566+
34567+static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
34568+{
34569+ struct drm_nouveau_private *dev_priv = dev->dev_private;
34570+ int i;
34571+
34572+ INSTANCE_WR(ctx, 0x410/4, 0x00000101);
34573+ INSTANCE_WR(ctx, 0x424/4, 0x00000111);
34574+ INSTANCE_WR(ctx, 0x428/4, 0x00000060);
34575+ INSTANCE_WR(ctx, 0x444/4, 0x00000080);
34576+ INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
34577+ INSTANCE_WR(ctx, 0x44c/4, 0x00000001);
34578+ INSTANCE_WR(ctx, 0x460/4, 0x44400000);
34579+ INSTANCE_WR(ctx, 0x48c/4, 0xffff0000);
34580+ for(i = 0x4e0; i< 0x4e8; i += 4)
34581+ INSTANCE_WR(ctx, i/4, 0x0fff0000);
34582+ INSTANCE_WR(ctx, 0x4ec/4, 0x00011100);
34583+ for(i = 0x508; i< 0x548; i += 4)
34584+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
34585+ INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff);
34586+ INSTANCE_WR(ctx, 0x58c/4, 0x00000080);
34587+ INSTANCE_WR(ctx, 0x590/4, 0x30201000);
34588+ INSTANCE_WR(ctx, 0x594/4, 0x70605040);
34589+ INSTANCE_WR(ctx, 0x598/4, 0xb8a89888);
34590+ INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8);
34591+ INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000);
34592+ for(i = 0x600; i< 0x640; i += 4)
34593+ INSTANCE_WR(ctx, i/4, 0x00010588);
34594+ for(i = 0x640; i< 0x680; i += 4)
34595+ INSTANCE_WR(ctx, i/4, 0x00030303);
34596+ for(i = 0x6c0; i< 0x700; i += 4)
34597+ INSTANCE_WR(ctx, i/4, 0x0008aae4);
34598+ for(i = 0x700; i< 0x740; i += 4)
34599+ INSTANCE_WR(ctx, i/4, 0x01012000);
34600+ for(i = 0x740; i< 0x780; i += 4)
34601+ INSTANCE_WR(ctx, i/4, 0x00080008);
34602+ INSTANCE_WR(ctx, 0x85c/4, 0x00040000);
34603+ INSTANCE_WR(ctx, 0x860/4, 0x00010000);
34604+ for(i = 0x864; i< 0x874; i += 4)
34605+ INSTANCE_WR(ctx, i/4, 0x00040004);
34606+ INSTANCE_WR(ctx, 0x1f18/4, 0x10700ff9);
34607+ INSTANCE_WR(ctx, 0x1f1c/4, 0x0436086c);
34608+ INSTANCE_WR(ctx, 0x1f20/4, 0x000c001b);
34609+ INSTANCE_WR(ctx, 0x1f28/4, 0x10700ff9);
34610+ INSTANCE_WR(ctx, 0x1f2c/4, 0x0436086c);
34611+ INSTANCE_WR(ctx, 0x1f30/4, 0x000c001b);
34612+ INSTANCE_WR(ctx, 0x1f38/4, 0x10700ff9);
34613+ INSTANCE_WR(ctx, 0x1f3c/4, 0x0436086c);
34614+ INSTANCE_WR(ctx, 0x1f40/4, 0x000c001b);
34615+ INSTANCE_WR(ctx, 0x1f48/4, 0x10700ff9);
34616+ INSTANCE_WR(ctx, 0x1f4c/4, 0x0436086c);
34617+ INSTANCE_WR(ctx, 0x1f50/4, 0x000c001b);
34618+ INSTANCE_WR(ctx, 0x1f58/4, 0x10700ff9);
34619+ INSTANCE_WR(ctx, 0x1f5c/4, 0x0436086c);
34620+ INSTANCE_WR(ctx, 0x1f60/4, 0x000c001b);
34621+ INSTANCE_WR(ctx, 0x1f68/4, 0x10700ff9);
34622+ INSTANCE_WR(ctx, 0x1f6c/4, 0x0436086c);
34623+ INSTANCE_WR(ctx, 0x1f70/4, 0x000c001b);
34624+ INSTANCE_WR(ctx, 0x1f78/4, 0x10700ff9);
34625+ INSTANCE_WR(ctx, 0x1f7c/4, 0x0436086c);
34626+ INSTANCE_WR(ctx, 0x1f80/4, 0x000c001b);
34627+ INSTANCE_WR(ctx, 0x1f88/4, 0x10700ff9);
34628+ INSTANCE_WR(ctx, 0x1f8c/4, 0x0436086c);
34629+ INSTANCE_WR(ctx, 0x1f90/4, 0x000c001b);
34630+ INSTANCE_WR(ctx, 0x1f98/4, 0x10700ff9);
34631+ INSTANCE_WR(ctx, 0x1f9c/4, 0x0436086c);
34632+ INSTANCE_WR(ctx, 0x1fa0/4, 0x000c001b);
34633+ INSTANCE_WR(ctx, 0x1fa8/4, 0x10700ff9);
34634+ INSTANCE_WR(ctx, 0x1fac/4, 0x0436086c);
34635+ INSTANCE_WR(ctx, 0x1fb0/4, 0x000c001b);
34636+ INSTANCE_WR(ctx, 0x1fb8/4, 0x10700ff9);
34637+ INSTANCE_WR(ctx, 0x1fbc/4, 0x0436086c);
34638+ INSTANCE_WR(ctx, 0x1fc0/4, 0x000c001b);
34639+ INSTANCE_WR(ctx, 0x1fc8/4, 0x10700ff9);
34640+ INSTANCE_WR(ctx, 0x1fcc/4, 0x0436086c);
34641+ INSTANCE_WR(ctx, 0x1fd0/4, 0x000c001b);
34642+ INSTANCE_WR(ctx, 0x1fd8/4, 0x10700ff9);
34643+ INSTANCE_WR(ctx, 0x1fdc/4, 0x0436086c);
34644+ INSTANCE_WR(ctx, 0x1fe0/4, 0x000c001b);
34645+ INSTANCE_WR(ctx, 0x1fe8/4, 0x10700ff9);
34646+ INSTANCE_WR(ctx, 0x1fec/4, 0x0436086c);
34647+ INSTANCE_WR(ctx, 0x1ff0/4, 0x000c001b);
34648+ INSTANCE_WR(ctx, 0x1ff8/4, 0x10700ff9);
34649+ INSTANCE_WR(ctx, 0x1ffc/4, 0x0436086c);
34650+ INSTANCE_WR(ctx, 0x2000/4, 0x000c001b);
34651+ INSTANCE_WR(ctx, 0x2008/4, 0x10700ff9);
34652+ INSTANCE_WR(ctx, 0x200c/4, 0x0436086c);
34653+ INSTANCE_WR(ctx, 0x2010/4, 0x000c001b);
34654+ INSTANCE_WR(ctx, 0x2018/4, 0x10700ff9);
34655+ INSTANCE_WR(ctx, 0x201c/4, 0x0436086c);
34656+ INSTANCE_WR(ctx, 0x2020/4, 0x000c001b);
34657+ INSTANCE_WR(ctx, 0x2028/4, 0x10700ff9);
34658+ INSTANCE_WR(ctx, 0x202c/4, 0x0436086c);
34659+ INSTANCE_WR(ctx, 0x2030/4, 0x000c001b);
34660+ INSTANCE_WR(ctx, 0x2038/4, 0x10700ff9);
34661+ INSTANCE_WR(ctx, 0x203c/4, 0x0436086c);
34662+ INSTANCE_WR(ctx, 0x2040/4, 0x000c001b);
34663+ INSTANCE_WR(ctx, 0x2048/4, 0x10700ff9);
34664+ INSTANCE_WR(ctx, 0x204c/4, 0x0436086c);
34665+ INSTANCE_WR(ctx, 0x2050/4, 0x000c001b);
34666+ INSTANCE_WR(ctx, 0x2058/4, 0x10700ff9);
34667+ INSTANCE_WR(ctx, 0x205c/4, 0x0436086c);
34668+ INSTANCE_WR(ctx, 0x2060/4, 0x000c001b);
34669+ INSTANCE_WR(ctx, 0x2068/4, 0x10700ff9);
34670+ INSTANCE_WR(ctx, 0x206c/4, 0x0436086c);
34671+ INSTANCE_WR(ctx, 0x2070/4, 0x000c001b);
34672+ INSTANCE_WR(ctx, 0x2078/4, 0x10700ff9);
34673+ INSTANCE_WR(ctx, 0x207c/4, 0x0436086c);
34674+ INSTANCE_WR(ctx, 0x2080/4, 0x000c001b);
34675+ INSTANCE_WR(ctx, 0x2088/4, 0x10700ff9);
34676+ INSTANCE_WR(ctx, 0x208c/4, 0x0436086c);
34677+ INSTANCE_WR(ctx, 0x2090/4, 0x000c001b);
34678+ INSTANCE_WR(ctx, 0x2098/4, 0x10700ff9);
34679+ INSTANCE_WR(ctx, 0x209c/4, 0x0436086c);
34680+ INSTANCE_WR(ctx, 0x20a0/4, 0x000c001b);
34681+ INSTANCE_WR(ctx, 0x20a8/4, 0x10700ff9);
34682+ INSTANCE_WR(ctx, 0x20ac/4, 0x0436086c);
34683+ INSTANCE_WR(ctx, 0x20b0/4, 0x000c001b);
34684+ INSTANCE_WR(ctx, 0x20b8/4, 0x10700ff9);
34685+ INSTANCE_WR(ctx, 0x20bc/4, 0x0436086c);
34686+ INSTANCE_WR(ctx, 0x20c0/4, 0x000c001b);
34687+ INSTANCE_WR(ctx, 0x20c8/4, 0x10700ff9);
34688+ INSTANCE_WR(ctx, 0x20cc/4, 0x0436086c);
34689+ INSTANCE_WR(ctx, 0x20d0/4, 0x000c001b);
34690+ INSTANCE_WR(ctx, 0x20d8/4, 0x10700ff9);
34691+ INSTANCE_WR(ctx, 0x20dc/4, 0x0436086c);
34692+ INSTANCE_WR(ctx, 0x20e0/4, 0x000c001b);
34693+ INSTANCE_WR(ctx, 0x20e8/4, 0x10700ff9);
34694+ INSTANCE_WR(ctx, 0x20ec/4, 0x0436086c);
34695+ INSTANCE_WR(ctx, 0x20f0/4, 0x000c001b);
34696+ INSTANCE_WR(ctx, 0x20f8/4, 0x10700ff9);
34697+ INSTANCE_WR(ctx, 0x20fc/4, 0x0436086c);
34698+ INSTANCE_WR(ctx, 0x2100/4, 0x000c001b);
34699+ INSTANCE_WR(ctx, 0x2108/4, 0x10700ff9);
34700+ INSTANCE_WR(ctx, 0x210c/4, 0x0436086c);
34701+ INSTANCE_WR(ctx, 0x2110/4, 0x000c001b);
34702+ INSTANCE_WR(ctx, 0x2118/4, 0x10700ff9);
34703+ INSTANCE_WR(ctx, 0x211c/4, 0x0436086c);
34704+ INSTANCE_WR(ctx, 0x2120/4, 0x000c001b);
34705+ INSTANCE_WR(ctx, 0x2128/4, 0x10700ff9);
34706+ INSTANCE_WR(ctx, 0x212c/4, 0x0436086c);
34707+ INSTANCE_WR(ctx, 0x2130/4, 0x000c001b);
34708+ INSTANCE_WR(ctx, 0x2138/4, 0x10700ff9);
34709+ INSTANCE_WR(ctx, 0x213c/4, 0x0436086c);
34710+ INSTANCE_WR(ctx, 0x2140/4, 0x000c001b);
34711+ INSTANCE_WR(ctx, 0x2148/4, 0x10700ff9);
34712+ INSTANCE_WR(ctx, 0x214c/4, 0x0436086c);
34713+ INSTANCE_WR(ctx, 0x2150/4, 0x000c001b);
34714+ INSTANCE_WR(ctx, 0x2158/4, 0x10700ff9);
34715+ INSTANCE_WR(ctx, 0x215c/4, 0x0436086c);
34716+ INSTANCE_WR(ctx, 0x2160/4, 0x000c001b);
34717+ INSTANCE_WR(ctx, 0x2168/4, 0x10700ff9);
34718+ INSTANCE_WR(ctx, 0x216c/4, 0x0436086c);
34719+ INSTANCE_WR(ctx, 0x2170/4, 0x000c001b);
34720+ INSTANCE_WR(ctx, 0x2178/4, 0x10700ff9);
34721+ INSTANCE_WR(ctx, 0x217c/4, 0x0436086c);
34722+ INSTANCE_WR(ctx, 0x2180/4, 0x000c001b);
34723+ INSTANCE_WR(ctx, 0x2188/4, 0x10700ff9);
34724+ INSTANCE_WR(ctx, 0x218c/4, 0x0436086c);
34725+ INSTANCE_WR(ctx, 0x2190/4, 0x000c001b);
34726+ INSTANCE_WR(ctx, 0x2198/4, 0x10700ff9);
34727+ INSTANCE_WR(ctx, 0x219c/4, 0x0436086c);
34728+ INSTANCE_WR(ctx, 0x21a0/4, 0x000c001b);
34729+ INSTANCE_WR(ctx, 0x21a8/4, 0x10700ff9);
34730+ INSTANCE_WR(ctx, 0x21ac/4, 0x0436086c);
34731+ INSTANCE_WR(ctx, 0x21b0/4, 0x000c001b);
34732+ INSTANCE_WR(ctx, 0x21b8/4, 0x10700ff9);
34733+ INSTANCE_WR(ctx, 0x21bc/4, 0x0436086c);
34734+ INSTANCE_WR(ctx, 0x21c0/4, 0x000c001b);
34735+ INSTANCE_WR(ctx, 0x21c8/4, 0x10700ff9);
34736+ INSTANCE_WR(ctx, 0x21cc/4, 0x0436086c);
34737+ INSTANCE_WR(ctx, 0x21d0/4, 0x000c001b);
34738+ INSTANCE_WR(ctx, 0x21d8/4, 0x10700ff9);
34739+ INSTANCE_WR(ctx, 0x21dc/4, 0x0436086c);
34740+ INSTANCE_WR(ctx, 0x21e0/4, 0x000c001b);
34741+ INSTANCE_WR(ctx, 0x21e8/4, 0x10700ff9);
34742+ INSTANCE_WR(ctx, 0x21ec/4, 0x0436086c);
34743+ INSTANCE_WR(ctx, 0x21f0/4, 0x000c001b);
34744+ INSTANCE_WR(ctx, 0x21f8/4, 0x10700ff9);
34745+ INSTANCE_WR(ctx, 0x21fc/4, 0x0436086c);
34746+ INSTANCE_WR(ctx, 0x2200/4, 0x000c001b);
34747+ INSTANCE_WR(ctx, 0x2208/4, 0x10700ff9);
34748+ INSTANCE_WR(ctx, 0x220c/4, 0x0436086c);
34749+ INSTANCE_WR(ctx, 0x2210/4, 0x000c001b);
34750+ INSTANCE_WR(ctx, 0x2218/4, 0x10700ff9);
34751+ INSTANCE_WR(ctx, 0x221c/4, 0x0436086c);
34752+ INSTANCE_WR(ctx, 0x2220/4, 0x000c001b);
34753+ INSTANCE_WR(ctx, 0x2228/4, 0x10700ff9);
34754+ INSTANCE_WR(ctx, 0x222c/4, 0x0436086c);
34755+ INSTANCE_WR(ctx, 0x2230/4, 0x000c001b);
34756+ INSTANCE_WR(ctx, 0x2238/4, 0x10700ff9);
34757+ INSTANCE_WR(ctx, 0x223c/4, 0x0436086c);
34758+ INSTANCE_WR(ctx, 0x2240/4, 0x000c001b);
34759+ INSTANCE_WR(ctx, 0x2248/4, 0x10700ff9);
34760+ INSTANCE_WR(ctx, 0x224c/4, 0x0436086c);
34761+ INSTANCE_WR(ctx, 0x2250/4, 0x000c001b);
34762+ INSTANCE_WR(ctx, 0x2258/4, 0x10700ff9);
34763+ INSTANCE_WR(ctx, 0x225c/4, 0x0436086c);
34764+ INSTANCE_WR(ctx, 0x2260/4, 0x000c001b);
34765+ INSTANCE_WR(ctx, 0x2268/4, 0x10700ff9);
34766+ INSTANCE_WR(ctx, 0x226c/4, 0x0436086c);
34767+ INSTANCE_WR(ctx, 0x2270/4, 0x000c001b);
34768+ INSTANCE_WR(ctx, 0x2278/4, 0x10700ff9);
34769+ INSTANCE_WR(ctx, 0x227c/4, 0x0436086c);
34770+ INSTANCE_WR(ctx, 0x2280/4, 0x000c001b);
34771+ INSTANCE_WR(ctx, 0x2288/4, 0x10700ff9);
34772+ INSTANCE_WR(ctx, 0x228c/4, 0x0436086c);
34773+ INSTANCE_WR(ctx, 0x2290/4, 0x000c001b);
34774+ INSTANCE_WR(ctx, 0x2298/4, 0x10700ff9);
34775+ INSTANCE_WR(ctx, 0x229c/4, 0x0436086c);
34776+ INSTANCE_WR(ctx, 0x22a0/4, 0x000c001b);
34777+ INSTANCE_WR(ctx, 0x22a8/4, 0x10700ff9);
34778+ INSTANCE_WR(ctx, 0x22ac/4, 0x0436086c);
34779+ INSTANCE_WR(ctx, 0x22b0/4, 0x000c001b);
34780+ INSTANCE_WR(ctx, 0x22b8/4, 0x10700ff9);
34781+ INSTANCE_WR(ctx, 0x22bc/4, 0x0436086c);
34782+ INSTANCE_WR(ctx, 0x22c0/4, 0x000c001b);
34783+ INSTANCE_WR(ctx, 0x22c8/4, 0x10700ff9);
34784+ INSTANCE_WR(ctx, 0x22cc/4, 0x0436086c);
34785+ INSTANCE_WR(ctx, 0x22d0/4, 0x000c001b);
34786+ INSTANCE_WR(ctx, 0x22d8/4, 0x10700ff9);
34787+ INSTANCE_WR(ctx, 0x22dc/4, 0x0436086c);
34788+ INSTANCE_WR(ctx, 0x22e0/4, 0x000c001b);
34789+ INSTANCE_WR(ctx, 0x22e8/4, 0x10700ff9);
34790+ INSTANCE_WR(ctx, 0x22ec/4, 0x0436086c);
34791+ INSTANCE_WR(ctx, 0x22f0/4, 0x000c001b);
34792+ INSTANCE_WR(ctx, 0x22f8/4, 0x10700ff9);
34793+ INSTANCE_WR(ctx, 0x22fc/4, 0x0436086c);
34794+ INSTANCE_WR(ctx, 0x2300/4, 0x000c001b);
34795+ INSTANCE_WR(ctx, 0x2308/4, 0x10700ff9);
34796+ INSTANCE_WR(ctx, 0x230c/4, 0x0436086c);
34797+ INSTANCE_WR(ctx, 0x2310/4, 0x000c001b);
34798+ INSTANCE_WR(ctx, 0x2318/4, 0x10700ff9);
34799+ INSTANCE_WR(ctx, 0x231c/4, 0x0436086c);
34800+ INSTANCE_WR(ctx, 0x2320/4, 0x000c001b);
34801+ INSTANCE_WR(ctx, 0x2328/4, 0x10700ff9);
34802+ INSTANCE_WR(ctx, 0x232c/4, 0x0436086c);
34803+ INSTANCE_WR(ctx, 0x2330/4, 0x000c001b);
34804+ INSTANCE_WR(ctx, 0x2338/4, 0x10700ff9);
34805+ INSTANCE_WR(ctx, 0x233c/4, 0x0436086c);
34806+ INSTANCE_WR(ctx, 0x2340/4, 0x000c001b);
34807+ INSTANCE_WR(ctx, 0x2348/4, 0x10700ff9);
34808+ INSTANCE_WR(ctx, 0x234c/4, 0x0436086c);
34809+ INSTANCE_WR(ctx, 0x2350/4, 0x000c001b);
34810+ INSTANCE_WR(ctx, 0x2358/4, 0x10700ff9);
34811+ INSTANCE_WR(ctx, 0x235c/4, 0x0436086c);
34812+ INSTANCE_WR(ctx, 0x2360/4, 0x000c001b);
34813+ INSTANCE_WR(ctx, 0x2368/4, 0x10700ff9);
34814+ INSTANCE_WR(ctx, 0x236c/4, 0x0436086c);
34815+ INSTANCE_WR(ctx, 0x2370/4, 0x000c001b);
34816+ INSTANCE_WR(ctx, 0x2378/4, 0x10700ff9);
34817+ INSTANCE_WR(ctx, 0x237c/4, 0x0436086c);
34818+ INSTANCE_WR(ctx, 0x2380/4, 0x000c001b);
34819+ INSTANCE_WR(ctx, 0x2388/4, 0x10700ff9);
34820+ INSTANCE_WR(ctx, 0x238c/4, 0x0436086c);
34821+ INSTANCE_WR(ctx, 0x2390/4, 0x000c001b);
34822+ INSTANCE_WR(ctx, 0x2398/4, 0x10700ff9);
34823+ INSTANCE_WR(ctx, 0x239c/4, 0x0436086c);
34824+ INSTANCE_WR(ctx, 0x23a0/4, 0x000c001b);
34825+ INSTANCE_WR(ctx, 0x23a8/4, 0x10700ff9);
34826+ INSTANCE_WR(ctx, 0x23ac/4, 0x0436086c);
34827+ INSTANCE_WR(ctx, 0x23b0/4, 0x000c001b);
34828+ INSTANCE_WR(ctx, 0x23b8/4, 0x10700ff9);
34829+ INSTANCE_WR(ctx, 0x23bc/4, 0x0436086c);
34830+ INSTANCE_WR(ctx, 0x23c0/4, 0x000c001b);
34831+ INSTANCE_WR(ctx, 0x23c8/4, 0x10700ff9);
34832+ INSTANCE_WR(ctx, 0x23cc/4, 0x0436086c);
34833+ INSTANCE_WR(ctx, 0x23d0/4, 0x000c001b);
34834+ INSTANCE_WR(ctx, 0x23d8/4, 0x10700ff9);
34835+ INSTANCE_WR(ctx, 0x23dc/4, 0x0436086c);
34836+ INSTANCE_WR(ctx, 0x23e0/4, 0x000c001b);
34837+ INSTANCE_WR(ctx, 0x23e8/4, 0x10700ff9);
34838+ INSTANCE_WR(ctx, 0x23ec/4, 0x0436086c);
34839+ INSTANCE_WR(ctx, 0x23f0/4, 0x000c001b);
34840+ INSTANCE_WR(ctx, 0x23f8/4, 0x10700ff9);
34841+ INSTANCE_WR(ctx, 0x23fc/4, 0x0436086c);
34842+ INSTANCE_WR(ctx, 0x2400/4, 0x000c001b);
34843+ INSTANCE_WR(ctx, 0x2408/4, 0x10700ff9);
34844+ INSTANCE_WR(ctx, 0x240c/4, 0x0436086c);
34845+ INSTANCE_WR(ctx, 0x2410/4, 0x000c001b);
34846+ INSTANCE_WR(ctx, 0x2418/4, 0x10700ff9);
34847+ INSTANCE_WR(ctx, 0x241c/4, 0x0436086c);
34848+ INSTANCE_WR(ctx, 0x2420/4, 0x000c001b);
34849+ INSTANCE_WR(ctx, 0x2428/4, 0x10700ff9);
34850+ INSTANCE_WR(ctx, 0x242c/4, 0x0436086c);
34851+ INSTANCE_WR(ctx, 0x2430/4, 0x000c001b);
34852+ INSTANCE_WR(ctx, 0x2438/4, 0x10700ff9);
34853+ INSTANCE_WR(ctx, 0x243c/4, 0x0436086c);
34854+ INSTANCE_WR(ctx, 0x2440/4, 0x000c001b);
34855+ INSTANCE_WR(ctx, 0x2448/4, 0x10700ff9);
34856+ INSTANCE_WR(ctx, 0x244c/4, 0x0436086c);
34857+ INSTANCE_WR(ctx, 0x2450/4, 0x000c001b);
34858+ INSTANCE_WR(ctx, 0x2458/4, 0x10700ff9);
34859+ INSTANCE_WR(ctx, 0x245c/4, 0x0436086c);
34860+ INSTANCE_WR(ctx, 0x2460/4, 0x000c001b);
34861+ INSTANCE_WR(ctx, 0x2468/4, 0x10700ff9);
34862+ INSTANCE_WR(ctx, 0x246c/4, 0x0436086c);
34863+ INSTANCE_WR(ctx, 0x2470/4, 0x000c001b);
34864+ INSTANCE_WR(ctx, 0x2478/4, 0x10700ff9);
34865+ INSTANCE_WR(ctx, 0x247c/4, 0x0436086c);
34866+ INSTANCE_WR(ctx, 0x2480/4, 0x000c001b);
34867+ INSTANCE_WR(ctx, 0x2488/4, 0x10700ff9);
34868+ INSTANCE_WR(ctx, 0x248c/4, 0x0436086c);
34869+ INSTANCE_WR(ctx, 0x2490/4, 0x000c001b);
34870+ INSTANCE_WR(ctx, 0x2498/4, 0x10700ff9);
34871+ INSTANCE_WR(ctx, 0x249c/4, 0x0436086c);
34872+ INSTANCE_WR(ctx, 0x24a0/4, 0x000c001b);
34873+ INSTANCE_WR(ctx, 0x24a8/4, 0x10700ff9);
34874+ INSTANCE_WR(ctx, 0x24ac/4, 0x0436086c);
34875+ INSTANCE_WR(ctx, 0x24b0/4, 0x000c001b);
34876+ INSTANCE_WR(ctx, 0x24b8/4, 0x10700ff9);
34877+ INSTANCE_WR(ctx, 0x24bc/4, 0x0436086c);
34878+ INSTANCE_WR(ctx, 0x24c0/4, 0x000c001b);
34879+ INSTANCE_WR(ctx, 0x24c8/4, 0x10700ff9);
34880+ INSTANCE_WR(ctx, 0x24cc/4, 0x0436086c);
34881+ INSTANCE_WR(ctx, 0x24d0/4, 0x000c001b);
34882+ INSTANCE_WR(ctx, 0x24d8/4, 0x10700ff9);
34883+ INSTANCE_WR(ctx, 0x24dc/4, 0x0436086c);
34884+ INSTANCE_WR(ctx, 0x24e0/4, 0x000c001b);
34885+ INSTANCE_WR(ctx, 0x24e8/4, 0x10700ff9);
34886+ INSTANCE_WR(ctx, 0x24ec/4, 0x0436086c);
34887+ INSTANCE_WR(ctx, 0x24f0/4, 0x000c001b);
34888+ INSTANCE_WR(ctx, 0x24f8/4, 0x10700ff9);
34889+ INSTANCE_WR(ctx, 0x24fc/4, 0x0436086c);
34890+ INSTANCE_WR(ctx, 0x2500/4, 0x000c001b);
34891+ INSTANCE_WR(ctx, 0x2508/4, 0x10700ff9);
34892+ INSTANCE_WR(ctx, 0x250c/4, 0x0436086c);
34893+ INSTANCE_WR(ctx, 0x2510/4, 0x000c001b);
34894+ INSTANCE_WR(ctx, 0x2518/4, 0x10700ff9);
34895+ INSTANCE_WR(ctx, 0x251c/4, 0x0436086c);
34896+ INSTANCE_WR(ctx, 0x2520/4, 0x000c001b);
34897+ INSTANCE_WR(ctx, 0x2528/4, 0x10700ff9);
34898+ INSTANCE_WR(ctx, 0x252c/4, 0x0436086c);
34899+ INSTANCE_WR(ctx, 0x2530/4, 0x000c001b);
34900+ INSTANCE_WR(ctx, 0x2538/4, 0x10700ff9);
34901+ INSTANCE_WR(ctx, 0x253c/4, 0x0436086c);
34902+ INSTANCE_WR(ctx, 0x2540/4, 0x000c001b);
34903+ INSTANCE_WR(ctx, 0x2548/4, 0x10700ff9);
34904+ INSTANCE_WR(ctx, 0x254c/4, 0x0436086c);
34905+ INSTANCE_WR(ctx, 0x2550/4, 0x000c001b);
34906+ INSTANCE_WR(ctx, 0x2558/4, 0x10700ff9);
34907+ INSTANCE_WR(ctx, 0x255c/4, 0x0436086c);
34908+ INSTANCE_WR(ctx, 0x2560/4, 0x000c001b);
34909+ INSTANCE_WR(ctx, 0x2568/4, 0x10700ff9);
34910+ INSTANCE_WR(ctx, 0x256c/4, 0x0436086c);
34911+ INSTANCE_WR(ctx, 0x2570/4, 0x000c001b);
34912+ INSTANCE_WR(ctx, 0x2578/4, 0x10700ff9);
34913+ INSTANCE_WR(ctx, 0x257c/4, 0x0436086c);
34914+ INSTANCE_WR(ctx, 0x2580/4, 0x000c001b);
34915+ INSTANCE_WR(ctx, 0x2588/4, 0x10700ff9);
34916+ INSTANCE_WR(ctx, 0x258c/4, 0x0436086c);
34917+ INSTANCE_WR(ctx, 0x2590/4, 0x000c001b);
34918+ INSTANCE_WR(ctx, 0x2598/4, 0x10700ff9);
34919+ INSTANCE_WR(ctx, 0x259c/4, 0x0436086c);
34920+ INSTANCE_WR(ctx, 0x25a0/4, 0x000c001b);
34921+ INSTANCE_WR(ctx, 0x25a8/4, 0x10700ff9);
34922+ INSTANCE_WR(ctx, 0x25ac/4, 0x0436086c);
34923+ INSTANCE_WR(ctx, 0x25b0/4, 0x000c001b);
34924+ INSTANCE_WR(ctx, 0x25b8/4, 0x10700ff9);
34925+ INSTANCE_WR(ctx, 0x25bc/4, 0x0436086c);
34926+ INSTANCE_WR(ctx, 0x25c0/4, 0x000c001b);
34927+ INSTANCE_WR(ctx, 0x25c8/4, 0x10700ff9);
34928+ INSTANCE_WR(ctx, 0x25cc/4, 0x0436086c);
34929+ INSTANCE_WR(ctx, 0x25d0/4, 0x000c001b);
34930+ INSTANCE_WR(ctx, 0x25d8/4, 0x10700ff9);
34931+ INSTANCE_WR(ctx, 0x25dc/4, 0x0436086c);
34932+ INSTANCE_WR(ctx, 0x25e0/4, 0x000c001b);
34933+ INSTANCE_WR(ctx, 0x25e8/4, 0x10700ff9);
34934+ INSTANCE_WR(ctx, 0x25ec/4, 0x0436086c);
34935+ INSTANCE_WR(ctx, 0x25f0/4, 0x000c001b);
34936+ INSTANCE_WR(ctx, 0x25f8/4, 0x10700ff9);
34937+ INSTANCE_WR(ctx, 0x25fc/4, 0x0436086c);
34938+ INSTANCE_WR(ctx, 0x2600/4, 0x000c001b);
34939+ INSTANCE_WR(ctx, 0x2608/4, 0x10700ff9);
34940+ INSTANCE_WR(ctx, 0x260c/4, 0x0436086c);
34941+ INSTANCE_WR(ctx, 0x2610/4, 0x000c001b);
34942+ INSTANCE_WR(ctx, 0x2618/4, 0x10700ff9);
34943+ INSTANCE_WR(ctx, 0x261c/4, 0x0436086c);
34944+ INSTANCE_WR(ctx, 0x2620/4, 0x000c001b);
34945+ INSTANCE_WR(ctx, 0x2628/4, 0x10700ff9);
34946+ INSTANCE_WR(ctx, 0x262c/4, 0x0436086c);
34947+ INSTANCE_WR(ctx, 0x2630/4, 0x000c001b);
34948+ INSTANCE_WR(ctx, 0x2638/4, 0x10700ff9);
34949+ INSTANCE_WR(ctx, 0x263c/4, 0x0436086c);
34950+ INSTANCE_WR(ctx, 0x2640/4, 0x000c001b);
34951+ INSTANCE_WR(ctx, 0x2648/4, 0x10700ff9);
34952+ INSTANCE_WR(ctx, 0x264c/4, 0x0436086c);
34953+ INSTANCE_WR(ctx, 0x2650/4, 0x000c001b);
34954+ INSTANCE_WR(ctx, 0x2658/4, 0x10700ff9);
34955+ INSTANCE_WR(ctx, 0x265c/4, 0x0436086c);
34956+ INSTANCE_WR(ctx, 0x2660/4, 0x000c001b);
34957+ INSTANCE_WR(ctx, 0x2668/4, 0x10700ff9);
34958+ INSTANCE_WR(ctx, 0x266c/4, 0x0436086c);
34959+ INSTANCE_WR(ctx, 0x2670/4, 0x000c001b);
34960+ INSTANCE_WR(ctx, 0x2678/4, 0x10700ff9);
34961+ INSTANCE_WR(ctx, 0x267c/4, 0x0436086c);
34962+ INSTANCE_WR(ctx, 0x2680/4, 0x000c001b);
34963+ INSTANCE_WR(ctx, 0x2688/4, 0x10700ff9);
34964+ INSTANCE_WR(ctx, 0x268c/4, 0x0436086c);
34965+ INSTANCE_WR(ctx, 0x2690/4, 0x000c001b);
34966+ INSTANCE_WR(ctx, 0x2698/4, 0x10700ff9);
34967+ INSTANCE_WR(ctx, 0x269c/4, 0x0436086c);
34968+ INSTANCE_WR(ctx, 0x26a0/4, 0x000c001b);
34969+ INSTANCE_WR(ctx, 0x26a8/4, 0x10700ff9);
34970+ INSTANCE_WR(ctx, 0x26ac/4, 0x0436086c);
34971+ INSTANCE_WR(ctx, 0x26b0/4, 0x000c001b);
34972+ INSTANCE_WR(ctx, 0x26b8/4, 0x10700ff9);
34973+ INSTANCE_WR(ctx, 0x26bc/4, 0x0436086c);
34974+ INSTANCE_WR(ctx, 0x26c0/4, 0x000c001b);
34975+ INSTANCE_WR(ctx, 0x26c8/4, 0x10700ff9);
34976+ INSTANCE_WR(ctx, 0x26cc/4, 0x0436086c);
34977+ INSTANCE_WR(ctx, 0x26d0/4, 0x000c001b);
34978+ INSTANCE_WR(ctx, 0x26d8/4, 0x10700ff9);
34979+ INSTANCE_WR(ctx, 0x26dc/4, 0x0436086c);
34980+ INSTANCE_WR(ctx, 0x26e0/4, 0x000c001b);
34981+ INSTANCE_WR(ctx, 0x26e8/4, 0x10700ff9);
34982+ INSTANCE_WR(ctx, 0x26ec/4, 0x0436086c);
34983+ INSTANCE_WR(ctx, 0x26f0/4, 0x000c001b);
34984+ INSTANCE_WR(ctx, 0x26f8/4, 0x10700ff9);
34985+ INSTANCE_WR(ctx, 0x26fc/4, 0x0436086c);
34986+ INSTANCE_WR(ctx, 0x2700/4, 0x000c001b);
34987+ INSTANCE_WR(ctx, 0x2708/4, 0x10700ff9);
34988+ INSTANCE_WR(ctx, 0x270c/4, 0x0436086c);
34989+ INSTANCE_WR(ctx, 0x2710/4, 0x000c001b);
34990+ INSTANCE_WR(ctx, 0x2718/4, 0x10700ff9);
34991+ INSTANCE_WR(ctx, 0x271c/4, 0x0436086c);
34992+ INSTANCE_WR(ctx, 0x2720/4, 0x000c001b);
34993+ INSTANCE_WR(ctx, 0x2728/4, 0x10700ff9);
34994+ INSTANCE_WR(ctx, 0x272c/4, 0x0436086c);
34995+ INSTANCE_WR(ctx, 0x2730/4, 0x000c001b);
34996+ INSTANCE_WR(ctx, 0x2738/4, 0x10700ff9);
34997+ INSTANCE_WR(ctx, 0x273c/4, 0x0436086c);
34998+ INSTANCE_WR(ctx, 0x2740/4, 0x000c001b);
34999+ INSTANCE_WR(ctx, 0x2748/4, 0x10700ff9);
35000+ INSTANCE_WR(ctx, 0x274c/4, 0x0436086c);
35001+ INSTANCE_WR(ctx, 0x2750/4, 0x000c001b);
35002+ INSTANCE_WR(ctx, 0x2758/4, 0x10700ff9);
35003+ INSTANCE_WR(ctx, 0x275c/4, 0x0436086c);
35004+ INSTANCE_WR(ctx, 0x2760/4, 0x000c001b);
35005+ INSTANCE_WR(ctx, 0x2768/4, 0x10700ff9);
35006+ INSTANCE_WR(ctx, 0x276c/4, 0x0436086c);
35007+ INSTANCE_WR(ctx, 0x2770/4, 0x000c001b);
35008+ INSTANCE_WR(ctx, 0x2778/4, 0x10700ff9);
35009+ INSTANCE_WR(ctx, 0x277c/4, 0x0436086c);
35010+ INSTANCE_WR(ctx, 0x2780/4, 0x000c001b);
35011+ INSTANCE_WR(ctx, 0x2788/4, 0x10700ff9);
35012+ INSTANCE_WR(ctx, 0x278c/4, 0x0436086c);
35013+ INSTANCE_WR(ctx, 0x2790/4, 0x000c001b);
35014+ INSTANCE_WR(ctx, 0x2798/4, 0x10700ff9);
35015+ INSTANCE_WR(ctx, 0x279c/4, 0x0436086c);
35016+ INSTANCE_WR(ctx, 0x27a0/4, 0x000c001b);
35017+ INSTANCE_WR(ctx, 0x27a8/4, 0x10700ff9);
35018+ INSTANCE_WR(ctx, 0x27ac/4, 0x0436086c);
35019+ INSTANCE_WR(ctx, 0x27b0/4, 0x000c001b);
35020+ INSTANCE_WR(ctx, 0x27b8/4, 0x10700ff9);
35021+ INSTANCE_WR(ctx, 0x27bc/4, 0x0436086c);
35022+ INSTANCE_WR(ctx, 0x27c0/4, 0x000c001b);
35023+ INSTANCE_WR(ctx, 0x27c8/4, 0x10700ff9);
35024+ INSTANCE_WR(ctx, 0x27cc/4, 0x0436086c);
35025+ INSTANCE_WR(ctx, 0x27d0/4, 0x000c001b);
35026+ INSTANCE_WR(ctx, 0x27d8/4, 0x10700ff9);
35027+ INSTANCE_WR(ctx, 0x27dc/4, 0x0436086c);
35028+ INSTANCE_WR(ctx, 0x27e0/4, 0x000c001b);
35029+ INSTANCE_WR(ctx, 0x27e8/4, 0x10700ff9);
35030+ INSTANCE_WR(ctx, 0x27ec/4, 0x0436086c);
35031+ INSTANCE_WR(ctx, 0x27f0/4, 0x000c001b);
35032+ INSTANCE_WR(ctx, 0x27f8/4, 0x10700ff9);
35033+ INSTANCE_WR(ctx, 0x27fc/4, 0x0436086c);
35034+ INSTANCE_WR(ctx, 0x2800/4, 0x000c001b);
35035+ INSTANCE_WR(ctx, 0x2808/4, 0x10700ff9);
35036+ INSTANCE_WR(ctx, 0x280c/4, 0x0436086c);
35037+ INSTANCE_WR(ctx, 0x2810/4, 0x000c001b);
35038+ INSTANCE_WR(ctx, 0x2818/4, 0x10700ff9);
35039+ INSTANCE_WR(ctx, 0x281c/4, 0x0436086c);
35040+ INSTANCE_WR(ctx, 0x2820/4, 0x000c001b);
35041+ INSTANCE_WR(ctx, 0x2828/4, 0x10700ff9);
35042+ INSTANCE_WR(ctx, 0x282c/4, 0x0436086c);
35043+ INSTANCE_WR(ctx, 0x2830/4, 0x000c001b);
35044+ INSTANCE_WR(ctx, 0x2838/4, 0x10700ff9);
35045+ INSTANCE_WR(ctx, 0x283c/4, 0x0436086c);
35046+ INSTANCE_WR(ctx, 0x2840/4, 0x000c001b);
35047+ INSTANCE_WR(ctx, 0x2848/4, 0x10700ff9);
35048+ INSTANCE_WR(ctx, 0x284c/4, 0x0436086c);
35049+ INSTANCE_WR(ctx, 0x2850/4, 0x000c001b);
35050+ INSTANCE_WR(ctx, 0x2858/4, 0x10700ff9);
35051+ INSTANCE_WR(ctx, 0x285c/4, 0x0436086c);
35052+ INSTANCE_WR(ctx, 0x2860/4, 0x000c001b);
35053+ INSTANCE_WR(ctx, 0x2868/4, 0x10700ff9);
35054+ INSTANCE_WR(ctx, 0x286c/4, 0x0436086c);
35055+ INSTANCE_WR(ctx, 0x2870/4, 0x000c001b);
35056+ INSTANCE_WR(ctx, 0x2878/4, 0x10700ff9);
35057+ INSTANCE_WR(ctx, 0x287c/4, 0x0436086c);
35058+ INSTANCE_WR(ctx, 0x2880/4, 0x000c001b);
35059+ INSTANCE_WR(ctx, 0x2888/4, 0x10700ff9);
35060+ INSTANCE_WR(ctx, 0x288c/4, 0x0436086c);
35061+ INSTANCE_WR(ctx, 0x2890/4, 0x000c001b);
35062+ INSTANCE_WR(ctx, 0x2898/4, 0x10700ff9);
35063+ INSTANCE_WR(ctx, 0x289c/4, 0x0436086c);
35064+ INSTANCE_WR(ctx, 0x28a0/4, 0x000c001b);
35065+ INSTANCE_WR(ctx, 0x28a8/4, 0x10700ff9);
35066+ INSTANCE_WR(ctx, 0x28ac/4, 0x0436086c);
35067+ INSTANCE_WR(ctx, 0x28b0/4, 0x000c001b);
35068+ INSTANCE_WR(ctx, 0x28b8/4, 0x10700ff9);
35069+ INSTANCE_WR(ctx, 0x28bc/4, 0x0436086c);
35070+ INSTANCE_WR(ctx, 0x28c0/4, 0x000c001b);
35071+ INSTANCE_WR(ctx, 0x28c8/4, 0x10700ff9);
35072+ INSTANCE_WR(ctx, 0x28cc/4, 0x0436086c);
35073+ INSTANCE_WR(ctx, 0x28d0/4, 0x000c001b);
35074+ INSTANCE_WR(ctx, 0x28d8/4, 0x10700ff9);
35075+ INSTANCE_WR(ctx, 0x28dc/4, 0x0436086c);
35076+ INSTANCE_WR(ctx, 0x28e0/4, 0x000c001b);
35077+ INSTANCE_WR(ctx, 0x28e8/4, 0x10700ff9);
35078+ INSTANCE_WR(ctx, 0x28ec/4, 0x0436086c);
35079+ INSTANCE_WR(ctx, 0x28f0/4, 0x000c001b);
35080+ INSTANCE_WR(ctx, 0x28f8/4, 0x10700ff9);
35081+ INSTANCE_WR(ctx, 0x28fc/4, 0x0436086c);
35082+ INSTANCE_WR(ctx, 0x2900/4, 0x000c001b);
35083+ INSTANCE_WR(ctx, 0x2908/4, 0x10700ff9);
35084+ INSTANCE_WR(ctx, 0x290c/4, 0x0436086c);
35085+ INSTANCE_WR(ctx, 0x2910/4, 0x000c001b);
35086+ INSTANCE_WR(ctx, 0x2918/4, 0x10700ff9);
35087+ INSTANCE_WR(ctx, 0x291c/4, 0x0436086c);
35088+ INSTANCE_WR(ctx, 0x2920/4, 0x000c001b);
35089+ INSTANCE_WR(ctx, 0x2928/4, 0x10700ff9);
35090+ INSTANCE_WR(ctx, 0x292c/4, 0x0436086c);
35091+ INSTANCE_WR(ctx, 0x2930/4, 0x000c001b);
35092+ INSTANCE_WR(ctx, 0x2938/4, 0x10700ff9);
35093+ INSTANCE_WR(ctx, 0x293c/4, 0x0436086c);
35094+ INSTANCE_WR(ctx, 0x2940/4, 0x000c001b);
35095+ INSTANCE_WR(ctx, 0x2948/4, 0x10700ff9);
35096+ INSTANCE_WR(ctx, 0x294c/4, 0x0436086c);
35097+ INSTANCE_WR(ctx, 0x2950/4, 0x000c001b);
35098+ INSTANCE_WR(ctx, 0x2958/4, 0x10700ff9);
35099+ INSTANCE_WR(ctx, 0x295c/4, 0x0436086c);
35100+ INSTANCE_WR(ctx, 0x2960/4, 0x000c001b);
35101+ INSTANCE_WR(ctx, 0x2968/4, 0x10700ff9);
35102+ INSTANCE_WR(ctx, 0x296c/4, 0x0436086c);
35103+ INSTANCE_WR(ctx, 0x2970/4, 0x000c001b);
35104+ INSTANCE_WR(ctx, 0x2978/4, 0x10700ff9);
35105+ INSTANCE_WR(ctx, 0x297c/4, 0x0436086c);
35106+ INSTANCE_WR(ctx, 0x2980/4, 0x000c001b);
35107+ INSTANCE_WR(ctx, 0x2988/4, 0x10700ff9);
35108+ INSTANCE_WR(ctx, 0x298c/4, 0x0436086c);
35109+ INSTANCE_WR(ctx, 0x2990/4, 0x000c001b);
35110+ INSTANCE_WR(ctx, 0x2998/4, 0x10700ff9);
35111+ INSTANCE_WR(ctx, 0x299c/4, 0x0436086c);
35112+ INSTANCE_WR(ctx, 0x29a0/4, 0x000c001b);
35113+ INSTANCE_WR(ctx, 0x29a8/4, 0x10700ff9);
35114+ INSTANCE_WR(ctx, 0x29ac/4, 0x0436086c);
35115+ INSTANCE_WR(ctx, 0x29b0/4, 0x000c001b);
35116+ INSTANCE_WR(ctx, 0x29b8/4, 0x10700ff9);
35117+ INSTANCE_WR(ctx, 0x29bc/4, 0x0436086c);
35118+ INSTANCE_WR(ctx, 0x29c0/4, 0x000c001b);
35119+ INSTANCE_WR(ctx, 0x29c8/4, 0x10700ff9);
35120+ INSTANCE_WR(ctx, 0x29cc/4, 0x0436086c);
35121+ INSTANCE_WR(ctx, 0x29d0/4, 0x000c001b);
35122+ INSTANCE_WR(ctx, 0x29d8/4, 0x10700ff9);
35123+ INSTANCE_WR(ctx, 0x29dc/4, 0x0436086c);
35124+ INSTANCE_WR(ctx, 0x29e0/4, 0x000c001b);
35125+ INSTANCE_WR(ctx, 0x29e8/4, 0x10700ff9);
35126+ INSTANCE_WR(ctx, 0x29ec/4, 0x0436086c);
35127+ INSTANCE_WR(ctx, 0x29f0/4, 0x000c001b);
35128+ INSTANCE_WR(ctx, 0x29f8/4, 0x10700ff9);
35129+ INSTANCE_WR(ctx, 0x29fc/4, 0x0436086c);
35130+ INSTANCE_WR(ctx, 0x2a00/4, 0x000c001b);
35131+ INSTANCE_WR(ctx, 0x2a08/4, 0x10700ff9);
35132+ INSTANCE_WR(ctx, 0x2a0c/4, 0x0436086c);
35133+ INSTANCE_WR(ctx, 0x2a10/4, 0x000c001b);
35134+ INSTANCE_WR(ctx, 0x2a18/4, 0x10700ff9);
35135+ INSTANCE_WR(ctx, 0x2a1c/4, 0x0436086c);
35136+ INSTANCE_WR(ctx, 0x2a20/4, 0x000c001b);
35137+ INSTANCE_WR(ctx, 0x2a28/4, 0x10700ff9);
35138+ INSTANCE_WR(ctx, 0x2a2c/4, 0x0436086c);
35139+ INSTANCE_WR(ctx, 0x2a30/4, 0x000c001b);
35140+ INSTANCE_WR(ctx, 0x2a38/4, 0x10700ff9);
35141+ INSTANCE_WR(ctx, 0x2a3c/4, 0x0436086c);
35142+ INSTANCE_WR(ctx, 0x2a40/4, 0x000c001b);
35143+ INSTANCE_WR(ctx, 0x2a48/4, 0x10700ff9);
35144+ INSTANCE_WR(ctx, 0x2a4c/4, 0x0436086c);
35145+ INSTANCE_WR(ctx, 0x2a50/4, 0x000c001b);
35146+ INSTANCE_WR(ctx, 0x2a58/4, 0x10700ff9);
35147+ INSTANCE_WR(ctx, 0x2a5c/4, 0x0436086c);
35148+ INSTANCE_WR(ctx, 0x2a60/4, 0x000c001b);
35149+ INSTANCE_WR(ctx, 0x2a68/4, 0x10700ff9);
35150+ INSTANCE_WR(ctx, 0x2a6c/4, 0x0436086c);
35151+ INSTANCE_WR(ctx, 0x2a70/4, 0x000c001b);
35152+ INSTANCE_WR(ctx, 0x2a78/4, 0x10700ff9);
35153+ INSTANCE_WR(ctx, 0x2a7c/4, 0x0436086c);
35154+ INSTANCE_WR(ctx, 0x2a80/4, 0x000c001b);
35155+ INSTANCE_WR(ctx, 0x2a88/4, 0x10700ff9);
35156+ INSTANCE_WR(ctx, 0x2a8c/4, 0x0436086c);
35157+ INSTANCE_WR(ctx, 0x2a90/4, 0x000c001b);
35158+ INSTANCE_WR(ctx, 0x2a98/4, 0x10700ff9);
35159+ INSTANCE_WR(ctx, 0x2a9c/4, 0x0436086c);
35160+ INSTANCE_WR(ctx, 0x2aa0/4, 0x000c001b);
35161+ INSTANCE_WR(ctx, 0x2aa8/4, 0x10700ff9);
35162+ INSTANCE_WR(ctx, 0x2aac/4, 0x0436086c);
35163+ INSTANCE_WR(ctx, 0x2ab0/4, 0x000c001b);
35164+ INSTANCE_WR(ctx, 0x2ab8/4, 0x10700ff9);
35165+ INSTANCE_WR(ctx, 0x2abc/4, 0x0436086c);
35166+ INSTANCE_WR(ctx, 0x2ac0/4, 0x000c001b);
35167+ INSTANCE_WR(ctx, 0x2ac8/4, 0x10700ff9);
35168+ INSTANCE_WR(ctx, 0x2acc/4, 0x0436086c);
35169+ INSTANCE_WR(ctx, 0x2ad0/4, 0x000c001b);
35170+ INSTANCE_WR(ctx, 0x2ad8/4, 0x10700ff9);
35171+ INSTANCE_WR(ctx, 0x2adc/4, 0x0436086c);
35172+ INSTANCE_WR(ctx, 0x2ae0/4, 0x000c001b);
35173+ INSTANCE_WR(ctx, 0x2ae8/4, 0x10700ff9);
35174+ INSTANCE_WR(ctx, 0x2aec/4, 0x0436086c);
35175+ INSTANCE_WR(ctx, 0x2af0/4, 0x000c001b);
35176+ INSTANCE_WR(ctx, 0x2af8/4, 0x10700ff9);
35177+ INSTANCE_WR(ctx, 0x2afc/4, 0x0436086c);
35178+ INSTANCE_WR(ctx, 0x2b00/4, 0x000c001b);
35179+ INSTANCE_WR(ctx, 0x2b08/4, 0x10700ff9);
35180+ INSTANCE_WR(ctx, 0x2b0c/4, 0x0436086c);
35181+ INSTANCE_WR(ctx, 0x2b10/4, 0x000c001b);
35182+ INSTANCE_WR(ctx, 0x2b18/4, 0x10700ff9);
35183+ INSTANCE_WR(ctx, 0x2b1c/4, 0x0436086c);
35184+ INSTANCE_WR(ctx, 0x2b20/4, 0x000c001b);
35185+ INSTANCE_WR(ctx, 0x2b28/4, 0x10700ff9);
35186+ INSTANCE_WR(ctx, 0x2b2c/4, 0x0436086c);
35187+ INSTANCE_WR(ctx, 0x2b30/4, 0x000c001b);
35188+ INSTANCE_WR(ctx, 0x2b38/4, 0x10700ff9);
35189+ INSTANCE_WR(ctx, 0x2b3c/4, 0x0436086c);
35190+ INSTANCE_WR(ctx, 0x2b40/4, 0x000c001b);
35191+ INSTANCE_WR(ctx, 0x2b48/4, 0x10700ff9);
35192+ INSTANCE_WR(ctx, 0x2b4c/4, 0x0436086c);
35193+ INSTANCE_WR(ctx, 0x2b50/4, 0x000c001b);
35194+ INSTANCE_WR(ctx, 0x2b58/4, 0x10700ff9);
35195+ INSTANCE_WR(ctx, 0x2b5c/4, 0x0436086c);
35196+ INSTANCE_WR(ctx, 0x2b60/4, 0x000c001b);
35197+ INSTANCE_WR(ctx, 0x2b68/4, 0x10700ff9);
35198+ INSTANCE_WR(ctx, 0x2b6c/4, 0x0436086c);
35199+ INSTANCE_WR(ctx, 0x2b70/4, 0x000c001b);
35200+ INSTANCE_WR(ctx, 0x2b78/4, 0x10700ff9);
35201+ INSTANCE_WR(ctx, 0x2b7c/4, 0x0436086c);
35202+ INSTANCE_WR(ctx, 0x2b80/4, 0x000c001b);
35203+ INSTANCE_WR(ctx, 0x2b88/4, 0x10700ff9);
35204+ INSTANCE_WR(ctx, 0x2b8c/4, 0x0436086c);
35205+ INSTANCE_WR(ctx, 0x2b90/4, 0x000c001b);
35206+ INSTANCE_WR(ctx, 0x2b98/4, 0x10700ff9);
35207+ INSTANCE_WR(ctx, 0x2b9c/4, 0x0436086c);
35208+ INSTANCE_WR(ctx, 0x2ba0/4, 0x000c001b);
35209+ INSTANCE_WR(ctx, 0x2ba8/4, 0x10700ff9);
35210+ INSTANCE_WR(ctx, 0x2bac/4, 0x0436086c);
35211+ INSTANCE_WR(ctx, 0x2bb0/4, 0x000c001b);
35212+ INSTANCE_WR(ctx, 0x2bb8/4, 0x10700ff9);
35213+ INSTANCE_WR(ctx, 0x2bbc/4, 0x0436086c);
35214+ INSTANCE_WR(ctx, 0x2bc0/4, 0x000c001b);
35215+ INSTANCE_WR(ctx, 0x2bc8/4, 0x10700ff9);
35216+ INSTANCE_WR(ctx, 0x2bcc/4, 0x0436086c);
35217+ INSTANCE_WR(ctx, 0x2bd0/4, 0x000c001b);
35218+ INSTANCE_WR(ctx, 0x2bd8/4, 0x10700ff9);
35219+ INSTANCE_WR(ctx, 0x2bdc/4, 0x0436086c);
35220+ INSTANCE_WR(ctx, 0x2be0/4, 0x000c001b);
35221+ INSTANCE_WR(ctx, 0x2be8/4, 0x10700ff9);
35222+ INSTANCE_WR(ctx, 0x2bec/4, 0x0436086c);
35223+ INSTANCE_WR(ctx, 0x2bf0/4, 0x000c001b);
35224+ INSTANCE_WR(ctx, 0x2bf8/4, 0x10700ff9);
35225+ INSTANCE_WR(ctx, 0x2bfc/4, 0x0436086c);
35226+ INSTANCE_WR(ctx, 0x2c00/4, 0x000c001b);
35227+ INSTANCE_WR(ctx, 0x2c08/4, 0x10700ff9);
35228+ INSTANCE_WR(ctx, 0x2c0c/4, 0x0436086c);
35229+ INSTANCE_WR(ctx, 0x2c10/4, 0x000c001b);
35230+ INSTANCE_WR(ctx, 0x2c18/4, 0x10700ff9);
35231+ INSTANCE_WR(ctx, 0x2c1c/4, 0x0436086c);
35232+ INSTANCE_WR(ctx, 0x2c20/4, 0x000c001b);
35233+ INSTANCE_WR(ctx, 0x2c28/4, 0x10700ff9);
35234+ INSTANCE_WR(ctx, 0x2c2c/4, 0x0436086c);
35235+ INSTANCE_WR(ctx, 0x2c30/4, 0x000c001b);
35236+ INSTANCE_WR(ctx, 0x2c38/4, 0x10700ff9);
35237+ INSTANCE_WR(ctx, 0x2c3c/4, 0x0436086c);
35238+ INSTANCE_WR(ctx, 0x2c40/4, 0x000c001b);
35239+ INSTANCE_WR(ctx, 0x2c48/4, 0x10700ff9);
35240+ INSTANCE_WR(ctx, 0x2c4c/4, 0x0436086c);
35241+ INSTANCE_WR(ctx, 0x2c50/4, 0x000c001b);
35242+ INSTANCE_WR(ctx, 0x2c58/4, 0x10700ff9);
35243+ INSTANCE_WR(ctx, 0x2c5c/4, 0x0436086c);
35244+ INSTANCE_WR(ctx, 0x2c60/4, 0x000c001b);
35245+ INSTANCE_WR(ctx, 0x2c68/4, 0x10700ff9);
35246+ INSTANCE_WR(ctx, 0x2c6c/4, 0x0436086c);
35247+ INSTANCE_WR(ctx, 0x2c70/4, 0x000c001b);
35248+ INSTANCE_WR(ctx, 0x2c78/4, 0x10700ff9);
35249+ INSTANCE_WR(ctx, 0x2c7c/4, 0x0436086c);
35250+ INSTANCE_WR(ctx, 0x2c80/4, 0x000c001b);
35251+ INSTANCE_WR(ctx, 0x2c88/4, 0x10700ff9);
35252+ INSTANCE_WR(ctx, 0x2c8c/4, 0x0436086c);
35253+ INSTANCE_WR(ctx, 0x2c90/4, 0x000c001b);
35254+ INSTANCE_WR(ctx, 0x2c98/4, 0x10700ff9);
35255+ INSTANCE_WR(ctx, 0x2c9c/4, 0x0436086c);
35256+ INSTANCE_WR(ctx, 0x2ca0/4, 0x000c001b);
35257+ INSTANCE_WR(ctx, 0x2ca8/4, 0x10700ff9);
35258+ INSTANCE_WR(ctx, 0x2cac/4, 0x0436086c);
35259+ INSTANCE_WR(ctx, 0x2cb0/4, 0x000c001b);
35260+ INSTANCE_WR(ctx, 0x2cb8/4, 0x10700ff9);
35261+ INSTANCE_WR(ctx, 0x2cbc/4, 0x0436086c);
35262+ INSTANCE_WR(ctx, 0x2cc0/4, 0x000c001b);
35263+ INSTANCE_WR(ctx, 0x2cc8/4, 0x10700ff9);
35264+ INSTANCE_WR(ctx, 0x2ccc/4, 0x0436086c);
35265+ INSTANCE_WR(ctx, 0x2cd0/4, 0x000c001b);
35266+ INSTANCE_WR(ctx, 0x2cd8/4, 0x10700ff9);
35267+ INSTANCE_WR(ctx, 0x2cdc/4, 0x0436086c);
35268+ INSTANCE_WR(ctx, 0x2ce0/4, 0x000c001b);
35269+ INSTANCE_WR(ctx, 0x2ce8/4, 0x10700ff9);
35270+ INSTANCE_WR(ctx, 0x2cec/4, 0x0436086c);
35271+ INSTANCE_WR(ctx, 0x2cf0/4, 0x000c001b);
35272+ INSTANCE_WR(ctx, 0x2cf8/4, 0x10700ff9);
35273+ INSTANCE_WR(ctx, 0x2cfc/4, 0x0436086c);
35274+ INSTANCE_WR(ctx, 0x2d00/4, 0x000c001b);
35275+ INSTANCE_WR(ctx, 0x2d08/4, 0x10700ff9);
35276+ INSTANCE_WR(ctx, 0x2d0c/4, 0x0436086c);
35277+ INSTANCE_WR(ctx, 0x2d10/4, 0x000c001b);
35278+ INSTANCE_WR(ctx, 0x2d18/4, 0x10700ff9);
35279+ INSTANCE_WR(ctx, 0x2d1c/4, 0x0436086c);
35280+ INSTANCE_WR(ctx, 0x2d20/4, 0x000c001b);
35281+ INSTANCE_WR(ctx, 0x2d28/4, 0x10700ff9);
35282+ INSTANCE_WR(ctx, 0x2d2c/4, 0x0436086c);
35283+ INSTANCE_WR(ctx, 0x2d30/4, 0x000c001b);
35284+ INSTANCE_WR(ctx, 0x2d38/4, 0x10700ff9);
35285+ INSTANCE_WR(ctx, 0x2d3c/4, 0x0436086c);
35286+ INSTANCE_WR(ctx, 0x2d40/4, 0x000c001b);
35287+ INSTANCE_WR(ctx, 0x2d48/4, 0x10700ff9);
35288+ INSTANCE_WR(ctx, 0x2d4c/4, 0x0436086c);
35289+ INSTANCE_WR(ctx, 0x2d50/4, 0x000c001b);
35290+ INSTANCE_WR(ctx, 0x2d58/4, 0x10700ff9);
35291+ INSTANCE_WR(ctx, 0x2d5c/4, 0x0436086c);
35292+ INSTANCE_WR(ctx, 0x2d60/4, 0x000c001b);
35293+ INSTANCE_WR(ctx, 0x2d68/4, 0x10700ff9);
35294+ INSTANCE_WR(ctx, 0x2d6c/4, 0x0436086c);
35295+ INSTANCE_WR(ctx, 0x2d70/4, 0x000c001b);
35296+ INSTANCE_WR(ctx, 0x2d78/4, 0x10700ff9);
35297+ INSTANCE_WR(ctx, 0x2d7c/4, 0x0436086c);
35298+ INSTANCE_WR(ctx, 0x2d80/4, 0x000c001b);
35299+ INSTANCE_WR(ctx, 0x2d88/4, 0x10700ff9);
35300+ INSTANCE_WR(ctx, 0x2d8c/4, 0x0436086c);
35301+ INSTANCE_WR(ctx, 0x2d90/4, 0x000c001b);
35302+ INSTANCE_WR(ctx, 0x2d98/4, 0x10700ff9);
35303+ INSTANCE_WR(ctx, 0x2d9c/4, 0x0436086c);
35304+ INSTANCE_WR(ctx, 0x2da0/4, 0x000c001b);
35305+ INSTANCE_WR(ctx, 0x2da8/4, 0x10700ff9);
35306+ INSTANCE_WR(ctx, 0x2dac/4, 0x0436086c);
35307+ INSTANCE_WR(ctx, 0x2db0/4, 0x000c001b);
35308+ INSTANCE_WR(ctx, 0x2db8/4, 0x10700ff9);
35309+ INSTANCE_WR(ctx, 0x2dbc/4, 0x0436086c);
35310+ INSTANCE_WR(ctx, 0x2dc0/4, 0x000c001b);
35311+ INSTANCE_WR(ctx, 0x2dc8/4, 0x10700ff9);
35312+ INSTANCE_WR(ctx, 0x2dcc/4, 0x0436086c);
35313+ INSTANCE_WR(ctx, 0x2dd0/4, 0x000c001b);
35314+ INSTANCE_WR(ctx, 0x2dd8/4, 0x10700ff9);
35315+ INSTANCE_WR(ctx, 0x2ddc/4, 0x0436086c);
35316+ INSTANCE_WR(ctx, 0x2de0/4, 0x000c001b);
35317+ INSTANCE_WR(ctx, 0x2de8/4, 0x10700ff9);
35318+ INSTANCE_WR(ctx, 0x2dec/4, 0x0436086c);
35319+ INSTANCE_WR(ctx, 0x2df0/4, 0x000c001b);
35320+ INSTANCE_WR(ctx, 0x2df8/4, 0x10700ff9);
35321+ INSTANCE_WR(ctx, 0x2dfc/4, 0x0436086c);
35322+ INSTANCE_WR(ctx, 0x2e00/4, 0x000c001b);
35323+ INSTANCE_WR(ctx, 0x2e08/4, 0x10700ff9);
35324+ INSTANCE_WR(ctx, 0x2e0c/4, 0x0436086c);
35325+ INSTANCE_WR(ctx, 0x2e10/4, 0x000c001b);
35326+ INSTANCE_WR(ctx, 0x2e18/4, 0x10700ff9);
35327+ INSTANCE_WR(ctx, 0x2e1c/4, 0x0436086c);
35328+ INSTANCE_WR(ctx, 0x2e20/4, 0x000c001b);
35329+ INSTANCE_WR(ctx, 0x2e28/4, 0x10700ff9);
35330+ INSTANCE_WR(ctx, 0x2e2c/4, 0x0436086c);
35331+ INSTANCE_WR(ctx, 0x2e30/4, 0x000c001b);
35332+ INSTANCE_WR(ctx, 0x2e38/4, 0x10700ff9);
35333+ INSTANCE_WR(ctx, 0x2e3c/4, 0x0436086c);
35334+ INSTANCE_WR(ctx, 0x2e40/4, 0x000c001b);
35335+ INSTANCE_WR(ctx, 0x2e48/4, 0x10700ff9);
35336+ INSTANCE_WR(ctx, 0x2e4c/4, 0x0436086c);
35337+ INSTANCE_WR(ctx, 0x2e50/4, 0x000c001b);
35338+ INSTANCE_WR(ctx, 0x2e58/4, 0x10700ff9);
35339+ INSTANCE_WR(ctx, 0x2e5c/4, 0x0436086c);
35340+ INSTANCE_WR(ctx, 0x2e60/4, 0x000c001b);
35341+ INSTANCE_WR(ctx, 0x2e68/4, 0x10700ff9);
35342+ INSTANCE_WR(ctx, 0x2e6c/4, 0x0436086c);
35343+ INSTANCE_WR(ctx, 0x2e70/4, 0x000c001b);
35344+ INSTANCE_WR(ctx, 0x2e78/4, 0x10700ff9);
35345+ INSTANCE_WR(ctx, 0x2e7c/4, 0x0436086c);
35346+ INSTANCE_WR(ctx, 0x2e80/4, 0x000c001b);
35347+ INSTANCE_WR(ctx, 0x2e88/4, 0x10700ff9);
35348+ INSTANCE_WR(ctx, 0x2e8c/4, 0x0436086c);
35349+ INSTANCE_WR(ctx, 0x2e90/4, 0x000c001b);
35350+ INSTANCE_WR(ctx, 0x2e98/4, 0x10700ff9);
35351+ INSTANCE_WR(ctx, 0x2e9c/4, 0x0436086c);
35352+ INSTANCE_WR(ctx, 0x2ea0/4, 0x000c001b);
35353+ INSTANCE_WR(ctx, 0x2ea8/4, 0x10700ff9);
35354+ INSTANCE_WR(ctx, 0x2eac/4, 0x0436086c);
35355+ INSTANCE_WR(ctx, 0x2eb0/4, 0x000c001b);
35356+ INSTANCE_WR(ctx, 0x2eb8/4, 0x10700ff9);
35357+ INSTANCE_WR(ctx, 0x2ebc/4, 0x0436086c);
35358+ INSTANCE_WR(ctx, 0x2ec0/4, 0x000c001b);
35359+ INSTANCE_WR(ctx, 0x2ec8/4, 0x10700ff9);
35360+ INSTANCE_WR(ctx, 0x2ecc/4, 0x0436086c);
35361+ INSTANCE_WR(ctx, 0x2ed0/4, 0x000c001b);
35362+ INSTANCE_WR(ctx, 0x2ed8/4, 0x10700ff9);
35363+ INSTANCE_WR(ctx, 0x2edc/4, 0x0436086c);
35364+ INSTANCE_WR(ctx, 0x2ee0/4, 0x000c001b);
35365+ INSTANCE_WR(ctx, 0x2ee8/4, 0x10700ff9);
35366+ INSTANCE_WR(ctx, 0x2eec/4, 0x0436086c);
35367+ INSTANCE_WR(ctx, 0x2ef0/4, 0x000c001b);
35368+ INSTANCE_WR(ctx, 0x2ef8/4, 0x10700ff9);
35369+ INSTANCE_WR(ctx, 0x2efc/4, 0x0436086c);
35370+ INSTANCE_WR(ctx, 0x2f00/4, 0x000c001b);
35371+ INSTANCE_WR(ctx, 0x2f08/4, 0x10700ff9);
35372+ INSTANCE_WR(ctx, 0x2f0c/4, 0x0436086c);
35373+ INSTANCE_WR(ctx, 0x2f10/4, 0x000c001b);
35374+ INSTANCE_WR(ctx, 0x2f18/4, 0x10700ff9);
35375+ INSTANCE_WR(ctx, 0x2f1c/4, 0x0436086c);
35376+ INSTANCE_WR(ctx, 0x2f20/4, 0x000c001b);
35377+ INSTANCE_WR(ctx, 0x2f28/4, 0x10700ff9);
35378+ INSTANCE_WR(ctx, 0x2f2c/4, 0x0436086c);
35379+ INSTANCE_WR(ctx, 0x2f30/4, 0x000c001b);
35380+ INSTANCE_WR(ctx, 0x2f38/4, 0x10700ff9);
35381+ INSTANCE_WR(ctx, 0x2f3c/4, 0x0436086c);
35382+ INSTANCE_WR(ctx, 0x2f40/4, 0x000c001b);
35383+ INSTANCE_WR(ctx, 0x2f48/4, 0x10700ff9);
35384+ INSTANCE_WR(ctx, 0x2f4c/4, 0x0436086c);
35385+ INSTANCE_WR(ctx, 0x2f50/4, 0x000c001b);
35386+ INSTANCE_WR(ctx, 0x2f58/4, 0x10700ff9);
35387+ INSTANCE_WR(ctx, 0x2f5c/4, 0x0436086c);
35388+ INSTANCE_WR(ctx, 0x2f60/4, 0x000c001b);
35389+ INSTANCE_WR(ctx, 0x2f68/4, 0x10700ff9);
35390+ INSTANCE_WR(ctx, 0x2f6c/4, 0x0436086c);
35391+ INSTANCE_WR(ctx, 0x2f70/4, 0x000c001b);
35392+ INSTANCE_WR(ctx, 0x2f78/4, 0x10700ff9);
35393+ INSTANCE_WR(ctx, 0x2f7c/4, 0x0436086c);
35394+ INSTANCE_WR(ctx, 0x2f80/4, 0x000c001b);
35395+ INSTANCE_WR(ctx, 0x2f88/4, 0x10700ff9);
35396+ INSTANCE_WR(ctx, 0x2f8c/4, 0x0436086c);
35397+ INSTANCE_WR(ctx, 0x2f90/4, 0x000c001b);
35398+ INSTANCE_WR(ctx, 0x2f98/4, 0x10700ff9);
35399+ INSTANCE_WR(ctx, 0x2f9c/4, 0x0436086c);
35400+ INSTANCE_WR(ctx, 0x2fa0/4, 0x000c001b);
35401+ INSTANCE_WR(ctx, 0x2fa8/4, 0x10700ff9);
35402+ INSTANCE_WR(ctx, 0x2fac/4, 0x0436086c);
35403+ INSTANCE_WR(ctx, 0x2fb0/4, 0x000c001b);
35404+ INSTANCE_WR(ctx, 0x2fb8/4, 0x10700ff9);
35405+ INSTANCE_WR(ctx, 0x2fbc/4, 0x0436086c);
35406+ INSTANCE_WR(ctx, 0x2fc0/4, 0x000c001b);
35407+ INSTANCE_WR(ctx, 0x2fc8/4, 0x10700ff9);
35408+ INSTANCE_WR(ctx, 0x2fcc/4, 0x0436086c);
35409+ INSTANCE_WR(ctx, 0x2fd0/4, 0x000c001b);
35410+ INSTANCE_WR(ctx, 0x2fd8/4, 0x10700ff9);
35411+ INSTANCE_WR(ctx, 0x2fdc/4, 0x0436086c);
35412+ INSTANCE_WR(ctx, 0x2fe0/4, 0x000c001b);
35413+ INSTANCE_WR(ctx, 0x2fe8/4, 0x10700ff9);
35414+ INSTANCE_WR(ctx, 0x2fec/4, 0x0436086c);
35415+ INSTANCE_WR(ctx, 0x2ff0/4, 0x000c001b);
35416+ INSTANCE_WR(ctx, 0x2ff8/4, 0x10700ff9);
35417+ INSTANCE_WR(ctx, 0x2ffc/4, 0x0436086c);
35418+ INSTANCE_WR(ctx, 0x3000/4, 0x000c001b);
35419+ INSTANCE_WR(ctx, 0x3008/4, 0x10700ff9);
35420+ INSTANCE_WR(ctx, 0x300c/4, 0x0436086c);
35421+ INSTANCE_WR(ctx, 0x3010/4, 0x000c001b);
35422+ INSTANCE_WR(ctx, 0x3018/4, 0x10700ff9);
35423+ INSTANCE_WR(ctx, 0x301c/4, 0x0436086c);
35424+ INSTANCE_WR(ctx, 0x3020/4, 0x000c001b);
35425+ INSTANCE_WR(ctx, 0x3028/4, 0x10700ff9);
35426+ INSTANCE_WR(ctx, 0x302c/4, 0x0436086c);
35427+ INSTANCE_WR(ctx, 0x3030/4, 0x000c001b);
35428+ INSTANCE_WR(ctx, 0x3038/4, 0x10700ff9);
35429+ INSTANCE_WR(ctx, 0x303c/4, 0x0436086c);
35430+ INSTANCE_WR(ctx, 0x3040/4, 0x000c001b);
35431+ INSTANCE_WR(ctx, 0x3048/4, 0x10700ff9);
35432+ INSTANCE_WR(ctx, 0x304c/4, 0x0436086c);
35433+ INSTANCE_WR(ctx, 0x3050/4, 0x000c001b);
35434+ INSTANCE_WR(ctx, 0x3058/4, 0x10700ff9);
35435+ INSTANCE_WR(ctx, 0x305c/4, 0x0436086c);
35436+ INSTANCE_WR(ctx, 0x3060/4, 0x000c001b);
35437+ INSTANCE_WR(ctx, 0x3068/4, 0x10700ff9);
35438+ INSTANCE_WR(ctx, 0x306c/4, 0x0436086c);
35439+ INSTANCE_WR(ctx, 0x3070/4, 0x000c001b);
35440+ INSTANCE_WR(ctx, 0x3078/4, 0x10700ff9);
35441+ INSTANCE_WR(ctx, 0x307c/4, 0x0436086c);
35442+ INSTANCE_WR(ctx, 0x3080/4, 0x000c001b);
35443+ INSTANCE_WR(ctx, 0x3088/4, 0x10700ff9);
35444+ INSTANCE_WR(ctx, 0x308c/4, 0x0436086c);
35445+ INSTANCE_WR(ctx, 0x3090/4, 0x000c001b);
35446+ for(i = 0x30b8; i< 0x30c8; i += 4)
35447+ INSTANCE_WR(ctx, i/4, 0x0000ffff);
35448+ INSTANCE_WR(ctx, 0x344c/4, 0x3f800000);
35449+ INSTANCE_WR(ctx, 0x3808/4, 0x3f800000);
35450+ INSTANCE_WR(ctx, 0x381c/4, 0x3f800000);
35451+ INSTANCE_WR(ctx, 0x3848/4, 0x40000000);
35452+ INSTANCE_WR(ctx, 0x384c/4, 0x3f800000);
35453+ INSTANCE_WR(ctx, 0x3850/4, 0x3f000000);
35454+ INSTANCE_WR(ctx, 0x3858/4, 0x40000000);
35455+ INSTANCE_WR(ctx, 0x385c/4, 0x3f800000);
35456+ INSTANCE_WR(ctx, 0x3864/4, 0xbf800000);
35457+ INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);
35458+}
35459+
35460+static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
35461+{
35462+ struct drm_nouveau_private *dev_priv = dev->dev_private;
35463+ int i;
35464+
35465+ INSTANCE_WR(ctx, 0x40c/4, 0x01000101);
35466+ INSTANCE_WR(ctx, 0x420/4, 0x00000111);
35467+ INSTANCE_WR(ctx, 0x424/4, 0x00000060);
35468+ INSTANCE_WR(ctx, 0x440/4, 0x00000080);
35469+ INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
35470+ INSTANCE_WR(ctx, 0x448/4, 0x00000001);
35471+ INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
35472+ INSTANCE_WR(ctx, 0x480/4, 0xffff0000);
35473+ for(i = 0x4d4; i< 0x4dc; i += 4)
35474+ INSTANCE_WR(ctx, i/4, 0x0fff0000);
35475+ INSTANCE_WR(ctx, 0x4e0/4, 0x00011100);
35476+ for(i = 0x4fc; i< 0x53c; i += 4)
35477+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
35478+ INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff);
35479+ INSTANCE_WR(ctx, 0x57c/4, 0x00000080);
35480+ INSTANCE_WR(ctx, 0x580/4, 0x30201000);
35481+ INSTANCE_WR(ctx, 0x584/4, 0x70605040);
35482+ INSTANCE_WR(ctx, 0x588/4, 0xb8a89888);
35483+ INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8);
35484+ INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000);
35485+ for(i = 0x5f0; i< 0x630; i += 4)
35486+ INSTANCE_WR(ctx, i/4, 0x00010588);
35487+ for(i = 0x630; i< 0x670; i += 4)
35488+ INSTANCE_WR(ctx, i/4, 0x00030303);
35489+ for(i = 0x6b0; i< 0x6f0; i += 4)
35490+ INSTANCE_WR(ctx, i/4, 0x0008aae4);
35491+ for(i = 0x6f0; i< 0x730; i += 4)
35492+ INSTANCE_WR(ctx, i/4, 0x01012000);
35493+ for(i = 0x730; i< 0x770; i += 4)
35494+ INSTANCE_WR(ctx, i/4, 0x00080008);
35495+ INSTANCE_WR(ctx, 0x850/4, 0x00040000);
35496+ INSTANCE_WR(ctx, 0x854/4, 0x00010000);
35497+ for(i = 0x858; i< 0x868; i += 4)
35498+ INSTANCE_WR(ctx, i/4, 0x00040004);
35499+ INSTANCE_WR(ctx, 0x15ac/4, 0x10700ff9);
35500+ INSTANCE_WR(ctx, 0x15b0/4, 0x0436086c);
35501+ INSTANCE_WR(ctx, 0x15b4/4, 0x000c001b);
35502+ INSTANCE_WR(ctx, 0x15bc/4, 0x10700ff9);
35503+ INSTANCE_WR(ctx, 0x15c0/4, 0x0436086c);
35504+ INSTANCE_WR(ctx, 0x15c4/4, 0x000c001b);
35505+ INSTANCE_WR(ctx, 0x15cc/4, 0x10700ff9);
35506+ INSTANCE_WR(ctx, 0x15d0/4, 0x0436086c);
35507+ INSTANCE_WR(ctx, 0x15d4/4, 0x000c001b);
35508+ INSTANCE_WR(ctx, 0x15dc/4, 0x10700ff9);
35509+ INSTANCE_WR(ctx, 0x15e0/4, 0x0436086c);
35510+ INSTANCE_WR(ctx, 0x15e4/4, 0x000c001b);
35511+ INSTANCE_WR(ctx, 0x15ec/4, 0x10700ff9);
35512+ INSTANCE_WR(ctx, 0x15f0/4, 0x0436086c);
35513+ INSTANCE_WR(ctx, 0x15f4/4, 0x000c001b);
35514+ INSTANCE_WR(ctx, 0x15fc/4, 0x10700ff9);
35515+ INSTANCE_WR(ctx, 0x1600/4, 0x0436086c);
35516+ INSTANCE_WR(ctx, 0x1604/4, 0x000c001b);
35517+ INSTANCE_WR(ctx, 0x160c/4, 0x10700ff9);
35518+ INSTANCE_WR(ctx, 0x1610/4, 0x0436086c);
35519+ INSTANCE_WR(ctx, 0x1614/4, 0x000c001b);
35520+ INSTANCE_WR(ctx, 0x161c/4, 0x10700ff9);
35521+ INSTANCE_WR(ctx, 0x1620/4, 0x0436086c);
35522+ INSTANCE_WR(ctx, 0x1624/4, 0x000c001b);
35523+ INSTANCE_WR(ctx, 0x162c/4, 0x10700ff9);
35524+ INSTANCE_WR(ctx, 0x1630/4, 0x0436086c);
35525+ INSTANCE_WR(ctx, 0x1634/4, 0x000c001b);
35526+ INSTANCE_WR(ctx, 0x163c/4, 0x10700ff9);
35527+ INSTANCE_WR(ctx, 0x1640/4, 0x0436086c);
35528+ INSTANCE_WR(ctx, 0x1644/4, 0x000c001b);
35529+ INSTANCE_WR(ctx, 0x164c/4, 0x10700ff9);
35530+ INSTANCE_WR(ctx, 0x1650/4, 0x0436086c);
35531+ INSTANCE_WR(ctx, 0x1654/4, 0x000c001b);
35532+ INSTANCE_WR(ctx, 0x165c/4, 0x10700ff9);
35533+ INSTANCE_WR(ctx, 0x1660/4, 0x0436086c);
35534+ INSTANCE_WR(ctx, 0x1664/4, 0x000c001b);
35535+ INSTANCE_WR(ctx, 0x166c/4, 0x10700ff9);
35536+ INSTANCE_WR(ctx, 0x1670/4, 0x0436086c);
35537+ INSTANCE_WR(ctx, 0x1674/4, 0x000c001b);
35538+ INSTANCE_WR(ctx, 0x167c/4, 0x10700ff9);
35539+ INSTANCE_WR(ctx, 0x1680/4, 0x0436086c);
35540+ INSTANCE_WR(ctx, 0x1684/4, 0x000c001b);
35541+ INSTANCE_WR(ctx, 0x168c/4, 0x10700ff9);
35542+ INSTANCE_WR(ctx, 0x1690/4, 0x0436086c);
35543+ INSTANCE_WR(ctx, 0x1694/4, 0x000c001b);
35544+ INSTANCE_WR(ctx, 0x169c/4, 0x10700ff9);
35545+ INSTANCE_WR(ctx, 0x16a0/4, 0x0436086c);
35546+ INSTANCE_WR(ctx, 0x16a4/4, 0x000c001b);
35547+ INSTANCE_WR(ctx, 0x16ac/4, 0x10700ff9);
35548+ INSTANCE_WR(ctx, 0x16b0/4, 0x0436086c);
35549+ INSTANCE_WR(ctx, 0x16b4/4, 0x000c001b);
35550+ INSTANCE_WR(ctx, 0x16bc/4, 0x10700ff9);
35551+ INSTANCE_WR(ctx, 0x16c0/4, 0x0436086c);
35552+ INSTANCE_WR(ctx, 0x16c4/4, 0x000c001b);
35553+ INSTANCE_WR(ctx, 0x16cc/4, 0x10700ff9);
35554+ INSTANCE_WR(ctx, 0x16d0/4, 0x0436086c);
35555+ INSTANCE_WR(ctx, 0x16d4/4, 0x000c001b);
35556+ INSTANCE_WR(ctx, 0x16dc/4, 0x10700ff9);
35557+ INSTANCE_WR(ctx, 0x16e0/4, 0x0436086c);
35558+ INSTANCE_WR(ctx, 0x16e4/4, 0x000c001b);
35559+ INSTANCE_WR(ctx, 0x16ec/4, 0x10700ff9);
35560+ INSTANCE_WR(ctx, 0x16f0/4, 0x0436086c);
35561+ INSTANCE_WR(ctx, 0x16f4/4, 0x000c001b);
35562+ INSTANCE_WR(ctx, 0x16fc/4, 0x10700ff9);
35563+ INSTANCE_WR(ctx, 0x1700/4, 0x0436086c);
35564+ INSTANCE_WR(ctx, 0x1704/4, 0x000c001b);
35565+ INSTANCE_WR(ctx, 0x170c/4, 0x10700ff9);
35566+ INSTANCE_WR(ctx, 0x1710/4, 0x0436086c);
35567+ INSTANCE_WR(ctx, 0x1714/4, 0x000c001b);
35568+ INSTANCE_WR(ctx, 0x171c/4, 0x10700ff9);
35569+ INSTANCE_WR(ctx, 0x1720/4, 0x0436086c);
35570+ INSTANCE_WR(ctx, 0x1724/4, 0x000c001b);
35571+ INSTANCE_WR(ctx, 0x172c/4, 0x10700ff9);
35572+ INSTANCE_WR(ctx, 0x1730/4, 0x0436086c);
35573+ INSTANCE_WR(ctx, 0x1734/4, 0x000c001b);
35574+ INSTANCE_WR(ctx, 0x173c/4, 0x10700ff9);
35575+ INSTANCE_WR(ctx, 0x1740/4, 0x0436086c);
35576+ INSTANCE_WR(ctx, 0x1744/4, 0x000c001b);
35577+ INSTANCE_WR(ctx, 0x174c/4, 0x10700ff9);
35578+ INSTANCE_WR(ctx, 0x1750/4, 0x0436086c);
35579+ INSTANCE_WR(ctx, 0x1754/4, 0x000c001b);
35580+ INSTANCE_WR(ctx, 0x175c/4, 0x10700ff9);
35581+ INSTANCE_WR(ctx, 0x1760/4, 0x0436086c);
35582+ INSTANCE_WR(ctx, 0x1764/4, 0x000c001b);
35583+ INSTANCE_WR(ctx, 0x176c/4, 0x10700ff9);
35584+ INSTANCE_WR(ctx, 0x1770/4, 0x0436086c);
35585+ INSTANCE_WR(ctx, 0x1774/4, 0x000c001b);
35586+ INSTANCE_WR(ctx, 0x177c/4, 0x10700ff9);
35587+ INSTANCE_WR(ctx, 0x1780/4, 0x0436086c);
35588+ INSTANCE_WR(ctx, 0x1784/4, 0x000c001b);
35589+ INSTANCE_WR(ctx, 0x178c/4, 0x10700ff9);
35590+ INSTANCE_WR(ctx, 0x1790/4, 0x0436086c);
35591+ INSTANCE_WR(ctx, 0x1794/4, 0x000c001b);
35592+ INSTANCE_WR(ctx, 0x179c/4, 0x10700ff9);
35593+ INSTANCE_WR(ctx, 0x17a0/4, 0x0436086c);
35594+ INSTANCE_WR(ctx, 0x17a4/4, 0x000c001b);
35595+ INSTANCE_WR(ctx, 0x17ac/4, 0x10700ff9);
35596+ INSTANCE_WR(ctx, 0x17b0/4, 0x0436086c);
35597+ INSTANCE_WR(ctx, 0x17b4/4, 0x000c001b);
35598+ INSTANCE_WR(ctx, 0x17bc/4, 0x10700ff9);
35599+ INSTANCE_WR(ctx, 0x17c0/4, 0x0436086c);
35600+ INSTANCE_WR(ctx, 0x17c4/4, 0x000c001b);
35601+ INSTANCE_WR(ctx, 0x17cc/4, 0x10700ff9);
35602+ INSTANCE_WR(ctx, 0x17d0/4, 0x0436086c);
35603+ INSTANCE_WR(ctx, 0x17d4/4, 0x000c001b);
35604+ INSTANCE_WR(ctx, 0x17dc/4, 0x10700ff9);
35605+ INSTANCE_WR(ctx, 0x17e0/4, 0x0436086c);
35606+ INSTANCE_WR(ctx, 0x17e4/4, 0x000c001b);
35607+ INSTANCE_WR(ctx, 0x17ec/4, 0x10700ff9);
35608+ INSTANCE_WR(ctx, 0x17f0/4, 0x0436086c);
35609+ INSTANCE_WR(ctx, 0x17f4/4, 0x000c001b);
35610+ INSTANCE_WR(ctx, 0x17fc/4, 0x10700ff9);
35611+ INSTANCE_WR(ctx, 0x1800/4, 0x0436086c);
35612+ INSTANCE_WR(ctx, 0x1804/4, 0x000c001b);
35613+ INSTANCE_WR(ctx, 0x180c/4, 0x10700ff9);
35614+ INSTANCE_WR(ctx, 0x1810/4, 0x0436086c);
35615+ INSTANCE_WR(ctx, 0x1814/4, 0x000c001b);
35616+ INSTANCE_WR(ctx, 0x181c/4, 0x10700ff9);
35617+ INSTANCE_WR(ctx, 0x1820/4, 0x0436086c);
35618+ INSTANCE_WR(ctx, 0x1824/4, 0x000c001b);
35619+ INSTANCE_WR(ctx, 0x182c/4, 0x10700ff9);
35620+ INSTANCE_WR(ctx, 0x1830/4, 0x0436086c);
35621+ INSTANCE_WR(ctx, 0x1834/4, 0x000c001b);
35622+ INSTANCE_WR(ctx, 0x183c/4, 0x10700ff9);
35623+ INSTANCE_WR(ctx, 0x1840/4, 0x0436086c);
35624+ INSTANCE_WR(ctx, 0x1844/4, 0x000c001b);
35625+ INSTANCE_WR(ctx, 0x184c/4, 0x10700ff9);
35626+ INSTANCE_WR(ctx, 0x1850/4, 0x0436086c);
35627+ INSTANCE_WR(ctx, 0x1854/4, 0x000c001b);
35628+ INSTANCE_WR(ctx, 0x185c/4, 0x10700ff9);
35629+ INSTANCE_WR(ctx, 0x1860/4, 0x0436086c);
35630+ INSTANCE_WR(ctx, 0x1864/4, 0x000c001b);
35631+ INSTANCE_WR(ctx, 0x186c/4, 0x10700ff9);
35632+ INSTANCE_WR(ctx, 0x1870/4, 0x0436086c);
35633+ INSTANCE_WR(ctx, 0x1874/4, 0x000c001b);
35634+ INSTANCE_WR(ctx, 0x187c/4, 0x10700ff9);
35635+ INSTANCE_WR(ctx, 0x1880/4, 0x0436086c);
35636+ INSTANCE_WR(ctx, 0x1884/4, 0x000c001b);
35637+ INSTANCE_WR(ctx, 0x188c/4, 0x10700ff9);
35638+ INSTANCE_WR(ctx, 0x1890/4, 0x0436086c);
35639+ INSTANCE_WR(ctx, 0x1894/4, 0x000c001b);
35640+ INSTANCE_WR(ctx, 0x189c/4, 0x10700ff9);
35641+ INSTANCE_WR(ctx, 0x18a0/4, 0x0436086c);
35642+ INSTANCE_WR(ctx, 0x18a4/4, 0x000c001b);
35643+ INSTANCE_WR(ctx, 0x18ac/4, 0x10700ff9);
35644+ INSTANCE_WR(ctx, 0x18b0/4, 0x0436086c);
35645+ INSTANCE_WR(ctx, 0x18b4/4, 0x000c001b);
35646+ INSTANCE_WR(ctx, 0x18bc/4, 0x10700ff9);
35647+ INSTANCE_WR(ctx, 0x18c0/4, 0x0436086c);
35648+ INSTANCE_WR(ctx, 0x18c4/4, 0x000c001b);
35649+ INSTANCE_WR(ctx, 0x18cc/4, 0x10700ff9);
35650+ INSTANCE_WR(ctx, 0x18d0/4, 0x0436086c);
35651+ INSTANCE_WR(ctx, 0x18d4/4, 0x000c001b);
35652+ INSTANCE_WR(ctx, 0x18dc/4, 0x10700ff9);
35653+ INSTANCE_WR(ctx, 0x18e0/4, 0x0436086c);
35654+ INSTANCE_WR(ctx, 0x18e4/4, 0x000c001b);
35655+ INSTANCE_WR(ctx, 0x18ec/4, 0x10700ff9);
35656+ INSTANCE_WR(ctx, 0x18f0/4, 0x0436086c);
35657+ INSTANCE_WR(ctx, 0x18f4/4, 0x000c001b);
35658+ INSTANCE_WR(ctx, 0x18fc/4, 0x10700ff9);
35659+ INSTANCE_WR(ctx, 0x1900/4, 0x0436086c);
35660+ INSTANCE_WR(ctx, 0x1904/4, 0x000c001b);
35661+ INSTANCE_WR(ctx, 0x190c/4, 0x10700ff9);
35662+ INSTANCE_WR(ctx, 0x1910/4, 0x0436086c);
35663+ INSTANCE_WR(ctx, 0x1914/4, 0x000c001b);
35664+ INSTANCE_WR(ctx, 0x191c/4, 0x10700ff9);
35665+ INSTANCE_WR(ctx, 0x1920/4, 0x0436086c);
35666+ INSTANCE_WR(ctx, 0x1924/4, 0x000c001b);
35667+ INSTANCE_WR(ctx, 0x192c/4, 0x10700ff9);
35668+ INSTANCE_WR(ctx, 0x1930/4, 0x0436086c);
35669+ INSTANCE_WR(ctx, 0x1934/4, 0x000c001b);
35670+ INSTANCE_WR(ctx, 0x193c/4, 0x10700ff9);
35671+ INSTANCE_WR(ctx, 0x1940/4, 0x0436086c);
35672+ INSTANCE_WR(ctx, 0x1944/4, 0x000c001b);
35673+ INSTANCE_WR(ctx, 0x194c/4, 0x10700ff9);
35674+ INSTANCE_WR(ctx, 0x1950/4, 0x0436086c);
35675+ INSTANCE_WR(ctx, 0x1954/4, 0x000c001b);
35676+ INSTANCE_WR(ctx, 0x195c/4, 0x10700ff9);
35677+ INSTANCE_WR(ctx, 0x1960/4, 0x0436086c);
35678+ INSTANCE_WR(ctx, 0x1964/4, 0x000c001b);
35679+ INSTANCE_WR(ctx, 0x196c/4, 0x10700ff9);
35680+ INSTANCE_WR(ctx, 0x1970/4, 0x0436086c);
35681+ INSTANCE_WR(ctx, 0x1974/4, 0x000c001b);
35682+ INSTANCE_WR(ctx, 0x197c/4, 0x10700ff9);
35683+ INSTANCE_WR(ctx, 0x1980/4, 0x0436086c);
35684+ INSTANCE_WR(ctx, 0x1984/4, 0x000c001b);
35685+ INSTANCE_WR(ctx, 0x198c/4, 0x10700ff9);
35686+ INSTANCE_WR(ctx, 0x1990/4, 0x0436086c);
35687+ INSTANCE_WR(ctx, 0x1994/4, 0x000c001b);
35688+ INSTANCE_WR(ctx, 0x199c/4, 0x10700ff9);
35689+ INSTANCE_WR(ctx, 0x19a0/4, 0x0436086c);
35690+ INSTANCE_WR(ctx, 0x19a4/4, 0x000c001b);
35691+ INSTANCE_WR(ctx, 0x19ac/4, 0x10700ff9);
35692+ INSTANCE_WR(ctx, 0x19b0/4, 0x0436086c);
35693+ INSTANCE_WR(ctx, 0x19b4/4, 0x000c001b);
35694+ INSTANCE_WR(ctx, 0x19bc/4, 0x10700ff9);
35695+ INSTANCE_WR(ctx, 0x19c0/4, 0x0436086c);
35696+ INSTANCE_WR(ctx, 0x19c4/4, 0x000c001b);
35697+ INSTANCE_WR(ctx, 0x19cc/4, 0x10700ff9);
35698+ INSTANCE_WR(ctx, 0x19d0/4, 0x0436086c);
35699+ INSTANCE_WR(ctx, 0x19d4/4, 0x000c001b);
35700+ INSTANCE_WR(ctx, 0x19dc/4, 0x10700ff9);
35701+ INSTANCE_WR(ctx, 0x19e0/4, 0x0436086c);
35702+ INSTANCE_WR(ctx, 0x19e4/4, 0x000c001b);
35703+ INSTANCE_WR(ctx, 0x19ec/4, 0x10700ff9);
35704+ INSTANCE_WR(ctx, 0x19f0/4, 0x0436086c);
35705+ INSTANCE_WR(ctx, 0x19f4/4, 0x000c001b);
35706+ INSTANCE_WR(ctx, 0x19fc/4, 0x10700ff9);
35707+ INSTANCE_WR(ctx, 0x1a00/4, 0x0436086c);
35708+ INSTANCE_WR(ctx, 0x1a04/4, 0x000c001b);
35709+ INSTANCE_WR(ctx, 0x1a0c/4, 0x10700ff9);
35710+ INSTANCE_WR(ctx, 0x1a10/4, 0x0436086c);
35711+ INSTANCE_WR(ctx, 0x1a14/4, 0x000c001b);
35712+ INSTANCE_WR(ctx, 0x1a1c/4, 0x10700ff9);
35713+ INSTANCE_WR(ctx, 0x1a20/4, 0x0436086c);
35714+ INSTANCE_WR(ctx, 0x1a24/4, 0x000c001b);
35715+ INSTANCE_WR(ctx, 0x1a2c/4, 0x10700ff9);
35716+ INSTANCE_WR(ctx, 0x1a30/4, 0x0436086c);
35717+ INSTANCE_WR(ctx, 0x1a34/4, 0x000c001b);
35718+ INSTANCE_WR(ctx, 0x1a3c/4, 0x10700ff9);
35719+ INSTANCE_WR(ctx, 0x1a40/4, 0x0436086c);
35720+ INSTANCE_WR(ctx, 0x1a44/4, 0x000c001b);
35721+ INSTANCE_WR(ctx, 0x1a4c/4, 0x10700ff9);
35722+ INSTANCE_WR(ctx, 0x1a50/4, 0x0436086c);
35723+ INSTANCE_WR(ctx, 0x1a54/4, 0x000c001b);
35724+ INSTANCE_WR(ctx, 0x1a5c/4, 0x10700ff9);
35725+ INSTANCE_WR(ctx, 0x1a60/4, 0x0436086c);
35726+ INSTANCE_WR(ctx, 0x1a64/4, 0x000c001b);
35727+ INSTANCE_WR(ctx, 0x1a6c/4, 0x10700ff9);
35728+ INSTANCE_WR(ctx, 0x1a70/4, 0x0436086c);
35729+ INSTANCE_WR(ctx, 0x1a74/4, 0x000c001b);
35730+ INSTANCE_WR(ctx, 0x1a7c/4, 0x10700ff9);
35731+ INSTANCE_WR(ctx, 0x1a80/4, 0x0436086c);
35732+ INSTANCE_WR(ctx, 0x1a84/4, 0x000c001b);
35733+ INSTANCE_WR(ctx, 0x1a8c/4, 0x10700ff9);
35734+ INSTANCE_WR(ctx, 0x1a90/4, 0x0436086c);
35735+ INSTANCE_WR(ctx, 0x1a94/4, 0x000c001b);
35736+ INSTANCE_WR(ctx, 0x1a9c/4, 0x10700ff9);
35737+ INSTANCE_WR(ctx, 0x1aa0/4, 0x0436086c);
35738+ INSTANCE_WR(ctx, 0x1aa4/4, 0x000c001b);
35739+ INSTANCE_WR(ctx, 0x1aac/4, 0x10700ff9);
35740+ INSTANCE_WR(ctx, 0x1ab0/4, 0x0436086c);
35741+ INSTANCE_WR(ctx, 0x1ab4/4, 0x000c001b);
35742+ INSTANCE_WR(ctx, 0x1abc/4, 0x10700ff9);
35743+ INSTANCE_WR(ctx, 0x1ac0/4, 0x0436086c);
35744+ INSTANCE_WR(ctx, 0x1ac4/4, 0x000c001b);
35745+ INSTANCE_WR(ctx, 0x1acc/4, 0x10700ff9);
35746+ INSTANCE_WR(ctx, 0x1ad0/4, 0x0436086c);
35747+ INSTANCE_WR(ctx, 0x1ad4/4, 0x000c001b);
35748+ INSTANCE_WR(ctx, 0x1adc/4, 0x10700ff9);
35749+ INSTANCE_WR(ctx, 0x1ae0/4, 0x0436086c);
35750+ INSTANCE_WR(ctx, 0x1ae4/4, 0x000c001b);
35751+ INSTANCE_WR(ctx, 0x1aec/4, 0x10700ff9);
35752+ INSTANCE_WR(ctx, 0x1af0/4, 0x0436086c);
35753+ INSTANCE_WR(ctx, 0x1af4/4, 0x000c001b);
35754+ INSTANCE_WR(ctx, 0x1afc/4, 0x10700ff9);
35755+ INSTANCE_WR(ctx, 0x1b00/4, 0x0436086c);
35756+ INSTANCE_WR(ctx, 0x1b04/4, 0x000c001b);
35757+ INSTANCE_WR(ctx, 0x1b0c/4, 0x10700ff9);
35758+ INSTANCE_WR(ctx, 0x1b10/4, 0x0436086c);
35759+ INSTANCE_WR(ctx, 0x1b14/4, 0x000c001b);
35760+ INSTANCE_WR(ctx, 0x1b1c/4, 0x10700ff9);
35761+ INSTANCE_WR(ctx, 0x1b20/4, 0x0436086c);
35762+ INSTANCE_WR(ctx, 0x1b24/4, 0x000c001b);
35763+ INSTANCE_WR(ctx, 0x1b2c/4, 0x10700ff9);
35764+ INSTANCE_WR(ctx, 0x1b30/4, 0x0436086c);
35765+ INSTANCE_WR(ctx, 0x1b34/4, 0x000c001b);
35766+ INSTANCE_WR(ctx, 0x1b3c/4, 0x10700ff9);
35767+ INSTANCE_WR(ctx, 0x1b40/4, 0x0436086c);
35768+ INSTANCE_WR(ctx, 0x1b44/4, 0x000c001b);
35769+ INSTANCE_WR(ctx, 0x1b4c/4, 0x10700ff9);
35770+ INSTANCE_WR(ctx, 0x1b50/4, 0x0436086c);
35771+ INSTANCE_WR(ctx, 0x1b54/4, 0x000c001b);
35772+ INSTANCE_WR(ctx, 0x1b5c/4, 0x10700ff9);
35773+ INSTANCE_WR(ctx, 0x1b60/4, 0x0436086c);
35774+ INSTANCE_WR(ctx, 0x1b64/4, 0x000c001b);
35775+ INSTANCE_WR(ctx, 0x1b6c/4, 0x10700ff9);
35776+ INSTANCE_WR(ctx, 0x1b70/4, 0x0436086c);
35777+ INSTANCE_WR(ctx, 0x1b74/4, 0x000c001b);
35778+ INSTANCE_WR(ctx, 0x1b7c/4, 0x10700ff9);
35779+ INSTANCE_WR(ctx, 0x1b80/4, 0x0436086c);
35780+ INSTANCE_WR(ctx, 0x1b84/4, 0x000c001b);
35781+ INSTANCE_WR(ctx, 0x1b8c/4, 0x10700ff9);
35782+ INSTANCE_WR(ctx, 0x1b90/4, 0x0436086c);
35783+ INSTANCE_WR(ctx, 0x1b94/4, 0x000c001b);
35784+ INSTANCE_WR(ctx, 0x1b9c/4, 0x10700ff9);
35785+ INSTANCE_WR(ctx, 0x1ba0/4, 0x0436086c);
35786+ INSTANCE_WR(ctx, 0x1ba4/4, 0x000c001b);
35787+ INSTANCE_WR(ctx, 0x1bac/4, 0x10700ff9);
35788+ INSTANCE_WR(ctx, 0x1bb0/4, 0x0436086c);
35789+ INSTANCE_WR(ctx, 0x1bb4/4, 0x000c001b);
35790+ INSTANCE_WR(ctx, 0x1bbc/4, 0x10700ff9);
35791+ INSTANCE_WR(ctx, 0x1bc0/4, 0x0436086c);
35792+ INSTANCE_WR(ctx, 0x1bc4/4, 0x000c001b);
35793+ INSTANCE_WR(ctx, 0x1bcc/4, 0x10700ff9);
35794+ INSTANCE_WR(ctx, 0x1bd0/4, 0x0436086c);
35795+ INSTANCE_WR(ctx, 0x1bd4/4, 0x000c001b);
35796+ INSTANCE_WR(ctx, 0x1bdc/4, 0x10700ff9);
35797+ INSTANCE_WR(ctx, 0x1be0/4, 0x0436086c);
35798+ INSTANCE_WR(ctx, 0x1be4/4, 0x000c001b);
35799+ INSTANCE_WR(ctx, 0x1bec/4, 0x10700ff9);
35800+ INSTANCE_WR(ctx, 0x1bf0/4, 0x0436086c);
35801+ INSTANCE_WR(ctx, 0x1bf4/4, 0x000c001b);
35802+ INSTANCE_WR(ctx, 0x1bfc/4, 0x10700ff9);
35803+ INSTANCE_WR(ctx, 0x1c00/4, 0x0436086c);
35804+ INSTANCE_WR(ctx, 0x1c04/4, 0x000c001b);
35805+ INSTANCE_WR(ctx, 0x1c0c/4, 0x10700ff9);
35806+ INSTANCE_WR(ctx, 0x1c10/4, 0x0436086c);
35807+ INSTANCE_WR(ctx, 0x1c14/4, 0x000c001b);
35808+ INSTANCE_WR(ctx, 0x1c1c/4, 0x10700ff9);
35809+ INSTANCE_WR(ctx, 0x1c20/4, 0x0436086c);
35810+ INSTANCE_WR(ctx, 0x1c24/4, 0x000c001b);
35811+ INSTANCE_WR(ctx, 0x1c2c/4, 0x10700ff9);
35812+ INSTANCE_WR(ctx, 0x1c30/4, 0x0436086c);
35813+ INSTANCE_WR(ctx, 0x1c34/4, 0x000c001b);
35814+ INSTANCE_WR(ctx, 0x1c3c/4, 0x10700ff9);
35815+ INSTANCE_WR(ctx, 0x1c40/4, 0x0436086c);
35816+ INSTANCE_WR(ctx, 0x1c44/4, 0x000c001b);
35817+ INSTANCE_WR(ctx, 0x1c4c/4, 0x10700ff9);
35818+ INSTANCE_WR(ctx, 0x1c50/4, 0x0436086c);
35819+ INSTANCE_WR(ctx, 0x1c54/4, 0x000c001b);
35820+ INSTANCE_WR(ctx, 0x1c5c/4, 0x10700ff9);
35821+ INSTANCE_WR(ctx, 0x1c60/4, 0x0436086c);
35822+ INSTANCE_WR(ctx, 0x1c64/4, 0x000c001b);
35823+ INSTANCE_WR(ctx, 0x1c6c/4, 0x10700ff9);
35824+ INSTANCE_WR(ctx, 0x1c70/4, 0x0436086c);
35825+ INSTANCE_WR(ctx, 0x1c74/4, 0x000c001b);
35826+ INSTANCE_WR(ctx, 0x1c7c/4, 0x10700ff9);
35827+ INSTANCE_WR(ctx, 0x1c80/4, 0x0436086c);
35828+ INSTANCE_WR(ctx, 0x1c84/4, 0x000c001b);
35829+ INSTANCE_WR(ctx, 0x1c8c/4, 0x10700ff9);
35830+ INSTANCE_WR(ctx, 0x1c90/4, 0x0436086c);
35831+ INSTANCE_WR(ctx, 0x1c94/4, 0x000c001b);
35832+ INSTANCE_WR(ctx, 0x1c9c/4, 0x10700ff9);
35833+ INSTANCE_WR(ctx, 0x1ca0/4, 0x0436086c);
35834+ INSTANCE_WR(ctx, 0x1ca4/4, 0x000c001b);
35835+ INSTANCE_WR(ctx, 0x1cac/4, 0x10700ff9);
35836+ INSTANCE_WR(ctx, 0x1cb0/4, 0x0436086c);
35837+ INSTANCE_WR(ctx, 0x1cb4/4, 0x000c001b);
35838+ INSTANCE_WR(ctx, 0x1cbc/4, 0x10700ff9);
35839+ INSTANCE_WR(ctx, 0x1cc0/4, 0x0436086c);
35840+ INSTANCE_WR(ctx, 0x1cc4/4, 0x000c001b);
35841+ INSTANCE_WR(ctx, 0x1ccc/4, 0x10700ff9);
35842+ INSTANCE_WR(ctx, 0x1cd0/4, 0x0436086c);
35843+ INSTANCE_WR(ctx, 0x1cd4/4, 0x000c001b);
35844+ INSTANCE_WR(ctx, 0x1cdc/4, 0x10700ff9);
35845+ INSTANCE_WR(ctx, 0x1ce0/4, 0x0436086c);
35846+ INSTANCE_WR(ctx, 0x1ce4/4, 0x000c001b);
35847+ INSTANCE_WR(ctx, 0x1cec/4, 0x10700ff9);
35848+ INSTANCE_WR(ctx, 0x1cf0/4, 0x0436086c);
35849+ INSTANCE_WR(ctx, 0x1cf4/4, 0x000c001b);
35850+ INSTANCE_WR(ctx, 0x1cfc/4, 0x10700ff9);
35851+ INSTANCE_WR(ctx, 0x1d00/4, 0x0436086c);
35852+ INSTANCE_WR(ctx, 0x1d04/4, 0x000c001b);
35853+ INSTANCE_WR(ctx, 0x1d0c/4, 0x10700ff9);
35854+ INSTANCE_WR(ctx, 0x1d10/4, 0x0436086c);
35855+ INSTANCE_WR(ctx, 0x1d14/4, 0x000c001b);
35856+ INSTANCE_WR(ctx, 0x1d1c/4, 0x10700ff9);
35857+ INSTANCE_WR(ctx, 0x1d20/4, 0x0436086c);
35858+ INSTANCE_WR(ctx, 0x1d24/4, 0x000c001b);
35859+ INSTANCE_WR(ctx, 0x1d2c/4, 0x10700ff9);
35860+ INSTANCE_WR(ctx, 0x1d30/4, 0x0436086c);
35861+ INSTANCE_WR(ctx, 0x1d34/4, 0x000c001b);
35862+ INSTANCE_WR(ctx, 0x1d3c/4, 0x10700ff9);
35863+ INSTANCE_WR(ctx, 0x1d40/4, 0x0436086c);
35864+ INSTANCE_WR(ctx, 0x1d44/4, 0x000c001b);
35865+ INSTANCE_WR(ctx, 0x1d4c/4, 0x10700ff9);
35866+ INSTANCE_WR(ctx, 0x1d50/4, 0x0436086c);
35867+ INSTANCE_WR(ctx, 0x1d54/4, 0x000c001b);
35868+ INSTANCE_WR(ctx, 0x1d5c/4, 0x10700ff9);
35869+ INSTANCE_WR(ctx, 0x1d60/4, 0x0436086c);
35870+ INSTANCE_WR(ctx, 0x1d64/4, 0x000c001b);
35871+ INSTANCE_WR(ctx, 0x1d6c/4, 0x10700ff9);
35872+ INSTANCE_WR(ctx, 0x1d70/4, 0x0436086c);
35873+ INSTANCE_WR(ctx, 0x1d74/4, 0x000c001b);
35874+ INSTANCE_WR(ctx, 0x1d7c/4, 0x10700ff9);
35875+ INSTANCE_WR(ctx, 0x1d80/4, 0x0436086c);
35876+ INSTANCE_WR(ctx, 0x1d84/4, 0x000c001b);
35877+ INSTANCE_WR(ctx, 0x1d8c/4, 0x10700ff9);
35878+ INSTANCE_WR(ctx, 0x1d90/4, 0x0436086c);
35879+ INSTANCE_WR(ctx, 0x1d94/4, 0x000c001b);
35880+ INSTANCE_WR(ctx, 0x1d9c/4, 0x10700ff9);
35881+ INSTANCE_WR(ctx, 0x1da0/4, 0x0436086c);
35882+ INSTANCE_WR(ctx, 0x1da4/4, 0x000c001b);
35883+ INSTANCE_WR(ctx, 0x1dac/4, 0x10700ff9);
35884+ INSTANCE_WR(ctx, 0x1db0/4, 0x0436086c);
35885+ INSTANCE_WR(ctx, 0x1db4/4, 0x000c001b);
35886+ INSTANCE_WR(ctx, 0x1dbc/4, 0x10700ff9);
35887+ INSTANCE_WR(ctx, 0x1dc0/4, 0x0436086c);
35888+ INSTANCE_WR(ctx, 0x1dc4/4, 0x000c001b);
35889+ INSTANCE_WR(ctx, 0x1dcc/4, 0x10700ff9);
35890+ INSTANCE_WR(ctx, 0x1dd0/4, 0x0436086c);
35891+ INSTANCE_WR(ctx, 0x1dd4/4, 0x000c001b);
35892+ INSTANCE_WR(ctx, 0x1ddc/4, 0x10700ff9);
35893+ INSTANCE_WR(ctx, 0x1de0/4, 0x0436086c);
35894+ INSTANCE_WR(ctx, 0x1de4/4, 0x000c001b);
35895+ INSTANCE_WR(ctx, 0x1dec/4, 0x10700ff9);
35896+ INSTANCE_WR(ctx, 0x1df0/4, 0x0436086c);
35897+ INSTANCE_WR(ctx, 0x1df4/4, 0x000c001b);
35898+ INSTANCE_WR(ctx, 0x1dfc/4, 0x10700ff9);
35899+ INSTANCE_WR(ctx, 0x1e00/4, 0x0436086c);
35900+ INSTANCE_WR(ctx, 0x1e04/4, 0x000c001b);
35901+ INSTANCE_WR(ctx, 0x1e0c/4, 0x10700ff9);
35902+ INSTANCE_WR(ctx, 0x1e10/4, 0x0436086c);
35903+ INSTANCE_WR(ctx, 0x1e14/4, 0x000c001b);
35904+ INSTANCE_WR(ctx, 0x1e1c/4, 0x10700ff9);
35905+ INSTANCE_WR(ctx, 0x1e20/4, 0x0436086c);
35906+ INSTANCE_WR(ctx, 0x1e24/4, 0x000c001b);
35907+ INSTANCE_WR(ctx, 0x1e2c/4, 0x10700ff9);
35908+ INSTANCE_WR(ctx, 0x1e30/4, 0x0436086c);
35909+ INSTANCE_WR(ctx, 0x1e34/4, 0x000c001b);
35910+ INSTANCE_WR(ctx, 0x1e3c/4, 0x10700ff9);
35911+ INSTANCE_WR(ctx, 0x1e40/4, 0x0436086c);
35912+ INSTANCE_WR(ctx, 0x1e44/4, 0x000c001b);
35913+ INSTANCE_WR(ctx, 0x1e4c/4, 0x10700ff9);
35914+ INSTANCE_WR(ctx, 0x1e50/4, 0x0436086c);
35915+ INSTANCE_WR(ctx, 0x1e54/4, 0x000c001b);
35916+ INSTANCE_WR(ctx, 0x1e5c/4, 0x10700ff9);
35917+ INSTANCE_WR(ctx, 0x1e60/4, 0x0436086c);
35918+ INSTANCE_WR(ctx, 0x1e64/4, 0x000c001b);
35919+ INSTANCE_WR(ctx, 0x1e6c/4, 0x10700ff9);
35920+ INSTANCE_WR(ctx, 0x1e70/4, 0x0436086c);
35921+ INSTANCE_WR(ctx, 0x1e74/4, 0x000c001b);
35922+ INSTANCE_WR(ctx, 0x1e7c/4, 0x10700ff9);
35923+ INSTANCE_WR(ctx, 0x1e80/4, 0x0436086c);
35924+ INSTANCE_WR(ctx, 0x1e84/4, 0x000c001b);
35925+ INSTANCE_WR(ctx, 0x1e8c/4, 0x10700ff9);
35926+ INSTANCE_WR(ctx, 0x1e90/4, 0x0436086c);
35927+ INSTANCE_WR(ctx, 0x1e94/4, 0x000c001b);
35928+ INSTANCE_WR(ctx, 0x1e9c/4, 0x10700ff9);
35929+ INSTANCE_WR(ctx, 0x1ea0/4, 0x0436086c);
35930+ INSTANCE_WR(ctx, 0x1ea4/4, 0x000c001b);
35931+ INSTANCE_WR(ctx, 0x1eac/4, 0x10700ff9);
35932+ INSTANCE_WR(ctx, 0x1eb0/4, 0x0436086c);
35933+ INSTANCE_WR(ctx, 0x1eb4/4, 0x000c001b);
35934+ INSTANCE_WR(ctx, 0x1ebc/4, 0x10700ff9);
35935+ INSTANCE_WR(ctx, 0x1ec0/4, 0x0436086c);
35936+ INSTANCE_WR(ctx, 0x1ec4/4, 0x000c001b);
35937+ INSTANCE_WR(ctx, 0x1ecc/4, 0x10700ff9);
35938+ INSTANCE_WR(ctx, 0x1ed0/4, 0x0436086c);
35939+ INSTANCE_WR(ctx, 0x1ed4/4, 0x000c001b);
35940+ INSTANCE_WR(ctx, 0x1edc/4, 0x10700ff9);
35941+ INSTANCE_WR(ctx, 0x1ee0/4, 0x0436086c);
35942+ INSTANCE_WR(ctx, 0x1ee4/4, 0x000c001b);
35943+ INSTANCE_WR(ctx, 0x1eec/4, 0x10700ff9);
35944+ INSTANCE_WR(ctx, 0x1ef0/4, 0x0436086c);
35945+ INSTANCE_WR(ctx, 0x1ef4/4, 0x000c001b);
35946+ INSTANCE_WR(ctx, 0x1efc/4, 0x10700ff9);
35947+ INSTANCE_WR(ctx, 0x1f00/4, 0x0436086c);
35948+ INSTANCE_WR(ctx, 0x1f04/4, 0x000c001b);
35949+ INSTANCE_WR(ctx, 0x1f0c/4, 0x10700ff9);
35950+ INSTANCE_WR(ctx, 0x1f10/4, 0x0436086c);
35951+ INSTANCE_WR(ctx, 0x1f14/4, 0x000c001b);
35952+ INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9);
35953+ INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c);
35954+ INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b);
35955+ INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9);
35956+ INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c);
35957+ INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b);
35958+ INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9);
35959+ INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c);
35960+ INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b);
35961+ INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9);
35962+ INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c);
35963+ INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b);
35964+ INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9);
35965+ INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c);
35966+ INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b);
35967+ INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9);
35968+ INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c);
35969+ INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b);
35970+ INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9);
35971+ INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c);
35972+ INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b);
35973+ INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9);
35974+ INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c);
35975+ INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b);
35976+ INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9);
35977+ INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c);
35978+ INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b);
35979+ INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9);
35980+ INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c);
35981+ INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b);
35982+ INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9);
35983+ INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c);
35984+ INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b);
35985+ INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9);
35986+ INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c);
35987+ INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b);
35988+ INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9);
35989+ INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c);
35990+ INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b);
35991+ INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9);
35992+ INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c);
35993+ INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b);
35994+ INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9);
35995+ INSTANCE_WR(ctx, 0x2000/4, 0x0436086c);
35996+ INSTANCE_WR(ctx, 0x2004/4, 0x000c001b);
35997+ INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9);
35998+ INSTANCE_WR(ctx, 0x2010/4, 0x0436086c);
35999+ INSTANCE_WR(ctx, 0x2014/4, 0x000c001b);
36000+ INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9);
36001+ INSTANCE_WR(ctx, 0x2020/4, 0x0436086c);
36002+ INSTANCE_WR(ctx, 0x2024/4, 0x000c001b);
36003+ INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9);
36004+ INSTANCE_WR(ctx, 0x2030/4, 0x0436086c);
36005+ INSTANCE_WR(ctx, 0x2034/4, 0x000c001b);
36006+ INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9);
36007+ INSTANCE_WR(ctx, 0x2040/4, 0x0436086c);
36008+ INSTANCE_WR(ctx, 0x2044/4, 0x000c001b);
36009+ INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9);
36010+ INSTANCE_WR(ctx, 0x2050/4, 0x0436086c);
36011+ INSTANCE_WR(ctx, 0x2054/4, 0x000c001b);
36012+ INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9);
36013+ INSTANCE_WR(ctx, 0x2060/4, 0x0436086c);
36014+ INSTANCE_WR(ctx, 0x2064/4, 0x000c001b);
36015+ INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9);
36016+ INSTANCE_WR(ctx, 0x2070/4, 0x0436086c);
36017+ INSTANCE_WR(ctx, 0x2074/4, 0x000c001b);
36018+ INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9);
36019+ INSTANCE_WR(ctx, 0x2080/4, 0x0436086c);
36020+ INSTANCE_WR(ctx, 0x2084/4, 0x000c001b);
36021+ INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9);
36022+ INSTANCE_WR(ctx, 0x2090/4, 0x0436086c);
36023+ INSTANCE_WR(ctx, 0x2094/4, 0x000c001b);
36024+ INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9);
36025+ INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c);
36026+ INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b);
36027+ INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9);
36028+ INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c);
36029+ INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b);
36030+ INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9);
36031+ INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c);
36032+ INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b);
36033+ INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9);
36034+ INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c);
36035+ INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b);
36036+ INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9);
36037+ INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c);
36038+ INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b);
36039+ INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9);
36040+ INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c);
36041+ INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b);
36042+ INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9);
36043+ INSTANCE_WR(ctx, 0x2100/4, 0x0436086c);
36044+ INSTANCE_WR(ctx, 0x2104/4, 0x000c001b);
36045+ INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9);
36046+ INSTANCE_WR(ctx, 0x2110/4, 0x0436086c);
36047+ INSTANCE_WR(ctx, 0x2114/4, 0x000c001b);
36048+ INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9);
36049+ INSTANCE_WR(ctx, 0x2120/4, 0x0436086c);
36050+ INSTANCE_WR(ctx, 0x2124/4, 0x000c001b);
36051+ INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9);
36052+ INSTANCE_WR(ctx, 0x2130/4, 0x0436086c);
36053+ INSTANCE_WR(ctx, 0x2134/4, 0x000c001b);
36054+ INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9);
36055+ INSTANCE_WR(ctx, 0x2140/4, 0x0436086c);
36056+ INSTANCE_WR(ctx, 0x2144/4, 0x000c001b);
36057+ INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9);
36058+ INSTANCE_WR(ctx, 0x2150/4, 0x0436086c);
36059+ INSTANCE_WR(ctx, 0x2154/4, 0x000c001b);
36060+ INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9);
36061+ INSTANCE_WR(ctx, 0x2160/4, 0x0436086c);
36062+ INSTANCE_WR(ctx, 0x2164/4, 0x000c001b);
36063+ INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9);
36064+ INSTANCE_WR(ctx, 0x2170/4, 0x0436086c);
36065+ INSTANCE_WR(ctx, 0x2174/4, 0x000c001b);
36066+ INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9);
36067+ INSTANCE_WR(ctx, 0x2180/4, 0x0436086c);
36068+ INSTANCE_WR(ctx, 0x2184/4, 0x000c001b);
36069+ INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9);
36070+ INSTANCE_WR(ctx, 0x2190/4, 0x0436086c);
36071+ INSTANCE_WR(ctx, 0x2194/4, 0x000c001b);
36072+ INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9);
36073+ INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c);
36074+ INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b);
36075+ INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9);
36076+ INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c);
36077+ INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b);
36078+ INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9);
36079+ INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c);
36080+ INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b);
36081+ INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9);
36082+ INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c);
36083+ INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b);
36084+ INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9);
36085+ INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c);
36086+ INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b);
36087+ INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9);
36088+ INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c);
36089+ INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b);
36090+ INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9);
36091+ INSTANCE_WR(ctx, 0x2200/4, 0x0436086c);
36092+ INSTANCE_WR(ctx, 0x2204/4, 0x000c001b);
36093+ INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9);
36094+ INSTANCE_WR(ctx, 0x2210/4, 0x0436086c);
36095+ INSTANCE_WR(ctx, 0x2214/4, 0x000c001b);
36096+ INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9);
36097+ INSTANCE_WR(ctx, 0x2220/4, 0x0436086c);
36098+ INSTANCE_WR(ctx, 0x2224/4, 0x000c001b);
36099+ INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9);
36100+ INSTANCE_WR(ctx, 0x2230/4, 0x0436086c);
36101+ INSTANCE_WR(ctx, 0x2234/4, 0x000c001b);
36102+ INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9);
36103+ INSTANCE_WR(ctx, 0x2240/4, 0x0436086c);
36104+ INSTANCE_WR(ctx, 0x2244/4, 0x000c001b);
36105+ INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9);
36106+ INSTANCE_WR(ctx, 0x2250/4, 0x0436086c);
36107+ INSTANCE_WR(ctx, 0x2254/4, 0x000c001b);
36108+ INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9);
36109+ INSTANCE_WR(ctx, 0x2260/4, 0x0436086c);
36110+ INSTANCE_WR(ctx, 0x2264/4, 0x000c001b);
36111+ INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9);
36112+ INSTANCE_WR(ctx, 0x2270/4, 0x0436086c);
36113+ INSTANCE_WR(ctx, 0x2274/4, 0x000c001b);
36114+ INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9);
36115+ INSTANCE_WR(ctx, 0x2280/4, 0x0436086c);
36116+ INSTANCE_WR(ctx, 0x2284/4, 0x000c001b);
36117+ INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9);
36118+ INSTANCE_WR(ctx, 0x2290/4, 0x0436086c);
36119+ INSTANCE_WR(ctx, 0x2294/4, 0x000c001b);
36120+ INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9);
36121+ INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c);
36122+ INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b);
36123+ INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9);
36124+ INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c);
36125+ INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b);
36126+ INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9);
36127+ INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c);
36128+ INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b);
36129+ INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9);
36130+ INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c);
36131+ INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b);
36132+ INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9);
36133+ INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c);
36134+ INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b);
36135+ INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9);
36136+ INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c);
36137+ INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b);
36138+ INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9);
36139+ INSTANCE_WR(ctx, 0x2300/4, 0x0436086c);
36140+ INSTANCE_WR(ctx, 0x2304/4, 0x000c001b);
36141+ INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9);
36142+ INSTANCE_WR(ctx, 0x2310/4, 0x0436086c);
36143+ INSTANCE_WR(ctx, 0x2314/4, 0x000c001b);
36144+ INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9);
36145+ INSTANCE_WR(ctx, 0x2320/4, 0x0436086c);
36146+ INSTANCE_WR(ctx, 0x2324/4, 0x000c001b);
36147+ INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9);
36148+ INSTANCE_WR(ctx, 0x2330/4, 0x0436086c);
36149+ INSTANCE_WR(ctx, 0x2334/4, 0x000c001b);
36150+ INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9);
36151+ INSTANCE_WR(ctx, 0x2340/4, 0x0436086c);
36152+ INSTANCE_WR(ctx, 0x2344/4, 0x000c001b);
36153+ INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9);
36154+ INSTANCE_WR(ctx, 0x2350/4, 0x0436086c);
36155+ INSTANCE_WR(ctx, 0x2354/4, 0x000c001b);
36156+ INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9);
36157+ INSTANCE_WR(ctx, 0x2360/4, 0x0436086c);
36158+ INSTANCE_WR(ctx, 0x2364/4, 0x000c001b);
36159+ INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9);
36160+ INSTANCE_WR(ctx, 0x2370/4, 0x0436086c);
36161+ INSTANCE_WR(ctx, 0x2374/4, 0x000c001b);
36162+ INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9);
36163+ INSTANCE_WR(ctx, 0x2380/4, 0x0436086c);
36164+ INSTANCE_WR(ctx, 0x2384/4, 0x000c001b);
36165+ INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9);
36166+ INSTANCE_WR(ctx, 0x2390/4, 0x0436086c);
36167+ INSTANCE_WR(ctx, 0x2394/4, 0x000c001b);
36168+ INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9);
36169+ INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c);
36170+ INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b);
36171+ INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9);
36172+ INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c);
36173+ INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b);
36174+ INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9);
36175+ INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c);
36176+ INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b);
36177+ INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9);
36178+ INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c);
36179+ INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b);
36180+ INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9);
36181+ INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c);
36182+ INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b);
36183+ INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9);
36184+ INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c);
36185+ INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b);
36186+ INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9);
36187+ INSTANCE_WR(ctx, 0x2400/4, 0x0436086c);
36188+ INSTANCE_WR(ctx, 0x2404/4, 0x000c001b);
36189+ INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9);
36190+ INSTANCE_WR(ctx, 0x2410/4, 0x0436086c);
36191+ INSTANCE_WR(ctx, 0x2414/4, 0x000c001b);
36192+ INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9);
36193+ INSTANCE_WR(ctx, 0x2420/4, 0x0436086c);
36194+ INSTANCE_WR(ctx, 0x2424/4, 0x000c001b);
36195+ INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9);
36196+ INSTANCE_WR(ctx, 0x2430/4, 0x0436086c);
36197+ INSTANCE_WR(ctx, 0x2434/4, 0x000c001b);
36198+ INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9);
36199+ INSTANCE_WR(ctx, 0x2440/4, 0x0436086c);
36200+ INSTANCE_WR(ctx, 0x2444/4, 0x000c001b);
36201+ INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9);
36202+ INSTANCE_WR(ctx, 0x2450/4, 0x0436086c);
36203+ INSTANCE_WR(ctx, 0x2454/4, 0x000c001b);
36204+ INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9);
36205+ INSTANCE_WR(ctx, 0x2460/4, 0x0436086c);
36206+ INSTANCE_WR(ctx, 0x2464/4, 0x000c001b);
36207+ INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9);
36208+ INSTANCE_WR(ctx, 0x2470/4, 0x0436086c);
36209+ INSTANCE_WR(ctx, 0x2474/4, 0x000c001b);
36210+ INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9);
36211+ INSTANCE_WR(ctx, 0x2480/4, 0x0436086c);
36212+ INSTANCE_WR(ctx, 0x2484/4, 0x000c001b);
36213+ INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9);
36214+ INSTANCE_WR(ctx, 0x2490/4, 0x0436086c);
36215+ INSTANCE_WR(ctx, 0x2494/4, 0x000c001b);
36216+ INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9);
36217+ INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c);
36218+ INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b);
36219+ INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9);
36220+ INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c);
36221+ INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b);
36222+ INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9);
36223+ INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c);
36224+ INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b);
36225+ INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9);
36226+ INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c);
36227+ INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b);
36228+ INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9);
36229+ INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c);
36230+ INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b);
36231+ INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9);
36232+ INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c);
36233+ INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b);
36234+ INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9);
36235+ INSTANCE_WR(ctx, 0x2500/4, 0x0436086c);
36236+ INSTANCE_WR(ctx, 0x2504/4, 0x000c001b);
36237+ INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9);
36238+ INSTANCE_WR(ctx, 0x2510/4, 0x0436086c);
36239+ INSTANCE_WR(ctx, 0x2514/4, 0x000c001b);
36240+ INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9);
36241+ INSTANCE_WR(ctx, 0x2520/4, 0x0436086c);
36242+ INSTANCE_WR(ctx, 0x2524/4, 0x000c001b);
36243+ INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9);
36244+ INSTANCE_WR(ctx, 0x2530/4, 0x0436086c);
36245+ INSTANCE_WR(ctx, 0x2534/4, 0x000c001b);
36246+ INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9);
36247+ INSTANCE_WR(ctx, 0x2540/4, 0x0436086c);
36248+ INSTANCE_WR(ctx, 0x2544/4, 0x000c001b);
36249+ INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9);
36250+ INSTANCE_WR(ctx, 0x2550/4, 0x0436086c);
36251+ INSTANCE_WR(ctx, 0x2554/4, 0x000c001b);
36252+ INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9);
36253+ INSTANCE_WR(ctx, 0x2560/4, 0x0436086c);
36254+ INSTANCE_WR(ctx, 0x2564/4, 0x000c001b);
36255+ INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9);
36256+ INSTANCE_WR(ctx, 0x2570/4, 0x0436086c);
36257+ INSTANCE_WR(ctx, 0x2574/4, 0x000c001b);
36258+ INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9);
36259+ INSTANCE_WR(ctx, 0x2580/4, 0x0436086c);
36260+ INSTANCE_WR(ctx, 0x2584/4, 0x000c001b);
36261+ INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9);
36262+ INSTANCE_WR(ctx, 0x2590/4, 0x0436086c);
36263+ INSTANCE_WR(ctx, 0x2594/4, 0x000c001b);
36264+ INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9);
36265+ INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c);
36266+ INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b);
36267+ INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9);
36268+ INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c);
36269+ INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b);
36270+ INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9);
36271+ INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c);
36272+ INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b);
36273+ INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9);
36274+ INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c);
36275+ INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b);
36276+ INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9);
36277+ INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c);
36278+ INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b);
36279+ INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9);
36280+ INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c);
36281+ INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b);
36282+ INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9);
36283+ INSTANCE_WR(ctx, 0x2600/4, 0x0436086c);
36284+ INSTANCE_WR(ctx, 0x2604/4, 0x000c001b);
36285+ INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9);
36286+ INSTANCE_WR(ctx, 0x2610/4, 0x0436086c);
36287+ INSTANCE_WR(ctx, 0x2614/4, 0x000c001b);
36288+ INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9);
36289+ INSTANCE_WR(ctx, 0x2620/4, 0x0436086c);
36290+ INSTANCE_WR(ctx, 0x2624/4, 0x000c001b);
36291+ INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9);
36292+ INSTANCE_WR(ctx, 0x2630/4, 0x0436086c);
36293+ INSTANCE_WR(ctx, 0x2634/4, 0x000c001b);
36294+ INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9);
36295+ INSTANCE_WR(ctx, 0x2640/4, 0x0436086c);
36296+ INSTANCE_WR(ctx, 0x2644/4, 0x000c001b);
36297+ INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9);
36298+ INSTANCE_WR(ctx, 0x2650/4, 0x0436086c);
36299+ INSTANCE_WR(ctx, 0x2654/4, 0x000c001b);
36300+ INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9);
36301+ INSTANCE_WR(ctx, 0x2660/4, 0x0436086c);
36302+ INSTANCE_WR(ctx, 0x2664/4, 0x000c001b);
36303+ INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9);
36304+ INSTANCE_WR(ctx, 0x2670/4, 0x0436086c);
36305+ INSTANCE_WR(ctx, 0x2674/4, 0x000c001b);
36306+ INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9);
36307+ INSTANCE_WR(ctx, 0x2680/4, 0x0436086c);
36308+ INSTANCE_WR(ctx, 0x2684/4, 0x000c001b);
36309+ INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9);
36310+ INSTANCE_WR(ctx, 0x2690/4, 0x0436086c);
36311+ INSTANCE_WR(ctx, 0x2694/4, 0x000c001b);
36312+ INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9);
36313+ INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c);
36314+ INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b);
36315+ INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9);
36316+ INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c);
36317+ INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b);
36318+ INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9);
36319+ INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c);
36320+ INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b);
36321+ INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9);
36322+ INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c);
36323+ INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b);
36324+ INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9);
36325+ INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c);
36326+ INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b);
36327+ INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9);
36328+ INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c);
36329+ INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b);
36330+ INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9);
36331+ INSTANCE_WR(ctx, 0x2700/4, 0x0436086c);
36332+ INSTANCE_WR(ctx, 0x2704/4, 0x000c001b);
36333+ INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9);
36334+ INSTANCE_WR(ctx, 0x2710/4, 0x0436086c);
36335+ INSTANCE_WR(ctx, 0x2714/4, 0x000c001b);
36336+ INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9);
36337+ INSTANCE_WR(ctx, 0x2720/4, 0x0436086c);
36338+ INSTANCE_WR(ctx, 0x2724/4, 0x000c001b);
36339+ for(i = 0x274c; i< 0x275c; i += 4)
36340+ INSTANCE_WR(ctx, i/4, 0x0000ffff);
36341+ INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000);
36342+ INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000);
36343+ INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000);
36344+ INSTANCE_WR(ctx, 0x2edc/4, 0x40000000);
36345+ INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000);
36346+ INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000);
36347+ INSTANCE_WR(ctx, 0x2eec/4, 0x40000000);
36348+ INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000);
36349+ INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000);
36350+ INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000);
36351+}
36352+
36353+static void nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
36354+{
36355+ struct drm_nouveau_private *dev_priv = dev->dev_private;
36356+ int i;
36357+
36358+ INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
36359+ INSTANCE_WR(ctx, 0x420/4, 0x00000111);
36360+ INSTANCE_WR(ctx, 0x424/4, 0x00000060);
36361+ INSTANCE_WR(ctx, 0x440/4, 0x00000080);
36362+ INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
36363+ INSTANCE_WR(ctx, 0x448/4, 0x00000001);
36364+ INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
36365+ INSTANCE_WR(ctx, 0x488/4, 0xffff0000);
36366+ for(i = 0x4dc; i< 0x4e4; i += 4)
36367+ INSTANCE_WR(ctx, i/4, 0x0fff0000);
36368+ INSTANCE_WR(ctx, 0x4e8/4, 0x00011100);
36369+ for(i = 0x504; i< 0x544; i += 4)
36370+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
36371+ INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff);
36372+ INSTANCE_WR(ctx, 0x588/4, 0x00000080);
36373+ INSTANCE_WR(ctx, 0x58c/4, 0x30201000);
36374+ INSTANCE_WR(ctx, 0x590/4, 0x70605040);
36375+ INSTANCE_WR(ctx, 0x594/4, 0xb8a89888);
36376+ INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8);
36377+ INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000);
36378+ for(i = 0x604; i< 0x644; i += 4)
36379+ INSTANCE_WR(ctx, i/4, 0x00010588);
36380+ for(i = 0x644; i< 0x684; i += 4)
36381+ INSTANCE_WR(ctx, i/4, 0x00030303);
36382+ for(i = 0x6c4; i< 0x704; i += 4)
36383+ INSTANCE_WR(ctx, i/4, 0x0008aae4);
36384+ for(i = 0x704; i< 0x744; i += 4)
36385+ INSTANCE_WR(ctx, i/4, 0x01012000);
36386+ for(i = 0x744; i< 0x784; i += 4)
36387+ INSTANCE_WR(ctx, i/4, 0x00080008);
36388+ INSTANCE_WR(ctx, 0x860/4, 0x00040000);
36389+ INSTANCE_WR(ctx, 0x864/4, 0x00010000);
36390+ for(i = 0x868; i< 0x878; i += 4)
36391+ INSTANCE_WR(ctx, i/4, 0x00040004);
36392+ INSTANCE_WR(ctx, 0x1f1c/4, 0x10700ff9);
36393+ INSTANCE_WR(ctx, 0x1f20/4, 0x0436086c);
36394+ INSTANCE_WR(ctx, 0x1f24/4, 0x000c001b);
36395+ INSTANCE_WR(ctx, 0x1f2c/4, 0x10700ff9);
36396+ INSTANCE_WR(ctx, 0x1f30/4, 0x0436086c);
36397+ INSTANCE_WR(ctx, 0x1f34/4, 0x000c001b);
36398+ INSTANCE_WR(ctx, 0x1f3c/4, 0x10700ff9);
36399+ INSTANCE_WR(ctx, 0x1f40/4, 0x0436086c);
36400+ INSTANCE_WR(ctx, 0x1f44/4, 0x000c001b);
36401+ INSTANCE_WR(ctx, 0x1f4c/4, 0x10700ff9);
36402+ INSTANCE_WR(ctx, 0x1f50/4, 0x0436086c);
36403+ INSTANCE_WR(ctx, 0x1f54/4, 0x000c001b);
36404+ INSTANCE_WR(ctx, 0x1f5c/4, 0x10700ff9);
36405+ INSTANCE_WR(ctx, 0x1f60/4, 0x0436086c);
36406+ INSTANCE_WR(ctx, 0x1f64/4, 0x000c001b);
36407+ INSTANCE_WR(ctx, 0x1f6c/4, 0x10700ff9);
36408+ INSTANCE_WR(ctx, 0x1f70/4, 0x0436086c);
36409+ INSTANCE_WR(ctx, 0x1f74/4, 0x000c001b);
36410+ INSTANCE_WR(ctx, 0x1f7c/4, 0x10700ff9);
36411+ INSTANCE_WR(ctx, 0x1f80/4, 0x0436086c);
36412+ INSTANCE_WR(ctx, 0x1f84/4, 0x000c001b);
36413+ INSTANCE_WR(ctx, 0x1f8c/4, 0x10700ff9);
36414+ INSTANCE_WR(ctx, 0x1f90/4, 0x0436086c);
36415+ INSTANCE_WR(ctx, 0x1f94/4, 0x000c001b);
36416+ INSTANCE_WR(ctx, 0x1f9c/4, 0x10700ff9);
36417+ INSTANCE_WR(ctx, 0x1fa0/4, 0x0436086c);
36418+ INSTANCE_WR(ctx, 0x1fa4/4, 0x000c001b);
36419+ INSTANCE_WR(ctx, 0x1fac/4, 0x10700ff9);
36420+ INSTANCE_WR(ctx, 0x1fb0/4, 0x0436086c);
36421+ INSTANCE_WR(ctx, 0x1fb4/4, 0x000c001b);
36422+ INSTANCE_WR(ctx, 0x1fbc/4, 0x10700ff9);
36423+ INSTANCE_WR(ctx, 0x1fc0/4, 0x0436086c);
36424+ INSTANCE_WR(ctx, 0x1fc4/4, 0x000c001b);
36425+ INSTANCE_WR(ctx, 0x1fcc/4, 0x10700ff9);
36426+ INSTANCE_WR(ctx, 0x1fd0/4, 0x0436086c);
36427+ INSTANCE_WR(ctx, 0x1fd4/4, 0x000c001b);
36428+ INSTANCE_WR(ctx, 0x1fdc/4, 0x10700ff9);
36429+ INSTANCE_WR(ctx, 0x1fe0/4, 0x0436086c);
36430+ INSTANCE_WR(ctx, 0x1fe4/4, 0x000c001b);
36431+ INSTANCE_WR(ctx, 0x1fec/4, 0x10700ff9);
36432+ INSTANCE_WR(ctx, 0x1ff0/4, 0x0436086c);
36433+ INSTANCE_WR(ctx, 0x1ff4/4, 0x000c001b);
36434+ INSTANCE_WR(ctx, 0x1ffc/4, 0x10700ff9);
36435+ INSTANCE_WR(ctx, 0x2000/4, 0x0436086c);
36436+ INSTANCE_WR(ctx, 0x2004/4, 0x000c001b);
36437+ INSTANCE_WR(ctx, 0x200c/4, 0x10700ff9);
36438+ INSTANCE_WR(ctx, 0x2010/4, 0x0436086c);
36439+ INSTANCE_WR(ctx, 0x2014/4, 0x000c001b);
36440+ INSTANCE_WR(ctx, 0x201c/4, 0x10700ff9);
36441+ INSTANCE_WR(ctx, 0x2020/4, 0x0436086c);
36442+ INSTANCE_WR(ctx, 0x2024/4, 0x000c001b);
36443+ INSTANCE_WR(ctx, 0x202c/4, 0x10700ff9);
36444+ INSTANCE_WR(ctx, 0x2030/4, 0x0436086c);
36445+ INSTANCE_WR(ctx, 0x2034/4, 0x000c001b);
36446+ INSTANCE_WR(ctx, 0x203c/4, 0x10700ff9);
36447+ INSTANCE_WR(ctx, 0x2040/4, 0x0436086c);
36448+ INSTANCE_WR(ctx, 0x2044/4, 0x000c001b);
36449+ INSTANCE_WR(ctx, 0x204c/4, 0x10700ff9);
36450+ INSTANCE_WR(ctx, 0x2050/4, 0x0436086c);
36451+ INSTANCE_WR(ctx, 0x2054/4, 0x000c001b);
36452+ INSTANCE_WR(ctx, 0x205c/4, 0x10700ff9);
36453+ INSTANCE_WR(ctx, 0x2060/4, 0x0436086c);
36454+ INSTANCE_WR(ctx, 0x2064/4, 0x000c001b);
36455+ INSTANCE_WR(ctx, 0x206c/4, 0x10700ff9);
36456+ INSTANCE_WR(ctx, 0x2070/4, 0x0436086c);
36457+ INSTANCE_WR(ctx, 0x2074/4, 0x000c001b);
36458+ INSTANCE_WR(ctx, 0x207c/4, 0x10700ff9);
36459+ INSTANCE_WR(ctx, 0x2080/4, 0x0436086c);
36460+ INSTANCE_WR(ctx, 0x2084/4, 0x000c001b);
36461+ INSTANCE_WR(ctx, 0x208c/4, 0x10700ff9);
36462+ INSTANCE_WR(ctx, 0x2090/4, 0x0436086c);
36463+ INSTANCE_WR(ctx, 0x2094/4, 0x000c001b);
36464+ INSTANCE_WR(ctx, 0x209c/4, 0x10700ff9);
36465+ INSTANCE_WR(ctx, 0x20a0/4, 0x0436086c);
36466+ INSTANCE_WR(ctx, 0x20a4/4, 0x000c001b);
36467+ INSTANCE_WR(ctx, 0x20ac/4, 0x10700ff9);
36468+ INSTANCE_WR(ctx, 0x20b0/4, 0x0436086c);
36469+ INSTANCE_WR(ctx, 0x20b4/4, 0x000c001b);
36470+ INSTANCE_WR(ctx, 0x20bc/4, 0x10700ff9);
36471+ INSTANCE_WR(ctx, 0x20c0/4, 0x0436086c);
36472+ INSTANCE_WR(ctx, 0x20c4/4, 0x000c001b);
36473+ INSTANCE_WR(ctx, 0x20cc/4, 0x10700ff9);
36474+ INSTANCE_WR(ctx, 0x20d0/4, 0x0436086c);
36475+ INSTANCE_WR(ctx, 0x20d4/4, 0x000c001b);
36476+ INSTANCE_WR(ctx, 0x20dc/4, 0x10700ff9);
36477+ INSTANCE_WR(ctx, 0x20e0/4, 0x0436086c);
36478+ INSTANCE_WR(ctx, 0x20e4/4, 0x000c001b);
36479+ INSTANCE_WR(ctx, 0x20ec/4, 0x10700ff9);
36480+ INSTANCE_WR(ctx, 0x20f0/4, 0x0436086c);
36481+ INSTANCE_WR(ctx, 0x20f4/4, 0x000c001b);
36482+ INSTANCE_WR(ctx, 0x20fc/4, 0x10700ff9);
36483+ INSTANCE_WR(ctx, 0x2100/4, 0x0436086c);
36484+ INSTANCE_WR(ctx, 0x2104/4, 0x000c001b);
36485+ INSTANCE_WR(ctx, 0x210c/4, 0x10700ff9);
36486+ INSTANCE_WR(ctx, 0x2110/4, 0x0436086c);
36487+ INSTANCE_WR(ctx, 0x2114/4, 0x000c001b);
36488+ INSTANCE_WR(ctx, 0x211c/4, 0x10700ff9);
36489+ INSTANCE_WR(ctx, 0x2120/4, 0x0436086c);
36490+ INSTANCE_WR(ctx, 0x2124/4, 0x000c001b);
36491+ INSTANCE_WR(ctx, 0x212c/4, 0x10700ff9);
36492+ INSTANCE_WR(ctx, 0x2130/4, 0x0436086c);
36493+ INSTANCE_WR(ctx, 0x2134/4, 0x000c001b);
36494+ INSTANCE_WR(ctx, 0x213c/4, 0x10700ff9);
36495+ INSTANCE_WR(ctx, 0x2140/4, 0x0436086c);
36496+ INSTANCE_WR(ctx, 0x2144/4, 0x000c001b);
36497+ INSTANCE_WR(ctx, 0x214c/4, 0x10700ff9);
36498+ INSTANCE_WR(ctx, 0x2150/4, 0x0436086c);
36499+ INSTANCE_WR(ctx, 0x2154/4, 0x000c001b);
36500+ INSTANCE_WR(ctx, 0x215c/4, 0x10700ff9);
36501+ INSTANCE_WR(ctx, 0x2160/4, 0x0436086c);
36502+ INSTANCE_WR(ctx, 0x2164/4, 0x000c001b);
36503+ INSTANCE_WR(ctx, 0x216c/4, 0x10700ff9);
36504+ INSTANCE_WR(ctx, 0x2170/4, 0x0436086c);
36505+ INSTANCE_WR(ctx, 0x2174/4, 0x000c001b);
36506+ INSTANCE_WR(ctx, 0x217c/4, 0x10700ff9);
36507+ INSTANCE_WR(ctx, 0x2180/4, 0x0436086c);
36508+ INSTANCE_WR(ctx, 0x2184/4, 0x000c001b);
36509+ INSTANCE_WR(ctx, 0x218c/4, 0x10700ff9);
36510+ INSTANCE_WR(ctx, 0x2190/4, 0x0436086c);
36511+ INSTANCE_WR(ctx, 0x2194/4, 0x000c001b);
36512+ INSTANCE_WR(ctx, 0x219c/4, 0x10700ff9);
36513+ INSTANCE_WR(ctx, 0x21a0/4, 0x0436086c);
36514+ INSTANCE_WR(ctx, 0x21a4/4, 0x000c001b);
36515+ INSTANCE_WR(ctx, 0x21ac/4, 0x10700ff9);
36516+ INSTANCE_WR(ctx, 0x21b0/4, 0x0436086c);
36517+ INSTANCE_WR(ctx, 0x21b4/4, 0x000c001b);
36518+ INSTANCE_WR(ctx, 0x21bc/4, 0x10700ff9);
36519+ INSTANCE_WR(ctx, 0x21c0/4, 0x0436086c);
36520+ INSTANCE_WR(ctx, 0x21c4/4, 0x000c001b);
36521+ INSTANCE_WR(ctx, 0x21cc/4, 0x10700ff9);
36522+ INSTANCE_WR(ctx, 0x21d0/4, 0x0436086c);
36523+ INSTANCE_WR(ctx, 0x21d4/4, 0x000c001b);
36524+ INSTANCE_WR(ctx, 0x21dc/4, 0x10700ff9);
36525+ INSTANCE_WR(ctx, 0x21e0/4, 0x0436086c);
36526+ INSTANCE_WR(ctx, 0x21e4/4, 0x000c001b);
36527+ INSTANCE_WR(ctx, 0x21ec/4, 0x10700ff9);
36528+ INSTANCE_WR(ctx, 0x21f0/4, 0x0436086c);
36529+ INSTANCE_WR(ctx, 0x21f4/4, 0x000c001b);
36530+ INSTANCE_WR(ctx, 0x21fc/4, 0x10700ff9);
36531+ INSTANCE_WR(ctx, 0x2200/4, 0x0436086c);
36532+ INSTANCE_WR(ctx, 0x2204/4, 0x000c001b);
36533+ INSTANCE_WR(ctx, 0x220c/4, 0x10700ff9);
36534+ INSTANCE_WR(ctx, 0x2210/4, 0x0436086c);
36535+ INSTANCE_WR(ctx, 0x2214/4, 0x000c001b);
36536+ INSTANCE_WR(ctx, 0x221c/4, 0x10700ff9);
36537+ INSTANCE_WR(ctx, 0x2220/4, 0x0436086c);
36538+ INSTANCE_WR(ctx, 0x2224/4, 0x000c001b);
36539+ INSTANCE_WR(ctx, 0x222c/4, 0x10700ff9);
36540+ INSTANCE_WR(ctx, 0x2230/4, 0x0436086c);
36541+ INSTANCE_WR(ctx, 0x2234/4, 0x000c001b);
36542+ INSTANCE_WR(ctx, 0x223c/4, 0x10700ff9);
36543+ INSTANCE_WR(ctx, 0x2240/4, 0x0436086c);
36544+ INSTANCE_WR(ctx, 0x2244/4, 0x000c001b);
36545+ INSTANCE_WR(ctx, 0x224c/4, 0x10700ff9);
36546+ INSTANCE_WR(ctx, 0x2250/4, 0x0436086c);
36547+ INSTANCE_WR(ctx, 0x2254/4, 0x000c001b);
36548+ INSTANCE_WR(ctx, 0x225c/4, 0x10700ff9);
36549+ INSTANCE_WR(ctx, 0x2260/4, 0x0436086c);
36550+ INSTANCE_WR(ctx, 0x2264/4, 0x000c001b);
36551+ INSTANCE_WR(ctx, 0x226c/4, 0x10700ff9);
36552+ INSTANCE_WR(ctx, 0x2270/4, 0x0436086c);
36553+ INSTANCE_WR(ctx, 0x2274/4, 0x000c001b);
36554+ INSTANCE_WR(ctx, 0x227c/4, 0x10700ff9);
36555+ INSTANCE_WR(ctx, 0x2280/4, 0x0436086c);
36556+ INSTANCE_WR(ctx, 0x2284/4, 0x000c001b);
36557+ INSTANCE_WR(ctx, 0x228c/4, 0x10700ff9);
36558+ INSTANCE_WR(ctx, 0x2290/4, 0x0436086c);
36559+ INSTANCE_WR(ctx, 0x2294/4, 0x000c001b);
36560+ INSTANCE_WR(ctx, 0x229c/4, 0x10700ff9);
36561+ INSTANCE_WR(ctx, 0x22a0/4, 0x0436086c);
36562+ INSTANCE_WR(ctx, 0x22a4/4, 0x000c001b);
36563+ INSTANCE_WR(ctx, 0x22ac/4, 0x10700ff9);
36564+ INSTANCE_WR(ctx, 0x22b0/4, 0x0436086c);
36565+ INSTANCE_WR(ctx, 0x22b4/4, 0x000c001b);
36566+ INSTANCE_WR(ctx, 0x22bc/4, 0x10700ff9);
36567+ INSTANCE_WR(ctx, 0x22c0/4, 0x0436086c);
36568+ INSTANCE_WR(ctx, 0x22c4/4, 0x000c001b);
36569+ INSTANCE_WR(ctx, 0x22cc/4, 0x10700ff9);
36570+ INSTANCE_WR(ctx, 0x22d0/4, 0x0436086c);
36571+ INSTANCE_WR(ctx, 0x22d4/4, 0x000c001b);
36572+ INSTANCE_WR(ctx, 0x22dc/4, 0x10700ff9);
36573+ INSTANCE_WR(ctx, 0x22e0/4, 0x0436086c);
36574+ INSTANCE_WR(ctx, 0x22e4/4, 0x000c001b);
36575+ INSTANCE_WR(ctx, 0x22ec/4, 0x10700ff9);
36576+ INSTANCE_WR(ctx, 0x22f0/4, 0x0436086c);
36577+ INSTANCE_WR(ctx, 0x22f4/4, 0x000c001b);
36578+ INSTANCE_WR(ctx, 0x22fc/4, 0x10700ff9);
36579+ INSTANCE_WR(ctx, 0x2300/4, 0x0436086c);
36580+ INSTANCE_WR(ctx, 0x2304/4, 0x000c001b);
36581+ INSTANCE_WR(ctx, 0x230c/4, 0x10700ff9);
36582+ INSTANCE_WR(ctx, 0x2310/4, 0x0436086c);
36583+ INSTANCE_WR(ctx, 0x2314/4, 0x000c001b);
36584+ INSTANCE_WR(ctx, 0x231c/4, 0x10700ff9);
36585+ INSTANCE_WR(ctx, 0x2320/4, 0x0436086c);
36586+ INSTANCE_WR(ctx, 0x2324/4, 0x000c001b);
36587+ INSTANCE_WR(ctx, 0x232c/4, 0x10700ff9);
36588+ INSTANCE_WR(ctx, 0x2330/4, 0x0436086c);
36589+ INSTANCE_WR(ctx, 0x2334/4, 0x000c001b);
36590+ INSTANCE_WR(ctx, 0x233c/4, 0x10700ff9);
36591+ INSTANCE_WR(ctx, 0x2340/4, 0x0436086c);
36592+ INSTANCE_WR(ctx, 0x2344/4, 0x000c001b);
36593+ INSTANCE_WR(ctx, 0x234c/4, 0x10700ff9);
36594+ INSTANCE_WR(ctx, 0x2350/4, 0x0436086c);
36595+ INSTANCE_WR(ctx, 0x2354/4, 0x000c001b);
36596+ INSTANCE_WR(ctx, 0x235c/4, 0x10700ff9);
36597+ INSTANCE_WR(ctx, 0x2360/4, 0x0436086c);
36598+ INSTANCE_WR(ctx, 0x2364/4, 0x000c001b);
36599+ INSTANCE_WR(ctx, 0x236c/4, 0x10700ff9);
36600+ INSTANCE_WR(ctx, 0x2370/4, 0x0436086c);
36601+ INSTANCE_WR(ctx, 0x2374/4, 0x000c001b);
36602+ INSTANCE_WR(ctx, 0x237c/4, 0x10700ff9);
36603+ INSTANCE_WR(ctx, 0x2380/4, 0x0436086c);
36604+ INSTANCE_WR(ctx, 0x2384/4, 0x000c001b);
36605+ INSTANCE_WR(ctx, 0x238c/4, 0x10700ff9);
36606+ INSTANCE_WR(ctx, 0x2390/4, 0x0436086c);
36607+ INSTANCE_WR(ctx, 0x2394/4, 0x000c001b);
36608+ INSTANCE_WR(ctx, 0x239c/4, 0x10700ff9);
36609+ INSTANCE_WR(ctx, 0x23a0/4, 0x0436086c);
36610+ INSTANCE_WR(ctx, 0x23a4/4, 0x000c001b);
36611+ INSTANCE_WR(ctx, 0x23ac/4, 0x10700ff9);
36612+ INSTANCE_WR(ctx, 0x23b0/4, 0x0436086c);
36613+ INSTANCE_WR(ctx, 0x23b4/4, 0x000c001b);
36614+ INSTANCE_WR(ctx, 0x23bc/4, 0x10700ff9);
36615+ INSTANCE_WR(ctx, 0x23c0/4, 0x0436086c);
36616+ INSTANCE_WR(ctx, 0x23c4/4, 0x000c001b);
36617+ INSTANCE_WR(ctx, 0x23cc/4, 0x10700ff9);
36618+ INSTANCE_WR(ctx, 0x23d0/4, 0x0436086c);
36619+ INSTANCE_WR(ctx, 0x23d4/4, 0x000c001b);
36620+ INSTANCE_WR(ctx, 0x23dc/4, 0x10700ff9);
36621+ INSTANCE_WR(ctx, 0x23e0/4, 0x0436086c);
36622+ INSTANCE_WR(ctx, 0x23e4/4, 0x000c001b);
36623+ INSTANCE_WR(ctx, 0x23ec/4, 0x10700ff9);
36624+ INSTANCE_WR(ctx, 0x23f0/4, 0x0436086c);
36625+ INSTANCE_WR(ctx, 0x23f4/4, 0x000c001b);
36626+ INSTANCE_WR(ctx, 0x23fc/4, 0x10700ff9);
36627+ INSTANCE_WR(ctx, 0x2400/4, 0x0436086c);
36628+ INSTANCE_WR(ctx, 0x2404/4, 0x000c001b);
36629+ INSTANCE_WR(ctx, 0x240c/4, 0x10700ff9);
36630+ INSTANCE_WR(ctx, 0x2410/4, 0x0436086c);
36631+ INSTANCE_WR(ctx, 0x2414/4, 0x000c001b);
36632+ INSTANCE_WR(ctx, 0x241c/4, 0x10700ff9);
36633+ INSTANCE_WR(ctx, 0x2420/4, 0x0436086c);
36634+ INSTANCE_WR(ctx, 0x2424/4, 0x000c001b);
36635+ INSTANCE_WR(ctx, 0x242c/4, 0x10700ff9);
36636+ INSTANCE_WR(ctx, 0x2430/4, 0x0436086c);
36637+ INSTANCE_WR(ctx, 0x2434/4, 0x000c001b);
36638+ INSTANCE_WR(ctx, 0x243c/4, 0x10700ff9);
36639+ INSTANCE_WR(ctx, 0x2440/4, 0x0436086c);
36640+ INSTANCE_WR(ctx, 0x2444/4, 0x000c001b);
36641+ INSTANCE_WR(ctx, 0x244c/4, 0x10700ff9);
36642+ INSTANCE_WR(ctx, 0x2450/4, 0x0436086c);
36643+ INSTANCE_WR(ctx, 0x2454/4, 0x000c001b);
36644+ INSTANCE_WR(ctx, 0x245c/4, 0x10700ff9);
36645+ INSTANCE_WR(ctx, 0x2460/4, 0x0436086c);
36646+ INSTANCE_WR(ctx, 0x2464/4, 0x000c001b);
36647+ INSTANCE_WR(ctx, 0x246c/4, 0x10700ff9);
36648+ INSTANCE_WR(ctx, 0x2470/4, 0x0436086c);
36649+ INSTANCE_WR(ctx, 0x2474/4, 0x000c001b);
36650+ INSTANCE_WR(ctx, 0x247c/4, 0x10700ff9);
36651+ INSTANCE_WR(ctx, 0x2480/4, 0x0436086c);
36652+ INSTANCE_WR(ctx, 0x2484/4, 0x000c001b);
36653+ INSTANCE_WR(ctx, 0x248c/4, 0x10700ff9);
36654+ INSTANCE_WR(ctx, 0x2490/4, 0x0436086c);
36655+ INSTANCE_WR(ctx, 0x2494/4, 0x000c001b);
36656+ INSTANCE_WR(ctx, 0x249c/4, 0x10700ff9);
36657+ INSTANCE_WR(ctx, 0x24a0/4, 0x0436086c);
36658+ INSTANCE_WR(ctx, 0x24a4/4, 0x000c001b);
36659+ INSTANCE_WR(ctx, 0x24ac/4, 0x10700ff9);
36660+ INSTANCE_WR(ctx, 0x24b0/4, 0x0436086c);
36661+ INSTANCE_WR(ctx, 0x24b4/4, 0x000c001b);
36662+ INSTANCE_WR(ctx, 0x24bc/4, 0x10700ff9);
36663+ INSTANCE_WR(ctx, 0x24c0/4, 0x0436086c);
36664+ INSTANCE_WR(ctx, 0x24c4/4, 0x000c001b);
36665+ INSTANCE_WR(ctx, 0x24cc/4, 0x10700ff9);
36666+ INSTANCE_WR(ctx, 0x24d0/4, 0x0436086c);
36667+ INSTANCE_WR(ctx, 0x24d4/4, 0x000c001b);
36668+ INSTANCE_WR(ctx, 0x24dc/4, 0x10700ff9);
36669+ INSTANCE_WR(ctx, 0x24e0/4, 0x0436086c);
36670+ INSTANCE_WR(ctx, 0x24e4/4, 0x000c001b);
36671+ INSTANCE_WR(ctx, 0x24ec/4, 0x10700ff9);
36672+ INSTANCE_WR(ctx, 0x24f0/4, 0x0436086c);
36673+ INSTANCE_WR(ctx, 0x24f4/4, 0x000c001b);
36674+ INSTANCE_WR(ctx, 0x24fc/4, 0x10700ff9);
36675+ INSTANCE_WR(ctx, 0x2500/4, 0x0436086c);
36676+ INSTANCE_WR(ctx, 0x2504/4, 0x000c001b);
36677+ INSTANCE_WR(ctx, 0x250c/4, 0x10700ff9);
36678+ INSTANCE_WR(ctx, 0x2510/4, 0x0436086c);
36679+ INSTANCE_WR(ctx, 0x2514/4, 0x000c001b);
36680+ INSTANCE_WR(ctx, 0x251c/4, 0x10700ff9);
36681+ INSTANCE_WR(ctx, 0x2520/4, 0x0436086c);
36682+ INSTANCE_WR(ctx, 0x2524/4, 0x000c001b);
36683+ INSTANCE_WR(ctx, 0x252c/4, 0x10700ff9);
36684+ INSTANCE_WR(ctx, 0x2530/4, 0x0436086c);
36685+ INSTANCE_WR(ctx, 0x2534/4, 0x000c001b);
36686+ INSTANCE_WR(ctx, 0x253c/4, 0x10700ff9);
36687+ INSTANCE_WR(ctx, 0x2540/4, 0x0436086c);
36688+ INSTANCE_WR(ctx, 0x2544/4, 0x000c001b);
36689+ INSTANCE_WR(ctx, 0x254c/4, 0x10700ff9);
36690+ INSTANCE_WR(ctx, 0x2550/4, 0x0436086c);
36691+ INSTANCE_WR(ctx, 0x2554/4, 0x000c001b);
36692+ INSTANCE_WR(ctx, 0x255c/4, 0x10700ff9);
36693+ INSTANCE_WR(ctx, 0x2560/4, 0x0436086c);
36694+ INSTANCE_WR(ctx, 0x2564/4, 0x000c001b);
36695+ INSTANCE_WR(ctx, 0x256c/4, 0x10700ff9);
36696+ INSTANCE_WR(ctx, 0x2570/4, 0x0436086c);
36697+ INSTANCE_WR(ctx, 0x2574/4, 0x000c001b);
36698+ INSTANCE_WR(ctx, 0x257c/4, 0x10700ff9);
36699+ INSTANCE_WR(ctx, 0x2580/4, 0x0436086c);
36700+ INSTANCE_WR(ctx, 0x2584/4, 0x000c001b);
36701+ INSTANCE_WR(ctx, 0x258c/4, 0x10700ff9);
36702+ INSTANCE_WR(ctx, 0x2590/4, 0x0436086c);
36703+ INSTANCE_WR(ctx, 0x2594/4, 0x000c001b);
36704+ INSTANCE_WR(ctx, 0x259c/4, 0x10700ff9);
36705+ INSTANCE_WR(ctx, 0x25a0/4, 0x0436086c);
36706+ INSTANCE_WR(ctx, 0x25a4/4, 0x000c001b);
36707+ INSTANCE_WR(ctx, 0x25ac/4, 0x10700ff9);
36708+ INSTANCE_WR(ctx, 0x25b0/4, 0x0436086c);
36709+ INSTANCE_WR(ctx, 0x25b4/4, 0x000c001b);
36710+ INSTANCE_WR(ctx, 0x25bc/4, 0x10700ff9);
36711+ INSTANCE_WR(ctx, 0x25c0/4, 0x0436086c);
36712+ INSTANCE_WR(ctx, 0x25c4/4, 0x000c001b);
36713+ INSTANCE_WR(ctx, 0x25cc/4, 0x10700ff9);
36714+ INSTANCE_WR(ctx, 0x25d0/4, 0x0436086c);
36715+ INSTANCE_WR(ctx, 0x25d4/4, 0x000c001b);
36716+ INSTANCE_WR(ctx, 0x25dc/4, 0x10700ff9);
36717+ INSTANCE_WR(ctx, 0x25e0/4, 0x0436086c);
36718+ INSTANCE_WR(ctx, 0x25e4/4, 0x000c001b);
36719+ INSTANCE_WR(ctx, 0x25ec/4, 0x10700ff9);
36720+ INSTANCE_WR(ctx, 0x25f0/4, 0x0436086c);
36721+ INSTANCE_WR(ctx, 0x25f4/4, 0x000c001b);
36722+ INSTANCE_WR(ctx, 0x25fc/4, 0x10700ff9);
36723+ INSTANCE_WR(ctx, 0x2600/4, 0x0436086c);
36724+ INSTANCE_WR(ctx, 0x2604/4, 0x000c001b);
36725+ INSTANCE_WR(ctx, 0x260c/4, 0x10700ff9);
36726+ INSTANCE_WR(ctx, 0x2610/4, 0x0436086c);
36727+ INSTANCE_WR(ctx, 0x2614/4, 0x000c001b);
36728+ INSTANCE_WR(ctx, 0x261c/4, 0x10700ff9);
36729+ INSTANCE_WR(ctx, 0x2620/4, 0x0436086c);
36730+ INSTANCE_WR(ctx, 0x2624/4, 0x000c001b);
36731+ INSTANCE_WR(ctx, 0x262c/4, 0x10700ff9);
36732+ INSTANCE_WR(ctx, 0x2630/4, 0x0436086c);
36733+ INSTANCE_WR(ctx, 0x2634/4, 0x000c001b);
36734+ INSTANCE_WR(ctx, 0x263c/4, 0x10700ff9);
36735+ INSTANCE_WR(ctx, 0x2640/4, 0x0436086c);
36736+ INSTANCE_WR(ctx, 0x2644/4, 0x000c001b);
36737+ INSTANCE_WR(ctx, 0x264c/4, 0x10700ff9);
36738+ INSTANCE_WR(ctx, 0x2650/4, 0x0436086c);
36739+ INSTANCE_WR(ctx, 0x2654/4, 0x000c001b);
36740+ INSTANCE_WR(ctx, 0x265c/4, 0x10700ff9);
36741+ INSTANCE_WR(ctx, 0x2660/4, 0x0436086c);
36742+ INSTANCE_WR(ctx, 0x2664/4, 0x000c001b);
36743+ INSTANCE_WR(ctx, 0x266c/4, 0x10700ff9);
36744+ INSTANCE_WR(ctx, 0x2670/4, 0x0436086c);
36745+ INSTANCE_WR(ctx, 0x2674/4, 0x000c001b);
36746+ INSTANCE_WR(ctx, 0x267c/4, 0x10700ff9);
36747+ INSTANCE_WR(ctx, 0x2680/4, 0x0436086c);
36748+ INSTANCE_WR(ctx, 0x2684/4, 0x000c001b);
36749+ INSTANCE_WR(ctx, 0x268c/4, 0x10700ff9);
36750+ INSTANCE_WR(ctx, 0x2690/4, 0x0436086c);
36751+ INSTANCE_WR(ctx, 0x2694/4, 0x000c001b);
36752+ INSTANCE_WR(ctx, 0x269c/4, 0x10700ff9);
36753+ INSTANCE_WR(ctx, 0x26a0/4, 0x0436086c);
36754+ INSTANCE_WR(ctx, 0x26a4/4, 0x000c001b);
36755+ INSTANCE_WR(ctx, 0x26ac/4, 0x10700ff9);
36756+ INSTANCE_WR(ctx, 0x26b0/4, 0x0436086c);
36757+ INSTANCE_WR(ctx, 0x26b4/4, 0x000c001b);
36758+ INSTANCE_WR(ctx, 0x26bc/4, 0x10700ff9);
36759+ INSTANCE_WR(ctx, 0x26c0/4, 0x0436086c);
36760+ INSTANCE_WR(ctx, 0x26c4/4, 0x000c001b);
36761+ INSTANCE_WR(ctx, 0x26cc/4, 0x10700ff9);
36762+ INSTANCE_WR(ctx, 0x26d0/4, 0x0436086c);
36763+ INSTANCE_WR(ctx, 0x26d4/4, 0x000c001b);
36764+ INSTANCE_WR(ctx, 0x26dc/4, 0x10700ff9);
36765+ INSTANCE_WR(ctx, 0x26e0/4, 0x0436086c);
36766+ INSTANCE_WR(ctx, 0x26e4/4, 0x000c001b);
36767+ INSTANCE_WR(ctx, 0x26ec/4, 0x10700ff9);
36768+ INSTANCE_WR(ctx, 0x26f0/4, 0x0436086c);
36769+ INSTANCE_WR(ctx, 0x26f4/4, 0x000c001b);
36770+ INSTANCE_WR(ctx, 0x26fc/4, 0x10700ff9);
36771+ INSTANCE_WR(ctx, 0x2700/4, 0x0436086c);
36772+ INSTANCE_WR(ctx, 0x2704/4, 0x000c001b);
36773+ INSTANCE_WR(ctx, 0x270c/4, 0x10700ff9);
36774+ INSTANCE_WR(ctx, 0x2710/4, 0x0436086c);
36775+ INSTANCE_WR(ctx, 0x2714/4, 0x000c001b);
36776+ INSTANCE_WR(ctx, 0x271c/4, 0x10700ff9);
36777+ INSTANCE_WR(ctx, 0x2720/4, 0x0436086c);
36778+ INSTANCE_WR(ctx, 0x2724/4, 0x000c001b);
36779+ INSTANCE_WR(ctx, 0x272c/4, 0x10700ff9);
36780+ INSTANCE_WR(ctx, 0x2730/4, 0x0436086c);
36781+ INSTANCE_WR(ctx, 0x2734/4, 0x000c001b);
36782+ INSTANCE_WR(ctx, 0x273c/4, 0x10700ff9);
36783+ INSTANCE_WR(ctx, 0x2740/4, 0x0436086c);
36784+ INSTANCE_WR(ctx, 0x2744/4, 0x000c001b);
36785+ INSTANCE_WR(ctx, 0x274c/4, 0x10700ff9);
36786+ INSTANCE_WR(ctx, 0x2750/4, 0x0436086c);
36787+ INSTANCE_WR(ctx, 0x2754/4, 0x000c001b);
36788+ INSTANCE_WR(ctx, 0x275c/4, 0x10700ff9);
36789+ INSTANCE_WR(ctx, 0x2760/4, 0x0436086c);
36790+ INSTANCE_WR(ctx, 0x2764/4, 0x000c001b);
36791+ INSTANCE_WR(ctx, 0x276c/4, 0x10700ff9);
36792+ INSTANCE_WR(ctx, 0x2770/4, 0x0436086c);
36793+ INSTANCE_WR(ctx, 0x2774/4, 0x000c001b);
36794+ INSTANCE_WR(ctx, 0x277c/4, 0x10700ff9);
36795+ INSTANCE_WR(ctx, 0x2780/4, 0x0436086c);
36796+ INSTANCE_WR(ctx, 0x2784/4, 0x000c001b);
36797+ INSTANCE_WR(ctx, 0x278c/4, 0x10700ff9);
36798+ INSTANCE_WR(ctx, 0x2790/4, 0x0436086c);
36799+ INSTANCE_WR(ctx, 0x2794/4, 0x000c001b);
36800+ INSTANCE_WR(ctx, 0x279c/4, 0x10700ff9);
36801+ INSTANCE_WR(ctx, 0x27a0/4, 0x0436086c);
36802+ INSTANCE_WR(ctx, 0x27a4/4, 0x000c001b);
36803+ INSTANCE_WR(ctx, 0x27ac/4, 0x10700ff9);
36804+ INSTANCE_WR(ctx, 0x27b0/4, 0x0436086c);
36805+ INSTANCE_WR(ctx, 0x27b4/4, 0x000c001b);
36806+ INSTANCE_WR(ctx, 0x27bc/4, 0x10700ff9);
36807+ INSTANCE_WR(ctx, 0x27c0/4, 0x0436086c);
36808+ INSTANCE_WR(ctx, 0x27c4/4, 0x000c001b);
36809+ INSTANCE_WR(ctx, 0x27cc/4, 0x10700ff9);
36810+ INSTANCE_WR(ctx, 0x27d0/4, 0x0436086c);
36811+ INSTANCE_WR(ctx, 0x27d4/4, 0x000c001b);
36812+ INSTANCE_WR(ctx, 0x27dc/4, 0x10700ff9);
36813+ INSTANCE_WR(ctx, 0x27e0/4, 0x0436086c);
36814+ INSTANCE_WR(ctx, 0x27e4/4, 0x000c001b);
36815+ INSTANCE_WR(ctx, 0x27ec/4, 0x10700ff9);
36816+ INSTANCE_WR(ctx, 0x27f0/4, 0x0436086c);
36817+ INSTANCE_WR(ctx, 0x27f4/4, 0x000c001b);
36818+ INSTANCE_WR(ctx, 0x27fc/4, 0x10700ff9);
36819+ INSTANCE_WR(ctx, 0x2800/4, 0x0436086c);
36820+ INSTANCE_WR(ctx, 0x2804/4, 0x000c001b);
36821+ INSTANCE_WR(ctx, 0x280c/4, 0x10700ff9);
36822+ INSTANCE_WR(ctx, 0x2810/4, 0x0436086c);
36823+ INSTANCE_WR(ctx, 0x2814/4, 0x000c001b);
36824+ INSTANCE_WR(ctx, 0x281c/4, 0x10700ff9);
36825+ INSTANCE_WR(ctx, 0x2820/4, 0x0436086c);
36826+ INSTANCE_WR(ctx, 0x2824/4, 0x000c001b);
36827+ INSTANCE_WR(ctx, 0x282c/4, 0x10700ff9);
36828+ INSTANCE_WR(ctx, 0x2830/4, 0x0436086c);
36829+ INSTANCE_WR(ctx, 0x2834/4, 0x000c001b);
36830+ INSTANCE_WR(ctx, 0x283c/4, 0x10700ff9);
36831+ INSTANCE_WR(ctx, 0x2840/4, 0x0436086c);
36832+ INSTANCE_WR(ctx, 0x2844/4, 0x000c001b);
36833+ INSTANCE_WR(ctx, 0x284c/4, 0x10700ff9);
36834+ INSTANCE_WR(ctx, 0x2850/4, 0x0436086c);
36835+ INSTANCE_WR(ctx, 0x2854/4, 0x000c001b);
36836+ INSTANCE_WR(ctx, 0x285c/4, 0x10700ff9);
36837+ INSTANCE_WR(ctx, 0x2860/4, 0x0436086c);
36838+ INSTANCE_WR(ctx, 0x2864/4, 0x000c001b);
36839+ INSTANCE_WR(ctx, 0x286c/4, 0x10700ff9);
36840+ INSTANCE_WR(ctx, 0x2870/4, 0x0436086c);
36841+ INSTANCE_WR(ctx, 0x2874/4, 0x000c001b);
36842+ INSTANCE_WR(ctx, 0x287c/4, 0x10700ff9);
36843+ INSTANCE_WR(ctx, 0x2880/4, 0x0436086c);
36844+ INSTANCE_WR(ctx, 0x2884/4, 0x000c001b);
36845+ INSTANCE_WR(ctx, 0x288c/4, 0x10700ff9);
36846+ INSTANCE_WR(ctx, 0x2890/4, 0x0436086c);
36847+ INSTANCE_WR(ctx, 0x2894/4, 0x000c001b);
36848+ INSTANCE_WR(ctx, 0x289c/4, 0x10700ff9);
36849+ INSTANCE_WR(ctx, 0x28a0/4, 0x0436086c);
36850+ INSTANCE_WR(ctx, 0x28a4/4, 0x000c001b);
36851+ INSTANCE_WR(ctx, 0x28ac/4, 0x10700ff9);
36852+ INSTANCE_WR(ctx, 0x28b0/4, 0x0436086c);
36853+ INSTANCE_WR(ctx, 0x28b4/4, 0x000c001b);
36854+ INSTANCE_WR(ctx, 0x28bc/4, 0x10700ff9);
36855+ INSTANCE_WR(ctx, 0x28c0/4, 0x0436086c);
36856+ INSTANCE_WR(ctx, 0x28c4/4, 0x000c001b);
36857+ INSTANCE_WR(ctx, 0x28cc/4, 0x10700ff9);
36858+ INSTANCE_WR(ctx, 0x28d0/4, 0x0436086c);
36859+ INSTANCE_WR(ctx, 0x28d4/4, 0x000c001b);
36860+ INSTANCE_WR(ctx, 0x28dc/4, 0x10700ff9);
36861+ INSTANCE_WR(ctx, 0x28e0/4, 0x0436086c);
36862+ INSTANCE_WR(ctx, 0x28e4/4, 0x000c001b);
36863+ INSTANCE_WR(ctx, 0x28ec/4, 0x10700ff9);
36864+ INSTANCE_WR(ctx, 0x28f0/4, 0x0436086c);
36865+ INSTANCE_WR(ctx, 0x28f4/4, 0x000c001b);
36866+ INSTANCE_WR(ctx, 0x28fc/4, 0x10700ff9);
36867+ INSTANCE_WR(ctx, 0x2900/4, 0x0436086c);
36868+ INSTANCE_WR(ctx, 0x2904/4, 0x000c001b);
36869+ INSTANCE_WR(ctx, 0x290c/4, 0x10700ff9);
36870+ INSTANCE_WR(ctx, 0x2910/4, 0x0436086c);
36871+ INSTANCE_WR(ctx, 0x2914/4, 0x000c001b);
36872+ INSTANCE_WR(ctx, 0x291c/4, 0x10700ff9);
36873+ INSTANCE_WR(ctx, 0x2920/4, 0x0436086c);
36874+ INSTANCE_WR(ctx, 0x2924/4, 0x000c001b);
36875+ INSTANCE_WR(ctx, 0x292c/4, 0x10700ff9);
36876+ INSTANCE_WR(ctx, 0x2930/4, 0x0436086c);
36877+ INSTANCE_WR(ctx, 0x2934/4, 0x000c001b);
36878+ INSTANCE_WR(ctx, 0x293c/4, 0x10700ff9);
36879+ INSTANCE_WR(ctx, 0x2940/4, 0x0436086c);
36880+ INSTANCE_WR(ctx, 0x2944/4, 0x000c001b);
36881+ INSTANCE_WR(ctx, 0x294c/4, 0x10700ff9);
36882+ INSTANCE_WR(ctx, 0x2950/4, 0x0436086c);
36883+ INSTANCE_WR(ctx, 0x2954/4, 0x000c001b);
36884+ INSTANCE_WR(ctx, 0x295c/4, 0x10700ff9);
36885+ INSTANCE_WR(ctx, 0x2960/4, 0x0436086c);
36886+ INSTANCE_WR(ctx, 0x2964/4, 0x000c001b);
36887+ INSTANCE_WR(ctx, 0x296c/4, 0x10700ff9);
36888+ INSTANCE_WR(ctx, 0x2970/4, 0x0436086c);
36889+ INSTANCE_WR(ctx, 0x2974/4, 0x000c001b);
36890+ INSTANCE_WR(ctx, 0x297c/4, 0x10700ff9);
36891+ INSTANCE_WR(ctx, 0x2980/4, 0x0436086c);
36892+ INSTANCE_WR(ctx, 0x2984/4, 0x000c001b);
36893+ INSTANCE_WR(ctx, 0x298c/4, 0x10700ff9);
36894+ INSTANCE_WR(ctx, 0x2990/4, 0x0436086c);
36895+ INSTANCE_WR(ctx, 0x2994/4, 0x000c001b);
36896+ INSTANCE_WR(ctx, 0x299c/4, 0x10700ff9);
36897+ INSTANCE_WR(ctx, 0x29a0/4, 0x0436086c);
36898+ INSTANCE_WR(ctx, 0x29a4/4, 0x000c001b);
36899+ INSTANCE_WR(ctx, 0x29ac/4, 0x10700ff9);
36900+ INSTANCE_WR(ctx, 0x29b0/4, 0x0436086c);
36901+ INSTANCE_WR(ctx, 0x29b4/4, 0x000c001b);
36902+ INSTANCE_WR(ctx, 0x29bc/4, 0x10700ff9);
36903+ INSTANCE_WR(ctx, 0x29c0/4, 0x0436086c);
36904+ INSTANCE_WR(ctx, 0x29c4/4, 0x000c001b);
36905+ INSTANCE_WR(ctx, 0x29cc/4, 0x10700ff9);
36906+ INSTANCE_WR(ctx, 0x29d0/4, 0x0436086c);
36907+ INSTANCE_WR(ctx, 0x29d4/4, 0x000c001b);
36908+ INSTANCE_WR(ctx, 0x29dc/4, 0x10700ff9);
36909+ INSTANCE_WR(ctx, 0x29e0/4, 0x0436086c);
36910+ INSTANCE_WR(ctx, 0x29e4/4, 0x000c001b);
36911+ INSTANCE_WR(ctx, 0x29ec/4, 0x10700ff9);
36912+ INSTANCE_WR(ctx, 0x29f0/4, 0x0436086c);
36913+ INSTANCE_WR(ctx, 0x29f4/4, 0x000c001b);
36914+ INSTANCE_WR(ctx, 0x29fc/4, 0x10700ff9);
36915+ INSTANCE_WR(ctx, 0x2a00/4, 0x0436086c);
36916+ INSTANCE_WR(ctx, 0x2a04/4, 0x000c001b);
36917+ INSTANCE_WR(ctx, 0x2a0c/4, 0x10700ff9);
36918+ INSTANCE_WR(ctx, 0x2a10/4, 0x0436086c);
36919+ INSTANCE_WR(ctx, 0x2a14/4, 0x000c001b);
36920+ INSTANCE_WR(ctx, 0x2a1c/4, 0x10700ff9);
36921+ INSTANCE_WR(ctx, 0x2a20/4, 0x0436086c);
36922+ INSTANCE_WR(ctx, 0x2a24/4, 0x000c001b);
36923+ INSTANCE_WR(ctx, 0x2a2c/4, 0x10700ff9);
36924+ INSTANCE_WR(ctx, 0x2a30/4, 0x0436086c);
36925+ INSTANCE_WR(ctx, 0x2a34/4, 0x000c001b);
36926+ INSTANCE_WR(ctx, 0x2a3c/4, 0x10700ff9);
36927+ INSTANCE_WR(ctx, 0x2a40/4, 0x0436086c);
36928+ INSTANCE_WR(ctx, 0x2a44/4, 0x000c001b);
36929+ INSTANCE_WR(ctx, 0x2a4c/4, 0x10700ff9);
36930+ INSTANCE_WR(ctx, 0x2a50/4, 0x0436086c);
36931+ INSTANCE_WR(ctx, 0x2a54/4, 0x000c001b);
36932+ INSTANCE_WR(ctx, 0x2a5c/4, 0x10700ff9);
36933+ INSTANCE_WR(ctx, 0x2a60/4, 0x0436086c);
36934+ INSTANCE_WR(ctx, 0x2a64/4, 0x000c001b);
36935+ INSTANCE_WR(ctx, 0x2a6c/4, 0x10700ff9);
36936+ INSTANCE_WR(ctx, 0x2a70/4, 0x0436086c);
36937+ INSTANCE_WR(ctx, 0x2a74/4, 0x000c001b);
36938+ INSTANCE_WR(ctx, 0x2a7c/4, 0x10700ff9);
36939+ INSTANCE_WR(ctx, 0x2a80/4, 0x0436086c);
36940+ INSTANCE_WR(ctx, 0x2a84/4, 0x000c001b);
36941+ INSTANCE_WR(ctx, 0x2a8c/4, 0x10700ff9);
36942+ INSTANCE_WR(ctx, 0x2a90/4, 0x0436086c);
36943+ INSTANCE_WR(ctx, 0x2a94/4, 0x000c001b);
36944+ INSTANCE_WR(ctx, 0x2a9c/4, 0x10700ff9);
36945+ INSTANCE_WR(ctx, 0x2aa0/4, 0x0436086c);
36946+ INSTANCE_WR(ctx, 0x2aa4/4, 0x000c001b);
36947+ INSTANCE_WR(ctx, 0x2aac/4, 0x10700ff9);
36948+ INSTANCE_WR(ctx, 0x2ab0/4, 0x0436086c);
36949+ INSTANCE_WR(ctx, 0x2ab4/4, 0x000c001b);
36950+ INSTANCE_WR(ctx, 0x2abc/4, 0x10700ff9);
36951+ INSTANCE_WR(ctx, 0x2ac0/4, 0x0436086c);
36952+ INSTANCE_WR(ctx, 0x2ac4/4, 0x000c001b);
36953+ INSTANCE_WR(ctx, 0x2acc/4, 0x10700ff9);
36954+ INSTANCE_WR(ctx, 0x2ad0/4, 0x0436086c);
36955+ INSTANCE_WR(ctx, 0x2ad4/4, 0x000c001b);
36956+ INSTANCE_WR(ctx, 0x2adc/4, 0x10700ff9);
36957+ INSTANCE_WR(ctx, 0x2ae0/4, 0x0436086c);
36958+ INSTANCE_WR(ctx, 0x2ae4/4, 0x000c001b);
36959+ INSTANCE_WR(ctx, 0x2aec/4, 0x10700ff9);
36960+ INSTANCE_WR(ctx, 0x2af0/4, 0x0436086c);
36961+ INSTANCE_WR(ctx, 0x2af4/4, 0x000c001b);
36962+ INSTANCE_WR(ctx, 0x2afc/4, 0x10700ff9);
36963+ INSTANCE_WR(ctx, 0x2b00/4, 0x0436086c);
36964+ INSTANCE_WR(ctx, 0x2b04/4, 0x000c001b);
36965+ INSTANCE_WR(ctx, 0x2b0c/4, 0x10700ff9);
36966+ INSTANCE_WR(ctx, 0x2b10/4, 0x0436086c);
36967+ INSTANCE_WR(ctx, 0x2b14/4, 0x000c001b);
36968+ INSTANCE_WR(ctx, 0x2b1c/4, 0x10700ff9);
36969+ INSTANCE_WR(ctx, 0x2b20/4, 0x0436086c);
36970+ INSTANCE_WR(ctx, 0x2b24/4, 0x000c001b);
36971+ INSTANCE_WR(ctx, 0x2b2c/4, 0x10700ff9);
36972+ INSTANCE_WR(ctx, 0x2b30/4, 0x0436086c);
36973+ INSTANCE_WR(ctx, 0x2b34/4, 0x000c001b);
36974+ INSTANCE_WR(ctx, 0x2b3c/4, 0x10700ff9);
36975+ INSTANCE_WR(ctx, 0x2b40/4, 0x0436086c);
36976+ INSTANCE_WR(ctx, 0x2b44/4, 0x000c001b);
36977+ INSTANCE_WR(ctx, 0x2b4c/4, 0x10700ff9);
36978+ INSTANCE_WR(ctx, 0x2b50/4, 0x0436086c);
36979+ INSTANCE_WR(ctx, 0x2b54/4, 0x000c001b);
36980+ INSTANCE_WR(ctx, 0x2b5c/4, 0x10700ff9);
36981+ INSTANCE_WR(ctx, 0x2b60/4, 0x0436086c);
36982+ INSTANCE_WR(ctx, 0x2b64/4, 0x000c001b);
36983+ INSTANCE_WR(ctx, 0x2b6c/4, 0x10700ff9);
36984+ INSTANCE_WR(ctx, 0x2b70/4, 0x0436086c);
36985+ INSTANCE_WR(ctx, 0x2b74/4, 0x000c001b);
36986+ INSTANCE_WR(ctx, 0x2b7c/4, 0x10700ff9);
36987+ INSTANCE_WR(ctx, 0x2b80/4, 0x0436086c);
36988+ INSTANCE_WR(ctx, 0x2b84/4, 0x000c001b);
36989+ INSTANCE_WR(ctx, 0x2b8c/4, 0x10700ff9);
36990+ INSTANCE_WR(ctx, 0x2b90/4, 0x0436086c);
36991+ INSTANCE_WR(ctx, 0x2b94/4, 0x000c001b);
36992+ INSTANCE_WR(ctx, 0x2b9c/4, 0x10700ff9);
36993+ INSTANCE_WR(ctx, 0x2ba0/4, 0x0436086c);
36994+ INSTANCE_WR(ctx, 0x2ba4/4, 0x000c001b);
36995+ INSTANCE_WR(ctx, 0x2bac/4, 0x10700ff9);
36996+ INSTANCE_WR(ctx, 0x2bb0/4, 0x0436086c);
36997+ INSTANCE_WR(ctx, 0x2bb4/4, 0x000c001b);
36998+ INSTANCE_WR(ctx, 0x2bbc/4, 0x10700ff9);
36999+ INSTANCE_WR(ctx, 0x2bc0/4, 0x0436086c);
37000+ INSTANCE_WR(ctx, 0x2bc4/4, 0x000c001b);
37001+ INSTANCE_WR(ctx, 0x2bcc/4, 0x10700ff9);
37002+ INSTANCE_WR(ctx, 0x2bd0/4, 0x0436086c);
37003+ INSTANCE_WR(ctx, 0x2bd4/4, 0x000c001b);
37004+ INSTANCE_WR(ctx, 0x2bdc/4, 0x10700ff9);
37005+ INSTANCE_WR(ctx, 0x2be0/4, 0x0436086c);
37006+ INSTANCE_WR(ctx, 0x2be4/4, 0x000c001b);
37007+ INSTANCE_WR(ctx, 0x2bec/4, 0x10700ff9);
37008+ INSTANCE_WR(ctx, 0x2bf0/4, 0x0436086c);
37009+ INSTANCE_WR(ctx, 0x2bf4/4, 0x000c001b);
37010+ INSTANCE_WR(ctx, 0x2bfc/4, 0x10700ff9);
37011+ INSTANCE_WR(ctx, 0x2c00/4, 0x0436086c);
37012+ INSTANCE_WR(ctx, 0x2c04/4, 0x000c001b);
37013+ INSTANCE_WR(ctx, 0x2c0c/4, 0x10700ff9);
37014+ INSTANCE_WR(ctx, 0x2c10/4, 0x0436086c);
37015+ INSTANCE_WR(ctx, 0x2c14/4, 0x000c001b);
37016+ INSTANCE_WR(ctx, 0x2c1c/4, 0x10700ff9);
37017+ INSTANCE_WR(ctx, 0x2c20/4, 0x0436086c);
37018+ INSTANCE_WR(ctx, 0x2c24/4, 0x000c001b);
37019+ INSTANCE_WR(ctx, 0x2c2c/4, 0x10700ff9);
37020+ INSTANCE_WR(ctx, 0x2c30/4, 0x0436086c);
37021+ INSTANCE_WR(ctx, 0x2c34/4, 0x000c001b);
37022+ INSTANCE_WR(ctx, 0x2c3c/4, 0x10700ff9);
37023+ INSTANCE_WR(ctx, 0x2c40/4, 0x0436086c);
37024+ INSTANCE_WR(ctx, 0x2c44/4, 0x000c001b);
37025+ INSTANCE_WR(ctx, 0x2c4c/4, 0x10700ff9);
37026+ INSTANCE_WR(ctx, 0x2c50/4, 0x0436086c);
37027+ INSTANCE_WR(ctx, 0x2c54/4, 0x000c001b);
37028+ INSTANCE_WR(ctx, 0x2c5c/4, 0x10700ff9);
37029+ INSTANCE_WR(ctx, 0x2c60/4, 0x0436086c);
37030+ INSTANCE_WR(ctx, 0x2c64/4, 0x000c001b);
37031+ INSTANCE_WR(ctx, 0x2c6c/4, 0x10700ff9);
37032+ INSTANCE_WR(ctx, 0x2c70/4, 0x0436086c);
37033+ INSTANCE_WR(ctx, 0x2c74/4, 0x000c001b);
37034+ INSTANCE_WR(ctx, 0x2c7c/4, 0x10700ff9);
37035+ INSTANCE_WR(ctx, 0x2c80/4, 0x0436086c);
37036+ INSTANCE_WR(ctx, 0x2c84/4, 0x000c001b);
37037+ INSTANCE_WR(ctx, 0x2c8c/4, 0x10700ff9);
37038+ INSTANCE_WR(ctx, 0x2c90/4, 0x0436086c);
37039+ INSTANCE_WR(ctx, 0x2c94/4, 0x000c001b);
37040+ INSTANCE_WR(ctx, 0x2c9c/4, 0x10700ff9);
37041+ INSTANCE_WR(ctx, 0x2ca0/4, 0x0436086c);
37042+ INSTANCE_WR(ctx, 0x2ca4/4, 0x000c001b);
37043+ INSTANCE_WR(ctx, 0x2cac/4, 0x10700ff9);
37044+ INSTANCE_WR(ctx, 0x2cb0/4, 0x0436086c);
37045+ INSTANCE_WR(ctx, 0x2cb4/4, 0x000c001b);
37046+ INSTANCE_WR(ctx, 0x2cbc/4, 0x10700ff9);
37047+ INSTANCE_WR(ctx, 0x2cc0/4, 0x0436086c);
37048+ INSTANCE_WR(ctx, 0x2cc4/4, 0x000c001b);
37049+ INSTANCE_WR(ctx, 0x2ccc/4, 0x10700ff9);
37050+ INSTANCE_WR(ctx, 0x2cd0/4, 0x0436086c);
37051+ INSTANCE_WR(ctx, 0x2cd4/4, 0x000c001b);
37052+ INSTANCE_WR(ctx, 0x2cdc/4, 0x10700ff9);
37053+ INSTANCE_WR(ctx, 0x2ce0/4, 0x0436086c);
37054+ INSTANCE_WR(ctx, 0x2ce4/4, 0x000c001b);
37055+ INSTANCE_WR(ctx, 0x2cec/4, 0x10700ff9);
37056+ INSTANCE_WR(ctx, 0x2cf0/4, 0x0436086c);
37057+ INSTANCE_WR(ctx, 0x2cf4/4, 0x000c001b);
37058+ INSTANCE_WR(ctx, 0x2cfc/4, 0x10700ff9);
37059+ INSTANCE_WR(ctx, 0x2d00/4, 0x0436086c);
37060+ INSTANCE_WR(ctx, 0x2d04/4, 0x000c001b);
37061+ INSTANCE_WR(ctx, 0x2d0c/4, 0x10700ff9);
37062+ INSTANCE_WR(ctx, 0x2d10/4, 0x0436086c);
37063+ INSTANCE_WR(ctx, 0x2d14/4, 0x000c001b);
37064+ INSTANCE_WR(ctx, 0x2d1c/4, 0x10700ff9);
37065+ INSTANCE_WR(ctx, 0x2d20/4, 0x0436086c);
37066+ INSTANCE_WR(ctx, 0x2d24/4, 0x000c001b);
37067+ INSTANCE_WR(ctx, 0x2d2c/4, 0x10700ff9);
37068+ INSTANCE_WR(ctx, 0x2d30/4, 0x0436086c);
37069+ INSTANCE_WR(ctx, 0x2d34/4, 0x000c001b);
37070+ INSTANCE_WR(ctx, 0x2d3c/4, 0x10700ff9);
37071+ INSTANCE_WR(ctx, 0x2d40/4, 0x0436086c);
37072+ INSTANCE_WR(ctx, 0x2d44/4, 0x000c001b);
37073+ INSTANCE_WR(ctx, 0x2d4c/4, 0x10700ff9);
37074+ INSTANCE_WR(ctx, 0x2d50/4, 0x0436086c);
37075+ INSTANCE_WR(ctx, 0x2d54/4, 0x000c001b);
37076+ INSTANCE_WR(ctx, 0x2d5c/4, 0x10700ff9);
37077+ INSTANCE_WR(ctx, 0x2d60/4, 0x0436086c);
37078+ INSTANCE_WR(ctx, 0x2d64/4, 0x000c001b);
37079+ INSTANCE_WR(ctx, 0x2d6c/4, 0x10700ff9);
37080+ INSTANCE_WR(ctx, 0x2d70/4, 0x0436086c);
37081+ INSTANCE_WR(ctx, 0x2d74/4, 0x000c001b);
37082+ INSTANCE_WR(ctx, 0x2d7c/4, 0x10700ff9);
37083+ INSTANCE_WR(ctx, 0x2d80/4, 0x0436086c);
37084+ INSTANCE_WR(ctx, 0x2d84/4, 0x000c001b);
37085+ INSTANCE_WR(ctx, 0x2d8c/4, 0x10700ff9);
37086+ INSTANCE_WR(ctx, 0x2d90/4, 0x0436086c);
37087+ INSTANCE_WR(ctx, 0x2d94/4, 0x000c001b);
37088+ INSTANCE_WR(ctx, 0x2d9c/4, 0x10700ff9);
37089+ INSTANCE_WR(ctx, 0x2da0/4, 0x0436086c);
37090+ INSTANCE_WR(ctx, 0x2da4/4, 0x000c001b);
37091+ INSTANCE_WR(ctx, 0x2dac/4, 0x10700ff9);
37092+ INSTANCE_WR(ctx, 0x2db0/4, 0x0436086c);
37093+ INSTANCE_WR(ctx, 0x2db4/4, 0x000c001b);
37094+ INSTANCE_WR(ctx, 0x2dbc/4, 0x10700ff9);
37095+ INSTANCE_WR(ctx, 0x2dc0/4, 0x0436086c);
37096+ INSTANCE_WR(ctx, 0x2dc4/4, 0x000c001b);
37097+ INSTANCE_WR(ctx, 0x2dcc/4, 0x10700ff9);
37098+ INSTANCE_WR(ctx, 0x2dd0/4, 0x0436086c);
37099+ INSTANCE_WR(ctx, 0x2dd4/4, 0x000c001b);
37100+ INSTANCE_WR(ctx, 0x2ddc/4, 0x10700ff9);
37101+ INSTANCE_WR(ctx, 0x2de0/4, 0x0436086c);
37102+ INSTANCE_WR(ctx, 0x2de4/4, 0x000c001b);
37103+ INSTANCE_WR(ctx, 0x2dec/4, 0x10700ff9);
37104+ INSTANCE_WR(ctx, 0x2df0/4, 0x0436086c);
37105+ INSTANCE_WR(ctx, 0x2df4/4, 0x000c001b);
37106+ INSTANCE_WR(ctx, 0x2dfc/4, 0x10700ff9);
37107+ INSTANCE_WR(ctx, 0x2e00/4, 0x0436086c);
37108+ INSTANCE_WR(ctx, 0x2e04/4, 0x000c001b);
37109+ INSTANCE_WR(ctx, 0x2e0c/4, 0x10700ff9);
37110+ INSTANCE_WR(ctx, 0x2e10/4, 0x0436086c);
37111+ INSTANCE_WR(ctx, 0x2e14/4, 0x000c001b);
37112+ INSTANCE_WR(ctx, 0x2e1c/4, 0x10700ff9);
37113+ INSTANCE_WR(ctx, 0x2e20/4, 0x0436086c);
37114+ INSTANCE_WR(ctx, 0x2e24/4, 0x000c001b);
37115+ INSTANCE_WR(ctx, 0x2e2c/4, 0x10700ff9);
37116+ INSTANCE_WR(ctx, 0x2e30/4, 0x0436086c);
37117+ INSTANCE_WR(ctx, 0x2e34/4, 0x000c001b);
37118+ INSTANCE_WR(ctx, 0x2e3c/4, 0x10700ff9);
37119+ INSTANCE_WR(ctx, 0x2e40/4, 0x0436086c);
37120+ INSTANCE_WR(ctx, 0x2e44/4, 0x000c001b);
37121+ INSTANCE_WR(ctx, 0x2e4c/4, 0x10700ff9);
37122+ INSTANCE_WR(ctx, 0x2e50/4, 0x0436086c);
37123+ INSTANCE_WR(ctx, 0x2e54/4, 0x000c001b);
37124+ INSTANCE_WR(ctx, 0x2e5c/4, 0x10700ff9);
37125+ INSTANCE_WR(ctx, 0x2e60/4, 0x0436086c);
37126+ INSTANCE_WR(ctx, 0x2e64/4, 0x000c001b);
37127+ INSTANCE_WR(ctx, 0x2e6c/4, 0x10700ff9);
37128+ INSTANCE_WR(ctx, 0x2e70/4, 0x0436086c);
37129+ INSTANCE_WR(ctx, 0x2e74/4, 0x000c001b);
37130+ INSTANCE_WR(ctx, 0x2e7c/4, 0x10700ff9);
37131+ INSTANCE_WR(ctx, 0x2e80/4, 0x0436086c);
37132+ INSTANCE_WR(ctx, 0x2e84/4, 0x000c001b);
37133+ INSTANCE_WR(ctx, 0x2e8c/4, 0x10700ff9);
37134+ INSTANCE_WR(ctx, 0x2e90/4, 0x0436086c);
37135+ INSTANCE_WR(ctx, 0x2e94/4, 0x000c001b);
37136+ INSTANCE_WR(ctx, 0x2e9c/4, 0x10700ff9);
37137+ INSTANCE_WR(ctx, 0x2ea0/4, 0x0436086c);
37138+ INSTANCE_WR(ctx, 0x2ea4/4, 0x000c001b);
37139+ INSTANCE_WR(ctx, 0x2eac/4, 0x10700ff9);
37140+ INSTANCE_WR(ctx, 0x2eb0/4, 0x0436086c);
37141+ INSTANCE_WR(ctx, 0x2eb4/4, 0x000c001b);
37142+ INSTANCE_WR(ctx, 0x2ebc/4, 0x10700ff9);
37143+ INSTANCE_WR(ctx, 0x2ec0/4, 0x0436086c);
37144+ INSTANCE_WR(ctx, 0x2ec4/4, 0x000c001b);
37145+ INSTANCE_WR(ctx, 0x2ecc/4, 0x10700ff9);
37146+ INSTANCE_WR(ctx, 0x2ed0/4, 0x0436086c);
37147+ INSTANCE_WR(ctx, 0x2ed4/4, 0x000c001b);
37148+ INSTANCE_WR(ctx, 0x2edc/4, 0x10700ff9);
37149+ INSTANCE_WR(ctx, 0x2ee0/4, 0x0436086c);
37150+ INSTANCE_WR(ctx, 0x2ee4/4, 0x000c001b);
37151+ INSTANCE_WR(ctx, 0x2eec/4, 0x10700ff9);
37152+ INSTANCE_WR(ctx, 0x2ef0/4, 0x0436086c);
37153+ INSTANCE_WR(ctx, 0x2ef4/4, 0x000c001b);
37154+ INSTANCE_WR(ctx, 0x2efc/4, 0x10700ff9);
37155+ INSTANCE_WR(ctx, 0x2f00/4, 0x0436086c);
37156+ INSTANCE_WR(ctx, 0x2f04/4, 0x000c001b);
37157+ INSTANCE_WR(ctx, 0x2f0c/4, 0x10700ff9);
37158+ INSTANCE_WR(ctx, 0x2f10/4, 0x0436086c);
37159+ INSTANCE_WR(ctx, 0x2f14/4, 0x000c001b);
37160+ INSTANCE_WR(ctx, 0x2f1c/4, 0x10700ff9);
37161+ INSTANCE_WR(ctx, 0x2f20/4, 0x0436086c);
37162+ INSTANCE_WR(ctx, 0x2f24/4, 0x000c001b);
37163+ INSTANCE_WR(ctx, 0x2f2c/4, 0x10700ff9);
37164+ INSTANCE_WR(ctx, 0x2f30/4, 0x0436086c);
37165+ INSTANCE_WR(ctx, 0x2f34/4, 0x000c001b);
37166+ INSTANCE_WR(ctx, 0x2f3c/4, 0x10700ff9);
37167+ INSTANCE_WR(ctx, 0x2f40/4, 0x0436086c);
37168+ INSTANCE_WR(ctx, 0x2f44/4, 0x000c001b);
37169+ INSTANCE_WR(ctx, 0x2f4c/4, 0x10700ff9);
37170+ INSTANCE_WR(ctx, 0x2f50/4, 0x0436086c);
37171+ INSTANCE_WR(ctx, 0x2f54/4, 0x000c001b);
37172+ INSTANCE_WR(ctx, 0x2f5c/4, 0x10700ff9);
37173+ INSTANCE_WR(ctx, 0x2f60/4, 0x0436086c);
37174+ INSTANCE_WR(ctx, 0x2f64/4, 0x000c001b);
37175+ INSTANCE_WR(ctx, 0x2f6c/4, 0x10700ff9);
37176+ INSTANCE_WR(ctx, 0x2f70/4, 0x0436086c);
37177+ INSTANCE_WR(ctx, 0x2f74/4, 0x000c001b);
37178+ INSTANCE_WR(ctx, 0x2f7c/4, 0x10700ff9);
37179+ INSTANCE_WR(ctx, 0x2f80/4, 0x0436086c);
37180+ INSTANCE_WR(ctx, 0x2f84/4, 0x000c001b);
37181+ INSTANCE_WR(ctx, 0x2f8c/4, 0x10700ff9);
37182+ INSTANCE_WR(ctx, 0x2f90/4, 0x0436086c);
37183+ INSTANCE_WR(ctx, 0x2f94/4, 0x000c001b);
37184+ INSTANCE_WR(ctx, 0x2f9c/4, 0x10700ff9);
37185+ INSTANCE_WR(ctx, 0x2fa0/4, 0x0436086c);
37186+ INSTANCE_WR(ctx, 0x2fa4/4, 0x000c001b);
37187+ INSTANCE_WR(ctx, 0x2fac/4, 0x10700ff9);
37188+ INSTANCE_WR(ctx, 0x2fb0/4, 0x0436086c);
37189+ INSTANCE_WR(ctx, 0x2fb4/4, 0x000c001b);
37190+ INSTANCE_WR(ctx, 0x2fbc/4, 0x10700ff9);
37191+ INSTANCE_WR(ctx, 0x2fc0/4, 0x0436086c);
37192+ INSTANCE_WR(ctx, 0x2fc4/4, 0x000c001b);
37193+ INSTANCE_WR(ctx, 0x2fcc/4, 0x10700ff9);
37194+ INSTANCE_WR(ctx, 0x2fd0/4, 0x0436086c);
37195+ INSTANCE_WR(ctx, 0x2fd4/4, 0x000c001b);
37196+ INSTANCE_WR(ctx, 0x2fdc/4, 0x10700ff9);
37197+ INSTANCE_WR(ctx, 0x2fe0/4, 0x0436086c);
37198+ INSTANCE_WR(ctx, 0x2fe4/4, 0x000c001b);
37199+ INSTANCE_WR(ctx, 0x2fec/4, 0x10700ff9);
37200+ INSTANCE_WR(ctx, 0x2ff0/4, 0x0436086c);
37201+ INSTANCE_WR(ctx, 0x2ff4/4, 0x000c001b);
37202+ INSTANCE_WR(ctx, 0x2ffc/4, 0x10700ff9);
37203+ INSTANCE_WR(ctx, 0x3000/4, 0x0436086c);
37204+ INSTANCE_WR(ctx, 0x3004/4, 0x000c001b);
37205+ INSTANCE_WR(ctx, 0x300c/4, 0x10700ff9);
37206+ INSTANCE_WR(ctx, 0x3010/4, 0x0436086c);
37207+ INSTANCE_WR(ctx, 0x3014/4, 0x000c001b);
37208+ INSTANCE_WR(ctx, 0x301c/4, 0x10700ff9);
37209+ INSTANCE_WR(ctx, 0x3020/4, 0x0436086c);
37210+ INSTANCE_WR(ctx, 0x3024/4, 0x000c001b);
37211+ INSTANCE_WR(ctx, 0x302c/4, 0x10700ff9);
37212+ INSTANCE_WR(ctx, 0x3030/4, 0x0436086c);
37213+ INSTANCE_WR(ctx, 0x3034/4, 0x000c001b);
37214+ INSTANCE_WR(ctx, 0x303c/4, 0x10700ff9);
37215+ INSTANCE_WR(ctx, 0x3040/4, 0x0436086c);
37216+ INSTANCE_WR(ctx, 0x3044/4, 0x000c001b);
37217+ INSTANCE_WR(ctx, 0x304c/4, 0x10700ff9);
37218+ INSTANCE_WR(ctx, 0x3050/4, 0x0436086c);
37219+ INSTANCE_WR(ctx, 0x3054/4, 0x000c001b);
37220+ INSTANCE_WR(ctx, 0x305c/4, 0x10700ff9);
37221+ INSTANCE_WR(ctx, 0x3060/4, 0x0436086c);
37222+ INSTANCE_WR(ctx, 0x3064/4, 0x000c001b);
37223+ INSTANCE_WR(ctx, 0x306c/4, 0x10700ff9);
37224+ INSTANCE_WR(ctx, 0x3070/4, 0x0436086c);
37225+ INSTANCE_WR(ctx, 0x3074/4, 0x000c001b);
37226+ INSTANCE_WR(ctx, 0x307c/4, 0x10700ff9);
37227+ INSTANCE_WR(ctx, 0x3080/4, 0x0436086c);
37228+ INSTANCE_WR(ctx, 0x3084/4, 0x000c001b);
37229+ INSTANCE_WR(ctx, 0x308c/4, 0x10700ff9);
37230+ INSTANCE_WR(ctx, 0x3090/4, 0x0436086c);
37231+ INSTANCE_WR(ctx, 0x3094/4, 0x000c001b);
37232+ for(i = 0x30bc; i< 0x30cc; i += 4)
37233+ INSTANCE_WR(ctx, i/4, 0x0000ffff);
37234+ INSTANCE_WR(ctx, 0x3450/4, 0x3f800000);
37235+ INSTANCE_WR(ctx, 0x380c/4, 0x3f800000);
37236+ INSTANCE_WR(ctx, 0x3820/4, 0x3f800000);
37237+ INSTANCE_WR(ctx, 0x384c/4, 0x40000000);
37238+ INSTANCE_WR(ctx, 0x3850/4, 0x3f800000);
37239+ INSTANCE_WR(ctx, 0x3854/4, 0x3f000000);
37240+ INSTANCE_WR(ctx, 0x385c/4, 0x40000000);
37241+ INSTANCE_WR(ctx, 0x3860/4, 0x3f800000);
37242+ INSTANCE_WR(ctx, 0x3868/4, 0xbf800000);
37243+ INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);}
37244+
37245+int nv30_graph_create_context(struct nouveau_channel *chan)
37246+{
37247+ struct drm_device *dev = chan->dev;
37248+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37249+ void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
37250+ unsigned int ctx_size;
37251+ int ret;
37252+
37253+ switch (dev_priv->chipset) {
37254+ case 0x30:
37255+ case 0x31:
37256+ ctx_size = NV30_31_GRCTX_SIZE;
37257+ ctx_init = nv30_31_graph_context_init;
37258+ break;
37259+ case 0x34:
37260+ ctx_size = NV34_GRCTX_SIZE;
37261+ ctx_init = nv34_graph_context_init;
37262+ break;
37263+ case 0x35:
37264+ case 0x36:
37265+ ctx_size = NV35_36_GRCTX_SIZE;
37266+ ctx_init = nv35_36_graph_context_init;
37267+ break;
37268+ default:
37269+ ctx_size = 0;
37270+ ctx_init = nv35_36_graph_context_init;
37271+ DRM_ERROR("Please contact the devs if you want your NV%x card to work\n",dev_priv->chipset);
37272+ break;
37273+ }
37274+
37275+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
37276+ NVOBJ_FLAG_ZERO_ALLOC,
37277+ &chan->ramin_grctx)))
37278+ return ret;
37279+
37280+ /* Initialise default context values */
37281+ ctx_init(dev, chan->ramin_grctx->gpuobj);
37282+
37283+ INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1); /* CTX_USER */
37284+ INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
37285+ chan->ramin_grctx->instance >> 4);
37286+
37287+ return 0;
37288+}
37289+
37290+void nv30_graph_destroy_context(struct nouveau_channel *chan)
37291+{
37292+ struct drm_device *dev = chan->dev;
37293+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37294+
37295+ if (chan->ramin_grctx)
37296+ nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
37297+
37298+ INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
37299+}
37300+
37301+static int
37302+nouveau_graph_wait_idle(struct drm_device *dev)
37303+{
37304+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37305+ int tv = 1000;
37306+
37307+ while (tv--) {
37308+ if (NV_READ(0x400700) == 0)
37309+ break;
37310+ }
37311+
37312+ if (NV_READ(0x400700)) {
37313+ DRM_ERROR("timeout!\n");
37314+ return -EBUSY;
37315+ }
37316+ return 0;
37317+}
37318+
37319+int nv30_graph_load_context(struct nouveau_channel *chan)
37320+{
37321+ struct drm_device *dev = chan->dev;
37322+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37323+ uint32_t inst;
37324+
37325+ if (!chan->ramin_grctx)
37326+ return -EINVAL;
37327+ inst = chan->ramin_grctx->instance >> 4;
37328+
37329+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
37330+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
37331+ NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
37332+
37333+ return nouveau_graph_wait_idle(dev);
37334+}
37335+
37336+int nv30_graph_save_context(struct nouveau_channel *chan)
37337+{
37338+ struct drm_device *dev = chan->dev;
37339+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37340+ uint32_t inst;
37341+
37342+ if (!chan->ramin_grctx)
37343+ return -EINVAL;
37344+ inst = chan->ramin_grctx->instance >> 4;
37345+
37346+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
37347+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
37348+ NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
37349+
37350+ return nouveau_graph_wait_idle(dev);
37351+}
37352+
37353+int nv30_graph_init(struct drm_device *dev)
37354+{
37355+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37356+ uint32_t vramsz, tmp;
37357+ int ret, i;
37358+
37359+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
37360+ ~NV_PMC_ENABLE_PGRAPH);
37361+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
37362+ NV_PMC_ENABLE_PGRAPH);
37363+
37364+ /* Create Context Pointer Table */
37365+ dev_priv->ctx_table_size = 32 * 4;
37366+ if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
37367+ dev_priv->ctx_table_size, 16,
37368+ NVOBJ_FLAG_ZERO_ALLOC,
37369+ &dev_priv->ctx_table)))
37370+ return ret;
37371+
37372+ NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_TABLE,
37373+ dev_priv->ctx_table->instance >> 4);
37374+
37375+ NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
37376+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
37377+
37378+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
37379+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
37380+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);
37381+ NV_WRITE(0x400890, 0x01b463ff);
37382+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf3de0471);
37383+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
37384+ NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
37385+ NV_WRITE(0x400B80, 0x1003d888);
37386+ NV_WRITE(0x400098, 0x00000000);
37387+ NV_WRITE(0x40009C, 0x0005ad00);
37388+ NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2
37389+ NV_WRITE(0x4000a0, 0x00000000);
37390+ NV_WRITE(0x4000a4, 0x00000008);
37391+ NV_WRITE(0x4008a8, 0xb784a400);
37392+ NV_WRITE(0x400ba0, 0x002f8685);
37393+ NV_WRITE(0x400ba4, 0x00231f3f);
37394+ NV_WRITE(0x4008a4, 0x40000020);
37395+ NV_WRITE(0x400B84, 0x0c000000);
37396+ NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x62ff0f7f);
37397+ NV_WRITE(0x4000c0, 0x00000016);
37398+ NV_WRITE(0x400780, 0x000014e4);
37399+
37400+ /* copy tile info from PFB */
37401+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
37402+ NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
37403+ NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
37404+ NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
37405+ NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
37406+ }
37407+
37408+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
37409+ NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
37410+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
37411+
37412+ /* begin RAM config */
37413+ vramsz = drm_get_resource_len(dev, 0) - 1;
37414+ NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
37415+ NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
37416+ NV_WRITE(0x400750, 0x00EA0000);
37417+ NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0));
37418+ NV_WRITE(0x400750, 0x00EA0004);
37419+ NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1));
37420+ NV_WRITE(0x400820, 0);
37421+ NV_WRITE(0x400824, 0);
37422+ NV_WRITE(0x400864, vramsz-1);
37423+ NV_WRITE(0x400868, vramsz-1);
37424+
37425+ NV_WRITE(0x400B20, 0x00000000);
37426+ NV_WRITE(0x400B04, 0xFFFFFFFF);
37427+
37428+ /* per-context state, doesn't belong here */
37429+ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
37430+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
37431+ tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
37432+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
37433+
37434+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
37435+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
37436+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
37437+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
37438+
37439+ return 0;
37440+}
37441+
37442+void nv30_graph_takedown(struct drm_device *dev)
37443+{
37444+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37445+
37446+ nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table);
37447+}
37448+
37449Index: git/shared-core/nv40_fb.c
37450===================================================================
37451--- /dev/null 1970-01-01 00:00:00.000000000 +0000
37452+++ git/shared-core/nv40_fb.c 2008-12-12 17:35:22.000000000 +0000
37453@@ -0,0 +1,56 @@
37454+#include "drmP.h"
37455+#include "drm.h"
37456+#include "nouveau_drv.h"
37457+#include "nouveau_drm.h"
37458+
37459+int
37460+nv40_fb_init(struct drm_device *dev)
37461+{
37462+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37463+ uint32_t fb_bar_size, tmp;
37464+ int num_tiles;
37465+ int i;
37466+
37467+ switch (dev_priv->chipset) {
37468+ case 0x40:
37469+ case 0x45:
37470+ tmp = NV_READ(NV10_PFB_CLOSE_PAGE2);
37471+ NV_WRITE(NV10_PFB_CLOSE_PAGE2, tmp & ~(1<<15));
37472+ num_tiles = NV10_PFB_TILE__SIZE;
37473+ break;
37474+ case 0x46: /* G72 */
37475+ case 0x47: /* G70 */
37476+ case 0x49: /* G71 */
37477+ case 0x4b: /* G73 */
37478+ case 0x4c: /* C51 (G7X version) */
37479+ num_tiles = NV40_PFB_TILE__SIZE_1;
37480+ break;
37481+ default:
37482+ num_tiles = NV40_PFB_TILE__SIZE_0;
37483+ break;
37484+ }
37485+
37486+ fb_bar_size = drm_get_resource_len(dev, 0) - 1;
37487+ switch (dev_priv->chipset) {
37488+ case 0x40:
37489+ for (i=0; i<num_tiles; i++) {
37490+ NV_WRITE(NV10_PFB_TILE(i), 0);
37491+ NV_WRITE(NV10_PFB_TLIMIT(i), fb_bar_size);
37492+ }
37493+ break;
37494+ default:
37495+ for (i=0; i<num_tiles; i++) {
37496+ NV_WRITE(NV40_PFB_TILE(i), 0);
37497+ NV_WRITE(NV40_PFB_TLIMIT(i), fb_bar_size);
37498+ }
37499+ break;
37500+ }
37501+
37502+ return 0;
37503+}
37504+
37505+void
37506+nv40_fb_takedown(struct drm_device *dev)
37507+{
37508+}
37509+
37510Index: git/shared-core/nv40_fifo.c
37511===================================================================
37512--- /dev/null 1970-01-01 00:00:00.000000000 +0000
37513+++ git/shared-core/nv40_fifo.c 2008-12-12 17:35:22.000000000 +0000
37514@@ -0,0 +1,208 @@
37515+/*
37516+ * Copyright (C) 2007 Ben Skeggs.
37517+ * All Rights Reserved.
37518+ *
37519+ * Permission is hereby granted, free of charge, to any person obtaining
37520+ * a copy of this software and associated documentation files (the
37521+ * "Software"), to deal in the Software without restriction, including
37522+ * without limitation the rights to use, copy, modify, merge, publish,
37523+ * distribute, sublicense, and/or sell copies of the Software, and to
37524+ * permit persons to whom the Software is furnished to do so, subject to
37525+ * the following conditions:
37526+ *
37527+ * The above copyright notice and this permission notice (including the
37528+ * next paragraph) shall be included in all copies or substantial
37529+ * portions of the Software.
37530+ *
37531+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37532+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37533+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37534+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37535+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
37536+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37537+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
37538+ *
37539+ */
37540+
37541+#include "drmP.h"
37542+#include "nouveau_drv.h"
37543+#include "nouveau_drm.h"
37544+
37545+
37546+#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
37547+ NV40_RAMFC_##offset/4, (val))
37548+#define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
37549+ NV40_RAMFC_##offset/4)
37550+#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE))
37551+#define NV40_RAMFC__SIZE 128
37552+
37553+int
37554+nv40_fifo_create_context(struct nouveau_channel *chan)
37555+{
37556+ struct drm_device *dev = chan->dev;
37557+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37558+ int ret;
37559+
37560+ if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
37561+ NV40_RAMFC__SIZE,
37562+ NVOBJ_FLAG_ZERO_ALLOC |
37563+ NVOBJ_FLAG_ZERO_FREE,
37564+ NULL, &chan->ramfc)))
37565+ return ret;
37566+
37567+ /* Fill entries that are seen filled in dumps of nvidia driver just
37568+ * after channel's is put into DMA mode
37569+ */
37570+ RAMFC_WR(DMA_PUT , chan->pushbuf_base);
37571+ RAMFC_WR(DMA_GET , chan->pushbuf_base);
37572+ RAMFC_WR(DMA_INSTANCE , chan->pushbuf->instance >> 4);
37573+ RAMFC_WR(DMA_FETCH , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
37574+ NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
37575+ NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
37576+#ifdef __BIG_ENDIAN
37577+ NV_PFIFO_CACHE1_BIG_ENDIAN |
37578+#endif
37579+ 0x30000000 /* no idea.. */);
37580+ RAMFC_WR(DMA_SUBROUTINE, 0);
37581+ RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4);
37582+ RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
37583+
37584+ /* enable the fifo dma operation */
37585+ NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
37586+ return 0;
37587+}
37588+
37589+void
37590+nv40_fifo_destroy_context(struct nouveau_channel *chan)
37591+{
37592+ struct drm_device *dev = chan->dev;
37593+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37594+
37595+ NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
37596+
37597+ if (chan->ramfc)
37598+ nouveau_gpuobj_ref_del(dev, &chan->ramfc);
37599+}
37600+
37601+int
37602+nv40_fifo_load_context(struct nouveau_channel *chan)
37603+{
37604+ struct drm_device *dev = chan->dev;
37605+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37606+ uint32_t tmp, tmp2;
37607+
37608+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
37609+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
37610+ NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT));
37611+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE , RAMFC_RD(DMA_INSTANCE));
37612+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT , RAMFC_RD(DMA_DCOUNT));
37613+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE , RAMFC_RD(DMA_STATE));
37614+
37615+ /* No idea what 0x2058 is.. */
37616+ tmp = RAMFC_RD(DMA_FETCH);
37617+ tmp2 = NV_READ(0x2058) & 0xFFF;
37618+ tmp2 |= (tmp & 0x30000000);
37619+ NV_WRITE(0x2058, tmp2);
37620+ tmp &= ~0x30000000;
37621+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH , tmp);
37622+
37623+ NV_WRITE(NV04_PFIFO_CACHE1_ENGINE , RAMFC_RD(ENGINE));
37624+ NV_WRITE(NV04_PFIFO_CACHE1_PULL1 , RAMFC_RD(PULL1_ENGINE));
37625+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE , RAMFC_RD(ACQUIRE_VALUE));
37626+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, RAMFC_RD(ACQUIRE_TIMESTAMP));
37627+ NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT , RAMFC_RD(ACQUIRE_TIMEOUT));
37628+ NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE , RAMFC_RD(SEMAPHORE));
37629+ NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE , RAMFC_RD(DMA_SUBROUTINE));
37630+ NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE , RAMFC_RD(GRCTX_INSTANCE));
37631+ NV_WRITE(0x32e4, RAMFC_RD(UNK_40));
37632+ /* NVIDIA does this next line twice... */
37633+ NV_WRITE(0x32e8, RAMFC_RD(UNK_44));
37634+ NV_WRITE(0x2088, RAMFC_RD(UNK_4C));
37635+ NV_WRITE(0x3300, RAMFC_RD(UNK_50));
37636+
37637+ /* not sure what part is PUT, and which is GET.. never seen a non-zero
37638+ * value appear in a mmio-trace yet..
37639+ */
37640+#if 0
37641+ tmp = NV_READ(UNK_84);
37642+ NV_WRITE(NV_PFIFO_CACHE1_GET, tmp ???);
37643+ NV_WRITE(NV_PFIFO_CACHE1_PUT, tmp ???);
37644+#endif
37645+
37646+ /* Don't clobber the TIMEOUT_ENABLED flag when restoring from RAMFC */
37647+ tmp = NV_READ(NV04_PFIFO_DMA_TIMESLICE) & ~0x1FFFF;
37648+ tmp |= RAMFC_RD(DMA_TIMESLICE) & 0x1FFFF;
37649+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
37650+
37651+ /* Set channel active, and in DMA mode */
37652+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | chan->id);
37653+ /* Reset DMA_CTL_AT_INFO to INVALID */
37654+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
37655+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
37656+
37657+ return 0;
37658+}
37659+
37660+int
37661+nv40_fifo_save_context(struct nouveau_channel *chan)
37662+{
37663+ struct drm_device *dev = chan->dev;
37664+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37665+ uint32_t tmp;
37666+
37667+ RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
37668+ RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
37669+ RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
37670+ RAMFC_WR(DMA_INSTANCE , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
37671+ RAMFC_WR(DMA_DCOUNT , NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT));
37672+ RAMFC_WR(DMA_STATE , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
37673+
37674+ tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH);
37675+ tmp |= NV_READ(0x2058) & 0x30000000;
37676+ RAMFC_WR(DMA_FETCH , tmp);
37677+
37678+ RAMFC_WR(ENGINE , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
37679+ RAMFC_WR(PULL1_ENGINE , NV_READ(NV04_PFIFO_CACHE1_PULL1));
37680+ RAMFC_WR(ACQUIRE_VALUE , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
37681+ tmp = NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
37682+ RAMFC_WR(ACQUIRE_TIMESTAMP, tmp);
37683+ RAMFC_WR(ACQUIRE_TIMEOUT , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
37684+ RAMFC_WR(SEMAPHORE , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
37685+
37686+ /* NVIDIA read 0x3228 first, then write DMA_GET here.. maybe something
37687+ * more involved depending on the value of 0x3228?
37688+ */
37689+ RAMFC_WR(DMA_SUBROUTINE , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
37690+
37691+ RAMFC_WR(GRCTX_INSTANCE , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
37692+
37693+ /* No idea what the below is for exactly, ripped from a mmio-trace */
37694+ RAMFC_WR(UNK_40 , NV_READ(NV40_PFIFO_UNK32E4));
37695+
37696+ /* NVIDIA do this next line twice.. bug? */
37697+ RAMFC_WR(UNK_44 , NV_READ(0x32e8));
37698+ RAMFC_WR(UNK_4C , NV_READ(0x2088));
37699+ RAMFC_WR(UNK_50 , NV_READ(0x3300));
37700+
37701+#if 0 /* no real idea which is PUT/GET in UNK_48.. */
37702+ tmp = NV_READ(NV04_PFIFO_CACHE1_GET);
37703+ tmp |= (NV_READ(NV04_PFIFO_CACHE1_PUT) << 16);
37704+ RAMFC_WR(UNK_48 , tmp);
37705+#endif
37706+
37707+ return 0;
37708+}
37709+
37710+int
37711+nv40_fifo_init(struct drm_device *dev)
37712+{
37713+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37714+ int ret;
37715+
37716+ if ((ret = nouveau_fifo_init(dev)))
37717+ return ret;
37718+
37719+ NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
37720+ return 0;
37721+}
37722+
37723Index: git/shared-core/nv40_graph.c
37724===================================================================
37725--- /dev/null 1970-01-01 00:00:00.000000000 +0000
37726+++ git/shared-core/nv40_graph.c 2008-12-12 17:35:22.000000000 +0000
37727@@ -0,0 +1,2055 @@
37728+/*
37729+ * Copyright (C) 2007 Ben Skeggs.
37730+ * All Rights Reserved.
37731+ *
37732+ * Permission is hereby granted, free of charge, to any person obtaining
37733+ * a copy of this software and associated documentation files (the
37734+ * "Software"), to deal in the Software without restriction, including
37735+ * without limitation the rights to use, copy, modify, merge, publish,
37736+ * distribute, sublicense, and/or sell copies of the Software, and to
37737+ * permit persons to whom the Software is furnished to do so, subject to
37738+ * the following conditions:
37739+ *
37740+ * The above copyright notice and this permission notice (including the
37741+ * next paragraph) shall be included in all copies or substantial
37742+ * portions of the Software.
37743+ *
37744+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37745+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37746+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37747+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37748+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
37749+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37750+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
37751+ *
37752+ */
37753+
37754+#include "drmP.h"
37755+#include "drm.h"
37756+#include "nouveau_drv.h"
37757+
37758+/* The sizes are taken from the difference between the start of two
37759+ * grctx addresses while running the nvidia driver. Probably slightly
37760+ * larger than they actually are, because of other objects being created
37761+ * between the contexts
37762+ */
37763+#define NV40_GRCTX_SIZE (175*1024)
37764+#define NV41_GRCTX_SIZE (92*1024)
37765+#define NV43_GRCTX_SIZE (70*1024)
37766+#define NV46_GRCTX_SIZE (70*1024) /* probably ~64KiB */
37767+#define NV49_GRCTX_SIZE (164640)
37768+#define NV4A_GRCTX_SIZE (64*1024)
37769+#define NV4B_GRCTX_SIZE (164640)
37770+#define NV4C_GRCTX_SIZE (25*1024)
37771+#define NV4E_GRCTX_SIZE (25*1024)
37772+
37773+/*TODO: deciper what each offset in the context represents. The below
37774+ * contexts are taken from dumps just after the 3D object is
37775+ * created.
37776+ */
37777+static void
37778+nv40_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
37779+{
37780+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37781+ int i;
37782+
37783+ /* Always has the "instance address" of itself at offset 0 */
37784+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
37785+ /* unknown */
37786+ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
37787+ INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
37788+ INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
37789+ INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
37790+ INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
37791+ INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
37792+ INSTANCE_WR(ctx, 0x0016c/4, 0x00000040);
37793+ INSTANCE_WR(ctx, 0x00170/4, 0x00000040);
37794+ INSTANCE_WR(ctx, 0x00174/4, 0x00000040);
37795+ INSTANCE_WR(ctx, 0x0017c/4, 0x80000000);
37796+ INSTANCE_WR(ctx, 0x00180/4, 0x80000000);
37797+ INSTANCE_WR(ctx, 0x00184/4, 0x80000000);
37798+ INSTANCE_WR(ctx, 0x00188/4, 0x80000000);
37799+ INSTANCE_WR(ctx, 0x0018c/4, 0x80000000);
37800+ INSTANCE_WR(ctx, 0x0019c/4, 0x00000040);
37801+ INSTANCE_WR(ctx, 0x001a0/4, 0x80000000);
37802+ INSTANCE_WR(ctx, 0x001b0/4, 0x80000000);
37803+ INSTANCE_WR(ctx, 0x001c0/4, 0x80000000);
37804+ INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
37805+ INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
37806+ INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
37807+ INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
37808+ INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
37809+ INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
37810+ INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
37811+ INSTANCE_WR(ctx, 0x0039c/4, 0x00000010);
37812+ INSTANCE_WR(ctx, 0x00480/4, 0x00000100);
37813+ INSTANCE_WR(ctx, 0x00494/4, 0x00000111);
37814+ INSTANCE_WR(ctx, 0x00498/4, 0x00080060);
37815+ INSTANCE_WR(ctx, 0x004b4/4, 0x00000080);
37816+ INSTANCE_WR(ctx, 0x004b8/4, 0xffff0000);
37817+ INSTANCE_WR(ctx, 0x004bc/4, 0x00000001);
37818+ INSTANCE_WR(ctx, 0x004d0/4, 0x46400000);
37819+ INSTANCE_WR(ctx, 0x004ec/4, 0xffff0000);
37820+ INSTANCE_WR(ctx, 0x004f8/4, 0x0fff0000);
37821+ INSTANCE_WR(ctx, 0x004fc/4, 0x0fff0000);
37822+ INSTANCE_WR(ctx, 0x00504/4, 0x00011100);
37823+ for (i=0x00520; i<=0x0055c; i+=4)
37824+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
37825+ INSTANCE_WR(ctx, 0x00568/4, 0x4b7fffff);
37826+ INSTANCE_WR(ctx, 0x00594/4, 0x30201000);
37827+ INSTANCE_WR(ctx, 0x00598/4, 0x70605040);
37828+ INSTANCE_WR(ctx, 0x0059c/4, 0xb8a89888);
37829+ INSTANCE_WR(ctx, 0x005a0/4, 0xf8e8d8c8);
37830+ INSTANCE_WR(ctx, 0x005b4/4, 0x40100000);
37831+ INSTANCE_WR(ctx, 0x005cc/4, 0x00000004);
37832+ INSTANCE_WR(ctx, 0x005d8/4, 0x0000ffff);
37833+ INSTANCE_WR(ctx, 0x0060c/4, 0x435185d6);
37834+ INSTANCE_WR(ctx, 0x00610/4, 0x2155b699);
37835+ INSTANCE_WR(ctx, 0x00614/4, 0xfedcba98);
37836+ INSTANCE_WR(ctx, 0x00618/4, 0x00000098);
37837+ INSTANCE_WR(ctx, 0x00628/4, 0xffffffff);
37838+ INSTANCE_WR(ctx, 0x0062c/4, 0x00ff7000);
37839+ INSTANCE_WR(ctx, 0x00630/4, 0x0000ffff);
37840+ INSTANCE_WR(ctx, 0x00640/4, 0x00ff0000);
37841+ INSTANCE_WR(ctx, 0x0067c/4, 0x00ffff00);
37842+ /* 0x680-0x6BC - NV30_TCL_PRIMITIVE_3D_TX_ADDRESS_UNIT(0-15) */
37843+ /* 0x6C0-0x6FC - NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT(0-15) */
37844+ for (i=0x006C0; i<=0x006fc; i+=4)
37845+ INSTANCE_WR(ctx, i/4, 0x00018488);
37846+ /* 0x700-0x73C - NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT(0-15) */
37847+ for (i=0x00700; i<=0x0073c; i+=4)
37848+ INSTANCE_WR(ctx, i/4, 0x00028202);
37849+ /* 0x740-0x77C - NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT(0-15) */
37850+ /* 0x780-0x7BC - NV30_TCL_PRIMITIVE_3D_TX_SWIZZLE_UNIT(0-15) */
37851+ for (i=0x00780; i<=0x007bc; i+=4)
37852+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
37853+ /* 0x7C0-0x7FC - NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT(0-15) */
37854+ for (i=0x007c0; i<=0x007fc; i+=4)
37855+ INSTANCE_WR(ctx, i/4, 0x01012000);
37856+ /* 0x800-0x83C - NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT(0-15) */
37857+ for (i=0x00800; i<=0x0083c; i+=4)
37858+ INSTANCE_WR(ctx, i/4, 0x00080008);
37859+ /* 0x840-0x87C - NV30_TCL_PRIMITIVE_3D_TX_UNK07_UNIT(0-15) */
37860+ /* 0x880-0x8BC - NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT(0-15) */
37861+ for (i=0x00880; i<=0x008bc; i+=4)
37862+ INSTANCE_WR(ctx, i/4, 0x00100008);
37863+ /* unknown */
37864+ for (i=0x00910; i<=0x0091c; i+=4)
37865+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
37866+ for (i=0x00920; i<=0x0092c; i+=4)
37867+ INSTANCE_WR(ctx, i/4, 0x00000202);
37868+ for (i=0x00940; i<=0x0094c; i+=4)
37869+ INSTANCE_WR(ctx, i/4, 0x00000008);
37870+ for (i=0x00960; i<=0x0096c; i+=4)
37871+ INSTANCE_WR(ctx, i/4, 0x00080008);
37872+ INSTANCE_WR(ctx, 0x00980/4, 0x00000002);
37873+ INSTANCE_WR(ctx, 0x009b4/4, 0x00000001);
37874+ INSTANCE_WR(ctx, 0x009c0/4, 0x3e020200);
37875+ INSTANCE_WR(ctx, 0x009c4/4, 0x00ffffff);
37876+ INSTANCE_WR(ctx, 0x009c8/4, 0x60103f00);
37877+ INSTANCE_WR(ctx, 0x009d4/4, 0x00020000);
37878+ INSTANCE_WR(ctx, 0x00a08/4, 0x00008100);
37879+ INSTANCE_WR(ctx, 0x00aac/4, 0x00000001);
37880+ INSTANCE_WR(ctx, 0x00af0/4, 0x00000001);
37881+ INSTANCE_WR(ctx, 0x00af8/4, 0x80800001);
37882+ INSTANCE_WR(ctx, 0x00bcc/4, 0x00000005);
37883+ INSTANCE_WR(ctx, 0x00bf8/4, 0x00005555);
37884+ INSTANCE_WR(ctx, 0x00bfc/4, 0x00005555);
37885+ INSTANCE_WR(ctx, 0x00c00/4, 0x00005555);
37886+ INSTANCE_WR(ctx, 0x00c04/4, 0x00005555);
37887+ INSTANCE_WR(ctx, 0x00c08/4, 0x00005555);
37888+ INSTANCE_WR(ctx, 0x00c0c/4, 0x00005555);
37889+ INSTANCE_WR(ctx, 0x00c44/4, 0x00000001);
37890+ for (i=0x03008; i<=0x03080; i+=8)
37891+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37892+ for (i=0x05288; i<=0x08570; i+=24)
37893+ INSTANCE_WR(ctx, i/4, 0x00000001);
37894+ for (i=0x08628; i<=0x08e18; i+=16)
37895+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37896+ for (i=0x0bd28; i<=0x0f010; i+=24)
37897+ INSTANCE_WR(ctx, i/4, 0x00000001);
37898+ for (i=0x0f0c8; i<=0x0f8b8; i+=16)
37899+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37900+ for (i=0x127c8; i<=0x15ab0; i+=24)
37901+ INSTANCE_WR(ctx, i/4, 0x00000001);
37902+ for (i=0x15b68; i<=0x16358; i+=16)
37903+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37904+ for (i=0x19268; i<=0x1c550; i+=24)
37905+ INSTANCE_WR(ctx, i/4, 0x00000001);
37906+ for (i=0x1c608; i<=0x1cdf8; i+=16)
37907+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37908+ for (i=0x1fd08; i<=0x22ff0; i+=24)
37909+ INSTANCE_WR(ctx, i/4, 0x00000001);
37910+ for (i=0x230a8; i<=0x23898; i+=16)
37911+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37912+ for (i=0x267a8; i<=0x29a90; i+=24)
37913+ INSTANCE_WR(ctx, i/4, 0x00000001);
37914+ for (i=0x29b48; i<=0x2a338; i+=16)
37915+ INSTANCE_WR(ctx, i/4, 0x3f800000);
37916+}
37917+
37918+static void
37919+nv41_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
37920+{
37921+ struct drm_nouveau_private *dev_priv = dev->dev_private;
37922+ int i;
37923+
37924+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
37925+ INSTANCE_WR(ctx, 0x00000024/4, 0x0000ffff);
37926+ INSTANCE_WR(ctx, 0x00000028/4, 0x0000ffff);
37927+ INSTANCE_WR(ctx, 0x00000030/4, 0x00000001);
37928+ INSTANCE_WR(ctx, 0x0000011c/4, 0x20010001);
37929+ INSTANCE_WR(ctx, 0x00000120/4, 0x0f73ef00);
37930+ INSTANCE_WR(ctx, 0x00000128/4, 0x02008821);
37931+ for (i = 0x00000178; i <= 0x00000180; i += 4)
37932+ INSTANCE_WR(ctx, i/4, 0x00000040);
37933+ INSTANCE_WR(ctx, 0x00000188/4, 0x00000040);
37934+ for (i = 0x00000194; i <= 0x000001b0; i += 4)
37935+ INSTANCE_WR(ctx, i/4, 0x80000000);
37936+ INSTANCE_WR(ctx, 0x000001d0/4, 0x0b0b0b0c);
37937+ INSTANCE_WR(ctx, 0x00000340/4, 0x00040000);
37938+ for (i = 0x00000350; i <= 0x0000035c; i += 4)
37939+ INSTANCE_WR(ctx, i/4, 0x55555555);
37940+ INSTANCE_WR(ctx, 0x00000388/4, 0x00000008);
37941+ INSTANCE_WR(ctx, 0x0000039c/4, 0x00001010);
37942+ INSTANCE_WR(ctx, 0x000003cc/4, 0x00000111);
37943+ INSTANCE_WR(ctx, 0x000003d0/4, 0x00080060);
37944+ INSTANCE_WR(ctx, 0x000003ec/4, 0x00000080);
37945+ INSTANCE_WR(ctx, 0x000003f0/4, 0xffff0000);
37946+ INSTANCE_WR(ctx, 0x000003f4/4, 0x00000001);
37947+ INSTANCE_WR(ctx, 0x00000408/4, 0x46400000);
37948+ INSTANCE_WR(ctx, 0x00000418/4, 0xffff0000);
37949+ INSTANCE_WR(ctx, 0x00000424/4, 0x0fff0000);
37950+ INSTANCE_WR(ctx, 0x00000428/4, 0x0fff0000);
37951+ INSTANCE_WR(ctx, 0x00000430/4, 0x00011100);
37952+ for (i = 0x0000044c; i <= 0x00000488; i += 4)
37953+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
37954+ INSTANCE_WR(ctx, 0x00000494/4, 0x4b7fffff);
37955+ INSTANCE_WR(ctx, 0x000004bc/4, 0x30201000);
37956+ INSTANCE_WR(ctx, 0x000004c0/4, 0x70605040);
37957+ INSTANCE_WR(ctx, 0x000004c4/4, 0xb8a89888);
37958+ INSTANCE_WR(ctx, 0x000004c8/4, 0xf8e8d8c8);
37959+ INSTANCE_WR(ctx, 0x000004dc/4, 0x40100000);
37960+ INSTANCE_WR(ctx, 0x000004f8/4, 0x0000ffff);
37961+ INSTANCE_WR(ctx, 0x0000052c/4, 0x435185d6);
37962+ INSTANCE_WR(ctx, 0x00000530/4, 0x2155b699);
37963+ INSTANCE_WR(ctx, 0x00000534/4, 0xfedcba98);
37964+ INSTANCE_WR(ctx, 0x00000538/4, 0x00000098);
37965+ INSTANCE_WR(ctx, 0x00000548/4, 0xffffffff);
37966+ INSTANCE_WR(ctx, 0x0000054c/4, 0x00ff7000);
37967+ INSTANCE_WR(ctx, 0x00000550/4, 0x0000ffff);
37968+ INSTANCE_WR(ctx, 0x00000560/4, 0x00ff0000);
37969+ INSTANCE_WR(ctx, 0x00000598/4, 0x00ffff00);
37970+ for (i = 0x000005dc; i <= 0x00000618; i += 4)
37971+ INSTANCE_WR(ctx, i/4, 0x00018488);
37972+ for (i = 0x0000061c; i <= 0x00000658; i += 4)
37973+ INSTANCE_WR(ctx, i/4, 0x00028202);
37974+ for (i = 0x0000069c; i <= 0x000006d8; i += 4)
37975+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
37976+ for (i = 0x000006dc; i <= 0x00000718; i += 4)
37977+ INSTANCE_WR(ctx, i/4, 0x01012000);
37978+ for (i = 0x0000071c; i <= 0x00000758; i += 4)
37979+ INSTANCE_WR(ctx, i/4, 0x00080008);
37980+ for (i = 0x0000079c; i <= 0x000007d8; i += 4)
37981+ INSTANCE_WR(ctx, i/4, 0x00100008);
37982+ for (i = 0x0000082c; i <= 0x00000838; i += 4)
37983+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
37984+ for (i = 0x0000083c; i <= 0x00000848; i += 4)
37985+ INSTANCE_WR(ctx, i/4, 0x00000202);
37986+ for (i = 0x0000085c; i <= 0x00000868; i += 4)
37987+ INSTANCE_WR(ctx, i/4, 0x00000008);
37988+ for (i = 0x0000087c; i <= 0x00000888; i += 4)
37989+ INSTANCE_WR(ctx, i/4, 0x00080008);
37990+ INSTANCE_WR(ctx, 0x0000089c/4, 0x00000002);
37991+ INSTANCE_WR(ctx, 0x000008d0/4, 0x00000021);
37992+ INSTANCE_WR(ctx, 0x000008d4/4, 0x030c30c3);
37993+ INSTANCE_WR(ctx, 0x000008e0/4, 0x3e020200);
37994+ INSTANCE_WR(ctx, 0x000008e4/4, 0x00ffffff);
37995+ INSTANCE_WR(ctx, 0x000008e8/4, 0x20103f00);
37996+ INSTANCE_WR(ctx, 0x000008f4/4, 0x00020000);
37997+ INSTANCE_WR(ctx, 0x0000092c/4, 0x00008100);
37998+ INSTANCE_WR(ctx, 0x000009b8/4, 0x00000001);
37999+ INSTANCE_WR(ctx, 0x000009fc/4, 0x00001001);
38000+ INSTANCE_WR(ctx, 0x00000a04/4, 0x00000003);
38001+ INSTANCE_WR(ctx, 0x00000a08/4, 0x00888001);
38002+ INSTANCE_WR(ctx, 0x00000aac/4, 0x00000005);
38003+ INSTANCE_WR(ctx, 0x00000ab8/4, 0x0000ffff);
38004+ for (i = 0x00000ad4; i <= 0x00000ae4; i += 4)
38005+ INSTANCE_WR(ctx, i/4, 0x00005555);
38006+ INSTANCE_WR(ctx, 0x00000ae8/4, 0x00000001);
38007+ INSTANCE_WR(ctx, 0x00000b20/4, 0x00000001);
38008+ for (i = 0x00002ee8; i <= 0x00002f60; i += 8)
38009+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38010+ for (i = 0x00005168; i <= 0x00007358; i += 24)
38011+ INSTANCE_WR(ctx, i/4, 0x00000001);
38012+ for (i = 0x00007368; i <= 0x00007758; i += 16)
38013+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38014+ for (i = 0x0000a068; i <= 0x0000c258; i += 24)
38015+ INSTANCE_WR(ctx, i/4, 0x00000001);
38016+ for (i = 0x0000c268; i <= 0x0000c658; i += 16)
38017+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38018+ for (i = 0x0000ef68; i <= 0x00011158; i += 24)
38019+ INSTANCE_WR(ctx, i/4, 0x00000001);
38020+ for (i = 0x00011168; i <= 0x00011558; i += 16)
38021+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38022+ for (i = 0x00013e68; i <= 0x00016058; i += 24)
38023+ INSTANCE_WR(ctx, i/4, 0x00000001);
38024+ for (i = 0x00016068; i <= 0x00016458; i += 16)
38025+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38026+};
38027+
38028+static void
38029+nv43_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38030+{
38031+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38032+ int i;
38033+
38034+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38035+ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
38036+ INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
38037+ INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
38038+ INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
38039+ INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
38040+ INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
38041+ INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
38042+ INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
38043+ INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
38044+ INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
38045+ INSTANCE_WR(ctx, 0x00194/4, 0x80000000);
38046+ INSTANCE_WR(ctx, 0x00198/4, 0x80000000);
38047+ INSTANCE_WR(ctx, 0x0019c/4, 0x80000000);
38048+ INSTANCE_WR(ctx, 0x001a0/4, 0x80000000);
38049+ INSTANCE_WR(ctx, 0x001a4/4, 0x80000000);
38050+ INSTANCE_WR(ctx, 0x001a8/4, 0x80000000);
38051+ INSTANCE_WR(ctx, 0x001ac/4, 0x80000000);
38052+ INSTANCE_WR(ctx, 0x001b0/4, 0x80000000);
38053+ INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
38054+ INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
38055+ INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
38056+ INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
38057+ INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
38058+ INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
38059+ INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
38060+ INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);
38061+ INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);
38062+ INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);
38063+ INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);
38064+ INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);
38065+ INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);
38066+ INSTANCE_WR(ctx, 0x00408/4, 0x46400000);
38067+ INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);
38068+ INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);
38069+ INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
38070+ INSTANCE_WR(ctx, 0x00430/4, 0x00011100);
38071+ for (i=0x0044c; i<=0x00488; i+=4)
38072+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
38073+ INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);
38074+ INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);
38075+ INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);
38076+ INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);
38077+ INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);
38078+ INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);
38079+ INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);
38080+ INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);
38081+ INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);
38082+ INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);
38083+ INSTANCE_WR(ctx, 0x00538/4, 0x00000098);
38084+ INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);
38085+ INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);
38086+ INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);
38087+ INSTANCE_WR(ctx, 0x00560/4, 0x00ff0000);
38088+ INSTANCE_WR(ctx, 0x00598/4, 0x00ffff00);
38089+ for (i=0x005dc; i<=0x00618; i+=4)
38090+ INSTANCE_WR(ctx, i/4, 0x00018488);
38091+ for (i=0x0061c; i<=0x00658; i+=4)
38092+ INSTANCE_WR(ctx, i/4, 0x00028202);
38093+ for (i=0x0069c; i<=0x006d8; i+=4)
38094+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38095+ for (i=0x006dc; i<=0x00718; i+=4)
38096+ INSTANCE_WR(ctx, i/4, 0x01012000);
38097+ for (i=0x0071c; i<=0x00758; i+=4)
38098+ INSTANCE_WR(ctx, i/4, 0x00080008);
38099+ for (i=0x0079c; i<=0x007d8; i+=4)
38100+ INSTANCE_WR(ctx, i/4, 0x00100008);
38101+ for (i=0x0082c; i<=0x00838; i+=4)
38102+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38103+ for (i=0x0083c; i<=0x00848; i+=4)
38104+ INSTANCE_WR(ctx, i/4, 0x00000202);
38105+ for (i=0x0085c; i<=0x00868; i+=4)
38106+ INSTANCE_WR(ctx, i/4, 0x00000008);
38107+ for (i=0x0087c; i<=0x00888; i+=4)
38108+ INSTANCE_WR(ctx, i/4, 0x00080008);
38109+ INSTANCE_WR(ctx, 0x0089c/4, 0x00000002);
38110+ INSTANCE_WR(ctx, 0x008d0/4, 0x00000021);
38111+ INSTANCE_WR(ctx, 0x008d4/4, 0x030c30c3);
38112+ INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);
38113+ INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);
38114+ INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);
38115+ INSTANCE_WR(ctx, 0x008f4/4, 0x00020000);
38116+ INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);
38117+ INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);
38118+ INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);
38119+ INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);
38120+ INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);
38121+ INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005);
38122+ INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff);
38123+ INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555);
38124+ INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555);
38125+ INSTANCE_WR(ctx, 0x00abc/4, 0x00005555);
38126+ INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001);
38127+ INSTANCE_WR(ctx, 0x00af8/4, 0x00000001);
38128+ for (i=0x02ec0; i<=0x02f38; i+=8)
38129+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38130+ for (i=0x04c80; i<=0x06e70; i+=24)
38131+ INSTANCE_WR(ctx, i/4, 0x00000001);
38132+ for (i=0x06e80; i<=0x07270; i+=16)
38133+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38134+ for (i=0x096c0; i<=0x0b8b0; i+=24)
38135+ INSTANCE_WR(ctx, i/4, 0x00000001);
38136+ for (i=0x0b8c0; i<=0x0bcb0; i+=16)
38137+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38138+ for (i=0x0e100; i<=0x102f0; i+=24)
38139+ INSTANCE_WR(ctx, i/4, 0x00000001);
38140+ for (i=0x10300; i<=0x106f0; i+=16)
38141+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38142+};
38143+
38144+static void
38145+nv46_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38146+{
38147+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38148+ int i;
38149+
38150+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38151+ INSTANCE_WR(ctx, 0x00040/4, 0x0000ffff);
38152+ INSTANCE_WR(ctx, 0x00044/4, 0x0000ffff);
38153+ INSTANCE_WR(ctx, 0x0004c/4, 0x00000001);
38154+ INSTANCE_WR(ctx, 0x00138/4, 0x20010001);
38155+ INSTANCE_WR(ctx, 0x0013c/4, 0x0f73ef00);
38156+ INSTANCE_WR(ctx, 0x00144/4, 0x02008821);
38157+ INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
38158+ INSTANCE_WR(ctx, 0x00178/4, 0x00000001);
38159+ INSTANCE_WR(ctx, 0x0017c/4, 0x00000001);
38160+ INSTANCE_WR(ctx, 0x00180/4, 0x00000001);
38161+ INSTANCE_WR(ctx, 0x00184/4, 0x00000001);
38162+ INSTANCE_WR(ctx, 0x00188/4, 0x00000001);
38163+ INSTANCE_WR(ctx, 0x0018c/4, 0x00000001);
38164+ INSTANCE_WR(ctx, 0x00190/4, 0x00000001);
38165+ INSTANCE_WR(ctx, 0x00194/4, 0x00000040);
38166+ INSTANCE_WR(ctx, 0x00198/4, 0x00000040);
38167+ INSTANCE_WR(ctx, 0x0019c/4, 0x00000040);
38168+ INSTANCE_WR(ctx, 0x001a4/4, 0x00000040);
38169+ INSTANCE_WR(ctx, 0x001ec/4, 0x0b0b0b0c);
38170+ INSTANCE_WR(ctx, 0x0035c/4, 0x00040000);
38171+ INSTANCE_WR(ctx, 0x0036c/4, 0x55555555);
38172+ INSTANCE_WR(ctx, 0x00370/4, 0x55555555);
38173+ INSTANCE_WR(ctx, 0x00374/4, 0x55555555);
38174+ INSTANCE_WR(ctx, 0x00378/4, 0x55555555);
38175+ INSTANCE_WR(ctx, 0x003a4/4, 0x00000008);
38176+ INSTANCE_WR(ctx, 0x003b8/4, 0x00003010);
38177+ INSTANCE_WR(ctx, 0x003dc/4, 0x00000111);
38178+ INSTANCE_WR(ctx, 0x003e0/4, 0x00000111);
38179+ INSTANCE_WR(ctx, 0x003e4/4, 0x00000111);
38180+ INSTANCE_WR(ctx, 0x003e8/4, 0x00000111);
38181+ INSTANCE_WR(ctx, 0x003ec/4, 0x00000111);
38182+ INSTANCE_WR(ctx, 0x003f0/4, 0x00000111);
38183+ INSTANCE_WR(ctx, 0x003f4/4, 0x00000111);
38184+ INSTANCE_WR(ctx, 0x003f8/4, 0x00000111);
38185+ INSTANCE_WR(ctx, 0x003fc/4, 0x00000111);
38186+ INSTANCE_WR(ctx, 0x00400/4, 0x00000111);
38187+ INSTANCE_WR(ctx, 0x00404/4, 0x00000111);
38188+ INSTANCE_WR(ctx, 0x00408/4, 0x00000111);
38189+ INSTANCE_WR(ctx, 0x0040c/4, 0x00000111);
38190+ INSTANCE_WR(ctx, 0x00410/4, 0x00000111);
38191+ INSTANCE_WR(ctx, 0x00414/4, 0x00000111);
38192+ INSTANCE_WR(ctx, 0x00418/4, 0x00000111);
38193+ INSTANCE_WR(ctx, 0x004b0/4, 0x00000111);
38194+ INSTANCE_WR(ctx, 0x004b4/4, 0x00080060);
38195+ INSTANCE_WR(ctx, 0x004d0/4, 0x00000080);
38196+ INSTANCE_WR(ctx, 0x004d4/4, 0xffff0000);
38197+ INSTANCE_WR(ctx, 0x004d8/4, 0x00000001);
38198+ INSTANCE_WR(ctx, 0x004ec/4, 0x46400000);
38199+ INSTANCE_WR(ctx, 0x004fc/4, 0xffff0000);
38200+ INSTANCE_WR(ctx, 0x00500/4, 0x88888888);
38201+ INSTANCE_WR(ctx, 0x00504/4, 0x88888888);
38202+ INSTANCE_WR(ctx, 0x00508/4, 0x88888888);
38203+ INSTANCE_WR(ctx, 0x0050c/4, 0x88888888);
38204+ INSTANCE_WR(ctx, 0x00510/4, 0x88888888);
38205+ INSTANCE_WR(ctx, 0x00514/4, 0x88888888);
38206+ INSTANCE_WR(ctx, 0x00518/4, 0x88888888);
38207+ INSTANCE_WR(ctx, 0x0051c/4, 0x88888888);
38208+ INSTANCE_WR(ctx, 0x00520/4, 0x88888888);
38209+ INSTANCE_WR(ctx, 0x00524/4, 0x88888888);
38210+ INSTANCE_WR(ctx, 0x00528/4, 0x88888888);
38211+ INSTANCE_WR(ctx, 0x0052c/4, 0x88888888);
38212+ INSTANCE_WR(ctx, 0x00530/4, 0x88888888);
38213+ INSTANCE_WR(ctx, 0x00534/4, 0x88888888);
38214+ INSTANCE_WR(ctx, 0x00538/4, 0x88888888);
38215+ INSTANCE_WR(ctx, 0x0053c/4, 0x88888888);
38216+ INSTANCE_WR(ctx, 0x00550/4, 0x0fff0000);
38217+ INSTANCE_WR(ctx, 0x00554/4, 0x0fff0000);
38218+ INSTANCE_WR(ctx, 0x0055c/4, 0x00011100);
38219+ for (i=0x00578; i<0x005b4; i+=4)
38220+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
38221+ INSTANCE_WR(ctx, 0x005c0/4, 0x4b7fffff);
38222+ INSTANCE_WR(ctx, 0x005e8/4, 0x30201000);
38223+ INSTANCE_WR(ctx, 0x005ec/4, 0x70605040);
38224+ INSTANCE_WR(ctx, 0x005f0/4, 0xb8a89888);
38225+ INSTANCE_WR(ctx, 0x005f4/4, 0xf8e8d8c8);
38226+ INSTANCE_WR(ctx, 0x00608/4, 0x40100000);
38227+ INSTANCE_WR(ctx, 0x00624/4, 0x0000ffff);
38228+ INSTANCE_WR(ctx, 0x00658/4, 0x435185d6);
38229+ INSTANCE_WR(ctx, 0x0065c/4, 0x2155b699);
38230+ INSTANCE_WR(ctx, 0x00660/4, 0xfedcba98);
38231+ INSTANCE_WR(ctx, 0x00664/4, 0x00000098);
38232+ INSTANCE_WR(ctx, 0x00674/4, 0xffffffff);
38233+ INSTANCE_WR(ctx, 0x00678/4, 0x00ff7000);
38234+ INSTANCE_WR(ctx, 0x0067c/4, 0x0000ffff);
38235+ INSTANCE_WR(ctx, 0x0068c/4, 0x00ff0000);
38236+ INSTANCE_WR(ctx, 0x006c8/4, 0x00ffff00);
38237+ for (i=0x0070c; i<=0x00748; i+=4)
38238+ INSTANCE_WR(ctx, i/4, 0x00018488);
38239+ for (i=0x0074c; i<=0x00788; i+=4)
38240+ INSTANCE_WR(ctx, i/4, 0x00028202);
38241+ for (i=0x007cc; i<=0x00808; i+=4)
38242+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38243+ for (i=0x0080c; i<=0x00848; i+=4)
38244+ INSTANCE_WR(ctx, i/4, 0x01012000);
38245+ for (i=0x0084c; i<=0x00888; i+=4)
38246+ INSTANCE_WR(ctx, i/4, 0x00080008);
38247+ for (i=0x008cc; i<=0x00908; i+=4)
38248+ INSTANCE_WR(ctx, i/4, 0x00100008);
38249+ for (i=0x0095c; i<=0x00968; i+=4)
38250+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38251+ for (i=0x0096c; i<=0x00978; i+=4)
38252+ INSTANCE_WR(ctx, i/4, 0x00000202);
38253+ for (i=0x0098c; i<=0x00998; i+=4)
38254+ INSTANCE_WR(ctx, i/4, 0x00000008);
38255+ for (i=0x009ac; i<=0x009b8; i+=4)
38256+ INSTANCE_WR(ctx, i/4, 0x00080008);
38257+ INSTANCE_WR(ctx, 0x009cc/4, 0x00000002);
38258+ INSTANCE_WR(ctx, 0x00a00/4, 0x00000421);
38259+ INSTANCE_WR(ctx, 0x00a04/4, 0x030c30c3);
38260+ INSTANCE_WR(ctx, 0x00a08/4, 0x00011001);
38261+ INSTANCE_WR(ctx, 0x00a14/4, 0x3e020200);
38262+ INSTANCE_WR(ctx, 0x00a18/4, 0x00ffffff);
38263+ INSTANCE_WR(ctx, 0x00a1c/4, 0x0c103f00);
38264+ INSTANCE_WR(ctx, 0x00a28/4, 0x00040000);
38265+ INSTANCE_WR(ctx, 0x00a60/4, 0x00008100);
38266+ INSTANCE_WR(ctx, 0x00aec/4, 0x00000001);
38267+ INSTANCE_WR(ctx, 0x00b30/4, 0x00001001);
38268+ INSTANCE_WR(ctx, 0x00b38/4, 0x00000003);
38269+ INSTANCE_WR(ctx, 0x00b3c/4, 0x00888001);
38270+ INSTANCE_WR(ctx, 0x00bc0/4, 0x00000005);
38271+ INSTANCE_WR(ctx, 0x00bcc/4, 0x0000ffff);
38272+ INSTANCE_WR(ctx, 0x00be8/4, 0x00005555);
38273+ INSTANCE_WR(ctx, 0x00bec/4, 0x00005555);
38274+ INSTANCE_WR(ctx, 0x00bf0/4, 0x00005555);
38275+ INSTANCE_WR(ctx, 0x00bf4/4, 0x00000001);
38276+ INSTANCE_WR(ctx, 0x00c2c/4, 0x00000001);
38277+ INSTANCE_WR(ctx, 0x00c30/4, 0x08e00001);
38278+ INSTANCE_WR(ctx, 0x00c34/4, 0x000e3000);
38279+ for (i=0x017f8; i<=0x01870; i+=8)
38280+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38281+ for (i=0x035b8; i<=0x057a8; i+=24)
38282+ INSTANCE_WR(ctx, i/4, 0x00000001);
38283+ for (i=0x057b8; i<=0x05ba8; i+=16)
38284+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38285+ for (i=0x07f38; i<=0x0a128; i+=24)
38286+ INSTANCE_WR(ctx, i/4, 0x00000001);
38287+ for (i=0x0a138; i<=0x0a528; i+=16)
38288+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38289+ for (i=0x0c8b8; i<=0x0eaa8; i+=24)
38290+ INSTANCE_WR(ctx, i/4, 0x00000001);
38291+ for (i=0x0eab8; i<=0x0eea8; i+=16)
38292+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38293+}
38294+
38295+static void
38296+nv49_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38297+{
38298+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38299+ int i;
38300+
38301+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38302+ INSTANCE_WR(ctx, 0x00004/4, 0x0000c040);
38303+ INSTANCE_WR(ctx, 0x00008/4, 0x0000c040);
38304+ INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040);
38305+ INSTANCE_WR(ctx, 0x00010/4, 0x0000c040);
38306+ INSTANCE_WR(ctx, 0x00014/4, 0x0000c040);
38307+ INSTANCE_WR(ctx, 0x00018/4, 0x0000c040);
38308+ INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040);
38309+ INSTANCE_WR(ctx, 0x00020/4, 0x0000c040);
38310+ INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff);
38311+ INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff);
38312+ INSTANCE_WR(ctx, 0x000d0/4, 0x00000001);
38313+ INSTANCE_WR(ctx, 0x001bc/4, 0x20010001);
38314+ INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00);
38315+ INSTANCE_WR(ctx, 0x001c8/4, 0x02008821);
38316+ INSTANCE_WR(ctx, 0x00218/4, 0x00000040);
38317+ INSTANCE_WR(ctx, 0x0021c/4, 0x00000040);
38318+ INSTANCE_WR(ctx, 0x00220/4, 0x00000040);
38319+ INSTANCE_WR(ctx, 0x00228/4, 0x00000040);
38320+ INSTANCE_WR(ctx, 0x00234/4, 0x80000000);
38321+ INSTANCE_WR(ctx, 0x00238/4, 0x80000000);
38322+ INSTANCE_WR(ctx, 0x0023c/4, 0x80000000);
38323+ INSTANCE_WR(ctx, 0x00240/4, 0x80000000);
38324+ INSTANCE_WR(ctx, 0x00244/4, 0x80000000);
38325+ INSTANCE_WR(ctx, 0x00248/4, 0x80000000);
38326+ INSTANCE_WR(ctx, 0x0024c/4, 0x80000000);
38327+ INSTANCE_WR(ctx, 0x00250/4, 0x80000000);
38328+ INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c);
38329+ INSTANCE_WR(ctx, 0x003e0/4, 0x00040000);
38330+ INSTANCE_WR(ctx, 0x003f0/4, 0x55555555);
38331+ INSTANCE_WR(ctx, 0x003f4/4, 0x55555555);
38332+ INSTANCE_WR(ctx, 0x003f8/4, 0x55555555);
38333+ INSTANCE_WR(ctx, 0x003fc/4, 0x55555555);
38334+ INSTANCE_WR(ctx, 0x00428/4, 0x00000008);
38335+ INSTANCE_WR(ctx, 0x0043c/4, 0x00001010);
38336+ INSTANCE_WR(ctx, 0x00460/4, 0x00000111);
38337+ INSTANCE_WR(ctx, 0x00464/4, 0x00000111);
38338+ INSTANCE_WR(ctx, 0x00468/4, 0x00000111);
38339+ INSTANCE_WR(ctx, 0x0046c/4, 0x00000111);
38340+ INSTANCE_WR(ctx, 0x00470/4, 0x00000111);
38341+ INSTANCE_WR(ctx, 0x00474/4, 0x00000111);
38342+ INSTANCE_WR(ctx, 0x00478/4, 0x00000111);
38343+ INSTANCE_WR(ctx, 0x0047c/4, 0x00000111);
38344+ INSTANCE_WR(ctx, 0x00480/4, 0x00000111);
38345+ INSTANCE_WR(ctx, 0x00484/4, 0x00000111);
38346+ INSTANCE_WR(ctx, 0x00488/4, 0x00000111);
38347+ INSTANCE_WR(ctx, 0x0048c/4, 0x00000111);
38348+ INSTANCE_WR(ctx, 0x00490/4, 0x00000111);
38349+ INSTANCE_WR(ctx, 0x00494/4, 0x00000111);
38350+ INSTANCE_WR(ctx, 0x00498/4, 0x00000111);
38351+ INSTANCE_WR(ctx, 0x0049c/4, 0x00000111);
38352+ INSTANCE_WR(ctx, 0x004f4/4, 0x00000111);
38353+ INSTANCE_WR(ctx, 0x004f8/4, 0x00080060);
38354+ INSTANCE_WR(ctx, 0x00514/4, 0x00000080);
38355+ INSTANCE_WR(ctx, 0x00518/4, 0xffff0000);
38356+ INSTANCE_WR(ctx, 0x0051c/4, 0x00000001);
38357+ INSTANCE_WR(ctx, 0x00530/4, 0x46400000);
38358+ INSTANCE_WR(ctx, 0x00540/4, 0xffff0000);
38359+ INSTANCE_WR(ctx, 0x00544/4, 0x88888888);
38360+ INSTANCE_WR(ctx, 0x00548/4, 0x88888888);
38361+ INSTANCE_WR(ctx, 0x0054c/4, 0x88888888);
38362+ INSTANCE_WR(ctx, 0x00550/4, 0x88888888);
38363+ INSTANCE_WR(ctx, 0x00554/4, 0x88888888);
38364+ INSTANCE_WR(ctx, 0x00558/4, 0x88888888);
38365+ INSTANCE_WR(ctx, 0x0055c/4, 0x88888888);
38366+ INSTANCE_WR(ctx, 0x00560/4, 0x88888888);
38367+ INSTANCE_WR(ctx, 0x00564/4, 0x88888888);
38368+ INSTANCE_WR(ctx, 0x00568/4, 0x88888888);
38369+ INSTANCE_WR(ctx, 0x0056c/4, 0x88888888);
38370+ INSTANCE_WR(ctx, 0x00570/4, 0x88888888);
38371+ INSTANCE_WR(ctx, 0x00574/4, 0x88888888);
38372+ INSTANCE_WR(ctx, 0x00578/4, 0x88888888);
38373+ INSTANCE_WR(ctx, 0x0057c/4, 0x88888888);
38374+ INSTANCE_WR(ctx, 0x00580/4, 0x88888888);
38375+ INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000);
38376+ INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000);
38377+ INSTANCE_WR(ctx, 0x005a0/4, 0x00011100);
38378+ INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000);
38379+ INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000);
38380+ INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000);
38381+ INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000);
38382+ INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000);
38383+ INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000);
38384+ INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000);
38385+ INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000);
38386+ INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000);
38387+ INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000);
38388+ INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000);
38389+ INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000);
38390+ INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000);
38391+ INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000);
38392+ INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000);
38393+ INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000);
38394+ INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff);
38395+ INSTANCE_WR(ctx, 0x0062c/4, 0x30201000);
38396+ INSTANCE_WR(ctx, 0x00630/4, 0x70605040);
38397+ INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888);
38398+ INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8);
38399+ INSTANCE_WR(ctx, 0x0064c/4, 0x40100000);
38400+ INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff);
38401+ INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6);
38402+ INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699);
38403+ INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98);
38404+ INSTANCE_WR(ctx, 0x006a8/4, 0x00000098);
38405+ INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff);
38406+ INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000);
38407+ INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff);
38408+ INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000);
38409+ INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00);
38410+ for (i=0x00750; i<=0x0078c; i+=4)
38411+ INSTANCE_WR(ctx, i/4, 0x00018488);
38412+ for (i=0x00790; i<=0x007cc; i+=4)
38413+ INSTANCE_WR(ctx, i/4, 0x00028202);
38414+ for (i=0x00810; i<=0x0084c; i+=4)
38415+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38416+ for (i=0x00850; i<=0x0088c; i+=4)
38417+ INSTANCE_WR(ctx, i/4, 0x01012000);
38418+ for (i=0x00890; i<=0x008cc; i+=4)
38419+ INSTANCE_WR(ctx, i/4, 0x00080008);
38420+ for (i=0x00910; i<=0x0094c; i+=4)
38421+ INSTANCE_WR(ctx, i/4, 0x00100008);
38422+ for (i=0x009a0; i<=0x009ac; i+=4)
38423+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38424+ for (i=0x009b0; i<=0x009bc; i+=4)
38425+ INSTANCE_WR(ctx, i/4, 0x00000202);
38426+ for (i=0x009d0; i<=0x009dc; i+=4)
38427+ INSTANCE_WR(ctx, i/4, 0x00000008);
38428+ for (i=0x009f0; i<=0x009fc; i+=4)
38429+ INSTANCE_WR(ctx, i/4, 0x00080008);
38430+ INSTANCE_WR(ctx, 0x00a10/4, 0x00000002);
38431+ INSTANCE_WR(ctx, 0x00a44/4, 0x00000421);
38432+ INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3);
38433+ INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200);
38434+ INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff);
38435+ INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00);
38436+ INSTANCE_WR(ctx, 0x00a68/4, 0x00040000);
38437+ INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100);
38438+ INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001);
38439+ INSTANCE_WR(ctx, 0x00b70/4, 0x00001001);
38440+ INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003);
38441+ INSTANCE_WR(ctx, 0x00b80/4, 0x00888001);
38442+ INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff);
38443+ INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff);
38444+ INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff);
38445+ INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff);
38446+ INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff);
38447+ INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff);
38448+ INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff);
38449+ INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff);
38450+ INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff);
38451+ INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff);
38452+ INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff);
38453+ INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff);
38454+ INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff);
38455+ INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff);
38456+ INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff);
38457+ INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff);
38458+ INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff);
38459+ INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff);
38460+ INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff);
38461+ INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff);
38462+ INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff);
38463+ INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff);
38464+ INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff);
38465+ INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff);
38466+ INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff);
38467+ INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff);
38468+ INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff);
38469+ INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff);
38470+ INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff);
38471+ INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff);
38472+ INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff);
38473+ INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff);
38474+ INSTANCE_WR(ctx, 0x00c54/4, 0x00000005);
38475+ INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff);
38476+ INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555);
38477+ INSTANCE_WR(ctx, 0x00c80/4, 0x00005555);
38478+ INSTANCE_WR(ctx, 0x00c84/4, 0x00005555);
38479+ INSTANCE_WR(ctx, 0x00c88/4, 0x00005555);
38480+ INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555);
38481+ INSTANCE_WR(ctx, 0x00c90/4, 0x00005555);
38482+ INSTANCE_WR(ctx, 0x00c94/4, 0x00005555);
38483+ INSTANCE_WR(ctx, 0x00c98/4, 0x00005555);
38484+ INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001);
38485+ INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001);
38486+ INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001);
38487+ INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000);
38488+ for(i=0x030a0; i<=0x03118; i+=8)
38489+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38490+ for(i=0x098a0; i<=0x0ba90; i+=24)
38491+ INSTANCE_WR(ctx, i/4, 0x00000001);
38492+ for(i=0x0baa0; i<=0x0be90; i+=16)
38493+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38494+ for(i=0x0e2e0; i<=0x0fff0; i+=24)
38495+ INSTANCE_WR(ctx, i/4, 0x00000001);
38496+ for(i=0x10008; i<=0x104d0; i+=24)
38497+ INSTANCE_WR(ctx, i/4, 0x00000001);
38498+ for(i=0x104e0; i<=0x108d0; i+=16)
38499+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38500+ for(i=0x12d20; i<=0x14f10; i+=24)
38501+ INSTANCE_WR(ctx, i/4, 0x00000001);
38502+ for(i=0x14f20; i<=0x15310; i+=16)
38503+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38504+ for(i=0x17760; i<=0x19950; i+=24)
38505+ INSTANCE_WR(ctx, i/4, 0x00000001);
38506+ for(i=0x19960; i<=0x19d50; i+=16)
38507+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38508+ for(i=0x1c1a0; i<=0x1e390; i+=24)
38509+ INSTANCE_WR(ctx, i/4, 0x00000001);
38510+ for(i=0x1e3a0; i<=0x1e790; i+=16)
38511+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38512+ for(i=0x20be0; i<=0x22dd0; i+=24)
38513+ INSTANCE_WR(ctx, i/4, 0x00000001);
38514+ for(i=0x22de0; i<=0x231d0; i+=16)
38515+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38516+}
38517+
38518+static void
38519+nv4a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38520+{
38521+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38522+ int i;
38523+
38524+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38525+ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
38526+ INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
38527+ INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
38528+ INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
38529+ INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
38530+ INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
38531+ INSTANCE_WR(ctx, 0x00158/4, 0x00000001);
38532+ INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);
38533+ INSTANCE_WR(ctx, 0x00160/4, 0x00000001);
38534+ INSTANCE_WR(ctx, 0x00164/4, 0x00000001);
38535+ INSTANCE_WR(ctx, 0x00168/4, 0x00000001);
38536+ INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);
38537+ INSTANCE_WR(ctx, 0x00170/4, 0x00000001);
38538+ INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
38539+ INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
38540+ INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
38541+ INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
38542+ INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
38543+ INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
38544+ INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
38545+ INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
38546+ INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
38547+ INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
38548+ INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
38549+ INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
38550+ INSTANCE_WR(ctx, 0x0039c/4, 0x00003010);
38551+ INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);
38552+ INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);
38553+ INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);
38554+ INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);
38555+ INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);
38556+ INSTANCE_WR(ctx, 0x00408/4, 0x46400000);
38557+ INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);
38558+ INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);
38559+ INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
38560+ INSTANCE_WR(ctx, 0x00430/4, 0x00011100);
38561+ for (i=0x0044c; i<=0x00488; i+=4)
38562+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
38563+ INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);
38564+ INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);
38565+ INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);
38566+ INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);
38567+ INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);
38568+ INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);
38569+ INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);
38570+ INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);
38571+ INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);
38572+ INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);
38573+ INSTANCE_WR(ctx, 0x00538/4, 0x00000098);
38574+ INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);
38575+ INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);
38576+ INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);
38577+ INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000);
38578+ INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00);
38579+ for (i=0x005d8; i<=0x00614; i+=4)
38580+ INSTANCE_WR(ctx, i/4, 0x00018488);
38581+ for (i=0x00618; i<=0x00654; i+=4)
38582+ INSTANCE_WR(ctx, i/4, 0x00028202);
38583+ for (i=0x00698; i<=0x006d4; i+=4)
38584+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38585+ for (i=0x006d8; i<=0x00714; i+=4)
38586+ INSTANCE_WR(ctx, i/4, 0x01012000);
38587+ for (i=0x00718; i<=0x00754; i+=4)
38588+ INSTANCE_WR(ctx, i/4, 0x00080008);
38589+ for (i=0x00798; i<=0x007d4; i+=4)
38590+ INSTANCE_WR(ctx, i/4, 0x00100008);
38591+ for (i=0x00828; i<=0x00834; i+=4)
38592+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38593+ for (i=0x00838; i<=0x00844; i+=4)
38594+ INSTANCE_WR(ctx, i/4, 0x00000202);
38595+ for (i=0x00858; i<=0x00864; i+=4)
38596+ INSTANCE_WR(ctx, i/4, 0x00000008);
38597+ for (i=0x00878; i<=0x00884; i+=4)
38598+ INSTANCE_WR(ctx, i/4, 0x00080008);
38599+ INSTANCE_WR(ctx, 0x00898/4, 0x00000002);
38600+ INSTANCE_WR(ctx, 0x008cc/4, 0x00000021);
38601+ INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3);
38602+ INSTANCE_WR(ctx, 0x008d4/4, 0x00011001);
38603+ INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);
38604+ INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);
38605+ INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);
38606+ INSTANCE_WR(ctx, 0x008f4/4, 0x00040000);
38607+ INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);
38608+ INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);
38609+ INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);
38610+ INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);
38611+ INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);
38612+ INSTANCE_WR(ctx, 0x00a8c/4, 0x00000005);
38613+ INSTANCE_WR(ctx, 0x00a98/4, 0x0000ffff);
38614+ INSTANCE_WR(ctx, 0x00ab4/4, 0x00005555);
38615+ INSTANCE_WR(ctx, 0x00ab8/4, 0x00005555);
38616+ INSTANCE_WR(ctx, 0x00abc/4, 0x00005555);
38617+ INSTANCE_WR(ctx, 0x00ac0/4, 0x00000001);
38618+ INSTANCE_WR(ctx, 0x00af8/4, 0x00000001);
38619+ for (i=0x016c0; i<=0x01738; i+=8)
38620+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38621+ for (i=0x03840; i<=0x05670; i+=24)
38622+ INSTANCE_WR(ctx, i/4, 0x00000001);
38623+ for (i=0x05680; i<=0x05a70; i+=16)
38624+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38625+ for (i=0x07e00; i<=0x09ff0; i+=24)
38626+ INSTANCE_WR(ctx, i/4, 0x00000001);
38627+ for (i=0x0a000; i<=0x0a3f0; i+=16)
38628+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38629+ for (i=0x0c780; i<=0x0e970; i+=24)
38630+ INSTANCE_WR(ctx, i/4, 0x00000001);
38631+ for (i=0x0e980; i<=0x0ed70; i+=16)
38632+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38633+}
38634+
38635+static void
38636+nv4b_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38637+{
38638+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38639+ int i;
38640+
38641+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38642+ INSTANCE_WR(ctx, 0x00004/4, 0x0000c040);
38643+ INSTANCE_WR(ctx, 0x00008/4, 0x0000c040);
38644+ INSTANCE_WR(ctx, 0x0000c/4, 0x0000c040);
38645+ INSTANCE_WR(ctx, 0x00010/4, 0x0000c040);
38646+ INSTANCE_WR(ctx, 0x00014/4, 0x0000c040);
38647+ INSTANCE_WR(ctx, 0x00018/4, 0x0000c040);
38648+ INSTANCE_WR(ctx, 0x0001c/4, 0x0000c040);
38649+ INSTANCE_WR(ctx, 0x00020/4, 0x0000c040);
38650+ INSTANCE_WR(ctx, 0x000c4/4, 0x0000ffff);
38651+ INSTANCE_WR(ctx, 0x000c8/4, 0x0000ffff);
38652+ INSTANCE_WR(ctx, 0x000d0/4, 0x00000001);
38653+ INSTANCE_WR(ctx, 0x001bc/4, 0x20010001);
38654+ INSTANCE_WR(ctx, 0x001c0/4, 0x0f73ef00);
38655+ INSTANCE_WR(ctx, 0x001c8/4, 0x02008821);
38656+ INSTANCE_WR(ctx, 0x00218/4, 0x00000040);
38657+ INSTANCE_WR(ctx, 0x0021c/4, 0x00000040);
38658+ INSTANCE_WR(ctx, 0x00220/4, 0x00000040);
38659+ INSTANCE_WR(ctx, 0x00228/4, 0x00000040);
38660+ INSTANCE_WR(ctx, 0x00234/4, 0x80000000);
38661+ INSTANCE_WR(ctx, 0x00238/4, 0x80000000);
38662+ INSTANCE_WR(ctx, 0x0023c/4, 0x80000000);
38663+ INSTANCE_WR(ctx, 0x00240/4, 0x80000000);
38664+ INSTANCE_WR(ctx, 0x00244/4, 0x80000000);
38665+ INSTANCE_WR(ctx, 0x00248/4, 0x80000000);
38666+ INSTANCE_WR(ctx, 0x0024c/4, 0x80000000);
38667+ INSTANCE_WR(ctx, 0x00250/4, 0x80000000);
38668+ INSTANCE_WR(ctx, 0x00270/4, 0x0b0b0b0c);
38669+ INSTANCE_WR(ctx, 0x003e0/4, 0x00040000);
38670+ INSTANCE_WR(ctx, 0x003f0/4, 0x55555555);
38671+ INSTANCE_WR(ctx, 0x003f4/4, 0x55555555);
38672+ INSTANCE_WR(ctx, 0x003f8/4, 0x55555555);
38673+ INSTANCE_WR(ctx, 0x003fc/4, 0x55555555);
38674+ INSTANCE_WR(ctx, 0x00428/4, 0x00000008);
38675+ INSTANCE_WR(ctx, 0x0043c/4, 0x00001010);
38676+ INSTANCE_WR(ctx, 0x00460/4, 0x00000111);
38677+ INSTANCE_WR(ctx, 0x00464/4, 0x00000111);
38678+ INSTANCE_WR(ctx, 0x00468/4, 0x00000111);
38679+ INSTANCE_WR(ctx, 0x0046c/4, 0x00000111);
38680+ INSTANCE_WR(ctx, 0x00470/4, 0x00000111);
38681+ INSTANCE_WR(ctx, 0x00474/4, 0x00000111);
38682+ INSTANCE_WR(ctx, 0x00478/4, 0x00000111);
38683+ INSTANCE_WR(ctx, 0x0047c/4, 0x00000111);
38684+ INSTANCE_WR(ctx, 0x00480/4, 0x00000111);
38685+ INSTANCE_WR(ctx, 0x00484/4, 0x00000111);
38686+ INSTANCE_WR(ctx, 0x00488/4, 0x00000111);
38687+ INSTANCE_WR(ctx, 0x0048c/4, 0x00000111);
38688+ INSTANCE_WR(ctx, 0x00490/4, 0x00000111);
38689+ INSTANCE_WR(ctx, 0x00494/4, 0x00000111);
38690+ INSTANCE_WR(ctx, 0x00498/4, 0x00000111);
38691+ INSTANCE_WR(ctx, 0x0049c/4, 0x00000111);
38692+ INSTANCE_WR(ctx, 0x004f4/4, 0x00000111);
38693+ INSTANCE_WR(ctx, 0x004f8/4, 0x00080060);
38694+ INSTANCE_WR(ctx, 0x00514/4, 0x00000080);
38695+ INSTANCE_WR(ctx, 0x00518/4, 0xffff0000);
38696+ INSTANCE_WR(ctx, 0x0051c/4, 0x00000001);
38697+ INSTANCE_WR(ctx, 0x00530/4, 0x46400000);
38698+ INSTANCE_WR(ctx, 0x00540/4, 0xffff0000);
38699+ INSTANCE_WR(ctx, 0x00544/4, 0x88888888);
38700+ INSTANCE_WR(ctx, 0x00548/4, 0x88888888);
38701+ INSTANCE_WR(ctx, 0x0054c/4, 0x88888888);
38702+ INSTANCE_WR(ctx, 0x00550/4, 0x88888888);
38703+ INSTANCE_WR(ctx, 0x00554/4, 0x88888888);
38704+ INSTANCE_WR(ctx, 0x00558/4, 0x88888888);
38705+ INSTANCE_WR(ctx, 0x0055c/4, 0x88888888);
38706+ INSTANCE_WR(ctx, 0x00560/4, 0x88888888);
38707+ INSTANCE_WR(ctx, 0x00564/4, 0x88888888);
38708+ INSTANCE_WR(ctx, 0x00568/4, 0x88888888);
38709+ INSTANCE_WR(ctx, 0x0056c/4, 0x88888888);
38710+ INSTANCE_WR(ctx, 0x00570/4, 0x88888888);
38711+ INSTANCE_WR(ctx, 0x00574/4, 0x88888888);
38712+ INSTANCE_WR(ctx, 0x00578/4, 0x88888888);
38713+ INSTANCE_WR(ctx, 0x0057c/4, 0x88888888);
38714+ INSTANCE_WR(ctx, 0x00580/4, 0x88888888);
38715+ INSTANCE_WR(ctx, 0x00594/4, 0x0fff0000);
38716+ INSTANCE_WR(ctx, 0x00598/4, 0x0fff0000);
38717+ INSTANCE_WR(ctx, 0x005a0/4, 0x00011100);
38718+ INSTANCE_WR(ctx, 0x005bc/4, 0x07ff0000);
38719+ INSTANCE_WR(ctx, 0x005c0/4, 0x07ff0000);
38720+ INSTANCE_WR(ctx, 0x005c4/4, 0x07ff0000);
38721+ INSTANCE_WR(ctx, 0x005c8/4, 0x07ff0000);
38722+ INSTANCE_WR(ctx, 0x005cc/4, 0x07ff0000);
38723+ INSTANCE_WR(ctx, 0x005d0/4, 0x07ff0000);
38724+ INSTANCE_WR(ctx, 0x005d4/4, 0x07ff0000);
38725+ INSTANCE_WR(ctx, 0x005d8/4, 0x07ff0000);
38726+ INSTANCE_WR(ctx, 0x005dc/4, 0x07ff0000);
38727+ INSTANCE_WR(ctx, 0x005e0/4, 0x07ff0000);
38728+ INSTANCE_WR(ctx, 0x005e4/4, 0x07ff0000);
38729+ INSTANCE_WR(ctx, 0x005e8/4, 0x07ff0000);
38730+ INSTANCE_WR(ctx, 0x005ec/4, 0x07ff0000);
38731+ INSTANCE_WR(ctx, 0x005f0/4, 0x07ff0000);
38732+ INSTANCE_WR(ctx, 0x005f4/4, 0x07ff0000);
38733+ INSTANCE_WR(ctx, 0x005f8/4, 0x07ff0000);
38734+ INSTANCE_WR(ctx, 0x00604/4, 0x4b7fffff);
38735+ INSTANCE_WR(ctx, 0x0062c/4, 0x30201000);
38736+ INSTANCE_WR(ctx, 0x00630/4, 0x70605040);
38737+ INSTANCE_WR(ctx, 0x00634/4, 0xb8a89888);
38738+ INSTANCE_WR(ctx, 0x00638/4, 0xf8e8d8c8);
38739+ INSTANCE_WR(ctx, 0x0064c/4, 0x40100000);
38740+ INSTANCE_WR(ctx, 0x00668/4, 0x0000ffff);
38741+ INSTANCE_WR(ctx, 0x0069c/4, 0x435185d6);
38742+ INSTANCE_WR(ctx, 0x006a0/4, 0x2155b699);
38743+ INSTANCE_WR(ctx, 0x006a4/4, 0xfedcba98);
38744+ INSTANCE_WR(ctx, 0x006a8/4, 0x00000098);
38745+ INSTANCE_WR(ctx, 0x006b8/4, 0xffffffff);
38746+ INSTANCE_WR(ctx, 0x006bc/4, 0x00ff7000);
38747+ INSTANCE_WR(ctx, 0x006c0/4, 0x0000ffff);
38748+ INSTANCE_WR(ctx, 0x006d0/4, 0x00ff0000);
38749+ INSTANCE_WR(ctx, 0x0070c/4, 0x00ffff00);
38750+ for (i=0x00750; i<=0x0078c; i+=4)
38751+ INSTANCE_WR(ctx, i/4, 0x00018488);
38752+ for (i=0x00790; i<=0x007cc; i+=4)
38753+ INSTANCE_WR(ctx, i/4, 0x00028202);
38754+ for (i=0x00810; i<=0x0084c; i+=4)
38755+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38756+ for (i=0x00850; i<=0x0088c; i+=4)
38757+ INSTANCE_WR(ctx, i/4, 0x01012000);
38758+ for (i=0x00890; i<=0x008cc; i+=4)
38759+ INSTANCE_WR(ctx, i/4, 0x00080008);
38760+ for (i=0x00910; i<=0x0094c; i+=4)
38761+ INSTANCE_WR(ctx, i/4, 0x00100008);
38762+ for (i=0x009a0; i<=0x009ac; i+=4)
38763+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38764+ for (i=0x009b0; i<=0x009bc; i+=4)
38765+ INSTANCE_WR(ctx, i/4, 0x00000202);
38766+ for (i=0x009d0; i<=0x009dc; i+=4)
38767+ INSTANCE_WR(ctx, i/4, 0x00000008);
38768+ for (i=0x009f0; i<=0x009fc; i+=4)
38769+ INSTANCE_WR(ctx, i/4, 0x00080008);
38770+ INSTANCE_WR(ctx, 0x00a10/4, 0x00000002);
38771+ INSTANCE_WR(ctx, 0x00a44/4, 0x00000421);
38772+ INSTANCE_WR(ctx, 0x00a48/4, 0x030c30c3);
38773+ INSTANCE_WR(ctx, 0x00a54/4, 0x3e020200);
38774+ INSTANCE_WR(ctx, 0x00a58/4, 0x00ffffff);
38775+ INSTANCE_WR(ctx, 0x00a5c/4, 0x20103f00);
38776+ INSTANCE_WR(ctx, 0x00a68/4, 0x00040000);
38777+ INSTANCE_WR(ctx, 0x00aa0/4, 0x00008100);
38778+ INSTANCE_WR(ctx, 0x00b2c/4, 0x00000001);
38779+ INSTANCE_WR(ctx, 0x00b70/4, 0x00001001);
38780+ INSTANCE_WR(ctx, 0x00b7c/4, 0x00000003);
38781+ INSTANCE_WR(ctx, 0x00b80/4, 0x00888001);
38782+ INSTANCE_WR(ctx, 0x00bb0/4, 0xffffffff);
38783+ INSTANCE_WR(ctx, 0x00bb4/4, 0xffffffff);
38784+ INSTANCE_WR(ctx, 0x00bb8/4, 0xffffffff);
38785+ INSTANCE_WR(ctx, 0x00bbc/4, 0xffffffff);
38786+ INSTANCE_WR(ctx, 0x00bc0/4, 0xffffffff);
38787+ INSTANCE_WR(ctx, 0x00bc4/4, 0xffffffff);
38788+ INSTANCE_WR(ctx, 0x00bc8/4, 0xffffffff);
38789+ INSTANCE_WR(ctx, 0x00bcc/4, 0xffffffff);
38790+ INSTANCE_WR(ctx, 0x00bd0/4, 0xffffffff);
38791+ INSTANCE_WR(ctx, 0x00bd4/4, 0xffffffff);
38792+ INSTANCE_WR(ctx, 0x00bd8/4, 0xffffffff);
38793+ INSTANCE_WR(ctx, 0x00bdc/4, 0xffffffff);
38794+ INSTANCE_WR(ctx, 0x00be0/4, 0xffffffff);
38795+ INSTANCE_WR(ctx, 0x00be4/4, 0xffffffff);
38796+ INSTANCE_WR(ctx, 0x00be8/4, 0xffffffff);
38797+ INSTANCE_WR(ctx, 0x00bec/4, 0xffffffff);
38798+ INSTANCE_WR(ctx, 0x00bf0/4, 0xffffffff);
38799+ INSTANCE_WR(ctx, 0x00bf4/4, 0xffffffff);
38800+ INSTANCE_WR(ctx, 0x00bf8/4, 0xffffffff);
38801+ INSTANCE_WR(ctx, 0x00bfc/4, 0xffffffff);
38802+ INSTANCE_WR(ctx, 0x00c00/4, 0xffffffff);
38803+ INSTANCE_WR(ctx, 0x00c04/4, 0xffffffff);
38804+ INSTANCE_WR(ctx, 0x00c08/4, 0xffffffff);
38805+ INSTANCE_WR(ctx, 0x00c0c/4, 0xffffffff);
38806+ INSTANCE_WR(ctx, 0x00c10/4, 0xffffffff);
38807+ INSTANCE_WR(ctx, 0x00c14/4, 0xffffffff);
38808+ INSTANCE_WR(ctx, 0x00c18/4, 0xffffffff);
38809+ INSTANCE_WR(ctx, 0x00c1c/4, 0xffffffff);
38810+ INSTANCE_WR(ctx, 0x00c20/4, 0xffffffff);
38811+ INSTANCE_WR(ctx, 0x00c24/4, 0xffffffff);
38812+ INSTANCE_WR(ctx, 0x00c28/4, 0xffffffff);
38813+ INSTANCE_WR(ctx, 0x00c2c/4, 0xffffffff);
38814+ INSTANCE_WR(ctx, 0x00c54/4, 0x00000005);
38815+ INSTANCE_WR(ctx, 0x00c60/4, 0x0000ffff);
38816+ INSTANCE_WR(ctx, 0x00c7c/4, 0x00005555);
38817+ INSTANCE_WR(ctx, 0x00c80/4, 0x00005555);
38818+ INSTANCE_WR(ctx, 0x00c84/4, 0x00005555);
38819+ INSTANCE_WR(ctx, 0x00c88/4, 0x00005555);
38820+ INSTANCE_WR(ctx, 0x00c8c/4, 0x00005555);
38821+ INSTANCE_WR(ctx, 0x00c90/4, 0x00005555);
38822+ INSTANCE_WR(ctx, 0x00c94/4, 0x00005555);
38823+ INSTANCE_WR(ctx, 0x00c98/4, 0x00005555);
38824+ INSTANCE_WR(ctx, 0x00c9c/4, 0x00000001);
38825+ INSTANCE_WR(ctx, 0x00cd4/4, 0x00000001);
38826+ INSTANCE_WR(ctx, 0x00cd8/4, 0x08e00001);
38827+ INSTANCE_WR(ctx, 0x00cdc/4, 0x000e3000);
38828+ for(i=0x030a0; i<=0x03118; i+=8)
38829+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38830+ for(i=0x098a0; i<=0x0ba90; i+=24)
38831+ INSTANCE_WR(ctx, i/4, 0x00000001);
38832+ for(i=0x0baa0; i<=0x0be90; i+=16)
38833+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38834+ for(i=0x0e2e0; i<=0x0fff0; i+=24)
38835+ INSTANCE_WR(ctx, i/4, 0x00000001);
38836+ for(i=0x10008; i<=0x104d0; i+=24)
38837+ INSTANCE_WR(ctx, i/4, 0x00000001);
38838+ for(i=0x104e0; i<=0x108d0; i+=16)
38839+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38840+ for(i=0x12d20; i<=0x14f10; i+=24)
38841+ INSTANCE_WR(ctx, i/4, 0x00000001);
38842+ for(i=0x14f20; i<=0x15310; i+=16)
38843+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38844+ for(i=0x17760; i<=0x19950; i+=24)
38845+ INSTANCE_WR(ctx, i/4, 0x00000001);
38846+ for(i=0x19960; i<=0x19d50; i+=16)
38847+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38848+}
38849+
38850+static void
38851+nv4c_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38852+{
38853+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38854+ int i;
38855+
38856+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38857+ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
38858+ INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
38859+ INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
38860+ INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
38861+ INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
38862+ INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
38863+ INSTANCE_WR(ctx, 0x00158/4, 0x00000001);
38864+ INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);
38865+ INSTANCE_WR(ctx, 0x00160/4, 0x00000001);
38866+ INSTANCE_WR(ctx, 0x00164/4, 0x00000001);
38867+ INSTANCE_WR(ctx, 0x00168/4, 0x00000001);
38868+ INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);
38869+ INSTANCE_WR(ctx, 0x00170/4, 0x00000001);
38870+ INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
38871+ INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
38872+ INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
38873+ INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
38874+ INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
38875+ INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
38876+ INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
38877+ INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
38878+ INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
38879+ INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
38880+ INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
38881+ INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
38882+ INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);
38883+ INSTANCE_WR(ctx, 0x003d0/4, 0x00000111);
38884+ INSTANCE_WR(ctx, 0x003d4/4, 0x00080060);
38885+ INSTANCE_WR(ctx, 0x003f0/4, 0x00000080);
38886+ INSTANCE_WR(ctx, 0x003f4/4, 0xffff0000);
38887+ INSTANCE_WR(ctx, 0x003f8/4, 0x00000001);
38888+ INSTANCE_WR(ctx, 0x0040c/4, 0x46400000);
38889+ INSTANCE_WR(ctx, 0x0041c/4, 0xffff0000);
38890+ INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
38891+ INSTANCE_WR(ctx, 0x0042c/4, 0x0fff0000);
38892+ INSTANCE_WR(ctx, 0x00434/4, 0x00011100);
38893+ for (i=0x00450; i<0x0048c; i+=4)
38894+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
38895+ INSTANCE_WR(ctx, 0x00498/4, 0x4b7fffff);
38896+ INSTANCE_WR(ctx, 0x004c0/4, 0x30201000);
38897+ INSTANCE_WR(ctx, 0x004c4/4, 0x70605040);
38898+ INSTANCE_WR(ctx, 0x004c8/4, 0xb8a89888);
38899+ INSTANCE_WR(ctx, 0x004cc/4, 0xf8e8d8c8);
38900+ INSTANCE_WR(ctx, 0x004e0/4, 0x40100000);
38901+ INSTANCE_WR(ctx, 0x004fc/4, 0x0000ffff);
38902+ INSTANCE_WR(ctx, 0x00530/4, 0x435185d6);
38903+ INSTANCE_WR(ctx, 0x00534/4, 0x2155b699);
38904+ INSTANCE_WR(ctx, 0x00538/4, 0xfedcba98);
38905+ INSTANCE_WR(ctx, 0x0053c/4, 0x00000098);
38906+ INSTANCE_WR(ctx, 0x0054c/4, 0xffffffff);
38907+ INSTANCE_WR(ctx, 0x00550/4, 0x00ff7000);
38908+ INSTANCE_WR(ctx, 0x00554/4, 0x0000ffff);
38909+ INSTANCE_WR(ctx, 0x00564/4, 0x00ff0000);
38910+ INSTANCE_WR(ctx, 0x0059c/4, 0x00ffff00);
38911+ for (i=0x005e0; i<=0x0061c; i+=4)
38912+ INSTANCE_WR(ctx, i/4, 0x00018488);
38913+ for (i=0x00620; i<=0x0065c; i+=4)
38914+ INSTANCE_WR(ctx, i/4, 0x00028202);
38915+ for (i=0x006a0; i<=0x006dc; i+=4)
38916+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
38917+ for (i=0x006e0; i<=0x0071c; i+=4)
38918+ INSTANCE_WR(ctx, i/4, 0x01012000);
38919+ for (i=0x00720; i<=0x0075c; i+=4)
38920+ INSTANCE_WR(ctx, i/4, 0x00080008);
38921+ for (i=0x007a0; i<=0x007dc; i+=4)
38922+ INSTANCE_WR(ctx, i/4, 0x00100008);
38923+ for (i=0x00830; i<=0x0083c; i+=4)
38924+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
38925+ for (i=0x00840; i<=0x0084c; i+=4)
38926+ INSTANCE_WR(ctx, i/4, 0x00000202);
38927+ for (i=0x00860; i<=0x0086c; i+=4)
38928+ INSTANCE_WR(ctx, i/4, 0x00000008);
38929+ for (i=0x00880; i<=0x0088c; i+=4)
38930+ INSTANCE_WR(ctx, i/4, 0x00080008);
38931+ INSTANCE_WR(ctx, 0x008a0/4, 0x00000002);
38932+ INSTANCE_WR(ctx, 0x008d4/4, 0x00000020);
38933+ INSTANCE_WR(ctx, 0x008d8/4, 0x030c30c3);
38934+ INSTANCE_WR(ctx, 0x008dc/4, 0x00011001);
38935+ INSTANCE_WR(ctx, 0x008e8/4, 0x3e020200);
38936+ INSTANCE_WR(ctx, 0x008ec/4, 0x00ffffff);
38937+ INSTANCE_WR(ctx, 0x008f0/4, 0x0c103f00);
38938+ INSTANCE_WR(ctx, 0x008fc/4, 0x00040000);
38939+ INSTANCE_WR(ctx, 0x00934/4, 0x00008100);
38940+ INSTANCE_WR(ctx, 0x009c0/4, 0x00000001);
38941+ INSTANCE_WR(ctx, 0x00a04/4, 0x00001001);
38942+ INSTANCE_WR(ctx, 0x00a0c/4, 0x00000003);
38943+ INSTANCE_WR(ctx, 0x00a10/4, 0x00888001);
38944+ INSTANCE_WR(ctx, 0x00a74/4, 0x00000005);
38945+ INSTANCE_WR(ctx, 0x00a80/4, 0x0000ffff);
38946+ INSTANCE_WR(ctx, 0x00a9c/4, 0x00005555);
38947+ INSTANCE_WR(ctx, 0x00aa0/4, 0x00000001);
38948+ INSTANCE_WR(ctx, 0x00ad8/4, 0x00000001);
38949+ for (i=0x016a0; i<0x01718; i+=8)
38950+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38951+ for (i=0x03460; i<0x05650; i+=24)
38952+ INSTANCE_WR(ctx, i/4, 0x00000001);
38953+ for (i=0x05660; i<0x05a50; i+=16)
38954+ INSTANCE_WR(ctx, i/4, 0x3f800000);
38955+}
38956+
38957+static void
38958+nv4e_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
38959+{
38960+ struct drm_nouveau_private *dev_priv = dev->dev_private;
38961+ int i;
38962+
38963+ INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
38964+ INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
38965+ INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
38966+ INSTANCE_WR(ctx, 0x00030/4, 0x00000001);
38967+ INSTANCE_WR(ctx, 0x0011c/4, 0x20010001);
38968+ INSTANCE_WR(ctx, 0x00120/4, 0x0f73ef00);
38969+ INSTANCE_WR(ctx, 0x00128/4, 0x02008821);
38970+ INSTANCE_WR(ctx, 0x00158/4, 0x00000001);
38971+ INSTANCE_WR(ctx, 0x0015c/4, 0x00000001);
38972+ INSTANCE_WR(ctx, 0x00160/4, 0x00000001);
38973+ INSTANCE_WR(ctx, 0x00164/4, 0x00000001);
38974+ INSTANCE_WR(ctx, 0x00168/4, 0x00000001);
38975+ INSTANCE_WR(ctx, 0x0016c/4, 0x00000001);
38976+ INSTANCE_WR(ctx, 0x00170/4, 0x00000001);
38977+ INSTANCE_WR(ctx, 0x00174/4, 0x00000001);
38978+ INSTANCE_WR(ctx, 0x00178/4, 0x00000040);
38979+ INSTANCE_WR(ctx, 0x0017c/4, 0x00000040);
38980+ INSTANCE_WR(ctx, 0x00180/4, 0x00000040);
38981+ INSTANCE_WR(ctx, 0x00188/4, 0x00000040);
38982+ INSTANCE_WR(ctx, 0x001d0/4, 0x0b0b0b0c);
38983+ INSTANCE_WR(ctx, 0x00340/4, 0x00040000);
38984+ INSTANCE_WR(ctx, 0x00350/4, 0x55555555);
38985+ INSTANCE_WR(ctx, 0x00354/4, 0x55555555);
38986+ INSTANCE_WR(ctx, 0x00358/4, 0x55555555);
38987+ INSTANCE_WR(ctx, 0x0035c/4, 0x55555555);
38988+ INSTANCE_WR(ctx, 0x00388/4, 0x00000008);
38989+ INSTANCE_WR(ctx, 0x0039c/4, 0x00001010);
38990+ INSTANCE_WR(ctx, 0x003cc/4, 0x00000111);
38991+ INSTANCE_WR(ctx, 0x003d0/4, 0x00080060);
38992+ INSTANCE_WR(ctx, 0x003ec/4, 0x00000080);
38993+ INSTANCE_WR(ctx, 0x003f0/4, 0xffff0000);
38994+ INSTANCE_WR(ctx, 0x003f4/4, 0x00000001);
38995+ INSTANCE_WR(ctx, 0x00408/4, 0x46400000);
38996+ INSTANCE_WR(ctx, 0x00418/4, 0xffff0000);
38997+ INSTANCE_WR(ctx, 0x00424/4, 0x0fff0000);
38998+ INSTANCE_WR(ctx, 0x00428/4, 0x0fff0000);
38999+ INSTANCE_WR(ctx, 0x00430/4, 0x00011100);
39000+ for (i=0x0044c; i<=0x00488; i+=4)
39001+ INSTANCE_WR(ctx, i/4, 0x07ff0000);
39002+ INSTANCE_WR(ctx, 0x00494/4, 0x4b7fffff);
39003+ INSTANCE_WR(ctx, 0x004bc/4, 0x30201000);
39004+ INSTANCE_WR(ctx, 0x004c0/4, 0x70605040);
39005+ INSTANCE_WR(ctx, 0x004c4/4, 0xb8a89888);
39006+ INSTANCE_WR(ctx, 0x004c8/4, 0xf8e8d8c8);
39007+ INSTANCE_WR(ctx, 0x004dc/4, 0x40100000);
39008+ INSTANCE_WR(ctx, 0x004f8/4, 0x0000ffff);
39009+ INSTANCE_WR(ctx, 0x0052c/4, 0x435185d6);
39010+ INSTANCE_WR(ctx, 0x00530/4, 0x2155b699);
39011+ INSTANCE_WR(ctx, 0x00534/4, 0xfedcba98);
39012+ INSTANCE_WR(ctx, 0x00538/4, 0x00000098);
39013+ INSTANCE_WR(ctx, 0x00548/4, 0xffffffff);
39014+ INSTANCE_WR(ctx, 0x0054c/4, 0x00ff7000);
39015+ INSTANCE_WR(ctx, 0x00550/4, 0x0000ffff);
39016+ INSTANCE_WR(ctx, 0x0055c/4, 0x00ff0000);
39017+ INSTANCE_WR(ctx, 0x00594/4, 0x00ffff00);
39018+ for (i=0x005d8; i<=0x00614; i+=4)
39019+ INSTANCE_WR(ctx, i/4, 0x00018488);
39020+ for (i=0x00618; i<=0x00654; i+=4)
39021+ INSTANCE_WR(ctx, i/4, 0x00028202);
39022+ for (i=0x00698; i<=0x006d4; i+=4)
39023+ INSTANCE_WR(ctx, i/4, 0x0000aae4);
39024+ for (i=0x006d8; i<=0x00714; i+=4)
39025+ INSTANCE_WR(ctx, i/4, 0x01012000);
39026+ for (i=0x00718; i<=0x00754; i+=4)
39027+ INSTANCE_WR(ctx, i/4, 0x00080008);
39028+ for (i=0x00798; i<=0x007d4; i+=4)
39029+ INSTANCE_WR(ctx, i/4, 0x00100008);
39030+ for (i=0x00828; i<=0x00834; i+=4)
39031+ INSTANCE_WR(ctx, i/4, 0x0001bc80);
39032+ for (i=0x00838; i<=0x00844; i+=4)
39033+ INSTANCE_WR(ctx, i/4, 0x00000202);
39034+ for (i=0x00858; i<=0x00864; i+=4)
39035+ INSTANCE_WR(ctx, i/4, 0x00000008);
39036+ for (i=0x00878; i<=0x00884; i+=4)
39037+ INSTANCE_WR(ctx, i/4, 0x00080008);
39038+ INSTANCE_WR(ctx, 0x00898/4, 0x00000002);
39039+ INSTANCE_WR(ctx, 0x008cc/4, 0x00000020);
39040+ INSTANCE_WR(ctx, 0x008d0/4, 0x030c30c3);
39041+ INSTANCE_WR(ctx, 0x008d4/4, 0x00011001);
39042+ INSTANCE_WR(ctx, 0x008e0/4, 0x3e020200);
39043+ INSTANCE_WR(ctx, 0x008e4/4, 0x00ffffff);
39044+ INSTANCE_WR(ctx, 0x008e8/4, 0x0c103f00);
39045+ INSTANCE_WR(ctx, 0x008f4/4, 0x00040000);
39046+ INSTANCE_WR(ctx, 0x0092c/4, 0x00008100);
39047+ INSTANCE_WR(ctx, 0x009b8/4, 0x00000001);
39048+ INSTANCE_WR(ctx, 0x009fc/4, 0x00001001);
39049+ INSTANCE_WR(ctx, 0x00a04/4, 0x00000003);
39050+ INSTANCE_WR(ctx, 0x00a08/4, 0x00888001);
39051+ INSTANCE_WR(ctx, 0x00a6c/4, 0x00000005);
39052+ INSTANCE_WR(ctx, 0x00a78/4, 0x0000ffff);
39053+ INSTANCE_WR(ctx, 0x00a94/4, 0x00005555);
39054+ INSTANCE_WR(ctx, 0x00a98/4, 0x00000001);
39055+ INSTANCE_WR(ctx, 0x00aa4/4, 0x00000001);
39056+ for (i=0x01668; i<=0x016e0; i+=8)
39057+ INSTANCE_WR(ctx, i/4, 0x3f800000);
39058+ for (i=0x03428; i<=0x05618; i+=24)
39059+ INSTANCE_WR(ctx, i/4, 0x00000001);
39060+ for (i=0x05628; i<=0x05a18; i+=16)
39061+ INSTANCE_WR(ctx, i/4, 0x3f800000);
39062+}
39063+
39064+int
39065+nv40_graph_create_context(struct nouveau_channel *chan)
39066+{
39067+ struct drm_device *dev = chan->dev;
39068+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39069+ void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
39070+ unsigned int ctx_size;
39071+ int ret;
39072+
39073+ switch (dev_priv->chipset) {
39074+ case 0x40:
39075+ ctx_size = NV40_GRCTX_SIZE;
39076+ ctx_init = nv40_graph_context_init;
39077+ break;
39078+ case 0x41:
39079+ case 0x42:
39080+ ctx_size = NV41_GRCTX_SIZE;
39081+ ctx_init = nv41_graph_context_init;
39082+ break;
39083+ case 0x43:
39084+ ctx_size = NV43_GRCTX_SIZE;
39085+ ctx_init = nv43_graph_context_init;
39086+ break;
39087+ case 0x46:
39088+ ctx_size = NV46_GRCTX_SIZE;
39089+ ctx_init = nv46_graph_context_init;
39090+ break;
39091+ case 0x49:
39092+ ctx_size = NV49_GRCTX_SIZE;
39093+ ctx_init = nv49_graph_context_init;
39094+ break;
39095+ case 0x44:
39096+ case 0x4a:
39097+ ctx_size = NV4A_GRCTX_SIZE;
39098+ ctx_init = nv4a_graph_context_init;
39099+ break;
39100+ case 0x4b:
39101+ ctx_size = NV4B_GRCTX_SIZE;
39102+ ctx_init = nv4b_graph_context_init;
39103+ break;
39104+ case 0x4c:
39105+ ctx_size = NV4C_GRCTX_SIZE;
39106+ ctx_init = nv4c_graph_context_init;
39107+ break;
39108+ case 0x4e:
39109+ ctx_size = NV4E_GRCTX_SIZE;
39110+ ctx_init = nv4e_graph_context_init;
39111+ break;
39112+ default:
39113+ ctx_size = NV40_GRCTX_SIZE;
39114+ ctx_init = nv40_graph_context_init;
39115+ break;
39116+ }
39117+
39118+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
39119+ NVOBJ_FLAG_ZERO_ALLOC,
39120+ &chan->ramin_grctx)))
39121+ return ret;
39122+
39123+ /* Initialise default context values */
39124+ ctx_init(dev, chan->ramin_grctx->gpuobj);
39125+
39126+ return 0;
39127+}
39128+
39129+void
39130+nv40_graph_destroy_context(struct nouveau_channel *chan)
39131+{
39132+ nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
39133+}
39134+
39135+static int
39136+nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
39137+{
39138+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39139+ uint32_t old_cp, tv = 1000, tmp;
39140+ int i;
39141+
39142+ old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
39143+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
39144+
39145+ tmp = NV_READ(NV40_PGRAPH_CTXCTL_0310);
39146+ tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
39147+ NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
39148+ NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp);
39149+
39150+ tmp = NV_READ(NV40_PGRAPH_CTXCTL_0304);
39151+ tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
39152+ NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp);
39153+
39154+ for (i = 0; i < tv; i++) {
39155+ if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
39156+ break;
39157+ }
39158+
39159+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
39160+
39161+ if (i == tv) {
39162+ uint32_t ucstat = NV_READ(NV40_PGRAPH_CTXCTL_UCODE_STAT);
39163+ DRM_ERROR("Failed: Instance=0x%08x Save=%d\n", inst, save);
39164+ DRM_ERROR("IP: 0x%02x, Opcode: 0x%08x\n",
39165+ ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
39166+ ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
39167+ DRM_ERROR("0x40030C = 0x%08x\n",
39168+ NV_READ(NV40_PGRAPH_CTXCTL_030C));
39169+ return -EBUSY;
39170+ }
39171+
39172+ return 0;
39173+}
39174+
39175+/* Save current context (from PGRAPH) into the channel's context
39176+ *XXX: fails sometimes, not sure why..
39177+ */
39178+int
39179+nv40_graph_save_context(struct nouveau_channel *chan)
39180+{
39181+ struct drm_device *dev = chan->dev;
39182+ uint32_t inst;
39183+
39184+ if (!chan->ramin_grctx)
39185+ return -EINVAL;
39186+ inst = chan->ramin_grctx->instance >> 4;
39187+
39188+ return nv40_graph_transfer_context(dev, inst, 1);
39189+}
39190+
39191+/* Restore the context for a specific channel into PGRAPH
39192+ * XXX: fails sometimes.. not sure why
39193+ */
39194+int
39195+nv40_graph_load_context(struct nouveau_channel *chan)
39196+{
39197+ struct drm_device *dev = chan->dev;
39198+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39199+ uint32_t inst;
39200+ int ret;
39201+
39202+ if (!chan->ramin_grctx)
39203+ return -EINVAL;
39204+ inst = chan->ramin_grctx->instance >> 4;
39205+
39206+ ret = nv40_graph_transfer_context(dev, inst, 0);
39207+ if (ret)
39208+ return ret;
39209+
39210+ /* 0x40032C, no idea of it's exact function. Could simply be a
39211+ * record of the currently active PGRAPH context. It's currently
39212+ * unknown as to what bit 24 does. The nv ddx has it set, so we will
39213+ * set it here too.
39214+ */
39215+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
39216+ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR,
39217+ (inst & NV40_PGRAPH_CTXCTL_CUR_INST_MASK) |
39218+ NV40_PGRAPH_CTXCTL_CUR_LOADED);
39219+ /* 0x32E0 records the instance address of the active FIFO's PGRAPH
39220+ * context. If at any time this doesn't match 0x40032C, you will
39221+ * recieve PGRAPH_INTR_CONTEXT_SWITCH
39222+ */
39223+ NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
39224+ return 0;
39225+}
39226+
39227+/* Some voodoo that makes context switching work without the binary driver
39228+ * initialising the card first.
39229+ *
39230+ * It is possible to effect how the context is saved from PGRAPH into a block
39231+ * of instance memory by altering the values in these tables. This may mean
39232+ * that the context layout of each chipset is slightly different (at least
39233+ * NV40 and C51 are different). It would also be possible for chipsets to
39234+ * have an identical context layout, but pull the data from different PGRAPH
39235+ * registers.
39236+ *
39237+ * TODO: decode the meaning of the magic values, may provide clues about the
39238+ * differences between the various NV40 chipsets.
39239+ * TODO: one we have a better idea of how each chipset differs, perhaps think
39240+ * about unifying these instead of providing a separate table for each
39241+ * chip.
39242+ *
39243+ * mmio-trace dumps from other nv4x/g7x/c5x cards very welcome :)
39244+ */
39245+static uint32_t nv40_ctx_voodoo[] = {
39246+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39247+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409406,
39248+ 0x0040a268, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39249+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
39250+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39251+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39252+ 0x001041c9, 0x0010c1dc, 0x00110205, 0x0011420a, 0x00114210, 0x00110216,
39253+ 0x0012421b, 0x00120270, 0x001242c0, 0x00200040, 0x00100280, 0x00128100,
39254+ 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029,
39255+ 0x00110400, 0x00104d10, 0x00500060, 0x00403b87, 0x0060000d, 0x004076e6,
39256+ 0x002000f0, 0x0060000a, 0x00200045, 0x00100620, 0x00108668, 0x0011466b,
39257+ 0x00120682, 0x0011068b, 0x00168691, 0x0010c6ae, 0x001206b4, 0x0020002a,
39258+ 0x001006c4, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1,
39259+ 0x00500060, 0x00405600, 0x00405684, 0x00600003, 0x00500067, 0x00600008,
39260+ 0x00500060, 0x00700082, 0x0020026c, 0x0060000a, 0x00104800, 0x00104901,
39261+ 0x00120920, 0x00200035, 0x00100940, 0x00148a00, 0x00104a14, 0x00200038,
39262+ 0x00100b00, 0x00138d00, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06,
39263+ 0x0020031a, 0x0060000a, 0x00300000, 0x00200680, 0x00406c00, 0x00200684,
39264+ 0x00800001, 0x00200b62, 0x0060000a, 0x0020a0b0, 0x0040728a, 0x00201b68,
39265+ 0x00800041, 0x00407684, 0x00203e60, 0x00800002, 0x00408700, 0x00600006,
39266+ 0x00700003, 0x004080e6, 0x00700080, 0x0020031a, 0x0060000a, 0x00200004,
39267+ 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a284,
39268+ 0x00700002, 0x00600004, 0x0040a268, 0x00700000, 0x00200000, 0x0060000a,
39269+ 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,
39270+ 0x00600007, 0x00409388, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,
39271+ 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,
39272+ 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,
39273+ 0x0040a406, 0x0040a505, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,
39274+ ~0
39275+};
39276+
39277+static uint32_t nv41_ctx_voodoo[] = {
39278+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39279+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,
39280+ 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
39281+ 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968,
39282+ 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39283+ 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39284+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39285+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39286+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39287+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39288+ 0x001046ec, 0x00500060, 0x00404087, 0x0060000d, 0x004079e6, 0x002000f1,
39289+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
39290+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
39291+ 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
39292+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200233, 0x0060000a, 0x00104800,
39293+ 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00,
39294+ 0x00108a14, 0x00200020, 0x00100b00, 0x00134b2c, 0x0010cd00, 0x0010cd04,
39295+ 0x00114d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06,
39296+ 0x002002d2, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684,
39297+ 0x00800001, 0x00200b1a, 0x0060000a, 0x00206380, 0x0040788a, 0x00201480,
39298+ 0x00800041, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x0020007a,
39299+ 0x0060000a, 0x00104280, 0x002002d2, 0x0060000a, 0x00200004, 0x00800001,
39300+ 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000,
39301+ 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060,
39302+ 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a,
39303+ 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x00940400, 0x00200020,
39304+ 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305,
39305+ 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
39306+};
39307+
39308+static uint32_t nv43_ctx_voodoo[] = {
39309+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39310+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,
39311+ 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39312+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
39313+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39314+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39315+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39316+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39317+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39318+ 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1,
39319+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
39320+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
39321+ 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
39322+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
39323+ 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200233, 0x0060000a,
39324+ 0x00104800, 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965,
39325+ 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04,
39326+ 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06,
39327+ 0x002002c8, 0x0060000a, 0x00300000, 0x00200680, 0x00407200, 0x00200684,
39328+ 0x00800001, 0x00200b10, 0x0060000a, 0x00203870, 0x0040788a, 0x00201350,
39329+ 0x00800041, 0x00407c84, 0x00201560, 0x00800002, 0x00408d00, 0x00600006,
39330+ 0x00700003, 0x004086e6, 0x00700080, 0x002002c8, 0x0060000a, 0x00200004,
39331+ 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884,
39332+ 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a,
39333+ 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,
39334+ 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,
39335+ 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,
39336+ 0x00940400, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,
39337+ 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,
39338+ ~0
39339+};
39340+
39341+static uint32_t nv44_ctx_voodoo[] = {
39342+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39343+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409a65, 0x00409f06,
39344+ 0x0040ac68, 0x0040248f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
39345+ 0x001041c6, 0x00104040, 0x00200001, 0x0060000a, 0x00700000, 0x001040c5,
39346+ 0x00402320, 0x00402321, 0x00402322, 0x00402324, 0x00402326, 0x0040232b,
39347+ 0x001040c5, 0x00402328, 0x001040c5, 0x00402320, 0x00402468, 0x0060000d,
39348+ 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080, 0x00402be6,
39349+ 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d, 0x00110158,
39350+ 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9,
39351+ 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0,
39352+ 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143, 0x0011415f,
39353+ 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10, 0x001046ec,
39354+ 0x00500060, 0x00404b87, 0x0060000d, 0x004084e6, 0x002000f1, 0x0060000a,
39355+ 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b, 0x00168691,
39356+ 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x001646cc,
39357+ 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7,
39358+ 0x001043e1, 0x00500060, 0x00200232, 0x0060000a, 0x00104800, 0x00108901,
39359+ 0x00104910, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00,
39360+ 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08,
39361+ 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x002002c8,
39362+ 0x0060000a, 0x00300000, 0x00200080, 0x00407d00, 0x00200084, 0x00800001,
39363+ 0x00200510, 0x0060000a, 0x002037e0, 0x0040838a, 0x00201320, 0x00800029,
39364+ 0x00409400, 0x00600006, 0x004090e6, 0x00700080, 0x0020007a, 0x0060000a,
39365+ 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
39366+ 0x00200000, 0x0060000a, 0x00106002, 0x0040ac68, 0x00700000, 0x00200000,
39367+ 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060, 0x00600007,
39368+ 0x00409e88, 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a,
39369+ 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
39370+ 0x0060000b, 0x00500069, 0x0060000c, 0x00402c68, 0x0040ae06, 0x0040af05,
39371+ 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
39372+};
39373+
39374+static uint32_t nv46_ctx_voodoo[] = {
39375+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39376+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00408f65, 0x00409306,
39377+ 0x0040a068, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
39378+ 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968,
39379+ 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39380+ 0x004020e6, 0x007000a0, 0x00500060, 0x00200008, 0x0060000a, 0x0011814d,
39381+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39382+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39383+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39384+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39385+ 0x00500060, 0x00403f87, 0x0060000d, 0x004079e6, 0x002000f7, 0x0060000a,
39386+ 0x00200045, 0x00100620, 0x00104668, 0x0017466d, 0x0011068b, 0x00168691,
39387+ 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6, 0x00200022,
39388+ 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700, 0x0010c3d7, 0x001043e1,
39389+ 0x00500060, 0x0020027f, 0x0060000a, 0x00104800, 0x00108901, 0x00104910,
39390+ 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00148a00, 0x00108a14,
39391+ 0x00160b00, 0x00134b2c, 0x0010cd00, 0x0010cd04, 0x0010cd08, 0x00104d80,
39392+ 0x00104e00, 0x0012d600, 0x00105c00, 0x00104f06, 0x00105406, 0x00105709,
39393+ 0x00200316, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084,
39394+ 0x00800001, 0x0020055e, 0x0060000a, 0x002037e0, 0x0040788a, 0x00201320,
39395+ 0x00800029, 0x00408900, 0x00600006, 0x004085e6, 0x00700080, 0x00200081,
39396+ 0x0060000a, 0x00104280, 0x00200316, 0x0060000a, 0x00200004, 0x00800001,
39397+ 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a068, 0x00700000,
39398+ 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68, 0x00500060,
39399+ 0x00600007, 0x00409388, 0x0060000f, 0x00500060, 0x00200000, 0x0060000a,
39400+ 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
39401+ 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a206, 0x0040a305,
39402+ 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
39403+};
39404+
39405+//this is used for nv49 and nv4b
39406+static uint32_t nv49_4b_ctx_voodoo[] ={
39407+ 0x00400564, 0x00400505, 0x00408165, 0x00408206, 0x00409e68, 0x00200020,
39408+ 0x0060000a, 0x00700080, 0x00104042, 0x00200020, 0x0060000a, 0x00700000,
39409+ 0x001040c5, 0x00400f26, 0x00401068, 0x0060000d, 0x0070008f, 0x0070000e,
39410+ 0x00408d68, 0x004015e6, 0x007000a0, 0x00700080, 0x0040180f, 0x00700000,
39411+ 0x00200029, 0x0060000a, 0x0011814d, 0x00110158, 0x00105401, 0x0020003a,
39412+ 0x00100051, 0x001040c5, 0x0010c1c4, 0x001041c9, 0x0010c1dc, 0x00150210,
39413+ 0x0012c225, 0x00108238, 0x0010823e, 0x001242c0, 0x00200040, 0x00100280,
39414+ 0x00128100, 0x00128120, 0x00128143, 0x0011415f, 0x0010815c, 0x0010c140,
39415+ 0x00104029, 0x00110400, 0x00104d12, 0x00500060, 0x004071e6, 0x00200118,
39416+ 0x0060000a, 0x00200020, 0x00100620, 0x00154650, 0x00104668, 0x0017466d,
39417+ 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4,
39418+ 0x001146c6, 0x00200022, 0x001006cc, 0x001246f0, 0x002000c0, 0x00100700,
39419+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200290, 0x0060000a, 0x00104800,
39420+ 0x00108901, 0x00124920, 0x0020001f, 0x00100940, 0x00140965, 0x00144a00,
39421+ 0x00104a19, 0x0010ca1c, 0x00110b00, 0x00200028, 0x00100b08, 0x00134c2e,
39422+ 0x0010cd00, 0x0010cd04, 0x00120d08, 0x00104d80, 0x00104e00, 0x0012d600,
39423+ 0x00105c00, 0x00104f06, 0x00105406, 0x00105709, 0x00200340, 0x0060000a,
39424+ 0x00300000, 0x00200680, 0x00406a0f, 0x00200684, 0x00800001, 0x00200b88,
39425+ 0x0060000a, 0x00209540, 0x0040708a, 0x00201350, 0x00800041, 0x00407c0f,
39426+ 0x00600006, 0x00407ce6, 0x00700080, 0x002000a2, 0x0060000a, 0x00104280,
39427+ 0x00200340, 0x0060000a, 0x00200004, 0x00800001, 0x0070008e, 0x00408d68,
39428+ 0x0040020f, 0x00600006, 0x00409e68, 0x00600007, 0x0070000f, 0x0070000e,
39429+ 0x00408d68, 0x0091a880, 0x00901ffe, 0x10940000, 0x00200020, 0x0060000b,
39430+ 0x00500069, 0x0060000c, 0x00401568, 0x00700000, 0x00200001, 0x0040910e,
39431+ 0x00200021, 0x0060000a, 0x00409b0d, 0x00104a40, 0x00104a50, 0x00104a60,
39432+ 0x00104a70, 0x00104a80, 0x00104a90, 0x00104aa0, 0x00104ab0, 0x00407e0e,
39433+ 0x0040130f, 0x00408568, 0x0040a006, 0x0040a105, 0x00600009, 0x00700005,
39434+ 0x00700006, 0x0060000e, ~0
39435+};
39436+
39437+
39438+static uint32_t nv4a_ctx_voodoo[] = {
39439+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39440+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
39441+ 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39442+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
39443+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39444+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39445+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39446+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39447+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39448+ 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,
39449+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
39450+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
39451+ 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
39452+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
39453+ 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
39454+ 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
39455+ 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,
39456+ 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
39457+ 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
39458+ 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,
39459+ 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,
39460+ 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,
39461+ 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
39462+ 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,
39463+ 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,
39464+ 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,
39465+ 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,
39466+ 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
39467+ 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,
39468+ 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
39469+};
39470+
39471+static uint32_t nv4c_ctx_voodoo[] = {
39472+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39473+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409065, 0x00409406,
39474+ 0x0040a168, 0x0040198f, 0x00200001, 0x0060000a, 0x00700080, 0x00104042,
39475+ 0x00200001, 0x0060000a, 0x00700000, 0x001040c5, 0x00401826, 0x00401968,
39476+ 0x0060000d, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39477+ 0x004020e6, 0x007000a0, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39478+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39479+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39480+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39481+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39482+ 0x0010427e, 0x001046ec, 0x00500060, 0x00404187, 0x0060000d, 0x00407ae6,
39483+ 0x002000f2, 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682,
39484+ 0x0011068b, 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4,
39485+ 0x001146c6, 0x00200020, 0x001006cc, 0x001046ed, 0x001246f0, 0x002000c0,
39486+ 0x00100700, 0x0010c3d7, 0x001043e1, 0x00500060, 0x00200234, 0x0060000a,
39487+ 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
39488+ 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00,
39489+ 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
39490+ 0x00104f06, 0x002002c0, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
39491+ 0x00200084, 0x00800001, 0x00200508, 0x0060000a, 0x00201320, 0x0040798a,
39492+ 0xfffffaf8, 0x00800029, 0x00408a00, 0x00600006, 0x004086e6, 0x00700080,
39493+ 0x0020007a, 0x0060000a, 0x00104280, 0x002002c0, 0x0060000a, 0x00200004,
39494+ 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a168,
39495+ 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080, 0x00400a68,
39496+ 0x00500060, 0x00600007, 0x00409488, 0x0060000f, 0x00500060, 0x00200000,
39497+ 0x0060000a, 0x00700000, 0x00106001, 0x00910880, 0x00901ffe, 0x01940000,
39498+ 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00402168, 0x0040a306,
39499+ 0x0040a405, 0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
39500+};
39501+
39502+static uint32_t nv4e_ctx_voodoo[] = {
39503+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
39504+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409565, 0x00409a06,
39505+ 0x0040a868, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
39506+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
39507+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
39508+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
39509+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
39510+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
39511+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
39512+ 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407ce6, 0x002000f1,
39513+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
39514+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
39515+ 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
39516+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
39517+ 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
39518+ 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
39519+ 0x00140965, 0x00148a00, 0x00108a14, 0x00140b00, 0x00134b2c, 0x0010cd00,
39520+ 0x0010cd04, 0x00104d08, 0x00104d80, 0x00104e00, 0x00105c00, 0x00104f06,
39521+ 0x002002b2, 0x0060000a, 0x00300000, 0x00200080, 0x00407200, 0x00200084,
39522+ 0x00800001, 0x002004fa, 0x0060000a, 0x00201320, 0x0040788a, 0xfffffb06,
39523+ 0x00800029, 0x00407c84, 0x00200b20, 0x00800002, 0x00408d00, 0x00600006,
39524+ 0x00700003, 0x004086e6, 0x00700080, 0x002002b2, 0x0060000a, 0x00200004,
39525+ 0x00800001, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x0040a884,
39526+ 0x00700002, 0x00600004, 0x0040a868, 0x00700000, 0x00200000, 0x0060000a,
39527+ 0x00106002, 0x00700080, 0x00400a84, 0x00700002, 0x00400a68, 0x00500060,
39528+ 0x00600007, 0x00409988, 0x0060000f, 0x00000000, 0x00500060, 0x00200000,
39529+ 0x0060000a, 0x00700000, 0x00106001, 0x00700083, 0x00910880, 0x00901ffe,
39530+ 0x01940000, 0x00200020, 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68,
39531+ 0x0040aa06, 0x0040ab05, 0x00600009, 0x00700005, 0x00700006, 0x0060000e,
39532+ ~0
39533+};
39534+
39535+/*
39536+ * G70 0x47
39537+ * G71 0x49
39538+ * NV45 0x48
39539+ * G72[M] 0x46
39540+ * G73 0x4b
39541+ * C51_G7X 0x4c
39542+ * C51 0x4e
39543+ */
39544+int
39545+nv40_graph_init(struct drm_device *dev)
39546+{
39547+ struct drm_nouveau_private *dev_priv =
39548+ (struct drm_nouveau_private *)dev->dev_private;
39549+ uint32_t *ctx_voodoo;
39550+ uint32_t vramsz, tmp;
39551+ int i, j;
39552+
39553+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
39554+ ~NV_PMC_ENABLE_PGRAPH);
39555+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
39556+ NV_PMC_ENABLE_PGRAPH);
39557+
39558+ switch (dev_priv->chipset) {
39559+ case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
39560+ case 0x41:
39561+ case 0x42: ctx_voodoo = nv41_ctx_voodoo; break;
39562+ case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
39563+ case 0x44: ctx_voodoo = nv44_ctx_voodoo; break;
39564+ case 0x46: ctx_voodoo = nv46_ctx_voodoo; break;
39565+ case 0x49: ctx_voodoo = nv49_4b_ctx_voodoo; break;
39566+ case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
39567+ case 0x4b: ctx_voodoo = nv49_4b_ctx_voodoo; break;
39568+ case 0x4c: ctx_voodoo = nv4c_ctx_voodoo; break;
39569+ case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
39570+ default:
39571+ DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",
39572+ dev_priv->chipset);
39573+ ctx_voodoo = NULL;
39574+ break;
39575+ }
39576+
39577+ /* Load the context voodoo onto the card */
39578+ if (ctx_voodoo) {
39579+ DRM_DEBUG("Loading context-switch voodoo\n");
39580+ i = 0;
39581+
39582+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
39583+ while (ctx_voodoo[i] != ~0) {
39584+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]);
39585+ i++;
39586+ }
39587+ }
39588+
39589+ /* No context present currently */
39590+ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
39591+
39592+ NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
39593+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
39594+
39595+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
39596+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
39597+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);
39598+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xe0de8055);
39599+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
39600+ NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
39601+
39602+ NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
39603+ NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
39604+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
39605+
39606+ j = NV_READ(0x1540) & 0xff;
39607+ if (j) {
39608+ for (i=0; !(j&1); j>>=1, i++);
39609+ NV_WRITE(0x405000, i);
39610+ }
39611+
39612+ if (dev_priv->chipset == 0x40) {
39613+ NV_WRITE(0x4009b0, 0x83280fff);
39614+ NV_WRITE(0x4009b4, 0x000000a0);
39615+ } else {
39616+ NV_WRITE(0x400820, 0x83280eff);
39617+ NV_WRITE(0x400824, 0x000000a0);
39618+ }
39619+
39620+ switch (dev_priv->chipset) {
39621+ case 0x40:
39622+ case 0x45:
39623+ NV_WRITE(0x4009b8, 0x0078e366);
39624+ NV_WRITE(0x4009bc, 0x0000014c);
39625+ break;
39626+ case 0x41:
39627+ case 0x42: /* pciid also 0x00Cx */
39628+// case 0x0120: //XXX (pciid)
39629+ NV_WRITE(0x400828, 0x007596ff);
39630+ NV_WRITE(0x40082c, 0x00000108);
39631+ break;
39632+ case 0x43:
39633+ NV_WRITE(0x400828, 0x0072cb77);
39634+ NV_WRITE(0x40082c, 0x00000108);
39635+ break;
39636+ case 0x44:
39637+ case 0x46: /* G72 */
39638+ case 0x4a:
39639+ case 0x4c: /* G7x-based C51 */
39640+ case 0x4e:
39641+ NV_WRITE(0x400860, 0);
39642+ NV_WRITE(0x400864, 0);
39643+ break;
39644+ case 0x47: /* G70 */
39645+ case 0x49: /* G71 */
39646+ case 0x4b: /* G73 */
39647+ NV_WRITE(0x400828, 0x07830610);
39648+ NV_WRITE(0x40082c, 0x0000016A);
39649+ break;
39650+ default:
39651+ break;
39652+ }
39653+
39654+ NV_WRITE(0x400b38, 0x2ffff800);
39655+ NV_WRITE(0x400b3c, 0x00006000);
39656+
39657+ /* copy tile info from PFB */
39658+ switch (dev_priv->chipset) {
39659+ case 0x40: /* vanilla NV40 */
39660+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
39661+ tmp = NV_READ(NV10_PFB_TILE(i));
39662+ NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
39663+ NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
39664+ tmp = NV_READ(NV10_PFB_TLIMIT(i));
39665+ NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
39666+ NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
39667+ tmp = NV_READ(NV10_PFB_TSIZE(i));
39668+ NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
39669+ NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
39670+ tmp = NV_READ(NV10_PFB_TSTATUS(i));
39671+ NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
39672+ NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
39673+ }
39674+ break;
39675+ case 0x44:
39676+ case 0x4a:
39677+ case 0x4e: /* NV44-based cores don't have 0x406900? */
39678+ for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {
39679+ tmp = NV_READ(NV40_PFB_TILE(i));
39680+ NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
39681+ tmp = NV_READ(NV40_PFB_TLIMIT(i));
39682+ NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
39683+ tmp = NV_READ(NV40_PFB_TSIZE(i));
39684+ NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
39685+ tmp = NV_READ(NV40_PFB_TSTATUS(i));
39686+ NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
39687+ }
39688+ break;
39689+ case 0x46:
39690+ case 0x47:
39691+ case 0x49:
39692+ case 0x4b: /* G7X-based cores */
39693+ for (i=0; i<NV40_PFB_TILE__SIZE_1; i++) {
39694+ tmp = NV_READ(NV40_PFB_TILE(i));
39695+ NV_WRITE(NV47_PGRAPH_TILE0(i), tmp);
39696+ NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
39697+ tmp = NV_READ(NV40_PFB_TLIMIT(i));
39698+ NV_WRITE(NV47_PGRAPH_TLIMIT0(i), tmp);
39699+ NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
39700+ tmp = NV_READ(NV40_PFB_TSIZE(i));
39701+ NV_WRITE(NV47_PGRAPH_TSIZE0(i), tmp);
39702+ NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
39703+ tmp = NV_READ(NV40_PFB_TSTATUS(i));
39704+ NV_WRITE(NV47_PGRAPH_TSTATUS0(i), tmp);
39705+ NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
39706+ }
39707+ break;
39708+ default: /* everything else */
39709+ for (i=0; i<NV40_PFB_TILE__SIZE_0; i++) {
39710+ tmp = NV_READ(NV40_PFB_TILE(i));
39711+ NV_WRITE(NV40_PGRAPH_TILE0(i), tmp);
39712+ NV_WRITE(NV40_PGRAPH_TILE1(i), tmp);
39713+ tmp = NV_READ(NV40_PFB_TLIMIT(i));
39714+ NV_WRITE(NV40_PGRAPH_TLIMIT0(i), tmp);
39715+ NV_WRITE(NV40_PGRAPH_TLIMIT1(i), tmp);
39716+ tmp = NV_READ(NV40_PFB_TSIZE(i));
39717+ NV_WRITE(NV40_PGRAPH_TSIZE0(i), tmp);
39718+ NV_WRITE(NV40_PGRAPH_TSIZE1(i), tmp);
39719+ tmp = NV_READ(NV40_PFB_TSTATUS(i));
39720+ NV_WRITE(NV40_PGRAPH_TSTATUS0(i), tmp);
39721+ NV_WRITE(NV40_PGRAPH_TSTATUS1(i), tmp);
39722+ }
39723+ break;
39724+ }
39725+
39726+ /* begin RAM config */
39727+ vramsz = drm_get_resource_len(dev, 0) - 1;
39728+ switch (dev_priv->chipset) {
39729+ case 0x40:
39730+ NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
39731+ NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
39732+ NV_WRITE(0x4069A4, NV_READ(NV04_PFB_CFG0));
39733+ NV_WRITE(0x4069A8, NV_READ(NV04_PFB_CFG1));
39734+ NV_WRITE(0x400820, 0);
39735+ NV_WRITE(0x400824, 0);
39736+ NV_WRITE(0x400864, vramsz);
39737+ NV_WRITE(0x400868, vramsz);
39738+ break;
39739+ default:
39740+ switch (dev_priv->chipset) {
39741+ case 0x46:
39742+ case 0x47:
39743+ case 0x49:
39744+ case 0x4b:
39745+ NV_WRITE(0x400DF0, NV_READ(NV04_PFB_CFG0));
39746+ NV_WRITE(0x400DF4, NV_READ(NV04_PFB_CFG1));
39747+ break;
39748+ default:
39749+ NV_WRITE(0x4009F0, NV_READ(NV04_PFB_CFG0));
39750+ NV_WRITE(0x4009F4, NV_READ(NV04_PFB_CFG1));
39751+ break;
39752+ }
39753+ NV_WRITE(0x4069F0, NV_READ(NV04_PFB_CFG0));
39754+ NV_WRITE(0x4069F4, NV_READ(NV04_PFB_CFG1));
39755+ NV_WRITE(0x400840, 0);
39756+ NV_WRITE(0x400844, 0);
39757+ NV_WRITE(0x4008A0, vramsz);
39758+ NV_WRITE(0x4008A4, vramsz);
39759+ break;
39760+ }
39761+
39762+ /* per-context state, doesn't belong here */
39763+ NV_WRITE(0x400B20, 0x00000000);
39764+ NV_WRITE(0x400B04, 0xFFFFFFFF);
39765+
39766+ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
39767+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
39768+ tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
39769+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
39770+
39771+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
39772+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
39773+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
39774+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
39775+
39776+ return 0;
39777+}
39778+
39779+void nv40_graph_takedown(struct drm_device *dev)
39780+{
39781+}
39782+
39783Index: git/shared-core/nv40_mc.c
39784===================================================================
39785--- /dev/null 1970-01-01 00:00:00.000000000 +0000
39786+++ git/shared-core/nv40_mc.c 2008-12-12 17:35:22.000000000 +0000
39787@@ -0,0 +1,39 @@
39788+#include "drmP.h"
39789+#include "drm.h"
39790+#include "nouveau_drv.h"
39791+#include "nouveau_drm.h"
39792+
39793+int
39794+nv40_mc_init(struct drm_device *dev)
39795+{
39796+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39797+ uint32_t tmp;
39798+
39799+ /* Power up everything, resetting each individual unit will
39800+ * be done later if needed.
39801+ */
39802+ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
39803+
39804+ switch (dev_priv->chipset) {
39805+ case 0x44:
39806+ case 0x46: /* G72 */
39807+ case 0x4e:
39808+ case 0x4c: /* C51_G7X */
39809+ tmp = NV_READ(NV40_PFB_020C);
39810+ NV_WRITE(NV40_PMC_1700, tmp);
39811+ NV_WRITE(NV40_PMC_1704, 0);
39812+ NV_WRITE(NV40_PMC_1708, 0);
39813+ NV_WRITE(NV40_PMC_170C, tmp);
39814+ break;
39815+ default:
39816+ break;
39817+ }
39818+
39819+ return 0;
39820+}
39821+
39822+void
39823+nv40_mc_takedown(struct drm_device *dev)
39824+{
39825+}
39826+
39827Index: git/shared-core/nv50_fifo.c
39828===================================================================
39829--- /dev/null 1970-01-01 00:00:00.000000000 +0000
39830+++ git/shared-core/nv50_fifo.c 2008-12-12 17:35:22.000000000 +0000
39831@@ -0,0 +1,327 @@
39832+/*
39833+ * Copyright (C) 2007 Ben Skeggs.
39834+ * All Rights Reserved.
39835+ *
39836+ * Permission is hereby granted, free of charge, to any person obtaining
39837+ * a copy of this software and associated documentation files (the
39838+ * "Software"), to deal in the Software without restriction, including
39839+ * without limitation the rights to use, copy, modify, merge, publish,
39840+ * distribute, sublicense, and/or sell copies of the Software, and to
39841+ * permit persons to whom the Software is furnished to do so, subject to
39842+ * the following conditions:
39843+ *
39844+ * The above copyright notice and this permission notice (including the
39845+ * next paragraph) shall be included in all copies or substantial
39846+ * portions of the Software.
39847+ *
39848+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39849+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39850+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
39851+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39852+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39853+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
39854+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
39855+ *
39856+ */
39857+
39858+#include "drmP.h"
39859+#include "drm.h"
39860+#include "nouveau_drv.h"
39861+
39862+typedef struct {
39863+ struct nouveau_gpuobj_ref *thingo;
39864+} nv50_fifo_priv;
39865+
39866+#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
39867+
39868+static void
39869+nv50_fifo_init_thingo(struct drm_device *dev)
39870+{
39871+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39872+ nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
39873+ struct nouveau_gpuobj_ref *thingo = priv->thingo;
39874+ int i, fi=2;
39875+
39876+ DRM_DEBUG("\n");
39877+
39878+ INSTANCE_WR(thingo->gpuobj, 0, 0x7e);
39879+ INSTANCE_WR(thingo->gpuobj, 1, 0x7e);
39880+ for (i = 1; i < 127; i++, fi) {
39881+ if (dev_priv->fifos[i]) {
39882+ INSTANCE_WR(thingo->gpuobj, fi, i);
39883+ fi++;
39884+ }
39885+ }
39886+
39887+ NV_WRITE(0x32f4, thingo->instance >> 12);
39888+ NV_WRITE(0x32ec, fi);
39889+ NV_WRITE(0x2500, 0x101);
39890+}
39891+
39892+static int
39893+nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
39894+{
39895+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39896+ struct nouveau_channel *chan = dev_priv->fifos[channel];
39897+ uint32_t inst;
39898+
39899+ DRM_DEBUG("ch%d\n", channel);
39900+
39901+ if (!chan->ramfc)
39902+ return -EINVAL;
39903+
39904+ if (IS_G80) inst = chan->ramfc->instance >> 12;
39905+ else inst = chan->ramfc->instance >> 8;
39906+ NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
39907+ inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
39908+
39909+ if (!nt) nv50_fifo_init_thingo(dev);
39910+ return 0;
39911+}
39912+
39913+static void
39914+nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
39915+{
39916+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39917+ uint32_t inst;
39918+
39919+ DRM_DEBUG("ch%d, nt=%d\n", channel, nt);
39920+
39921+ if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
39922+ else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
39923+ NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
39924+
39925+ if (!nt) nv50_fifo_init_thingo(dev);
39926+}
39927+
39928+static void
39929+nv50_fifo_init_reset(struct drm_device *dev)
39930+{
39931+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39932+ uint32_t pmc_e;
39933+
39934+ DRM_DEBUG("\n");
39935+
39936+ pmc_e = NV_READ(NV03_PMC_ENABLE);
39937+ NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO);
39938+ pmc_e = NV_READ(NV03_PMC_ENABLE);
39939+ NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PFIFO);
39940+}
39941+
39942+static void
39943+nv50_fifo_init_intr(struct drm_device *dev)
39944+{
39945+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39946+
39947+ DRM_DEBUG("\n");
39948+
39949+ NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
39950+ NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
39951+}
39952+
39953+static void
39954+nv50_fifo_init_context_table(struct drm_device *dev)
39955+{
39956+ int i;
39957+
39958+ DRM_DEBUG("\n");
39959+
39960+ for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++)
39961+ nv50_fifo_channel_disable(dev, i, 1);
39962+ nv50_fifo_init_thingo(dev);
39963+}
39964+
39965+static void
39966+nv50_fifo_init_regs__nv(struct drm_device *dev)
39967+{
39968+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39969+
39970+ DRM_DEBUG("\n");
39971+
39972+ NV_WRITE(0x250c, 0x6f3cfc34);
39973+}
39974+
39975+static int
39976+nv50_fifo_init_regs(struct drm_device *dev)
39977+{
39978+ struct drm_nouveau_private *dev_priv = dev->dev_private;
39979+
39980+ DRM_DEBUG("\n");
39981+
39982+ NV_WRITE(0x2500, 0);
39983+ NV_WRITE(0x3250, 0);
39984+ NV_WRITE(0x3220, 0);
39985+ NV_WRITE(0x3204, 0);
39986+ NV_WRITE(0x3210, 0);
39987+ NV_WRITE(0x3270, 0);
39988+
39989+ /* Enable dummy channels setup by nv50_instmem.c */
39990+ nv50_fifo_channel_enable(dev, 0, 1);
39991+ nv50_fifo_channel_enable(dev, 127, 1);
39992+
39993+ return 0;
39994+}
39995+
39996+int
39997+nv50_fifo_init(struct drm_device *dev)
39998+{
39999+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40000+ nv50_fifo_priv *priv;
40001+ int ret;
40002+
40003+ DRM_DEBUG("\n");
40004+
40005+ priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
40006+ if (!priv)
40007+ return -ENOMEM;
40008+ dev_priv->Engine.fifo.priv = priv;
40009+
40010+ nv50_fifo_init_reset(dev);
40011+ nv50_fifo_init_intr(dev);
40012+
40013+ if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000,
40014+ NVOBJ_FLAG_ZERO_ALLOC,
40015+ &priv->thingo))) {
40016+ DRM_ERROR("error creating thingo: %d\n", ret);
40017+ return ret;
40018+ }
40019+
40020+ nv50_fifo_init_context_table(dev);
40021+
40022+ nv50_fifo_init_regs__nv(dev);
40023+ if ((ret = nv50_fifo_init_regs(dev)))
40024+ return ret;
40025+
40026+ return 0;
40027+}
40028+
40029+void
40030+nv50_fifo_takedown(struct drm_device *dev)
40031+{
40032+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40033+ nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
40034+
40035+ DRM_DEBUG("\n");
40036+
40037+ if (!priv)
40038+ return;
40039+
40040+ nouveau_gpuobj_ref_del(dev, &priv->thingo);
40041+
40042+ dev_priv->Engine.fifo.priv = NULL;
40043+ drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
40044+}
40045+
40046+int
40047+nv50_fifo_create_context(struct nouveau_channel *chan)
40048+{
40049+ struct drm_device *dev = chan->dev;
40050+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40051+ struct nouveau_gpuobj *ramfc = NULL;
40052+ int ret;
40053+
40054+ DRM_DEBUG("ch%d\n", chan->id);
40055+
40056+ if (IS_G80) {
40057+ uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
40058+ uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
40059+ if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
40060+ vram_offset, 0x100,
40061+ NVOBJ_FLAG_ZERO_ALLOC |
40062+ NVOBJ_FLAG_ZERO_FREE,
40063+ &ramfc, &chan->ramfc)))
40064+ return ret;
40065+ } else {
40066+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100,
40067+ 256,
40068+ NVOBJ_FLAG_ZERO_ALLOC |
40069+ NVOBJ_FLAG_ZERO_FREE,
40070+ &chan->ramfc)))
40071+ return ret;
40072+ ramfc = chan->ramfc->gpuobj;
40073+ }
40074+
40075+ INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4);
40076+ INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4));
40077+ INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */
40078+ INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff);
40079+ INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff);
40080+ INSTANCE_WR(ramfc, 0x10/4, 0x00000000);
40081+ INSTANCE_WR(ramfc, 0x08/4, 0x00000000);
40082+ INSTANCE_WR(ramfc, 0x40/4, 0x00000000);
40083+ INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0);
40084+ INSTANCE_WR(ramfc, 0x54/4, 0x000f0000);
40085+ INSTANCE_WR(ramfc, 0x7c/4, 0x30000001);
40086+ INSTANCE_WR(ramfc, 0x78/4, 0x00000000);
40087+ INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1);
40088+
40089+ if (!IS_G80) {
40090+ INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id);
40091+ INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance);
40092+
40093+ INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */
40094+ INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
40095+ }
40096+
40097+ if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) {
40098+ DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
40099+ nouveau_gpuobj_ref_del(dev, &chan->ramfc);
40100+ return ret;
40101+ }
40102+
40103+ return 0;
40104+}
40105+
40106+void
40107+nv50_fifo_destroy_context(struct nouveau_channel *chan)
40108+{
40109+ struct drm_device *dev = chan->dev;
40110+
40111+ DRM_DEBUG("ch%d\n", chan->id);
40112+
40113+ nv50_fifo_channel_disable(dev, chan->id, 0);
40114+
40115+ /* Dummy channel, also used on ch 127 */
40116+ if (chan->id == 0)
40117+ nv50_fifo_channel_disable(dev, 127, 0);
40118+
40119+ nouveau_gpuobj_ref_del(dev, &chan->ramfc);
40120+}
40121+
40122+int
40123+nv50_fifo_load_context(struct nouveau_channel *chan)
40124+{
40125+ struct drm_device *dev = chan->dev;
40126+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40127+ struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
40128+
40129+ DRM_DEBUG("ch%d\n", chan->id);
40130+
40131+ /*XXX: incomplete, only touches the regs that NV does */
40132+
40133+ NV_WRITE(0x3244, 0);
40134+ NV_WRITE(0x3240, 0);
40135+
40136+ NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4));
40137+ NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4));
40138+ NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4));
40139+ NV_WRITE(0x3254, 1);
40140+ NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4));
40141+
40142+ if (!IS_G80) {
40143+ NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4));
40144+ NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4));
40145+ }
40146+
40147+ NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
40148+ return 0;
40149+}
40150+
40151+int
40152+nv50_fifo_save_context(struct nouveau_channel *chan)
40153+{
40154+ DRM_DEBUG("ch%d\n", chan->id);
40155+ DRM_ERROR("stub!\n");
40156+ return 0;
40157+}
40158+
40159Index: git/shared-core/nv50_graph.c
40160===================================================================
40161--- /dev/null 1970-01-01 00:00:00.000000000 +0000
40162+++ git/shared-core/nv50_graph.c 2008-12-12 17:35:22.000000000 +0000
40163@@ -0,0 +1,316 @@
40164+/*
40165+ * Copyright (C) 2007 Ben Skeggs.
40166+ * All Rights Reserved.
40167+ *
40168+ * Permission is hereby granted, free of charge, to any person obtaining
40169+ * a copy of this software and associated documentation files (the
40170+ * "Software"), to deal in the Software without restriction, including
40171+ * without limitation the rights to use, copy, modify, merge, publish,
40172+ * distribute, sublicense, and/or sell copies of the Software, and to
40173+ * permit persons to whom the Software is furnished to do so, subject to
40174+ * the following conditions:
40175+ *
40176+ * The above copyright notice and this permission notice (including the
40177+ * next paragraph) shall be included in all copies or substantial
40178+ * portions of the Software.
40179+ *
40180+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40181+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
40182+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40183+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
40184+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40185+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40186+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40187+ *
40188+ */
40189+
40190+#include "drmP.h"
40191+#include "drm.h"
40192+#include "nouveau_drv.h"
40193+
40194+#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
40195+
40196+static void
40197+nv50_graph_init_reset(struct drm_device *dev)
40198+{
40199+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40200+ uint32_t pmc_e;
40201+
40202+ DRM_DEBUG("\n");
40203+
40204+ pmc_e = NV_READ(NV03_PMC_ENABLE);
40205+ NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PGRAPH);
40206+ pmc_e = NV_READ(NV03_PMC_ENABLE);
40207+ NV_WRITE(NV03_PMC_ENABLE, pmc_e | NV_PMC_ENABLE_PGRAPH);
40208+}
40209+
40210+static void
40211+nv50_graph_init_intr(struct drm_device *dev)
40212+{
40213+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40214+
40215+ DRM_DEBUG("\n");
40216+ NV_WRITE(NV03_PGRAPH_INTR, 0xffffffff);
40217+ NV_WRITE(NV40_PGRAPH_INTR_EN, 0xffffffff);
40218+}
40219+
40220+static void
40221+nv50_graph_init_regs__nv(struct drm_device *dev)
40222+{
40223+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40224+
40225+ DRM_DEBUG("\n");
40226+
40227+ NV_WRITE(0x400804, 0xc0000000);
40228+ NV_WRITE(0x406800, 0xc0000000);
40229+ NV_WRITE(0x400c04, 0xc0000000);
40230+ NV_WRITE(0x401804, 0xc0000000);
40231+ NV_WRITE(0x405018, 0xc0000000);
40232+ NV_WRITE(0x402000, 0xc0000000);
40233+
40234+ NV_WRITE(0x400108, 0xffffffff);
40235+
40236+ NV_WRITE(0x400824, 0x00004000);
40237+ NV_WRITE(0x400500, 0x00010001);
40238+}
40239+
40240+static void
40241+nv50_graph_init_regs(struct drm_device *dev)
40242+{
40243+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40244+
40245+ DRM_DEBUG("\n");
40246+
40247+ NV_WRITE(NV04_PGRAPH_DEBUG_3, (1<<2) /* HW_CONTEXT_SWITCH_ENABLED */);
40248+}
40249+
40250+static uint32_t nv84_ctx_voodoo[] = {
40251+ 0x0070008e, 0x0070009c, 0x00200020, 0x00600008, 0x0050004c, 0x00400e89,
40252+ 0x00200000, 0x00600007, 0x00300000, 0x00c000ff, 0x00200000, 0x008000ff,
40253+ 0x00700009, 0x0041634d, 0x00402944, 0x00402905, 0x0040290d, 0x00413e06,
40254+ 0x00600005, 0x004015c5, 0x00600011, 0x0040270b, 0x004021c5, 0x00700000,
40255+ 0x00700081, 0x00600004, 0x0050004a, 0x00216f40, 0x00600007, 0x00c02801,
40256+ 0x0020002e, 0x00800001, 0x005000cb, 0x0090ffff, 0x0091ffff, 0x00200020,
40257+ 0x00600008, 0x0050004c, 0x00600009, 0x00413e45, 0x0041594d, 0x0070009d,
40258+ 0x00402dcf, 0x0070009f, 0x0050009f, 0x00402ac0, 0x00200200, 0x00600008,
40259+ 0x00402a4f, 0x00402ac0, 0x004030cc, 0x00700081, 0x00200000, 0x00600006,
40260+ 0x00700000, 0x00111bfc, 0x00700083, 0x00300000, 0x00216f40, 0x00600007,
40261+ 0x00c00b01, 0x0020001e, 0x00800001, 0x005000cb, 0x00c000ff, 0x00700080,
40262+ 0x00700083, 0x00200047, 0x00600006, 0x0011020a, 0x00200480, 0x00600007,
40263+ 0x00300000, 0x00c000ff, 0x00c800ff, 0x00414907, 0x00202916, 0x008000ff,
40264+ 0x0040508c, 0x005000cb, 0x00a0023f, 0x00200040, 0x00600006, 0x0070000f,
40265+ 0x00170202, 0x0011020a, 0x00200032, 0x0010020d, 0x001c0242, 0x00120302,
40266+ 0x00140402, 0x00180500, 0x00130509, 0x00150550, 0x00110605, 0x0020000f,
40267+ 0x00100607, 0x00110700, 0x00110900, 0x00120902, 0x00110a00, 0x00160b02,
40268+ 0x00120b28, 0x00140b2b, 0x00110c01, 0x00111400, 0x00111405, 0x00111407,
40269+ 0x00111409, 0x0011140b, 0x002000cb, 0x00101500, 0x0040790f, 0x0040794b,
40270+ 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040798c,
40271+ 0x005000cb, 0x00000000, 0x0020002b, 0x00101a05, 0x00131c00, 0x00121c04,
40272+ 0x00141c20, 0x00111c25, 0x00131c40, 0x00121c44, 0x00141c60, 0x00111c65,
40273+ 0x00131c80, 0x00121c84, 0x00141ca0, 0x00111ca5, 0x00131cc0, 0x00121cc4,
40274+ 0x00141ce0, 0x00111ce5, 0x00131f00, 0x00191f40, 0x0040a1e0, 0x002001ed,
40275+ 0x00600006, 0x00200044, 0x00102080, 0x001120c6, 0x001520c9, 0x001920d0,
40276+ 0x00122100, 0x00122103, 0x00162200, 0x00122207, 0x00112280, 0x00112300,
40277+ 0x00112302, 0x00122380, 0x0011238b, 0x00112394, 0x0011239c, 0x0040bee1,
40278+ 0x00200254, 0x00600006, 0x00200044, 0x00102480, 0x0040af0f, 0x0040af4b,
40279+ 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040af8c,
40280+ 0x005000cb, 0x00000000, 0x001124c6, 0x001524c9, 0x001924d0, 0x00122500,
40281+ 0x00122503, 0x00162600, 0x00122607, 0x00112680, 0x00112700, 0x00112702,
40282+ 0x00122780, 0x0011278b, 0x00112794, 0x0011279c, 0x0040d1e2, 0x002002bb,
40283+ 0x00600006, 0x00200044, 0x00102880, 0x001128c6, 0x001528c9, 0x001928d0,
40284+ 0x00122900, 0x00122903, 0x00162a00, 0x00122a07, 0x00112a80, 0x00112b00,
40285+ 0x00112b02, 0x00122b80, 0x00112b8b, 0x00112b94, 0x00112b9c, 0x0040eee3,
40286+ 0x00200322, 0x00600006, 0x00200044, 0x00102c80, 0x0040df0f, 0x0040df4b,
40287+ 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x0040df8c,
40288+ 0x005000cb, 0x00000000, 0x00112cc6, 0x00152cc9, 0x00192cd0, 0x00122d00,
40289+ 0x00122d03, 0x00162e00, 0x00122e07, 0x00112e80, 0x00112f00, 0x00112f02,
40290+ 0x00122f80, 0x00112f8b, 0x00112f94, 0x00112f9c, 0x004101e4, 0x00200389,
40291+ 0x00600006, 0x00200044, 0x00103080, 0x001130c6, 0x001530c9, 0x001930d0,
40292+ 0x00123100, 0x00123103, 0x00163200, 0x00123207, 0x00113280, 0x00113300,
40293+ 0x00113302, 0x00123380, 0x0011338b, 0x00113394, 0x0011339c, 0x00411ee5,
40294+ 0x002003f0, 0x00600006, 0x00200044, 0x00103480, 0x00410f0f, 0x00410f4b,
40295+ 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x0070008f, 0x00410f8c,
40296+ 0x005000cb, 0x00000000, 0x001134c6, 0x001534c9, 0x001934d0, 0x00123500,
40297+ 0x00123503, 0x00163600, 0x00123607, 0x00113680, 0x00113700, 0x00113702,
40298+ 0x00123780, 0x0011378b, 0x00113794, 0x0011379c, 0x00000000, 0x0041250f,
40299+ 0x005000cb, 0x00214d40, 0x00600007, 0x0020043e, 0x008800ff, 0x005000cb,
40300+ 0x00412887, 0x0060000a, 0x00000000, 0x00413700, 0x007000a0, 0x00700080,
40301+ 0x00200480, 0x00600007, 0x00200004, 0x00c000ff, 0x008000ff, 0x005000cb,
40302+ 0x00700000, 0x00200000, 0x00600006, 0x00111bfe, 0x0041594d, 0x00700000,
40303+ 0x00200000, 0x00600006, 0x00111bfe, 0x00700080, 0x0070001d, 0x0040114d,
40304+ 0x00700081, 0x00600004, 0x0050004a, 0x00414388, 0x0060000b, 0x00200000,
40305+ 0x00600006, 0x00700000, 0x0041590b, 0x00111bfd, 0x0040424d, 0x00202916,
40306+ 0x008000fd, 0x005000cb, 0x00c00002, 0x00200480, 0x00600007, 0x00200160,
40307+ 0x00800002, 0x005000cb, 0x00c01802, 0x002027b6, 0x00800002, 0x005000cb,
40308+ 0x00404e4d, 0x0060000b, 0x0041574d, 0x00700001, 0x005000cf, 0x00700003,
40309+ 0x00415e06, 0x00415f05, 0x0060000d, 0x00700005, 0x0070000d, 0x00700006,
40310+ 0x0070000b, 0x0070000e, 0x0070001c, 0x0060000c, ~0
40311+};
40312+
40313+static void
40314+nv50_graph_init_ctxctl(struct drm_device *dev)
40315+{
40316+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40317+ uint32_t *voodoo;
40318+
40319+ DRM_DEBUG("\n");
40320+
40321+ switch (dev_priv->chipset) {
40322+ case 0x84:
40323+ voodoo = nv84_ctx_voodoo;
40324+ break;
40325+ default:
40326+ DRM_ERROR("no voodoo for chipset NV%02x\n", dev_priv->chipset);
40327+ break;
40328+ }
40329+
40330+ if (voodoo) {
40331+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
40332+ while (*voodoo != ~0) {
40333+ NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, *voodoo);
40334+ voodoo++;
40335+ }
40336+ }
40337+
40338+ NV_WRITE(0x400320, 4);
40339+ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0);
40340+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
40341+}
40342+
40343+int
40344+nv50_graph_init(struct drm_device *dev)
40345+{
40346+ DRM_DEBUG("\n");
40347+
40348+ nv50_graph_init_reset(dev);
40349+ nv50_graph_init_intr(dev);
40350+ nv50_graph_init_regs__nv(dev);
40351+ nv50_graph_init_regs(dev);
40352+ nv50_graph_init_ctxctl(dev);
40353+
40354+ return 0;
40355+}
40356+
40357+void
40358+nv50_graph_takedown(struct drm_device *dev)
40359+{
40360+ DRM_DEBUG("\n");
40361+}
40362+
40363+int
40364+nv50_graph_create_context(struct nouveau_channel *chan)
40365+{
40366+ struct drm_device *dev = chan->dev;
40367+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40368+ struct nouveau_engine *engine = &dev_priv->Engine;
40369+ struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
40370+ int grctx_size = 0x60000, hdr;
40371+ int ret;
40372+
40373+ DRM_DEBUG("ch%d\n", chan->id);
40374+
40375+ if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
40376+ grctx_size, 0x1000,
40377+ NVOBJ_FLAG_ZERO_ALLOC |
40378+ NVOBJ_FLAG_ZERO_FREE,
40379+ &chan->ramin_grctx)))
40380+ return ret;
40381+
40382+ hdr = IS_G80 ? 0x200 : 0x20;
40383+ INSTANCE_WR(ramin, (hdr + 0x00)/4, 0x00190002);
40384+ INSTANCE_WR(ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance +
40385+ grctx_size - 1);
40386+ INSTANCE_WR(ramin, (hdr + 0x08)/4, chan->ramin_grctx->instance);
40387+ INSTANCE_WR(ramin, (hdr + 0x0c)/4, 0);
40388+ INSTANCE_WR(ramin, (hdr + 0x10)/4, 0);
40389+ INSTANCE_WR(ramin, (hdr + 0x14)/4, 0x00010000);
40390+
40391+ if ((ret = engine->graph.load_context(chan))) {
40392+ DRM_ERROR("Error hacking up initial context: %d\n", ret);
40393+ return ret;
40394+ }
40395+
40396+ return 0;
40397+}
40398+
40399+void
40400+nv50_graph_destroy_context(struct nouveau_channel *chan)
40401+{
40402+ struct drm_device *dev = chan->dev;
40403+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40404+ int i, hdr;
40405+
40406+ DRM_DEBUG("ch%d\n", chan->id);
40407+
40408+ hdr = IS_G80 ? 0x200 : 0x20;
40409+ for (i=hdr; i<hdr+24; i+=4)
40410+ INSTANCE_WR(chan->ramin->gpuobj, i/4, 0);
40411+
40412+ nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
40413+}
40414+
40415+static int
40416+nv50_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
40417+{
40418+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40419+ uint32_t old_cp, tv = 20000;
40420+ int i;
40421+
40422+ DRM_DEBUG("inst=0x%08x, save=%d\n", inst, save);
40423+
40424+ old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
40425+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst | (1<<31));
40426+ NV_WRITE(0x400824, NV_READ(0x400824) |
40427+ (save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
40428+ NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
40429+ NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
40430+
40431+ for (i = 0; i < tv; i++) {
40432+ if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
40433+ break;
40434+ }
40435+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
40436+
40437+ if (i == tv) {
40438+ DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save);
40439+ DRM_ERROR("0x40030C = 0x%08x\n",
40440+ NV_READ(NV40_PGRAPH_CTXCTL_030C));
40441+ return -EBUSY;
40442+ }
40443+
40444+ return 0;
40445+}
40446+
40447+int
40448+nv50_graph_load_context(struct nouveau_channel *chan)
40449+{
40450+ struct drm_device *dev = chan->dev;
40451+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40452+ uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
40453+ int ret; (void)ret;
40454+
40455+ DRM_DEBUG("ch%d\n", chan->id);
40456+
40457+#if 0
40458+ if ((ret = nv50_graph_transfer_context(dev, inst, 0)))
40459+ return ret;
40460+#endif
40461+
40462+ NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
40463+ NV_WRITE(0x400320, 4);
40464+ NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, inst);
40465+
40466+ return 0;
40467+}
40468+
40469+int
40470+nv50_graph_save_context(struct nouveau_channel *chan)
40471+{
40472+ struct drm_device *dev = chan->dev;
40473+ uint32_t inst = ((chan->ramin->instance >> 12) | (1<<31));
40474+
40475+ DRM_DEBUG("ch%d\n", chan->id);
40476+
40477+ return nv50_graph_transfer_context(dev, inst, 1);
40478+}
40479+
40480Index: git/shared-core/nv50_mc.c
40481===================================================================
40482--- /dev/null 1970-01-01 00:00:00.000000000 +0000
40483+++ git/shared-core/nv50_mc.c 2008-12-12 17:35:22.000000000 +0000
40484@@ -0,0 +1,43 @@
40485+/*
40486+ * Copyright (C) 2007 Ben Skeggs.
40487+ * All Rights Reserved.
40488+ *
40489+ * Permission is hereby granted, free of charge, to any person obtaining
40490+ * a copy of this software and associated documentation files (the
40491+ * "Software"), to deal in the Software without restriction, including
40492+ * without limitation the rights to use, copy, modify, merge, publish,
40493+ * distribute, sublicense, and/or sell copies of the Software, and to
40494+ * permit persons to whom the Software is furnished to do so, subject to
40495+ * the following conditions:
40496+ *
40497+ * The above copyright notice and this permission notice (including the
40498+ * next paragraph) shall be included in all copies or substantial
40499+ * portions of the Software.
40500+ *
40501+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40502+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
40503+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40504+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
40505+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40506+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40507+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40508+ *
40509+ */
40510+
40511+#include "drmP.h"
40512+#include "drm.h"
40513+#include "nouveau_drv.h"
40514+
40515+int
40516+nv50_mc_init(struct drm_device *dev)
40517+{
40518+ struct drm_nouveau_private *dev_priv = dev->dev_private;
40519+
40520+ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
40521+
40522+ return 0;
40523+}
40524+
40525+void nv50_mc_takedown(struct drm_device *dev)
40526+{
40527+}
40528Index: git/shared-core/nv_drv.h
40529===================================================================
40530--- /dev/null 1970-01-01 00:00:00.000000000 +0000
40531+++ git/shared-core/nv_drv.h 2008-12-12 17:35:22.000000000 +0000
40532@@ -0,0 +1,52 @@
40533+/* nv_drv.h -- NV DRM template customization -*- linux-c -*-
40534+ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
40535+ *
40536+ * Copyright 2005 Lars Knoll <lars@trolltech.com>
40537+ * All Rights Reserved.
40538+ *
40539+ * Permission is hereby granted, free of charge, to any person obtaining a
40540+ * copy of this software and associated documentation files (the "Software"),
40541+ * to deal in the Software without restriction, including without limitation
40542+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
40543+ * and/or sell copies of the Software, and to permit persons to whom the
40544+ * Software is furnished to do so, subject to the following conditions:
40545+ *
40546+ * The above copyright notice and this permission notice (including the next
40547+ * paragraph) shall be included in all copies or substantial portions of the
40548+ * Software.
40549+ *
40550+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40551+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40552+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
40553+ * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
40554+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
40555+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40556+ * OTHER DEALINGS IN THE SOFTWARE.
40557+ *
40558+ * Authors:
40559+ * Lars Knoll <lars@trolltech.com>
40560+ */
40561+
40562+#ifndef __NV_H__
40563+#define __NV_H__
40564+
40565+/* General customization:
40566+ */
40567+
40568+#define DRIVER_AUTHOR "Lars Knoll"
40569+
40570+#define DRIVER_NAME "nv"
40571+#define DRIVER_DESC "NV"
40572+#define DRIVER_DATE "20051006"
40573+
40574+#define DRIVER_MAJOR 0
40575+#define DRIVER_MINOR 0
40576+#define DRIVER_PATCHLEVEL 1
40577+
40578+#define NV04 04
40579+#define NV10 10
40580+#define NV20 20
40581+#define NV30 30
40582+#define NV40 40
40583+
40584+#endif
40585Index: git/shared-core/psb_drm.h
40586===================================================================
40587--- /dev/null 1970-01-01 00:00:00.000000000 +0000
40588+++ git/shared-core/psb_drm.h 2008-12-12 17:35:22.000000000 +0000
40589@@ -0,0 +1,359 @@
40590+/**************************************************************************
40591+ * Copyright (c) 2007, Intel Corporation.
40592+ * All Rights Reserved.
40593+ *
40594+ * This program is free software; you can redistribute it and/or modify it
40595+ * under the terms and conditions of the GNU General Public License,
40596+ * version 2, as published by the Free Software Foundation.
40597+ *
40598+ * This program is distributed in the hope it will be useful, but WITHOUT
40599+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
40600+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
40601+ * more details.
40602+ *
40603+ * You should have received a copy of the GNU General Public License along with
40604+ * this program; if not, write to the Free Software Foundation, Inc.,
40605+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
40606+ *
40607+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
40608+ * develop this driver.
40609+ *
40610+ **************************************************************************/
40611+/*
40612+ */
40613+
40614+#ifndef _PSB_DRM_H_
40615+#define _PSB_DRM_H_
40616+
40617+#if defined(__linux__) && !defined(__KERNEL__)
40618+#include<stdint.h>
40619+#endif
40620+
40621+/*
40622+ * Intel Poulsbo driver package version.
40623+ *
40624+ */
40625+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
40626+#define PSB_PACKAGE_VERSION "2.0.0.32L.0007"
40627+
40628+#define DRM_PSB_SAREA_MAJOR 0
40629+#define DRM_PSB_SAREA_MINOR 1
40630+#define PSB_FIXED_SHIFT 16
40631+
40632+/*
40633+ * Public memory types.
40634+ */
40635+
40636+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
40637+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
40638+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
40639+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
40640+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
40641+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
40642+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
40643+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
40644+#define PSB_MEM_RASTGEOM_START 0x30000000
40645+
40646+typedef int32_t psb_fixed;
40647+typedef uint32_t psb_ufixed;
40648+
40649+static inline psb_fixed psb_int_to_fixed(int a)
40650+{
40651+ return a * (1 << PSB_FIXED_SHIFT);
40652+}
40653+
40654+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
40655+{
40656+ return a << PSB_FIXED_SHIFT;
40657+}
40658+
40659+/*Status of the command sent to the gfx device.*/
40660+typedef enum {
40661+ DRM_CMD_SUCCESS,
40662+ DRM_CMD_FAILED,
40663+ DRM_CMD_HANG
40664+} drm_cmd_status_t;
40665+
40666+struct drm_psb_scanout {
40667+ uint32_t buffer_id; /* DRM buffer object ID */
40668+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
40669+ uint32_t stride; /* Buffer stride in bytes */
40670+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
40671+ uint32_t width; /* Buffer width in pixels */
40672+ uint32_t height; /* Buffer height in lines */
40673+ psb_fixed transform[3][3]; /* Buffer composite transform */
40674+ /* (scaling, rot, reflect) */
40675+};
40676+
40677+#define DRM_PSB_SAREA_OWNERS 16
40678+#define DRM_PSB_SAREA_OWNER_2D 0
40679+#define DRM_PSB_SAREA_OWNER_3D 1
40680+
40681+#define DRM_PSB_SAREA_SCANOUTS 3
40682+
40683+struct drm_psb_sarea {
40684+ /* Track changes of this data structure */
40685+
40686+ uint32_t major;
40687+ uint32_t minor;
40688+
40689+ /* Last context to touch part of hw */
40690+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
40691+
40692+ /* Definition of front- and rotated buffers */
40693+ uint32_t num_scanouts;
40694+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
40695+
40696+ int planeA_x;
40697+ int planeA_y;
40698+ int planeA_w;
40699+ int planeA_h;
40700+ int planeB_x;
40701+ int planeB_y;
40702+ int planeB_w;
40703+ int planeB_h;
40704+ uint32_t msvdx_state;
40705+ uint32_t msvdx_context;
40706+};
40707+
40708+#define PSB_RELOC_MAGIC 0x67676767
40709+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
40710+#define PSB_RELOC_SHIFT_SHIFT 0
40711+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
40712+#define PSB_RELOC_ALSHIFT_SHIFT 16
40713+
40714+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
40715+ * buffer
40716+ */
40717+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
40718+ * buffer, relative to 2D
40719+ * base address
40720+ */
40721+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
40722+ * relative to PDS base address
40723+ */
40724+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
40725+ * buffer (for tiling)
40726+ */
40727+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
40728+ * relative to base reg
40729+ */
40730+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
40731+
40732+struct drm_psb_reloc {
40733+ uint32_t reloc_op;
40734+ uint32_t where; /* offset in destination buffer */
40735+ uint32_t buffer; /* Buffer reloc applies to */
40736+ uint32_t mask; /* Destination format: */
40737+ uint32_t shift; /* Destination format: */
40738+ uint32_t pre_add; /* Destination format: */
40739+ uint32_t background; /* Destination add */
40740+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
40741+ uint32_t arg0; /* Reloc-op dependant */
40742+ uint32_t arg1;
40743+};
40744+
40745+#define PSB_BO_FLAG_TA (1ULL << 48)
40746+#define PSB_BO_FLAG_SCENE (1ULL << 49)
40747+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
40748+#define PSB_BO_FLAG_USSE (1ULL << 51)
40749+
40750+#define PSB_ENGINE_2D 0
40751+#define PSB_ENGINE_VIDEO 1
40752+#define PSB_ENGINE_RASTERIZER 2
40753+#define PSB_ENGINE_TA 3
40754+#define PSB_ENGINE_HPRAST 4
40755+
40756+/*
40757+ * For this fence class we have a couple of
40758+ * fence types.
40759+ */
40760+
40761+#define _PSB_FENCE_EXE_SHIFT 0
40762+#define _PSB_FENCE_TA_DONE_SHIFT 1
40763+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
40764+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
40765+#define _PSB_FENCE_FEEDBACK_SHIFT 4
40766+
40767+#define _PSB_ENGINE_TA_FENCE_TYPES 5
40768+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
40769+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
40770+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
40771+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
40772+
40773+#define PSB_ENGINE_HPRAST 4
40774+#define PSB_NUM_ENGINES 5
40775+
40776+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
40777+#define PSB_TA_FLAG_LASTPASS (1 << 1)
40778+
40779+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
40780+
40781+struct drm_psb_scene {
40782+ int handle_valid;
40783+ uint32_t handle;
40784+ uint32_t w;
40785+ uint32_t h;
40786+ uint32_t num_buffers;
40787+};
40788+
40789+typedef struct drm_psb_cmdbuf_arg {
40790+ uint64_t buffer_list; /* List of buffers to validate */
40791+ uint64_t clip_rects; /* See i915 counterpart */
40792+ uint64_t scene_arg;
40793+ uint64_t fence_arg;
40794+
40795+ uint32_t ta_flags;
40796+
40797+ uint32_t ta_handle; /* TA reg-value pairs */
40798+ uint32_t ta_offset;
40799+ uint32_t ta_size;
40800+
40801+ uint32_t oom_handle;
40802+ uint32_t oom_offset;
40803+ uint32_t oom_size;
40804+
40805+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
40806+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
40807+ uint32_t cmdbuf_size;
40808+
40809+ uint32_t reloc_handle; /* Reloc buffer object */
40810+ uint32_t reloc_offset;
40811+ uint32_t num_relocs;
40812+
40813+ int32_t damage; /* Damage front buffer with cliprects */
40814+ /* Not implemented yet */
40815+ uint32_t fence_flags;
40816+ uint32_t engine;
40817+
40818+ /*
40819+ * Feedback;
40820+ */
40821+
40822+ uint32_t feedback_ops;
40823+ uint32_t feedback_handle;
40824+ uint32_t feedback_offset;
40825+ uint32_t feedback_breakpoints;
40826+ uint32_t feedback_size;
40827+} drm_psb_cmdbuf_arg_t;
40828+
40829+struct drm_psb_xhw_init_arg {
40830+ uint32_t operation;
40831+ uint32_t buffer_handle;
40832+};
40833+
40834+/*
40835+ * Feedback components:
40836+ */
40837+
40838+/*
40839+ * Vistest component. The number of these in the feedback buffer
40840+ * equals the number of vistest breakpoints + 1.
40841+ * This is currently the only feedback component.
40842+ */
40843+
40844+struct drm_psb_vistest {
40845+ uint32_t vt[8];
40846+};
40847+
40848+#define PSB_HW_COOKIE_SIZE 16
40849+#define PSB_HW_FEEDBACK_SIZE 8
40850+#define PSB_HW_OOM_CMD_SIZE 6
40851+
40852+struct drm_psb_xhw_arg {
40853+ uint32_t op;
40854+ int ret;
40855+ uint32_t irq_op;
40856+ uint32_t issue_irq;
40857+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
40858+ union {
40859+ struct {
40860+ uint32_t w;
40861+ uint32_t h;
40862+ uint32_t size;
40863+ uint32_t clear_p_start;
40864+ uint32_t clear_num_pages;
40865+ } si;
40866+ struct {
40867+ uint32_t fire_flags;
40868+ uint32_t hw_context;
40869+ uint32_t offset;
40870+ uint32_t engine;
40871+ uint32_t flags;
40872+ uint32_t rca;
40873+ uint32_t num_oom_cmds;
40874+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
40875+ } sb;
40876+ struct {
40877+ uint32_t pages;
40878+ uint32_t size;
40879+ } bi;
40880+ struct {
40881+ uint32_t bca;
40882+ uint32_t rca;
40883+ uint32_t flags;
40884+ } oom;
40885+ struct {
40886+ uint32_t pt_offset;
40887+ uint32_t param_offset;
40888+ uint32_t flags;
40889+ } bl;
40890+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
40891+ } arg;
40892+};
40893+
40894+#define DRM_PSB_CMDBUF 0x00
40895+#define DRM_PSB_XHW_INIT 0x01
40896+#define DRM_PSB_XHW 0x02
40897+#define DRM_PSB_SCENE_UNREF 0x03
40898+/* Controlling the kernel modesetting buffers */
40899+#define DRM_PSB_KMS_OFF 0x04
40900+#define DRM_PSB_KMS_ON 0x05
40901+
40902+#define PSB_XHW_INIT 0x00
40903+#define PSB_XHW_TAKEDOWN 0x01
40904+
40905+#define PSB_XHW_FIRE_RASTER 0x00
40906+#define PSB_XHW_SCENE_INFO 0x01
40907+#define PSB_XHW_SCENE_BIND_FIRE 0x02
40908+#define PSB_XHW_TA_MEM_INFO 0x03
40909+#define PSB_XHW_RESET_DPM 0x04
40910+#define PSB_XHW_OOM 0x05
40911+#define PSB_XHW_TERMINATE 0x06
40912+#define PSB_XHW_VISTEST 0x07
40913+#define PSB_XHW_RESUME 0x08
40914+#define PSB_XHW_TA_MEM_LOAD 0x09
40915+
40916+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
40917+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
40918+#define PSB_SCENE_FLAG_SETUP (1 << 2)
40919+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
40920+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
40921+
40922+#define PSB_TA_MEM_FLAG_TA (1 << 0)
40923+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
40924+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
40925+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
40926+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
40927+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
40928+
40929+/*Raster fire will deallocate memory */
40930+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
40931+/*Isp reset needed due to change in ZLS format */
40932+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
40933+/*These are set by Xpsb. */
40934+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
40935+/*The task has had at least one OOM and Xpsb will
40936+ send back messages on each fire. */
40937+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
40938+
40939+#define PSB_SCENE_ENGINE_TA 0
40940+#define PSB_SCENE_ENGINE_RASTER 1
40941+#define PSB_SCENE_NUM_ENGINES 2
40942+
40943+struct drm_psb_dev_info_arg {
40944+ uint32_t num_use_attribute_registers;
40945+};
40946+#define DRM_PSB_DEVINFO 0x01
40947+
40948+#endif
40949Index: git/shared-core/psb_drv.h
40950===================================================================
40951--- /dev/null 1970-01-01 00:00:00.000000000 +0000
40952+++ git/shared-core/psb_drv.h 2008-12-12 17:35:22.000000000 +0000
40953@@ -0,0 +1,786 @@
40954+/**************************************************************************
40955+ * Copyright (c) 2007, Intel Corporation.
40956+ * All Rights Reserved.
40957+ *
40958+ * This program is free software; you can redistribute it and/or modify it
40959+ * under the terms and conditions of the GNU General Public License,
40960+ * version 2, as published by the Free Software Foundation.
40961+ *
40962+ * This program is distributed in the hope it will be useful, but WITHOUT
40963+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
40964+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
40965+ * more details.
40966+ *
40967+ * You should have received a copy of the GNU General Public License along with
40968+ * this program; if not, write to the Free Software Foundation, Inc.,
40969+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
40970+ *
40971+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
40972+ * develop this driver.
40973+ *
40974+ **************************************************************************/
40975+/*
40976+ */
40977+#ifndef _PSB_DRV_H_
40978+#define _PSB_DRV_H_
40979+
40980+#include "drmP.h"
40981+#include "psb_drm.h"
40982+#include "psb_reg.h"
40983+#include "psb_schedule.h"
40984+#include "intel_drv.h"
40985+
40986+enum {
40987+ CHIP_PSB_8108 = 0,
40988+ CHIP_PSB_8109 = 1
40989+};
40990+
40991+#define DRIVER_NAME "psb"
40992+#define DRIVER_DESC "drm driver for the Intel GMA500"
40993+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
40994+
40995+#define PSB_DRM_DRIVER_DATE "20080107"
40996+#define PSB_DRM_DRIVER_MAJOR 4
40997+#define PSB_DRM_DRIVER_MINOR 1
40998+#define PSB_DRM_DRIVER_PATCHLEVEL 0
40999+
41000+#define PSB_VDC_OFFSET 0x00000000
41001+#define PSB_VDC_SIZE 0x000080000
41002+#define PSB_SGX_SIZE 0x8000
41003+#define PSB_SGX_OFFSET 0x00040000
41004+#define PSB_MMIO_RESOURCE 0
41005+#define PSB_GATT_RESOURCE 2
41006+#define PSB_GTT_RESOURCE 3
41007+#define PSB_GMCH_CTRL 0x52
41008+#define PSB_BSM 0x5C
41009+#define _PSB_GMCH_ENABLED 0x4
41010+#define PSB_PGETBL_CTL 0x2020
41011+#define _PSB_PGETBL_ENABLED 0x00000001
41012+#define PSB_SGX_2D_SLAVE_PORT 0x4000
41013+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
41014+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
41015+#define PSB_NUM_VALIDATE_BUFFERS 640
41016+#define PSB_MEM_KERNEL_START 0x10000000
41017+#define PSB_MEM_PDS_START 0x20000000
41018+#define PSB_MEM_MMU_START 0x40000000
41019+
41020+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
41021+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
41022+
41023+/*
41024+ * Flags for external memory type field.
41025+ */
41026+
41027+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
41028+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
41029+
41030+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
41031+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
41032+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
41033+
41034+/*
41035+ * PTE's and PDE's
41036+ */
41037+
41038+#define PSB_PDE_MASK 0x003FFFFF
41039+#define PSB_PDE_SHIFT 22
41040+#define PSB_PTE_SHIFT 12
41041+
41042+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
41043+#define PSB_PTE_WO 0x0002 /* Write only */
41044+#define PSB_PTE_RO 0x0004 /* Read only */
41045+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
41046+
41047+/*
41048+ * VDC registers and bits
41049+ */
41050+#define PSB_HWSTAM 0x2098
41051+#define PSB_INSTPM 0x20C0
41052+#define PSB_INT_IDENTITY_R 0x20A4
41053+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
41054+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
41055+#define _PSB_IRQ_SGX_FLAG (1<<18)
41056+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
41057+#define PSB_INT_MASK_R 0x20A8
41058+#define PSB_INT_ENABLE_R 0x20A0
41059+#define PSB_PIPEASTAT 0x70024
41060+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
41061+#define _PSB_VBLANK_CLEAR (1 << 1)
41062+#define PSB_PIPEBSTAT 0x71024
41063+
41064+#define _PSB_MMU_ER_MASK 0x0001FF00
41065+#define _PSB_MMU_ER_HOST (1 << 16)
41066+#define GPIOA 0x5010
41067+#define GPIOB 0x5014
41068+#define GPIOC 0x5018
41069+#define GPIOD 0x501c
41070+#define GPIOE 0x5020
41071+#define GPIOF 0x5024
41072+#define GPIOG 0x5028
41073+#define GPIOH 0x502c
41074+#define GPIO_CLOCK_DIR_MASK (1 << 0)
41075+#define GPIO_CLOCK_DIR_IN (0 << 1)
41076+#define GPIO_CLOCK_DIR_OUT (1 << 1)
41077+#define GPIO_CLOCK_VAL_MASK (1 << 2)
41078+#define GPIO_CLOCK_VAL_OUT (1 << 3)
41079+#define GPIO_CLOCK_VAL_IN (1 << 4)
41080+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
41081+#define GPIO_DATA_DIR_MASK (1 << 8)
41082+#define GPIO_DATA_DIR_IN (0 << 9)
41083+#define GPIO_DATA_DIR_OUT (1 << 9)
41084+#define GPIO_DATA_VAL_MASK (1 << 10)
41085+#define GPIO_DATA_VAL_OUT (1 << 11)
41086+#define GPIO_DATA_VAL_IN (1 << 12)
41087+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
41088+
41089+#define VCLK_DIVISOR_VGA0 0x6000
41090+#define VCLK_DIVISOR_VGA1 0x6004
41091+#define VCLK_POST_DIV 0x6010
41092+
41093+#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
41094+#define I915_WRITE(_offs, _val) \
41095+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
41096+#define I915_READ(_offs) \
41097+ ioread32(dev_priv->vdc_reg + (_offs))
41098+
41099+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
41100+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
41101+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
41102+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
41103+#define PSB_COMM_USER_IRQ (1024 >> 2)
41104+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
41105+#define PSB_COMM_FW (2048 >> 2)
41106+
41107+#define PSB_UIRQ_VISTEST 1
41108+#define PSB_UIRQ_OOM_REPLY 2
41109+#define PSB_UIRQ_FIRE_TA_REPLY 3
41110+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
41111+
41112+#define PSB_2D_SIZE (256*1024*1024)
41113+#define PSB_MAX_RELOC_PAGES 1024
41114+
41115+#define PSB_LOW_REG_OFFS 0x0204
41116+#define PSB_HIGH_REG_OFFS 0x0600
41117+
41118+#define PSB_NUM_VBLANKS 2
41119+
41120+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
41121+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
41122+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
41123+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
41124+#define PSB_COMM_FW (2048 >> 2)
41125+
41126+#define PSB_2D_SIZE (256*1024*1024)
41127+#define PSB_MAX_RELOC_PAGES 1024
41128+
41129+#define PSB_LOW_REG_OFFS 0x0204
41130+#define PSB_HIGH_REG_OFFS 0x0600
41131+
41132+#define PSB_NUM_VBLANKS 2
41133+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
41134+
41135+/*
41136+ * User options.
41137+ */
41138+
41139+struct drm_psb_uopt {
41140+ int disable_clock_gating;
41141+};
41142+
41143+struct psb_gtt {
41144+ struct drm_device *dev;
41145+ int initialized;
41146+ uint32_t gatt_start;
41147+ uint32_t gtt_start;
41148+ uint32_t gtt_phys_start;
41149+ unsigned gtt_pages;
41150+ unsigned gatt_pages;
41151+ uint32_t stolen_base;
41152+ uint32_t pge_ctl;
41153+ u16 gmch_ctrl;
41154+ unsigned long stolen_size;
41155+ uint32_t *gtt_map;
41156+ struct rw_semaphore sem;
41157+};
41158+
41159+struct psb_use_base {
41160+ struct list_head head;
41161+ struct drm_fence_object *fence;
41162+ unsigned int reg;
41163+ unsigned long offset;
41164+ unsigned int dm;
41165+};
41166+
41167+struct psb_buflist_item {
41168+ struct drm_buffer_object *bo;
41169+ void __user *data;
41170+ struct drm_bo_info_rep rep;
41171+ int ret;
41172+};
41173+
41174+struct psb_msvdx_cmd_queue {
41175+ struct list_head head;
41176+ void *cmd;
41177+ unsigned long cmd_size;
41178+ uint32_t sequence;
41179+};
41180+
41181+struct drm_psb_private {
41182+ unsigned long chipset;
41183+
41184+ struct psb_xhw_buf resume_buf;
41185+ struct drm_psb_dev_info_arg dev_info;
41186+ struct drm_psb_uopt uopt;
41187+
41188+ struct psb_gtt *pg;
41189+
41190+ struct page *scratch_page;
41191+ struct page *comm_page;
41192+
41193+ volatile uint32_t *comm;
41194+ uint32_t comm_mmu_offset;
41195+ uint32_t mmu_2d_offset;
41196+ uint32_t sequence[PSB_NUM_ENGINES];
41197+ uint32_t last_sequence[PSB_NUM_ENGINES];
41198+ int idle[PSB_NUM_ENGINES];
41199+ uint32_t last_submitted_seq[PSB_NUM_ENGINES];
41200+ int engine_lockup_2d;
41201+
41202+ struct psb_mmu_driver *mmu;
41203+ struct psb_mmu_pd *pf_pd;
41204+
41205+ uint8_t *sgx_reg;
41206+ uint8_t *vdc_reg;
41207+ uint8_t *msvdx_reg;
41208+ /*MSVDX*/ int msvdx_needs_reset;
41209+ int has_msvdx;
41210+ uint32_t gatt_free_offset;
41211+
41212+ /*
41213+ * Fencing / irq.
41214+ */
41215+
41216+ uint32_t sgx_irq_mask;
41217+ uint32_t vdc_irq_mask;
41218+
41219+ spinlock_t irqmask_lock;
41220+ spinlock_t sequence_lock;
41221+ int fence0_irq_on;
41222+ int irq_enabled;
41223+ unsigned int irqen_count_2d;
41224+ wait_queue_head_t event_2d_queue;
41225+
41226+ uint32_t msvdx_current_sequence;
41227+ uint32_t msvdx_last_sequence;
41228+ int fence2_irq_on;
41229+ struct mutex mutex_2d;
41230+
41231+ /*
41232+ * MSVDX Rendec Memory
41233+ */
41234+ struct drm_buffer_object *ccb0;
41235+ uint32_t base_addr0;
41236+ struct drm_buffer_object *ccb1;
41237+ uint32_t base_addr1;
41238+
41239+ /*
41240+ * Memory managers
41241+ */
41242+
41243+ int have_vram;
41244+ int have_tt;
41245+ int have_mem_mmu;
41246+ int have_mem_aper;
41247+ int have_mem_kernel;
41248+ int have_mem_pds;
41249+ int have_mem_rastgeom;
41250+ struct mutex temp_mem;
41251+
41252+ /*
41253+ * Relocation buffer mapping.
41254+ */
41255+
41256+ spinlock_t reloc_lock;
41257+ unsigned int rel_mapped_pages;
41258+ wait_queue_head_t rel_mapped_queue;
41259+
41260+ /*
41261+ * SAREA
41262+ */
41263+ struct drm_psb_sarea *sarea_priv;
41264+
41265+ /*
41266+ * LVDS info
41267+ */
41268+ uint8_t blc_type;
41269+ uint8_t blc_pol;
41270+ uint8_t blc_freq;
41271+ uint8_t blc_minbrightness;
41272+ uint8_t blc_i2caddr;
41273+ uint8_t blc_brightnesscmd;
41274+ int backlight; /* restore backlight to this value */
41275+
41276+ struct intel_i2c_chan *i2c_bus;
41277+ u32 CoreClock;
41278+ u32 PWMControlRegFreq;
41279+
41280+ unsigned char * OpRegion;
41281+ unsigned int OpRegionSize;
41282+
41283+ int backlight_duty_cycle; /* restore backlight to this value */
41284+ bool panel_wants_dither;
41285+ struct drm_display_mode *panel_fixed_mode;
41286+
41287+ /*
41288+ * Register state
41289+ */
41290+ uint32_t saveDSPACNTR;
41291+ uint32_t saveDSPBCNTR;
41292+ uint32_t savePIPEACONF;
41293+ uint32_t savePIPEBCONF;
41294+ uint32_t savePIPEASRC;
41295+ uint32_t savePIPEBSRC;
41296+ uint32_t saveFPA0;
41297+ uint32_t saveFPA1;
41298+ uint32_t saveDPLL_A;
41299+ uint32_t saveDPLL_A_MD;
41300+ uint32_t saveHTOTAL_A;
41301+ uint32_t saveHBLANK_A;
41302+ uint32_t saveHSYNC_A;
41303+ uint32_t saveVTOTAL_A;
41304+ uint32_t saveVBLANK_A;
41305+ uint32_t saveVSYNC_A;
41306+ uint32_t saveDSPASTRIDE;
41307+ uint32_t saveDSPASIZE;
41308+ uint32_t saveDSPAPOS;
41309+ uint32_t saveDSPABASE;
41310+ uint32_t saveDSPASURF;
41311+ uint32_t saveFPB0;
41312+ uint32_t saveFPB1;
41313+ uint32_t saveDPLL_B;
41314+ uint32_t saveDPLL_B_MD;
41315+ uint32_t saveHTOTAL_B;
41316+ uint32_t saveHBLANK_B;
41317+ uint32_t saveHSYNC_B;
41318+ uint32_t saveVTOTAL_B;
41319+ uint32_t saveVBLANK_B;
41320+ uint32_t saveVSYNC_B;
41321+ uint32_t saveDSPBSTRIDE;
41322+ uint32_t saveDSPBSIZE;
41323+ uint32_t saveDSPBPOS;
41324+ uint32_t saveDSPBBASE;
41325+ uint32_t saveDSPBSURF;
41326+ uint32_t saveVCLK_DIVISOR_VGA0;
41327+ uint32_t saveVCLK_DIVISOR_VGA1;
41328+ uint32_t saveVCLK_POST_DIV;
41329+ uint32_t saveVGACNTRL;
41330+ uint32_t saveADPA;
41331+ uint32_t saveLVDS;
41332+ uint32_t saveDVOA;
41333+ uint32_t saveDVOB;
41334+ uint32_t saveDVOC;
41335+ uint32_t savePP_ON;
41336+ uint32_t savePP_OFF;
41337+ uint32_t savePP_CONTROL;
41338+ uint32_t savePP_CYCLE;
41339+ uint32_t savePFIT_CONTROL;
41340+ uint32_t savePaletteA[256];
41341+ uint32_t savePaletteB[256];
41342+ uint32_t saveBLC_PWM_CTL;
41343+
41344+ /*
41345+ * USE code base register management.
41346+ */
41347+
41348+ struct drm_reg_manager use_manager;
41349+
41350+ /*
41351+ * Xhw
41352+ */
41353+
41354+ uint32_t *xhw;
41355+ struct drm_buffer_object *xhw_bo;
41356+ struct drm_bo_kmap_obj xhw_kmap;
41357+ struct list_head xhw_in;
41358+ spinlock_t xhw_lock;
41359+ atomic_t xhw_client;
41360+ struct drm_file *xhw_file;
41361+ wait_queue_head_t xhw_queue;
41362+ wait_queue_head_t xhw_caller_queue;
41363+ struct mutex xhw_mutex;
41364+ struct psb_xhw_buf *xhw_cur_buf;
41365+ int xhw_submit_ok;
41366+ int xhw_on;
41367+
41368+ /*
41369+ * Scheduling.
41370+ */
41371+
41372+ struct mutex reset_mutex;
41373+ struct mutex cmdbuf_mutex;
41374+ struct psb_scheduler scheduler;
41375+ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS];
41376+ uint32_t ta_mem_pages;
41377+ struct psb_ta_mem *ta_mem;
41378+ int force_ta_mem_load;
41379+
41380+ /*
41381+ * Watchdog
41382+ */
41383+
41384+ spinlock_t watchdog_lock;
41385+ struct timer_list watchdog_timer;
41386+ struct work_struct watchdog_wq;
41387+ struct work_struct msvdx_watchdog_wq;
41388+ int timer_available;
41389+
41390+ /*
41391+ * msvdx command queue
41392+ */
41393+ spinlock_t msvdx_lock;
41394+ struct mutex msvdx_mutex;
41395+ struct list_head msvdx_queue;
41396+ int msvdx_busy;
41397+};
41398+
41399+struct psb_mmu_driver;
41400+
41401+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
41402+ int trap_pagefaults,
41403+ int invalid_type);
41404+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
41405+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
41406+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
41407+ uint32_t gtt_start, uint32_t gtt_pages);
41408+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
41409+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
41410+ int trap_pagefaults,
41411+ int invalid_type);
41412+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
41413+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
41414+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
41415+ unsigned long address,
41416+ uint32_t num_pages);
41417+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
41418+ uint32_t start_pfn,
41419+ unsigned long address,
41420+ uint32_t num_pages, int type);
41421+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
41422+ unsigned long *pfn);
41423+
41424+/*
41425+ * Enable / disable MMU for different requestors.
41426+ */
41427+
41428+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
41429+ uint32_t mask);
41430+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
41431+ uint32_t mask);
41432+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
41433+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
41434+ unsigned long address, uint32_t num_pages,
41435+ uint32_t desired_tile_stride,
41436+ uint32_t hw_tile_stride, int type);
41437+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
41438+ uint32_t num_pages,
41439+ uint32_t desired_tile_stride,
41440+ uint32_t hw_tile_stride);
41441+/*
41442+ * psb_sgx.c
41443+ */
41444+
41445+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
41446+ uint32_t sequence);
41447+extern void psb_init_2d(struct drm_psb_private *dev_priv);
41448+extern int drm_psb_idle(struct drm_device *dev);
41449+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
41450+ uint32_t src_offset,
41451+ uint32_t dst_offset, uint32_t pages,
41452+ int direction);
41453+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
41454+ struct drm_file *file_priv);
41455+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
41456+ unsigned int cmds);
41457+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
41458+ struct drm_buffer_object *cmd_buffer,
41459+ unsigned long cmd_offset,
41460+ unsigned long cmd_size, int engine,
41461+ uint32_t * copy_buffer);
41462+
41463+extern int psb_fence_for_errors(struct drm_file *priv,
41464+ struct drm_psb_cmdbuf_arg *arg,
41465+ struct drm_fence_arg *fence_arg,
41466+ struct drm_fence_object **fence_p);
41467+
41468+/*
41469+ * psb_irq.c
41470+ */
41471+
41472+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
41473+extern void psb_irq_preinstall(struct drm_device *dev);
41474+extern void psb_irq_postinstall(struct drm_device *dev);
41475+extern void psb_irq_uninstall(struct drm_device *dev);
41476+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
41477+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
41478+
41479+/*
41480+ * psb_fence.c
41481+ */
41482+
41483+extern void psb_poke_flush(struct drm_device *dev, uint32_t class);
41484+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class,
41485+ uint32_t flags, uint32_t * sequence,
41486+ uint32_t * native_type);
41487+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
41488+extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class,
41489+ uint32_t flags);
41490+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
41491+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
41492+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
41493+ uint32_t class);
41494+extern void psb_fence_error(struct drm_device *dev,
41495+ uint32_t class,
41496+ uint32_t sequence, uint32_t type, int error);
41497+
41498+/*MSVDX stuff*/
41499+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
41500+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
41501+
41502+/*
41503+ * psb_buffer.c
41504+ */
41505+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
41506+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
41507+ uint32_t * type);
41508+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
41509+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
41510+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
41511+ struct drm_mem_type_manager *man);
41512+extern int psb_move(struct drm_buffer_object *bo,
41513+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
41514+
41515+/*
41516+ * psb_gtt.c
41517+ */
41518+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
41519+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
41520+ unsigned offset_pages, unsigned num_pages,
41521+ unsigned desired_tile_stride,
41522+ unsigned hw_tile_stride, int type);
41523+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
41524+ unsigned num_pages,
41525+ unsigned desired_tile_stride,
41526+ unsigned hw_tile_stride);
41527+
41528+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
41529+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
41530+
41531+/*
41532+ * psb_fb.c
41533+ */
41534+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
41535+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
41536+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
41537+ struct drm_file *file_priv);
41538+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
41539+ struct drm_file *file_priv);
41540+
41541+/*
41542+ * psb_reset.c
41543+ */
41544+
41545+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
41546+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
41547+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
41548+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
41549+
41550+/*
41551+ * psb_regman.c
41552+ */
41553+
41554+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
41555+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
41556+ unsigned long dev_virtual,
41557+ unsigned long size,
41558+ unsigned int data_master,
41559+ uint32_t fence_class,
41560+ uint32_t fence_type,
41561+ int no_wait,
41562+ int ignore_signals,
41563+ int *r_reg, uint32_t * r_offset);
41564+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
41565+ unsigned int reg_start, unsigned int reg_num);
41566+
41567+/*
41568+ * psb_xhw.c
41569+ */
41570+
41571+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
41572+ struct drm_file *file_priv);
41573+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
41574+ struct drm_file *file_priv);
41575+extern int psb_xhw_init(struct drm_device *dev);
41576+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
41577+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
41578+ struct drm_file *file_priv, int closing);
41579+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
41580+ struct psb_xhw_buf *buf,
41581+ uint32_t fire_flags,
41582+ uint32_t hw_context,
41583+ uint32_t * cookie,
41584+ uint32_t * oom_cmds,
41585+ uint32_t num_oom_cmds,
41586+ uint32_t offset,
41587+ uint32_t engine, uint32_t flags);
41588+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
41589+ struct psb_xhw_buf *buf, uint32_t fire_flags);
41590+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
41591+ struct psb_xhw_buf *buf,
41592+ uint32_t w,
41593+ uint32_t h,
41594+ uint32_t * hw_cookie,
41595+ uint32_t * bo_size,
41596+ uint32_t * clear_p_start,
41597+ uint32_t * clear_num_pages);
41598+
41599+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
41600+ struct psb_xhw_buf *buf);
41601+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
41602+ struct psb_xhw_buf *buf,
41603+ uint32_t pages,
41604+ uint32_t * hw_cookie, uint32_t * size);
41605+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
41606+ struct psb_xhw_buf *buf, uint32_t * cookie);
41607+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
41608+ struct psb_xhw_buf *buf,
41609+ uint32_t * cookie,
41610+ uint32_t * bca,
41611+ uint32_t * rca, uint32_t * flags);
41612+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
41613+ struct psb_xhw_buf *buf);
41614+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
41615+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
41616+ struct psb_xhw_buf *buf);
41617+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
41618+ struct psb_xhw_buf *buf, uint32_t * cookie);
41619+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
41620+ struct psb_xhw_buf *buf,
41621+ uint32_t flags,
41622+ uint32_t param_offset,
41623+ uint32_t pt_offset,
41624+ uint32_t *hw_cookie);
41625+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
41626+ struct psb_xhw_buf *buf);
41627+
41628+/*
41629+ * Utilities
41630+ */
41631+
41632+#define PSB_ALIGN_TO(_val, _align) \
41633+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
41634+#define PSB_WVDC32(_val, _offs) \
41635+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
41636+#define PSB_RVDC32(_offs) \
41637+ ioread32(dev_priv->vdc_reg + (_offs))
41638+#define PSB_WSGX32(_val, _offs) \
41639+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
41640+#define PSB_RSGX32(_offs) \
41641+ ioread32(dev_priv->sgx_reg + (_offs))
41642+#define PSB_WMSVDX32(_val, _offs) \
41643+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
41644+#define PSB_RMSVDX32(_offs) \
41645+ ioread32(dev_priv->msvdx_reg + (_offs))
41646+
41647+#define PSB_ALPL(_val, _base) \
41648+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
41649+#define PSB_ALPLM(_val, _base) \
41650+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
41651+
41652+static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b)
41653+{
41654+ s64 tmp;
41655+ s64 a64 = (s64) a;
41656+ s64 b64 = (s64) b;
41657+
41658+ tmp = a64 * b64;
41659+ return tmp / (1ULL << PSB_FIXED_SHIFT) +
41660+ ((tmp & 0x80000000ULL) ? 1 : 0);
41661+}
41662+
41663+static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b)
41664+{
41665+ u64 tmp;
41666+ u64 a64 = (u64) a;
41667+ u64 b64 = (u64) b;
41668+
41669+ tmp = a64 * b64;
41670+ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0);
41671+}
41672+
41673+static inline uint32_t psb_ufixed_to_float32(psb_ufixed a)
41674+{
41675+ uint32_t exp = 0x7f + 7;
41676+ uint32_t mantissa = (uint32_t) a;
41677+
41678+ if (a == 0)
41679+ return 0;
41680+ while ((mantissa & 0xff800000) == 0) {
41681+ exp -= 1;
41682+ mantissa <<= 1;
41683+ }
41684+ while ((mantissa & 0xff800000) > 0x00800000) {
41685+ exp += 1;
41686+ mantissa >>= 1;
41687+ }
41688+ return (mantissa & ~0xff800000) | (exp << 23);
41689+}
41690+
41691+static inline uint32_t psb_fixed_to_float32(psb_fixed a)
41692+{
41693+ if (a < 0)
41694+ return psb_ufixed_to_float32(-a) | 0x80000000;
41695+ else
41696+ return psb_ufixed_to_float32(a);
41697+}
41698+
41699+#define PSB_D_RENDER (1 << 16)
41700+
41701+#define PSB_D_GENERAL (1 << 0)
41702+#define PSB_D_INIT (1 << 1)
41703+#define PSB_D_IRQ (1 << 2)
41704+#define PSB_D_FW (1 << 3)
41705+#define PSB_D_PERF (1 << 4)
41706+#define PSB_D_TMP (1 << 5)
41707+
41708+extern int drm_psb_debug;
41709+extern int drm_psb_no_fb;
41710+extern int drm_psb_disable_vsync;
41711+
41712+#define PSB_DEBUG_FW(_fmt, _arg...) \
41713+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
41714+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
41715+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
41716+#define PSB_DEBUG_INIT(_fmt, _arg...) \
41717+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
41718+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
41719+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
41720+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
41721+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
41722+#define PSB_DEBUG_PERF(_fmt, _arg...) \
41723+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
41724+#define PSB_DEBUG_TMP(_fmt, _arg...) \
41725+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
41726+
41727+#if DRM_DEBUG_CODE
41728+#define PSB_DEBUG(_flag, _fmt, _arg...) \
41729+ do { \
41730+ if ((_flag) & drm_psb_debug) \
41731+ printk(KERN_DEBUG \
41732+ "[psb:0x%02x:%s] " _fmt , _flag, \
41733+ __FUNCTION__ , ##_arg); \
41734+ } while (0)
41735+#else
41736+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
41737+#endif
41738+
41739+#endif
41740Index: git/shared-core/psb_reg.h
41741===================================================================
41742--- /dev/null 1970-01-01 00:00:00.000000000 +0000
41743+++ git/shared-core/psb_reg.h 2008-12-12 17:35:22.000000000 +0000
41744@@ -0,0 +1,555 @@
41745+/**************************************************************************
41746+ *
41747+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
41748+ * Copyright (c) 2007, Intel Corporation.
41749+ * All Rights Reserved.
41750+ *
41751+ * This program is free software; you can redistribute it and/or modify it
41752+ * under the terms and conditions of the GNU General Public License,
41753+ * version 2, as published by the Free Software Foundation.
41754+ *
41755+ * This program is distributed in the hope it will be useful, but WITHOUT
41756+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
41757+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
41758+ * more details.
41759+ *
41760+ * You should have received a copy of the GNU General Public License along with
41761+ * this program; if not, write to the Free Software Foundation, Inc.,
41762+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
41763+ *
41764+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
41765+ * develop this driver.
41766+ *
41767+ **************************************************************************/
41768+/*
41769+ */
41770+#ifndef _PSB_REG_H_
41771+#define _PSB_REG_H_
41772+
41773+#define PSB_CR_CLKGATECTL 0x0000
41774+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
41775+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
41776+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
41777+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
41778+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
41779+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
41780+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
41781+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
41782+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
41783+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
41784+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
41785+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
41786+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
41787+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
41788+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
41789+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
41790+
41791+#define PSB_CR_CORE_ID 0x0010
41792+#define _PSB_CC_ID_ID_SHIFT (16)
41793+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
41794+#define _PSB_CC_ID_CONFIG_SHIFT (0)
41795+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
41796+
41797+#define PSB_CR_CORE_REVISION 0x0014
41798+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
41799+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
41800+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
41801+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
41802+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
41803+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
41804+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
41805+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
41806+
41807+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
41808+
41809+#define PSB_CR_SOFT_RESET 0x0080
41810+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
41811+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
41812+#define _PSB_CS_RESET_USE_RESET (1 << 4)
41813+#define _PSB_CS_RESET_TA_RESET (1 << 3)
41814+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
41815+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
41816+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
41817+
41818+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
41819+
41820+#define PSB_CR_EVENT_STATUS 0x012C
41821+
41822+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
41823+
41824+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
41825+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
41826+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
41827+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
41828+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
41829+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
41830+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
41831+#define _PSB_CE_SW_EVENT (1 << 14)
41832+#define _PSB_CE_TA_FINISHED (1 << 13)
41833+#define _PSB_CE_TA_TERMINATE (1 << 12)
41834+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
41835+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
41836+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
41837+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
41838+
41839+
41840+#define PSB_USE_OFFSET_MASK 0x0007FFFF
41841+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
41842+#define PSB_CR_USE_CODE_BASE0 0x0A0C
41843+#define PSB_CR_USE_CODE_BASE1 0x0A10
41844+#define PSB_CR_USE_CODE_BASE2 0x0A14
41845+#define PSB_CR_USE_CODE_BASE3 0x0A18
41846+#define PSB_CR_USE_CODE_BASE4 0x0A1C
41847+#define PSB_CR_USE_CODE_BASE5 0x0A20
41848+#define PSB_CR_USE_CODE_BASE6 0x0A24
41849+#define PSB_CR_USE_CODE_BASE7 0x0A28
41850+#define PSB_CR_USE_CODE_BASE8 0x0A2C
41851+#define PSB_CR_USE_CODE_BASE9 0x0A30
41852+#define PSB_CR_USE_CODE_BASE10 0x0A34
41853+#define PSB_CR_USE_CODE_BASE11 0x0A38
41854+#define PSB_CR_USE_CODE_BASE12 0x0A3C
41855+#define PSB_CR_USE_CODE_BASE13 0x0A40
41856+#define PSB_CR_USE_CODE_BASE14 0x0A44
41857+#define PSB_CR_USE_CODE_BASE15 0x0A48
41858+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
41859+#define _PSB_CUC_BASE_DM_SHIFT (25)
41860+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
41861+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
41862+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
41863+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
41864+#define _PSB_CUC_DM_VERTEX (0)
41865+#define _PSB_CUC_DM_PIXEL (1)
41866+#define _PSB_CUC_DM_RESERVED (2)
41867+#define _PSB_CUC_DM_EDM (3)
41868+
41869+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
41870+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
41871+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
41872+
41873+#define PSB_CR_EVENT_KICKER 0x0AC4
41874+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
41875+
41876+#define PSB_CR_EVENT_KICK 0x0AC8
41877+#define _PSB_CE_KICK_NOW (1 << 0)
41878+
41879+
41880+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
41881+
41882+#define PSB_CR_BIF_CTRL 0x0C00
41883+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
41884+#define _PSB_CB_CTRL_INVALDC (1 << 3)
41885+#define _PSB_CB_CTRL_FLUSH (1 << 2)
41886+
41887+#define PSB_CR_BIF_INT_STAT 0x0C04
41888+
41889+#define PSB_CR_BIF_FAULT 0x0C08
41890+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
41891+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
41892+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
41893+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
41894+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
41895+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
41896+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
41897+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
41898+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
41899+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
41900+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
41901+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
41902+
41903+#define PSB_CR_BIF_BANK0 0x0C78
41904+
41905+#define PSB_CR_BIF_BANK1 0x0C7C
41906+
41907+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
41908+
41909+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
41910+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
41911+
41912+#define PSB_CR_2D_SOCIF 0x0E18
41913+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
41914+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
41915+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
41916+
41917+#define PSB_CR_2D_BLIT_STATUS 0x0E04
41918+#define _PSB_C2B_STATUS_BUSY (1 << 24)
41919+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
41920+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
41921+
41922+/*
41923+ * 2D defs.
41924+ */
41925+
41926+/*
41927+ * 2D Slave Port Data : Block Header's Object Type
41928+ */
41929+
41930+#define PSB_2D_CLIP_BH (0x00000000)
41931+#define PSB_2D_PAT_BH (0x10000000)
41932+#define PSB_2D_CTRL_BH (0x20000000)
41933+#define PSB_2D_SRC_OFF_BH (0x30000000)
41934+#define PSB_2D_MASK_OFF_BH (0x40000000)
41935+#define PSB_2D_RESERVED1_BH (0x50000000)
41936+#define PSB_2D_RESERVED2_BH (0x60000000)
41937+#define PSB_2D_FENCE_BH (0x70000000)
41938+#define PSB_2D_BLIT_BH (0x80000000)
41939+#define PSB_2D_SRC_SURF_BH (0x90000000)
41940+#define PSB_2D_DST_SURF_BH (0xA0000000)
41941+#define PSB_2D_PAT_SURF_BH (0xB0000000)
41942+#define PSB_2D_SRC_PAL_BH (0xC0000000)
41943+#define PSB_2D_PAT_PAL_BH (0xD0000000)
41944+#define PSB_2D_MASK_SURF_BH (0xE0000000)
41945+#define PSB_2D_FLUSH_BH (0xF0000000)
41946+
41947+/*
41948+ * Clip Definition block (PSB_2D_CLIP_BH)
41949+ */
41950+#define PSB_2D_CLIPCOUNT_MAX (1)
41951+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
41952+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
41953+#define PSB_2D_CLIPCOUNT_SHIFT (0)
41954+// clip rectangle min & max
41955+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
41956+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
41957+#define PSB_2D_CLIP_XMAX_SHIFT (12)
41958+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
41959+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
41960+#define PSB_2D_CLIP_XMIN_SHIFT (0)
41961+// clip rectangle offset
41962+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
41963+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
41964+#define PSB_2D_CLIP_YMAX_SHIFT (12)
41965+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
41966+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
41967+#define PSB_2D_CLIP_YMIN_SHIFT (0)
41968+
41969+/*
41970+ * Pattern Control (PSB_2D_PAT_BH)
41971+ */
41972+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
41973+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
41974+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
41975+#define PSB_2D_PAT_WIDTH_SHIFT (5)
41976+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
41977+#define PSB_2D_PAT_YSTART_SHIFT (10)
41978+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
41979+#define PSB_2D_PAT_XSTART_SHIFT (15)
41980+
41981+/*
41982+ * 2D Control block (PSB_2D_CTRL_BH)
41983+ */
41984+// Present Flags
41985+#define PSB_2D_SRCCK_CTRL (0x00000001)
41986+#define PSB_2D_DSTCK_CTRL (0x00000002)
41987+#define PSB_2D_ALPHA_CTRL (0x00000004)
41988+// Colour Key Colour (SRC/DST)
41989+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
41990+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
41991+#define PSB_2D_CK_COL_SHIFT (0)
41992+// Colour Key Mask (SRC/DST)
41993+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
41994+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
41995+#define PSB_2D_CK_MASK_SHIFT (0)
41996+// Alpha Control (Alpha/RGB)
41997+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
41998+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
41999+#define PSB_2D_GBLALPHA_SHIFT (12)
42000+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
42001+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
42002+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
42003+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
42004+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
42005+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
42006+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
42007+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
42008+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
42009+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
42010+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
42011+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
42012+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
42013+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
42014+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
42015+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
42016+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
42017+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
42018+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
42019+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
42020+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
42021+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
42022+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
42023+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
42024+
42025+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
42026+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
42027+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
42028+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
42029+
42030+/*
42031+ *Source Offset (PSB_2D_SRC_OFF_BH)
42032+ */
42033+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
42034+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
42035+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
42036+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
42037+
42038+/*
42039+ * Mask Offset (PSB_2D_MASK_OFF_BH)
42040+ */
42041+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
42042+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
42043+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
42044+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
42045+
42046+/*
42047+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
42048+ */
42049+
42050+/*
42051+ *Blit Rectangle (PSB_2D_BLIT_BH)
42052+ */
42053+
42054+#define PSB_2D_ROT_MASK (3<<25)
42055+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
42056+#define PSB_2D_ROT_NONE (0<<25)
42057+#define PSB_2D_ROT_90DEGS (1<<25)
42058+#define PSB_2D_ROT_180DEGS (2<<25)
42059+#define PSB_2D_ROT_270DEGS (3<<25)
42060+
42061+#define PSB_2D_COPYORDER_MASK (3<<23)
42062+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
42063+#define PSB_2D_COPYORDER_TL2BR (0<<23)
42064+#define PSB_2D_COPYORDER_BR2TL (1<<23)
42065+#define PSB_2D_COPYORDER_TR2BL (2<<23)
42066+#define PSB_2D_COPYORDER_BL2TR (3<<23)
42067+
42068+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
42069+#define PSB_2D_DSTCK_DISABLE (0x00000000)
42070+#define PSB_2D_DSTCK_PASS (0x00200000)
42071+#define PSB_2D_DSTCK_REJECT (0x00400000)
42072+
42073+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
42074+#define PSB_2D_SRCCK_DISABLE (0x00000000)
42075+#define PSB_2D_SRCCK_PASS (0x00080000)
42076+#define PSB_2D_SRCCK_REJECT (0x00100000)
42077+
42078+#define PSB_2D_CLIP_ENABLE (0x00040000)
42079+
42080+#define PSB_2D_ALPHA_ENABLE (0x00020000)
42081+
42082+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
42083+#define PSB_2D_PAT_MASK (0x00010000)
42084+#define PSB_2D_USE_PAT (0x00010000)
42085+#define PSB_2D_USE_FILL (0x00000000)
42086+/*
42087+ * Tungsten Graphics note on rop codes: If rop A and rop B are
42088+ * identical, the mask surface will not be read and need not be
42089+ * set up.
42090+ */
42091+
42092+#define PSB_2D_ROP3B_MASK (0x0000FF00)
42093+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
42094+#define PSB_2D_ROP3B_SHIFT (8)
42095+// rop code A
42096+#define PSB_2D_ROP3A_MASK (0x000000FF)
42097+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
42098+#define PSB_2D_ROP3A_SHIFT (0)
42099+
42100+#define PSB_2D_ROP4_MASK (0x0000FFFF)
42101+/*
42102+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
42103+ * Fill Colour RGBA8888
42104+ */
42105+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
42106+#define PSB_2D_FILLCOLOUR_SHIFT (0)
42107+/*
42108+ * DWORD1: (Always Present)
42109+ * X Start (Dest)
42110+ * Y Start (Dest)
42111+ */
42112+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
42113+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
42114+#define PSB_2D_DST_XSTART_SHIFT (12)
42115+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
42116+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
42117+#define PSB_2D_DST_YSTART_SHIFT (0)
42118+/*
42119+ * DWORD2: (Always Present)
42120+ * X Size (Dest)
42121+ * Y Size (Dest)
42122+ */
42123+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
42124+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
42125+#define PSB_2D_DST_XSIZE_SHIFT (12)
42126+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
42127+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
42128+#define PSB_2D_DST_YSIZE_SHIFT (0)
42129+
42130+/*
42131+ * Source Surface (PSB_2D_SRC_SURF_BH)
42132+ */
42133+/*
42134+ * WORD 0
42135+ */
42136+
42137+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
42138+#define PSB_2D_SRC_1_PAL (0x00000000)
42139+#define PSB_2D_SRC_2_PAL (0x00008000)
42140+#define PSB_2D_SRC_4_PAL (0x00010000)
42141+#define PSB_2D_SRC_8_PAL (0x00018000)
42142+#define PSB_2D_SRC_8_ALPHA (0x00020000)
42143+#define PSB_2D_SRC_4_ALPHA (0x00028000)
42144+#define PSB_2D_SRC_332RGB (0x00030000)
42145+#define PSB_2D_SRC_4444ARGB (0x00038000)
42146+#define PSB_2D_SRC_555RGB (0x00040000)
42147+#define PSB_2D_SRC_1555ARGB (0x00048000)
42148+#define PSB_2D_SRC_565RGB (0x00050000)
42149+#define PSB_2D_SRC_0888ARGB (0x00058000)
42150+#define PSB_2D_SRC_8888ARGB (0x00060000)
42151+#define PSB_2D_SRC_8888UYVY (0x00068000)
42152+#define PSB_2D_SRC_RESERVED (0x00070000)
42153+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
42154+
42155+
42156+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
42157+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
42158+#define PSB_2D_SRC_STRIDE_SHIFT (0)
42159+/*
42160+ * WORD 1 - Base Address
42161+ */
42162+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
42163+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
42164+#define PSB_2D_SRC_ADDR_SHIFT (2)
42165+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
42166+
42167+/*
42168+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
42169+ */
42170+/*
42171+ * WORD 0
42172+ */
42173+
42174+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
42175+#define PSB_2D_PAT_1_PAL (0x00000000)
42176+#define PSB_2D_PAT_2_PAL (0x00008000)
42177+#define PSB_2D_PAT_4_PAL (0x00010000)
42178+#define PSB_2D_PAT_8_PAL (0x00018000)
42179+#define PSB_2D_PAT_8_ALPHA (0x00020000)
42180+#define PSB_2D_PAT_4_ALPHA (0x00028000)
42181+#define PSB_2D_PAT_332RGB (0x00030000)
42182+#define PSB_2D_PAT_4444ARGB (0x00038000)
42183+#define PSB_2D_PAT_555RGB (0x00040000)
42184+#define PSB_2D_PAT_1555ARGB (0x00048000)
42185+#define PSB_2D_PAT_565RGB (0x00050000)
42186+#define PSB_2D_PAT_0888ARGB (0x00058000)
42187+#define PSB_2D_PAT_8888ARGB (0x00060000)
42188+
42189+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
42190+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
42191+#define PSB_2D_PAT_STRIDE_SHIFT (0)
42192+/*
42193+ * WORD 1 - Base Address
42194+ */
42195+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
42196+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
42197+#define PSB_2D_PAT_ADDR_SHIFT (2)
42198+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
42199+
42200+/*
42201+ * Destination Surface (PSB_2D_DST_SURF_BH)
42202+ */
42203+/*
42204+ * WORD 0
42205+ */
42206+
42207+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
42208+#define PSB_2D_DST_332RGB (0x00030000)
42209+#define PSB_2D_DST_4444ARGB (0x00038000)
42210+#define PSB_2D_DST_555RGB (0x00040000)
42211+#define PSB_2D_DST_1555ARGB (0x00048000)
42212+#define PSB_2D_DST_565RGB (0x00050000)
42213+#define PSB_2D_DST_0888ARGB (0x00058000)
42214+#define PSB_2D_DST_8888ARGB (0x00060000)
42215+#define PSB_2D_DST_8888AYUV (0x00070000)
42216+
42217+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
42218+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
42219+#define PSB_2D_DST_STRIDE_SHIFT (0)
42220+/*
42221+ * WORD 1 - Base Address
42222+ */
42223+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
42224+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
42225+#define PSB_2D_DST_ADDR_SHIFT (2)
42226+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
42227+
42228+/*
42229+ * Mask Surface (PSB_2D_MASK_SURF_BH)
42230+ */
42231+/*
42232+ * WORD 0
42233+ */
42234+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
42235+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
42236+#define PSB_2D_MASK_STRIDE_SHIFT (0)
42237+/*
42238+ * WORD 1 - Base Address
42239+ */
42240+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
42241+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
42242+#define PSB_2D_MASK_ADDR_SHIFT (2)
42243+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
42244+
42245+/*
42246+ * Source Palette (PSB_2D_SRC_PAL_BH)
42247+ */
42248+
42249+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
42250+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
42251+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
42252+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
42253+
42254+/*
42255+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
42256+ */
42257+
42258+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
42259+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
42260+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
42261+#define PSB_2D_PATPAL_BYTEALIGN (1024)
42262+
42263+/*
42264+ * Rop3 Codes (2 LS bytes)
42265+ */
42266+
42267+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
42268+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
42269+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
42270+#define PSB_2D_ROP3_BLACKNESS (0x0000)
42271+#define PSB_2D_ROP3_SRC (0xCC)
42272+#define PSB_2D_ROP3_PAT (0xF0)
42273+#define PSB_2D_ROP3_DST (0xAA)
42274+
42275+
42276+/*
42277+ * Sizes.
42278+ */
42279+
42280+#define PSB_SCENE_HW_COOKIE_SIZE 16
42281+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
42282+
42283+/*
42284+ * Scene stuff.
42285+ */
42286+
42287+#define PSB_NUM_HW_SCENES 2
42288+
42289+/*
42290+ * Scheduler completion actions.
42291+ */
42292+
42293+#define PSB_RASTER_BLOCK 0
42294+#define PSB_RASTER 1
42295+#define PSB_RETURN 2
42296+#define PSB_TA 3
42297+
42298+
42299+#endif
42300Index: git/shared-core/r128_cce.c
42301===================================================================
42302--- /dev/null 1970-01-01 00:00:00.000000000 +0000
42303+++ git/shared-core/r128_cce.c 2008-12-12 17:35:22.000000000 +0000
42304@@ -0,0 +1,932 @@
42305+/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
42306+ * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
42307+ */
42308+/*
42309+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
42310+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
42311+ * All Rights Reserved.
42312+ *
42313+ * Permission is hereby granted, free of charge, to any person obtaining a
42314+ * copy of this software and associated documentation files (the "Software"),
42315+ * to deal in the Software without restriction, including without limitation
42316+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
42317+ * and/or sell copies of the Software, and to permit persons to whom the
42318+ * Software is furnished to do so, subject to the following conditions:
42319+ *
42320+ * The above copyright notice and this permission notice (including the next
42321+ * paragraph) shall be included in all copies or substantial portions of the
42322+ * Software.
42323+ *
42324+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42325+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42326+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42327+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
42328+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
42329+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42330+ * DEALINGS IN THE SOFTWARE.
42331+ *
42332+ * Authors:
42333+ * Gareth Hughes <gareth@valinux.com>
42334+ */
42335+
42336+#include "drmP.h"
42337+#include "drm.h"
42338+#include "r128_drm.h"
42339+#include "r128_drv.h"
42340+
42341+#define R128_FIFO_DEBUG 0
42342+
42343+/* CCE microcode (from ATI) */
42344+static u32 r128_cce_microcode[] = {
42345+ 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
42346+ 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
42347+ 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
42348+ 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
42349+ 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
42350+ 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
42351+ 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
42352+ 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
42353+ 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
42354+ 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
42355+ 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
42356+ 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
42357+ 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
42358+ 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
42359+ 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
42360+ 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
42361+ 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
42362+ 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
42363+ 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
42364+ 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
42365+ 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
42366+ 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
42367+ 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
42368+ 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
42369+ 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
42370+ 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
42371+ 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
42372+ 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
42373+ 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
42374+ 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
42375+ 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
42376+ 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
42377+ 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
42378+ 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
42379+ 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42380+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42381+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42382+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42383+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42384+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42385+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
42386+};
42387+
42388+static int R128_READ_PLL(struct drm_device * dev, int addr)
42389+{
42390+ drm_r128_private_t *dev_priv = dev->dev_private;
42391+
42392+ R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
42393+ return R128_READ(R128_CLOCK_CNTL_DATA);
42394+}
42395+
42396+#if R128_FIFO_DEBUG
42397+static void r128_status(drm_r128_private_t * dev_priv)
42398+{
42399+ printk("GUI_STAT = 0x%08x\n",
42400+ (unsigned int)R128_READ(R128_GUI_STAT));
42401+ printk("PM4_STAT = 0x%08x\n",
42402+ (unsigned int)R128_READ(R128_PM4_STAT));
42403+ printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
42404+ (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
42405+ printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
42406+ (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
42407+ printk("PM4_MICRO_CNTL = 0x%08x\n",
42408+ (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
42409+ printk("PM4_BUFFER_CNTL = 0x%08x\n",
42410+ (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
42411+}
42412+#endif
42413+
42414+/* ================================================================
42415+ * Engine, FIFO control
42416+ */
42417+
42418+static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
42419+{
42420+ u32 tmp;
42421+ int i;
42422+
42423+ tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
42424+ R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
42425+
42426+ for (i = 0; i < dev_priv->usec_timeout; i++) {
42427+ if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
42428+ return 0;
42429+ }
42430+ DRM_UDELAY(1);
42431+ }
42432+
42433+#if R128_FIFO_DEBUG
42434+ DRM_ERROR("failed!\n");
42435+#endif
42436+ return -EBUSY;
42437+}
42438+
42439+static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
42440+{
42441+ int i;
42442+
42443+ for (i = 0; i < dev_priv->usec_timeout; i++) {
42444+ int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
42445+ if (slots >= entries)
42446+ return 0;
42447+ DRM_UDELAY(1);
42448+ }
42449+
42450+#if R128_FIFO_DEBUG
42451+ DRM_ERROR("failed!\n");
42452+#endif
42453+ return -EBUSY;
42454+}
42455+
42456+static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
42457+{
42458+ int i, ret;
42459+
42460+ ret = r128_do_wait_for_fifo(dev_priv, 64);
42461+ if (ret)
42462+ return ret;
42463+
42464+ for (i = 0; i < dev_priv->usec_timeout; i++) {
42465+ if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
42466+ r128_do_pixcache_flush(dev_priv);
42467+ return 0;
42468+ }
42469+ DRM_UDELAY(1);
42470+ }
42471+
42472+#if R128_FIFO_DEBUG
42473+ DRM_ERROR("failed!\n");
42474+#endif
42475+ return -EBUSY;
42476+}
42477+
42478+/* ================================================================
42479+ * CCE control, initialization
42480+ */
42481+
42482+/* Load the microcode for the CCE */
42483+static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
42484+{
42485+ int i;
42486+
42487+ DRM_DEBUG("\n");
42488+
42489+ r128_do_wait_for_idle(dev_priv);
42490+
42491+ R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
42492+ for (i = 0; i < 256; i++) {
42493+ R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
42494+ R128_WRITE(R128_PM4_MICROCODE_DATAL,
42495+ r128_cce_microcode[i * 2 + 1]);
42496+ }
42497+}
42498+
42499+/* Flush any pending commands to the CCE. This should only be used just
42500+ * prior to a wait for idle, as it informs the engine that the command
42501+ * stream is ending.
42502+ */
42503+static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
42504+{
42505+ u32 tmp;
42506+
42507+ tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
42508+ R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
42509+}
42510+
42511+/* Wait for the CCE to go idle.
42512+ */
42513+int r128_do_cce_idle(drm_r128_private_t * dev_priv)
42514+{
42515+ int i;
42516+
42517+ for (i = 0; i < dev_priv->usec_timeout; i++) {
42518+ if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
42519+ int pm4stat = R128_READ(R128_PM4_STAT);
42520+ if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
42521+ dev_priv->cce_fifo_size) &&
42522+ !(pm4stat & (R128_PM4_BUSY |
42523+ R128_PM4_GUI_ACTIVE))) {
42524+ return r128_do_pixcache_flush(dev_priv);
42525+ }
42526+ }
42527+ DRM_UDELAY(1);
42528+ }
42529+
42530+#if R128_FIFO_DEBUG
42531+ DRM_ERROR("failed!\n");
42532+ r128_status(dev_priv);
42533+#endif
42534+ return -EBUSY;
42535+}
42536+
42537+/* Start the Concurrent Command Engine.
42538+ */
42539+static void r128_do_cce_start(drm_r128_private_t * dev_priv)
42540+{
42541+ r128_do_wait_for_idle(dev_priv);
42542+
42543+ R128_WRITE(R128_PM4_BUFFER_CNTL,
42544+ dev_priv->cce_mode | dev_priv->ring.size_l2qw
42545+ | R128_PM4_BUFFER_CNTL_NOUPDATE);
42546+ R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
42547+ R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
42548+
42549+ dev_priv->cce_running = 1;
42550+}
42551+
42552+/* Reset the Concurrent Command Engine. This will not flush any pending
42553+ * commands, so you must wait for the CCE command stream to complete
42554+ * before calling this routine.
42555+ */
42556+static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
42557+{
42558+ R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
42559+ R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
42560+ dev_priv->ring.tail = 0;
42561+}
42562+
42563+/* Stop the Concurrent Command Engine. This will not flush any pending
42564+ * commands, so you must flush the command stream and wait for the CCE
42565+ * to go idle before calling this routine.
42566+ */
42567+static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
42568+{
42569+ R128_WRITE(R128_PM4_MICRO_CNTL, 0);
42570+ R128_WRITE(R128_PM4_BUFFER_CNTL,
42571+ R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
42572+
42573+ dev_priv->cce_running = 0;
42574+}
42575+
42576+/* Reset the engine. This will stop the CCE if it is running.
42577+ */
42578+static int r128_do_engine_reset(struct drm_device * dev)
42579+{
42580+ drm_r128_private_t *dev_priv = dev->dev_private;
42581+ u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
42582+
42583+ r128_do_pixcache_flush(dev_priv);
42584+
42585+ clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
42586+ mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
42587+
42588+ R128_WRITE_PLL(R128_MCLK_CNTL,
42589+ mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
42590+
42591+ gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
42592+
42593+ /* Taken from the sample code - do not change */
42594+ R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
42595+ R128_READ(R128_GEN_RESET_CNTL);
42596+ R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
42597+ R128_READ(R128_GEN_RESET_CNTL);
42598+
42599+ R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
42600+ R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
42601+ R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
42602+
42603+ /* Reset the CCE ring */
42604+ r128_do_cce_reset(dev_priv);
42605+
42606+ /* The CCE is no longer running after an engine reset */
42607+ dev_priv->cce_running = 0;
42608+
42609+ /* Reset any pending vertex, indirect buffers */
42610+ r128_freelist_reset(dev);
42611+
42612+ return 0;
42613+}
42614+
42615+static void r128_cce_init_ring_buffer(struct drm_device * dev,
42616+ drm_r128_private_t * dev_priv)
42617+{
42618+ u32 ring_start;
42619+ u32 tmp;
42620+
42621+ DRM_DEBUG("\n");
42622+
42623+ /* The manual (p. 2) says this address is in "VM space". This
42624+ * means it's an offset from the start of AGP space.
42625+ */
42626+#if __OS_HAS_AGP
42627+ if (!dev_priv->is_pci)
42628+ ring_start = dev_priv->cce_ring->offset - dev->agp->base;
42629+ else
42630+#endif
42631+ ring_start = dev_priv->cce_ring->offset -
42632+ (unsigned long)dev->sg->virtual;
42633+
42634+ R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
42635+
42636+ R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
42637+ R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
42638+
42639+ /* Set watermark control */
42640+ R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
42641+ ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
42642+ | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
42643+ | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
42644+ | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
42645+
42646+ /* Force read. Why? Because it's in the examples... */
42647+ R128_READ(R128_PM4_BUFFER_ADDR);
42648+
42649+ /* Turn on bus mastering */
42650+ tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
42651+ R128_WRITE(R128_BUS_CNTL, tmp);
42652+}
42653+
42654+static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
42655+{
42656+ drm_r128_private_t *dev_priv;
42657+
42658+ DRM_DEBUG("\n");
42659+
42660+ dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
42661+ if (dev_priv == NULL)
42662+ return -ENOMEM;
42663+
42664+ memset(dev_priv, 0, sizeof(drm_r128_private_t));
42665+
42666+ dev_priv->is_pci = init->is_pci;
42667+
42668+ if (dev_priv->is_pci && !dev->sg) {
42669+ DRM_ERROR("PCI GART memory not allocated!\n");
42670+ dev->dev_private = (void *)dev_priv;
42671+ r128_do_cleanup_cce(dev);
42672+ return -EINVAL;
42673+ }
42674+
42675+ dev_priv->usec_timeout = init->usec_timeout;
42676+ if (dev_priv->usec_timeout < 1 ||
42677+ dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
42678+ DRM_DEBUG("TIMEOUT problem!\n");
42679+ dev->dev_private = (void *)dev_priv;
42680+ r128_do_cleanup_cce(dev);
42681+ return -EINVAL;
42682+ }
42683+
42684+ dev_priv->cce_mode = init->cce_mode;
42685+
42686+ /* GH: Simple idle check.
42687+ */
42688+ atomic_set(&dev_priv->idle_count, 0);
42689+
42690+ /* We don't support anything other than bus-mastering ring mode,
42691+ * but the ring can be in either AGP or PCI space for the ring
42692+ * read pointer.
42693+ */
42694+ if ((init->cce_mode != R128_PM4_192BM) &&
42695+ (init->cce_mode != R128_PM4_128BM_64INDBM) &&
42696+ (init->cce_mode != R128_PM4_64BM_128INDBM) &&
42697+ (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
42698+ DRM_DEBUG("Bad cce_mode!\n");
42699+ dev->dev_private = (void *)dev_priv;
42700+ r128_do_cleanup_cce(dev);
42701+ return -EINVAL;
42702+ }
42703+
42704+ switch (init->cce_mode) {
42705+ case R128_PM4_NONPM4:
42706+ dev_priv->cce_fifo_size = 0;
42707+ break;
42708+ case R128_PM4_192PIO:
42709+ case R128_PM4_192BM:
42710+ dev_priv->cce_fifo_size = 192;
42711+ break;
42712+ case R128_PM4_128PIO_64INDBM:
42713+ case R128_PM4_128BM_64INDBM:
42714+ dev_priv->cce_fifo_size = 128;
42715+ break;
42716+ case R128_PM4_64PIO_128INDBM:
42717+ case R128_PM4_64BM_128INDBM:
42718+ case R128_PM4_64PIO_64VCBM_64INDBM:
42719+ case R128_PM4_64BM_64VCBM_64INDBM:
42720+ case R128_PM4_64PIO_64VCPIO_64INDPIO:
42721+ dev_priv->cce_fifo_size = 64;
42722+ break;
42723+ }
42724+
42725+ switch (init->fb_bpp) {
42726+ case 16:
42727+ dev_priv->color_fmt = R128_DATATYPE_RGB565;
42728+ break;
42729+ case 32:
42730+ default:
42731+ dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
42732+ break;
42733+ }
42734+ dev_priv->front_offset = init->front_offset;
42735+ dev_priv->front_pitch = init->front_pitch;
42736+ dev_priv->back_offset = init->back_offset;
42737+ dev_priv->back_pitch = init->back_pitch;
42738+
42739+ switch (init->depth_bpp) {
42740+ case 16:
42741+ dev_priv->depth_fmt = R128_DATATYPE_RGB565;
42742+ break;
42743+ case 24:
42744+ case 32:
42745+ default:
42746+ dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
42747+ break;
42748+ }
42749+ dev_priv->depth_offset = init->depth_offset;
42750+ dev_priv->depth_pitch = init->depth_pitch;
42751+ dev_priv->span_offset = init->span_offset;
42752+
42753+ dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
42754+ (dev_priv->front_offset >> 5));
42755+ dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
42756+ (dev_priv->back_offset >> 5));
42757+ dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
42758+ (dev_priv->depth_offset >> 5) |
42759+ R128_DST_TILE);
42760+ dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
42761+ (dev_priv->span_offset >> 5));
42762+
42763+ dev_priv->sarea = drm_getsarea(dev);
42764+ if (!dev_priv->sarea) {
42765+ DRM_ERROR("could not find sarea!\n");
42766+ dev->dev_private = (void *)dev_priv;
42767+ r128_do_cleanup_cce(dev);
42768+ return -EINVAL;
42769+ }
42770+
42771+ dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
42772+ if (!dev_priv->mmio) {
42773+ DRM_ERROR("could not find mmio region!\n");
42774+ dev->dev_private = (void *)dev_priv;
42775+ r128_do_cleanup_cce(dev);
42776+ return -EINVAL;
42777+ }
42778+ dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
42779+ if (!dev_priv->cce_ring) {
42780+ DRM_ERROR("could not find cce ring region!\n");
42781+ dev->dev_private = (void *)dev_priv;
42782+ r128_do_cleanup_cce(dev);
42783+ return -EINVAL;
42784+ }
42785+ dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
42786+ if (!dev_priv->ring_rptr) {
42787+ DRM_ERROR("could not find ring read pointer!\n");
42788+ dev->dev_private = (void *)dev_priv;
42789+ r128_do_cleanup_cce(dev);
42790+ return -EINVAL;
42791+ }
42792+ dev->agp_buffer_token = init->buffers_offset;
42793+ dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
42794+ if (!dev->agp_buffer_map) {
42795+ DRM_ERROR("could not find dma buffer region!\n");
42796+ dev->dev_private = (void *)dev_priv;
42797+ r128_do_cleanup_cce(dev);
42798+ return -EINVAL;
42799+ }
42800+
42801+ if (!dev_priv->is_pci) {
42802+ dev_priv->agp_textures =
42803+ drm_core_findmap(dev, init->agp_textures_offset);
42804+ if (!dev_priv->agp_textures) {
42805+ DRM_ERROR("could not find agp texture region!\n");
42806+ dev->dev_private = (void *)dev_priv;
42807+ r128_do_cleanup_cce(dev);
42808+ return -EINVAL;
42809+ }
42810+ }
42811+
42812+ dev_priv->sarea_priv =
42813+ (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
42814+ init->sarea_priv_offset);
42815+
42816+#if __OS_HAS_AGP
42817+ if (!dev_priv->is_pci) {
42818+ drm_core_ioremap(dev_priv->cce_ring, dev);
42819+ drm_core_ioremap(dev_priv->ring_rptr, dev);
42820+ drm_core_ioremap(dev->agp_buffer_map, dev);
42821+ if (!dev_priv->cce_ring->handle ||
42822+ !dev_priv->ring_rptr->handle ||
42823+ !dev->agp_buffer_map->handle) {
42824+ DRM_ERROR("Could not ioremap agp regions!\n");
42825+ dev->dev_private = (void *)dev_priv;
42826+ r128_do_cleanup_cce(dev);
42827+ return -ENOMEM;
42828+ }
42829+ } else
42830+#endif
42831+ {
42832+ dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
42833+ dev_priv->ring_rptr->handle =
42834+ (void *)dev_priv->ring_rptr->offset;
42835+ dev->agp_buffer_map->handle =
42836+ (void *)dev->agp_buffer_map->offset;
42837+ }
42838+
42839+#if __OS_HAS_AGP
42840+ if (!dev_priv->is_pci)
42841+ dev_priv->cce_buffers_offset = dev->agp->base;
42842+ else
42843+#endif
42844+ dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
42845+
42846+ dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
42847+ dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
42848+ + init->ring_size / sizeof(u32));
42849+ dev_priv->ring.size = init->ring_size;
42850+ dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
42851+
42852+ dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
42853+
42854+ dev_priv->ring.high_mark = 128;
42855+
42856+ dev_priv->sarea_priv->last_frame = 0;
42857+ R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
42858+
42859+ dev_priv->sarea_priv->last_dispatch = 0;
42860+ R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
42861+
42862+#if __OS_HAS_AGP
42863+ if (dev_priv->is_pci) {
42864+#endif
42865+ dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
42866+ dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
42867+ dev_priv->gart_info.addr = NULL;
42868+ dev_priv->gart_info.bus_addr = 0;
42869+ dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
42870+ if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
42871+ DRM_ERROR("failed to init PCI GART!\n");
42872+ dev->dev_private = (void *)dev_priv;
42873+ r128_do_cleanup_cce(dev);
42874+ return -ENOMEM;
42875+ }
42876+ R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
42877+#if __OS_HAS_AGP
42878+ }
42879+#endif
42880+
42881+ r128_cce_init_ring_buffer(dev, dev_priv);
42882+ r128_cce_load_microcode(dev_priv);
42883+
42884+ dev->dev_private = (void *)dev_priv;
42885+
42886+ r128_do_engine_reset(dev);
42887+
42888+ return 0;
42889+}
42890+
42891+int r128_do_cleanup_cce(struct drm_device * dev)
42892+{
42893+
42894+ /* Make sure interrupts are disabled here because the uninstall ioctl
42895+ * may not have been called from userspace and after dev_private
42896+ * is freed, it's too late.
42897+ */
42898+ if (dev->irq_enabled)
42899+ drm_irq_uninstall(dev);
42900+
42901+ if (dev->dev_private) {
42902+ drm_r128_private_t *dev_priv = dev->dev_private;
42903+
42904+#if __OS_HAS_AGP
42905+ if (!dev_priv->is_pci) {
42906+ if (dev_priv->cce_ring != NULL)
42907+ drm_core_ioremapfree(dev_priv->cce_ring, dev);
42908+ if (dev_priv->ring_rptr != NULL)
42909+ drm_core_ioremapfree(dev_priv->ring_rptr, dev);
42910+ if (dev->agp_buffer_map != NULL) {
42911+ drm_core_ioremapfree(dev->agp_buffer_map, dev);
42912+ dev->agp_buffer_map = NULL;
42913+ }
42914+ } else
42915+#endif
42916+ {
42917+ if (dev_priv->gart_info.bus_addr)
42918+ if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
42919+ DRM_ERROR("failed to cleanup PCI GART!\n");
42920+ }
42921+
42922+ drm_free(dev->dev_private, sizeof(drm_r128_private_t),
42923+ DRM_MEM_DRIVER);
42924+ dev->dev_private = NULL;
42925+ }
42926+
42927+ return 0;
42928+}
42929+
42930+int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
42931+{
42932+ drm_r128_init_t *init = data;
42933+
42934+ DRM_DEBUG("\n");
42935+
42936+ LOCK_TEST_WITH_RETURN(dev, file_priv);
42937+
42938+ switch (init->func) {
42939+ case R128_INIT_CCE:
42940+ return r128_do_init_cce(dev, init);
42941+ case R128_CLEANUP_CCE:
42942+ return r128_do_cleanup_cce(dev);
42943+ }
42944+
42945+ return -EINVAL;
42946+}
42947+
42948+int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
42949+{
42950+ drm_r128_private_t *dev_priv = dev->dev_private;
42951+ DRM_DEBUG("\n");
42952+
42953+ LOCK_TEST_WITH_RETURN(dev, file_priv);
42954+
42955+ if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
42956+ DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
42957+ return 0;
42958+ }
42959+
42960+ r128_do_cce_start(dev_priv);
42961+
42962+ return 0;
42963+}
42964+
42965+/* Stop the CCE. The engine must have been idled before calling this
42966+ * routine.
42967+ */
42968+int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
42969+{
42970+ drm_r128_private_t *dev_priv = dev->dev_private;
42971+ drm_r128_cce_stop_t *stop = data;
42972+ int ret;
42973+ DRM_DEBUG("\n");
42974+
42975+ LOCK_TEST_WITH_RETURN(dev, file_priv);
42976+
42977+ /* Flush any pending CCE commands. This ensures any outstanding
42978+ * commands are exectuted by the engine before we turn it off.
42979+ */
42980+ if (stop->flush) {
42981+ r128_do_cce_flush(dev_priv);
42982+ }
42983+
42984+ /* If we fail to make the engine go idle, we return an error
42985+ * code so that the DRM ioctl wrapper can try again.
42986+ */
42987+ if (stop->idle) {
42988+ ret = r128_do_cce_idle(dev_priv);
42989+ if (ret)
42990+ return ret;
42991+ }
42992+
42993+ /* Finally, we can turn off the CCE. If the engine isn't idle,
42994+ * we will get some dropped triangles as they won't be fully
42995+ * rendered before the CCE is shut down.
42996+ */
42997+ r128_do_cce_stop(dev_priv);
42998+
42999+ /* Reset the engine */
43000+ r128_do_engine_reset(dev);
43001+
43002+ return 0;
43003+}
43004+
43005+/* Just reset the CCE ring. Called as part of an X Server engine reset.
43006+ */
43007+int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
43008+{
43009+ drm_r128_private_t *dev_priv = dev->dev_private;
43010+ DRM_DEBUG("\n");
43011+
43012+ LOCK_TEST_WITH_RETURN(dev, file_priv);
43013+
43014+ if (!dev_priv) {
43015+ DRM_DEBUG("%s called before init done\n", __FUNCTION__);
43016+ return -EINVAL;
43017+ }
43018+
43019+ r128_do_cce_reset(dev_priv);
43020+
43021+ /* The CCE is no longer running after an engine reset */
43022+ dev_priv->cce_running = 0;
43023+
43024+ return 0;
43025+}
43026+
43027+int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
43028+{
43029+ drm_r128_private_t *dev_priv = dev->dev_private;
43030+ DRM_DEBUG("\n");
43031+
43032+ LOCK_TEST_WITH_RETURN(dev, file_priv);
43033+
43034+ if (dev_priv->cce_running) {
43035+ r128_do_cce_flush(dev_priv);
43036+ }
43037+
43038+ return r128_do_cce_idle(dev_priv);
43039+}
43040+
43041+int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
43042+{
43043+ DRM_DEBUG("\n");
43044+
43045+ LOCK_TEST_WITH_RETURN(dev, file_priv);
43046+
43047+ return r128_do_engine_reset(dev);
43048+}
43049+
43050+int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
43051+{
43052+ return -EINVAL;
43053+}
43054+
43055+/* ================================================================
43056+ * Freelist management
43057+ */
43058+#define R128_BUFFER_USED 0xffffffff
43059+#define R128_BUFFER_FREE 0
43060+
43061+#if 0
43062+static int r128_freelist_init(struct drm_device * dev)
43063+{
43064+ struct drm_device_dma *dma = dev->dma;
43065+ drm_r128_private_t *dev_priv = dev->dev_private;
43066+ struct drm_buf *buf;
43067+ drm_r128_buf_priv_t *buf_priv;
43068+ drm_r128_freelist_t *entry;
43069+ int i;
43070+
43071+ dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
43072+ if (dev_priv->head == NULL)
43073+ return -ENOMEM;
43074+
43075+ memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
43076+ dev_priv->head->age = R128_BUFFER_USED;
43077+
43078+ for (i = 0; i < dma->buf_count; i++) {
43079+ buf = dma->buflist[i];
43080+ buf_priv = buf->dev_private;
43081+
43082+ entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
43083+ if (!entry)
43084+ return -ENOMEM;
43085+
43086+ entry->age = R128_BUFFER_FREE;
43087+ entry->buf = buf;
43088+ entry->prev = dev_priv->head;
43089+ entry->next = dev_priv->head->next;
43090+ if (!entry->next)
43091+ dev_priv->tail = entry;
43092+
43093+ buf_priv->discard = 0;
43094+ buf_priv->dispatched = 0;
43095+ buf_priv->list_entry = entry;
43096+
43097+ dev_priv->head->next = entry;
43098+
43099+ if (dev_priv->head->next)
43100+ dev_priv->head->next->prev = entry;
43101+ }
43102+
43103+ return 0;
43104+
43105+}
43106+#endif
43107+
43108+static struct drm_buf *r128_freelist_get(struct drm_device * dev)
43109+{
43110+ struct drm_device_dma *dma = dev->dma;
43111+ drm_r128_private_t *dev_priv = dev->dev_private;
43112+ drm_r128_buf_priv_t *buf_priv;
43113+ struct drm_buf *buf;
43114+ int i, t;
43115+
43116+ /* FIXME: Optimize -- use freelist code */
43117+
43118+ for (i = 0; i < dma->buf_count; i++) {
43119+ buf = dma->buflist[i];
43120+ buf_priv = buf->dev_private;
43121+ if (buf->file_priv == 0)
43122+ return buf;
43123+ }
43124+
43125+ for (t = 0; t < dev_priv->usec_timeout; t++) {
43126+ u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
43127+
43128+ for (i = 0; i < dma->buf_count; i++) {
43129+ buf = dma->buflist[i];
43130+ buf_priv = buf->dev_private;
43131+ if (buf->pending && buf_priv->age <= done_age) {
43132+ /* The buffer has been processed, so it
43133+ * can now be used.
43134+ */
43135+ buf->pending = 0;
43136+ return buf;
43137+ }
43138+ }
43139+ DRM_UDELAY(1);
43140+ }
43141+
43142+ DRM_DEBUG("returning NULL!\n");
43143+ return NULL;
43144+}
43145+
43146+void r128_freelist_reset(struct drm_device * dev)
43147+{
43148+ struct drm_device_dma *dma = dev->dma;
43149+ int i;
43150+
43151+ for (i = 0; i < dma->buf_count; i++) {
43152+ struct drm_buf *buf = dma->buflist[i];
43153+ drm_r128_buf_priv_t *buf_priv = buf->dev_private;
43154+ buf_priv->age = 0;
43155+ }
43156+}
43157+
43158+/* ================================================================
43159+ * CCE command submission
43160+ */
43161+
43162+int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
43163+{
43164+ drm_r128_ring_buffer_t *ring = &dev_priv->ring;
43165+ int i;
43166+
43167+ for (i = 0; i < dev_priv->usec_timeout; i++) {
43168+ r128_update_ring_snapshot(dev_priv);
43169+ if (ring->space >= n)
43170+ return 0;
43171+ DRM_UDELAY(1);
43172+ }
43173+
43174+ /* FIXME: This is being ignored... */
43175+ DRM_ERROR("failed!\n");
43176+ return -EBUSY;
43177+}
43178+
43179+static int r128_cce_get_buffers(struct drm_device * dev,
43180+ struct drm_file *file_priv,
43181+ struct drm_dma * d)
43182+{
43183+ int i;
43184+ struct drm_buf *buf;
43185+
43186+ for (i = d->granted_count; i < d->request_count; i++) {
43187+ buf = r128_freelist_get(dev);
43188+ if (!buf)
43189+ return -EAGAIN;
43190+
43191+ buf->file_priv = file_priv;
43192+
43193+ if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
43194+ sizeof(buf->idx)))
43195+ return -EFAULT;
43196+ if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
43197+ sizeof(buf->total)))
43198+ return -EFAULT;
43199+
43200+ d->granted_count++;
43201+ }
43202+ return 0;
43203+}
43204+
43205+int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
43206+{
43207+ struct drm_device_dma *dma = dev->dma;
43208+ int ret = 0;
43209+ struct drm_dma *d = data;
43210+
43211+ LOCK_TEST_WITH_RETURN(dev, file_priv);
43212+
43213+ /* Please don't send us buffers.
43214+ */
43215+ if (d->send_count != 0) {
43216+ DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
43217+ DRM_CURRENTPID, d->send_count);
43218+ return -EINVAL;
43219+ }
43220+
43221+ /* We'll send you buffers.
43222+ */
43223+ if (d->request_count < 0 || d->request_count > dma->buf_count) {
43224+ DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
43225+ DRM_CURRENTPID, d->request_count, dma->buf_count);
43226+ return -EINVAL;
43227+ }
43228+
43229+ d->granted_count = 0;
43230+
43231+ if (d->request_count) {
43232+ ret = r128_cce_get_buffers(dev, file_priv, d);
43233+ }
43234+
43235+ return ret;
43236+}
43237Index: git/shared-core/r128_drm.h
43238===================================================================
43239--- git.orig/shared-core/r128_drm.h 2008-12-12 17:20:14.000000000 +0000
43240+++ git/shared-core/r128_drm.h 2008-12-12 17:35:22.000000000 +0000
43241@@ -153,7 +153,7 @@
43242
43243 /* The current cliprects, or a subset thereof.
43244 */
43245- drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
43246+ struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
43247 unsigned int nbox;
43248
43249 /* Counters for client-side throttling of rendering clients.
43250@@ -161,7 +161,7 @@
43251 unsigned int last_frame;
43252 unsigned int last_dispatch;
43253
43254- drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
43255+ struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
43256 unsigned int tex_age[R128_NR_TEX_HEAPS];
43257 int ctx_owner;
43258 int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */
43259@@ -222,11 +222,7 @@
43260 R128_INIT_CCE = 0x01,
43261 R128_CLEANUP_CCE = 0x02
43262 } func;
43263-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
43264- int sarea_priv_offset;
43265-#else
43266 unsigned long sarea_priv_offset;
43267-#endif
43268 int is_pci;
43269 int cce_mode;
43270 int cce_secure;
43271@@ -240,21 +236,12 @@
43272 unsigned int depth_offset, depth_pitch;
43273 unsigned int span_offset;
43274
43275-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
43276- unsigned int fb_offset;
43277- unsigned int mmio_offset;
43278- unsigned int ring_offset;
43279- unsigned int ring_rptr_offset;
43280- unsigned int buffers_offset;
43281- unsigned int agp_textures_offset;
43282-#else
43283 unsigned long fb_offset;
43284 unsigned long mmio_offset;
43285 unsigned long ring_offset;
43286 unsigned long ring_rptr_offset;
43287 unsigned long buffers_offset;
43288 unsigned long agp_textures_offset;
43289-#endif
43290 } drm_r128_init_t;
43291
43292 typedef struct drm_r128_cce_stop {
43293@@ -264,15 +251,10 @@
43294
43295 typedef struct drm_r128_clear {
43296 unsigned int flags;
43297-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
43298- int x, y, w, h;
43299-#endif
43300 unsigned int clear_color;
43301 unsigned int clear_depth;
43302-#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
43303 unsigned int color_mask;
43304 unsigned int depth_mask;
43305-#endif
43306 } drm_r128_clear_t;
43307
43308 typedef struct drm_r128_vertex {
43309Index: git/shared-core/r128_drv.h
43310===================================================================
43311--- /dev/null 1970-01-01 00:00:00.000000000 +0000
43312+++ git/shared-core/r128_drv.h 2008-12-12 17:35:22.000000000 +0000
43313@@ -0,0 +1,523 @@
43314+/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
43315+ * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
43316+ */
43317+/*
43318+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
43319+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
43320+ * All rights reserved.
43321+ *
43322+ * Permission is hereby granted, free of charge, to any person obtaining a
43323+ * copy of this software and associated documentation files (the "Software"),
43324+ * to deal in the Software without restriction, including without limitation
43325+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
43326+ * and/or sell copies of the Software, and to permit persons to whom the
43327+ * Software is furnished to do so, subject to the following conditions:
43328+ *
43329+ * The above copyright notice and this permission notice (including the next
43330+ * paragraph) shall be included in all copies or substantial portions of the
43331+ * Software.
43332+ *
43333+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43334+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43335+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43336+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
43337+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
43338+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
43339+ * DEALINGS IN THE SOFTWARE.
43340+ *
43341+ * Authors:
43342+ * Rickard E. (Rik) Faith <faith@valinux.com>
43343+ * Kevin E. Martin <martin@valinux.com>
43344+ * Gareth Hughes <gareth@valinux.com>
43345+ * Michel D�zer <daenzerm@student.ethz.ch>
43346+ */
43347+
43348+#ifndef __R128_DRV_H__
43349+#define __R128_DRV_H__
43350+
43351+/* General customization:
43352+ */
43353+#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
43354+
43355+#define DRIVER_NAME "r128"
43356+#define DRIVER_DESC "ATI Rage 128"
43357+#define DRIVER_DATE "20030725"
43358+
43359+/* Interface history:
43360+ *
43361+ * ?? - ??
43362+ * 2.4 - Add support for ycbcr textures (no new ioctls)
43363+ * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
43364+ */
43365+#define DRIVER_MAJOR 2
43366+#define DRIVER_MINOR 5
43367+#define DRIVER_PATCHLEVEL 0
43368+
43369+#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR )
43370+
43371+typedef struct drm_r128_freelist {
43372+ unsigned int age;
43373+ struct drm_buf *buf;
43374+ struct drm_r128_freelist *next;
43375+ struct drm_r128_freelist *prev;
43376+} drm_r128_freelist_t;
43377+
43378+typedef struct drm_r128_ring_buffer {
43379+ u32 *start;
43380+ u32 *end;
43381+ int size;
43382+ int size_l2qw;
43383+
43384+ u32 tail;
43385+ u32 tail_mask;
43386+ int space;
43387+
43388+ int high_mark;
43389+} drm_r128_ring_buffer_t;
43390+
43391+typedef struct drm_r128_private {
43392+ drm_r128_ring_buffer_t ring;
43393+ drm_r128_sarea_t *sarea_priv;
43394+
43395+ int cce_mode;
43396+ int cce_fifo_size;
43397+ int cce_running;
43398+
43399+ drm_r128_freelist_t *head;
43400+ drm_r128_freelist_t *tail;
43401+
43402+ int usec_timeout;
43403+ int is_pci;
43404+ unsigned long cce_buffers_offset;
43405+
43406+ atomic_t idle_count;
43407+
43408+ int page_flipping;
43409+ int current_page;
43410+ u32 crtc_offset;
43411+ u32 crtc_offset_cntl;
43412+
43413+ u32 color_fmt;
43414+ unsigned int front_offset;
43415+ unsigned int front_pitch;
43416+ unsigned int back_offset;
43417+ unsigned int back_pitch;
43418+
43419+ u32 depth_fmt;
43420+ unsigned int depth_offset;
43421+ unsigned int depth_pitch;
43422+ unsigned int span_offset;
43423+
43424+ u32 front_pitch_offset_c;
43425+ u32 back_pitch_offset_c;
43426+ u32 depth_pitch_offset_c;
43427+ u32 span_pitch_offset_c;
43428+
43429+ drm_local_map_t *sarea;
43430+ drm_local_map_t *mmio;
43431+ drm_local_map_t *cce_ring;
43432+ drm_local_map_t *ring_rptr;
43433+ drm_local_map_t *agp_textures;
43434+ struct ati_pcigart_info gart_info;
43435+} drm_r128_private_t;
43436+
43437+typedef struct drm_r128_buf_priv {
43438+ u32 age;
43439+ int prim;
43440+ int discard;
43441+ int dispatched;
43442+ drm_r128_freelist_t *list_entry;
43443+} drm_r128_buf_priv_t;
43444+
43445+extern struct drm_ioctl_desc r128_ioctls[];
43446+extern int r128_max_ioctl;
43447+
43448+ /* r128_cce.c */
43449+extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
43450+extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
43451+extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
43452+extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
43453+extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
43454+extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
43455+extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
43456+extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
43457+
43458+extern void r128_freelist_reset(struct drm_device * dev);
43459+
43460+extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
43461+
43462+extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
43463+extern int r128_do_cleanup_cce(struct drm_device * dev);
43464+
43465+extern int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
43466+
43467+extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
43468+extern void r128_driver_irq_preinstall(struct drm_device * dev);
43469+extern void r128_driver_irq_postinstall(struct drm_device * dev);
43470+extern void r128_driver_irq_uninstall(struct drm_device * dev);
43471+extern void r128_driver_lastclose(struct drm_device * dev);
43472+extern void r128_driver_preclose(struct drm_device * dev,
43473+ struct drm_file *file_priv);
43474+
43475+extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
43476+ unsigned long arg);
43477+
43478+/* Register definitions, register access macros and drmAddMap constants
43479+ * for Rage 128 kernel driver.
43480+ */
43481+
43482+#define R128_AUX_SC_CNTL 0x1660
43483+# define R128_AUX1_SC_EN (1 << 0)
43484+# define R128_AUX1_SC_MODE_OR (0 << 1)
43485+# define R128_AUX1_SC_MODE_NAND (1 << 1)
43486+# define R128_AUX2_SC_EN (1 << 2)
43487+# define R128_AUX2_SC_MODE_OR (0 << 3)
43488+# define R128_AUX2_SC_MODE_NAND (1 << 3)
43489+# define R128_AUX3_SC_EN (1 << 4)
43490+# define R128_AUX3_SC_MODE_OR (0 << 5)
43491+# define R128_AUX3_SC_MODE_NAND (1 << 5)
43492+#define R128_AUX1_SC_LEFT 0x1664
43493+#define R128_AUX1_SC_RIGHT 0x1668
43494+#define R128_AUX1_SC_TOP 0x166c
43495+#define R128_AUX1_SC_BOTTOM 0x1670
43496+#define R128_AUX2_SC_LEFT 0x1674
43497+#define R128_AUX2_SC_RIGHT 0x1678
43498+#define R128_AUX2_SC_TOP 0x167c
43499+#define R128_AUX2_SC_BOTTOM 0x1680
43500+#define R128_AUX3_SC_LEFT 0x1684
43501+#define R128_AUX3_SC_RIGHT 0x1688
43502+#define R128_AUX3_SC_TOP 0x168c
43503+#define R128_AUX3_SC_BOTTOM 0x1690
43504+
43505+#define R128_BRUSH_DATA0 0x1480
43506+#define R128_BUS_CNTL 0x0030
43507+# define R128_BUS_MASTER_DIS (1 << 6)
43508+
43509+#define R128_CLOCK_CNTL_INDEX 0x0008
43510+#define R128_CLOCK_CNTL_DATA 0x000c
43511+# define R128_PLL_WR_EN (1 << 7)
43512+#define R128_CONSTANT_COLOR_C 0x1d34
43513+#define R128_CRTC_OFFSET 0x0224
43514+#define R128_CRTC_OFFSET_CNTL 0x0228
43515+# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
43516+
43517+#define R128_DP_GUI_MASTER_CNTL 0x146c
43518+# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
43519+# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
43520+# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
43521+# define R128_GMC_BRUSH_NONE (15 << 4)
43522+# define R128_GMC_DST_16BPP (4 << 8)
43523+# define R128_GMC_DST_24BPP (5 << 8)
43524+# define R128_GMC_DST_32BPP (6 << 8)
43525+# define R128_GMC_DST_DATATYPE_SHIFT 8
43526+# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
43527+# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
43528+# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
43529+# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
43530+# define R128_GMC_AUX_CLIP_DIS (1 << 29)
43531+# define R128_GMC_WR_MSK_DIS (1 << 30)
43532+# define R128_ROP3_S 0x00cc0000
43533+# define R128_ROP3_P 0x00f00000
43534+#define R128_DP_WRITE_MASK 0x16cc
43535+#define R128_DST_PITCH_OFFSET_C 0x1c80
43536+# define R128_DST_TILE (1 << 31)
43537+
43538+#define R128_GEN_INT_CNTL 0x0040
43539+# define R128_CRTC_VBLANK_INT_EN (1 << 0)
43540+#define R128_GEN_INT_STATUS 0x0044
43541+# define R128_CRTC_VBLANK_INT (1 << 0)
43542+# define R128_CRTC_VBLANK_INT_AK (1 << 0)
43543+#define R128_GEN_RESET_CNTL 0x00f0
43544+# define R128_SOFT_RESET_GUI (1 << 0)
43545+
43546+#define R128_GUI_SCRATCH_REG0 0x15e0
43547+#define R128_GUI_SCRATCH_REG1 0x15e4
43548+#define R128_GUI_SCRATCH_REG2 0x15e8
43549+#define R128_GUI_SCRATCH_REG3 0x15ec
43550+#define R128_GUI_SCRATCH_REG4 0x15f0
43551+#define R128_GUI_SCRATCH_REG5 0x15f4
43552+
43553+#define R128_GUI_STAT 0x1740
43554+# define R128_GUI_FIFOCNT_MASK 0x0fff
43555+# define R128_GUI_ACTIVE (1 << 31)
43556+
43557+#define R128_MCLK_CNTL 0x000f
43558+# define R128_FORCE_GCP (1 << 16)
43559+# define R128_FORCE_PIPE3D_CP (1 << 17)
43560+# define R128_FORCE_RCP (1 << 18)
43561+
43562+#define R128_PC_GUI_CTLSTAT 0x1748
43563+#define R128_PC_NGUI_CTLSTAT 0x0184
43564+# define R128_PC_FLUSH_GUI (3 << 0)
43565+# define R128_PC_RI_GUI (1 << 2)
43566+# define R128_PC_FLUSH_ALL 0x00ff
43567+# define R128_PC_BUSY (1 << 31)
43568+
43569+#define R128_PCI_GART_PAGE 0x017c
43570+#define R128_PRIM_TEX_CNTL_C 0x1cb0
43571+
43572+#define R128_SCALE_3D_CNTL 0x1a00
43573+#define R128_SEC_TEX_CNTL_C 0x1d00
43574+#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
43575+#define R128_SETUP_CNTL 0x1bc4
43576+#define R128_STEN_REF_MASK_C 0x1d40
43577+
43578+#define R128_TEX_CNTL_C 0x1c9c
43579+# define R128_TEX_CACHE_FLUSH (1 << 23)
43580+
43581+#define R128_WAIT_UNTIL 0x1720
43582+# define R128_EVENT_CRTC_OFFSET (1 << 0)
43583+#define R128_WINDOW_XY_OFFSET 0x1bcc
43584+
43585+/* CCE registers
43586+ */
43587+#define R128_PM4_BUFFER_OFFSET 0x0700
43588+#define R128_PM4_BUFFER_CNTL 0x0704
43589+# define R128_PM4_MASK (15 << 28)
43590+# define R128_PM4_NONPM4 (0 << 28)
43591+# define R128_PM4_192PIO (1 << 28)
43592+# define R128_PM4_192BM (2 << 28)
43593+# define R128_PM4_128PIO_64INDBM (3 << 28)
43594+# define R128_PM4_128BM_64INDBM (4 << 28)
43595+# define R128_PM4_64PIO_128INDBM (5 << 28)
43596+# define R128_PM4_64BM_128INDBM (6 << 28)
43597+# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
43598+# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
43599+# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
43600+# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27)
43601+
43602+#define R128_PM4_BUFFER_WM_CNTL 0x0708
43603+# define R128_WMA_SHIFT 0
43604+# define R128_WMB_SHIFT 8
43605+# define R128_WMC_SHIFT 16
43606+# define R128_WB_WM_SHIFT 24
43607+
43608+#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
43609+#define R128_PM4_BUFFER_DL_RPTR 0x0710
43610+#define R128_PM4_BUFFER_DL_WPTR 0x0714
43611+# define R128_PM4_BUFFER_DL_DONE (1 << 31)
43612+
43613+#define R128_PM4_VC_FPU_SETUP 0x071c
43614+
43615+#define R128_PM4_IW_INDOFF 0x0738
43616+#define R128_PM4_IW_INDSIZE 0x073c
43617+
43618+#define R128_PM4_STAT 0x07b8
43619+# define R128_PM4_FIFOCNT_MASK 0x0fff
43620+# define R128_PM4_BUSY (1 << 16)
43621+# define R128_PM4_GUI_ACTIVE (1 << 31)
43622+
43623+#define R128_PM4_MICROCODE_ADDR 0x07d4
43624+#define R128_PM4_MICROCODE_RADDR 0x07d8
43625+#define R128_PM4_MICROCODE_DATAH 0x07dc
43626+#define R128_PM4_MICROCODE_DATAL 0x07e0
43627+
43628+#define R128_PM4_BUFFER_ADDR 0x07f0
43629+#define R128_PM4_MICRO_CNTL 0x07fc
43630+# define R128_PM4_MICRO_FREERUN (1 << 30)
43631+
43632+#define R128_PM4_FIFO_DATA_EVEN 0x1000
43633+#define R128_PM4_FIFO_DATA_ODD 0x1004
43634+
43635+/* CCE command packets
43636+ */
43637+#define R128_CCE_PACKET0 0x00000000
43638+#define R128_CCE_PACKET1 0x40000000
43639+#define R128_CCE_PACKET2 0x80000000
43640+#define R128_CCE_PACKET3 0xC0000000
43641+# define R128_CNTL_HOSTDATA_BLT 0x00009400
43642+# define R128_CNTL_PAINT_MULTI 0x00009A00
43643+# define R128_CNTL_BITBLT_MULTI 0x00009B00
43644+# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
43645+
43646+#define R128_CCE_PACKET_MASK 0xC0000000
43647+#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
43648+#define R128_CCE_PACKET0_REG_MASK 0x000007ff
43649+#define R128_CCE_PACKET1_REG0_MASK 0x000007ff
43650+#define R128_CCE_PACKET1_REG1_MASK 0x003ff800
43651+
43652+#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
43653+#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
43654+#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
43655+#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
43656+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
43657+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
43658+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
43659+#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
43660+#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
43661+#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
43662+#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
43663+#define R128_CCE_VC_CNTL_NUM_SHIFT 16
43664+
43665+#define R128_DATATYPE_VQ 0
43666+#define R128_DATATYPE_CI4 1
43667+#define R128_DATATYPE_CI8 2
43668+#define R128_DATATYPE_ARGB1555 3
43669+#define R128_DATATYPE_RGB565 4
43670+#define R128_DATATYPE_RGB888 5
43671+#define R128_DATATYPE_ARGB8888 6
43672+#define R128_DATATYPE_RGB332 7
43673+#define R128_DATATYPE_Y8 8
43674+#define R128_DATATYPE_RGB8 9
43675+#define R128_DATATYPE_CI16 10
43676+#define R128_DATATYPE_YVYU422 11
43677+#define R128_DATATYPE_VYUY422 12
43678+#define R128_DATATYPE_AYUV444 14
43679+#define R128_DATATYPE_ARGB4444 15
43680+
43681+/* Constants */
43682+#define R128_AGP_OFFSET 0x02000000
43683+
43684+#define R128_WATERMARK_L 16
43685+#define R128_WATERMARK_M 8
43686+#define R128_WATERMARK_N 8
43687+#define R128_WATERMARK_K 128
43688+
43689+#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
43690+
43691+#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
43692+#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
43693+#define R128_MAX_VB_AGE 0x7fffffff
43694+#define R128_MAX_VB_VERTS (0xffff)
43695+
43696+#define R128_RING_HIGH_MARK 128
43697+
43698+#define R128_PERFORMANCE_BOXES 0
43699+
43700+#define R128_PCIGART_TABLE_SIZE 32768
43701+
43702+#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
43703+#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
43704+#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
43705+#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
43706+
43707+#define R128_WRITE_PLL(addr,val) \
43708+do { \
43709+ R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
43710+ ((addr) & 0x1f) | R128_PLL_WR_EN); \
43711+ R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
43712+} while (0)
43713+
43714+#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
43715+ ((n) << 16) | ((reg) >> 2))
43716+#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
43717+ (((reg1) >> 2) << 11) | ((reg0) >> 2))
43718+#define CCE_PACKET2() (R128_CCE_PACKET2)
43719+#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
43720+ (pkt) | ((n) << 16))
43721+
43722+static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
43723+{
43724+ drm_r128_ring_buffer_t *ring = &dev_priv->ring;
43725+ ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
43726+ if (ring->space <= 0)
43727+ ring->space += ring->size;
43728+}
43729+
43730+/* ================================================================
43731+ * Misc helper macros
43732+ */
43733+
43734+#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
43735+do { \
43736+ drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
43737+ if ( ring->space < ring->high_mark ) { \
43738+ for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
43739+ r128_update_ring_snapshot( dev_priv ); \
43740+ if ( ring->space >= ring->high_mark ) \
43741+ goto __ring_space_done; \
43742+ DRM_UDELAY(1); \
43743+ } \
43744+ DRM_ERROR( "ring space check failed!\n" ); \
43745+ return -EBUSY; \
43746+ } \
43747+ __ring_space_done: \
43748+ ; \
43749+} while (0)
43750+
43751+#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
43752+do { \
43753+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
43754+ if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
43755+ int __ret = r128_do_cce_idle( dev_priv ); \
43756+ if ( __ret ) return __ret; \
43757+ sarea_priv->last_dispatch = 0; \
43758+ r128_freelist_reset( dev ); \
43759+ } \
43760+} while (0)
43761+
43762+#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
43763+ OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
43764+ OUT_RING( R128_EVENT_CRTC_OFFSET ); \
43765+} while (0)
43766+
43767+/* ================================================================
43768+ * Ring control
43769+ */
43770+
43771+#define R128_VERBOSE 0
43772+
43773+#define RING_LOCALS \
43774+ int write, _nr; unsigned int tail_mask; volatile u32 *ring;
43775+
43776+#define BEGIN_RING( n ) do { \
43777+ if ( R128_VERBOSE ) { \
43778+ DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
43779+ (n), __FUNCTION__ ); \
43780+ } \
43781+ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
43782+ COMMIT_RING(); \
43783+ r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
43784+ } \
43785+ _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
43786+ ring = dev_priv->ring.start; \
43787+ write = dev_priv->ring.tail; \
43788+ tail_mask = dev_priv->ring.tail_mask; \
43789+} while (0)
43790+
43791+/* You can set this to zero if you want. If the card locks up, you'll
43792+ * need to keep this set. It works around a bug in early revs of the
43793+ * Rage 128 chipset, where the CCE would read 32 dwords past the end of
43794+ * the ring buffer before wrapping around.
43795+ */
43796+#define R128_BROKEN_CCE 1
43797+
43798+#define ADVANCE_RING() do { \
43799+ if ( R128_VERBOSE ) { \
43800+ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
43801+ write, dev_priv->ring.tail ); \
43802+ } \
43803+ if ( R128_BROKEN_CCE && write < 32 ) { \
43804+ memcpy( dev_priv->ring.end, \
43805+ dev_priv->ring.start, \
43806+ write * sizeof(u32) ); \
43807+ } \
43808+ if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
43809+ DRM_ERROR( \
43810+ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
43811+ ((dev_priv->ring.tail + _nr) & tail_mask), \
43812+ write, __LINE__); \
43813+ } else \
43814+ dev_priv->ring.tail = write; \
43815+} while (0)
43816+
43817+#define COMMIT_RING() do { \
43818+ if ( R128_VERBOSE ) { \
43819+ DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \
43820+ dev_priv->ring.tail ); \
43821+ } \
43822+ DRM_MEMORYBARRIER(); \
43823+ R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \
43824+ R128_READ( R128_PM4_BUFFER_DL_WPTR ); \
43825+} while (0)
43826+
43827+#define OUT_RING( x ) do { \
43828+ if ( R128_VERBOSE ) { \
43829+ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
43830+ (unsigned int)(x), write ); \
43831+ } \
43832+ ring[write++] = cpu_to_le32( x ); \
43833+ write &= tail_mask; \
43834+} while (0)
43835+
43836+#endif /* __R128_DRV_H__ */
43837Index: git/shared-core/r128_irq.c
43838===================================================================
43839--- /dev/null 1970-01-01 00:00:00.000000000 +0000
43840+++ git/shared-core/r128_irq.c 2008-12-12 17:35:22.000000000 +0000
43841@@ -0,0 +1,101 @@
43842+/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */
43843+/*
43844+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
43845+ *
43846+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
43847+ * initial release of the Radeon 8500 driver under the XFree86 license.
43848+ * This notice must be preserved.
43849+ *
43850+ * Permission is hereby granted, free of charge, to any person obtaining a
43851+ * copy of this software and associated documentation files (the "Software"),
43852+ * to deal in the Software without restriction, including without limitation
43853+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
43854+ * and/or sell copies of the Software, and to permit persons to whom the
43855+ * Software is furnished to do so, subject to the following conditions:
43856+ *
43857+ * The above copyright notice and this permission notice (including the next
43858+ * paragraph) shall be included in all copies or substantial portions of the
43859+ * Software.
43860+ *
43861+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43862+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43863+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43864+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
43865+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
43866+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
43867+ * DEALINGS IN THE SOFTWARE.
43868+ *
43869+ * Authors:
43870+ * Keith Whitwell <keith@tungstengraphics.com>
43871+ * Eric Anholt <anholt@FreeBSD.org>
43872+ */
43873+
43874+#include "drmP.h"
43875+#include "drm.h"
43876+#include "r128_drm.h"
43877+#include "r128_drv.h"
43878+
43879+irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
43880+{
43881+ struct drm_device *dev = (struct drm_device *) arg;
43882+ drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
43883+ int status;
43884+
43885+ status = R128_READ(R128_GEN_INT_STATUS);
43886+
43887+ /* VBLANK interrupt */
43888+ if (status & R128_CRTC_VBLANK_INT) {
43889+ R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
43890+ atomic_inc(&dev->vbl_received);
43891+ DRM_WAKEUP(&dev->vbl_queue);
43892+ drm_vbl_send_signals(dev);
43893+ return IRQ_HANDLED;
43894+ }
43895+ return IRQ_NONE;
43896+}
43897+
43898+int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
43899+{
43900+ unsigned int cur_vblank;
43901+ int ret = 0;
43902+
43903+ /* Assume that the user has missed the current sequence number
43904+ * by about a day rather than she wants to wait for years
43905+ * using vertical blanks...
43906+ */
43907+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
43908+ (((cur_vblank = atomic_read(&dev->vbl_received))
43909+ - *sequence) <= (1 << 23)));
43910+
43911+ *sequence = cur_vblank;
43912+
43913+ return ret;
43914+}
43915+
43916+void r128_driver_irq_preinstall(struct drm_device * dev)
43917+{
43918+ drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
43919+
43920+ /* Disable *all* interrupts */
43921+ R128_WRITE(R128_GEN_INT_CNTL, 0);
43922+ /* Clear vblank bit if it's already high */
43923+ R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
43924+}
43925+
43926+void r128_driver_irq_postinstall(struct drm_device * dev)
43927+{
43928+ drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
43929+
43930+ /* Turn on VBL interrupt */
43931+ R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
43932+}
43933+
43934+void r128_driver_irq_uninstall(struct drm_device * dev)
43935+{
43936+ drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
43937+ if (!dev_priv)
43938+ return;
43939+
43940+ /* Disable *all* interrupts */
43941+ R128_WRITE(R128_GEN_INT_CNTL, 0);
43942+}
43943Index: git/shared-core/r128_state.c
43944===================================================================
43945--- /dev/null 1970-01-01 00:00:00.000000000 +0000
43946+++ git/shared-core/r128_state.c 2008-12-12 17:35:22.000000000 +0000
43947@@ -0,0 +1,1682 @@
43948+/* r128_state.c -- State support for r128 -*- linux-c -*-
43949+ * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
43950+ */
43951+/*
43952+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
43953+ * All Rights Reserved.
43954+ *
43955+ * Permission is hereby granted, free of charge, to any person obtaining a
43956+ * copy of this software and associated documentation files (the "Software"),
43957+ * to deal in the Software without restriction, including without limitation
43958+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
43959+ * and/or sell copies of the Software, and to permit persons to whom the
43960+ * Software is furnished to do so, subject to the following conditions:
43961+ *
43962+ * The above copyright notice and this permission notice (including the next
43963+ * paragraph) shall be included in all copies or substantial portions of the
43964+ * Software.
43965+ *
43966+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43967+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43968+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43969+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
43970+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
43971+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
43972+ * DEALINGS IN THE SOFTWARE.
43973+ *
43974+ * Authors:
43975+ * Gareth Hughes <gareth@valinux.com>
43976+ */
43977+
43978+#include "drmP.h"
43979+#include "drm.h"
43980+#include "r128_drm.h"
43981+#include "r128_drv.h"
43982+
43983+/* ================================================================
43984+ * CCE hardware state programming functions
43985+ */
43986+
43987+static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
43988+ struct drm_clip_rect * boxes, int count)
43989+{
43990+ u32 aux_sc_cntl = 0x00000000;
43991+ RING_LOCALS;
43992+ DRM_DEBUG(" %s\n", __FUNCTION__);
43993+
43994+ BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
43995+
43996+ if (count >= 1) {
43997+ OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
43998+ OUT_RING(boxes[0].x1);
43999+ OUT_RING(boxes[0].x2 - 1);
44000+ OUT_RING(boxes[0].y1);
44001+ OUT_RING(boxes[0].y2 - 1);
44002+
44003+ aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
44004+ }
44005+ if (count >= 2) {
44006+ OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
44007+ OUT_RING(boxes[1].x1);
44008+ OUT_RING(boxes[1].x2 - 1);
44009+ OUT_RING(boxes[1].y1);
44010+ OUT_RING(boxes[1].y2 - 1);
44011+
44012+ aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
44013+ }
44014+ if (count >= 3) {
44015+ OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
44016+ OUT_RING(boxes[2].x1);
44017+ OUT_RING(boxes[2].x2 - 1);
44018+ OUT_RING(boxes[2].y1);
44019+ OUT_RING(boxes[2].y2 - 1);
44020+
44021+ aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
44022+ }
44023+
44024+ OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
44025+ OUT_RING(aux_sc_cntl);
44026+
44027+ ADVANCE_RING();
44028+}
44029+
44030+static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
44031+{
44032+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44033+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44034+ RING_LOCALS;
44035+ DRM_DEBUG(" %s\n", __FUNCTION__);
44036+
44037+ BEGIN_RING(2);
44038+
44039+ OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
44040+ OUT_RING(ctx->scale_3d_cntl);
44041+
44042+ ADVANCE_RING();
44043+}
44044+
44045+static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
44046+{
44047+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44048+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44049+ RING_LOCALS;
44050+ DRM_DEBUG(" %s\n", __FUNCTION__);
44051+
44052+ BEGIN_RING(13);
44053+
44054+ OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
44055+ OUT_RING(ctx->dst_pitch_offset_c);
44056+ OUT_RING(ctx->dp_gui_master_cntl_c);
44057+ OUT_RING(ctx->sc_top_left_c);
44058+ OUT_RING(ctx->sc_bottom_right_c);
44059+ OUT_RING(ctx->z_offset_c);
44060+ OUT_RING(ctx->z_pitch_c);
44061+ OUT_RING(ctx->z_sten_cntl_c);
44062+ OUT_RING(ctx->tex_cntl_c);
44063+ OUT_RING(ctx->misc_3d_state_cntl_reg);
44064+ OUT_RING(ctx->texture_clr_cmp_clr_c);
44065+ OUT_RING(ctx->texture_clr_cmp_msk_c);
44066+ OUT_RING(ctx->fog_color_c);
44067+
44068+ ADVANCE_RING();
44069+}
44070+
44071+static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
44072+{
44073+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44074+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44075+ RING_LOCALS;
44076+ DRM_DEBUG(" %s\n", __FUNCTION__);
44077+
44078+ BEGIN_RING(3);
44079+
44080+ OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
44081+ OUT_RING(ctx->setup_cntl);
44082+ OUT_RING(ctx->pm4_vc_fpu_setup);
44083+
44084+ ADVANCE_RING();
44085+}
44086+
44087+static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
44088+{
44089+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44090+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44091+ RING_LOCALS;
44092+ DRM_DEBUG(" %s\n", __FUNCTION__);
44093+
44094+ BEGIN_RING(5);
44095+
44096+ OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
44097+ OUT_RING(ctx->dp_write_mask);
44098+
44099+ OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
44100+ OUT_RING(ctx->sten_ref_mask_c);
44101+ OUT_RING(ctx->plane_3d_mask_c);
44102+
44103+ ADVANCE_RING();
44104+}
44105+
44106+static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
44107+{
44108+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44109+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44110+ RING_LOCALS;
44111+ DRM_DEBUG(" %s\n", __FUNCTION__);
44112+
44113+ BEGIN_RING(2);
44114+
44115+ OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
44116+ OUT_RING(ctx->window_xy_offset);
44117+
44118+ ADVANCE_RING();
44119+}
44120+
44121+static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
44122+{
44123+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44124+ drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
44125+ drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
44126+ int i;
44127+ RING_LOCALS;
44128+ DRM_DEBUG(" %s\n", __FUNCTION__);
44129+
44130+ BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
44131+
44132+ OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
44133+ 2 + R128_MAX_TEXTURE_LEVELS));
44134+ OUT_RING(tex->tex_cntl);
44135+ OUT_RING(tex->tex_combine_cntl);
44136+ OUT_RING(ctx->tex_size_pitch_c);
44137+ for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
44138+ OUT_RING(tex->tex_offset[i]);
44139+ }
44140+
44141+ OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
44142+ OUT_RING(ctx->constant_color_c);
44143+ OUT_RING(tex->tex_border_color);
44144+
44145+ ADVANCE_RING();
44146+}
44147+
44148+static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
44149+{
44150+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44151+ drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
44152+ int i;
44153+ RING_LOCALS;
44154+ DRM_DEBUG(" %s\n", __FUNCTION__);
44155+
44156+ BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
44157+
44158+ OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
44159+ OUT_RING(tex->tex_cntl);
44160+ OUT_RING(tex->tex_combine_cntl);
44161+ for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
44162+ OUT_RING(tex->tex_offset[i]);
44163+ }
44164+
44165+ OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
44166+ OUT_RING(tex->tex_border_color);
44167+
44168+ ADVANCE_RING();
44169+}
44170+
44171+static void r128_emit_state(drm_r128_private_t * dev_priv)
44172+{
44173+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44174+ unsigned int dirty = sarea_priv->dirty;
44175+
44176+ DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
44177+
44178+ if (dirty & R128_UPLOAD_CORE) {
44179+ r128_emit_core(dev_priv);
44180+ sarea_priv->dirty &= ~R128_UPLOAD_CORE;
44181+ }
44182+
44183+ if (dirty & R128_UPLOAD_CONTEXT) {
44184+ r128_emit_context(dev_priv);
44185+ sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
44186+ }
44187+
44188+ if (dirty & R128_UPLOAD_SETUP) {
44189+ r128_emit_setup(dev_priv);
44190+ sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
44191+ }
44192+
44193+ if (dirty & R128_UPLOAD_MASKS) {
44194+ r128_emit_masks(dev_priv);
44195+ sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
44196+ }
44197+
44198+ if (dirty & R128_UPLOAD_WINDOW) {
44199+ r128_emit_window(dev_priv);
44200+ sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
44201+ }
44202+
44203+ if (dirty & R128_UPLOAD_TEX0) {
44204+ r128_emit_tex0(dev_priv);
44205+ sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
44206+ }
44207+
44208+ if (dirty & R128_UPLOAD_TEX1) {
44209+ r128_emit_tex1(dev_priv);
44210+ sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
44211+ }
44212+
44213+ /* Turn off the texture cache flushing */
44214+ sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
44215+
44216+ sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
44217+}
44218+
44219+#if R128_PERFORMANCE_BOXES
44220+/* ================================================================
44221+ * Performance monitoring functions
44222+ */
44223+
44224+static void r128_clear_box(drm_r128_private_t * dev_priv,
44225+ int x, int y, int w, int h, int r, int g, int b)
44226+{
44227+ u32 pitch, offset;
44228+ u32 fb_bpp, color;
44229+ RING_LOCALS;
44230+
44231+ switch (dev_priv->fb_bpp) {
44232+ case 16:
44233+ fb_bpp = R128_GMC_DST_16BPP;
44234+ color = (((r & 0xf8) << 8) |
44235+ ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
44236+ break;
44237+ case 24:
44238+ fb_bpp = R128_GMC_DST_24BPP;
44239+ color = ((r << 16) | (g << 8) | b);
44240+ break;
44241+ case 32:
44242+ fb_bpp = R128_GMC_DST_32BPP;
44243+ color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
44244+ break;
44245+ default:
44246+ return;
44247+ }
44248+
44249+ offset = dev_priv->back_offset;
44250+ pitch = dev_priv->back_pitch >> 3;
44251+
44252+ BEGIN_RING(6);
44253+
44254+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44255+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44256+ R128_GMC_BRUSH_SOLID_COLOR |
44257+ fb_bpp |
44258+ R128_GMC_SRC_DATATYPE_COLOR |
44259+ R128_ROP3_P |
44260+ R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
44261+
44262+ OUT_RING((pitch << 21) | (offset >> 5));
44263+ OUT_RING(color);
44264+
44265+ OUT_RING((x << 16) | y);
44266+ OUT_RING((w << 16) | h);
44267+
44268+ ADVANCE_RING();
44269+}
44270+
44271+static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
44272+{
44273+ if (atomic_read(&dev_priv->idle_count) == 0) {
44274+ r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
44275+ } else {
44276+ atomic_set(&dev_priv->idle_count, 0);
44277+ }
44278+}
44279+
44280+#endif
44281+
44282+/* ================================================================
44283+ * CCE command dispatch functions
44284+ */
44285+
44286+static void r128_print_dirty(const char *msg, unsigned int flags)
44287+{
44288+ DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
44289+ msg,
44290+ flags,
44291+ (flags & R128_UPLOAD_CORE) ? "core, " : "",
44292+ (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
44293+ (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
44294+ (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
44295+ (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
44296+ (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
44297+ (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
44298+ (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
44299+ (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
44300+}
44301+
44302+static void r128_cce_dispatch_clear(struct drm_device * dev,
44303+ drm_r128_clear_t * clear)
44304+{
44305+ drm_r128_private_t *dev_priv = dev->dev_private;
44306+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44307+ int nbox = sarea_priv->nbox;
44308+ struct drm_clip_rect *pbox = sarea_priv->boxes;
44309+ unsigned int flags = clear->flags;
44310+ int i;
44311+ RING_LOCALS;
44312+ DRM_DEBUG("%s\n", __FUNCTION__);
44313+
44314+ if (dev_priv->page_flipping && dev_priv->current_page == 1) {
44315+ unsigned int tmp = flags;
44316+
44317+ flags &= ~(R128_FRONT | R128_BACK);
44318+ if (tmp & R128_FRONT)
44319+ flags |= R128_BACK;
44320+ if (tmp & R128_BACK)
44321+ flags |= R128_FRONT;
44322+ }
44323+
44324+ for (i = 0; i < nbox; i++) {
44325+ int x = pbox[i].x1;
44326+ int y = pbox[i].y1;
44327+ int w = pbox[i].x2 - x;
44328+ int h = pbox[i].y2 - y;
44329+
44330+ DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
44331+ pbox[i].x1, pbox[i].y1, pbox[i].x2,
44332+ pbox[i].y2, flags);
44333+
44334+ if (flags & (R128_FRONT | R128_BACK)) {
44335+ BEGIN_RING(2);
44336+
44337+ OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
44338+ OUT_RING(clear->color_mask);
44339+
44340+ ADVANCE_RING();
44341+ }
44342+
44343+ if (flags & R128_FRONT) {
44344+ BEGIN_RING(6);
44345+
44346+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44347+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44348+ R128_GMC_BRUSH_SOLID_COLOR |
44349+ (dev_priv->color_fmt << 8) |
44350+ R128_GMC_SRC_DATATYPE_COLOR |
44351+ R128_ROP3_P |
44352+ R128_GMC_CLR_CMP_CNTL_DIS |
44353+ R128_GMC_AUX_CLIP_DIS);
44354+
44355+ OUT_RING(dev_priv->front_pitch_offset_c);
44356+ OUT_RING(clear->clear_color);
44357+
44358+ OUT_RING((x << 16) | y);
44359+ OUT_RING((w << 16) | h);
44360+
44361+ ADVANCE_RING();
44362+ }
44363+
44364+ if (flags & R128_BACK) {
44365+ BEGIN_RING(6);
44366+
44367+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44368+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44369+ R128_GMC_BRUSH_SOLID_COLOR |
44370+ (dev_priv->color_fmt << 8) |
44371+ R128_GMC_SRC_DATATYPE_COLOR |
44372+ R128_ROP3_P |
44373+ R128_GMC_CLR_CMP_CNTL_DIS |
44374+ R128_GMC_AUX_CLIP_DIS);
44375+
44376+ OUT_RING(dev_priv->back_pitch_offset_c);
44377+ OUT_RING(clear->clear_color);
44378+
44379+ OUT_RING((x << 16) | y);
44380+ OUT_RING((w << 16) | h);
44381+
44382+ ADVANCE_RING();
44383+ }
44384+
44385+ if (flags & R128_DEPTH) {
44386+ BEGIN_RING(6);
44387+
44388+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44389+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44390+ R128_GMC_BRUSH_SOLID_COLOR |
44391+ (dev_priv->depth_fmt << 8) |
44392+ R128_GMC_SRC_DATATYPE_COLOR |
44393+ R128_ROP3_P |
44394+ R128_GMC_CLR_CMP_CNTL_DIS |
44395+ R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
44396+
44397+ OUT_RING(dev_priv->depth_pitch_offset_c);
44398+ OUT_RING(clear->clear_depth);
44399+
44400+ OUT_RING((x << 16) | y);
44401+ OUT_RING((w << 16) | h);
44402+
44403+ ADVANCE_RING();
44404+ }
44405+ }
44406+}
44407+
44408+static void r128_cce_dispatch_swap(struct drm_device * dev)
44409+{
44410+ drm_r128_private_t *dev_priv = dev->dev_private;
44411+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44412+ int nbox = sarea_priv->nbox;
44413+ struct drm_clip_rect *pbox = sarea_priv->boxes;
44414+ int i;
44415+ RING_LOCALS;
44416+ DRM_DEBUG("%s\n", __FUNCTION__);
44417+
44418+#if R128_PERFORMANCE_BOXES
44419+ /* Do some trivial performance monitoring...
44420+ */
44421+ r128_cce_performance_boxes(dev_priv);
44422+#endif
44423+
44424+ for (i = 0; i < nbox; i++) {
44425+ int x = pbox[i].x1;
44426+ int y = pbox[i].y1;
44427+ int w = pbox[i].x2 - x;
44428+ int h = pbox[i].y2 - y;
44429+
44430+ BEGIN_RING(7);
44431+
44432+ OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
44433+ OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
44434+ R128_GMC_DST_PITCH_OFFSET_CNTL |
44435+ R128_GMC_BRUSH_NONE |
44436+ (dev_priv->color_fmt << 8) |
44437+ R128_GMC_SRC_DATATYPE_COLOR |
44438+ R128_ROP3_S |
44439+ R128_DP_SRC_SOURCE_MEMORY |
44440+ R128_GMC_CLR_CMP_CNTL_DIS |
44441+ R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
44442+
44443+ /* Make this work even if front & back are flipped:
44444+ */
44445+ if (dev_priv->current_page == 0) {
44446+ OUT_RING(dev_priv->back_pitch_offset_c);
44447+ OUT_RING(dev_priv->front_pitch_offset_c);
44448+ } else {
44449+ OUT_RING(dev_priv->front_pitch_offset_c);
44450+ OUT_RING(dev_priv->back_pitch_offset_c);
44451+ }
44452+
44453+ OUT_RING((x << 16) | y);
44454+ OUT_RING((x << 16) | y);
44455+ OUT_RING((w << 16) | h);
44456+
44457+ ADVANCE_RING();
44458+ }
44459+
44460+ /* Increment the frame counter. The client-side 3D driver must
44461+ * throttle the framerate by waiting for this value before
44462+ * performing the swapbuffer ioctl.
44463+ */
44464+ dev_priv->sarea_priv->last_frame++;
44465+
44466+ BEGIN_RING(2);
44467+
44468+ OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
44469+ OUT_RING(dev_priv->sarea_priv->last_frame);
44470+
44471+ ADVANCE_RING();
44472+}
44473+
44474+static void r128_cce_dispatch_flip(struct drm_device * dev)
44475+{
44476+ drm_r128_private_t *dev_priv = dev->dev_private;
44477+ RING_LOCALS;
44478+ DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
44479+ __FUNCTION__,
44480+ dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
44481+
44482+#if R128_PERFORMANCE_BOXES
44483+ /* Do some trivial performance monitoring...
44484+ */
44485+ r128_cce_performance_boxes(dev_priv);
44486+#endif
44487+
44488+ BEGIN_RING(4);
44489+
44490+ R128_WAIT_UNTIL_PAGE_FLIPPED();
44491+ OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
44492+
44493+ if (dev_priv->current_page == 0) {
44494+ OUT_RING(dev_priv->back_offset);
44495+ } else {
44496+ OUT_RING(dev_priv->front_offset);
44497+ }
44498+
44499+ ADVANCE_RING();
44500+
44501+ /* Increment the frame counter. The client-side 3D driver must
44502+ * throttle the framerate by waiting for this value before
44503+ * performing the swapbuffer ioctl.
44504+ */
44505+ dev_priv->sarea_priv->last_frame++;
44506+ dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
44507+ 1 - dev_priv->current_page;
44508+
44509+ BEGIN_RING(2);
44510+
44511+ OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
44512+ OUT_RING(dev_priv->sarea_priv->last_frame);
44513+
44514+ ADVANCE_RING();
44515+}
44516+
44517+static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf)
44518+{
44519+ drm_r128_private_t *dev_priv = dev->dev_private;
44520+ drm_r128_buf_priv_t *buf_priv = buf->dev_private;
44521+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44522+ int format = sarea_priv->vc_format;
44523+ int offset = buf->bus_address;
44524+ int size = buf->used;
44525+ int prim = buf_priv->prim;
44526+ int i = 0;
44527+ RING_LOCALS;
44528+ DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
44529+
44530+ if (0)
44531+ r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
44532+
44533+ if (buf->used) {
44534+ buf_priv->dispatched = 1;
44535+
44536+ if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
44537+ r128_emit_state(dev_priv);
44538+ }
44539+
44540+ do {
44541+ /* Emit the next set of up to three cliprects */
44542+ if (i < sarea_priv->nbox) {
44543+ r128_emit_clip_rects(dev_priv,
44544+ &sarea_priv->boxes[i],
44545+ sarea_priv->nbox - i);
44546+ }
44547+
44548+ /* Emit the vertex buffer rendering commands */
44549+ BEGIN_RING(5);
44550+
44551+ OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
44552+ OUT_RING(offset);
44553+ OUT_RING(size);
44554+ OUT_RING(format);
44555+ OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
44556+ (size << R128_CCE_VC_CNTL_NUM_SHIFT));
44557+
44558+ ADVANCE_RING();
44559+
44560+ i += 3;
44561+ } while (i < sarea_priv->nbox);
44562+ }
44563+
44564+ if (buf_priv->discard) {
44565+ buf_priv->age = dev_priv->sarea_priv->last_dispatch;
44566+
44567+ /* Emit the vertex buffer age */
44568+ BEGIN_RING(2);
44569+
44570+ OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
44571+ OUT_RING(buf_priv->age);
44572+
44573+ ADVANCE_RING();
44574+
44575+ buf->pending = 1;
44576+ buf->used = 0;
44577+ /* FIXME: Check dispatched field */
44578+ buf_priv->dispatched = 0;
44579+ }
44580+
44581+ dev_priv->sarea_priv->last_dispatch++;
44582+
44583+ sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
44584+ sarea_priv->nbox = 0;
44585+}
44586+
44587+static void r128_cce_dispatch_indirect(struct drm_device * dev,
44588+ struct drm_buf * buf, int start, int end)
44589+{
44590+ drm_r128_private_t *dev_priv = dev->dev_private;
44591+ drm_r128_buf_priv_t *buf_priv = buf->dev_private;
44592+ RING_LOCALS;
44593+ DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
44594+
44595+ if (start != end) {
44596+ int offset = buf->bus_address + start;
44597+ int dwords = (end - start + 3) / sizeof(u32);
44598+
44599+ /* Indirect buffer data must be an even number of
44600+ * dwords, so if we've been given an odd number we must
44601+ * pad the data with a Type-2 CCE packet.
44602+ */
44603+ if (dwords & 1) {
44604+ u32 *data = (u32 *)
44605+ ((char *)dev->agp_buffer_map->handle
44606+ + buf->offset + start);
44607+ data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
44608+ }
44609+
44610+ buf_priv->dispatched = 1;
44611+
44612+ /* Fire off the indirect buffer */
44613+ BEGIN_RING(3);
44614+
44615+ OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
44616+ OUT_RING(offset);
44617+ OUT_RING(dwords);
44618+
44619+ ADVANCE_RING();
44620+ }
44621+
44622+ if (buf_priv->discard) {
44623+ buf_priv->age = dev_priv->sarea_priv->last_dispatch;
44624+
44625+ /* Emit the indirect buffer age */
44626+ BEGIN_RING(2);
44627+
44628+ OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
44629+ OUT_RING(buf_priv->age);
44630+
44631+ ADVANCE_RING();
44632+
44633+ buf->pending = 1;
44634+ buf->used = 0;
44635+ /* FIXME: Check dispatched field */
44636+ buf_priv->dispatched = 0;
44637+ }
44638+
44639+ dev_priv->sarea_priv->last_dispatch++;
44640+}
44641+
44642+static void r128_cce_dispatch_indices(struct drm_device * dev,
44643+ struct drm_buf * buf,
44644+ int start, int end, int count)
44645+{
44646+ drm_r128_private_t *dev_priv = dev->dev_private;
44647+ drm_r128_buf_priv_t *buf_priv = buf->dev_private;
44648+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
44649+ int format = sarea_priv->vc_format;
44650+ int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
44651+ int prim = buf_priv->prim;
44652+ u32 *data;
44653+ int dwords;
44654+ int i = 0;
44655+ RING_LOCALS;
44656+ DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
44657+
44658+ if (0)
44659+ r128_print_dirty("dispatch_indices", sarea_priv->dirty);
44660+
44661+ if (start != end) {
44662+ buf_priv->dispatched = 1;
44663+
44664+ if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
44665+ r128_emit_state(dev_priv);
44666+ }
44667+
44668+ dwords = (end - start + 3) / sizeof(u32);
44669+
44670+ data = (u32 *) ((char *)dev->agp_buffer_map->handle
44671+ + buf->offset + start);
44672+
44673+ data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
44674+ dwords - 2));
44675+
44676+ data[1] = cpu_to_le32(offset);
44677+ data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
44678+ data[3] = cpu_to_le32(format);
44679+ data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
44680+ (count << 16)));
44681+
44682+ if (count & 0x1) {
44683+#ifdef __LITTLE_ENDIAN
44684+ data[dwords - 1] &= 0x0000ffff;
44685+#else
44686+ data[dwords - 1] &= 0xffff0000;
44687+#endif
44688+ }
44689+
44690+ do {
44691+ /* Emit the next set of up to three cliprects */
44692+ if (i < sarea_priv->nbox) {
44693+ r128_emit_clip_rects(dev_priv,
44694+ &sarea_priv->boxes[i],
44695+ sarea_priv->nbox - i);
44696+ }
44697+
44698+ r128_cce_dispatch_indirect(dev, buf, start, end);
44699+
44700+ i += 3;
44701+ } while (i < sarea_priv->nbox);
44702+ }
44703+
44704+ if (buf_priv->discard) {
44705+ buf_priv->age = dev_priv->sarea_priv->last_dispatch;
44706+
44707+ /* Emit the vertex buffer age */
44708+ BEGIN_RING(2);
44709+
44710+ OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
44711+ OUT_RING(buf_priv->age);
44712+
44713+ ADVANCE_RING();
44714+
44715+ buf->pending = 1;
44716+ /* FIXME: Check dispatched field */
44717+ buf_priv->dispatched = 0;
44718+ }
44719+
44720+ dev_priv->sarea_priv->last_dispatch++;
44721+
44722+ sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
44723+ sarea_priv->nbox = 0;
44724+}
44725+
44726+static int r128_cce_dispatch_blit(struct drm_device * dev,
44727+ struct drm_file *file_priv,
44728+ drm_r128_blit_t * blit)
44729+{
44730+ drm_r128_private_t *dev_priv = dev->dev_private;
44731+ struct drm_device_dma *dma = dev->dma;
44732+ struct drm_buf *buf;
44733+ drm_r128_buf_priv_t *buf_priv;
44734+ u32 *data;
44735+ int dword_shift, dwords;
44736+ RING_LOCALS;
44737+ DRM_DEBUG("\n");
44738+
44739+ /* The compiler won't optimize away a division by a variable,
44740+ * even if the only legal values are powers of two. Thus, we'll
44741+ * use a shift instead.
44742+ */
44743+ switch (blit->format) {
44744+ case R128_DATATYPE_ARGB8888:
44745+ dword_shift = 0;
44746+ break;
44747+ case R128_DATATYPE_ARGB1555:
44748+ case R128_DATATYPE_RGB565:
44749+ case R128_DATATYPE_ARGB4444:
44750+ case R128_DATATYPE_YVYU422:
44751+ case R128_DATATYPE_VYUY422:
44752+ dword_shift = 1;
44753+ break;
44754+ case R128_DATATYPE_CI8:
44755+ case R128_DATATYPE_RGB8:
44756+ dword_shift = 2;
44757+ break;
44758+ default:
44759+ DRM_ERROR("invalid blit format %d\n", blit->format);
44760+ return -EINVAL;
44761+ }
44762+
44763+ /* Flush the pixel cache, and mark the contents as Read Invalid.
44764+ * This ensures no pixel data gets mixed up with the texture
44765+ * data from the host data blit, otherwise part of the texture
44766+ * image may be corrupted.
44767+ */
44768+ BEGIN_RING(2);
44769+
44770+ OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
44771+ OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
44772+
44773+ ADVANCE_RING();
44774+
44775+ /* Dispatch the indirect buffer.
44776+ */
44777+ buf = dma->buflist[blit->idx];
44778+ buf_priv = buf->dev_private;
44779+
44780+ if (buf->file_priv != file_priv) {
44781+ DRM_ERROR("process %d using buffer owned by %p\n",
44782+ DRM_CURRENTPID, buf->file_priv);
44783+ return -EINVAL;
44784+ }
44785+ if (buf->pending) {
44786+ DRM_ERROR("sending pending buffer %d\n", blit->idx);
44787+ return -EINVAL;
44788+ }
44789+
44790+ buf_priv->discard = 1;
44791+
44792+ dwords = (blit->width * blit->height) >> dword_shift;
44793+
44794+ data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
44795+
44796+ data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
44797+ data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
44798+ R128_GMC_BRUSH_NONE |
44799+ (blit->format << 8) |
44800+ R128_GMC_SRC_DATATYPE_COLOR |
44801+ R128_ROP3_S |
44802+ R128_DP_SRC_SOURCE_HOST_DATA |
44803+ R128_GMC_CLR_CMP_CNTL_DIS |
44804+ R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
44805+
44806+ data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
44807+ data[3] = cpu_to_le32(0xffffffff);
44808+ data[4] = cpu_to_le32(0xffffffff);
44809+ data[5] = cpu_to_le32((blit->y << 16) | blit->x);
44810+ data[6] = cpu_to_le32((blit->height << 16) | blit->width);
44811+ data[7] = cpu_to_le32(dwords);
44812+
44813+ buf->used = (dwords + 8) * sizeof(u32);
44814+
44815+ r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
44816+
44817+ /* Flush the pixel cache after the blit completes. This ensures
44818+ * the texture data is written out to memory before rendering
44819+ * continues.
44820+ */
44821+ BEGIN_RING(2);
44822+
44823+ OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
44824+ OUT_RING(R128_PC_FLUSH_GUI);
44825+
44826+ ADVANCE_RING();
44827+
44828+ return 0;
44829+}
44830+
44831+/* ================================================================
44832+ * Tiled depth buffer management
44833+ *
44834+ * FIXME: These should all set the destination write mask for when we
44835+ * have hardware stencil support.
44836+ */
44837+
44838+static int r128_cce_dispatch_write_span(struct drm_device * dev,
44839+ drm_r128_depth_t * depth)
44840+{
44841+ drm_r128_private_t *dev_priv = dev->dev_private;
44842+ int count, x, y;
44843+ u32 *buffer;
44844+ u8 *mask;
44845+ int i, buffer_size, mask_size;
44846+ RING_LOCALS;
44847+ DRM_DEBUG("\n");
44848+
44849+ count = depth->n;
44850+ if (count > 4096 || count <= 0)
44851+ return -EMSGSIZE;
44852+
44853+ if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
44854+ return -EFAULT;
44855+ }
44856+ if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
44857+ return -EFAULT;
44858+ }
44859+
44860+ buffer_size = depth->n * sizeof(u32);
44861+ buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
44862+ if (buffer == NULL)
44863+ return -ENOMEM;
44864+ if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
44865+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44866+ return -EFAULT;
44867+ }
44868+
44869+ mask_size = depth->n * sizeof(u8);
44870+ if (depth->mask) {
44871+ mask = drm_alloc(mask_size, DRM_MEM_BUFS);
44872+ if (mask == NULL) {
44873+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44874+ return -ENOMEM;
44875+ }
44876+ if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
44877+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44878+ drm_free(mask, mask_size, DRM_MEM_BUFS);
44879+ return -EFAULT;
44880+ }
44881+
44882+ for (i = 0; i < count; i++, x++) {
44883+ if (mask[i]) {
44884+ BEGIN_RING(6);
44885+
44886+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44887+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44888+ R128_GMC_BRUSH_SOLID_COLOR |
44889+ (dev_priv->depth_fmt << 8) |
44890+ R128_GMC_SRC_DATATYPE_COLOR |
44891+ R128_ROP3_P |
44892+ R128_GMC_CLR_CMP_CNTL_DIS |
44893+ R128_GMC_WR_MSK_DIS);
44894+
44895+ OUT_RING(dev_priv->depth_pitch_offset_c);
44896+ OUT_RING(buffer[i]);
44897+
44898+ OUT_RING((x << 16) | y);
44899+ OUT_RING((1 << 16) | 1);
44900+
44901+ ADVANCE_RING();
44902+ }
44903+ }
44904+
44905+ drm_free(mask, mask_size, DRM_MEM_BUFS);
44906+ } else {
44907+ for (i = 0; i < count; i++, x++) {
44908+ BEGIN_RING(6);
44909+
44910+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
44911+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
44912+ R128_GMC_BRUSH_SOLID_COLOR |
44913+ (dev_priv->depth_fmt << 8) |
44914+ R128_GMC_SRC_DATATYPE_COLOR |
44915+ R128_ROP3_P |
44916+ R128_GMC_CLR_CMP_CNTL_DIS |
44917+ R128_GMC_WR_MSK_DIS);
44918+
44919+ OUT_RING(dev_priv->depth_pitch_offset_c);
44920+ OUT_RING(buffer[i]);
44921+
44922+ OUT_RING((x << 16) | y);
44923+ OUT_RING((1 << 16) | 1);
44924+
44925+ ADVANCE_RING();
44926+ }
44927+ }
44928+
44929+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44930+
44931+ return 0;
44932+}
44933+
44934+static int r128_cce_dispatch_write_pixels(struct drm_device * dev,
44935+ drm_r128_depth_t * depth)
44936+{
44937+ drm_r128_private_t *dev_priv = dev->dev_private;
44938+ int count, *x, *y;
44939+ u32 *buffer;
44940+ u8 *mask;
44941+ int i, xbuf_size, ybuf_size, buffer_size, mask_size;
44942+ RING_LOCALS;
44943+ DRM_DEBUG("\n");
44944+
44945+ count = depth->n;
44946+ if (count > 4096 || count <= 0)
44947+ return -EMSGSIZE;
44948+
44949+ xbuf_size = count * sizeof(*x);
44950+ ybuf_size = count * sizeof(*y);
44951+ x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
44952+ if (x == NULL) {
44953+ return -ENOMEM;
44954+ }
44955+ y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
44956+ if (y == NULL) {
44957+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44958+ return -ENOMEM;
44959+ }
44960+ if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
44961+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44962+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44963+ return -EFAULT;
44964+ }
44965+ if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
44966+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44967+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44968+ return -EFAULT;
44969+ }
44970+
44971+ buffer_size = depth->n * sizeof(u32);
44972+ buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
44973+ if (buffer == NULL) {
44974+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44975+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44976+ return -ENOMEM;
44977+ }
44978+ if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
44979+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44980+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44981+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44982+ return -EFAULT;
44983+ }
44984+
44985+ if (depth->mask) {
44986+ mask_size = depth->n * sizeof(u8);
44987+ mask = drm_alloc(mask_size, DRM_MEM_BUFS);
44988+ if (mask == NULL) {
44989+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44990+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44991+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44992+ return -ENOMEM;
44993+ }
44994+ if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
44995+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
44996+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
44997+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
44998+ drm_free(mask, mask_size, DRM_MEM_BUFS);
44999+ return -EFAULT;
45000+ }
45001+
45002+ for (i = 0; i < count; i++) {
45003+ if (mask[i]) {
45004+ BEGIN_RING(6);
45005+
45006+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
45007+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
45008+ R128_GMC_BRUSH_SOLID_COLOR |
45009+ (dev_priv->depth_fmt << 8) |
45010+ R128_GMC_SRC_DATATYPE_COLOR |
45011+ R128_ROP3_P |
45012+ R128_GMC_CLR_CMP_CNTL_DIS |
45013+ R128_GMC_WR_MSK_DIS);
45014+
45015+ OUT_RING(dev_priv->depth_pitch_offset_c);
45016+ OUT_RING(buffer[i]);
45017+
45018+ OUT_RING((x[i] << 16) | y[i]);
45019+ OUT_RING((1 << 16) | 1);
45020+
45021+ ADVANCE_RING();
45022+ }
45023+ }
45024+
45025+ drm_free(mask, mask_size, DRM_MEM_BUFS);
45026+ } else {
45027+ for (i = 0; i < count; i++) {
45028+ BEGIN_RING(6);
45029+
45030+ OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
45031+ OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
45032+ R128_GMC_BRUSH_SOLID_COLOR |
45033+ (dev_priv->depth_fmt << 8) |
45034+ R128_GMC_SRC_DATATYPE_COLOR |
45035+ R128_ROP3_P |
45036+ R128_GMC_CLR_CMP_CNTL_DIS |
45037+ R128_GMC_WR_MSK_DIS);
45038+
45039+ OUT_RING(dev_priv->depth_pitch_offset_c);
45040+ OUT_RING(buffer[i]);
45041+
45042+ OUT_RING((x[i] << 16) | y[i]);
45043+ OUT_RING((1 << 16) | 1);
45044+
45045+ ADVANCE_RING();
45046+ }
45047+ }
45048+
45049+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
45050+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
45051+ drm_free(buffer, buffer_size, DRM_MEM_BUFS);
45052+
45053+ return 0;
45054+}
45055+
45056+static int r128_cce_dispatch_read_span(struct drm_device * dev,
45057+ drm_r128_depth_t * depth)
45058+{
45059+ drm_r128_private_t *dev_priv = dev->dev_private;
45060+ int count, x, y;
45061+ RING_LOCALS;
45062+ DRM_DEBUG("\n");
45063+
45064+ count = depth->n;
45065+ if (count > 4096 || count <= 0)
45066+ return -EMSGSIZE;
45067+
45068+ if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
45069+ return -EFAULT;
45070+ }
45071+ if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
45072+ return -EFAULT;
45073+ }
45074+
45075+ BEGIN_RING(7);
45076+
45077+ OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
45078+ OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
45079+ R128_GMC_DST_PITCH_OFFSET_CNTL |
45080+ R128_GMC_BRUSH_NONE |
45081+ (dev_priv->depth_fmt << 8) |
45082+ R128_GMC_SRC_DATATYPE_COLOR |
45083+ R128_ROP3_S |
45084+ R128_DP_SRC_SOURCE_MEMORY |
45085+ R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
45086+
45087+ OUT_RING(dev_priv->depth_pitch_offset_c);
45088+ OUT_RING(dev_priv->span_pitch_offset_c);
45089+
45090+ OUT_RING((x << 16) | y);
45091+ OUT_RING((0 << 16) | 0);
45092+ OUT_RING((count << 16) | 1);
45093+
45094+ ADVANCE_RING();
45095+
45096+ return 0;
45097+}
45098+
45099+static int r128_cce_dispatch_read_pixels(struct drm_device * dev,
45100+ drm_r128_depth_t * depth)
45101+{
45102+ drm_r128_private_t *dev_priv = dev->dev_private;
45103+ int count, *x, *y;
45104+ int i, xbuf_size, ybuf_size;
45105+ RING_LOCALS;
45106+ DRM_DEBUG("%s\n", __FUNCTION__);
45107+
45108+ count = depth->n;
45109+ if (count > 4096 || count <= 0)
45110+ return -EMSGSIZE;
45111+
45112+ if (count > dev_priv->depth_pitch) {
45113+ count = dev_priv->depth_pitch;
45114+ }
45115+
45116+ xbuf_size = count * sizeof(*x);
45117+ ybuf_size = count * sizeof(*y);
45118+ x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
45119+ if (x == NULL) {
45120+ return -ENOMEM;
45121+ }
45122+ y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
45123+ if (y == NULL) {
45124+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
45125+ return -ENOMEM;
45126+ }
45127+ if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
45128+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
45129+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
45130+ return -EFAULT;
45131+ }
45132+ if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
45133+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
45134+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
45135+ return -EFAULT;
45136+ }
45137+
45138+ for (i = 0; i < count; i++) {
45139+ BEGIN_RING(7);
45140+
45141+ OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
45142+ OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
45143+ R128_GMC_DST_PITCH_OFFSET_CNTL |
45144+ R128_GMC_BRUSH_NONE |
45145+ (dev_priv->depth_fmt << 8) |
45146+ R128_GMC_SRC_DATATYPE_COLOR |
45147+ R128_ROP3_S |
45148+ R128_DP_SRC_SOURCE_MEMORY |
45149+ R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
45150+
45151+ OUT_RING(dev_priv->depth_pitch_offset_c);
45152+ OUT_RING(dev_priv->span_pitch_offset_c);
45153+
45154+ OUT_RING((x[i] << 16) | y[i]);
45155+ OUT_RING((i << 16) | 0);
45156+ OUT_RING((1 << 16) | 1);
45157+
45158+ ADVANCE_RING();
45159+ }
45160+
45161+ drm_free(x, xbuf_size, DRM_MEM_BUFS);
45162+ drm_free(y, ybuf_size, DRM_MEM_BUFS);
45163+
45164+ return 0;
45165+}
45166+
45167+/* ================================================================
45168+ * Polygon stipple
45169+ */
45170+
45171+static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple)
45172+{
45173+ drm_r128_private_t *dev_priv = dev->dev_private;
45174+ int i;
45175+ RING_LOCALS;
45176+ DRM_DEBUG("%s\n", __FUNCTION__);
45177+
45178+ BEGIN_RING(33);
45179+
45180+ OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
45181+ for (i = 0; i < 32; i++) {
45182+ OUT_RING(stipple[i]);
45183+ }
45184+
45185+ ADVANCE_RING();
45186+}
45187+
45188+/* ================================================================
45189+ * IOCTL functions
45190+ */
45191+
45192+static int r128_cce_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
45193+{
45194+ drm_r128_private_t *dev_priv = dev->dev_private;
45195+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
45196+ drm_r128_clear_t *clear = data;
45197+ DRM_DEBUG("\n");
45198+
45199+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45200+
45201+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45202+
45203+ if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
45204+ sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
45205+
45206+ r128_cce_dispatch_clear(dev, clear);
45207+ COMMIT_RING();
45208+
45209+ /* Make sure we restore the 3D state next time.
45210+ */
45211+ dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
45212+
45213+ return 0;
45214+}
45215+
45216+static int r128_do_init_pageflip(struct drm_device * dev)
45217+{
45218+ drm_r128_private_t *dev_priv = dev->dev_private;
45219+ DRM_DEBUG("\n");
45220+
45221+ dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
45222+ dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
45223+
45224+ R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
45225+ R128_WRITE(R128_CRTC_OFFSET_CNTL,
45226+ dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
45227+
45228+ dev_priv->page_flipping = 1;
45229+ dev_priv->current_page = 0;
45230+ dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
45231+
45232+ return 0;
45233+}
45234+
45235+static int r128_do_cleanup_pageflip(struct drm_device * dev)
45236+{
45237+ drm_r128_private_t *dev_priv = dev->dev_private;
45238+ DRM_DEBUG("\n");
45239+
45240+ R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
45241+ R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
45242+
45243+ if (dev_priv->current_page != 0) {
45244+ r128_cce_dispatch_flip(dev);
45245+ COMMIT_RING();
45246+ }
45247+
45248+ dev_priv->page_flipping = 0;
45249+ return 0;
45250+}
45251+
45252+/* Swapping and flipping are different operations, need different ioctls.
45253+ * They can & should be intermixed to support multiple 3d windows.
45254+ */
45255+
45256+static int r128_cce_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
45257+{
45258+ drm_r128_private_t *dev_priv = dev->dev_private;
45259+ DRM_DEBUG("%s\n", __FUNCTION__);
45260+
45261+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45262+
45263+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45264+
45265+ if (!dev_priv->page_flipping)
45266+ r128_do_init_pageflip(dev);
45267+
45268+ r128_cce_dispatch_flip(dev);
45269+
45270+ COMMIT_RING();
45271+ return 0;
45272+}
45273+
45274+static int r128_cce_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
45275+{
45276+ drm_r128_private_t *dev_priv = dev->dev_private;
45277+ drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
45278+ DRM_DEBUG("%s\n", __FUNCTION__);
45279+
45280+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45281+
45282+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45283+
45284+ if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
45285+ sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
45286+
45287+ r128_cce_dispatch_swap(dev);
45288+ dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
45289+ R128_UPLOAD_MASKS);
45290+
45291+ COMMIT_RING();
45292+ return 0;
45293+}
45294+
45295+static int r128_cce_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
45296+{
45297+ drm_r128_private_t *dev_priv = dev->dev_private;
45298+ struct drm_device_dma *dma = dev->dma;
45299+ struct drm_buf *buf;
45300+ drm_r128_buf_priv_t *buf_priv;
45301+ drm_r128_vertex_t *vertex = data;
45302+
45303+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45304+
45305+ if (!dev_priv) {
45306+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
45307+ return -EINVAL;
45308+ }
45309+
45310+ DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
45311+ DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
45312+
45313+ if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
45314+ DRM_ERROR("buffer index %d (of %d max)\n",
45315+ vertex->idx, dma->buf_count - 1);
45316+ return -EINVAL;
45317+ }
45318+ if (vertex->prim < 0 ||
45319+ vertex->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
45320+ DRM_ERROR("buffer prim %d\n", vertex->prim);
45321+ return -EINVAL;
45322+ }
45323+
45324+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45325+ VB_AGE_TEST_WITH_RETURN(dev_priv);
45326+
45327+ buf = dma->buflist[vertex->idx];
45328+ buf_priv = buf->dev_private;
45329+
45330+ if (buf->file_priv != file_priv) {
45331+ DRM_ERROR("process %d using buffer owned by %p\n",
45332+ DRM_CURRENTPID, buf->file_priv);
45333+ return -EINVAL;
45334+ }
45335+ if (buf->pending) {
45336+ DRM_ERROR("sending pending buffer %d\n", vertex->idx);
45337+ return -EINVAL;
45338+ }
45339+
45340+ buf->used = vertex->count;
45341+ buf_priv->prim = vertex->prim;
45342+ buf_priv->discard = vertex->discard;
45343+
45344+ r128_cce_dispatch_vertex(dev, buf);
45345+
45346+ COMMIT_RING();
45347+ return 0;
45348+}
45349+
45350+static int r128_cce_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
45351+{
45352+ drm_r128_private_t *dev_priv = dev->dev_private;
45353+ struct drm_device_dma *dma = dev->dma;
45354+ struct drm_buf *buf;
45355+ drm_r128_buf_priv_t *buf_priv;
45356+ drm_r128_indices_t *elts = data;
45357+ int count;
45358+
45359+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45360+
45361+ if (!dev_priv) {
45362+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
45363+ return -EINVAL;
45364+ }
45365+
45366+ DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
45367+ elts->idx, elts->start, elts->end, elts->discard);
45368+
45369+ if (elts->idx < 0 || elts->idx >= dma->buf_count) {
45370+ DRM_ERROR("buffer index %d (of %d max)\n",
45371+ elts->idx, dma->buf_count - 1);
45372+ return -EINVAL;
45373+ }
45374+ if (elts->prim < 0 ||
45375+ elts->prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
45376+ DRM_ERROR("buffer prim %d\n", elts->prim);
45377+ return -EINVAL;
45378+ }
45379+
45380+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45381+ VB_AGE_TEST_WITH_RETURN(dev_priv);
45382+
45383+ buf = dma->buflist[elts->idx];
45384+ buf_priv = buf->dev_private;
45385+
45386+ if (buf->file_priv != file_priv) {
45387+ DRM_ERROR("process %d using buffer owned by %p\n",
45388+ DRM_CURRENTPID, buf->file_priv);
45389+ return -EINVAL;
45390+ }
45391+ if (buf->pending) {
45392+ DRM_ERROR("sending pending buffer %d\n", elts->idx);
45393+ return -EINVAL;
45394+ }
45395+
45396+ count = (elts->end - elts->start) / sizeof(u16);
45397+ elts->start -= R128_INDEX_PRIM_OFFSET;
45398+
45399+ if (elts->start & 0x7) {
45400+ DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
45401+ return -EINVAL;
45402+ }
45403+ if (elts->start < buf->used) {
45404+ DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
45405+ return -EINVAL;
45406+ }
45407+
45408+ buf->used = elts->end;
45409+ buf_priv->prim = elts->prim;
45410+ buf_priv->discard = elts->discard;
45411+
45412+ r128_cce_dispatch_indices(dev, buf, elts->start, elts->end, count);
45413+
45414+ COMMIT_RING();
45415+ return 0;
45416+}
45417+
45418+static int r128_cce_blit(struct drm_device *dev, void *data, struct drm_file *file_priv)
45419+{
45420+ struct drm_device_dma *dma = dev->dma;
45421+ drm_r128_private_t *dev_priv = dev->dev_private;
45422+ drm_r128_blit_t *blit = data;
45423+ int ret;
45424+
45425+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45426+
45427+ DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit->idx);
45428+
45429+ if (blit->idx < 0 || blit->idx >= dma->buf_count) {
45430+ DRM_ERROR("buffer index %d (of %d max)\n",
45431+ blit->idx, dma->buf_count - 1);
45432+ return -EINVAL;
45433+ }
45434+
45435+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45436+ VB_AGE_TEST_WITH_RETURN(dev_priv);
45437+
45438+ ret = r128_cce_dispatch_blit(dev, file_priv, blit);
45439+
45440+ COMMIT_RING();
45441+ return ret;
45442+}
45443+
45444+static int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv)
45445+{
45446+ drm_r128_private_t *dev_priv = dev->dev_private;
45447+ drm_r128_depth_t *depth = data;
45448+ int ret;
45449+
45450+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45451+
45452+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45453+
45454+ ret = -EINVAL;
45455+ switch (depth->func) {
45456+ case R128_WRITE_SPAN:
45457+ ret = r128_cce_dispatch_write_span(dev, depth);
45458+ break;
45459+ case R128_WRITE_PIXELS:
45460+ ret = r128_cce_dispatch_write_pixels(dev, depth);
45461+ break;
45462+ case R128_READ_SPAN:
45463+ ret = r128_cce_dispatch_read_span(dev, depth);
45464+ break;
45465+ case R128_READ_PIXELS:
45466+ ret = r128_cce_dispatch_read_pixels(dev, depth);
45467+ break;
45468+ }
45469+
45470+ COMMIT_RING();
45471+ return ret;
45472+}
45473+
45474+static int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
45475+{
45476+ drm_r128_private_t *dev_priv = dev->dev_private;
45477+ drm_r128_stipple_t *stipple = data;
45478+ u32 mask[32];
45479+
45480+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45481+
45482+ if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
45483+ return -EFAULT;
45484+
45485+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45486+
45487+ r128_cce_dispatch_stipple(dev, mask);
45488+
45489+ COMMIT_RING();
45490+ return 0;
45491+}
45492+
45493+static int r128_cce_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
45494+{
45495+ drm_r128_private_t *dev_priv = dev->dev_private;
45496+ struct drm_device_dma *dma = dev->dma;
45497+ struct drm_buf *buf;
45498+ drm_r128_buf_priv_t *buf_priv;
45499+ drm_r128_indirect_t *indirect = data;
45500+#if 0
45501+ RING_LOCALS;
45502+#endif
45503+
45504+ LOCK_TEST_WITH_RETURN(dev, file_priv);
45505+
45506+ if (!dev_priv) {
45507+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
45508+ return -EINVAL;
45509+ }
45510+
45511+ DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
45512+ indirect->idx, indirect->start, indirect->end,
45513+ indirect->discard);
45514+
45515+ if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
45516+ DRM_ERROR("buffer index %d (of %d max)\n",
45517+ indirect->idx, dma->buf_count - 1);
45518+ return -EINVAL;
45519+ }
45520+
45521+ buf = dma->buflist[indirect->idx];
45522+ buf_priv = buf->dev_private;
45523+
45524+ if (buf->file_priv != file_priv) {
45525+ DRM_ERROR("process %d using buffer owned by %p\n",
45526+ DRM_CURRENTPID, buf->file_priv);
45527+ return -EINVAL;
45528+ }
45529+ if (buf->pending) {
45530+ DRM_ERROR("sending pending buffer %d\n", indirect->idx);
45531+ return -EINVAL;
45532+ }
45533+
45534+ if (indirect->start < buf->used) {
45535+ DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
45536+ indirect->start, buf->used);
45537+ return -EINVAL;
45538+ }
45539+
45540+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
45541+ VB_AGE_TEST_WITH_RETURN(dev_priv);
45542+
45543+ buf->used = indirect->end;
45544+ buf_priv->discard = indirect->discard;
45545+
45546+#if 0
45547+ /* Wait for the 3D stream to idle before the indirect buffer
45548+ * containing 2D acceleration commands is processed.
45549+ */
45550+ BEGIN_RING(2);
45551+ RADEON_WAIT_UNTIL_3D_IDLE();
45552+ ADVANCE_RING();
45553+#endif
45554+
45555+ /* Dispatch the indirect buffer full of commands from the
45556+ * X server. This is insecure and is thus only available to
45557+ * privileged clients.
45558+ */
45559+ r128_cce_dispatch_indirect(dev, buf, indirect->start, indirect->end);
45560+
45561+ COMMIT_RING();
45562+ return 0;
45563+}
45564+
45565+static int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
45566+{
45567+ drm_r128_private_t *dev_priv = dev->dev_private;
45568+ drm_r128_getparam_t *param = data;
45569+ int value;
45570+
45571+ if (!dev_priv) {
45572+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
45573+ return -EINVAL;
45574+ }
45575+
45576+ DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
45577+
45578+ switch (param->param) {
45579+ case R128_PARAM_IRQ_NR:
45580+ value = dev->irq;
45581+ break;
45582+ default:
45583+ return -EINVAL;
45584+ }
45585+
45586+ if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
45587+ DRM_ERROR("copy_to_user\n");
45588+ return -EFAULT;
45589+ }
45590+
45591+ return 0;
45592+}
45593+
45594+void r128_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
45595+{
45596+ if (dev->dev_private) {
45597+ drm_r128_private_t *dev_priv = dev->dev_private;
45598+ if (dev_priv->page_flipping) {
45599+ r128_do_cleanup_pageflip(dev);
45600+ }
45601+ }
45602+}
45603+
45604+void r128_driver_lastclose(struct drm_device * dev)
45605+{
45606+ r128_do_cleanup_cce(dev);
45607+}
45608+
45609+struct drm_ioctl_desc r128_ioctls[] = {
45610+ DRM_IOCTL_DEF(DRM_R128_INIT, r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45611+ DRM_IOCTL_DEF(DRM_R128_CCE_START, r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45612+ DRM_IOCTL_DEF(DRM_R128_CCE_STOP, r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45613+ DRM_IOCTL_DEF(DRM_R128_CCE_RESET, r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45614+ DRM_IOCTL_DEF(DRM_R128_CCE_IDLE, r128_cce_idle, DRM_AUTH),
45615+ DRM_IOCTL_DEF(DRM_R128_RESET, r128_engine_reset, DRM_AUTH),
45616+ DRM_IOCTL_DEF(DRM_R128_FULLSCREEN, r128_fullscreen, DRM_AUTH),
45617+ DRM_IOCTL_DEF(DRM_R128_SWAP, r128_cce_swap, DRM_AUTH),
45618+ DRM_IOCTL_DEF(DRM_R128_FLIP, r128_cce_flip, DRM_AUTH),
45619+ DRM_IOCTL_DEF(DRM_R128_CLEAR, r128_cce_clear, DRM_AUTH),
45620+ DRM_IOCTL_DEF(DRM_R128_VERTEX, r128_cce_vertex, DRM_AUTH),
45621+ DRM_IOCTL_DEF(DRM_R128_INDICES, r128_cce_indices, DRM_AUTH),
45622+ DRM_IOCTL_DEF(DRM_R128_BLIT, r128_cce_blit, DRM_AUTH),
45623+ DRM_IOCTL_DEF(DRM_R128_DEPTH, r128_cce_depth, DRM_AUTH),
45624+ DRM_IOCTL_DEF(DRM_R128_STIPPLE, r128_cce_stipple, DRM_AUTH),
45625+ DRM_IOCTL_DEF(DRM_R128_INDIRECT, r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
45626+ DRM_IOCTL_DEF(DRM_R128_GETPARAM, r128_getparam, DRM_AUTH),
45627+};
45628+
45629+int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
45630Index: git/shared-core/r300_cmdbuf.c
45631===================================================================
45632--- /dev/null 1970-01-01 00:00:00.000000000 +0000
45633+++ git/shared-core/r300_cmdbuf.c 2008-12-12 17:35:22.000000000 +0000
45634@@ -0,0 +1,954 @@
45635+/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
45636+ *
45637+ * Copyright (C) The Weather Channel, Inc. 2002.
45638+ * Copyright (C) 2004 Nicolai Haehnle.
45639+ * All Rights Reserved.
45640+ *
45641+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
45642+ * initial release of the Radeon 8500 driver under the XFree86 license.
45643+ * This notice must be preserved.
45644+ *
45645+ * Permission is hereby granted, free of charge, to any person obtaining a
45646+ * copy of this software and associated documentation files (the "Software"),
45647+ * to deal in the Software without restriction, including without limitation
45648+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
45649+ * and/or sell copies of the Software, and to permit persons to whom the
45650+ * Software is furnished to do so, subject to the following conditions:
45651+ *
45652+ * The above copyright notice and this permission notice (including the next
45653+ * paragraph) shall be included in all copies or substantial portions of the
45654+ * Software.
45655+ *
45656+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45657+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
45658+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
45659+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
45660+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
45661+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
45662+ * DEALINGS IN THE SOFTWARE.
45663+ *
45664+ * Authors:
45665+ * Nicolai Haehnle <prefect_@gmx.net>
45666+ */
45667+
45668+#include "drmP.h"
45669+#include "drm.h"
45670+#include "radeon_drm.h"
45671+#include "radeon_drv.h"
45672+#include "r300_reg.h"
45673+
45674+#define R300_SIMULTANEOUS_CLIPRECTS 4
45675+
45676+/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
45677+ */
45678+static const int r300_cliprect_cntl[4] = {
45679+ 0xAAAA,
45680+ 0xEEEE,
45681+ 0xFEFE,
45682+ 0xFFFE
45683+};
45684+
45685+/**
45686+ * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
45687+ * buffer, starting with index n.
45688+ */
45689+static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
45690+ drm_radeon_kcmd_buffer_t *cmdbuf, int n)
45691+{
45692+ struct drm_clip_rect box;
45693+ int nr;
45694+ int i;
45695+ RING_LOCALS;
45696+
45697+ nr = cmdbuf->nbox - n;
45698+ if (nr > R300_SIMULTANEOUS_CLIPRECTS)
45699+ nr = R300_SIMULTANEOUS_CLIPRECTS;
45700+
45701+ DRM_DEBUG("%i cliprects\n", nr);
45702+
45703+ if (nr) {
45704+ BEGIN_RING(6 + nr * 2);
45705+ OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
45706+
45707+ for (i = 0; i < nr; ++i) {
45708+ if (DRM_COPY_FROM_USER_UNCHECKED
45709+ (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
45710+ DRM_ERROR("copy cliprect faulted\n");
45711+ return -EFAULT;
45712+ }
45713+
45714+ box.x1 =
45715+ (box.x1 +
45716+ R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
45717+ box.y1 =
45718+ (box.y1 +
45719+ R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
45720+ box.x2 =
45721+ (box.x2 +
45722+ R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
45723+ box.y2 =
45724+ (box.y2 +
45725+ R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
45726+
45727+ OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
45728+ (box.y1 << R300_CLIPRECT_Y_SHIFT));
45729+ OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
45730+ (box.y2 << R300_CLIPRECT_Y_SHIFT));
45731+ }
45732+
45733+ OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
45734+
45735+ /* TODO/SECURITY: Force scissors to a safe value, otherwise the
45736+ * client might be able to trample over memory.
45737+ * The impact should be very limited, but I'd rather be safe than
45738+ * sorry.
45739+ */
45740+ OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
45741+ OUT_RING(0);
45742+ OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
45743+ ADVANCE_RING();
45744+ } else {
45745+ /* Why we allow zero cliprect rendering:
45746+ * There are some commands in a command buffer that must be submitted
45747+ * even when there are no cliprects, e.g. DMA buffer discard
45748+ * or state setting (though state setting could be avoided by
45749+ * simulating a loss of context).
45750+ *
45751+ * Now since the cmdbuf interface is so chaotic right now (and is
45752+ * bound to remain that way for a bit until things settle down),
45753+ * it is basically impossible to filter out the commands that are
45754+ * necessary and those that aren't.
45755+ *
45756+ * So I choose the safe way and don't do any filtering at all;
45757+ * instead, I simply set up the engine so that all rendering
45758+ * can't produce any fragments.
45759+ */
45760+ BEGIN_RING(2);
45761+ OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
45762+ ADVANCE_RING();
45763+ }
45764+
45765+ return 0;
45766+}
45767+
45768+static u8 r300_reg_flags[0x10000 >> 2];
45769+
45770+void r300_init_reg_flags(void)
45771+{
45772+ int i;
45773+ memset(r300_reg_flags, 0, 0x10000 >> 2);
45774+#define ADD_RANGE_MARK(reg, count,mark) \
45775+ for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
45776+ r300_reg_flags[i]|=(mark);
45777+
45778+#define MARK_SAFE 1
45779+#define MARK_CHECK_OFFSET 2
45780+
45781+#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
45782+
45783+ /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
45784+ ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
45785+ ADD_RANGE(R300_VAP_CNTL, 1);
45786+ ADD_RANGE(R300_SE_VTE_CNTL, 2);
45787+ ADD_RANGE(0x2134, 2);
45788+ ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
45789+ ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
45790+ ADD_RANGE(0x21DC, 1);
45791+ ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
45792+ ADD_RANGE(R300_VAP_CLIP_X_0, 4);
45793+ ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
45794+ ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
45795+ ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
45796+ ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
45797+ ADD_RANGE(R300_GB_ENABLE, 1);
45798+ ADD_RANGE(R300_GB_MSPOS0, 5);
45799+ ADD_RANGE(R300_TX_CNTL, 1);
45800+ ADD_RANGE(R300_TX_ENABLE, 1);
45801+ ADD_RANGE(0x4200, 4);
45802+ ADD_RANGE(0x4214, 1);
45803+ ADD_RANGE(R300_RE_POINTSIZE, 1);
45804+ ADD_RANGE(0x4230, 3);
45805+ ADD_RANGE(R300_RE_LINE_CNT, 1);
45806+ ADD_RANGE(R300_RE_UNK4238, 1);
45807+ ADD_RANGE(0x4260, 3);
45808+ ADD_RANGE(R300_RE_SHADE, 4);
45809+ ADD_RANGE(R300_RE_POLYGON_MODE, 5);
45810+ ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
45811+ ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
45812+ ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
45813+ ADD_RANGE(R300_RE_CULL_CNTL, 1);
45814+ ADD_RANGE(0x42C0, 2);
45815+ ADD_RANGE(R300_RS_CNTL_0, 2);
45816+ ADD_RANGE(R300_RS_INTERP_0, 8);
45817+ ADD_RANGE(R300_RS_ROUTE_0, 8);
45818+ ADD_RANGE(0x43A4, 2);
45819+ ADD_RANGE(0x43E8, 1);
45820+ ADD_RANGE(R300_PFS_CNTL_0, 3);
45821+ ADD_RANGE(R300_PFS_NODE_0, 4);
45822+ ADD_RANGE(R300_PFS_TEXI_0, 64);
45823+ ADD_RANGE(0x46A4, 5);
45824+ ADD_RANGE(R300_PFS_INSTR0_0, 64);
45825+ ADD_RANGE(R300_PFS_INSTR1_0, 64);
45826+ ADD_RANGE(R300_PFS_INSTR2_0, 64);
45827+ ADD_RANGE(R300_PFS_INSTR3_0, 64);
45828+ ADD_RANGE(R300_RE_FOG_STATE, 1);
45829+ ADD_RANGE(R300_FOG_COLOR_R, 3);
45830+ ADD_RANGE(R300_PP_ALPHA_TEST, 2);
45831+ ADD_RANGE(0x4BD8, 1);
45832+ ADD_RANGE(R300_PFS_PARAM_0_X, 64);
45833+ ADD_RANGE(0x4E00, 1);
45834+ ADD_RANGE(R300_RB3D_CBLEND, 2);
45835+ ADD_RANGE(R300_RB3D_COLORMASK, 1);
45836+ ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
45837+ ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
45838+ ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
45839+ ADD_RANGE(0x4E50, 9);
45840+ ADD_RANGE(0x4E88, 1);
45841+ ADD_RANGE(0x4EA0, 2);
45842+ ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
45843+ ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
45844+ ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
45845+ ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
45846+ ADD_RANGE(0x4F28, 1);
45847+ ADD_RANGE(0x4F30, 2);
45848+ ADD_RANGE(0x4F44, 1);
45849+ ADD_RANGE(0x4F54, 1);
45850+
45851+ ADD_RANGE(R300_TX_FILTER_0, 16);
45852+ ADD_RANGE(R300_TX_FILTER1_0, 16);
45853+ ADD_RANGE(R300_TX_SIZE_0, 16);
45854+ ADD_RANGE(R300_TX_FORMAT_0, 16);
45855+ ADD_RANGE(R300_TX_PITCH_0, 16);
45856+ /* Texture offset is dangerous and needs more checking */
45857+ ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
45858+ ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
45859+ ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
45860+
45861+ /* Sporadic registers used as primitives are emitted */
45862+ ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
45863+ ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
45864+ ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
45865+ ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
45866+
45867+}
45868+
45869+static __inline__ int r300_check_range(unsigned reg, int count)
45870+{
45871+ int i;
45872+ if (reg & ~0xffff)
45873+ return -1;
45874+ for (i = (reg >> 2); i < (reg >> 2) + count; i++)
45875+ if (r300_reg_flags[i] != MARK_SAFE)
45876+ return 1;
45877+ return 0;
45878+}
45879+
45880+static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
45881+ dev_priv,
45882+ drm_radeon_kcmd_buffer_t
45883+ * cmdbuf,
45884+ drm_r300_cmd_header_t
45885+ header)
45886+{
45887+ int reg;
45888+ int sz;
45889+ int i;
45890+ int values[64];
45891+ RING_LOCALS;
45892+
45893+ sz = header.packet0.count;
45894+ reg = (header.packet0.reghi << 8) | header.packet0.reglo;
45895+
45896+ if ((sz > 64) || (sz < 0)) {
45897+ DRM_ERROR
45898+ ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
45899+ reg, sz);
45900+ return -EINVAL;
45901+ }
45902+ for (i = 0; i < sz; i++) {
45903+ values[i] = ((int *)cmdbuf->buf)[i];
45904+ switch (r300_reg_flags[(reg >> 2) + i]) {
45905+ case MARK_SAFE:
45906+ break;
45907+ case MARK_CHECK_OFFSET:
45908+ if (!radeon_check_offset(dev_priv, (u32) values[i])) {
45909+ DRM_ERROR
45910+ ("Offset failed range check (reg=%04x sz=%d)\n",
45911+ reg, sz);
45912+ return -EINVAL;
45913+ }
45914+ break;
45915+ default:
45916+ DRM_ERROR("Register %04x failed check as flag=%02x\n",
45917+ reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
45918+ return -EINVAL;
45919+ }
45920+ }
45921+
45922+ BEGIN_RING(1 + sz);
45923+ OUT_RING(CP_PACKET0(reg, sz - 1));
45924+ OUT_RING_TABLE(values, sz);
45925+ ADVANCE_RING();
45926+
45927+ cmdbuf->buf += sz * 4;
45928+ cmdbuf->bufsz -= sz * 4;
45929+
45930+ return 0;
45931+}
45932+
45933+/**
45934+ * Emits a packet0 setting arbitrary registers.
45935+ * Called by r300_do_cp_cmdbuf.
45936+ *
45937+ * Note that checks are performed on contents and addresses of the registers
45938+ */
45939+static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
45940+ drm_radeon_kcmd_buffer_t *cmdbuf,
45941+ drm_r300_cmd_header_t header)
45942+{
45943+ int reg;
45944+ int sz;
45945+ RING_LOCALS;
45946+
45947+ sz = header.packet0.count;
45948+ reg = (header.packet0.reghi << 8) | header.packet0.reglo;
45949+
45950+ if (!sz)
45951+ return 0;
45952+
45953+ if (sz * 4 > cmdbuf->bufsz)
45954+ return -EINVAL;
45955+
45956+ if (reg + sz * 4 >= 0x10000) {
45957+ DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
45958+ sz);
45959+ return -EINVAL;
45960+ }
45961+
45962+ if (r300_check_range(reg, sz)) {
45963+ /* go and check everything */
45964+ return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
45965+ header);
45966+ }
45967+ /* the rest of the data is safe to emit, whatever the values the user passed */
45968+
45969+ BEGIN_RING(1 + sz);
45970+ OUT_RING(CP_PACKET0(reg, sz - 1));
45971+ OUT_RING_TABLE((int *)cmdbuf->buf, sz);
45972+ ADVANCE_RING();
45973+
45974+ cmdbuf->buf += sz * 4;
45975+ cmdbuf->bufsz -= sz * 4;
45976+
45977+ return 0;
45978+}
45979+
45980+/**
45981+ * Uploads user-supplied vertex program instructions or parameters onto
45982+ * the graphics card.
45983+ * Called by r300_do_cp_cmdbuf.
45984+ */
45985+static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
45986+ drm_radeon_kcmd_buffer_t *cmdbuf,
45987+ drm_r300_cmd_header_t header)
45988+{
45989+ int sz;
45990+ int addr;
45991+ RING_LOCALS;
45992+
45993+ sz = header.vpu.count;
45994+ addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
45995+
45996+ if (!sz)
45997+ return 0;
45998+ if (sz * 16 > cmdbuf->bufsz)
45999+ return -EINVAL;
46000+
46001+ BEGIN_RING(5 + sz * 4);
46002+ /* Wait for VAP to come to senses.. */
46003+ /* there is no need to emit it multiple times, (only once before VAP is programmed,
46004+ but this optimization is for later */
46005+ OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
46006+ OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
46007+ OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
46008+ OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
46009+
46010+ ADVANCE_RING();
46011+
46012+ cmdbuf->buf += sz * 16;
46013+ cmdbuf->bufsz -= sz * 16;
46014+
46015+ return 0;
46016+}
46017+
46018+/**
46019+ * Emit a clear packet from userspace.
46020+ * Called by r300_emit_packet3.
46021+ */
46022+static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
46023+ drm_radeon_kcmd_buffer_t *cmdbuf)
46024+{
46025+ RING_LOCALS;
46026+
46027+ if (8 * 4 > cmdbuf->bufsz)
46028+ return -EINVAL;
46029+
46030+ BEGIN_RING(10);
46031+ OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
46032+ OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
46033+ (1 << R300_PRIM_NUM_VERTICES_SHIFT));
46034+ OUT_RING_TABLE((int *)cmdbuf->buf, 8);
46035+ ADVANCE_RING();
46036+
46037+ cmdbuf->buf += 8 * 4;
46038+ cmdbuf->bufsz -= 8 * 4;
46039+
46040+ return 0;
46041+}
46042+
46043+static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
46044+ drm_radeon_kcmd_buffer_t *cmdbuf,
46045+ u32 header)
46046+{
46047+ int count, i, k;
46048+#define MAX_ARRAY_PACKET 64
46049+ u32 payload[MAX_ARRAY_PACKET];
46050+ u32 narrays;
46051+ RING_LOCALS;
46052+
46053+ count = (header >> 16) & 0x3fff;
46054+
46055+ if ((count + 1) > MAX_ARRAY_PACKET) {
46056+ DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
46057+ count);
46058+ return -EINVAL;
46059+ }
46060+ memset(payload, 0, MAX_ARRAY_PACKET * 4);
46061+ memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
46062+
46063+ /* carefully check packet contents */
46064+
46065+ narrays = payload[0];
46066+ k = 0;
46067+ i = 1;
46068+ while ((k < narrays) && (i < (count + 1))) {
46069+ i++; /* skip attribute field */
46070+ if (!radeon_check_offset(dev_priv, payload[i])) {
46071+ DRM_ERROR
46072+ ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
46073+ k, i);
46074+ return -EINVAL;
46075+ }
46076+ k++;
46077+ i++;
46078+ if (k == narrays)
46079+ break;
46080+ /* have one more to process, they come in pairs */
46081+ if (!radeon_check_offset(dev_priv, payload[i])) {
46082+ DRM_ERROR
46083+ ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
46084+ k, i);
46085+ return -EINVAL;
46086+ }
46087+ k++;
46088+ i++;
46089+ }
46090+ /* do the counts match what we expect ? */
46091+ if ((k != narrays) || (i != (count + 1))) {
46092+ DRM_ERROR
46093+ ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
46094+ k, i, narrays, count + 1);
46095+ return -EINVAL;
46096+ }
46097+
46098+ /* all clear, output packet */
46099+
46100+ BEGIN_RING(count + 2);
46101+ OUT_RING(header);
46102+ OUT_RING_TABLE(payload, count + 1);
46103+ ADVANCE_RING();
46104+
46105+ cmdbuf->buf += (count + 2) * 4;
46106+ cmdbuf->bufsz -= (count + 2) * 4;
46107+
46108+ return 0;
46109+}
46110+
46111+static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
46112+ drm_radeon_kcmd_buffer_t *cmdbuf)
46113+{
46114+ u32 *cmd = (u32 *) cmdbuf->buf;
46115+ int count, ret;
46116+ RING_LOCALS;
46117+
46118+ count=(cmd[0]>>16) & 0x3fff;
46119+
46120+ if (cmd[0] & 0x8000) {
46121+ u32 offset;
46122+
46123+ if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
46124+ | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
46125+ offset = cmd[2] << 10;
46126+ ret = !radeon_check_offset(dev_priv, offset);
46127+ if (ret) {
46128+ DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
46129+ return -EINVAL;
46130+ }
46131+ }
46132+
46133+ if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
46134+ (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
46135+ offset = cmd[3] << 10;
46136+ ret = !radeon_check_offset(dev_priv, offset);
46137+ if (ret) {
46138+ DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
46139+ return -EINVAL;
46140+ }
46141+
46142+ }
46143+ }
46144+
46145+ BEGIN_RING(count+2);
46146+ OUT_RING(cmd[0]);
46147+ OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
46148+ ADVANCE_RING();
46149+
46150+ cmdbuf->buf += (count+2)*4;
46151+ cmdbuf->bufsz -= (count+2)*4;
46152+
46153+ return 0;
46154+}
46155+
46156+static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
46157+ drm_radeon_kcmd_buffer_t *cmdbuf)
46158+{
46159+ u32 *cmd = (u32 *) cmdbuf->buf;
46160+ int count, ret;
46161+ RING_LOCALS;
46162+
46163+ count=(cmd[0]>>16) & 0x3fff;
46164+
46165+ if ((cmd[1] & 0x8000ffff) != 0x80000810) {
46166+ DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
46167+ return -EINVAL;
46168+ }
46169+ ret = !radeon_check_offset(dev_priv, cmd[2]);
46170+ if (ret) {
46171+ DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
46172+ return -EINVAL;
46173+ }
46174+
46175+ BEGIN_RING(count+2);
46176+ OUT_RING(cmd[0]);
46177+ OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
46178+ ADVANCE_RING();
46179+
46180+ cmdbuf->buf += (count+2)*4;
46181+ cmdbuf->bufsz -= (count+2)*4;
46182+
46183+ return 0;
46184+}
46185+
46186+static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
46187+ drm_radeon_kcmd_buffer_t *cmdbuf)
46188+{
46189+ u32 header;
46190+ int count;
46191+ RING_LOCALS;
46192+
46193+ if (4 > cmdbuf->bufsz)
46194+ return -EINVAL;
46195+
46196+ /* Fixme !! This simply emits a packet without much checking.
46197+ We need to be smarter. */
46198+
46199+ /* obtain first word - actual packet3 header */
46200+ header = *(u32 *) cmdbuf->buf;
46201+
46202+ /* Is it packet 3 ? */
46203+ if ((header >> 30) != 0x3) {
46204+ DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
46205+ return -EINVAL;
46206+ }
46207+
46208+ count = (header >> 16) & 0x3fff;
46209+
46210+ /* Check again now that we know how much data to expect */
46211+ if ((count + 2) * 4 > cmdbuf->bufsz) {
46212+ DRM_ERROR
46213+ ("Expected packet3 of length %d but have only %d bytes left\n",
46214+ (count + 2) * 4, cmdbuf->bufsz);
46215+ return -EINVAL;
46216+ }
46217+
46218+ /* Is it a packet type we know about ? */
46219+ switch (header & 0xff00) {
46220+ case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
46221+ return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
46222+
46223+ case RADEON_CNTL_BITBLT_MULTI:
46224+ return r300_emit_bitblt_multi(dev_priv, cmdbuf);
46225+
46226+ case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
46227+ return r300_emit_indx_buffer(dev_priv, cmdbuf);
46228+ case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
46229+ case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
46230+ case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
46231+ case RADEON_WAIT_FOR_IDLE:
46232+ case RADEON_CP_NOP:
46233+ /* these packets are safe */
46234+ break;
46235+ default:
46236+ DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
46237+ return -EINVAL;
46238+ }
46239+
46240+ BEGIN_RING(count + 2);
46241+ OUT_RING(header);
46242+ OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
46243+ ADVANCE_RING();
46244+
46245+ cmdbuf->buf += (count + 2) * 4;
46246+ cmdbuf->bufsz -= (count + 2) * 4;
46247+
46248+ return 0;
46249+}
46250+
46251+/**
46252+ * Emit a rendering packet3 from userspace.
46253+ * Called by r300_do_cp_cmdbuf.
46254+ */
46255+static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
46256+ drm_radeon_kcmd_buffer_t *cmdbuf,
46257+ drm_r300_cmd_header_t header)
46258+{
46259+ int n;
46260+ int ret;
46261+ char *orig_buf = cmdbuf->buf;
46262+ int orig_bufsz = cmdbuf->bufsz;
46263+
46264+ /* This is a do-while-loop so that we run the interior at least once,
46265+ * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
46266+ */
46267+ n = 0;
46268+ do {
46269+ if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
46270+ ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
46271+ if (ret)
46272+ return ret;
46273+
46274+ cmdbuf->buf = orig_buf;
46275+ cmdbuf->bufsz = orig_bufsz;
46276+ }
46277+
46278+ switch (header.packet3.packet) {
46279+ case R300_CMD_PACKET3_CLEAR:
46280+ DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
46281+ ret = r300_emit_clear(dev_priv, cmdbuf);
46282+ if (ret) {
46283+ DRM_ERROR("r300_emit_clear failed\n");
46284+ return ret;
46285+ }
46286+ break;
46287+
46288+ case R300_CMD_PACKET3_RAW:
46289+ DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
46290+ ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
46291+ if (ret) {
46292+ DRM_ERROR("r300_emit_raw_packet3 failed\n");
46293+ return ret;
46294+ }
46295+ break;
46296+
46297+ default:
46298+ DRM_ERROR("bad packet3 type %i at %p\n",
46299+ header.packet3.packet,
46300+ cmdbuf->buf - sizeof(header));
46301+ return -EINVAL;
46302+ }
46303+
46304+ n += R300_SIMULTANEOUS_CLIPRECTS;
46305+ } while (n < cmdbuf->nbox);
46306+
46307+ return 0;
46308+}
46309+
46310+/* Some of the R300 chips seem to be extremely touchy about the two registers
46311+ * that are configured in r300_pacify.
46312+ * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
46313+ * sends a command buffer that contains only state setting commands and a
46314+ * vertex program/parameter upload sequence, this will eventually lead to a
46315+ * lockup, unless the sequence is bracketed by calls to r300_pacify.
46316+ * So we should take great care to *always* call r300_pacify before
46317+ * *anything* 3D related, and again afterwards. This is what the
46318+ * call bracket in r300_do_cp_cmdbuf is for.
46319+ */
46320+
46321+/**
46322+ * Emit the sequence to pacify R300.
46323+ */
46324+static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
46325+{
46326+ RING_LOCALS;
46327+
46328+ BEGIN_RING(6);
46329+ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
46330+ OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
46331+ OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
46332+ OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
46333+ OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
46334+ OUT_RING(0x0);
46335+ ADVANCE_RING();
46336+}
46337+
46338+/**
46339+ * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
46340+ * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
46341+ * be careful about how this function is called.
46342+ */
46343+static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
46344+{
46345+ drm_radeon_private_t *dev_priv = dev->dev_private;
46346+ drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
46347+
46348+ buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
46349+ buf->pending = 1;
46350+ buf->used = 0;
46351+}
46352+
46353+static int r300_scratch(drm_radeon_private_t *dev_priv,
46354+ drm_radeon_kcmd_buffer_t *cmdbuf,
46355+ drm_r300_cmd_header_t header)
46356+{
46357+ u32 *ref_age_base;
46358+ u32 i, buf_idx, h_pending;
46359+ RING_LOCALS;
46360+
46361+ if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
46362+ return -EINVAL;
46363+ }
46364+
46365+ if (header.scratch.reg >= 5) {
46366+ return -EINVAL;
46367+ }
46368+
46369+ dev_priv->scratch_ages[header.scratch.reg] ++;
46370+
46371+ ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
46372+
46373+ cmdbuf->buf += sizeof(uint64_t);
46374+ cmdbuf->bufsz -= sizeof(uint64_t);
46375+
46376+ for (i=0; i < header.scratch.n_bufs; i++) {
46377+ buf_idx = *(u32 *)cmdbuf->buf;
46378+ buf_idx *= 2; /* 8 bytes per buf */
46379+
46380+ if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
46381+ return -EINVAL;
46382+ }
46383+
46384+ if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
46385+ return -EINVAL;
46386+ }
46387+
46388+ if (h_pending == 0) {
46389+ return -EINVAL;
46390+ }
46391+
46392+ h_pending--;
46393+
46394+ if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
46395+ return -EINVAL;
46396+ }
46397+
46398+ cmdbuf->buf += sizeof(buf_idx);
46399+ cmdbuf->bufsz -= sizeof(buf_idx);
46400+ }
46401+
46402+ BEGIN_RING(2);
46403+ OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
46404+ OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
46405+ ADVANCE_RING();
46406+
46407+ return 0;
46408+}
46409+
46410+/**
46411+ * Parses and validates a user-supplied command buffer and emits appropriate
46412+ * commands on the DMA ring buffer.
46413+ * Called by the ioctl handler function radeon_cp_cmdbuf.
46414+ */
46415+int r300_do_cp_cmdbuf(struct drm_device *dev,
46416+ struct drm_file *file_priv,
46417+ drm_radeon_kcmd_buffer_t *cmdbuf)
46418+{
46419+ drm_radeon_private_t *dev_priv = dev->dev_private;
46420+ struct drm_device_dma *dma = dev->dma;
46421+ struct drm_buf *buf = NULL;
46422+ int emit_dispatch_age = 0;
46423+ int ret = 0;
46424+
46425+ DRM_DEBUG("\n");
46426+
46427+ /* See the comment above r300_emit_begin3d for why this call must be here,
46428+ * and what the cleanup gotos are for. */
46429+ r300_pacify(dev_priv);
46430+
46431+ if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
46432+ ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
46433+ if (ret)
46434+ goto cleanup;
46435+ }
46436+
46437+ while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
46438+ int idx;
46439+ drm_r300_cmd_header_t header;
46440+
46441+ header.u = *(unsigned int *)cmdbuf->buf;
46442+
46443+ cmdbuf->buf += sizeof(header);
46444+ cmdbuf->bufsz -= sizeof(header);
46445+
46446+ switch (header.header.cmd_type) {
46447+ case R300_CMD_PACKET0:
46448+ DRM_DEBUG("R300_CMD_PACKET0\n");
46449+ ret = r300_emit_packet0(dev_priv, cmdbuf, header);
46450+ if (ret) {
46451+ DRM_ERROR("r300_emit_packet0 failed\n");
46452+ goto cleanup;
46453+ }
46454+ break;
46455+
46456+ case R300_CMD_VPU:
46457+ DRM_DEBUG("R300_CMD_VPU\n");
46458+ ret = r300_emit_vpu(dev_priv, cmdbuf, header);
46459+ if (ret) {
46460+ DRM_ERROR("r300_emit_vpu failed\n");
46461+ goto cleanup;
46462+ }
46463+ break;
46464+
46465+ case R300_CMD_PACKET3:
46466+ DRM_DEBUG("R300_CMD_PACKET3\n");
46467+ ret = r300_emit_packet3(dev_priv, cmdbuf, header);
46468+ if (ret) {
46469+ DRM_ERROR("r300_emit_packet3 failed\n");
46470+ goto cleanup;
46471+ }
46472+ break;
46473+
46474+ case R300_CMD_END3D:
46475+ DRM_DEBUG("R300_CMD_END3D\n");
46476+ /* TODO:
46477+ Ideally userspace driver should not need to issue this call,
46478+ i.e. the drm driver should issue it automatically and prevent
46479+ lockups.
46480+
46481+ In practice, we do not understand why this call is needed and what
46482+ it does (except for some vague guesses that it has to do with cache
46483+ coherence) and so the user space driver does it.
46484+
46485+ Once we are sure which uses prevent lockups the code could be moved
46486+ into the kernel and the userspace driver will not
46487+ need to use this command.
46488+
46489+ Note that issuing this command does not hurt anything
46490+ except, possibly, performance */
46491+ r300_pacify(dev_priv);
46492+ break;
46493+
46494+ case R300_CMD_CP_DELAY:
46495+ /* simple enough, we can do it here */
46496+ DRM_DEBUG("R300_CMD_CP_DELAY\n");
46497+ {
46498+ int i;
46499+ RING_LOCALS;
46500+
46501+ BEGIN_RING(header.delay.count);
46502+ for (i = 0; i < header.delay.count; i++)
46503+ OUT_RING(RADEON_CP_PACKET2);
46504+ ADVANCE_RING();
46505+ }
46506+ break;
46507+
46508+ case R300_CMD_DMA_DISCARD:
46509+ DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
46510+ idx = header.dma.buf_idx;
46511+ if (idx < 0 || idx >= dma->buf_count) {
46512+ DRM_ERROR("buffer index %d (of %d max)\n",
46513+ idx, dma->buf_count - 1);
46514+ ret = -EINVAL;
46515+ goto cleanup;
46516+ }
46517+
46518+ buf = dma->buflist[idx];
46519+ if (buf->file_priv != file_priv || buf->pending) {
46520+ DRM_ERROR("bad buffer %p %p %d\n",
46521+ buf->file_priv, file_priv,
46522+ buf->pending);
46523+ ret = -EINVAL;
46524+ goto cleanup;
46525+ }
46526+
46527+ emit_dispatch_age = 1;
46528+ r300_discard_buffer(dev, buf);
46529+ break;
46530+
46531+ case R300_CMD_WAIT:
46532+ /* simple enough, we can do it here */
46533+ DRM_DEBUG("R300_CMD_WAIT\n");
46534+ if (header.wait.flags == 0)
46535+ break; /* nothing to do */
46536+
46537+ {
46538+ RING_LOCALS;
46539+
46540+ BEGIN_RING(2);
46541+ OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
46542+ OUT_RING((header.wait.flags & 0xf) << 14);
46543+ ADVANCE_RING();
46544+ }
46545+ break;
46546+
46547+ case R300_CMD_SCRATCH:
46548+ DRM_DEBUG("R300_CMD_SCRATCH\n");
46549+ ret = r300_scratch(dev_priv, cmdbuf, header);
46550+ if (ret) {
46551+ DRM_ERROR("r300_scratch failed\n");
46552+ goto cleanup;
46553+ }
46554+ break;
46555+
46556+ default:
46557+ DRM_ERROR("bad cmd_type %i at %p\n",
46558+ header.header.cmd_type,
46559+ cmdbuf->buf - sizeof(header));
46560+ ret = -EINVAL;
46561+ goto cleanup;
46562+ }
46563+ }
46564+
46565+ DRM_DEBUG("END\n");
46566+
46567+ cleanup:
46568+ r300_pacify(dev_priv);
46569+
46570+ /* We emit the vertex buffer age here, outside the pacifier "brackets"
46571+ * for two reasons:
46572+ * (1) This may coalesce multiple age emissions into a single one and
46573+ * (2) more importantly, some chips lock up hard when scratch registers
46574+ * are written inside the pacifier bracket.
46575+ */
46576+ if (emit_dispatch_age) {
46577+ RING_LOCALS;
46578+
46579+ /* Emit the vertex buffer age */
46580+ BEGIN_RING(2);
46581+ RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
46582+ ADVANCE_RING();
46583+ }
46584+
46585+ COMMIT_RING();
46586+
46587+ return ret;
46588+}
46589Index: git/shared-core/r300_reg.h
46590===================================================================
46591--- git.orig/shared-core/r300_reg.h 2008-12-12 17:20:14.000000000 +0000
46592+++ git/shared-core/r300_reg.h 2008-12-12 17:35:22.000000000 +0000
46593@@ -23,6 +23,8 @@
46594
46595 **************************************************************************/
46596
46597+/* *INDENT-OFF* */
46598+
46599 #ifndef _R300_REG_H
46600 #define _R300_REG_H
46601
46602@@ -48,12 +50,12 @@
46603 # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
46604
46605 /*
46606-This file contains registers and constants for the R300. They have been
46607-found mostly by examining command buffers captured using glxtest, as well
46608-as by extrapolating some known registers and constants from the R200.
46609-
46610-I am fairly certain that they are correct unless stated otherwise in comments.
46611-*/
46612+ * This file contains registers and constants for the R300. They have been
46613+ * found mostly by examining command buffers captured using glxtest, as well
46614+ * as by extrapolating some known registers and constants from the R200.
46615+ * I am fairly certain that they are correct unless stated otherwise
46616+ * in comments.
46617+ */
46618
46619 #define R300_SE_VPORT_XSCALE 0x1D98
46620 #define R300_SE_VPORT_XOFFSET 0x1D9C
46621@@ -63,49 +65,59 @@
46622 #define R300_SE_VPORT_ZOFFSET 0x1DAC
46623
46624
46625-/* This register is written directly and also starts data section in many 3d CP_PACKET3's */
46626-#define R300_VAP_VF_CNTL 0x2084
46627+/*
46628+ * Vertex Array Processing (VAP) Control
46629+ * Stolen from r200 code from Christoph Brill (It's a guess!)
46630+ */
46631+#define R300_VAP_CNTL 0x2080
46632
46633-# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
46634-# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
46635-# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
46636-# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
46637-# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
46638-# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
46639-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
46640-# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
46641-# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
46642-# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
46643-# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
46644-# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
46645-
46646-# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
46647- /* State based - direct writes to registers trigger vertex generation */
46648-# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
46649-# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
46650-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
46651-# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
46652-
46653- /* I don't think I saw these three used.. */
46654-# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
46655-# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
46656-# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
46657-
46658- /* index size - when not set the indices are assumed to be 16 bit */
46659-# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
46660- /* number of vertices */
46661-# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
46662+/* This register is written directly and also starts data section
46663+ * in many 3d CP_PACKET3's
46664+ */
46665+#define R300_VAP_VF_CNTL 0x2084
46666+# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
46667+# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
46668+# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
46669+# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
46670+# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
46671+# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
46672+# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
46673+# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
46674+# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
46675+# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
46676+# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
46677+# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
46678+
46679+# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
46680+ /* State based - direct writes to registers trigger vertex
46681+ generation */
46682+# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
46683+# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
46684+# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
46685+# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
46686+
46687+ /* I don't think I saw these three used.. */
46688+# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
46689+# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
46690+# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
46691+
46692+ /* index size - when not set the indices are assumed to be 16 bit */
46693+# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
46694+ /* number of vertices */
46695+# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
46696
46697 /* BEGIN: Wild guesses */
46698 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
46699 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
46700 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
46701-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
46702-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
46703-# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
46704+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
46705+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
46706+# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
46707 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
46708
46709 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
46710+ /* each of the following is 3 bits wide, specifies number
46711+ of components */
46712 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
46713 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
46714 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
46715@@ -114,7 +126,7 @@
46716 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
46717 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
46718 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
46719-/* END */
46720+/* END: Wild guesses */
46721
46722 #define R300_SE_VTE_CNTL 0x20b0
46723 # define R300_VPORT_X_SCALE_ENA 0x00000001
46724@@ -130,29 +142,40 @@
46725 # define R300_VTX_ST_DENORMALIZED 0x00001000
46726
46727 /* BEGIN: Vertex data assembly - lots of uncertainties */
46728+
46729 /* gap */
46730+
46731+#define R300_VAP_CNTL_STATUS 0x2140
46732+# define R300_VC_NO_SWAP (0 << 0)
46733+# define R300_VC_16BIT_SWAP (1 << 0)
46734+# define R300_VC_32BIT_SWAP (2 << 0)
46735+# define R300_VAP_TCL_BYPASS (1 << 8)
46736+
46737+/* gap */
46738+
46739 /* Where do we get our vertex data?
46740-//
46741-// Vertex data either comes either from immediate mode registers or from
46742-// vertex arrays.
46743-// There appears to be no mixed mode (though we can force the pitch of
46744-// vertex arrays to 0, effectively reusing the same element over and over
46745-// again).
46746-//
46747-// Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
46748-// if these registers influence vertex array processing.
46749-//
46750-// Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
46751-//
46752-// In both cases, vertex attributes are then passed through INPUT_ROUTE.
46753-
46754-// Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
46755-// into the vertex processor's input registers.
46756-// The first word routes the first input, the second word the second, etc.
46757-// The corresponding input is routed into the register with the given index.
46758-// The list is ended by a word with INPUT_ROUTE_END set.
46759-//
46760-// Always set COMPONENTS_4 in immediate mode. */
46761+ *
46762+ * Vertex data either comes either from immediate mode registers or from
46763+ * vertex arrays.
46764+ * There appears to be no mixed mode (though we can force the pitch of
46765+ * vertex arrays to 0, effectively reusing the same element over and over
46766+ * again).
46767+ *
46768+ * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
46769+ * if these registers influence vertex array processing.
46770+ *
46771+ * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
46772+ *
46773+ * In both cases, vertex attributes are then passed through INPUT_ROUTE.
46774+ *
46775+ * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
46776+ * into the vertex processor's input registers.
46777+ * The first word routes the first input, the second word the second, etc.
46778+ * The corresponding input is routed into the register with the given index.
46779+ * The list is ended by a word with INPUT_ROUTE_END set.
46780+ *
46781+ * Always set COMPONENTS_4 in immediate mode.
46782+ */
46783
46784 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
46785 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
46786@@ -176,10 +199,12 @@
46787 #define R300_VAP_INPUT_ROUTE_0_7 0x216C
46788
46789 /* gap */
46790+
46791 /* Notes:
46792-// - always set up to produce at least two attributes:
46793-// if vertex program uses only position, fglrx will set normal, too
46794-// - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */
46795+ * - always set up to produce at least two attributes:
46796+ * if vertex program uses only position, fglrx will set normal, too
46797+ * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
46798+ */
46799 #define R300_VAP_INPUT_CNTL_0 0x2180
46800 # define R300_INPUT_CNTL_0_COLOR 0x00000001
46801 #define R300_VAP_INPUT_CNTL_1 0x2184
46802@@ -196,12 +221,14 @@
46803 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
46804
46805 /* gap */
46806+
46807 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
46808-// are set to a swizzling bit pattern, other words are 0.
46809-//
46810-// In immediate mode, the pattern is always set to xyzw. In vertex array
46811-// mode, the swizzling pattern is e.g. used to set zw components in texture
46812-// coordinates with only tweo components. */
46813+ * are set to a swizzling bit pattern, other words are 0.
46814+ *
46815+ * In immediate mode, the pattern is always set to xyzw. In vertex array
46816+ * mode, the swizzling pattern is e.g. used to set zw components in texture
46817+ * coordinates with only tweo components.
46818+ */
46819 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
46820 # define R300_INPUT_ROUTE_SELECT_X 0
46821 # define R300_INPUT_ROUTE_SELECT_Y 1
46822@@ -210,11 +237,11 @@
46823 # define R300_INPUT_ROUTE_SELECT_ZERO 4
46824 # define R300_INPUT_ROUTE_SELECT_ONE 5
46825 # define R300_INPUT_ROUTE_SELECT_MASK 7
46826-# define R300_INPUT_ROUTE_X_SHIFT 0
46827-# define R300_INPUT_ROUTE_Y_SHIFT 3
46828-# define R300_INPUT_ROUTE_Z_SHIFT 6
46829-# define R300_INPUT_ROUTE_W_SHIFT 9
46830-# define R300_INPUT_ROUTE_ENABLE (15 << 12)
46831+# define R300_INPUT_ROUTE_X_SHIFT 0
46832+# define R300_INPUT_ROUTE_Y_SHIFT 3
46833+# define R300_INPUT_ROUTE_Z_SHIFT 6
46834+# define R300_INPUT_ROUTE_W_SHIFT 9
46835+# define R300_INPUT_ROUTE_ENABLE (15 << 12)
46836 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
46837 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
46838 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
46839@@ -223,53 +250,76 @@
46840 #define R300_VAP_INPUT_ROUTE_1_6 0x21F8
46841 #define R300_VAP_INPUT_ROUTE_1_7 0x21FC
46842
46843-/* END */
46844+/* END: Vertex data assembly */
46845
46846 /* gap */
46847-/* BEGIN: Upload vertex program and data
46848-// The programmable vertex shader unit has a memory bank of unknown size
46849-// that can be written to in 16 byte units by writing the address into
46850-// UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
46851-//
46852-// Pointers into the memory bank are always in multiples of 16 bytes.
46853-//
46854-// The memory bank is divided into areas with fixed meaning.
46855-//
46856-// Starting at address UPLOAD_PROGRAM: Vertex program instructions.
46857-// Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
46858-// whereas the difference between known addresses suggests size 512.
46859-//
46860-// Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
46861-// Native reported limits and the VPI layout suggest size 256, whereas
46862-// difference between known addresses suggests size 512.
46863-//
46864-// At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
46865-// floating point pointsize. The exact purpose of this state is uncertain,
46866-// as there is also the R300_RE_POINTSIZE register.
46867-//
46868-// Multiple vertex programs and parameter sets can be loaded at once,
46869-// which could explain the size discrepancy. */
46870+
46871+/* BEGIN: Upload vertex program and data */
46872+
46873+/*
46874+ * The programmable vertex shader unit has a memory bank of unknown size
46875+ * that can be written to in 16 byte units by writing the address into
46876+ * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
46877+ *
46878+ * Pointers into the memory bank are always in multiples of 16 bytes.
46879+ *
46880+ * The memory bank is divided into areas with fixed meaning.
46881+ *
46882+ * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
46883+ * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
46884+ * whereas the difference between known addresses suggests size 512.
46885+ *
46886+ * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
46887+ * Native reported limits and the VPI layout suggest size 256, whereas
46888+ * difference between known addresses suggests size 512.
46889+ *
46890+ * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
46891+ * floating point pointsize. The exact purpose of this state is uncertain,
46892+ * as there is also the R300_RE_POINTSIZE register.
46893+ *
46894+ * Multiple vertex programs and parameter sets can be loaded at once,
46895+ * which could explain the size discrepancy.
46896+ */
46897 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
46898 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
46899 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
46900 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406
46901+
46902 /* gap */
46903+
46904 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
46905-/* END */
46906+
46907+/* END: Upload vertex program and data */
46908
46909 /* gap */
46910+
46911 /* I do not know the purpose of this register. However, I do know that
46912-// it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
46913-// for normal rendering. */
46914+ * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
46915+ * for normal rendering.
46916+ */
46917 #define R300_VAP_UNKNOWN_221C 0x221C
46918 # define R300_221C_NORMAL 0x00000000
46919 # define R300_221C_CLEAR 0x0001C000
46920
46921+/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
46922+ * plane is per-pixel and the second plane is per-vertex.
46923+ *
46924+ * This was determined by experimentation alone but I believe it is correct.
46925+ *
46926+ * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
46927+ */
46928+#define R300_VAP_CLIP_X_0 0x2220
46929+#define R300_VAP_CLIP_X_1 0x2224
46930+#define R300_VAP_CLIP_Y_0 0x2228
46931+#define R300_VAP_CLIP_Y_1 0x2230
46932+
46933 /* gap */
46934+
46935 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
46936-// rendering commands and overwriting vertex program parameters.
46937-// Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
46938-// avoids bugs caused by still running shaders reading bad data from memory. */
46939+ * rendering commands and overwriting vertex program parameters.
46940+ * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
46941+ * avoids bugs caused by still running shaders reading bad data from memory.
46942+ */
46943 #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
46944
46945 /* Absolutely no clue what this register is about. */
46946@@ -278,19 +328,24 @@
46947 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
46948
46949 /* gap */
46950+
46951 /* Addresses are relative to the vertex program instruction area of the
46952-// memory bank. PROGRAM_END points to the last instruction of the active
46953-// program
46954-//
46955-// The meaning of the two UNKNOWN fields is obviously not known. However,
46956-// experiments so far have shown that both *must* point to an instruction
46957-// inside the vertex program, otherwise the GPU locks up.
46958-// fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
46959-// CNTL_1_UNKNOWN points to instruction where last write to position takes place.
46960-// Most likely this is used to ignore rest of the program in cases where group of verts arent visible.
46961-// For some reason this "section" is sometimes accepted other instruction that have
46962-// no relationship with position calculations.
46963-*/
46964+ * memory bank. PROGRAM_END points to the last instruction of the active
46965+ * program
46966+ *
46967+ * The meaning of the two UNKNOWN fields is obviously not known. However,
46968+ * experiments so far have shown that both *must* point to an instruction
46969+ * inside the vertex program, otherwise the GPU locks up.
46970+ *
46971+ * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
46972+ * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
46973+ * position takes place.
46974+ *
46975+ * Most likely this is used to ignore rest of the program in cases
46976+ * where group of verts arent visible. For some reason this "section"
46977+ * is sometimes accepted other instruction that have no relationship with
46978+ * position calculations.
46979+ */
46980 #define R300_VAP_PVS_CNTL_1 0x22D0
46981 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
46982 # define R300_PVS_CNTL_1_POS_END_SHIFT 10
46983@@ -304,7 +359,8 @@
46984 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
46985
46986 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
46987-// immediate vertices */
46988+ * immediate vertices
46989+ */
46990 #define R300_VAP_VTX_COLOR_R 0x2464
46991 #define R300_VAP_VTX_COLOR_G 0x2468
46992 #define R300_VAP_VTX_COLOR_B 0x246C
46993@@ -314,13 +370,15 @@
46994 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
46995 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
46996 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
46997-#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */
46998+/* write 0 to indicate end of packet? */
46999+#define R300_VAP_VTX_END_OF_PKT 0x24AC
47000
47001 /* gap */
47002
47003 /* These are values from r300_reg/r300_reg.h - they are known to be correct
47004- and are here so we can use one register file instead of several
47005- - Vladimir */
47006+ * and are here so we can use one register file instead of several
47007+ * - Vladimir
47008+ */
47009 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
47010 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
47011 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
47012@@ -343,14 +401,16 @@
47013 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
47014
47015 /* UNK30 seems to enables point to quad transformation on textures
47016- (or something closely related to that).
47017- This bit is rather fatal at the time being due to lackings at pixel shader side */
47018+ * (or something closely related to that).
47019+ * This bit is rather fatal at the time being due to lackings at pixel
47020+ * shader side
47021+ */
47022 #define R300_GB_ENABLE 0x4008
47023 # define R300_GB_POINT_STUFF_ENABLE (1<<0)
47024 # define R300_GB_LINE_STUFF_ENABLE (1<<1)
47025 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
47026 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
47027-# define R300_GB_UNK30 (1<<30)
47028+# define R300_GB_UNK31 (1<<31)
47029 /* each of the following is 2 bits wide */
47030 #define R300_GB_TEX_REPLICATE 0
47031 #define R300_GB_TEX_ST 1
47032@@ -391,6 +451,7 @@
47033 # define R300_GB_TILE_PIPE_COUNT_RV300 0
47034 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
47035 # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
47036+# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)
47037 # define R300_GB_TILE_SIZE_8 0
47038 # define R300_GB_TILE_SIZE_16 (1<<4)
47039 # define R300_GB_TILE_SIZE_32 (2<<4)
47040@@ -445,17 +506,18 @@
47041 # define R300_GB_W_SELECT_1 (1<<4)
47042
47043 #define R300_GB_AA_CONFIG 0x4020
47044+# define R300_AA_DISABLE 0x00
47045 # define R300_AA_ENABLE 0x01
47046 # define R300_AA_SUBSAMPLES_2 0
47047 # define R300_AA_SUBSAMPLES_3 (1<<1)
47048 # define R300_AA_SUBSAMPLES_4 (2<<1)
47049 # define R300_AA_SUBSAMPLES_6 (3<<1)
47050
47051-/* END */
47052-
47053 /* gap */
47054+
47055 /* Zero to flush caches. */
47056 #define R300_TX_CNTL 0x4100
47057+#define R300_TX_FLUSH 0x0
47058
47059 /* The upper enable bits are guessed, based on fglrx reported limits. */
47060 #define R300_TX_ENABLE 0x4104
47061@@ -477,8 +539,9 @@
47062 # define R300_TX_ENABLE_15 (1 << 15)
47063
47064 /* The pointsize is given in multiples of 6. The pointsize can be
47065-// enormous: Clear() renders a single point that fills the entire
47066-// framebuffer. */
47067+ * enormous: Clear() renders a single point that fills the entire
47068+ * framebuffer.
47069+ */
47070 #define R300_RE_POINTSIZE 0x421C
47071 # define R300_POINTSIZE_Y_SHIFT 0
47072 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
47073@@ -487,11 +550,11 @@
47074 # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
47075
47076 /* The line width is given in multiples of 6.
47077- In default mode lines are classified as vertical lines.
47078- HO: horizontal
47079- VE: vertical or horizontal
47080- HO & VE: no classification
47081-*/
47082+ * In default mode lines are classified as vertical lines.
47083+ * HO: horizontal
47084+ * VE: vertical or horizontal
47085+ * HO & VE: no classification
47086+ */
47087 #define R300_RE_LINE_CNT 0x4234
47088 # define R300_LINESIZE_SHIFT 0
47089 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
47090@@ -502,6 +565,9 @@
47091 /* Some sort of scale or clamp value for texcoordless textures. */
47092 #define R300_RE_UNK4238 0x4238
47093
47094+/* Something shade related */
47095+#define R300_RE_SHADE 0x4274
47096+
47097 #define R300_RE_SHADE_MODEL 0x4278
47098 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa
47099 # define R300_RE_SHADE_MODEL_FLAT 0x39595
47100@@ -516,24 +582,31 @@
47101 # define R300_PM_BACK_LINE (1 << 7)
47102 # define R300_PM_BACK_FILL (1 << 8)
47103
47104-/* Not sure why there are duplicate of factor and constant values.
47105- My best guess so far is that there are seperate zbiases for test and write.
47106- Ordering might be wrong.
47107- Some of the tests indicate that fgl has a fallback implementation of zbias
47108- via pixel shaders. */
47109+/* Fog parameters */
47110+#define R300_RE_FOG_SCALE 0x4294
47111+#define R300_RE_FOG_START 0x4298
47112+
47113+/* Not sure why there are duplicate of factor and constant values.
47114+ * My best guess so far is that there are seperate zbiases for test and write.
47115+ * Ordering might be wrong.
47116+ * Some of the tests indicate that fgl has a fallback implementation of zbias
47117+ * via pixel shaders.
47118+ */
47119+#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */
47120 #define R300_RE_ZBIAS_T_FACTOR 0x42A4
47121 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8
47122 #define R300_RE_ZBIAS_W_FACTOR 0x42AC
47123 #define R300_RE_ZBIAS_W_CONSTANT 0x42B0
47124
47125 /* This register needs to be set to (1<<1) for RV350 to correctly
47126- perform depth test (see --vb-triangles in r300_demo)
47127- Don't know about other chips. - Vladimir
47128- This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
47129- My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT).
47130- One to enable depth test and one for depth write.
47131- Yet this doesnt explain why depth writes work ...
47132- */
47133+ * perform depth test (see --vb-triangles in r300_demo)
47134+ * Don't know about other chips. - Vladimir
47135+ * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
47136+ * My guess is that there are two bits for each zbias primitive
47137+ * (FILL, LINE, POINT).
47138+ * One to enable depth test and one for depth write.
47139+ * Yet this doesnt explain why depth writes work ...
47140+ */
47141 #define R300_RE_OCCLUSION_CNTL 0x42B4
47142 # define R300_OCCLUSION_ON (1<<1)
47143
47144@@ -544,30 +617,37 @@
47145 # define R300_FRONT_FACE_CW (1 << 2)
47146
47147
47148-/* BEGIN: Rasterization / Interpolators - many guesses
47149-// 0_UNKNOWN_18 has always been set except for clear operations.
47150-// TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
47151-// on the vertex program, *not* the fragment program) */
47152+/* BEGIN: Rasterization / Interpolators - many guesses */
47153+
47154+/* 0_UNKNOWN_18 has always been set except for clear operations.
47155+ * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
47156+ * on the vertex program, *not* the fragment program)
47157+ */
47158 #define R300_RS_CNTL_0 0x4300
47159 # define R300_RS_CNTL_TC_CNT_SHIFT 2
47160 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
47161-# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */
47162+ /* number of color interpolators used */
47163+# define R300_RS_CNTL_CI_CNT_SHIFT 7
47164 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
47165-/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */
47166+ /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
47167+ register. */
47168 #define R300_RS_CNTL_1 0x4304
47169
47170 /* gap */
47171+
47172 /* Only used for texture coordinates.
47173-// Use the source field to route texture coordinate input from the vertex program
47174-// to the desired interpolator. Note that the source field is relative to the
47175-// outputs the vertex program *actually* writes. If a vertex program only writes
47176-// texcoord[1], this will be source index 0.
47177-// Set INTERP_USED on all interpolators that produce data used by the
47178-// fragment program. INTERP_USED looks like a swizzling mask, but
47179-// I haven't seen it used that way.
47180-//
47181-// Note: The _UNKNOWN constants are always set in their respective register.
47182-// I don't know if this is necessary. */
47183+ * Use the source field to route texture coordinate input from the
47184+ * vertex program to the desired interpolator. Note that the source
47185+ * field is relative to the outputs the vertex program *actually*
47186+ * writes. If a vertex program only writes texcoord[1], this will
47187+ * be source index 0.
47188+ * Set INTERP_USED on all interpolators that produce data used by
47189+ * the fragment program. INTERP_USED looks like a swizzling mask,
47190+ * but I haven't seen it used that way.
47191+ *
47192+ * Note: The _UNKNOWN constants are always set in their respective
47193+ * register. I don't know if this is necessary.
47194+ */
47195 #define R300_RS_INTERP_0 0x4310
47196 #define R300_RS_INTERP_1 0x4314
47197 # define R300_RS_INTERP_1_UNKNOWN 0x40
47198@@ -584,7 +664,8 @@
47199 # define R300_RS_INTERP_USED 0x00D10000
47200
47201 /* These DWORDs control how vertex data is routed into fragment program
47202-// registers, after interpolators. */
47203+ * registers, after interpolators.
47204+ */
47205 #define R300_RS_ROUTE_0 0x4330
47206 #define R300_RS_ROUTE_1 0x4334
47207 #define R300_RS_ROUTE_2 0x4338
47208@@ -606,8 +687,14 @@
47209 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
47210
47211 /* Special handling for color: When the fragment program uses color,
47212-// the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
47213-// color register index. */
47214+ * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
47215+ * color register index.
47216+ *
47217+ * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
47218+ * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
47219+ * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
47220+ * correct or not. - Oliver.
47221+ */
47222 # define R300_RS_ROUTE_0_COLOR (1 << 14)
47223 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
47224 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
47225@@ -616,22 +703,24 @@
47226 # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
47227 # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)
47228 # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
47229-/* END */
47230+/* END: Rasterization / Interpolators - many guesses */
47231+
47232+/* BEGIN: Scissors and cliprects */
47233
47234-/* BEGIN: Scissors and cliprects
47235-// There are four clipping rectangles. Their corner coordinates are inclusive.
47236-// Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
47237-// on whether the pixel is inside cliprects 0-3, respectively. For example,
47238-// if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
47239-// the number 3 (binary 0011).
47240-// Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
47241-// the pixel is rasterized.
47242-//
47243-// In addition to this, there is a scissors rectangle. Only pixels inside the
47244-// scissors rectangle are drawn. (coordinates are inclusive)
47245-//
47246-// For some reason, the top-left corner of the framebuffer is at (1440, 1440)
47247-// for the purpose of clipping and scissors. */
47248+/* There are four clipping rectangles. Their corner coordinates are inclusive.
47249+ * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
47250+ * on whether the pixel is inside cliprects 0-3, respectively. For example,
47251+ * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
47252+ * the number 3 (binary 0011).
47253+ * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
47254+ * the pixel is rasterized.
47255+ *
47256+ * In addition to this, there is a scissors rectangle. Only pixels inside the
47257+ * scissors rectangle are drawn. (coordinates are inclusive)
47258+ *
47259+ * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
47260+ * for the purpose of clipping and scissors.
47261+ */
47262 #define R300_RE_CLIPRECT_TL_0 0x43B0
47263 #define R300_RE_CLIPRECT_BR_0 0x43B4
47264 #define R300_RE_CLIPRECT_TL_1 0x43B8
47265@@ -665,6 +754,7 @@
47266 # define R300_CLIP_3210 (1 << 15)
47267
47268 /* gap */
47269+
47270 #define R300_RE_SCISSORS_TL 0x43E0
47271 #define R300_RE_SCISSORS_BR 0x43E4
47272 # define R300_SCISSORS_OFFSET 1440
47273@@ -672,12 +762,15 @@
47274 # define R300_SCISSORS_X_MASK (0x1FFF << 0)
47275 # define R300_SCISSORS_Y_SHIFT 13
47276 # define R300_SCISSORS_Y_MASK (0x1FFF << 13)
47277-/* END */
47278+/* END: Scissors and cliprects */
47279+
47280+/* BEGIN: Texture specification */
47281
47282-/* BEGIN: Texture specification
47283-// The texture specification dwords are grouped by meaning and not by texture unit.
47284-// This means that e.g. the offset for texture image unit N is found in register
47285-// TX_OFFSET_0 + (4*N) */
47286+/*
47287+ * The texture specification dwords are grouped by meaning and not by texture
47288+ * unit. This means that e.g. the offset for texture image unit N is found in
47289+ * register TX_OFFSET_0 + (4*N)
47290+ */
47291 #define R300_TX_FILTER_0 0x4400
47292 # define R300_TX_REPEAT 0
47293 # define R300_TX_MIRRORED 1
47294@@ -701,13 +794,14 @@
47295 # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
47296
47297 /* NOTE: NEAREST doesnt seem to exist.
47298- Im not seting MAG_FILTER_MASK and (3 << 11) on for all
47299- anisotropy modes because that would void selected mag filter */
47300-# define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
47301-# define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
47302-# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
47303-# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/)
47304-# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
47305+ * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
47306+ * anisotropy modes because that would void selected mag filter
47307+ */
47308+# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13)
47309+# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13)
47310+# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
47311+# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)
47312+# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
47313 # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
47314 # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)
47315 # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)
47316@@ -738,10 +832,10 @@
47317 # define R300_TX_HEIGHTMASK_SHIFT 11
47318 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
47319 # define R300_TX_UNK23 (1 << 23)
47320-# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */
47321-# define R300_TX_SIZE_MASK (15 << 26)
47322-# define R300_TX_SIZE_PROJECTED (1<<30)
47323-# define R300_TX_SIZE_TXPITCH_EN (1<<31)
47324+# define R300_TX_MAX_MIP_LEVEL_SHIFT 26
47325+# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
47326+# define R300_TX_SIZE_PROJECTED (1<<30)
47327+# define R300_TX_SIZE_TXPITCH_EN (1<<31)
47328 #define R300_TX_FORMAT_0 0x44C0
47329 /* The interpretation of the format word by Wladimir van der Laan */
47330 /* The X, Y, Z and W refer to the layout of the components.
47331@@ -762,33 +856,33 @@
47332 # define R300_TX_FORMAT_W8Z8Y8X8 0xC
47333 # define R300_TX_FORMAT_W2Z10Y10X10 0xD
47334 # define R300_TX_FORMAT_W16Z16Y16X16 0xE
47335-# define R300_TX_FORMAT_DXT1 0xF
47336-# define R300_TX_FORMAT_DXT3 0x10
47337-# define R300_TX_FORMAT_DXT5 0x11
47338+# define R300_TX_FORMAT_DXT1 0xF
47339+# define R300_TX_FORMAT_DXT3 0x10
47340+# define R300_TX_FORMAT_DXT5 0x11
47341 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
47342-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
47343-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
47344-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
47345- /* 0x16 - some 16 bit green format.. ?? */
47346+# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
47347+# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
47348+# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
47349+ /* 0x16 - some 16 bit green format.. ?? */
47350 # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
47351 # define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
47352
47353 /* gap */
47354 /* Floating point formats */
47355 /* Note - hardware supports both 16 and 32 bit floating point */
47356-# define R300_TX_FORMAT_FL_I16 0x18
47357-# define R300_TX_FORMAT_FL_I16A16 0x19
47358+# define R300_TX_FORMAT_FL_I16 0x18
47359+# define R300_TX_FORMAT_FL_I16A16 0x19
47360 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
47361-# define R300_TX_FORMAT_FL_I32 0x1B
47362-# define R300_TX_FORMAT_FL_I32A32 0x1C
47363+# define R300_TX_FORMAT_FL_I32 0x1B
47364+# define R300_TX_FORMAT_FL_I32A32 0x1C
47365 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
47366 /* alpha modes, convenience mostly */
47367 /* if you have alpha, pick constant appropriate to the
47368 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
47369-# define R300_TX_FORMAT_ALPHA_1CH 0x000
47370-# define R300_TX_FORMAT_ALPHA_2CH 0x200
47371-# define R300_TX_FORMAT_ALPHA_4CH 0x600
47372-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
47373+# define R300_TX_FORMAT_ALPHA_1CH 0x000
47374+# define R300_TX_FORMAT_ALPHA_2CH 0x200
47375+# define R300_TX_FORMAT_ALPHA_4CH 0x600
47376+# define R300_TX_FORMAT_ALPHA_NONE 0xA00
47377 /* Swizzling */
47378 /* constants */
47379 # define R300_TX_FORMAT_X 0
47380@@ -797,23 +891,26 @@
47381 # define R300_TX_FORMAT_W 3
47382 # define R300_TX_FORMAT_ZERO 4
47383 # define R300_TX_FORMAT_ONE 5
47384-# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */
47385-# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */
47386+ /* 2.0*Z, everything above 1.0 is set to 0.0 */
47387+# define R300_TX_FORMAT_CUT_Z 6
47388+ /* 2.0*W, everything above 1.0 is set to 0.0 */
47389+# define R300_TX_FORMAT_CUT_W 7
47390
47391 # define R300_TX_FORMAT_B_SHIFT 18
47392 # define R300_TX_FORMAT_G_SHIFT 15
47393 # define R300_TX_FORMAT_R_SHIFT 12
47394 # define R300_TX_FORMAT_A_SHIFT 9
47395 /* Convenience macro to take care of layout and swizzling */
47396-# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) (\
47397- ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
47398- | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
47399- | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
47400- | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
47401- | (R300_TX_FORMAT_##FMT) \
47402- )
47403- /* These can be ORed with result of R300_EASY_TX_FORMAT() */
47404- /* We don't really know what they do. Take values from a constant color ? */
47405+# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
47406+ ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
47407+ | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
47408+ | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
47409+ | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
47410+ | (R300_TX_FORMAT_##FMT) \
47411+ )
47412+ /* These can be ORed with result of R300_EASY_TX_FORMAT()
47413+ We don't really know what they do. Take values from a
47414+ constant color ? */
47415 # define R300_TX_FORMAT_CONST_X (1<<5)
47416 # define R300_TX_FORMAT_CONST_Y (2<<5)
47417 # define R300_TX_FORMAT_CONST_Z (4<<5)
47418@@ -823,7 +920,7 @@
47419
47420 #define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
47421 #define R300_TX_OFFSET_0 0x4540
47422-/* BEGIN: Guess from R200 */
47423+ /* BEGIN: Guess from R200 */
47424 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
47425 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
47426 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
47427@@ -832,53 +929,61 @@
47428 # define R300_TXO_MICRO_TILE (1 << 3)
47429 # define R300_TXO_OFFSET_MASK 0xffffffe0
47430 # define R300_TXO_OFFSET_SHIFT 5
47431-/* END */
47432-#define R300_TX_CHROMA_KEY_0 0x4580 /* 32 bit chroma key */
47433-#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 }
47434-
47435-/* END */
47436-
47437-/* BEGIN: Fragment program instruction set
47438-// Fragment programs are written directly into register space.
47439-// There are separate instruction streams for texture instructions and ALU
47440-// instructions.
47441-// In order to synchronize these streams, the program is divided into up
47442-// to 4 nodes. Each node begins with a number of TEX operations, followed
47443-// by a number of ALU operations.
47444-// The first node can have zero TEX ops, all subsequent nodes must have at least
47445-// one TEX ops.
47446-// All nodes must have at least one ALU op.
47447-//
47448-// The index of the last node is stored in PFS_CNTL_0: A value of 0 means
47449-// 1 node, a value of 3 means 4 nodes.
47450-// The total amount of instructions is defined in PFS_CNTL_2. The offsets are
47451-// offsets into the respective instruction streams, while *_END points to the
47452-// last instruction relative to this offset. */
47453+ /* END: Guess from R200 */
47454+
47455+/* 32 bit chroma key */
47456+#define R300_TX_CHROMA_KEY_0 0x4580
47457+/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
47458+#define R300_TX_BORDER_COLOR_0 0x45C0
47459+
47460+/* END: Texture specification */
47461+
47462+/* BEGIN: Fragment program instruction set */
47463+
47464+/* Fragment programs are written directly into register space.
47465+ * There are separate instruction streams for texture instructions and ALU
47466+ * instructions.
47467+ * In order to synchronize these streams, the program is divided into up
47468+ * to 4 nodes. Each node begins with a number of TEX operations, followed
47469+ * by a number of ALU operations.
47470+ * The first node can have zero TEX ops, all subsequent nodes must have at
47471+ * least
47472+ * one TEX ops.
47473+ * All nodes must have at least one ALU op.
47474+ *
47475+ * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
47476+ * 1 node, a value of 3 means 4 nodes.
47477+ * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
47478+ * offsets into the respective instruction streams, while *_END points to the
47479+ * last instruction relative to this offset.
47480+ */
47481 #define R300_PFS_CNTL_0 0x4600
47482 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
47483 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
47484 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
47485 #define R300_PFS_CNTL_1 0x4604
47486 /* There is an unshifted value here which has so far always been equal to the
47487-// index of the highest used temporary register. */
47488+ * index of the highest used temporary register.
47489+ */
47490 #define R300_PFS_CNTL_2 0x4608
47491 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
47492 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
47493 # define R300_PFS_CNTL_ALU_END_SHIFT 6
47494-# define R300_PFS_CNTL_ALU_END_MASK (63 << 0)
47495+# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
47496 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
47497 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
47498 # define R300_PFS_CNTL_TEX_END_SHIFT 18
47499 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
47500
47501 /* gap */
47502+
47503 /* Nodes are stored backwards. The last active node is always stored in
47504-// PFS_NODE_3.
47505-// Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
47506-// first node is stored in NODE_2, the second node is stored in NODE_3.
47507-//
47508-// Offsets are relative to the master offset from PFS_CNTL_2.
47509-// LAST_NODE is set for the last node, and only for the last node. */
47510+ * PFS_NODE_3.
47511+ * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
47512+ * first node is stored in NODE_2, the second node is stored in NODE_3.
47513+ *
47514+ * Offsets are relative to the master offset from PFS_CNTL_2.
47515+ */
47516 #define R300_PFS_NODE_0 0x4610
47517 #define R300_PFS_NODE_1 0x4614
47518 #define R300_PFS_NODE_2 0x4618
47519@@ -891,91 +996,98 @@
47520 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
47521 # define R300_PFS_NODE_TEX_END_SHIFT 17
47522 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
47523-/*# define R300_PFS_NODE_LAST_NODE (1 << 22) */
47524 # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22)
47525 # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23)
47526
47527 /* TEX
47528-// As far as I can tell, texture instructions cannot write into output
47529-// registers directly. A subsequent ALU instruction is always necessary,
47530-// even if it's just MAD o0, r0, 1, 0 */
47531+ * As far as I can tell, texture instructions cannot write into output
47532+ * registers directly. A subsequent ALU instruction is always necessary,
47533+ * even if it's just MAD o0, r0, 1, 0
47534+ */
47535 #define R300_PFS_TEXI_0 0x4620
47536-# define R300_FPITX_SRC_SHIFT 0
47537-# define R300_FPITX_SRC_MASK (31 << 0)
47538-# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */
47539-# define R300_FPITX_DST_SHIFT 6
47540-# define R300_FPITX_DST_MASK (31 << 6)
47541-# define R300_FPITX_IMAGE_SHIFT 11
47542-# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */
47543+# define R300_FPITX_SRC_SHIFT 0
47544+# define R300_FPITX_SRC_MASK (31 << 0)
47545+ /* GUESS */
47546+# define R300_FPITX_SRC_CONST (1 << 5)
47547+# define R300_FPITX_DST_SHIFT 6
47548+# define R300_FPITX_DST_MASK (31 << 6)
47549+# define R300_FPITX_IMAGE_SHIFT 11
47550+ /* GUESS based on layout and native limits */
47551+# define R300_FPITX_IMAGE_MASK (15 << 11)
47552 /* Unsure if these are opcodes, or some kind of bitfield, but this is how
47553 * they were set when I checked
47554 */
47555-# define R300_FPITX_OPCODE_SHIFT 15
47556-# define R300_FPITX_OP_TEX 1
47557-# define R300_FPITX_OP_KIL 2
47558-# define R300_FPITX_OP_TXP 3
47559-# define R300_FPITX_OP_TXB 4
47560+# define R300_FPITX_OPCODE_SHIFT 15
47561+# define R300_FPITX_OP_TEX 1
47562+# define R300_FPITX_OP_KIL 2
47563+# define R300_FPITX_OP_TXP 3
47564+# define R300_FPITX_OP_TXB 4
47565+# define R300_FPITX_OPCODE_MASK (7 << 15)
47566
47567 /* ALU
47568-// The ALU instructions register blocks are enumerated according to the order
47569-// in which fglrx. I assume there is space for 64 instructions, since
47570-// each block has space for a maximum of 64 DWORDs, and this matches reported
47571-// native limits.
47572-//
47573-// The basic functional block seems to be one MAD for each color and alpha,
47574-// and an adder that adds all components after the MUL.
47575-// - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
47576-// - DP4: Use OUTC_DP4, OUTA_DP4
47577-// - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
47578-// - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
47579-// - CMP: If ARG2 < 0, return ARG1, else return ARG0
47580-// - FLR: use FRC+MAD
47581-// - XPD: use MAD+MAD
47582-// - SGE, SLT: use MAD+CMP
47583-// - RSQ: use ABS modifier for argument
47584-// - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP)
47585-// into color register
47586-// - apparently, there's no quick DST operation
47587-// - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
47588-// - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
47589-// - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
47590-//
47591-// Operand selection
47592-// First stage selects three sources from the available registers and
47593-// constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
47594-// fglrx sorts the three source fields: Registers before constants,
47595-// lower indices before higher indices; I do not know whether this is necessary.
47596-// fglrx fills unused sources with "read constant 0"
47597-// According to specs, you cannot select more than two different constants.
47598-//
47599-// Second stage selects the operands from the sources. This is defined in
47600-// INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
47601-// zero and one.
47602-// Swizzling and negation happens in this stage, as well.
47603-//
47604-// Important: Color and alpha seem to be mostly separate, i.e. their sources
47605-// selection appears to be fully independent (the register storage is probably
47606-// physically split into a color and an alpha section).
47607-// However (because of the apparent physical split), there is some interaction
47608-// WRT swizzling. If, for example, you want to load an R component into an
47609-// Alpha operand, this R component is taken from a *color* source, not from
47610-// an alpha source. The corresponding register doesn't even have to appear in
47611-// the alpha sources list. (I hope this alll makes sense to you)
47612-//
47613-// Destination selection
47614-// The destination register index is in FPI1 (color) and FPI3 (alpha) together
47615-// with enable bits.
47616-// There are separate enable bits for writing into temporary registers
47617-// (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT).
47618-// You can write to both at once, or not write at all (the same index
47619-// must be used for both).
47620-//
47621-// Note: There is a special form for LRP
47622-// - Argument order is the same as in ARB_fragment_program.
47623-// - Operation is MAD
47624-// - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
47625-// - Set FPI0/FPI2_SPECIAL_LRP
47626-// Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */
47627+ * The ALU instructions register blocks are enumerated according to the order
47628+ * in which fglrx. I assume there is space for 64 instructions, since
47629+ * each block has space for a maximum of 64 DWORDs, and this matches reported
47630+ * native limits.
47631+ *
47632+ * The basic functional block seems to be one MAD for each color and alpha,
47633+ * and an adder that adds all components after the MUL.
47634+ * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
47635+ * - DP4: Use OUTC_DP4, OUTA_DP4
47636+ * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
47637+ * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
47638+ * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
47639+ * - CMP: If ARG2 < 0, return ARG1, else return ARG0
47640+ * - FLR: use FRC+MAD
47641+ * - XPD: use MAD+MAD
47642+ * - SGE, SLT: use MAD+CMP
47643+ * - RSQ: use ABS modifier for argument
47644+ * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
47645+ * (e.g. RCP) into color register
47646+ * - apparently, there's no quick DST operation
47647+ * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
47648+ * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
47649+ * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
47650+ *
47651+ * Operand selection
47652+ * First stage selects three sources from the available registers and
47653+ * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
47654+ * fglrx sorts the three source fields: Registers before constants,
47655+ * lower indices before higher indices; I do not know whether this is
47656+ * necessary.
47657+ *
47658+ * fglrx fills unused sources with "read constant 0"
47659+ * According to specs, you cannot select more than two different constants.
47660+ *
47661+ * Second stage selects the operands from the sources. This is defined in
47662+ * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
47663+ * zero and one.
47664+ * Swizzling and negation happens in this stage, as well.
47665+ *
47666+ * Important: Color and alpha seem to be mostly separate, i.e. their sources
47667+ * selection appears to be fully independent (the register storage is probably
47668+ * physically split into a color and an alpha section).
47669+ * However (because of the apparent physical split), there is some interaction
47670+ * WRT swizzling. If, for example, you want to load an R component into an
47671+ * Alpha operand, this R component is taken from a *color* source, not from
47672+ * an alpha source. The corresponding register doesn't even have to appear in
47673+ * the alpha sources list. (I hope this all makes sense to you)
47674+ *
47675+ * Destination selection
47676+ * The destination register index is in FPI1 (color) and FPI3 (alpha)
47677+ * together with enable bits.
47678+ * There are separate enable bits for writing into temporary registers
47679+ * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
47680+ * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
47681+ * same index must be used for both).
47682+ *
47683+ * Note: There is a special form for LRP
47684+ * - Argument order is the same as in ARB_fragment_program.
47685+ * - Operation is MAD
47686+ * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
47687+ * - Set FPI0/FPI2_SPECIAL_LRP
47688+ * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
47689+ */
47690 #define R300_PFS_INSTR1_0 0x46C0
47691 # define R300_FPI1_SRC0C_SHIFT 0
47692 # define R300_FPI1_SRC0C_MASK (31 << 0)
47693@@ -986,6 +1098,7 @@
47694 # define R300_FPI1_SRC2C_SHIFT 12
47695 # define R300_FPI1_SRC2C_MASK (31 << 12)
47696 # define R300_FPI1_SRC2C_CONST (1 << 17)
47697+# define R300_FPI1_SRC_MASK 0x0003ffff
47698 # define R300_FPI1_DSTC_SHIFT 18
47699 # define R300_FPI1_DSTC_MASK (31 << 18)
47700 # define R300_FPI1_DSTC_REG_MASK_SHIFT 23
47701@@ -1007,6 +1120,7 @@
47702 # define R300_FPI3_SRC2A_SHIFT 12
47703 # define R300_FPI3_SRC2A_MASK (31 << 12)
47704 # define R300_FPI3_SRC2A_CONST (1 << 17)
47705+# define R300_FPI3_SRC_MASK 0x0003ffff
47706 # define R300_FPI3_DSTA_SHIFT 18
47707 # define R300_FPI3_DSTA_MASK (31 << 18)
47708 # define R300_FPI3_DSTA_REG (1 << 23)
47709@@ -1032,7 +1146,8 @@
47710 # define R300_FPI0_ARGC_SRC1C_LRP 15
47711 # define R300_FPI0_ARGC_ZERO 20
47712 # define R300_FPI0_ARGC_ONE 21
47713-# define R300_FPI0_ARGC_HALF 22 /* GUESS */
47714+ /* GUESS */
47715+# define R300_FPI0_ARGC_HALF 22
47716 # define R300_FPI0_ARGC_SRC0C_YZX 23
47717 # define R300_FPI0_ARGC_SRC1C_YZX 24
47718 # define R300_FPI0_ARGC_SRC2C_YZX 25
47719@@ -1061,6 +1176,7 @@
47720 # define R300_FPI0_OUTC_DP4 (2 << 23)
47721 # define R300_FPI0_OUTC_MIN (4 << 23)
47722 # define R300_FPI0_OUTC_MAX (5 << 23)
47723+# define R300_FPI0_OUTC_CMPH (7 << 23)
47724 # define R300_FPI0_OUTC_CMP (8 << 23)
47725 # define R300_FPI0_OUTC_FRC (9 << 23)
47726 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
47727@@ -1083,20 +1199,23 @@
47728 # define R300_FPI2_ARGA_SRC1A_LRP 15
47729 # define R300_FPI2_ARGA_ZERO 16
47730 # define R300_FPI2_ARGA_ONE 17
47731-# define R300_FPI2_ARGA_HALF 18 /* GUESS */
47732-
47733+ /* GUESS */
47734+# define R300_FPI2_ARGA_HALF 18
47735 # define R300_FPI2_ARG0A_SHIFT 0
47736 # define R300_FPI2_ARG0A_MASK (31 << 0)
47737 # define R300_FPI2_ARG0A_NEG (1 << 5)
47738-# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */
47739+ /* GUESS */
47740+# define R300_FPI2_ARG0A_ABS (1 << 6)
47741 # define R300_FPI2_ARG1A_SHIFT 7
47742 # define R300_FPI2_ARG1A_MASK (31 << 7)
47743 # define R300_FPI2_ARG1A_NEG (1 << 12)
47744-# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */
47745+ /* GUESS */
47746+# define R300_FPI2_ARG1A_ABS (1 << 13)
47747 # define R300_FPI2_ARG2A_SHIFT 14
47748 # define R300_FPI2_ARG2A_MASK (31 << 14)
47749 # define R300_FPI2_ARG2A_NEG (1 << 19)
47750-# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */
47751+ /* GUESS */
47752+# define R300_FPI2_ARG2A_ABS (1 << 20)
47753 # define R300_FPI2_SPECIAL_LRP (1 << 21)
47754 # define R300_FPI2_OUTA_MAD (0 << 23)
47755 # define R300_FPI2_OUTA_DP4 (1 << 23)
47756@@ -1110,9 +1229,19 @@
47757 # define R300_FPI2_OUTA_RSQ (11 << 23)
47758 # define R300_FPI2_OUTA_SAT (1 << 30)
47759 # define R300_FPI2_UNKNOWN_31 (1 << 31)
47760-/* END */
47761+/* END: Fragment program instruction set */
47762+
47763+/* Fog state and color */
47764+#define R300_RE_FOG_STATE 0x4BC0
47765+# define R300_FOG_ENABLE (1 << 0)
47766+# define R300_FOG_MODE_LINEAR (0 << 1)
47767+# define R300_FOG_MODE_EXP (1 << 1)
47768+# define R300_FOG_MODE_EXP2 (2 << 1)
47769+# define R300_FOG_MODE_MASK (3 << 1)
47770+#define R300_FOG_COLOR_R 0x4BC8
47771+#define R300_FOG_COLOR_G 0x4BCC
47772+#define R300_FOG_COLOR_B 0x4BD0
47773
47774-/* gap */
47775 #define R300_PP_ALPHA_TEST 0x4BD4
47776 # define R300_REF_ALPHA_MASK 0x000000ff
47777 # define R300_ALPHA_TEST_FAIL (0 << 8)
47778@@ -1127,6 +1256,7 @@
47779 # define R300_ALPHA_TEST_ENABLE (1 << 11)
47780
47781 /* gap */
47782+
47783 /* Fragment program parameters in 7.16 floating point */
47784 #define R300_PFS_PARAM_0_X 0x4C00
47785 #define R300_PFS_PARAM_0_Y 0x4C04
47786@@ -1139,45 +1269,48 @@
47787 #define R300_PFS_PARAM_31_W 0x4DFC
47788
47789 /* Notes:
47790-// - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application
47791-// - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same
47792-// function (both registers are always set up completely in any case)
47793-// - Most blend flags are simply copied from R200 and not tested yet */
47794+ * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
47795+ * the application
47796+ * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
47797+ * are set to the same
47798+ * function (both registers are always set up completely in any case)
47799+ * - Most blend flags are simply copied from R200 and not tested yet
47800+ */
47801 #define R300_RB3D_CBLEND 0x4E04
47802 #define R300_RB3D_ABLEND 0x4E08
47803- /* the following only appear in CBLEND */
47804+/* the following only appear in CBLEND */
47805 # define R300_BLEND_ENABLE (1 << 0)
47806 # define R300_BLEND_UNKNOWN (3 << 1)
47807 # define R300_BLEND_NO_SEPARATE (1 << 3)
47808- /* the following are shared between CBLEND and ABLEND */
47809+/* the following are shared between CBLEND and ABLEND */
47810 # define R300_FCN_MASK (3 << 12)
47811 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
47812 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
47813 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
47814 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
47815-# define R300_SRC_BLEND_GL_ZERO (32 << 16)
47816-# define R300_SRC_BLEND_GL_ONE (33 << 16)
47817-# define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16)
47818-# define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
47819-# define R300_SRC_BLEND_GL_DST_COLOR (36 << 16)
47820-# define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
47821-# define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
47822-# define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
47823-# define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16)
47824-# define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
47825-# define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
47826-# define R300_SRC_BLEND_MASK (63 << 16)
47827-# define R300_DST_BLEND_GL_ZERO (32 << 24)
47828-# define R300_DST_BLEND_GL_ONE (33 << 24)
47829-# define R300_DST_BLEND_GL_SRC_COLOR (34 << 24)
47830-# define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
47831-# define R300_DST_BLEND_GL_DST_COLOR (36 << 24)
47832-# define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
47833-# define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24)
47834-# define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
47835-# define R300_DST_BLEND_GL_DST_ALPHA (40 << 24)
47836-# define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
47837-# define R300_DST_BLEND_MASK (63 << 24)
47838+# define R300_COMB_FCN_MIN (4 << 12)
47839+# define R300_COMB_FCN_MAX (5 << 12)
47840+# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
47841+# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
47842+# define R300_BLEND_GL_ZERO (32)
47843+# define R300_BLEND_GL_ONE (33)
47844+# define R300_BLEND_GL_SRC_COLOR (34)
47845+# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
47846+# define R300_BLEND_GL_DST_COLOR (36)
47847+# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
47848+# define R300_BLEND_GL_SRC_ALPHA (38)
47849+# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
47850+# define R300_BLEND_GL_DST_ALPHA (40)
47851+# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
47852+# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
47853+# define R300_BLEND_GL_CONST_COLOR (43)
47854+# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
47855+# define R300_BLEND_GL_CONST_ALPHA (45)
47856+# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
47857+# define R300_BLEND_MASK (63)
47858+# define R300_SRC_BLEND_SHIFT (16)
47859+# define R300_DST_BLEND_SHIFT (24)
47860+#define R300_RB3D_BLEND_COLOR 0x4E10
47861 #define R300_RB3D_COLORMASK 0x4E0C
47862 # define R300_COLORMASK0_B (1<<0)
47863 # define R300_COLORMASK0_G (1<<1)
47864@@ -1185,15 +1318,19 @@
47865 # define R300_COLORMASK0_A (1<<3)
47866
47867 /* gap */
47868+
47869 #define R300_RB3D_COLOROFFSET0 0x4E28
47870 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
47871 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
47872 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
47873 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
47874+
47875 /* gap */
47876+
47877 /* Bit 16: Larger tiles
47878-// Bit 17: 4x2 tiles
47879-// Bit 18: Extremely weird tile like, but some pixels duplicated? */
47880+ * Bit 17: 4x2 tiles
47881+ * Bit 18: Extremely weird tile like, but some pixels duplicated?
47882+ */
47883 #define R300_RB3D_COLORPITCH0 0x4E38
47884 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
47885 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
47886@@ -1208,29 +1345,33 @@
47887 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
47888
47889 /* gap */
47890+
47891 /* Guess by Vladimir.
47892-// Set to 0A before 3D operations, set to 02 afterwards. */
47893+ * Set to 0A before 3D operations, set to 02 afterwards.
47894+ */
47895 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
47896-# define R300_RB3D_DSTCACHE_02 0x00000002
47897-# define R300_RB3D_DSTCACHE_0A 0x0000000A
47898+# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
47899+# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
47900
47901 /* gap */
47902-/* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */
47903-/* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */
47904+/* There seems to be no "write only" setting, so use Z-test = ALWAYS
47905+ * for this.
47906+ * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
47907+ */
47908 #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
47909-# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */
47910-# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */
47911+# define R300_RB3D_Z_DISABLED_1 0x00000010
47912+# define R300_RB3D_Z_DISABLED_2 0x00000014
47913 # define R300_RB3D_Z_TEST 0x00000012
47914 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
47915-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
47916+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
47917
47918 # define R300_RB3D_Z_TEST 0x00000012
47919 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
47920-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
47921+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
47922 # define R300_RB3D_STENCIL_ENABLE 0x00000001
47923
47924 #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
47925- /* functions */
47926+ /* functions */
47927 # define R300_ZS_NEVER 0
47928 # define R300_ZS_LESS 1
47929 # define R300_ZS_LEQUAL 2
47930@@ -1240,7 +1381,7 @@
47931 # define R300_ZS_NOTEQUAL 6
47932 # define R300_ZS_ALWAYS 7
47933 # define R300_ZS_MASK 7
47934- /* operations */
47935+ /* operations */
47936 # define R300_ZS_KEEP 0
47937 # define R300_ZS_ZERO 1
47938 # define R300_ZS_REPLACE 2
47939@@ -1249,9 +1390,8 @@
47940 # define R300_ZS_INVERT 5
47941 # define R300_ZS_INCR_WRAP 6
47942 # define R300_ZS_DECR_WRAP 7
47943-
47944- /* front and back refer to operations done for front
47945- and back faces, i.e. separate stencil function support */
47946+ /* front and back refer to operations done for front
47947+ and back faces, i.e. separate stencil function support */
47948 # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
47949 # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
47950 # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
47951@@ -1262,8 +1402,6 @@
47952 # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
47953 # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
47954
47955-
47956-
47957 #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
47958 # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
47959 # define R300_RB3D_ZS2_STENCIL_MASK 0xFF
47960@@ -1275,8 +1413,21 @@
47961 #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
47962 # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
47963 # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
47964+ /* 16 bit format or some aditional bit ? */
47965+# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
47966+
47967+#define R300_RB3D_EARLY_Z 0x4F14
47968+# define R300_EARLY_Z_DISABLE (0 << 0)
47969+# define R300_EARLY_Z_ENABLE (1 << 0)
47970+
47971+/* gap */
47972+
47973+#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
47974+# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
47975+# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
47976
47977 /* gap */
47978+
47979 #define R300_RB3D_DEPTHOFFSET 0x4F20
47980 #define R300_RB3D_DEPTHPITCH 0x4F24
47981 # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
47982@@ -1286,34 +1437,40 @@
47983 # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
47984 # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
47985
47986-/* BEGIN: Vertex program instruction set
47987-// Every instruction is four dwords long:
47988-// DWORD 0: output and opcode
47989-// DWORD 1: first argument
47990-// DWORD 2: second argument
47991-// DWORD 3: third argument
47992-//
47993-// Notes:
47994-// - ABS r, a is implemented as MAX r, a, -a
47995-// - MOV is implemented as ADD to zero
47996-// - XPD is implemented as MUL + MAD
47997-// - FLR is implemented as FRC + ADD
47998-// - apparently, fglrx tries to schedule instructions so that there is at least
47999-// one instruction between the write to a temporary and the first read
48000-// from said temporary; however, violations of this scheduling are allowed
48001-// - register indices seem to be unrelated with OpenGL aliasing to conventional state
48002-// - only one attribute and one parameter can be loaded at a time; however, the
48003-// same attribute/parameter can be used for more than one argument
48004-// - the second software argument for POW is the third hardware argument (no idea why)
48005-// - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
48006-//
48007-// There is some magic surrounding LIT:
48008-// The single argument is replicated across all three inputs, but swizzled:
48009-// First argument: xyzy
48010-// Second argument: xyzx
48011-// Third argument: xyzw
48012-// Whenever the result is used later in the fragment program, fglrx forces x and w
48013-// to be 1.0 in the input selection; I don't know whether this is strictly necessary */
48014+/* BEGIN: Vertex program instruction set */
48015+
48016+/* Every instruction is four dwords long:
48017+ * DWORD 0: output and opcode
48018+ * DWORD 1: first argument
48019+ * DWORD 2: second argument
48020+ * DWORD 3: third argument
48021+ *
48022+ * Notes:
48023+ * - ABS r, a is implemented as MAX r, a, -a
48024+ * - MOV is implemented as ADD to zero
48025+ * - XPD is implemented as MUL + MAD
48026+ * - FLR is implemented as FRC + ADD
48027+ * - apparently, fglrx tries to schedule instructions so that there is at
48028+ * least one instruction between the write to a temporary and the first
48029+ * read from said temporary; however, violations of this scheduling are
48030+ * allowed
48031+ * - register indices seem to be unrelated with OpenGL aliasing to
48032+ * conventional state
48033+ * - only one attribute and one parameter can be loaded at a time; however,
48034+ * the same attribute/parameter can be used for more than one argument
48035+ * - the second software argument for POW is the third hardware argument
48036+ * (no idea why)
48037+ * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
48038+ *
48039+ * There is some magic surrounding LIT:
48040+ * The single argument is replicated across all three inputs, but swizzled:
48041+ * First argument: xyzy
48042+ * Second argument: xyzx
48043+ * Third argument: xyzw
48044+ * Whenever the result is used later in the fragment program, fglrx forces
48045+ * x and w to be 1.0 in the input selection; I don't know whether this is
48046+ * strictly necessary
48047+ */
48048 #define R300_VPI_OUT_OP_DOT (1 << 0)
48049 #define R300_VPI_OUT_OP_MUL (2 << 0)
48050 #define R300_VPI_OUT_OP_ADD (3 << 0)
48051@@ -1324,26 +1481,33 @@
48052 #define R300_VPI_OUT_OP_MIN (8 << 0)
48053 #define R300_VPI_OUT_OP_SGE (9 << 0)
48054 #define R300_VPI_OUT_OP_SLT (10 << 0)
48055-#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
48056+ /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
48057+#define R300_VPI_OUT_OP_UNK12 (12 << 0)
48058+#define R300_VPI_OUT_OP_ARL (13 << 0)
48059 #define R300_VPI_OUT_OP_EXP (65 << 0)
48060 #define R300_VPI_OUT_OP_LOG (66 << 0)
48061-#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */
48062+ /* Used in fog computations, scalar(scalar) */
48063+#define R300_VPI_OUT_OP_UNK67 (67 << 0)
48064 #define R300_VPI_OUT_OP_LIT (68 << 0)
48065 #define R300_VPI_OUT_OP_POW (69 << 0)
48066 #define R300_VPI_OUT_OP_RCP (70 << 0)
48067 #define R300_VPI_OUT_OP_RSQ (72 << 0)
48068-#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
48069+ /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
48070+#define R300_VPI_OUT_OP_UNK73 (73 << 0)
48071 #define R300_VPI_OUT_OP_EX2 (75 << 0)
48072 #define R300_VPI_OUT_OP_LG2 (76 << 0)
48073 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
48074-#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */
48075+ /* all temps, vector(scalar, vector, vector) */
48076+#define R300_VPI_OUT_OP_UNK129 (129 << 0)
48077
48078 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
48079+#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)
48080 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
48081 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
48082
48083 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
48084-#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */
48085+ /* GUESS based on fglrx native limits */
48086+#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)
48087
48088 #define R300_VPI_OUT_WRITE_X (1 << 20)
48089 #define R300_VPI_OUT_WRITE_Y (1 << 21)
48090@@ -1354,14 +1518,16 @@
48091 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
48092 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
48093 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
48094-#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */
48095+#define R300_VPI_IN_REG_CLASS_MASK (31 << 0)
48096
48097 #define R300_VPI_IN_REG_INDEX_SHIFT 5
48098-#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */
48099+ /* GUESS based on fglrx native limits */
48100+#define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
48101
48102 /* The R300 can select components from the input register arbitrarily.
48103-// Use the following constants, shifted by the component shift you
48104-// want to select */
48105+ * Use the following constants, shifted by the component shift you
48106+ * want to select
48107+ */
48108 #define R300_VPI_IN_SELECT_X 0
48109 #define R300_VPI_IN_SELECT_Y 1
48110 #define R300_VPI_IN_SELECT_Z 2
48111@@ -1379,11 +1545,11 @@
48112 #define R300_VPI_IN_NEG_Y (1 << 26)
48113 #define R300_VPI_IN_NEG_Z (1 << 27)
48114 #define R300_VPI_IN_NEG_W (1 << 28)
48115-/* END */
48116+/* END: Vertex program instruction set */
48117
48118-//BEGIN: Packet 3 commands
48119+/* BEGIN: Packet 3 commands */
48120
48121-// A primitive emission dword.
48122+/* A primitive emission dword. */
48123 #define R300_PRIM_TYPE_NONE (0 << 0)
48124 #define R300_PRIM_TYPE_POINT (1 << 0)
48125 #define R300_PRIM_TYPE_LINE (2 << 0)
48126@@ -1395,7 +1561,8 @@
48127 #define R300_PRIM_TYPE_RECT_LIST (8 << 0)
48128 #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
48129 #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
48130-#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200)
48131+ /* GUESS (based on r200) */
48132+#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
48133 #define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
48134 #define R300_PRIM_TYPE_QUADS (13 << 0)
48135 #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
48136@@ -1405,37 +1572,60 @@
48137 #define R300_PRIM_WALK_LIST (2 << 4)
48138 #define R300_PRIM_WALK_RING (3 << 4)
48139 #define R300_PRIM_WALK_MASK (3 << 4)
48140-#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200)
48141-#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS
48142+ /* GUESS (based on r200) */
48143+#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
48144+#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
48145 #define R300_PRIM_NUM_VERTICES_SHIFT 16
48146+#define R300_PRIM_NUM_VERTICES_MASK 0xffff
48147
48148-// Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
48149-// Two parameter dwords:
48150-// 0. The first parameter appears to be always 0
48151-// 1. The second parameter is a standard primitive emission dword.
48152+/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
48153+ * Two parameter dwords:
48154+ * 0. The first parameter appears to be always 0
48155+ * 1. The second parameter is a standard primitive emission dword.
48156+ */
48157 #define R300_PACKET3_3D_DRAW_VBUF 0x00002800
48158
48159-// Specify the full set of vertex arrays as (address, stride).
48160-// The first parameter is the number of vertex arrays specified.
48161-// The rest of the command is a variable length list of blocks, where
48162-// each block is three dwords long and specifies two arrays.
48163-// The first dword of a block is split into two words, the lower significant
48164-// word refers to the first array, the more significant word to the second
48165-// array in the block.
48166-// The low byte of each word contains the size of an array entry in dwords,
48167-// the high byte contains the stride of the array.
48168-// The second dword of a block contains the pointer to the first array,
48169-// the third dword of a block contains the pointer to the second array.
48170-// Note that if the total number of arrays is odd, the third dword of
48171-// the last block is omitted.
48172+/* Specify the full set of vertex arrays as (address, stride).
48173+ * The first parameter is the number of vertex arrays specified.
48174+ * The rest of the command is a variable length list of blocks, where
48175+ * each block is three dwords long and specifies two arrays.
48176+ * The first dword of a block is split into two words, the lower significant
48177+ * word refers to the first array, the more significant word to the second
48178+ * array in the block.
48179+ * The low byte of each word contains the size of an array entry in dwords,
48180+ * the high byte contains the stride of the array.
48181+ * The second dword of a block contains the pointer to the first array,
48182+ * the third dword of a block contains the pointer to the second array.
48183+ * Note that if the total number of arrays is odd, the third dword of
48184+ * the last block is omitted.
48185+ */
48186 #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
48187
48188 #define R300_PACKET3_INDX_BUFFER 0x00003300
48189 # define R300_EB_UNK1_SHIFT 24
48190 # define R300_EB_UNK1 (0x80<<24)
48191 # define R300_EB_UNK2 0x0810
48192+#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
48193 #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
48194
48195-//END
48196+/* END: Packet 3 commands */
48197+
48198+
48199+/* Color formats for 2d packets
48200+ */
48201+#define R300_CP_COLOR_FORMAT_CI8 2
48202+#define R300_CP_COLOR_FORMAT_ARGB1555 3
48203+#define R300_CP_COLOR_FORMAT_RGB565 4
48204+#define R300_CP_COLOR_FORMAT_ARGB8888 6
48205+#define R300_CP_COLOR_FORMAT_RGB332 7
48206+#define R300_CP_COLOR_FORMAT_RGB8 9
48207+#define R300_CP_COLOR_FORMAT_ARGB4444 15
48208+
48209+/*
48210+ * CP type-3 packets
48211+ */
48212+#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
48213
48214 #endif /* _R300_REG_H */
48215+
48216+/* *INDENT-ON* */
48217Index: git/shared-core/radeon_cp.c
48218===================================================================
48219--- /dev/null 1970-01-01 00:00:00.000000000 +0000
48220+++ git/shared-core/radeon_cp.c 2008-12-12 17:35:22.000000000 +0000
48221@@ -0,0 +1,2316 @@
48222+/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
48223+/*
48224+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
48225+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
48226+ * All Rights Reserved.
48227+ *
48228+ * Permission is hereby granted, free of charge, to any person obtaining a
48229+ * copy of this software and associated documentation files (the "Software"),
48230+ * to deal in the Software without restriction, including without limitation
48231+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
48232+ * and/or sell copies of the Software, and to permit persons to whom the
48233+ * Software is furnished to do so, subject to the following conditions:
48234+ *
48235+ * The above copyright notice and this permission notice (including the next
48236+ * paragraph) shall be included in all copies or substantial portions of the
48237+ * Software.
48238+ *
48239+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48240+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
48241+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
48242+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
48243+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
48244+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48245+ * DEALINGS IN THE SOFTWARE.
48246+ *
48247+ * Authors:
48248+ * Kevin E. Martin <martin@valinux.com>
48249+ * Gareth Hughes <gareth@valinux.com>
48250+ */
48251+
48252+#include "drmP.h"
48253+#include "drm.h"
48254+#include "radeon_drm.h"
48255+#include "radeon_drv.h"
48256+#include "r300_reg.h"
48257+
48258+#define RADEON_FIFO_DEBUG 0
48259+
48260+static int radeon_do_cleanup_cp(struct drm_device * dev);
48261+
48262+/* CP microcode (from ATI) */
48263+static const u32 R200_cp_microcode[][2] = {
48264+ {0x21007000, 0000000000},
48265+ {0x20007000, 0000000000},
48266+ {0x000000ab, 0x00000004},
48267+ {0x000000af, 0x00000004},
48268+ {0x66544a49, 0000000000},
48269+ {0x49494174, 0000000000},
48270+ {0x54517d83, 0000000000},
48271+ {0x498d8b64, 0000000000},
48272+ {0x49494949, 0000000000},
48273+ {0x49da493c, 0000000000},
48274+ {0x49989898, 0000000000},
48275+ {0xd34949d5, 0000000000},
48276+ {0x9dc90e11, 0000000000},
48277+ {0xce9b9b9b, 0000000000},
48278+ {0x000f0000, 0x00000016},
48279+ {0x352e232c, 0000000000},
48280+ {0x00000013, 0x00000004},
48281+ {0x000f0000, 0x00000016},
48282+ {0x352e272c, 0000000000},
48283+ {0x000f0001, 0x00000016},
48284+ {0x3239362f, 0000000000},
48285+ {0x000077ef, 0x00000002},
48286+ {0x00061000, 0x00000002},
48287+ {0x00000020, 0x0000001a},
48288+ {0x00004000, 0x0000001e},
48289+ {0x00061000, 0x00000002},
48290+ {0x00000020, 0x0000001a},
48291+ {0x00004000, 0x0000001e},
48292+ {0x00061000, 0x00000002},
48293+ {0x00000020, 0x0000001a},
48294+ {0x00004000, 0x0000001e},
48295+ {0x00000016, 0x00000004},
48296+ {0x0003802a, 0x00000002},
48297+ {0x040067e0, 0x00000002},
48298+ {0x00000016, 0x00000004},
48299+ {0x000077e0, 0x00000002},
48300+ {0x00065000, 0x00000002},
48301+ {0x000037e1, 0x00000002},
48302+ {0x040067e1, 0x00000006},
48303+ {0x000077e0, 0x00000002},
48304+ {0x000077e1, 0x00000002},
48305+ {0x000077e1, 0x00000006},
48306+ {0xffffffff, 0000000000},
48307+ {0x10000000, 0000000000},
48308+ {0x0003802a, 0x00000002},
48309+ {0x040067e0, 0x00000006},
48310+ {0x00007675, 0x00000002},
48311+ {0x00007676, 0x00000002},
48312+ {0x00007677, 0x00000002},
48313+ {0x00007678, 0x00000006},
48314+ {0x0003802b, 0x00000002},
48315+ {0x04002676, 0x00000002},
48316+ {0x00007677, 0x00000002},
48317+ {0x00007678, 0x00000006},
48318+ {0x0000002e, 0x00000018},
48319+ {0x0000002e, 0x00000018},
48320+ {0000000000, 0x00000006},
48321+ {0x0000002f, 0x00000018},
48322+ {0x0000002f, 0x00000018},
48323+ {0000000000, 0x00000006},
48324+ {0x01605000, 0x00000002},
48325+ {0x00065000, 0x00000002},
48326+ {0x00098000, 0x00000002},
48327+ {0x00061000, 0x00000002},
48328+ {0x64c0603d, 0x00000004},
48329+ {0x00080000, 0x00000016},
48330+ {0000000000, 0000000000},
48331+ {0x0400251d, 0x00000002},
48332+ {0x00007580, 0x00000002},
48333+ {0x00067581, 0x00000002},
48334+ {0x04002580, 0x00000002},
48335+ {0x00067581, 0x00000002},
48336+ {0x00000046, 0x00000004},
48337+ {0x00005000, 0000000000},
48338+ {0x00061000, 0x00000002},
48339+ {0x0000750e, 0x00000002},
48340+ {0x00019000, 0x00000002},
48341+ {0x00011055, 0x00000014},
48342+ {0x00000055, 0x00000012},
48343+ {0x0400250f, 0x00000002},
48344+ {0x0000504a, 0x00000004},
48345+ {0x00007565, 0x00000002},
48346+ {0x00007566, 0x00000002},
48347+ {0x00000051, 0x00000004},
48348+ {0x01e655b4, 0x00000002},
48349+ {0x4401b0dc, 0x00000002},
48350+ {0x01c110dc, 0x00000002},
48351+ {0x2666705d, 0x00000018},
48352+ {0x040c2565, 0x00000002},
48353+ {0x0000005d, 0x00000018},
48354+ {0x04002564, 0x00000002},
48355+ {0x00007566, 0x00000002},
48356+ {0x00000054, 0x00000004},
48357+ {0x00401060, 0x00000008},
48358+ {0x00101000, 0x00000002},
48359+ {0x000d80ff, 0x00000002},
48360+ {0x00800063, 0x00000008},
48361+ {0x000f9000, 0x00000002},
48362+ {0x000e00ff, 0x00000002},
48363+ {0000000000, 0x00000006},
48364+ {0x00000080, 0x00000018},
48365+ {0x00000054, 0x00000004},
48366+ {0x00007576, 0x00000002},
48367+ {0x00065000, 0x00000002},
48368+ {0x00009000, 0x00000002},
48369+ {0x00041000, 0x00000002},
48370+ {0x0c00350e, 0x00000002},
48371+ {0x00049000, 0x00000002},
48372+ {0x00051000, 0x00000002},
48373+ {0x01e785f8, 0x00000002},
48374+ {0x00200000, 0x00000002},
48375+ {0x00600073, 0x0000000c},
48376+ {0x00007563, 0x00000002},
48377+ {0x006075f0, 0x00000021},
48378+ {0x20007068, 0x00000004},
48379+ {0x00005068, 0x00000004},
48380+ {0x00007576, 0x00000002},
48381+ {0x00007577, 0x00000002},
48382+ {0x0000750e, 0x00000002},
48383+ {0x0000750f, 0x00000002},
48384+ {0x00a05000, 0x00000002},
48385+ {0x00600076, 0x0000000c},
48386+ {0x006075f0, 0x00000021},
48387+ {0x000075f8, 0x00000002},
48388+ {0x00000076, 0x00000004},
48389+ {0x000a750e, 0x00000002},
48390+ {0x0020750f, 0x00000002},
48391+ {0x00600079, 0x00000004},
48392+ {0x00007570, 0x00000002},
48393+ {0x00007571, 0x00000002},
48394+ {0x00007572, 0x00000006},
48395+ {0x00005000, 0x00000002},
48396+ {0x00a05000, 0x00000002},
48397+ {0x00007568, 0x00000002},
48398+ {0x00061000, 0x00000002},
48399+ {0x00000084, 0x0000000c},
48400+ {0x00058000, 0x00000002},
48401+ {0x0c607562, 0x00000002},
48402+ {0x00000086, 0x00000004},
48403+ {0x00600085, 0x00000004},
48404+ {0x400070dd, 0000000000},
48405+ {0x000380dd, 0x00000002},
48406+ {0x00000093, 0x0000001c},
48407+ {0x00065095, 0x00000018},
48408+ {0x040025bb, 0x00000002},
48409+ {0x00061096, 0x00000018},
48410+ {0x040075bc, 0000000000},
48411+ {0x000075bb, 0x00000002},
48412+ {0x000075bc, 0000000000},
48413+ {0x00090000, 0x00000006},
48414+ {0x00090000, 0x00000002},
48415+ {0x000d8002, 0x00000006},
48416+ {0x00005000, 0x00000002},
48417+ {0x00007821, 0x00000002},
48418+ {0x00007800, 0000000000},
48419+ {0x00007821, 0x00000002},
48420+ {0x00007800, 0000000000},
48421+ {0x01665000, 0x00000002},
48422+ {0x000a0000, 0x00000002},
48423+ {0x000671cc, 0x00000002},
48424+ {0x0286f1cd, 0x00000002},
48425+ {0x000000a3, 0x00000010},
48426+ {0x21007000, 0000000000},
48427+ {0x000000aa, 0x0000001c},
48428+ {0x00065000, 0x00000002},
48429+ {0x000a0000, 0x00000002},
48430+ {0x00061000, 0x00000002},
48431+ {0x000b0000, 0x00000002},
48432+ {0x38067000, 0x00000002},
48433+ {0x000a00a6, 0x00000004},
48434+ {0x20007000, 0000000000},
48435+ {0x01200000, 0x00000002},
48436+ {0x20077000, 0x00000002},
48437+ {0x01200000, 0x00000002},
48438+ {0x20007000, 0000000000},
48439+ {0x00061000, 0x00000002},
48440+ {0x0120751b, 0x00000002},
48441+ {0x8040750a, 0x00000002},
48442+ {0x8040750b, 0x00000002},
48443+ {0x00110000, 0x00000002},
48444+ {0x000380dd, 0x00000002},
48445+ {0x000000bd, 0x0000001c},
48446+ {0x00061096, 0x00000018},
48447+ {0x844075bd, 0x00000002},
48448+ {0x00061095, 0x00000018},
48449+ {0x840075bb, 0x00000002},
48450+ {0x00061096, 0x00000018},
48451+ {0x844075bc, 0x00000002},
48452+ {0x000000c0, 0x00000004},
48453+ {0x804075bd, 0x00000002},
48454+ {0x800075bb, 0x00000002},
48455+ {0x804075bc, 0x00000002},
48456+ {0x00108000, 0x00000002},
48457+ {0x01400000, 0x00000002},
48458+ {0x006000c4, 0x0000000c},
48459+ {0x20c07000, 0x00000020},
48460+ {0x000000c6, 0x00000012},
48461+ {0x00800000, 0x00000006},
48462+ {0x0080751d, 0x00000006},
48463+ {0x000025bb, 0x00000002},
48464+ {0x000040c0, 0x00000004},
48465+ {0x0000775c, 0x00000002},
48466+ {0x00a05000, 0x00000002},
48467+ {0x00661000, 0x00000002},
48468+ {0x0460275d, 0x00000020},
48469+ {0x00004000, 0000000000},
48470+ {0x00007999, 0x00000002},
48471+ {0x00a05000, 0x00000002},
48472+ {0x00661000, 0x00000002},
48473+ {0x0460299b, 0x00000020},
48474+ {0x00004000, 0000000000},
48475+ {0x01e00830, 0x00000002},
48476+ {0x21007000, 0000000000},
48477+ {0x00005000, 0x00000002},
48478+ {0x00038042, 0x00000002},
48479+ {0x040025e0, 0x00000002},
48480+ {0x000075e1, 0000000000},
48481+ {0x00000001, 0000000000},
48482+ {0x000380d9, 0x00000002},
48483+ {0x04007394, 0000000000},
48484+ {0000000000, 0000000000},
48485+ {0000000000, 0000000000},
48486+ {0000000000, 0000000000},
48487+ {0000000000, 0000000000},
48488+ {0000000000, 0000000000},
48489+ {0000000000, 0000000000},
48490+ {0000000000, 0000000000},
48491+ {0000000000, 0000000000},
48492+ {0000000000, 0000000000},
48493+ {0000000000, 0000000000},
48494+ {0000000000, 0000000000},
48495+ {0000000000, 0000000000},
48496+ {0000000000, 0000000000},
48497+ {0000000000, 0000000000},
48498+ {0000000000, 0000000000},
48499+ {0000000000, 0000000000},
48500+ {0000000000, 0000000000},
48501+ {0000000000, 0000000000},
48502+ {0000000000, 0000000000},
48503+ {0000000000, 0000000000},
48504+ {0000000000, 0000000000},
48505+ {0000000000, 0000000000},
48506+ {0000000000, 0000000000},
48507+ {0000000000, 0000000000},
48508+ {0000000000, 0000000000},
48509+ {0000000000, 0000000000},
48510+ {0000000000, 0000000000},
48511+ {0000000000, 0000000000},
48512+ {0000000000, 0000000000},
48513+ {0000000000, 0000000000},
48514+ {0000000000, 0000000000},
48515+ {0000000000, 0000000000},
48516+ {0000000000, 0000000000},
48517+ {0000000000, 0000000000},
48518+ {0000000000, 0000000000},
48519+ {0000000000, 0000000000},
48520+};
48521+
48522+static const u32 radeon_cp_microcode[][2] = {
48523+ {0x21007000, 0000000000},
48524+ {0x20007000, 0000000000},
48525+ {0x000000b4, 0x00000004},
48526+ {0x000000b8, 0x00000004},
48527+ {0x6f5b4d4c, 0000000000},
48528+ {0x4c4c427f, 0000000000},
48529+ {0x5b568a92, 0000000000},
48530+ {0x4ca09c6d, 0000000000},
48531+ {0xad4c4c4c, 0000000000},
48532+ {0x4ce1af3d, 0000000000},
48533+ {0xd8afafaf, 0000000000},
48534+ {0xd64c4cdc, 0000000000},
48535+ {0x4cd10d10, 0000000000},
48536+ {0x000f0000, 0x00000016},
48537+ {0x362f242d, 0000000000},
48538+ {0x00000012, 0x00000004},
48539+ {0x000f0000, 0x00000016},
48540+ {0x362f282d, 0000000000},
48541+ {0x000380e7, 0x00000002},
48542+ {0x04002c97, 0x00000002},
48543+ {0x000f0001, 0x00000016},
48544+ {0x333a3730, 0000000000},
48545+ {0x000077ef, 0x00000002},
48546+ {0x00061000, 0x00000002},
48547+ {0x00000021, 0x0000001a},
48548+ {0x00004000, 0x0000001e},
48549+ {0x00061000, 0x00000002},
48550+ {0x00000021, 0x0000001a},
48551+ {0x00004000, 0x0000001e},
48552+ {0x00061000, 0x00000002},
48553+ {0x00000021, 0x0000001a},
48554+ {0x00004000, 0x0000001e},
48555+ {0x00000017, 0x00000004},
48556+ {0x0003802b, 0x00000002},
48557+ {0x040067e0, 0x00000002},
48558+ {0x00000017, 0x00000004},
48559+ {0x000077e0, 0x00000002},
48560+ {0x00065000, 0x00000002},
48561+ {0x000037e1, 0x00000002},
48562+ {0x040067e1, 0x00000006},
48563+ {0x000077e0, 0x00000002},
48564+ {0x000077e1, 0x00000002},
48565+ {0x000077e1, 0x00000006},
48566+ {0xffffffff, 0000000000},
48567+ {0x10000000, 0000000000},
48568+ {0x0003802b, 0x00000002},
48569+ {0x040067e0, 0x00000006},
48570+ {0x00007675, 0x00000002},
48571+ {0x00007676, 0x00000002},
48572+ {0x00007677, 0x00000002},
48573+ {0x00007678, 0x00000006},
48574+ {0x0003802c, 0x00000002},
48575+ {0x04002676, 0x00000002},
48576+ {0x00007677, 0x00000002},
48577+ {0x00007678, 0x00000006},
48578+ {0x0000002f, 0x00000018},
48579+ {0x0000002f, 0x00000018},
48580+ {0000000000, 0x00000006},
48581+ {0x00000030, 0x00000018},
48582+ {0x00000030, 0x00000018},
48583+ {0000000000, 0x00000006},
48584+ {0x01605000, 0x00000002},
48585+ {0x00065000, 0x00000002},
48586+ {0x00098000, 0x00000002},
48587+ {0x00061000, 0x00000002},
48588+ {0x64c0603e, 0x00000004},
48589+ {0x000380e6, 0x00000002},
48590+ {0x040025c5, 0x00000002},
48591+ {0x00080000, 0x00000016},
48592+ {0000000000, 0000000000},
48593+ {0x0400251d, 0x00000002},
48594+ {0x00007580, 0x00000002},
48595+ {0x00067581, 0x00000002},
48596+ {0x04002580, 0x00000002},
48597+ {0x00067581, 0x00000002},
48598+ {0x00000049, 0x00000004},
48599+ {0x00005000, 0000000000},
48600+ {0x000380e6, 0x00000002},
48601+ {0x040025c5, 0x00000002},
48602+ {0x00061000, 0x00000002},
48603+ {0x0000750e, 0x00000002},
48604+ {0x00019000, 0x00000002},
48605+ {0x00011055, 0x00000014},
48606+ {0x00000055, 0x00000012},
48607+ {0x0400250f, 0x00000002},
48608+ {0x0000504f, 0x00000004},
48609+ {0x000380e6, 0x00000002},
48610+ {0x040025c5, 0x00000002},
48611+ {0x00007565, 0x00000002},
48612+ {0x00007566, 0x00000002},
48613+ {0x00000058, 0x00000004},
48614+ {0x000380e6, 0x00000002},
48615+ {0x040025c5, 0x00000002},
48616+ {0x01e655b4, 0x00000002},
48617+ {0x4401b0e4, 0x00000002},
48618+ {0x01c110e4, 0x00000002},
48619+ {0x26667066, 0x00000018},
48620+ {0x040c2565, 0x00000002},
48621+ {0x00000066, 0x00000018},
48622+ {0x04002564, 0x00000002},
48623+ {0x00007566, 0x00000002},
48624+ {0x0000005d, 0x00000004},
48625+ {0x00401069, 0x00000008},
48626+ {0x00101000, 0x00000002},
48627+ {0x000d80ff, 0x00000002},
48628+ {0x0080006c, 0x00000008},
48629+ {0x000f9000, 0x00000002},
48630+ {0x000e00ff, 0x00000002},
48631+ {0000000000, 0x00000006},
48632+ {0x0000008f, 0x00000018},
48633+ {0x0000005b, 0x00000004},
48634+ {0x000380e6, 0x00000002},
48635+ {0x040025c5, 0x00000002},
48636+ {0x00007576, 0x00000002},
48637+ {0x00065000, 0x00000002},
48638+ {0x00009000, 0x00000002},
48639+ {0x00041000, 0x00000002},
48640+ {0x0c00350e, 0x00000002},
48641+ {0x00049000, 0x00000002},
48642+ {0x00051000, 0x00000002},
48643+ {0x01e785f8, 0x00000002},
48644+ {0x00200000, 0x00000002},
48645+ {0x0060007e, 0x0000000c},
48646+ {0x00007563, 0x00000002},
48647+ {0x006075f0, 0x00000021},
48648+ {0x20007073, 0x00000004},
48649+ {0x00005073, 0x00000004},
48650+ {0x000380e6, 0x00000002},
48651+ {0x040025c5, 0x00000002},
48652+ {0x00007576, 0x00000002},
48653+ {0x00007577, 0x00000002},
48654+ {0x0000750e, 0x00000002},
48655+ {0x0000750f, 0x00000002},
48656+ {0x00a05000, 0x00000002},
48657+ {0x00600083, 0x0000000c},
48658+ {0x006075f0, 0x00000021},
48659+ {0x000075f8, 0x00000002},
48660+ {0x00000083, 0x00000004},
48661+ {0x000a750e, 0x00000002},
48662+ {0x000380e6, 0x00000002},
48663+ {0x040025c5, 0x00000002},
48664+ {0x0020750f, 0x00000002},
48665+ {0x00600086, 0x00000004},
48666+ {0x00007570, 0x00000002},
48667+ {0x00007571, 0x00000002},
48668+ {0x00007572, 0x00000006},
48669+ {0x000380e6, 0x00000002},
48670+ {0x040025c5, 0x00000002},
48671+ {0x00005000, 0x00000002},
48672+ {0x00a05000, 0x00000002},
48673+ {0x00007568, 0x00000002},
48674+ {0x00061000, 0x00000002},
48675+ {0x00000095, 0x0000000c},
48676+ {0x00058000, 0x00000002},
48677+ {0x0c607562, 0x00000002},
48678+ {0x00000097, 0x00000004},
48679+ {0x000380e6, 0x00000002},
48680+ {0x040025c5, 0x00000002},
48681+ {0x00600096, 0x00000004},
48682+ {0x400070e5, 0000000000},
48683+ {0x000380e6, 0x00000002},
48684+ {0x040025c5, 0x00000002},
48685+ {0x000380e5, 0x00000002},
48686+ {0x000000a8, 0x0000001c},
48687+ {0x000650aa, 0x00000018},
48688+ {0x040025bb, 0x00000002},
48689+ {0x000610ab, 0x00000018},
48690+ {0x040075bc, 0000000000},
48691+ {0x000075bb, 0x00000002},
48692+ {0x000075bc, 0000000000},
48693+ {0x00090000, 0x00000006},
48694+ {0x00090000, 0x00000002},
48695+ {0x000d8002, 0x00000006},
48696+ {0x00007832, 0x00000002},
48697+ {0x00005000, 0x00000002},
48698+ {0x000380e7, 0x00000002},
48699+ {0x04002c97, 0x00000002},
48700+ {0x00007820, 0x00000002},
48701+ {0x00007821, 0x00000002},
48702+ {0x00007800, 0000000000},
48703+ {0x01200000, 0x00000002},
48704+ {0x20077000, 0x00000002},
48705+ {0x01200000, 0x00000002},
48706+ {0x20007000, 0x00000002},
48707+ {0x00061000, 0x00000002},
48708+ {0x0120751b, 0x00000002},
48709+ {0x8040750a, 0x00000002},
48710+ {0x8040750b, 0x00000002},
48711+ {0x00110000, 0x00000002},
48712+ {0x000380e5, 0x00000002},
48713+ {0x000000c6, 0x0000001c},
48714+ {0x000610ab, 0x00000018},
48715+ {0x844075bd, 0x00000002},
48716+ {0x000610aa, 0x00000018},
48717+ {0x840075bb, 0x00000002},
48718+ {0x000610ab, 0x00000018},
48719+ {0x844075bc, 0x00000002},
48720+ {0x000000c9, 0x00000004},
48721+ {0x804075bd, 0x00000002},
48722+ {0x800075bb, 0x00000002},
48723+ {0x804075bc, 0x00000002},
48724+ {0x00108000, 0x00000002},
48725+ {0x01400000, 0x00000002},
48726+ {0x006000cd, 0x0000000c},
48727+ {0x20c07000, 0x00000020},
48728+ {0x000000cf, 0x00000012},
48729+ {0x00800000, 0x00000006},
48730+ {0x0080751d, 0x00000006},
48731+ {0000000000, 0000000000},
48732+ {0x0000775c, 0x00000002},
48733+ {0x00a05000, 0x00000002},
48734+ {0x00661000, 0x00000002},
48735+ {0x0460275d, 0x00000020},
48736+ {0x00004000, 0000000000},
48737+ {0x01e00830, 0x00000002},
48738+ {0x21007000, 0000000000},
48739+ {0x6464614d, 0000000000},
48740+ {0x69687420, 0000000000},
48741+ {0x00000073, 0000000000},
48742+ {0000000000, 0000000000},
48743+ {0x00005000, 0x00000002},
48744+ {0x000380d0, 0x00000002},
48745+ {0x040025e0, 0x00000002},
48746+ {0x000075e1, 0000000000},
48747+ {0x00000001, 0000000000},
48748+ {0x000380e0, 0x00000002},
48749+ {0x04002394, 0x00000002},
48750+ {0x00005000, 0000000000},
48751+ {0000000000, 0000000000},
48752+ {0000000000, 0000000000},
48753+ {0x00000008, 0000000000},
48754+ {0x00000004, 0000000000},
48755+ {0000000000, 0000000000},
48756+ {0000000000, 0000000000},
48757+ {0000000000, 0000000000},
48758+ {0000000000, 0000000000},
48759+ {0000000000, 0000000000},
48760+ {0000000000, 0000000000},
48761+ {0000000000, 0000000000},
48762+ {0000000000, 0000000000},
48763+ {0000000000, 0000000000},
48764+ {0000000000, 0000000000},
48765+ {0000000000, 0000000000},
48766+ {0000000000, 0000000000},
48767+ {0000000000, 0000000000},
48768+ {0000000000, 0000000000},
48769+ {0000000000, 0000000000},
48770+ {0000000000, 0000000000},
48771+ {0000000000, 0000000000},
48772+ {0000000000, 0000000000},
48773+ {0000000000, 0000000000},
48774+ {0000000000, 0000000000},
48775+ {0000000000, 0000000000},
48776+ {0000000000, 0000000000},
48777+ {0000000000, 0000000000},
48778+ {0000000000, 0000000000},
48779+};
48780+
48781+static const u32 R300_cp_microcode[][2] = {
48782+ { 0x4200e000, 0000000000 },
48783+ { 0x4000e000, 0000000000 },
48784+ { 0x000000af, 0x00000008 },
48785+ { 0x000000b3, 0x00000008 },
48786+ { 0x6c5a504f, 0000000000 },
48787+ { 0x4f4f497a, 0000000000 },
48788+ { 0x5a578288, 0000000000 },
48789+ { 0x4f91906a, 0000000000 },
48790+ { 0x4f4f4f4f, 0000000000 },
48791+ { 0x4fe24f44, 0000000000 },
48792+ { 0x4f9c9c9c, 0000000000 },
48793+ { 0xdc4f4fde, 0000000000 },
48794+ { 0xa1cd4f4f, 0000000000 },
48795+ { 0xd29d9d9d, 0000000000 },
48796+ { 0x4f0f9fd7, 0000000000 },
48797+ { 0x000ca000, 0x00000004 },
48798+ { 0x000d0012, 0x00000038 },
48799+ { 0x0000e8b4, 0x00000004 },
48800+ { 0x000d0014, 0x00000038 },
48801+ { 0x0000e8b6, 0x00000004 },
48802+ { 0x000d0016, 0x00000038 },
48803+ { 0x0000e854, 0x00000004 },
48804+ { 0x000d0018, 0x00000038 },
48805+ { 0x0000e855, 0x00000004 },
48806+ { 0x000d001a, 0x00000038 },
48807+ { 0x0000e856, 0x00000004 },
48808+ { 0x000d001c, 0x00000038 },
48809+ { 0x0000e857, 0x00000004 },
48810+ { 0x000d001e, 0x00000038 },
48811+ { 0x0000e824, 0x00000004 },
48812+ { 0x000d0020, 0x00000038 },
48813+ { 0x0000e825, 0x00000004 },
48814+ { 0x000d0022, 0x00000038 },
48815+ { 0x0000e830, 0x00000004 },
48816+ { 0x000d0024, 0x00000038 },
48817+ { 0x0000f0c0, 0x00000004 },
48818+ { 0x000d0026, 0x00000038 },
48819+ { 0x0000f0c1, 0x00000004 },
48820+ { 0x000d0028, 0x00000038 },
48821+ { 0x0000f041, 0x00000004 },
48822+ { 0x000d002a, 0x00000038 },
48823+ { 0x0000f184, 0x00000004 },
48824+ { 0x000d002c, 0x00000038 },
48825+ { 0x0000f185, 0x00000004 },
48826+ { 0x000d002e, 0x00000038 },
48827+ { 0x0000f186, 0x00000004 },
48828+ { 0x000d0030, 0x00000038 },
48829+ { 0x0000f187, 0x00000004 },
48830+ { 0x000d0032, 0x00000038 },
48831+ { 0x0000f180, 0x00000004 },
48832+ { 0x000d0034, 0x00000038 },
48833+ { 0x0000f393, 0x00000004 },
48834+ { 0x000d0036, 0x00000038 },
48835+ { 0x0000f38a, 0x00000004 },
48836+ { 0x000d0038, 0x00000038 },
48837+ { 0x0000f38e, 0x00000004 },
48838+ { 0x0000e821, 0x00000004 },
48839+ { 0x0140a000, 0x00000004 },
48840+ { 0x00000043, 0x00000018 },
48841+ { 0x00cce800, 0x00000004 },
48842+ { 0x001b0001, 0x00000004 },
48843+ { 0x08004800, 0x00000004 },
48844+ { 0x001b0001, 0x00000004 },
48845+ { 0x08004800, 0x00000004 },
48846+ { 0x001b0001, 0x00000004 },
48847+ { 0x08004800, 0x00000004 },
48848+ { 0x0000003a, 0x00000008 },
48849+ { 0x0000a000, 0000000000 },
48850+ { 0x02c0a000, 0x00000004 },
48851+ { 0x000ca000, 0x00000004 },
48852+ { 0x00130000, 0x00000004 },
48853+ { 0x000c2000, 0x00000004 },
48854+ { 0xc980c045, 0x00000008 },
48855+ { 0x2000451d, 0x00000004 },
48856+ { 0x0000e580, 0x00000004 },
48857+ { 0x000ce581, 0x00000004 },
48858+ { 0x08004580, 0x00000004 },
48859+ { 0x000ce581, 0x00000004 },
48860+ { 0x0000004c, 0x00000008 },
48861+ { 0x0000a000, 0000000000 },
48862+ { 0x000c2000, 0x00000004 },
48863+ { 0x0000e50e, 0x00000004 },
48864+ { 0x00032000, 0x00000004 },
48865+ { 0x00022056, 0x00000028 },
48866+ { 0x00000056, 0x00000024 },
48867+ { 0x0800450f, 0x00000004 },
48868+ { 0x0000a050, 0x00000008 },
48869+ { 0x0000e565, 0x00000004 },
48870+ { 0x0000e566, 0x00000004 },
48871+ { 0x00000057, 0x00000008 },
48872+ { 0x03cca5b4, 0x00000004 },
48873+ { 0x05432000, 0x00000004 },
48874+ { 0x00022000, 0x00000004 },
48875+ { 0x4ccce063, 0x00000030 },
48876+ { 0x08274565, 0x00000004 },
48877+ { 0x00000063, 0x00000030 },
48878+ { 0x08004564, 0x00000004 },
48879+ { 0x0000e566, 0x00000004 },
48880+ { 0x0000005a, 0x00000008 },
48881+ { 0x00802066, 0x00000010 },
48882+ { 0x00202000, 0x00000004 },
48883+ { 0x001b00ff, 0x00000004 },
48884+ { 0x01000069, 0x00000010 },
48885+ { 0x001f2000, 0x00000004 },
48886+ { 0x001c00ff, 0x00000004 },
48887+ { 0000000000, 0x0000000c },
48888+ { 0x00000085, 0x00000030 },
48889+ { 0x0000005a, 0x00000008 },
48890+ { 0x0000e576, 0x00000004 },
48891+ { 0x000ca000, 0x00000004 },
48892+ { 0x00012000, 0x00000004 },
48893+ { 0x00082000, 0x00000004 },
48894+ { 0x1800650e, 0x00000004 },
48895+ { 0x00092000, 0x00000004 },
48896+ { 0x000a2000, 0x00000004 },
48897+ { 0x000f0000, 0x00000004 },
48898+ { 0x00400000, 0x00000004 },
48899+ { 0x00000079, 0x00000018 },
48900+ { 0x0000e563, 0x00000004 },
48901+ { 0x00c0e5f9, 0x000000c2 },
48902+ { 0x0000006e, 0x00000008 },
48903+ { 0x0000a06e, 0x00000008 },
48904+ { 0x0000e576, 0x00000004 },
48905+ { 0x0000e577, 0x00000004 },
48906+ { 0x0000e50e, 0x00000004 },
48907+ { 0x0000e50f, 0x00000004 },
48908+ { 0x0140a000, 0x00000004 },
48909+ { 0x0000007c, 0x00000018 },
48910+ { 0x00c0e5f9, 0x000000c2 },
48911+ { 0x0000007c, 0x00000008 },
48912+ { 0x0014e50e, 0x00000004 },
48913+ { 0x0040e50f, 0x00000004 },
48914+ { 0x00c0007f, 0x00000008 },
48915+ { 0x0000e570, 0x00000004 },
48916+ { 0x0000e571, 0x00000004 },
48917+ { 0x0000e572, 0x0000000c },
48918+ { 0x0000a000, 0x00000004 },
48919+ { 0x0140a000, 0x00000004 },
48920+ { 0x0000e568, 0x00000004 },
48921+ { 0x000c2000, 0x00000004 },
48922+ { 0x00000089, 0x00000018 },
48923+ { 0x000b0000, 0x00000004 },
48924+ { 0x18c0e562, 0x00000004 },
48925+ { 0x0000008b, 0x00000008 },
48926+ { 0x00c0008a, 0x00000008 },
48927+ { 0x000700e4, 0x00000004 },
48928+ { 0x00000097, 0x00000038 },
48929+ { 0x000ca099, 0x00000030 },
48930+ { 0x080045bb, 0x00000004 },
48931+ { 0x000c209a, 0x00000030 },
48932+ { 0x0800e5bc, 0000000000 },
48933+ { 0x0000e5bb, 0x00000004 },
48934+ { 0x0000e5bc, 0000000000 },
48935+ { 0x00120000, 0x0000000c },
48936+ { 0x00120000, 0x00000004 },
48937+ { 0x001b0002, 0x0000000c },
48938+ { 0x0000a000, 0x00000004 },
48939+ { 0x0000e821, 0x00000004 },
48940+ { 0x0000e800, 0000000000 },
48941+ { 0x0000e821, 0x00000004 },
48942+ { 0x0000e82e, 0000000000 },
48943+ { 0x02cca000, 0x00000004 },
48944+ { 0x00140000, 0x00000004 },
48945+ { 0x000ce1cc, 0x00000004 },
48946+ { 0x050de1cd, 0x00000004 },
48947+ { 0x000000a7, 0x00000020 },
48948+ { 0x4200e000, 0000000000 },
48949+ { 0x000000ae, 0x00000038 },
48950+ { 0x000ca000, 0x00000004 },
48951+ { 0x00140000, 0x00000004 },
48952+ { 0x000c2000, 0x00000004 },
48953+ { 0x00160000, 0x00000004 },
48954+ { 0x700ce000, 0x00000004 },
48955+ { 0x001400aa, 0x00000008 },
48956+ { 0x4000e000, 0000000000 },
48957+ { 0x02400000, 0x00000004 },
48958+ { 0x400ee000, 0x00000004 },
48959+ { 0x02400000, 0x00000004 },
48960+ { 0x4000e000, 0000000000 },
48961+ { 0x000c2000, 0x00000004 },
48962+ { 0x0240e51b, 0x00000004 },
48963+ { 0x0080e50a, 0x00000005 },
48964+ { 0x0080e50b, 0x00000005 },
48965+ { 0x00220000, 0x00000004 },
48966+ { 0x000700e4, 0x00000004 },
48967+ { 0x000000c1, 0x00000038 },
48968+ { 0x000c209a, 0x00000030 },
48969+ { 0x0880e5bd, 0x00000005 },
48970+ { 0x000c2099, 0x00000030 },
48971+ { 0x0800e5bb, 0x00000005 },
48972+ { 0x000c209a, 0x00000030 },
48973+ { 0x0880e5bc, 0x00000005 },
48974+ { 0x000000c4, 0x00000008 },
48975+ { 0x0080e5bd, 0x00000005 },
48976+ { 0x0000e5bb, 0x00000005 },
48977+ { 0x0080e5bc, 0x00000005 },
48978+ { 0x00210000, 0x00000004 },
48979+ { 0x02800000, 0x00000004 },
48980+ { 0x00c000c8, 0x00000018 },
48981+ { 0x4180e000, 0x00000040 },
48982+ { 0x000000ca, 0x00000024 },
48983+ { 0x01000000, 0x0000000c },
48984+ { 0x0100e51d, 0x0000000c },
48985+ { 0x000045bb, 0x00000004 },
48986+ { 0x000080c4, 0x00000008 },
48987+ { 0x0000f3ce, 0x00000004 },
48988+ { 0x0140a000, 0x00000004 },
48989+ { 0x00cc2000, 0x00000004 },
48990+ { 0x08c053cf, 0x00000040 },
48991+ { 0x00008000, 0000000000 },
48992+ { 0x0000f3d2, 0x00000004 },
48993+ { 0x0140a000, 0x00000004 },
48994+ { 0x00cc2000, 0x00000004 },
48995+ { 0x08c053d3, 0x00000040 },
48996+ { 0x00008000, 0000000000 },
48997+ { 0x0000f39d, 0x00000004 },
48998+ { 0x0140a000, 0x00000004 },
48999+ { 0x00cc2000, 0x00000004 },
49000+ { 0x08c0539e, 0x00000040 },
49001+ { 0x00008000, 0000000000 },
49002+ { 0x03c00830, 0x00000004 },
49003+ { 0x4200e000, 0000000000 },
49004+ { 0x0000a000, 0x00000004 },
49005+ { 0x200045e0, 0x00000004 },
49006+ { 0x0000e5e1, 0000000000 },
49007+ { 0x00000001, 0000000000 },
49008+ { 0x000700e1, 0x00000004 },
49009+ { 0x0800e394, 0000000000 },
49010+ { 0000000000, 0000000000 },
49011+ { 0000000000, 0000000000 },
49012+ { 0000000000, 0000000000 },
49013+ { 0000000000, 0000000000 },
49014+ { 0000000000, 0000000000 },
49015+ { 0000000000, 0000000000 },
49016+ { 0000000000, 0000000000 },
49017+ { 0000000000, 0000000000 },
49018+ { 0000000000, 0000000000 },
49019+ { 0000000000, 0000000000 },
49020+ { 0000000000, 0000000000 },
49021+ { 0000000000, 0000000000 },
49022+ { 0000000000, 0000000000 },
49023+ { 0000000000, 0000000000 },
49024+ { 0000000000, 0000000000 },
49025+ { 0000000000, 0000000000 },
49026+ { 0000000000, 0000000000 },
49027+ { 0000000000, 0000000000 },
49028+ { 0000000000, 0000000000 },
49029+ { 0000000000, 0000000000 },
49030+ { 0000000000, 0000000000 },
49031+ { 0000000000, 0000000000 },
49032+ { 0000000000, 0000000000 },
49033+ { 0000000000, 0000000000 },
49034+ { 0000000000, 0000000000 },
49035+ { 0000000000, 0000000000 },
49036+ { 0000000000, 0000000000 },
49037+ { 0000000000, 0000000000 },
49038+};
49039+
49040+static int RADEON_READ_PLL(struct drm_device * dev, int addr)
49041+{
49042+ drm_radeon_private_t *dev_priv = dev->dev_private;
49043+
49044+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
49045+ return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
49046+}
49047+
49048+static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
49049+{
49050+ RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
49051+ return RADEON_READ(RADEON_PCIE_DATA);
49052+}
49053+
49054+static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
49055+{
49056+ u32 ret;
49057+ RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
49058+ ret = RADEON_READ(RADEON_IGPGART_DATA);
49059+ RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
49060+ return ret;
49061+}
49062+
49063+#if RADEON_FIFO_DEBUG
49064+static void radeon_status(drm_radeon_private_t * dev_priv)
49065+{
49066+ printk("%s:\n", __FUNCTION__);
49067+ printk("RBBM_STATUS = 0x%08x\n",
49068+ (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
49069+ printk("CP_RB_RTPR = 0x%08x\n",
49070+ (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
49071+ printk("CP_RB_WTPR = 0x%08x\n",
49072+ (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
49073+ printk("AIC_CNTL = 0x%08x\n",
49074+ (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
49075+ printk("AIC_STAT = 0x%08x\n",
49076+ (unsigned int)RADEON_READ(RADEON_AIC_STAT));
49077+ printk("AIC_PT_BASE = 0x%08x\n",
49078+ (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
49079+ printk("TLB_ADDR = 0x%08x\n",
49080+ (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
49081+ printk("TLB_DATA = 0x%08x\n",
49082+ (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
49083+}
49084+#endif
49085+
49086+/* ================================================================
49087+ * Engine, FIFO control
49088+ */
49089+
49090+static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
49091+{
49092+ u32 tmp;
49093+ int i;
49094+
49095+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
49096+
49097+ tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
49098+ tmp |= RADEON_RB3D_DC_FLUSH_ALL;
49099+ RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
49100+
49101+ for (i = 0; i < dev_priv->usec_timeout; i++) {
49102+ if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
49103+ & RADEON_RB3D_DC_BUSY)) {
49104+ return 0;
49105+ }
49106+ DRM_UDELAY(1);
49107+ }
49108+
49109+#if RADEON_FIFO_DEBUG
49110+ DRM_ERROR("failed!\n");
49111+ radeon_status(dev_priv);
49112+#endif
49113+ return -EBUSY;
49114+}
49115+
49116+static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
49117+{
49118+ int i;
49119+
49120+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
49121+
49122+ for (i = 0; i < dev_priv->usec_timeout; i++) {
49123+ int slots = (RADEON_READ(RADEON_RBBM_STATUS)
49124+ & RADEON_RBBM_FIFOCNT_MASK);
49125+ if (slots >= entries)
49126+ return 0;
49127+ DRM_UDELAY(1);
49128+ }
49129+
49130+#if RADEON_FIFO_DEBUG
49131+ DRM_ERROR("failed!\n");
49132+ radeon_status(dev_priv);
49133+#endif
49134+ return -EBUSY;
49135+}
49136+
49137+static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
49138+{
49139+ int i, ret;
49140+
49141+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
49142+
49143+ ret = radeon_do_wait_for_fifo(dev_priv, 64);
49144+ if (ret)
49145+ return ret;
49146+
49147+ for (i = 0; i < dev_priv->usec_timeout; i++) {
49148+ if (!(RADEON_READ(RADEON_RBBM_STATUS)
49149+ & RADEON_RBBM_ACTIVE)) {
49150+ radeon_do_pixcache_flush(dev_priv);
49151+ return 0;
49152+ }
49153+ DRM_UDELAY(1);
49154+ }
49155+
49156+#if RADEON_FIFO_DEBUG
49157+ DRM_ERROR("failed!\n");
49158+ radeon_status(dev_priv);
49159+#endif
49160+ return -EBUSY;
49161+}
49162+
49163+/* ================================================================
49164+ * CP control, initialization
49165+ */
49166+
49167+/* Load the microcode for the CP */
49168+static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
49169+{
49170+ int i;
49171+ DRM_DEBUG("\n");
49172+
49173+ radeon_do_wait_for_idle(dev_priv);
49174+
49175+ RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
49176+
49177+ if (dev_priv->microcode_version == UCODE_R200) {
49178+ DRM_INFO("Loading R200 Microcode\n");
49179+ for (i = 0; i < 256; i++) {
49180+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
49181+ R200_cp_microcode[i][1]);
49182+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
49183+ R200_cp_microcode[i][0]);
49184+ }
49185+ } else if (dev_priv->microcode_version == UCODE_R300) {
49186+ DRM_INFO("Loading R300 Microcode\n");
49187+ for (i = 0; i < 256; i++) {
49188+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
49189+ R300_cp_microcode[i][1]);
49190+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
49191+ R300_cp_microcode[i][0]);
49192+ }
49193+ } else {
49194+ for (i = 0; i < 256; i++) {
49195+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
49196+ radeon_cp_microcode[i][1]);
49197+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
49198+ radeon_cp_microcode[i][0]);
49199+ }
49200+ }
49201+}
49202+
49203+/* Flush any pending commands to the CP. This should only be used just
49204+ * prior to a wait for idle, as it informs the engine that the command
49205+ * stream is ending.
49206+ */
49207+static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
49208+{
49209+ DRM_DEBUG("\n");
49210+#if 0
49211+ u32 tmp;
49212+
49213+ tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
49214+ RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
49215+#endif
49216+}
49217+
49218+/* Wait for the CP to go idle.
49219+ */
49220+int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
49221+{
49222+ RING_LOCALS;
49223+ DRM_DEBUG("\n");
49224+
49225+ BEGIN_RING(6);
49226+
49227+ RADEON_PURGE_CACHE();
49228+ RADEON_PURGE_ZCACHE();
49229+ RADEON_WAIT_UNTIL_IDLE();
49230+
49231+ ADVANCE_RING();
49232+ COMMIT_RING();
49233+
49234+ return radeon_do_wait_for_idle(dev_priv);
49235+}
49236+
49237+/* Start the Command Processor.
49238+ */
49239+static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
49240+{
49241+ RING_LOCALS;
49242+ DRM_DEBUG("\n");
49243+
49244+ radeon_do_wait_for_idle(dev_priv);
49245+
49246+ RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
49247+
49248+ dev_priv->cp_running = 1;
49249+
49250+ BEGIN_RING(6);
49251+
49252+ RADEON_PURGE_CACHE();
49253+ RADEON_PURGE_ZCACHE();
49254+ RADEON_WAIT_UNTIL_IDLE();
49255+
49256+ ADVANCE_RING();
49257+ COMMIT_RING();
49258+}
49259+
49260+/* Reset the Command Processor. This will not flush any pending
49261+ * commands, so you must wait for the CP command stream to complete
49262+ * before calling this routine.
49263+ */
49264+static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
49265+{
49266+ u32 cur_read_ptr;
49267+ DRM_DEBUG("\n");
49268+
49269+ cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
49270+ RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
49271+ SET_RING_HEAD(dev_priv, cur_read_ptr);
49272+ dev_priv->ring.tail = cur_read_ptr;
49273+}
49274+
49275+/* Stop the Command Processor. This will not flush any pending
49276+ * commands, so you must flush the command stream and wait for the CP
49277+ * to go idle before calling this routine.
49278+ */
49279+static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
49280+{
49281+ DRM_DEBUG("\n");
49282+
49283+ RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
49284+
49285+ dev_priv->cp_running = 0;
49286+}
49287+
49288+/* Reset the engine. This will stop the CP if it is running.
49289+ */
49290+static int radeon_do_engine_reset(struct drm_device * dev)
49291+{
49292+ drm_radeon_private_t *dev_priv = dev->dev_private;
49293+ u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
49294+ DRM_DEBUG("\n");
49295+
49296+ radeon_do_pixcache_flush(dev_priv);
49297+
49298+ clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
49299+ mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
49300+
49301+ RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
49302+ RADEON_FORCEON_MCLKA |
49303+ RADEON_FORCEON_MCLKB |
49304+ RADEON_FORCEON_YCLKA |
49305+ RADEON_FORCEON_YCLKB |
49306+ RADEON_FORCEON_MC |
49307+ RADEON_FORCEON_AIC));
49308+
49309+ rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
49310+
49311+ RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
49312+ RADEON_SOFT_RESET_CP |
49313+ RADEON_SOFT_RESET_HI |
49314+ RADEON_SOFT_RESET_SE |
49315+ RADEON_SOFT_RESET_RE |
49316+ RADEON_SOFT_RESET_PP |
49317+ RADEON_SOFT_RESET_E2 |
49318+ RADEON_SOFT_RESET_RB));
49319+ RADEON_READ(RADEON_RBBM_SOFT_RESET);
49320+ RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
49321+ ~(RADEON_SOFT_RESET_CP |
49322+ RADEON_SOFT_RESET_HI |
49323+ RADEON_SOFT_RESET_SE |
49324+ RADEON_SOFT_RESET_RE |
49325+ RADEON_SOFT_RESET_PP |
49326+ RADEON_SOFT_RESET_E2 |
49327+ RADEON_SOFT_RESET_RB)));
49328+ RADEON_READ(RADEON_RBBM_SOFT_RESET);
49329+
49330+ RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
49331+ RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
49332+ RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
49333+
49334+ /* Reset the CP ring */
49335+ radeon_do_cp_reset(dev_priv);
49336+
49337+ /* The CP is no longer running after an engine reset */
49338+ dev_priv->cp_running = 0;
49339+
49340+ /* Reset any pending vertex, indirect buffers */
49341+ radeon_freelist_reset(dev);
49342+
49343+ return 0;
49344+}
49345+
49346+static void radeon_cp_init_ring_buffer(struct drm_device * dev,
49347+ drm_radeon_private_t * dev_priv)
49348+{
49349+ u32 ring_start, cur_read_ptr;
49350+ u32 tmp;
49351+
49352+ /* Initialize the memory controller. With new memory map, the fb location
49353+ * is not changed, it should have been properly initialized already. Part
49354+ * of the problem is that the code below is bogus, assuming the GART is
49355+ * always appended to the fb which is not necessarily the case
49356+ */
49357+ if (!dev_priv->new_memmap)
49358+ RADEON_WRITE(RADEON_MC_FB_LOCATION,
49359+ ((dev_priv->gart_vm_start - 1) & 0xffff0000)
49360+ | (dev_priv->fb_location >> 16));
49361+
49362+#if __OS_HAS_AGP
49363+ if (dev_priv->flags & RADEON_IS_AGP) {
49364+ RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
49365+ RADEON_WRITE(RADEON_MC_AGP_LOCATION,
49366+ (((dev_priv->gart_vm_start - 1 +
49367+ dev_priv->gart_size) & 0xffff0000) |
49368+ (dev_priv->gart_vm_start >> 16)));
49369+
49370+ ring_start = (dev_priv->cp_ring->offset
49371+ - dev->agp->base
49372+ + dev_priv->gart_vm_start);
49373+ } else
49374+#endif
49375+ ring_start = (dev_priv->cp_ring->offset
49376+ - (unsigned long)dev->sg->virtual
49377+ + dev_priv->gart_vm_start);
49378+
49379+ RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
49380+
49381+ /* Set the write pointer delay */
49382+ RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
49383+
49384+ /* Initialize the ring buffer's read and write pointers */
49385+ cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
49386+ RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
49387+ SET_RING_HEAD(dev_priv, cur_read_ptr);
49388+ dev_priv->ring.tail = cur_read_ptr;
49389+
49390+#if __OS_HAS_AGP
49391+ if (dev_priv->flags & RADEON_IS_AGP) {
49392+ RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
49393+ dev_priv->ring_rptr->offset
49394+ - dev->agp->base + dev_priv->gart_vm_start);
49395+ } else
49396+#endif
49397+ {
49398+ struct drm_sg_mem *entry = dev->sg;
49399+ unsigned long tmp_ofs, page_ofs;
49400+
49401+ tmp_ofs = dev_priv->ring_rptr->offset -
49402+ (unsigned long)dev->sg->virtual;
49403+ page_ofs = tmp_ofs >> PAGE_SHIFT;
49404+
49405+ RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
49406+ DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
49407+ (unsigned long)entry->busaddr[page_ofs],
49408+ entry->handle + tmp_ofs);
49409+ }
49410+
49411+ /* Set ring buffer size */
49412+#ifdef __BIG_ENDIAN
49413+ RADEON_WRITE(RADEON_CP_RB_CNTL,
49414+ RADEON_BUF_SWAP_32BIT |
49415+ (dev_priv->ring.fetch_size_l2ow << 18) |
49416+ (dev_priv->ring.rptr_update_l2qw << 8) |
49417+ dev_priv->ring.size_l2qw);
49418+#else
49419+ RADEON_WRITE(RADEON_CP_RB_CNTL,
49420+ (dev_priv->ring.fetch_size_l2ow << 18) |
49421+ (dev_priv->ring.rptr_update_l2qw << 8) |
49422+ dev_priv->ring.size_l2qw);
49423+#endif
49424+
49425+ /* Start with assuming that writeback doesn't work */
49426+ dev_priv->writeback_works = 0;
49427+
49428+ /* Initialize the scratch register pointer. This will cause
49429+ * the scratch register values to be written out to memory
49430+ * whenever they are updated.
49431+ *
49432+ * We simply put this behind the ring read pointer, this works
49433+ * with PCI GART as well as (whatever kind of) AGP GART
49434+ */
49435+ RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
49436+ + RADEON_SCRATCH_REG_OFFSET);
49437+
49438+ dev_priv->scratch = ((__volatile__ u32 *)
49439+ dev_priv->ring_rptr->handle +
49440+ (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
49441+
49442+ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
49443+
49444+ /* Turn on bus mastering */
49445+ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
49446+ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
49447+
49448+ dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
49449+ RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
49450+
49451+ dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
49452+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
49453+ dev_priv->sarea_priv->last_dispatch);
49454+
49455+ dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
49456+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
49457+
49458+ radeon_do_wait_for_idle(dev_priv);
49459+
49460+ /* Sync everything up */
49461+ RADEON_WRITE(RADEON_ISYNC_CNTL,
49462+ (RADEON_ISYNC_ANY2D_IDLE3D |
49463+ RADEON_ISYNC_ANY3D_IDLE2D |
49464+ RADEON_ISYNC_WAIT_IDLEGUI |
49465+ RADEON_ISYNC_CPSCRATCH_IDLEGUI));
49466+
49467+}
49468+
49469+static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
49470+{
49471+ u32 tmp;
49472+
49473+ /* Writeback doesn't seem to work everywhere, test it here and possibly
49474+ * enable it if it appears to work
49475+ */
49476+ DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
49477+ RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
49478+
49479+ for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
49480+ if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
49481+ 0xdeadbeef)
49482+ break;
49483+ DRM_UDELAY(1);
49484+ }
49485+
49486+ if (tmp < dev_priv->usec_timeout) {
49487+ dev_priv->writeback_works = 1;
49488+ DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
49489+ } else {
49490+ dev_priv->writeback_works = 0;
49491+ DRM_INFO("writeback test failed\n");
49492+ }
49493+ if (radeon_no_wb == 1) {
49494+ dev_priv->writeback_works = 0;
49495+ DRM_INFO("writeback forced off\n");
49496+ }
49497+
49498+ if (!dev_priv->writeback_works) {
49499+ /* Disable writeback to avoid unnecessary bus master transfers */
49500+ RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
49501+ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
49502+ }
49503+}
49504+
49505+/* Enable or disable IGP GART on the chip */
49506+static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
49507+{
49508+ u32 temp, tmp;
49509+
49510+ tmp = RADEON_READ(RADEON_AIC_CNTL);
49511+ DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
49512+ if (on) {
49513+ DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
49514+ dev_priv->gart_vm_start,
49515+ (long)dev_priv->gart_info.bus_addr,
49516+ dev_priv->gart_size);
49517+
49518+ RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
49519+ RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
49520+ RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
49521+ RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
49522+ dev_priv->gart_info.bus_addr);
49523+
49524+ temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
49525+ RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
49526+
49527+ RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
49528+ dev_priv->gart_size = 32*1024*1024;
49529+ RADEON_WRITE(RADEON_MC_AGP_LOCATION,
49530+ (((dev_priv->gart_vm_start - 1 +
49531+ dev_priv->gart_size) & 0xffff0000) |
49532+ (dev_priv->gart_vm_start >> 16)));
49533+
49534+ temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
49535+ RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
49536+
49537+ RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
49538+ RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
49539+ RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
49540+ RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
49541+ }
49542+}
49543+
49544+static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
49545+{
49546+ u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
49547+ if (on) {
49548+
49549+ DRM_DEBUG("programming pcie %08X %08lX %08X\n",
49550+ dev_priv->gart_vm_start,
49551+ (long)dev_priv->gart_info.bus_addr,
49552+ dev_priv->gart_size);
49553+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
49554+ dev_priv->gart_vm_start);
49555+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
49556+ dev_priv->gart_info.bus_addr);
49557+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
49558+ dev_priv->gart_vm_start);
49559+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
49560+ dev_priv->gart_vm_start +
49561+ dev_priv->gart_size - 1);
49562+
49563+ RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
49564+
49565+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
49566+ RADEON_PCIE_TX_GART_EN);
49567+ } else {
49568+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
49569+ tmp & ~RADEON_PCIE_TX_GART_EN);
49570+ }
49571+}
49572+
49573+/* Enable or disable PCI GART on the chip */
49574+static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
49575+{
49576+ u32 tmp;
49577+
49578+ if (dev_priv->flags & RADEON_IS_IGPGART) {
49579+ radeon_set_igpgart(dev_priv, on);
49580+ return;
49581+ }
49582+
49583+ if (dev_priv->flags & RADEON_IS_PCIE) {
49584+ radeon_set_pciegart(dev_priv, on);
49585+ return;
49586+ }
49587+
49588+ tmp = RADEON_READ(RADEON_AIC_CNTL);
49589+
49590+ if (on) {
49591+ RADEON_WRITE(RADEON_AIC_CNTL,
49592+ tmp | RADEON_PCIGART_TRANSLATE_EN);
49593+
49594+ /* set PCI GART page-table base address
49595+ */
49596+ RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
49597+
49598+ /* set address range for PCI address translate
49599+ */
49600+ RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
49601+ RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
49602+ + dev_priv->gart_size - 1);
49603+
49604+ /* Turn off AGP aperture -- is this required for PCI GART?
49605+ */
49606+ RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
49607+ RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
49608+ } else {
49609+ RADEON_WRITE(RADEON_AIC_CNTL,
49610+ tmp & ~RADEON_PCIGART_TRANSLATE_EN);
49611+ }
49612+}
49613+
49614+static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
49615+{
49616+ drm_radeon_private_t *dev_priv = dev->dev_private;
49617+
49618+ DRM_DEBUG("\n");
49619+
49620+ /* if we require new memory map but we don't have it fail */
49621+ if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
49622+ DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
49623+ radeon_do_cleanup_cp(dev);
49624+ return -EINVAL;
49625+ }
49626+
49627+ if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
49628+ {
49629+ DRM_DEBUG("Forcing AGP card to PCI mode\n");
49630+ dev_priv->flags &= ~RADEON_IS_AGP;
49631+ }
49632+ else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
49633+ && !init->is_pci)
49634+ {
49635+ DRM_DEBUG("Restoring AGP flag\n");
49636+ dev_priv->flags |= RADEON_IS_AGP;
49637+ }
49638+
49639+ if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
49640+ DRM_ERROR("PCI GART memory not allocated!\n");
49641+ radeon_do_cleanup_cp(dev);
49642+ return -EINVAL;
49643+ }
49644+
49645+ dev_priv->usec_timeout = init->usec_timeout;
49646+ if (dev_priv->usec_timeout < 1 ||
49647+ dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
49648+ DRM_DEBUG("TIMEOUT problem!\n");
49649+ radeon_do_cleanup_cp(dev);
49650+ return -EINVAL;
49651+ }
49652+
49653+ /* Enable vblank on CRTC1 for older X servers
49654+ */
49655+ dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
49656+
49657+ switch(init->func) {
49658+ case RADEON_INIT_R200_CP:
49659+ dev_priv->microcode_version = UCODE_R200;
49660+ break;
49661+ case RADEON_INIT_R300_CP:
49662+ dev_priv->microcode_version = UCODE_R300;
49663+ break;
49664+ default:
49665+ dev_priv->microcode_version = UCODE_R100;
49666+ }
49667+
49668+ dev_priv->do_boxes = 0;
49669+ dev_priv->cp_mode = init->cp_mode;
49670+
49671+ /* We don't support anything other than bus-mastering ring mode,
49672+ * but the ring can be in either AGP or PCI space for the ring
49673+ * read pointer.
49674+ */
49675+ if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
49676+ (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
49677+ DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
49678+ radeon_do_cleanup_cp(dev);
49679+ return -EINVAL;
49680+ }
49681+
49682+ switch (init->fb_bpp) {
49683+ case 16:
49684+ dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
49685+ break;
49686+ case 32:
49687+ default:
49688+ dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
49689+ break;
49690+ }
49691+ dev_priv->front_offset = init->front_offset;
49692+ dev_priv->front_pitch = init->front_pitch;
49693+ dev_priv->back_offset = init->back_offset;
49694+ dev_priv->back_pitch = init->back_pitch;
49695+
49696+ switch (init->depth_bpp) {
49697+ case 16:
49698+ dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
49699+ break;
49700+ case 32:
49701+ default:
49702+ dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
49703+ break;
49704+ }
49705+ dev_priv->depth_offset = init->depth_offset;
49706+ dev_priv->depth_pitch = init->depth_pitch;
49707+
49708+ /* Hardware state for depth clears. Remove this if/when we no
49709+ * longer clear the depth buffer with a 3D rectangle. Hard-code
49710+ * all values to prevent unwanted 3D state from slipping through
49711+ * and screwing with the clear operation.
49712+ */
49713+ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
49714+ (dev_priv->color_fmt << 10) |
49715+ (dev_priv->microcode_version ==
49716+ UCODE_R100 ? RADEON_ZBLOCK16 : 0));
49717+
49718+ dev_priv->depth_clear.rb3d_zstencilcntl =
49719+ (dev_priv->depth_fmt |
49720+ RADEON_Z_TEST_ALWAYS |
49721+ RADEON_STENCIL_TEST_ALWAYS |
49722+ RADEON_STENCIL_S_FAIL_REPLACE |
49723+ RADEON_STENCIL_ZPASS_REPLACE |
49724+ RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
49725+
49726+ dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
49727+ RADEON_BFACE_SOLID |
49728+ RADEON_FFACE_SOLID |
49729+ RADEON_FLAT_SHADE_VTX_LAST |
49730+ RADEON_DIFFUSE_SHADE_FLAT |
49731+ RADEON_ALPHA_SHADE_FLAT |
49732+ RADEON_SPECULAR_SHADE_FLAT |
49733+ RADEON_FOG_SHADE_FLAT |
49734+ RADEON_VTX_PIX_CENTER_OGL |
49735+ RADEON_ROUND_MODE_TRUNC |
49736+ RADEON_ROUND_PREC_8TH_PIX);
49737+
49738+
49739+ dev_priv->ring_offset = init->ring_offset;
49740+ dev_priv->ring_rptr_offset = init->ring_rptr_offset;
49741+ dev_priv->buffers_offset = init->buffers_offset;
49742+ dev_priv->gart_textures_offset = init->gart_textures_offset;
49743+
49744+ dev_priv->sarea = drm_getsarea(dev);
49745+ if (!dev_priv->sarea) {
49746+ DRM_ERROR("could not find sarea!\n");
49747+ radeon_do_cleanup_cp(dev);
49748+ return -EINVAL;
49749+ }
49750+
49751+ dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
49752+ if (!dev_priv->cp_ring) {
49753+ DRM_ERROR("could not find cp ring region!\n");
49754+ radeon_do_cleanup_cp(dev);
49755+ return -EINVAL;
49756+ }
49757+ dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
49758+ if (!dev_priv->ring_rptr) {
49759+ DRM_ERROR("could not find ring read pointer!\n");
49760+ radeon_do_cleanup_cp(dev);
49761+ return -EINVAL;
49762+ }
49763+ dev->agp_buffer_token = init->buffers_offset;
49764+ dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
49765+ if (!dev->agp_buffer_map) {
49766+ DRM_ERROR("could not find dma buffer region!\n");
49767+ radeon_do_cleanup_cp(dev);
49768+ return -EINVAL;
49769+ }
49770+
49771+ if (init->gart_textures_offset) {
49772+ dev_priv->gart_textures =
49773+ drm_core_findmap(dev, init->gart_textures_offset);
49774+ if (!dev_priv->gart_textures) {
49775+ DRM_ERROR("could not find GART texture region!\n");
49776+ radeon_do_cleanup_cp(dev);
49777+ return -EINVAL;
49778+ }
49779+ }
49780+
49781+ dev_priv->sarea_priv =
49782+ (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
49783+ init->sarea_priv_offset);
49784+
49785+#if __OS_HAS_AGP
49786+ if (dev_priv->flags & RADEON_IS_AGP) {
49787+ drm_core_ioremap(dev_priv->cp_ring, dev);
49788+ drm_core_ioremap(dev_priv->ring_rptr, dev);
49789+ drm_core_ioremap(dev->agp_buffer_map, dev);
49790+ if (!dev_priv->cp_ring->handle ||
49791+ !dev_priv->ring_rptr->handle ||
49792+ !dev->agp_buffer_map->handle) {
49793+ DRM_ERROR("could not find ioremap agp regions!\n");
49794+ radeon_do_cleanup_cp(dev);
49795+ return -EINVAL;
49796+ }
49797+ } else
49798+#endif
49799+ {
49800+ dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
49801+ dev_priv->ring_rptr->handle =
49802+ (void *)dev_priv->ring_rptr->offset;
49803+ dev->agp_buffer_map->handle =
49804+ (void *)dev->agp_buffer_map->offset;
49805+
49806+ DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
49807+ dev_priv->cp_ring->handle);
49808+ DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
49809+ dev_priv->ring_rptr->handle);
49810+ DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
49811+ dev->agp_buffer_map->handle);
49812+ }
49813+
49814+ dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
49815+ & 0xffff) << 16;
49816+ dev_priv->fb_size =
49817+ ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
49818+ - dev_priv->fb_location;
49819+
49820+ dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
49821+ ((dev_priv->front_offset
49822+ + dev_priv->fb_location) >> 10));
49823+
49824+ dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
49825+ ((dev_priv->back_offset
49826+ + dev_priv->fb_location) >> 10));
49827+
49828+ dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
49829+ ((dev_priv->depth_offset
49830+ + dev_priv->fb_location) >> 10));
49831+
49832+ dev_priv->gart_size = init->gart_size;
49833+
49834+ /* New let's set the memory map ... */
49835+ if (dev_priv->new_memmap) {
49836+ u32 base = 0;
49837+
49838+ DRM_INFO("Setting GART location based on new memory map\n");
49839+
49840+ /* If using AGP, try to locate the AGP aperture at the same
49841+ * location in the card and on the bus, though we have to
49842+ * align it down.
49843+ */
49844+#if __OS_HAS_AGP
49845+ if (dev_priv->flags & RADEON_IS_AGP) {
49846+ base = dev->agp->base;
49847+ /* Check if valid */
49848+ if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
49849+ base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
49850+ DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
49851+ dev->agp->base);
49852+ base = 0;
49853+ }
49854+ }
49855+#endif
49856+ /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
49857+ if (base == 0) {
49858+ base = dev_priv->fb_location + dev_priv->fb_size;
49859+ if (base < dev_priv->fb_location ||
49860+ ((base + dev_priv->gart_size) & 0xfffffffful) < base)
49861+ base = dev_priv->fb_location
49862+ - dev_priv->gart_size;
49863+ }
49864+ dev_priv->gart_vm_start = base & 0xffc00000u;
49865+ if (dev_priv->gart_vm_start != base)
49866+ DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
49867+ base, dev_priv->gart_vm_start);
49868+ } else {
49869+ DRM_INFO("Setting GART location based on old memory map\n");
49870+ dev_priv->gart_vm_start = dev_priv->fb_location +
49871+ RADEON_READ(RADEON_CONFIG_APER_SIZE);
49872+ }
49873+
49874+#if __OS_HAS_AGP
49875+ if (dev_priv->flags & RADEON_IS_AGP)
49876+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
49877+ - dev->agp->base
49878+ + dev_priv->gart_vm_start);
49879+ else
49880+#endif
49881+ dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
49882+ - (unsigned long)dev->sg->virtual
49883+ + dev_priv->gart_vm_start);
49884+
49885+ DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
49886+ DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
49887+ DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
49888+ dev_priv->gart_buffers_offset);
49889+
49890+ dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
49891+ dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
49892+ + init->ring_size / sizeof(u32));
49893+ dev_priv->ring.size = init->ring_size;
49894+ dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
49895+
49896+ dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
49897+ dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
49898+
49899+ dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
49900+ dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
49901+
49902+ dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
49903+
49904+ dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
49905+
49906+#if __OS_HAS_AGP
49907+ if (dev_priv->flags & RADEON_IS_AGP) {
49908+ /* Turn off PCI GART */
49909+ radeon_set_pcigart(dev_priv, 0);
49910+ } else
49911+#endif
49912+ {
49913+ /* if we have an offset set from userspace */
49914+ if (dev_priv->pcigart_offset_set) {
49915+ dev_priv->gart_info.bus_addr =
49916+ dev_priv->pcigart_offset + dev_priv->fb_location;
49917+ dev_priv->gart_info.mapping.offset =
49918+ dev_priv->gart_info.bus_addr;
49919+ dev_priv->gart_info.mapping.size =
49920+ dev_priv->gart_info.table_size;
49921+
49922+ drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
49923+ dev_priv->gart_info.addr =
49924+ dev_priv->gart_info.mapping.handle;
49925+
49926+ if (dev_priv->flags & RADEON_IS_PCIE)
49927+ dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
49928+ else
49929+ dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
49930+ dev_priv->gart_info.gart_table_location =
49931+ DRM_ATI_GART_FB;
49932+
49933+ DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
49934+ dev_priv->gart_info.addr,
49935+ dev_priv->pcigart_offset);
49936+ } else {
49937+ if (dev_priv->flags & RADEON_IS_IGPGART)
49938+ dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
49939+ else
49940+ dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
49941+ dev_priv->gart_info.gart_table_location =
49942+ DRM_ATI_GART_MAIN;
49943+ dev_priv->gart_info.addr = NULL;
49944+ dev_priv->gart_info.bus_addr = 0;
49945+ if (dev_priv->flags & RADEON_IS_PCIE) {
49946+ DRM_ERROR
49947+ ("Cannot use PCI Express without GART in FB memory\n");
49948+ radeon_do_cleanup_cp(dev);
49949+ return -EINVAL;
49950+ }
49951+ }
49952+
49953+ if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
49954+ DRM_ERROR("failed to init PCI GART!\n");
49955+ radeon_do_cleanup_cp(dev);
49956+ return -ENOMEM;
49957+ }
49958+
49959+ /* Turn on PCI GART */
49960+ radeon_set_pcigart(dev_priv, 1);
49961+ }
49962+
49963+ radeon_cp_load_microcode(dev_priv);
49964+ radeon_cp_init_ring_buffer(dev, dev_priv);
49965+
49966+ dev_priv->last_buf = 0;
49967+
49968+ radeon_do_engine_reset(dev);
49969+ radeon_test_writeback(dev_priv);
49970+
49971+ return 0;
49972+}
49973+
49974+static int radeon_do_cleanup_cp(struct drm_device * dev)
49975+{
49976+ drm_radeon_private_t *dev_priv = dev->dev_private;
49977+ DRM_DEBUG("\n");
49978+
49979+ /* Make sure interrupts are disabled here because the uninstall ioctl
49980+ * may not have been called from userspace and after dev_private
49981+ * is freed, it's too late.
49982+ */
49983+ if (dev->irq_enabled)
49984+ drm_irq_uninstall(dev);
49985+
49986+#if __OS_HAS_AGP
49987+ if (dev_priv->flags & RADEON_IS_AGP) {
49988+ if (dev_priv->cp_ring != NULL) {
49989+ drm_core_ioremapfree(dev_priv->cp_ring, dev);
49990+ dev_priv->cp_ring = NULL;
49991+ }
49992+ if (dev_priv->ring_rptr != NULL) {
49993+ drm_core_ioremapfree(dev_priv->ring_rptr, dev);
49994+ dev_priv->ring_rptr = NULL;
49995+ }
49996+ if (dev->agp_buffer_map != NULL) {
49997+ drm_core_ioremapfree(dev->agp_buffer_map, dev);
49998+ dev->agp_buffer_map = NULL;
49999+ }
50000+ } else
50001+#endif
50002+ {
50003+
50004+ if (dev_priv->gart_info.bus_addr) {
50005+ /* Turn off PCI GART */
50006+ radeon_set_pcigart(dev_priv, 0);
50007+ if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
50008+ DRM_ERROR("failed to cleanup PCI GART!\n");
50009+ }
50010+
50011+ if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
50012+ {
50013+ drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
50014+ dev_priv->gart_info.addr = 0;
50015+ }
50016+ }
50017+ /* only clear to the start of flags */
50018+ memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
50019+
50020+ return 0;
50021+}
50022+
50023+/* This code will reinit the Radeon CP hardware after a resume from disc.
50024+ * AFAIK, it would be very difficult to pickle the state at suspend time, so
50025+ * here we make sure that all Radeon hardware initialisation is re-done without
50026+ * affecting running applications.
50027+ *
50028+ * Charl P. Botha <http://cpbotha.net>
50029+ */
50030+static int radeon_do_resume_cp(struct drm_device * dev)
50031+{
50032+ drm_radeon_private_t *dev_priv = dev->dev_private;
50033+
50034+ if (!dev_priv) {
50035+ DRM_ERROR("Called with no initialization\n");
50036+ return -EINVAL;
50037+ }
50038+
50039+ DRM_DEBUG("Starting radeon_do_resume_cp()\n");
50040+
50041+#if __OS_HAS_AGP
50042+ if (dev_priv->flags & RADEON_IS_AGP) {
50043+ /* Turn off PCI GART */
50044+ radeon_set_pcigart(dev_priv, 0);
50045+ } else
50046+#endif
50047+ {
50048+ /* Turn on PCI GART */
50049+ radeon_set_pcigart(dev_priv, 1);
50050+ }
50051+
50052+ radeon_cp_load_microcode(dev_priv);
50053+ radeon_cp_init_ring_buffer(dev, dev_priv);
50054+
50055+ radeon_do_engine_reset(dev);
50056+
50057+ DRM_DEBUG("radeon_do_resume_cp() complete\n");
50058+
50059+ return 0;
50060+}
50061+
50062+int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
50063+{
50064+ drm_radeon_init_t *init = data;
50065+
50066+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50067+
50068+ if (init->func == RADEON_INIT_R300_CP)
50069+ r300_init_reg_flags();
50070+
50071+ switch (init->func) {
50072+ case RADEON_INIT_CP:
50073+ case RADEON_INIT_R200_CP:
50074+ case RADEON_INIT_R300_CP:
50075+ return radeon_do_init_cp(dev, init);
50076+ case RADEON_CLEANUP_CP:
50077+ return radeon_do_cleanup_cp(dev);
50078+ }
50079+
50080+ return -EINVAL;
50081+}
50082+
50083+int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
50084+{
50085+ drm_radeon_private_t *dev_priv = dev->dev_private;
50086+ DRM_DEBUG("\n");
50087+
50088+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50089+
50090+ if (dev_priv->cp_running) {
50091+ DRM_DEBUG("%s while CP running\n", __FUNCTION__);
50092+ return 0;
50093+ }
50094+ if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
50095+ DRM_DEBUG("%s called with bogus CP mode (%d)\n",
50096+ __FUNCTION__, dev_priv->cp_mode);
50097+ return 0;
50098+ }
50099+
50100+ radeon_do_cp_start(dev_priv);
50101+
50102+ return 0;
50103+}
50104+
50105+/* Stop the CP. The engine must have been idled before calling this
50106+ * routine.
50107+ */
50108+int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
50109+{
50110+ drm_radeon_private_t *dev_priv = dev->dev_private;
50111+ drm_radeon_cp_stop_t *stop = data;
50112+ int ret;
50113+ DRM_DEBUG("\n");
50114+
50115+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50116+
50117+ if (!dev_priv->cp_running)
50118+ return 0;
50119+
50120+ /* Flush any pending CP commands. This ensures any outstanding
50121+ * commands are exectuted by the engine before we turn it off.
50122+ */
50123+ if (stop->flush) {
50124+ radeon_do_cp_flush(dev_priv);
50125+ }
50126+
50127+ /* If we fail to make the engine go idle, we return an error
50128+ * code so that the DRM ioctl wrapper can try again.
50129+ */
50130+ if (stop->idle) {
50131+ ret = radeon_do_cp_idle(dev_priv);
50132+ if (ret)
50133+ return ret;
50134+ }
50135+
50136+ /* Finally, we can turn off the CP. If the engine isn't idle,
50137+ * we will get some dropped triangles as they won't be fully
50138+ * rendered before the CP is shut down.
50139+ */
50140+ radeon_do_cp_stop(dev_priv);
50141+
50142+ /* Reset the engine */
50143+ radeon_do_engine_reset(dev);
50144+
50145+ return 0;
50146+}
50147+
50148+void radeon_do_release(struct drm_device * dev)
50149+{
50150+ drm_radeon_private_t *dev_priv = dev->dev_private;
50151+ int i, ret;
50152+
50153+ if (dev_priv) {
50154+ if (dev_priv->cp_running) {
50155+ /* Stop the cp */
50156+ while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
50157+ DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
50158+#ifdef __linux__
50159+ schedule();
50160+#else
50161+#if defined(__FreeBSD__) && __FreeBSD_version > 500000
50162+ msleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
50163+ 1);
50164+#else
50165+ tsleep(&ret, PZERO, "rdnrel", 1);
50166+#endif
50167+#endif
50168+ }
50169+ radeon_do_cp_stop(dev_priv);
50170+ radeon_do_engine_reset(dev);
50171+ }
50172+
50173+ /* Disable *all* interrupts */
50174+ if (dev_priv->mmio) /* remove this after permanent addmaps */
50175+ RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
50176+
50177+ if (dev_priv->mmio) { /* remove all surfaces */
50178+ for (i = 0; i < RADEON_MAX_SURFACES; i++) {
50179+ RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
50180+ RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
50181+ 16 * i, 0);
50182+ RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
50183+ 16 * i, 0);
50184+ }
50185+ }
50186+
50187+ /* Free memory heap structures */
50188+ radeon_mem_takedown(&(dev_priv->gart_heap));
50189+ radeon_mem_takedown(&(dev_priv->fb_heap));
50190+
50191+ /* deallocate kernel resources */
50192+ radeon_do_cleanup_cp(dev);
50193+ }
50194+}
50195+
50196+/* Just reset the CP ring. Called as part of an X Server engine reset.
50197+ */
50198+int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
50199+{
50200+ drm_radeon_private_t *dev_priv = dev->dev_private;
50201+ DRM_DEBUG("\n");
50202+
50203+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50204+
50205+ if (!dev_priv) {
50206+ DRM_DEBUG("%s called before init done\n", __FUNCTION__);
50207+ return -EINVAL;
50208+ }
50209+
50210+ radeon_do_cp_reset(dev_priv);
50211+
50212+ /* The CP is no longer running after an engine reset */
50213+ dev_priv->cp_running = 0;
50214+
50215+ return 0;
50216+}
50217+
50218+int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
50219+{
50220+ drm_radeon_private_t *dev_priv = dev->dev_private;
50221+ DRM_DEBUG("\n");
50222+
50223+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50224+
50225+ return radeon_do_cp_idle(dev_priv);
50226+}
50227+
50228+/* Added by Charl P. Botha to call radeon_do_resume_cp().
50229+ */
50230+int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
50231+{
50232+
50233+ return radeon_do_resume_cp(dev);
50234+}
50235+
50236+int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
50237+{
50238+ DRM_DEBUG("\n");
50239+
50240+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50241+
50242+ return radeon_do_engine_reset(dev);
50243+}
50244+
50245+/* ================================================================
50246+ * Fullscreen mode
50247+ */
50248+
50249+/* KW: Deprecated to say the least:
50250+ */
50251+int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
50252+{
50253+ return 0;
50254+}
50255+
50256+/* ================================================================
50257+ * Freelist management
50258+ */
50259+
50260+/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
50261+ * bufs until freelist code is used. Note this hides a problem with
50262+ * the scratch register * (used to keep track of last buffer
50263+ * completed) being written to before * the last buffer has actually
50264+ * completed rendering.
50265+ *
50266+ * KW: It's also a good way to find free buffers quickly.
50267+ *
50268+ * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
50269+ * sleep. However, bugs in older versions of radeon_accel.c mean that
50270+ * we essentially have to do this, else old clients will break.
50271+ *
50272+ * However, it does leave open a potential deadlock where all the
50273+ * buffers are held by other clients, which can't release them because
50274+ * they can't get the lock.
50275+ */
50276+
50277+struct drm_buf *radeon_freelist_get(struct drm_device * dev)
50278+{
50279+ struct drm_device_dma *dma = dev->dma;
50280+ drm_radeon_private_t *dev_priv = dev->dev_private;
50281+ drm_radeon_buf_priv_t *buf_priv;
50282+ struct drm_buf *buf;
50283+ int i, t;
50284+ int start;
50285+
50286+ if (++dev_priv->last_buf >= dma->buf_count)
50287+ dev_priv->last_buf = 0;
50288+
50289+ start = dev_priv->last_buf;
50290+
50291+ for (t = 0; t < dev_priv->usec_timeout; t++) {
50292+ u32 done_age = GET_SCRATCH(1);
50293+ DRM_DEBUG("done_age = %d\n", done_age);
50294+ for (i = start; i < dma->buf_count; i++) {
50295+ buf = dma->buflist[i];
50296+ buf_priv = buf->dev_private;
50297+ if (buf->file_priv == NULL || (buf->pending &&
50298+ buf_priv->age <=
50299+ done_age)) {
50300+ dev_priv->stats.requested_bufs++;
50301+ buf->pending = 0;
50302+ return buf;
50303+ }
50304+ start = 0;
50305+ }
50306+
50307+ if (t) {
50308+ DRM_UDELAY(1);
50309+ dev_priv->stats.freelist_loops++;
50310+ }
50311+ }
50312+
50313+ DRM_DEBUG("returning NULL!\n");
50314+ return NULL;
50315+}
50316+
50317+#if 0
50318+struct drm_buf *radeon_freelist_get(struct drm_device * dev)
50319+{
50320+ struct drm_device_dma *dma = dev->dma;
50321+ drm_radeon_private_t *dev_priv = dev->dev_private;
50322+ drm_radeon_buf_priv_t *buf_priv;
50323+ struct drm_buf *buf;
50324+ int i, t;
50325+ int start;
50326+ u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
50327+
50328+ if (++dev_priv->last_buf >= dma->buf_count)
50329+ dev_priv->last_buf = 0;
50330+
50331+ start = dev_priv->last_buf;
50332+ dev_priv->stats.freelist_loops++;
50333+
50334+ for (t = 0; t < 2; t++) {
50335+ for (i = start; i < dma->buf_count; i++) {
50336+ buf = dma->buflist[i];
50337+ buf_priv = buf->dev_private;
50338+ if (buf->file_priv == 0 || (buf->pending &&
50339+ buf_priv->age <=
50340+ done_age)) {
50341+ dev_priv->stats.requested_bufs++;
50342+ buf->pending = 0;
50343+ return buf;
50344+ }
50345+ }
50346+ start = 0;
50347+ }
50348+
50349+ return NULL;
50350+}
50351+#endif
50352+
50353+void radeon_freelist_reset(struct drm_device * dev)
50354+{
50355+ struct drm_device_dma *dma = dev->dma;
50356+ drm_radeon_private_t *dev_priv = dev->dev_private;
50357+ int i;
50358+
50359+ dev_priv->last_buf = 0;
50360+ for (i = 0; i < dma->buf_count; i++) {
50361+ struct drm_buf *buf = dma->buflist[i];
50362+ drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
50363+ buf_priv->age = 0;
50364+ }
50365+}
50366+
50367+/* ================================================================
50368+ * CP command submission
50369+ */
50370+
50371+int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
50372+{
50373+ drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
50374+ int i;
50375+ u32 last_head = GET_RING_HEAD(dev_priv);
50376+
50377+ for (i = 0; i < dev_priv->usec_timeout; i++) {
50378+ u32 head = GET_RING_HEAD(dev_priv);
50379+
50380+ ring->space = (head - ring->tail) * sizeof(u32);
50381+ if (ring->space <= 0)
50382+ ring->space += ring->size;
50383+ if (ring->space > n)
50384+ return 0;
50385+
50386+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
50387+
50388+ if (head != last_head)
50389+ i = 0;
50390+ last_head = head;
50391+
50392+ DRM_UDELAY(1);
50393+ }
50394+
50395+ /* FIXME: This return value is ignored in the BEGIN_RING macro! */
50396+#if RADEON_FIFO_DEBUG
50397+ radeon_status(dev_priv);
50398+ DRM_ERROR("failed!\n");
50399+#endif
50400+ return -EBUSY;
50401+}
50402+
50403+static int radeon_cp_get_buffers(struct drm_device *dev,
50404+ struct drm_file *file_priv,
50405+ struct drm_dma * d)
50406+{
50407+ int i;
50408+ struct drm_buf *buf;
50409+
50410+ for (i = d->granted_count; i < d->request_count; i++) {
50411+ buf = radeon_freelist_get(dev);
50412+ if (!buf)
50413+ return -EBUSY; /* NOTE: broken client */
50414+
50415+ buf->file_priv = file_priv;
50416+
50417+ if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
50418+ sizeof(buf->idx)))
50419+ return -EFAULT;
50420+ if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
50421+ sizeof(buf->total)))
50422+ return -EFAULT;
50423+
50424+ d->granted_count++;
50425+ }
50426+ return 0;
50427+}
50428+
50429+int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
50430+{
50431+ struct drm_device_dma *dma = dev->dma;
50432+ int ret = 0;
50433+ struct drm_dma *d = data;
50434+
50435+ LOCK_TEST_WITH_RETURN(dev, file_priv);
50436+
50437+ /* Please don't send us buffers.
50438+ */
50439+ if (d->send_count != 0) {
50440+ DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
50441+ DRM_CURRENTPID, d->send_count);
50442+ return -EINVAL;
50443+ }
50444+
50445+ /* We'll send you buffers.
50446+ */
50447+ if (d->request_count < 0 || d->request_count > dma->buf_count) {
50448+ DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
50449+ DRM_CURRENTPID, d->request_count, dma->buf_count);
50450+ return -EINVAL;
50451+ }
50452+
50453+ d->granted_count = 0;
50454+
50455+ if (d->request_count) {
50456+ ret = radeon_cp_get_buffers(dev, file_priv, d);
50457+ }
50458+
50459+ return ret;
50460+}
50461+
50462+int radeon_driver_load(struct drm_device *dev, unsigned long flags)
50463+{
50464+ drm_radeon_private_t *dev_priv;
50465+ int ret = 0;
50466+
50467+ dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
50468+ if (dev_priv == NULL)
50469+ return -ENOMEM;
50470+
50471+ memset(dev_priv, 0, sizeof(drm_radeon_private_t));
50472+ dev->dev_private = (void *)dev_priv;
50473+ dev_priv->flags = flags;
50474+
50475+ switch (flags & RADEON_FAMILY_MASK) {
50476+ case CHIP_R100:
50477+ case CHIP_RV200:
50478+ case CHIP_R200:
50479+ case CHIP_R300:
50480+ case CHIP_R350:
50481+ case CHIP_R420:
50482+ case CHIP_RV410:
50483+ dev_priv->flags |= RADEON_HAS_HIERZ;
50484+ break;
50485+ default:
50486+ /* all other chips have no hierarchical z buffer */
50487+ break;
50488+ }
50489+
50490+ if (drm_device_is_agp(dev))
50491+ dev_priv->flags |= RADEON_IS_AGP;
50492+ else if (drm_device_is_pcie(dev))
50493+ dev_priv->flags |= RADEON_IS_PCIE;
50494+ else
50495+ dev_priv->flags |= RADEON_IS_PCI;
50496+
50497+ DRM_DEBUG("%s card detected\n",
50498+ ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
50499+ return ret;
50500+}
50501+
50502+/* Create mappings for registers and framebuffer so userland doesn't necessarily
50503+ * have to find them.
50504+ */
50505+int radeon_driver_firstopen(struct drm_device *dev)
50506+{
50507+ int ret;
50508+ drm_local_map_t *map;
50509+ drm_radeon_private_t *dev_priv = dev->dev_private;
50510+
50511+ dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
50512+
50513+ ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
50514+ drm_get_resource_len(dev, 2), _DRM_REGISTERS,
50515+ _DRM_READ_ONLY, &dev_priv->mmio);
50516+ if (ret != 0)
50517+ return ret;
50518+
50519+ ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
50520+ drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
50521+ _DRM_WRITE_COMBINING, &map);
50522+ if (ret != 0)
50523+ return ret;
50524+
50525+ return 0;
50526+}
50527+
50528+int radeon_driver_unload(struct drm_device *dev)
50529+{
50530+ drm_radeon_private_t *dev_priv = dev->dev_private;
50531+
50532+ DRM_DEBUG("\n");
50533+ drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
50534+
50535+ dev->dev_private = NULL;
50536+ return 0;
50537+}
50538Index: git/shared-core/radeon_drm.h
50539===================================================================
50540--- git.orig/shared-core/radeon_drm.h 2008-12-12 17:20:14.000000000 +0000
50541+++ git/shared-core/radeon_drm.h 2008-12-12 17:35:22.000000000 +0000
50542@@ -223,10 +223,10 @@
50543 #define R300_CMD_CP_DELAY 5
50544 #define R300_CMD_DMA_DISCARD 6
50545 #define R300_CMD_WAIT 7
50546-# define R300_WAIT_2D 0x1
50547-# define R300_WAIT_3D 0x2
50548-# define R300_WAIT_2D_CLEAN 0x3
50549-# define R300_WAIT_3D_CLEAN 0x4
50550+# define R300_WAIT_2D 0x1
50551+# define R300_WAIT_3D 0x2
50552+# define R300_WAIT_2D_CLEAN 0x3
50553+# define R300_WAIT_3D_CLEAN 0x4
50554 #define R300_CMD_SCRATCH 8
50555
50556 typedef union {
50557@@ -417,7 +417,7 @@
50558
50559 /* The current cliprects, or a subset thereof.
50560 */
50561- drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
50562+ struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
50563 unsigned int nbox;
50564
50565 /* Counters for client-side throttling of rendering clients.
50566@@ -426,7 +426,7 @@
50567 unsigned int last_dispatch;
50568 unsigned int last_clear;
50569
50570- drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
50571+ struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
50572 1];
50573 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
50574 int ctx_owner;
50575@@ -434,8 +434,17 @@
50576 int pfCurrentPage; /* which buffer is being displayed? */
50577 int crtc2_base; /* CRTC2 frame offset */
50578 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
50579+
50580+ unsigned int last_fence;
50581 } drm_radeon_sarea_t;
50582
50583+/* The only fence class we support */
50584+#define DRM_RADEON_FENCE_CLASS_ACCEL 0
50585+/* Fence type that guarantees read-write flush */
50586+#define DRM_RADEON_FENCE_TYPE_RW 2
50587+/* cache flushes programmed just before the fence */
50588+#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000
50589+
50590 /* WARNING: If you change any of these defines, make sure to change the
50591 * defines in the Xserver file (xf86drmRadeon.h)
50592 *
50593@@ -604,7 +613,7 @@
50594 int bufsz;
50595 char __user *buf;
50596 int nbox;
50597- drm_clip_rect_t __user *boxes;
50598+ struct drm_clip_rect __user *boxes;
50599 } drm_radeon_cmd_buffer_t;
50600
50601 typedef struct drm_radeon_tex_image {
50602@@ -655,6 +664,7 @@
50603 #define RADEON_PARAM_GART_TEX_HANDLE 10
50604 #define RADEON_PARAM_SCRATCH_OFFSET 11
50605 #define RADEON_PARAM_CARD_TYPE 12
50606+#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
50607
50608 typedef struct drm_radeon_getparam {
50609 int param;
50610@@ -708,7 +718,8 @@
50611 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
50612
50613 #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
50614-
50615+#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
50616+#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
50617 /* 1.14: Clients can allocate/free a surface
50618 */
50619 typedef struct drm_radeon_surface_alloc {
50620@@ -721,5 +732,7 @@
50621 unsigned int address;
50622 } drm_radeon_surface_free_t;
50623
50624+#define DRM_RADEON_VBLANK_CRTC1 1
50625+#define DRM_RADEON_VBLANK_CRTC2 2
50626
50627 #endif
50628Index: git/shared-core/radeon_drv.h
50629===================================================================
50630--- /dev/null 1970-01-01 00:00:00.000000000 +0000
50631+++ git/shared-core/radeon_drv.h 2008-12-12 17:35:22.000000000 +0000
50632@@ -0,0 +1,1269 @@
50633+/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
50634+ *
50635+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
50636+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
50637+ * All rights reserved.
50638+ *
50639+ * Permission is hereby granted, free of charge, to any person obtaining a
50640+ * copy of this software and associated documentation files (the "Software"),
50641+ * to deal in the Software without restriction, including without limitation
50642+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
50643+ * and/or sell copies of the Software, and to permit persons to whom the
50644+ * Software is furnished to do so, subject to the following conditions:
50645+ *
50646+ * The above copyright notice and this permission notice (including the next
50647+ * paragraph) shall be included in all copies or substantial portions of the
50648+ * Software.
50649+ *
50650+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
50651+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
50652+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50653+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
50654+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
50655+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
50656+ * DEALINGS IN THE SOFTWARE.
50657+ *
50658+ * Authors:
50659+ * Kevin E. Martin <martin@valinux.com>
50660+ * Gareth Hughes <gareth@valinux.com>
50661+ */
50662+
50663+#ifndef __RADEON_DRV_H__
50664+#define __RADEON_DRV_H__
50665+
50666+/* General customization:
50667+ */
50668+
50669+#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
50670+
50671+#define DRIVER_NAME "radeon"
50672+#define DRIVER_DESC "ATI Radeon"
50673+#define DRIVER_DATE "20060524"
50674+
50675+/* Interface history:
50676+ *
50677+ * 1.1 - ??
50678+ * 1.2 - Add vertex2 ioctl (keith)
50679+ * - Add stencil capability to clear ioctl (gareth, keith)
50680+ * - Increase MAX_TEXTURE_LEVELS (brian)
50681+ * 1.3 - Add cmdbuf ioctl (keith)
50682+ * - Add support for new radeon packets (keith)
50683+ * - Add getparam ioctl (keith)
50684+ * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
50685+ * 1.4 - Add scratch registers to get_param ioctl.
50686+ * 1.5 - Add r200 packets to cmdbuf ioctl
50687+ * - Add r200 function to init ioctl
50688+ * - Add 'scalar2' instruction to cmdbuf
50689+ * 1.6 - Add static GART memory manager
50690+ * Add irq handler (won't be turned on unless X server knows to)
50691+ * Add irq ioctls and irq_active getparam.
50692+ * Add wait command for cmdbuf ioctl
50693+ * Add GART offset query for getparam
50694+ * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
50695+ * and R200_PP_CUBIC_OFFSET_F1_[0..5].
50696+ * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
50697+ * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
50698+ * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
50699+ * Add 'GET' queries for starting additional clients on different VT's.
50700+ * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
50701+ * Add texture rectangle support for r100.
50702+ * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
50703+ * clients use to tell the DRM where they think the framebuffer is
50704+ * located in the card's address space
50705+ * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
50706+ * and GL_EXT_blend_[func|equation]_separate on r200
50707+ * 1.12- Add R300 CP microcode support - this just loads the CP on r300
50708+ * (No 3D support yet - just microcode loading).
50709+ * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
50710+ * - Add hyperz support, add hyperz flags to clear ioctl.
50711+ * 1.14- Add support for color tiling
50712+ * - Add R100/R200 surface allocation/free support
50713+ * 1.15- Add support for texture micro tiling
50714+ * - Add support for r100 cube maps
50715+ * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
50716+ * texture filtering on r200
50717+ * 1.17- Add initial support for R300 (3D).
50718+ * 1.18- Add support for GL_ATI_fragment_shader, new packets
50719+ * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
50720+ * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
50721+ * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
50722+ * 1.19- Add support for gart table in FB memory and PCIE r300
50723+ * 1.20- Add support for r300 texrect
50724+ * 1.21- Add support for card type getparam
50725+ * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
50726+ * 1.23- Add new radeon memory map work from benh
50727+ * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
50728+ * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
50729+ * new packet type)
50730+ * 1.26- Add support for variable size PCI(E) gart aperture
50731+ * 1.27- Add support for IGP GART
50732+ * 1.28- Add support for VBL on CRTC2
50733+ */
50734+
50735+#define DRIVER_MAJOR 1
50736+#define DRIVER_MINOR 28
50737+#define DRIVER_PATCHLEVEL 0
50738+
50739+/*
50740+ * Radeon chip families
50741+ */
50742+enum radeon_family {
50743+ CHIP_R100,
50744+ CHIP_RV100,
50745+ CHIP_RS100,
50746+ CHIP_RV200,
50747+ CHIP_RS200,
50748+ CHIP_R200,
50749+ CHIP_RV250,
50750+ CHIP_RS300,
50751+ CHIP_RV280,
50752+ CHIP_R300,
50753+ CHIP_R350,
50754+ CHIP_RV350,
50755+ CHIP_RV380,
50756+ CHIP_R420,
50757+ CHIP_RV410,
50758+ CHIP_RS400,
50759+ CHIP_LAST,
50760+};
50761+
50762+enum radeon_cp_microcode_version {
50763+ UCODE_R100,
50764+ UCODE_R200,
50765+ UCODE_R300,
50766+};
50767+
50768+/*
50769+ * Chip flags
50770+ */
50771+enum radeon_chip_flags {
50772+ RADEON_FAMILY_MASK = 0x0000ffffUL,
50773+ RADEON_FLAGS_MASK = 0xffff0000UL,
50774+ RADEON_IS_MOBILITY = 0x00010000UL,
50775+ RADEON_IS_IGP = 0x00020000UL,
50776+ RADEON_SINGLE_CRTC = 0x00040000UL,
50777+ RADEON_IS_AGP = 0x00080000UL,
50778+ RADEON_HAS_HIERZ = 0x00100000UL,
50779+ RADEON_IS_PCIE = 0x00200000UL,
50780+ RADEON_NEW_MEMMAP = 0x00400000UL,
50781+ RADEON_IS_PCI = 0x00800000UL,
50782+ RADEON_IS_IGPGART = 0x01000000UL,
50783+};
50784+
50785+#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
50786+ DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
50787+#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
50788+
50789+typedef struct drm_radeon_freelist {
50790+ unsigned int age;
50791+ struct drm_buf *buf;
50792+ struct drm_radeon_freelist *next;
50793+ struct drm_radeon_freelist *prev;
50794+} drm_radeon_freelist_t;
50795+
50796+typedef struct drm_radeon_ring_buffer {
50797+ u32 *start;
50798+ u32 *end;
50799+ int size; /* Double Words */
50800+ int size_l2qw; /* log2 Quad Words */
50801+
50802+ int rptr_update; /* Double Words */
50803+ int rptr_update_l2qw; /* log2 Quad Words */
50804+
50805+ int fetch_size; /* Double Words */
50806+ int fetch_size_l2ow; /* log2 Oct Words */
50807+
50808+ u32 tail;
50809+ u32 tail_mask;
50810+ int space;
50811+
50812+ int high_mark;
50813+} drm_radeon_ring_buffer_t;
50814+
50815+typedef struct drm_radeon_depth_clear_t {
50816+ u32 rb3d_cntl;
50817+ u32 rb3d_zstencilcntl;
50818+ u32 se_cntl;
50819+} drm_radeon_depth_clear_t;
50820+
50821+struct drm_radeon_driver_file_fields {
50822+ int64_t radeon_fb_delta;
50823+};
50824+
50825+struct mem_block {
50826+ struct mem_block *next;
50827+ struct mem_block *prev;
50828+ int start;
50829+ int size;
50830+ struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
50831+};
50832+
50833+struct radeon_surface {
50834+ int refcount;
50835+ u32 lower;
50836+ u32 upper;
50837+ u32 flags;
50838+};
50839+
50840+struct radeon_virt_surface {
50841+ int surface_index;
50842+ u32 lower;
50843+ u32 upper;
50844+ u32 flags;
50845+ struct drm_file *file_priv;
50846+};
50847+
50848+typedef struct drm_radeon_private {
50849+
50850+ drm_radeon_ring_buffer_t ring;
50851+ drm_radeon_sarea_t *sarea_priv;
50852+
50853+ u32 fb_location;
50854+ u32 fb_size;
50855+ int new_memmap;
50856+
50857+ int gart_size;
50858+ u32 gart_vm_start;
50859+ unsigned long gart_buffers_offset;
50860+
50861+ int cp_mode;
50862+ int cp_running;
50863+
50864+ drm_radeon_freelist_t *head;
50865+ drm_radeon_freelist_t *tail;
50866+ int last_buf;
50867+ volatile u32 *scratch;
50868+ int writeback_works;
50869+
50870+ int usec_timeout;
50871+
50872+ int microcode_version;
50873+
50874+ struct {
50875+ u32 boxes;
50876+ int freelist_timeouts;
50877+ int freelist_loops;
50878+ int requested_bufs;
50879+ int last_frame_reads;
50880+ int last_clear_reads;
50881+ int clears;
50882+ int texture_uploads;
50883+ } stats;
50884+
50885+ int do_boxes;
50886+ int page_flipping;
50887+
50888+ u32 color_fmt;
50889+ unsigned int front_offset;
50890+ unsigned int front_pitch;
50891+ unsigned int back_offset;
50892+ unsigned int back_pitch;
50893+
50894+ u32 depth_fmt;
50895+ unsigned int depth_offset;
50896+ unsigned int depth_pitch;
50897+
50898+ u32 front_pitch_offset;
50899+ u32 back_pitch_offset;
50900+ u32 depth_pitch_offset;
50901+
50902+ drm_radeon_depth_clear_t depth_clear;
50903+
50904+ unsigned long ring_offset;
50905+ unsigned long ring_rptr_offset;
50906+ unsigned long buffers_offset;
50907+ unsigned long gart_textures_offset;
50908+
50909+ drm_local_map_t *sarea;
50910+ drm_local_map_t *mmio;
50911+ drm_local_map_t *cp_ring;
50912+ drm_local_map_t *ring_rptr;
50913+ drm_local_map_t *gart_textures;
50914+
50915+ struct mem_block *gart_heap;
50916+ struct mem_block *fb_heap;
50917+
50918+ /* SW interrupt */
50919+ wait_queue_head_t swi_queue;
50920+ atomic_t swi_emitted;
50921+ int vblank_crtc;
50922+ uint32_t irq_enable_reg;
50923+ int irq_enabled;
50924+
50925+ struct radeon_surface surfaces[RADEON_MAX_SURFACES];
50926+ struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
50927+
50928+ unsigned long pcigart_offset;
50929+ unsigned int pcigart_offset_set;
50930+ struct ati_pcigart_info gart_info;
50931+
50932+ u32 scratch_ages[5];
50933+
50934+ /* starting from here on, data is preserved accross an open */
50935+ uint32_t flags; /* see radeon_chip_flags */
50936+
50937+} drm_radeon_private_t;
50938+
50939+typedef struct drm_radeon_buf_priv {
50940+ u32 age;
50941+} drm_radeon_buf_priv_t;
50942+
50943+typedef struct drm_radeon_kcmd_buffer {
50944+ int bufsz;
50945+ char *buf;
50946+ int nbox;
50947+ struct drm_clip_rect __user *boxes;
50948+} drm_radeon_kcmd_buffer_t;
50949+
50950+extern int radeon_no_wb;
50951+extern struct drm_ioctl_desc radeon_ioctls[];
50952+extern int radeon_max_ioctl;
50953+
50954+/* Check whether the given hardware address is inside the framebuffer or the
50955+ * GART area.
50956+ */
50957+static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
50958+ u64 off)
50959+{
50960+ u32 fb_start = dev_priv->fb_location;
50961+ u32 fb_end = fb_start + dev_priv->fb_size - 1;
50962+ u32 gart_start = dev_priv->gart_vm_start;
50963+ u32 gart_end = gart_start + dev_priv->gart_size - 1;
50964+
50965+ return ((off >= fb_start && off <= fb_end) ||
50966+ (off >= gart_start && off <= gart_end));
50967+}
50968+
50969+ /* radeon_cp.c */
50970+extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
50971+extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
50972+extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
50973+extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
50974+extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
50975+extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
50976+extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
50977+extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
50978+extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
50979+
50980+extern void radeon_freelist_reset(struct drm_device * dev);
50981+extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
50982+
50983+extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
50984+
50985+extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
50986+
50987+extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
50988+extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
50989+extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
50990+extern void radeon_mem_takedown(struct mem_block **heap);
50991+extern void radeon_mem_release(struct drm_file *file_priv,
50992+ struct mem_block *heap);
50993+
50994+ /* radeon_irq.c */
50995+extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
50996+extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
50997+
50998+extern void radeon_do_release(struct drm_device * dev);
50999+extern int radeon_driver_vblank_wait(struct drm_device * dev,
51000+ unsigned int *sequence);
51001+extern int radeon_driver_vblank_wait2(struct drm_device * dev,
51002+ unsigned int *sequence);
51003+extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
51004+extern void radeon_driver_irq_preinstall(struct drm_device * dev);
51005+extern void radeon_driver_irq_postinstall(struct drm_device * dev);
51006+extern void radeon_driver_irq_uninstall(struct drm_device * dev);
51007+extern int radeon_vblank_crtc_get(struct drm_device *dev);
51008+extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
51009+
51010+extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
51011+extern int radeon_driver_unload(struct drm_device *dev);
51012+extern int radeon_driver_firstopen(struct drm_device *dev);
51013+extern void radeon_driver_preclose(struct drm_device * dev,
51014+ struct drm_file *file_priv);
51015+extern void radeon_driver_postclose(struct drm_device * dev,
51016+ struct drm_file *file_priv);
51017+extern void radeon_driver_lastclose(struct drm_device * dev);
51018+extern int radeon_driver_open(struct drm_device * dev,
51019+ struct drm_file * file_priv);
51020+extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
51021+ unsigned long arg);
51022+
51023+/* r300_cmdbuf.c */
51024+extern void r300_init_reg_flags(void);
51025+
51026+extern int r300_do_cp_cmdbuf(struct drm_device *dev,
51027+ struct drm_file *file_priv,
51028+ drm_radeon_kcmd_buffer_t* cmdbuf);
51029+
51030+/* Flags for stats.boxes
51031+ */
51032+#define RADEON_BOX_DMA_IDLE 0x1
51033+#define RADEON_BOX_RING_FULL 0x2
51034+#define RADEON_BOX_FLIP 0x4
51035+#define RADEON_BOX_WAIT_IDLE 0x8
51036+#define RADEON_BOX_TEXTURE_LOAD 0x10
51037+
51038+/* Register definitions, register access macros and drmAddMap constants
51039+ * for Radeon kernel driver.
51040+ */
51041+#define RADEON_AGP_COMMAND 0x0f60
51042+#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
51043+# define RADEON_AGP_ENABLE (1<<8)
51044+#define RADEON_AUX_SCISSOR_CNTL 0x26f0
51045+# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
51046+# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
51047+# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
51048+# define RADEON_SCISSOR_0_ENABLE (1 << 28)
51049+# define RADEON_SCISSOR_1_ENABLE (1 << 29)
51050+# define RADEON_SCISSOR_2_ENABLE (1 << 30)
51051+
51052+#define RADEON_BUS_CNTL 0x0030
51053+# define RADEON_BUS_MASTER_DIS (1 << 6)
51054+
51055+#define RADEON_CLOCK_CNTL_DATA 0x000c
51056+# define RADEON_PLL_WR_EN (1 << 7)
51057+#define RADEON_CLOCK_CNTL_INDEX 0x0008
51058+#define RADEON_CONFIG_APER_SIZE 0x0108
51059+#define RADEON_CONFIG_MEMSIZE 0x00f8
51060+#define RADEON_CRTC_OFFSET 0x0224
51061+#define RADEON_CRTC_OFFSET_CNTL 0x0228
51062+# define RADEON_CRTC_TILE_EN (1 << 15)
51063+# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
51064+#define RADEON_CRTC2_OFFSET 0x0324
51065+#define RADEON_CRTC2_OFFSET_CNTL 0x0328
51066+
51067+#define RADEON_PCIE_INDEX 0x0030
51068+#define RADEON_PCIE_DATA 0x0034
51069+#define RADEON_PCIE_TX_GART_CNTL 0x10
51070+# define RADEON_PCIE_TX_GART_EN (1 << 0)
51071+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
51072+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
51073+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
51074+# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
51075+# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
51076+# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
51077+# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
51078+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
51079+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
51080+#define RADEON_PCIE_TX_GART_BASE 0x13
51081+#define RADEON_PCIE_TX_GART_START_LO 0x14
51082+#define RADEON_PCIE_TX_GART_START_HI 0x15
51083+#define RADEON_PCIE_TX_GART_END_LO 0x16
51084+#define RADEON_PCIE_TX_GART_END_HI 0x17
51085+
51086+#define RADEON_IGPGART_INDEX 0x168
51087+#define RADEON_IGPGART_DATA 0x16c
51088+#define RADEON_IGPGART_UNK_18 0x18
51089+#define RADEON_IGPGART_CTRL 0x2b
51090+#define RADEON_IGPGART_BASE_ADDR 0x2c
51091+#define RADEON_IGPGART_FLUSH 0x2e
51092+#define RADEON_IGPGART_ENABLE 0x38
51093+#define RADEON_IGPGART_UNK_39 0x39
51094+
51095+
51096+#define RADEON_MPP_TB_CONFIG 0x01c0
51097+#define RADEON_MEM_CNTL 0x0140
51098+#define RADEON_MEM_SDRAM_MODE_REG 0x0158
51099+#define RADEON_AGP_BASE 0x0170
51100+
51101+#define RADEON_RB3D_COLOROFFSET 0x1c40
51102+#define RADEON_RB3D_COLORPITCH 0x1c48
51103+
51104+#define RADEON_SRC_X_Y 0x1590
51105+
51106+#define RADEON_DP_GUI_MASTER_CNTL 0x146c
51107+# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
51108+# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
51109+# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
51110+# define RADEON_GMC_BRUSH_NONE (15 << 4)
51111+# define RADEON_GMC_DST_16BPP (4 << 8)
51112+# define RADEON_GMC_DST_24BPP (5 << 8)
51113+# define RADEON_GMC_DST_32BPP (6 << 8)
51114+# define RADEON_GMC_DST_DATATYPE_SHIFT 8
51115+# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
51116+# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
51117+# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
51118+# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
51119+# define RADEON_GMC_WR_MSK_DIS (1 << 30)
51120+# define RADEON_ROP3_S 0x00cc0000
51121+# define RADEON_ROP3_P 0x00f00000
51122+#define RADEON_DP_WRITE_MASK 0x16cc
51123+#define RADEON_SRC_PITCH_OFFSET 0x1428
51124+#define RADEON_DST_PITCH_OFFSET 0x142c
51125+#define RADEON_DST_PITCH_OFFSET_C 0x1c80
51126+# define RADEON_DST_TILE_LINEAR (0 << 30)
51127+# define RADEON_DST_TILE_MACRO (1 << 30)
51128+# define RADEON_DST_TILE_MICRO (2 << 30)
51129+# define RADEON_DST_TILE_BOTH (3 << 30)
51130+
51131+#define RADEON_SCRATCH_REG0 0x15e0
51132+#define RADEON_SCRATCH_REG1 0x15e4
51133+#define RADEON_SCRATCH_REG2 0x15e8
51134+#define RADEON_SCRATCH_REG3 0x15ec
51135+#define RADEON_SCRATCH_REG4 0x15f0
51136+#define RADEON_SCRATCH_REG5 0x15f4
51137+#define RADEON_SCRATCH_UMSK 0x0770
51138+#define RADEON_SCRATCH_ADDR 0x0774
51139+
51140+#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
51141+
51142+#define GET_SCRATCH( x ) (dev_priv->writeback_works \
51143+ ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
51144+ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
51145+
51146+#define RADEON_GEN_INT_CNTL 0x0040
51147+# define RADEON_CRTC_VBLANK_MASK (1 << 0)
51148+# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
51149+# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
51150+# define RADEON_SW_INT_ENABLE (1 << 25)
51151+
51152+#define RADEON_GEN_INT_STATUS 0x0044
51153+# define RADEON_CRTC_VBLANK_STAT (1 << 0)
51154+# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
51155+# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
51156+# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
51157+# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
51158+# define RADEON_SW_INT_TEST (1 << 25)
51159+# define RADEON_SW_INT_TEST_ACK (1 << 25)
51160+# define RADEON_SW_INT_FIRE (1 << 26)
51161+
51162+#define RADEON_HOST_PATH_CNTL 0x0130
51163+# define RADEON_HDP_SOFT_RESET (1 << 26)
51164+# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
51165+# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
51166+
51167+#define RADEON_ISYNC_CNTL 0x1724
51168+# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
51169+# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
51170+# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
51171+# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
51172+# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
51173+# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
51174+
51175+#define RADEON_RBBM_GUICNTL 0x172c
51176+# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
51177+# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
51178+# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
51179+# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
51180+
51181+#define RADEON_MC_AGP_LOCATION 0x014c
51182+#define RADEON_MC_FB_LOCATION 0x0148
51183+#define RADEON_MCLK_CNTL 0x0012
51184+# define RADEON_FORCEON_MCLKA (1 << 16)
51185+# define RADEON_FORCEON_MCLKB (1 << 17)
51186+# define RADEON_FORCEON_YCLKA (1 << 18)
51187+# define RADEON_FORCEON_YCLKB (1 << 19)
51188+# define RADEON_FORCEON_MC (1 << 20)
51189+# define RADEON_FORCEON_AIC (1 << 21)
51190+
51191+#define RADEON_PP_BORDER_COLOR_0 0x1d40
51192+#define RADEON_PP_BORDER_COLOR_1 0x1d44
51193+#define RADEON_PP_BORDER_COLOR_2 0x1d48
51194+#define RADEON_PP_CNTL 0x1c38
51195+# define RADEON_SCISSOR_ENABLE (1 << 1)
51196+#define RADEON_PP_LUM_MATRIX 0x1d00
51197+#define RADEON_PP_MISC 0x1c14
51198+#define RADEON_PP_ROT_MATRIX_0 0x1d58
51199+#define RADEON_PP_TXFILTER_0 0x1c54
51200+#define RADEON_PP_TXOFFSET_0 0x1c5c
51201+#define RADEON_PP_TXFILTER_1 0x1c6c
51202+#define RADEON_PP_TXFILTER_2 0x1c84
51203+
51204+#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
51205+# define RADEON_RB2D_DC_FLUSH (3 << 0)
51206+# define RADEON_RB2D_DC_FREE (3 << 2)
51207+# define RADEON_RB2D_DC_FLUSH_ALL 0xf
51208+# define RADEON_RB2D_DC_BUSY (1 << 31)
51209+#define RADEON_RB3D_CNTL 0x1c3c
51210+# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
51211+# define RADEON_PLANE_MASK_ENABLE (1 << 1)
51212+# define RADEON_DITHER_ENABLE (1 << 2)
51213+# define RADEON_ROUND_ENABLE (1 << 3)
51214+# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
51215+# define RADEON_DITHER_INIT (1 << 5)
51216+# define RADEON_ROP_ENABLE (1 << 6)
51217+# define RADEON_STENCIL_ENABLE (1 << 7)
51218+# define RADEON_Z_ENABLE (1 << 8)
51219+# define RADEON_ZBLOCK16 (1 << 15)
51220+#define RADEON_RB3D_DEPTHOFFSET 0x1c24
51221+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
51222+#define RADEON_RB3D_DEPTHPITCH 0x1c28
51223+#define RADEON_RB3D_PLANEMASK 0x1d84
51224+#define RADEON_RB3D_STENCILREFMASK 0x1d7c
51225+#define RADEON_RB3D_ZCACHE_MODE 0x3250
51226+#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
51227+# define RADEON_RB3D_ZC_FLUSH (1 << 0)
51228+# define RADEON_RB3D_ZC_FREE (1 << 2)
51229+# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
51230+# define RADEON_RB3D_ZC_BUSY (1 << 31)
51231+#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
51232+# define RADEON_RB3D_DC_FLUSH (3 << 0)
51233+# define RADEON_RB3D_DC_FREE (3 << 2)
51234+# define RADEON_RB3D_DC_FLUSH_ALL 0xf
51235+# define RADEON_RB3D_DC_BUSY (1 << 31)
51236+#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
51237+# define RADEON_Z_TEST_MASK (7 << 4)
51238+# define RADEON_Z_TEST_ALWAYS (7 << 4)
51239+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
51240+# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
51241+# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
51242+# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
51243+# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
51244+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
51245+# define RADEON_FORCE_Z_DIRTY (1 << 29)
51246+# define RADEON_Z_WRITE_ENABLE (1 << 30)
51247+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
51248+#define RADEON_RBBM_SOFT_RESET 0x00f0
51249+# define RADEON_SOFT_RESET_CP (1 << 0)
51250+# define RADEON_SOFT_RESET_HI (1 << 1)
51251+# define RADEON_SOFT_RESET_SE (1 << 2)
51252+# define RADEON_SOFT_RESET_RE (1 << 3)
51253+# define RADEON_SOFT_RESET_PP (1 << 4)
51254+# define RADEON_SOFT_RESET_E2 (1 << 5)
51255+# define RADEON_SOFT_RESET_RB (1 << 6)
51256+# define RADEON_SOFT_RESET_HDP (1 << 7)
51257+/*
51258+ * 6:0 Available slots in the FIFO
51259+ * 8 Host Interface active
51260+ * 9 CP request active
51261+ * 10 FIFO request active
51262+ * 11 Host Interface retry active
51263+ * 12 CP retry active
51264+ * 13 FIFO retry active
51265+ * 14 FIFO pipeline busy
51266+ * 15 Event engine busy
51267+ * 16 CP command stream busy
51268+ * 17 2D engine busy
51269+ * 18 2D portion of render backend busy
51270+ * 20 3D setup engine busy
51271+ * 26 GA engine busy
51272+ * 27 CBA 2D engine busy
51273+ * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
51274+ * command stream queue not empty or Ring Buffer not empty
51275+ */
51276+#define RADEON_RBBM_STATUS 0x0e40
51277+/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
51278+/* #define RADEON_RBBM_STATUS 0x1740 */
51279+/* bits 6:0 are dword slots available in the cmd fifo */
51280+# define RADEON_RBBM_FIFOCNT_MASK 0x007f
51281+# define RADEON_HIRQ_ON_RBB (1 << 8)
51282+# define RADEON_CPRQ_ON_RBB (1 << 9)
51283+# define RADEON_CFRQ_ON_RBB (1 << 10)
51284+# define RADEON_HIRQ_IN_RTBUF (1 << 11)
51285+# define RADEON_CPRQ_IN_RTBUF (1 << 12)
51286+# define RADEON_CFRQ_IN_RTBUF (1 << 13)
51287+# define RADEON_PIPE_BUSY (1 << 14)
51288+# define RADEON_ENG_EV_BUSY (1 << 15)
51289+# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
51290+# define RADEON_E2_BUSY (1 << 17)
51291+# define RADEON_RB2D_BUSY (1 << 18)
51292+# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
51293+# define RADEON_VAP_BUSY (1 << 20)
51294+# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
51295+# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
51296+# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
51297+# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
51298+# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
51299+# define RADEON_GA_BUSY (1 << 26)
51300+# define RADEON_CBA2D_BUSY (1 << 27)
51301+# define RADEON_RBBM_ACTIVE (1 << 31)
51302+#define RADEON_RE_LINE_PATTERN 0x1cd0
51303+#define RADEON_RE_MISC 0x26c4
51304+#define RADEON_RE_TOP_LEFT 0x26c0
51305+#define RADEON_RE_WIDTH_HEIGHT 0x1c44
51306+#define RADEON_RE_STIPPLE_ADDR 0x1cc8
51307+#define RADEON_RE_STIPPLE_DATA 0x1ccc
51308+
51309+#define RADEON_SCISSOR_TL_0 0x1cd8
51310+#define RADEON_SCISSOR_BR_0 0x1cdc
51311+#define RADEON_SCISSOR_TL_1 0x1ce0
51312+#define RADEON_SCISSOR_BR_1 0x1ce4
51313+#define RADEON_SCISSOR_TL_2 0x1ce8
51314+#define RADEON_SCISSOR_BR_2 0x1cec
51315+#define RADEON_SE_COORD_FMT 0x1c50
51316+#define RADEON_SE_CNTL 0x1c4c
51317+# define RADEON_FFACE_CULL_CW (0 << 0)
51318+# define RADEON_BFACE_SOLID (3 << 1)
51319+# define RADEON_FFACE_SOLID (3 << 3)
51320+# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
51321+# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
51322+# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
51323+# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
51324+# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
51325+# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
51326+# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
51327+# define RADEON_FOG_SHADE_FLAT (1 << 14)
51328+# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
51329+# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
51330+# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
51331+# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
51332+# define RADEON_ROUND_MODE_TRUNC (0 << 28)
51333+# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
51334+#define RADEON_SE_CNTL_STATUS 0x2140
51335+#define RADEON_SE_LINE_WIDTH 0x1db8
51336+#define RADEON_SE_VPORT_XSCALE 0x1d98
51337+#define RADEON_SE_ZBIAS_FACTOR 0x1db0
51338+#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
51339+#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
51340+#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
51341+# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
51342+# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
51343+#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
51344+#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
51345+# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
51346+#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
51347+#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
51348+#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
51349+#define RADEON_SURFACE_CNTL 0x0b00
51350+# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
51351+# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
51352+# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
51353+# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
51354+# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
51355+# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
51356+# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
51357+# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
51358+# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
51359+#define RADEON_SURFACE0_INFO 0x0b0c
51360+# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
51361+# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
51362+# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
51363+# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
51364+# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
51365+# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
51366+#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
51367+#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
51368+# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
51369+#define RADEON_SURFACE1_INFO 0x0b1c
51370+#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
51371+#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
51372+#define RADEON_SURFACE2_INFO 0x0b2c
51373+#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
51374+#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
51375+#define RADEON_SURFACE3_INFO 0x0b3c
51376+#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
51377+#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
51378+#define RADEON_SURFACE4_INFO 0x0b4c
51379+#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
51380+#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
51381+#define RADEON_SURFACE5_INFO 0x0b5c
51382+#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
51383+#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
51384+#define RADEON_SURFACE6_INFO 0x0b6c
51385+#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
51386+#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
51387+#define RADEON_SURFACE7_INFO 0x0b7c
51388+#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
51389+#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
51390+#define RADEON_SW_SEMAPHORE 0x013c
51391+
51392+#define RADEON_WAIT_UNTIL 0x1720
51393+# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
51394+# define RADEON_WAIT_2D_IDLE (1 << 14)
51395+# define RADEON_WAIT_3D_IDLE (1 << 15)
51396+# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
51397+# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
51398+# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
51399+
51400+#define RADEON_RB3D_ZMASKOFFSET 0x3234
51401+#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
51402+# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
51403+# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
51404+
51405+/* CP registers */
51406+#define RADEON_CP_ME_RAM_ADDR 0x07d4
51407+#define RADEON_CP_ME_RAM_RADDR 0x07d8
51408+#define RADEON_CP_ME_RAM_DATAH 0x07dc
51409+#define RADEON_CP_ME_RAM_DATAL 0x07e0
51410+
51411+#define RADEON_CP_RB_BASE 0x0700
51412+#define RADEON_CP_RB_CNTL 0x0704
51413+# define RADEON_BUF_SWAP_32BIT (2 << 16)
51414+# define RADEON_RB_NO_UPDATE (1 << 27)
51415+#define RADEON_CP_RB_RPTR_ADDR 0x070c
51416+#define RADEON_CP_RB_RPTR 0x0710
51417+#define RADEON_CP_RB_WPTR 0x0714
51418+
51419+#define RADEON_CP_RB_WPTR_DELAY 0x0718
51420+# define RADEON_PRE_WRITE_TIMER_SHIFT 0
51421+# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
51422+
51423+#define RADEON_CP_IB_BASE 0x0738
51424+
51425+#define RADEON_CP_CSQ_CNTL 0x0740
51426+# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
51427+# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
51428+# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
51429+# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
51430+# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
51431+# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
51432+# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
51433+
51434+#define RADEON_AIC_CNTL 0x01d0
51435+# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
51436+#define RADEON_AIC_STAT 0x01d4
51437+#define RADEON_AIC_PT_BASE 0x01d8
51438+#define RADEON_AIC_LO_ADDR 0x01dc
51439+#define RADEON_AIC_HI_ADDR 0x01e0
51440+#define RADEON_AIC_TLB_ADDR 0x01e4
51441+#define RADEON_AIC_TLB_DATA 0x01e8
51442+
51443+/* CP command packets */
51444+#define RADEON_CP_PACKET0 0x00000000
51445+# define RADEON_ONE_REG_WR (1 << 15)
51446+#define RADEON_CP_PACKET1 0x40000000
51447+#define RADEON_CP_PACKET2 0x80000000
51448+#define RADEON_CP_PACKET3 0xC0000000
51449+# define RADEON_CP_NOP 0x00001000
51450+# define RADEON_CP_NEXT_CHAR 0x00001900
51451+# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
51452+# define RADEON_CP_SET_SCISSORS 0x00001E00
51453+ /* GEN_INDX_PRIM is unsupported starting with R300 */
51454+# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
51455+# define RADEON_WAIT_FOR_IDLE 0x00002600
51456+# define RADEON_3D_DRAW_VBUF 0x00002800
51457+# define RADEON_3D_DRAW_IMMD 0x00002900
51458+# define RADEON_3D_DRAW_INDX 0x00002A00
51459+# define RADEON_CP_LOAD_PALETTE 0x00002C00
51460+# define RADEON_3D_LOAD_VBPNTR 0x00002F00
51461+# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
51462+# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
51463+# define RADEON_3D_CLEAR_ZMASK 0x00003200
51464+# define RADEON_CP_INDX_BUFFER 0x00003300
51465+# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
51466+# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
51467+# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
51468+# define RADEON_3D_CLEAR_HIZ 0x00003700
51469+# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
51470+# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
51471+# define RADEON_CNTL_PAINT_MULTI 0x00009A00
51472+# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
51473+# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
51474+
51475+#define RADEON_CP_PACKET_MASK 0xC0000000
51476+#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
51477+#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
51478+#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
51479+#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
51480+
51481+#define RADEON_VTX_Z_PRESENT (1 << 31)
51482+#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
51483+
51484+#define RADEON_PRIM_TYPE_NONE (0 << 0)
51485+#define RADEON_PRIM_TYPE_POINT (1 << 0)
51486+#define RADEON_PRIM_TYPE_LINE (2 << 0)
51487+#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
51488+#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
51489+#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
51490+#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
51491+#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
51492+#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
51493+#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
51494+#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
51495+#define RADEON_PRIM_TYPE_MASK 0xf
51496+#define RADEON_PRIM_WALK_IND (1 << 4)
51497+#define RADEON_PRIM_WALK_LIST (2 << 4)
51498+#define RADEON_PRIM_WALK_RING (3 << 4)
51499+#define RADEON_COLOR_ORDER_BGRA (0 << 6)
51500+#define RADEON_COLOR_ORDER_RGBA (1 << 6)
51501+#define RADEON_MAOS_ENABLE (1 << 7)
51502+#define RADEON_VTX_FMT_R128_MODE (0 << 8)
51503+#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
51504+#define RADEON_NUM_VERTICES_SHIFT 16
51505+
51506+#define RADEON_COLOR_FORMAT_CI8 2
51507+#define RADEON_COLOR_FORMAT_ARGB1555 3
51508+#define RADEON_COLOR_FORMAT_RGB565 4
51509+#define RADEON_COLOR_FORMAT_ARGB8888 6
51510+#define RADEON_COLOR_FORMAT_RGB332 7
51511+#define RADEON_COLOR_FORMAT_RGB8 9
51512+#define RADEON_COLOR_FORMAT_ARGB4444 15
51513+
51514+#define RADEON_TXFORMAT_I8 0
51515+#define RADEON_TXFORMAT_AI88 1
51516+#define RADEON_TXFORMAT_RGB332 2
51517+#define RADEON_TXFORMAT_ARGB1555 3
51518+#define RADEON_TXFORMAT_RGB565 4
51519+#define RADEON_TXFORMAT_ARGB4444 5
51520+#define RADEON_TXFORMAT_ARGB8888 6
51521+#define RADEON_TXFORMAT_RGBA8888 7
51522+#define RADEON_TXFORMAT_Y8 8
51523+#define RADEON_TXFORMAT_VYUY422 10
51524+#define RADEON_TXFORMAT_YVYU422 11
51525+#define RADEON_TXFORMAT_DXT1 12
51526+#define RADEON_TXFORMAT_DXT23 14
51527+#define RADEON_TXFORMAT_DXT45 15
51528+
51529+#define R200_PP_TXCBLEND_0 0x2f00
51530+#define R200_PP_TXCBLEND_1 0x2f10
51531+#define R200_PP_TXCBLEND_2 0x2f20
51532+#define R200_PP_TXCBLEND_3 0x2f30
51533+#define R200_PP_TXCBLEND_4 0x2f40
51534+#define R200_PP_TXCBLEND_5 0x2f50
51535+#define R200_PP_TXCBLEND_6 0x2f60
51536+#define R200_PP_TXCBLEND_7 0x2f70
51537+#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
51538+#define R200_PP_TFACTOR_0 0x2ee0
51539+#define R200_SE_VTX_FMT_0 0x2088
51540+#define R200_SE_VAP_CNTL 0x2080
51541+#define R200_SE_TCL_MATRIX_SEL_0 0x2230
51542+#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
51543+#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
51544+#define R200_PP_TXFILTER_5 0x2ca0
51545+#define R200_PP_TXFILTER_4 0x2c80
51546+#define R200_PP_TXFILTER_3 0x2c60
51547+#define R200_PP_TXFILTER_2 0x2c40
51548+#define R200_PP_TXFILTER_1 0x2c20
51549+#define R200_PP_TXFILTER_0 0x2c00
51550+#define R200_PP_TXOFFSET_5 0x2d78
51551+#define R200_PP_TXOFFSET_4 0x2d60
51552+#define R200_PP_TXOFFSET_3 0x2d48
51553+#define R200_PP_TXOFFSET_2 0x2d30
51554+#define R200_PP_TXOFFSET_1 0x2d18
51555+#define R200_PP_TXOFFSET_0 0x2d00
51556+
51557+#define R200_PP_CUBIC_FACES_0 0x2c18
51558+#define R200_PP_CUBIC_FACES_1 0x2c38
51559+#define R200_PP_CUBIC_FACES_2 0x2c58
51560+#define R200_PP_CUBIC_FACES_3 0x2c78
51561+#define R200_PP_CUBIC_FACES_4 0x2c98
51562+#define R200_PP_CUBIC_FACES_5 0x2cb8
51563+#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
51564+#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
51565+#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
51566+#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
51567+#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
51568+#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
51569+#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
51570+#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
51571+#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
51572+#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
51573+#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
51574+#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
51575+#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
51576+#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
51577+#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
51578+#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
51579+#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
51580+#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
51581+#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
51582+#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
51583+#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
51584+#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
51585+#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
51586+#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
51587+#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
51588+#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
51589+#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
51590+#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
51591+#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
51592+#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
51593+
51594+#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
51595+#define R200_SE_VTE_CNTL 0x20b0
51596+#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
51597+#define R200_PP_TAM_DEBUG3 0x2d9c
51598+#define R200_PP_CNTL_X 0x2cc4
51599+#define R200_SE_VAP_CNTL_STATUS 0x2140
51600+#define R200_RE_SCISSOR_TL_0 0x1cd8
51601+#define R200_RE_SCISSOR_TL_1 0x1ce0
51602+#define R200_RE_SCISSOR_TL_2 0x1ce8
51603+#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
51604+#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
51605+#define R200_SE_VTX_STATE_CNTL 0x2180
51606+#define R200_RE_POINTSIZE 0x2648
51607+#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
51608+
51609+#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
51610+#define RADEON_PP_TEX_SIZE_1 0x1d0c
51611+#define RADEON_PP_TEX_SIZE_2 0x1d14
51612+
51613+#define RADEON_PP_CUBIC_FACES_0 0x1d24
51614+#define RADEON_PP_CUBIC_FACES_1 0x1d28
51615+#define RADEON_PP_CUBIC_FACES_2 0x1d2c
51616+#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
51617+#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
51618+#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
51619+
51620+#define RADEON_SE_TCL_STATE_FLUSH 0x2284
51621+
51622+#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
51623+#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
51624+#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
51625+#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
51626+#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
51627+#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
51628+#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
51629+#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
51630+#define R200_3D_DRAW_IMMD_2 0xC0003500
51631+#define R200_SE_VTX_FMT_1 0x208c
51632+#define R200_RE_CNTL 0x1c50
51633+
51634+#define R200_RB3D_BLENDCOLOR 0x3218
51635+
51636+#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
51637+
51638+#define R200_PP_TRI_PERF 0x2cf8
51639+
51640+#define R200_PP_AFS_0 0x2f80
51641+#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
51642+
51643+#define R200_VAP_PVS_CNTL_1 0x22D0
51644+
51645+/* MPEG settings from VHA code */
51646+#define RADEON_VHA_SETTO16_1 0x2694
51647+#define RADEON_VHA_SETTO16_2 0x2680
51648+#define RADEON_VHA_SETTO0_1 0x1840
51649+#define RADEON_VHA_FB_OFFSET 0x19e4
51650+#define RADEON_VHA_SETTO1AND70S 0x19d8
51651+#define RADEON_VHA_DST_PITCH 0x1408
51652+
51653+// set as reference header
51654+#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
51655+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
51656+#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
51657+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
51658+#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
51659+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
51660+#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
51661+#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
51662+#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
51663+#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
51664+#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
51665+#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
51666+#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
51667+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
51668+#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
51669+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
51670+#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
51671+#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
51672+
51673+
51674+
51675+/* Constants */
51676+#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
51677+
51678+#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
51679+#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
51680+#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
51681+#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
51682+#define RADEON_LAST_DISPATCH 1
51683+
51684+#define RADEON_MAX_VB_AGE 0x7fffffff
51685+#define RADEON_MAX_VB_VERTS (0xffff)
51686+
51687+#define RADEON_RING_HIGH_MARK 128
51688+
51689+#define RADEON_PCIGART_TABLE_SIZE (32*1024)
51690+
51691+#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
51692+#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
51693+#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
51694+#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
51695+
51696+#define RADEON_WRITE_PLL( addr, val ) \
51697+do { \
51698+ RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
51699+ ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
51700+ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
51701+} while (0)
51702+
51703+#define RADEON_WRITE_IGPGART( addr, val ) \
51704+do { \
51705+ RADEON_WRITE( RADEON_IGPGART_INDEX, \
51706+ ((addr) & 0x7f) | (1 << 8)); \
51707+ RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \
51708+ RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \
51709+} while (0)
51710+
51711+#define RADEON_WRITE_PCIE( addr, val ) \
51712+do { \
51713+ RADEON_WRITE8( RADEON_PCIE_INDEX, \
51714+ ((addr) & 0xff)); \
51715+ RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
51716+} while (0)
51717+
51718+#define CP_PACKET0( reg, n ) \
51719+ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
51720+#define CP_PACKET0_TABLE( reg, n ) \
51721+ (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
51722+#define CP_PACKET1( reg0, reg1 ) \
51723+ (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
51724+#define CP_PACKET2() \
51725+ (RADEON_CP_PACKET2)
51726+#define CP_PACKET3( pkt, n ) \
51727+ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
51728+
51729+/* ================================================================
51730+ * Engine control helper macros
51731+ */
51732+
51733+#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
51734+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
51735+ OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
51736+ RADEON_WAIT_HOST_IDLECLEAN) ); \
51737+} while (0)
51738+
51739+#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
51740+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
51741+ OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
51742+ RADEON_WAIT_HOST_IDLECLEAN) ); \
51743+} while (0)
51744+
51745+#define RADEON_WAIT_UNTIL_IDLE() do { \
51746+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
51747+ OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
51748+ RADEON_WAIT_3D_IDLECLEAN | \
51749+ RADEON_WAIT_HOST_IDLECLEAN) ); \
51750+} while (0)
51751+
51752+#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
51753+ OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
51754+ OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
51755+} while (0)
51756+
51757+#define RADEON_FLUSH_CACHE() do { \
51758+ OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
51759+ OUT_RING( RADEON_RB3D_DC_FLUSH ); \
51760+} while (0)
51761+
51762+#define RADEON_PURGE_CACHE() do { \
51763+ OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
51764+ OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
51765+} while (0)
51766+
51767+#define RADEON_FLUSH_ZCACHE() do { \
51768+ OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
51769+ OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
51770+} while (0)
51771+
51772+#define RADEON_PURGE_ZCACHE() do { \
51773+ OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
51774+ OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
51775+} while (0)
51776+
51777+/* ================================================================
51778+ * Misc helper macros
51779+ */
51780+
51781+/* Perfbox functionality only.
51782+ */
51783+#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
51784+do { \
51785+ if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
51786+ u32 head = GET_RING_HEAD( dev_priv ); \
51787+ if (head == dev_priv->ring.tail) \
51788+ dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
51789+ } \
51790+} while (0)
51791+
51792+#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
51793+do { \
51794+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
51795+ if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
51796+ int __ret = radeon_do_cp_idle( dev_priv ); \
51797+ if ( __ret ) return __ret; \
51798+ sarea_priv->last_dispatch = 0; \
51799+ radeon_freelist_reset( dev ); \
51800+ } \
51801+} while (0)
51802+
51803+#define RADEON_DISPATCH_AGE( age ) do { \
51804+ OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
51805+ OUT_RING( age ); \
51806+} while (0)
51807+
51808+#define RADEON_FRAME_AGE( age ) do { \
51809+ OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
51810+ OUT_RING( age ); \
51811+} while (0)
51812+
51813+#define RADEON_CLEAR_AGE( age ) do { \
51814+ OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
51815+ OUT_RING( age ); \
51816+} while (0)
51817+
51818+/* ================================================================
51819+ * Ring control
51820+ */
51821+
51822+#define RADEON_VERBOSE 0
51823+
51824+#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
51825+
51826+#define BEGIN_RING( n ) do { \
51827+ if ( RADEON_VERBOSE ) { \
51828+ DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
51829+ n, __FUNCTION__ ); \
51830+ } \
51831+ if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
51832+ COMMIT_RING(); \
51833+ radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
51834+ } \
51835+ _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
51836+ ring = dev_priv->ring.start; \
51837+ write = dev_priv->ring.tail; \
51838+ mask = dev_priv->ring.tail_mask; \
51839+} while (0)
51840+
51841+#define ADVANCE_RING() do { \
51842+ if ( RADEON_VERBOSE ) { \
51843+ DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
51844+ write, dev_priv->ring.tail ); \
51845+ } \
51846+ if (((dev_priv->ring.tail + _nr) & mask) != write) { \
51847+ DRM_ERROR( \
51848+ "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
51849+ ((dev_priv->ring.tail + _nr) & mask), \
51850+ write, __LINE__); \
51851+ } else \
51852+ dev_priv->ring.tail = write; \
51853+} while (0)
51854+
51855+#define COMMIT_RING() do { \
51856+ /* Flush writes to ring */ \
51857+ DRM_MEMORYBARRIER(); \
51858+ GET_RING_HEAD( dev_priv ); \
51859+ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
51860+ /* read from PCI bus to ensure correct posting */ \
51861+ RADEON_READ( RADEON_CP_RB_RPTR ); \
51862+} while (0)
51863+
51864+#define OUT_RING( x ) do { \
51865+ if ( RADEON_VERBOSE ) { \
51866+ DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
51867+ (unsigned int)(x), write ); \
51868+ } \
51869+ ring[write++] = (x); \
51870+ write &= mask; \
51871+} while (0)
51872+
51873+#define OUT_RING_REG( reg, val ) do { \
51874+ OUT_RING( CP_PACKET0( reg, 0 ) ); \
51875+ OUT_RING( val ); \
51876+} while (0)
51877+
51878+#define OUT_RING_TABLE( tab, sz ) do { \
51879+ int _size = (sz); \
51880+ int *_tab = (int *)(tab); \
51881+ \
51882+ if (write + _size > mask) { \
51883+ int _i = (mask+1) - write; \
51884+ _size -= _i; \
51885+ while (_i > 0) { \
51886+ *(int *)(ring + write) = *_tab++; \
51887+ write++; \
51888+ _i--; \
51889+ } \
51890+ write = 0; \
51891+ _tab += _i; \
51892+ } \
51893+ while (_size > 0) { \
51894+ *(ring + write) = *_tab++; \
51895+ write++; \
51896+ _size--; \
51897+ } \
51898+ write &= mask; \
51899+} while (0)
51900+
51901+#endif /* __RADEON_DRV_H__ */
51902Index: git/shared-core/radeon_irq.c
51903===================================================================
51904--- /dev/null 1970-01-01 00:00:00.000000000 +0000
51905+++ git/shared-core/radeon_irq.c 2008-12-12 17:35:22.000000000 +0000
51906@@ -0,0 +1,321 @@
51907+/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
51908+/*
51909+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
51910+ *
51911+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
51912+ * initial release of the Radeon 8500 driver under the XFree86 license.
51913+ * This notice must be preserved.
51914+ *
51915+ * Permission is hereby granted, free of charge, to any person obtaining a
51916+ * copy of this software and associated documentation files (the "Software"),
51917+ * to deal in the Software without restriction, including without limitation
51918+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
51919+ * and/or sell copies of the Software, and to permit persons to whom the
51920+ * Software is furnished to do so, subject to the following conditions:
51921+ *
51922+ * The above copyright notice and this permission notice (including the next
51923+ * paragraph) shall be included in all copies or substantial portions of the
51924+ * Software.
51925+ *
51926+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
51927+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
51928+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
51929+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
51930+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
51931+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
51932+ * DEALINGS IN THE SOFTWARE.
51933+ *
51934+ * Authors:
51935+ * Keith Whitwell <keith@tungstengraphics.com>
51936+ * Michel D�zer <michel@daenzer.net>
51937+ */
51938+
51939+#include "drmP.h"
51940+#include "drm.h"
51941+#include "radeon_drm.h"
51942+#include "radeon_drv.h"
51943+
51944+static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
51945+ u32 mask)
51946+{
51947+ u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
51948+ if (irqs)
51949+ RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
51950+ return irqs;
51951+}
51952+
51953+/* Interrupts - Used for device synchronization and flushing in the
51954+ * following circumstances:
51955+ *
51956+ * - Exclusive FB access with hw idle:
51957+ * - Wait for GUI Idle (?) interrupt, then do normal flush.
51958+ *
51959+ * - Frame throttling, NV_fence:
51960+ * - Drop marker irq's into command stream ahead of time.
51961+ * - Wait on irq's with lock *not held*
51962+ * - Check each for termination condition
51963+ *
51964+ * - Internally in cp_getbuffer, etc:
51965+ * - as above, but wait with lock held???
51966+ *
51967+ * NOTE: These functions are misleadingly named -- the irq's aren't
51968+ * tied to dma at all, this is just a hangover from dri prehistory.
51969+ */
51970+
51971+irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
51972+{
51973+ struct drm_device *dev = (struct drm_device *) arg;
51974+ drm_radeon_private_t *dev_priv =
51975+ (drm_radeon_private_t *) dev->dev_private;
51976+ u32 stat;
51977+
51978+ /* Only consider the bits we're interested in - others could be used
51979+ * outside the DRM
51980+ */
51981+ stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
51982+ RADEON_CRTC_VBLANK_STAT |
51983+ RADEON_CRTC2_VBLANK_STAT));
51984+ if (!stat)
51985+ return IRQ_NONE;
51986+
51987+ stat &= dev_priv->irq_enable_reg;
51988+
51989+ /* SW interrupt */
51990+ if (stat & RADEON_SW_INT_TEST) {
51991+ DRM_WAKEUP(&dev_priv->swi_queue);
51992+ }
51993+
51994+ /* VBLANK interrupt */
51995+ if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
51996+ int vblank_crtc = dev_priv->vblank_crtc;
51997+
51998+ if ((vblank_crtc &
51999+ (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
52000+ (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
52001+ if (stat & RADEON_CRTC_VBLANK_STAT)
52002+ atomic_inc(&dev->vbl_received);
52003+ if (stat & RADEON_CRTC2_VBLANK_STAT)
52004+ atomic_inc(&dev->vbl_received2);
52005+ } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
52006+ (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
52007+ ((stat & RADEON_CRTC2_VBLANK_STAT) &&
52008+ (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
52009+ atomic_inc(&dev->vbl_received);
52010+
52011+ DRM_WAKEUP(&dev->vbl_queue);
52012+ drm_vbl_send_signals(dev);
52013+ }
52014+
52015+ return IRQ_HANDLED;
52016+}
52017+
52018+static int radeon_emit_irq(struct drm_device * dev)
52019+{
52020+ drm_radeon_private_t *dev_priv = dev->dev_private;
52021+ unsigned int ret;
52022+ RING_LOCALS;
52023+
52024+ atomic_inc(&dev_priv->swi_emitted);
52025+ ret = atomic_read(&dev_priv->swi_emitted);
52026+
52027+ BEGIN_RING(4);
52028+ OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
52029+ OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
52030+ ADVANCE_RING();
52031+ COMMIT_RING();
52032+
52033+ return ret;
52034+}
52035+
52036+static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
52037+{
52038+ drm_radeon_private_t *dev_priv =
52039+ (drm_radeon_private_t *) dev->dev_private;
52040+ int ret = 0;
52041+
52042+ if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
52043+ return 0;
52044+
52045+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
52046+
52047+ DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
52048+ RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
52049+
52050+ return ret;
52051+}
52052+
52053+static int radeon_driver_vblank_do_wait(struct drm_device * dev,
52054+ unsigned int *sequence,
52055+ int crtc)
52056+{
52057+ drm_radeon_private_t *dev_priv =
52058+ (drm_radeon_private_t *) dev->dev_private;
52059+ unsigned int cur_vblank;
52060+ int ret = 0;
52061+ int ack = 0;
52062+ atomic_t *counter;
52063+ if (!dev_priv) {
52064+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52065+ return -EINVAL;
52066+ }
52067+
52068+ if (crtc == DRM_RADEON_VBLANK_CRTC1) {
52069+ counter = &dev->vbl_received;
52070+ ack |= RADEON_CRTC_VBLANK_STAT;
52071+ } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
52072+ counter = &dev->vbl_received2;
52073+ ack |= RADEON_CRTC2_VBLANK_STAT;
52074+ } else
52075+ return -EINVAL;
52076+
52077+ radeon_acknowledge_irqs(dev_priv, ack);
52078+
52079+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
52080+
52081+ /* Assume that the user has missed the current sequence number
52082+ * by about a day rather than she wants to wait for years
52083+ * using vertical blanks...
52084+ */
52085+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
52086+ (((cur_vblank = atomic_read(counter))
52087+ - *sequence) <= (1 << 23)));
52088+
52089+ *sequence = cur_vblank;
52090+
52091+ return ret;
52092+}
52093+
52094+int radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
52095+{
52096+ return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
52097+}
52098+
52099+int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
52100+{
52101+ return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
52102+}
52103+
52104+/* Needs the lock as it touches the ring.
52105+ */
52106+int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
52107+{
52108+ drm_radeon_private_t *dev_priv = dev->dev_private;
52109+ drm_radeon_irq_emit_t *emit = data;
52110+ int result;
52111+
52112+ LOCK_TEST_WITH_RETURN(dev, file_priv);
52113+
52114+ if (!dev_priv) {
52115+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52116+ return -EINVAL;
52117+ }
52118+
52119+ result = radeon_emit_irq(dev);
52120+
52121+ if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
52122+ DRM_ERROR("copy_to_user\n");
52123+ return -EFAULT;
52124+ }
52125+
52126+ return 0;
52127+}
52128+
52129+/* Doesn't need the hardware lock.
52130+ */
52131+int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
52132+{
52133+ drm_radeon_private_t *dev_priv = dev->dev_private;
52134+ drm_radeon_irq_wait_t *irqwait = data;
52135+
52136+ if (!dev_priv) {
52137+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52138+ return -EINVAL;
52139+ }
52140+
52141+ return radeon_wait_irq(dev, irqwait->irq_seq);
52142+}
52143+
52144+static void radeon_enable_interrupt(struct drm_device *dev)
52145+{
52146+ drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
52147+
52148+ dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
52149+ if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
52150+ dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
52151+
52152+ if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
52153+ dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
52154+
52155+ RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
52156+ dev_priv->irq_enabled = 1;
52157+}
52158+
52159+/* drm_dma.h hooks
52160+*/
52161+void radeon_driver_irq_preinstall(struct drm_device * dev)
52162+{
52163+ drm_radeon_private_t *dev_priv =
52164+ (drm_radeon_private_t *) dev->dev_private;
52165+
52166+ /* Disable *all* interrupts */
52167+ RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
52168+
52169+ /* Clear bits if they're already high */
52170+ radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
52171+ RADEON_CRTC_VBLANK_STAT |
52172+ RADEON_CRTC2_VBLANK_STAT));
52173+}
52174+
52175+void radeon_driver_irq_postinstall(struct drm_device * dev)
52176+{
52177+ drm_radeon_private_t *dev_priv =
52178+ (drm_radeon_private_t *) dev->dev_private;
52179+
52180+ atomic_set(&dev_priv->swi_emitted, 0);
52181+ DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
52182+
52183+ radeon_enable_interrupt(dev);
52184+}
52185+
52186+void radeon_driver_irq_uninstall(struct drm_device * dev)
52187+{
52188+ drm_radeon_private_t *dev_priv =
52189+ (drm_radeon_private_t *) dev->dev_private;
52190+ if (!dev_priv)
52191+ return;
52192+
52193+ dev_priv->irq_enabled = 0;
52194+
52195+ /* Disable *all* interrupts */
52196+ RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
52197+}
52198+
52199+
52200+int radeon_vblank_crtc_get(struct drm_device *dev)
52201+{
52202+ drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
52203+ u32 flag;
52204+ u32 value;
52205+
52206+ flag = RADEON_READ(RADEON_GEN_INT_CNTL);
52207+ value = 0;
52208+
52209+ if (flag & RADEON_CRTC_VBLANK_MASK)
52210+ value |= DRM_RADEON_VBLANK_CRTC1;
52211+
52212+ if (flag & RADEON_CRTC2_VBLANK_MASK)
52213+ value |= DRM_RADEON_VBLANK_CRTC2;
52214+ return value;
52215+}
52216+
52217+int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
52218+{
52219+ drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
52220+ if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
52221+ DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
52222+ return -EINVAL;
52223+ }
52224+ dev_priv->vblank_crtc = (unsigned int)value;
52225+ radeon_enable_interrupt(dev);
52226+ return 0;
52227+}
52228Index: git/shared-core/radeon_mem.c
52229===================================================================
52230--- /dev/null 1970-01-01 00:00:00.000000000 +0000
52231+++ git/shared-core/radeon_mem.c 2008-12-12 17:35:22.000000000 +0000
52232@@ -0,0 +1,302 @@
52233+/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */
52234+/*
52235+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
52236+ *
52237+ * The Weather Channel (TM) funded Tungsten Graphics to develop the
52238+ * initial release of the Radeon 8500 driver under the XFree86 license.
52239+ * This notice must be preserved.
52240+ *
52241+ * Permission is hereby granted, free of charge, to any person obtaining a
52242+ * copy of this software and associated documentation files (the "Software"),
52243+ * to deal in the Software without restriction, including without limitation
52244+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
52245+ * and/or sell copies of the Software, and to permit persons to whom the
52246+ * Software is furnished to do so, subject to the following conditions:
52247+ *
52248+ * The above copyright notice and this permission notice (including the next
52249+ * paragraph) shall be included in all copies or substantial portions of the
52250+ * Software.
52251+ *
52252+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52253+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52254+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52255+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
52256+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
52257+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
52258+ * DEALINGS IN THE SOFTWARE.
52259+ *
52260+ * Authors:
52261+ * Keith Whitwell <keith@tungstengraphics.com>
52262+ */
52263+
52264+#include "drmP.h"
52265+#include "drm.h"
52266+#include "radeon_drm.h"
52267+#include "radeon_drv.h"
52268+
52269+/* Very simple allocator for GART memory, working on a static range
52270+ * already mapped into each client's address space.
52271+ */
52272+
52273+static struct mem_block *split_block(struct mem_block *p, int start, int size,
52274+ struct drm_file *file_priv)
52275+{
52276+ /* Maybe cut off the start of an existing block */
52277+ if (start > p->start) {
52278+ struct mem_block *newblock =
52279+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
52280+ if (!newblock)
52281+ goto out;
52282+ newblock->start = start;
52283+ newblock->size = p->size - (start - p->start);
52284+ newblock->file_priv = NULL;
52285+ newblock->next = p->next;
52286+ newblock->prev = p;
52287+ p->next->prev = newblock;
52288+ p->next = newblock;
52289+ p->size -= newblock->size;
52290+ p = newblock;
52291+ }
52292+
52293+ /* Maybe cut off the end of an existing block */
52294+ if (size < p->size) {
52295+ struct mem_block *newblock =
52296+ drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
52297+ if (!newblock)
52298+ goto out;
52299+ newblock->start = start + size;
52300+ newblock->size = p->size - size;
52301+ newblock->file_priv = NULL;
52302+ newblock->next = p->next;
52303+ newblock->prev = p;
52304+ p->next->prev = newblock;
52305+ p->next = newblock;
52306+ p->size = size;
52307+ }
52308+
52309+ out:
52310+ /* Our block is in the middle */
52311+ p->file_priv = file_priv;
52312+ return p;
52313+}
52314+
52315+static struct mem_block *alloc_block(struct mem_block *heap, int size,
52316+ int align2, struct drm_file *file_priv)
52317+{
52318+ struct mem_block *p;
52319+ int mask = (1 << align2) - 1;
52320+
52321+ list_for_each(p, heap) {
52322+ int start = (p->start + mask) & ~mask;
52323+ if (p->file_priv == 0 && start + size <= p->start + p->size)
52324+ return split_block(p, start, size, file_priv);
52325+ }
52326+
52327+ return NULL;
52328+}
52329+
52330+static struct mem_block *find_block(struct mem_block *heap, int start)
52331+{
52332+ struct mem_block *p;
52333+
52334+ list_for_each(p, heap)
52335+ if (p->start == start)
52336+ return p;
52337+
52338+ return NULL;
52339+}
52340+
52341+static void free_block(struct mem_block *p)
52342+{
52343+ p->file_priv = NULL;
52344+
52345+ /* Assumes a single contiguous range. Needs a special file_priv in
52346+ * 'heap' to stop it being subsumed.
52347+ */
52348+ if (p->next->file_priv == 0) {
52349+ struct mem_block *q = p->next;
52350+ p->size += q->size;
52351+ p->next = q->next;
52352+ p->next->prev = p;
52353+ drm_free(q, sizeof(*q), DRM_MEM_BUFS);
52354+ }
52355+
52356+ if (p->prev->file_priv == 0) {
52357+ struct mem_block *q = p->prev;
52358+ q->size += p->size;
52359+ q->next = p->next;
52360+ q->next->prev = q;
52361+ drm_free(p, sizeof(*q), DRM_MEM_BUFS);
52362+ }
52363+}
52364+
52365+/* Initialize. How to check for an uninitialized heap?
52366+ */
52367+static int init_heap(struct mem_block **heap, int start, int size)
52368+{
52369+ struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS);
52370+
52371+ if (!blocks)
52372+ return -ENOMEM;
52373+
52374+ *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS);
52375+ if (!*heap) {
52376+ drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS);
52377+ return -ENOMEM;
52378+ }
52379+
52380+ blocks->start = start;
52381+ blocks->size = size;
52382+ blocks->file_priv = NULL;
52383+ blocks->next = blocks->prev = *heap;
52384+
52385+ memset(*heap, 0, sizeof(**heap));
52386+ (*heap)->file_priv = (struct drm_file *) - 1;
52387+ (*heap)->next = (*heap)->prev = blocks;
52388+ return 0;
52389+}
52390+
52391+/* Free all blocks associated with the releasing file.
52392+ */
52393+void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap)
52394+{
52395+ struct mem_block *p;
52396+
52397+ if (!heap || !heap->next)
52398+ return;
52399+
52400+ list_for_each(p, heap) {
52401+ if (p->file_priv == file_priv)
52402+ p->file_priv = NULL;
52403+ }
52404+
52405+ /* Assumes a single contiguous range. Needs a special file_priv in
52406+ * 'heap' to stop it being subsumed.
52407+ */
52408+ list_for_each(p, heap) {
52409+ while (p->file_priv == 0 && p->next->file_priv == 0) {
52410+ struct mem_block *q = p->next;
52411+ p->size += q->size;
52412+ p->next = q->next;
52413+ p->next->prev = p;
52414+ drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
52415+ }
52416+ }
52417+}
52418+
52419+/* Shutdown.
52420+ */
52421+void radeon_mem_takedown(struct mem_block **heap)
52422+{
52423+ struct mem_block *p;
52424+
52425+ if (!*heap)
52426+ return;
52427+
52428+ for (p = (*heap)->next; p != *heap;) {
52429+ struct mem_block *q = p;
52430+ p = p->next;
52431+ drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
52432+ }
52433+
52434+ drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER);
52435+ *heap = NULL;
52436+}
52437+
52438+/* IOCTL HANDLERS */
52439+
52440+static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region)
52441+{
52442+ switch (region) {
52443+ case RADEON_MEM_REGION_GART:
52444+ return &dev_priv->gart_heap;
52445+ case RADEON_MEM_REGION_FB:
52446+ return &dev_priv->fb_heap;
52447+ default:
52448+ return NULL;
52449+ }
52450+}
52451+
52452+int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
52453+{
52454+ drm_radeon_private_t *dev_priv = dev->dev_private;
52455+ drm_radeon_mem_alloc_t *alloc = data;
52456+ struct mem_block *block, **heap;
52457+
52458+ if (!dev_priv) {
52459+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52460+ return -EINVAL;
52461+ }
52462+
52463+ heap = get_heap(dev_priv, alloc->region);
52464+ if (!heap || !*heap)
52465+ return -EFAULT;
52466+
52467+ /* Make things easier on ourselves: all allocations at least
52468+ * 4k aligned.
52469+ */
52470+ if (alloc->alignment < 12)
52471+ alloc->alignment = 12;
52472+
52473+ block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv);
52474+
52475+ if (!block)
52476+ return -ENOMEM;
52477+
52478+ if (DRM_COPY_TO_USER(alloc->region_offset, &block->start,
52479+ sizeof(int))) {
52480+ DRM_ERROR("copy_to_user\n");
52481+ return -EFAULT;
52482+ }
52483+
52484+ return 0;
52485+}
52486+
52487+int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
52488+{
52489+ drm_radeon_private_t *dev_priv = dev->dev_private;
52490+ drm_radeon_mem_free_t *memfree = data;
52491+ struct mem_block *block, **heap;
52492+
52493+ if (!dev_priv) {
52494+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52495+ return -EINVAL;
52496+ }
52497+
52498+ heap = get_heap(dev_priv, memfree->region);
52499+ if (!heap || !*heap)
52500+ return -EFAULT;
52501+
52502+ block = find_block(*heap, memfree->region_offset);
52503+ if (!block)
52504+ return -EFAULT;
52505+
52506+ if (block->file_priv != file_priv)
52507+ return -EPERM;
52508+
52509+ free_block(block);
52510+ return 0;
52511+}
52512+
52513+int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv)
52514+{
52515+ drm_radeon_private_t *dev_priv = dev->dev_private;
52516+ drm_radeon_mem_init_heap_t *initheap = data;
52517+ struct mem_block **heap;
52518+
52519+ if (!dev_priv) {
52520+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
52521+ return -EINVAL;
52522+ }
52523+
52524+ heap = get_heap(dev_priv, initheap->region);
52525+ if (!heap)
52526+ return -EFAULT;
52527+
52528+ if (*heap) {
52529+ DRM_ERROR("heap already initialized?");
52530+ return -EFAULT;
52531+ }
52532+
52533+ return init_heap(heap, initheap->start, initheap->size);
52534+}
52535Index: git/shared-core/radeon_state.c
52536===================================================================
52537--- /dev/null 1970-01-01 00:00:00.000000000 +0000
52538+++ git/shared-core/radeon_state.c 2008-12-12 17:35:22.000000000 +0000
52539@@ -0,0 +1,3240 @@
52540+/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
52541+/*
52542+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
52543+ * All Rights Reserved.
52544+ *
52545+ * Permission is hereby granted, free of charge, to any person obtaining a
52546+ * copy of this software and associated documentation files (the "Software"),
52547+ * to deal in the Software without restriction, including without limitation
52548+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
52549+ * and/or sell copies of the Software, and to permit persons to whom the
52550+ * Software is furnished to do so, subject to the following conditions:
52551+ *
52552+ * The above copyright notice and this permission notice (including the next
52553+ * paragraph) shall be included in all copies or substantial portions of the
52554+ * Software.
52555+ *
52556+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
52557+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
52558+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
52559+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
52560+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
52561+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
52562+ * DEALINGS IN THE SOFTWARE.
52563+ *
52564+ * Authors:
52565+ * Gareth Hughes <gareth@valinux.com>
52566+ * Kevin E. Martin <martin@valinux.com>
52567+ */
52568+
52569+#include "drmP.h"
52570+#include "drm.h"
52571+#include "drm_sarea.h"
52572+#include "radeon_drm.h"
52573+#include "radeon_drv.h"
52574+
52575+/* ================================================================
52576+ * Helper functions for client state checking and fixup
52577+ */
52578+
52579+static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
52580+ dev_priv,
52581+ struct drm_file *file_priv,
52582+ u32 * offset)
52583+{
52584+ u64 off = *offset;
52585+ u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
52586+ struct drm_radeon_driver_file_fields *radeon_priv;
52587+
52588+ /* Hrm ... the story of the offset ... So this function converts
52589+ * the various ideas of what userland clients might have for an
52590+ * offset in the card address space into an offset into the card
52591+ * address space :) So with a sane client, it should just keep
52592+ * the value intact and just do some boundary checking. However,
52593+ * not all clients are sane. Some older clients pass us 0 based
52594+ * offsets relative to the start of the framebuffer and some may
52595+ * assume the AGP aperture it appended to the framebuffer, so we
52596+ * try to detect those cases and fix them up.
52597+ *
52598+ * Note: It might be a good idea here to make sure the offset lands
52599+ * in some "allowed" area to protect things like the PCIE GART...
52600+ */
52601+
52602+ /* First, the best case, the offset already lands in either the
52603+ * framebuffer or the GART mapped space
52604+ */
52605+ if (radeon_check_offset(dev_priv, off))
52606+ return 0;
52607+
52608+ /* Ok, that didn't happen... now check if we have a zero based
52609+ * offset that fits in the framebuffer + gart space, apply the
52610+ * magic offset we get from SETPARAM or calculated from fb_location
52611+ */
52612+ if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
52613+ radeon_priv = file_priv->driver_priv;
52614+ off += radeon_priv->radeon_fb_delta;
52615+ }
52616+
52617+ /* Finally, assume we aimed at a GART offset if beyond the fb */
52618+ if (off > fb_end)
52619+ off = off - fb_end - 1 + dev_priv->gart_vm_start;
52620+
52621+ /* Now recheck and fail if out of bounds */
52622+ if (radeon_check_offset(dev_priv, off)) {
52623+ DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
52624+ *offset = off;
52625+ return 0;
52626+ }
52627+ return -EINVAL;
52628+}
52629+
52630+static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
52631+ dev_priv,
52632+ struct drm_file *file_priv,
52633+ int id, u32 *data)
52634+{
52635+ switch (id) {
52636+
52637+ case RADEON_EMIT_PP_MISC:
52638+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52639+ &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) {
52640+ DRM_ERROR("Invalid depth buffer offset\n");
52641+ return -EINVAL;
52642+ }
52643+ break;
52644+
52645+ case RADEON_EMIT_PP_CNTL:
52646+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52647+ &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) {
52648+ DRM_ERROR("Invalid colour buffer offset\n");
52649+ return -EINVAL;
52650+ }
52651+ break;
52652+
52653+ case R200_EMIT_PP_TXOFFSET_0:
52654+ case R200_EMIT_PP_TXOFFSET_1:
52655+ case R200_EMIT_PP_TXOFFSET_2:
52656+ case R200_EMIT_PP_TXOFFSET_3:
52657+ case R200_EMIT_PP_TXOFFSET_4:
52658+ case R200_EMIT_PP_TXOFFSET_5:
52659+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52660+ &data[0])) {
52661+ DRM_ERROR("Invalid R200 texture offset\n");
52662+ return -EINVAL;
52663+ }
52664+ break;
52665+
52666+ case RADEON_EMIT_PP_TXFILTER_0:
52667+ case RADEON_EMIT_PP_TXFILTER_1:
52668+ case RADEON_EMIT_PP_TXFILTER_2:
52669+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52670+ &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) {
52671+ DRM_ERROR("Invalid R100 texture offset\n");
52672+ return -EINVAL;
52673+ }
52674+ break;
52675+
52676+ case R200_EMIT_PP_CUBIC_OFFSETS_0:
52677+ case R200_EMIT_PP_CUBIC_OFFSETS_1:
52678+ case R200_EMIT_PP_CUBIC_OFFSETS_2:
52679+ case R200_EMIT_PP_CUBIC_OFFSETS_3:
52680+ case R200_EMIT_PP_CUBIC_OFFSETS_4:
52681+ case R200_EMIT_PP_CUBIC_OFFSETS_5:{
52682+ int i;
52683+ for (i = 0; i < 5; i++) {
52684+ if (radeon_check_and_fixup_offset(dev_priv,
52685+ file_priv,
52686+ &data[i])) {
52687+ DRM_ERROR
52688+ ("Invalid R200 cubic texture offset\n");
52689+ return -EINVAL;
52690+ }
52691+ }
52692+ break;
52693+ }
52694+
52695+ case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
52696+ case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
52697+ case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
52698+ int i;
52699+ for (i = 0; i < 5; i++) {
52700+ if (radeon_check_and_fixup_offset(dev_priv,
52701+ file_priv,
52702+ &data[i])) {
52703+ DRM_ERROR
52704+ ("Invalid R100 cubic texture offset\n");
52705+ return -EINVAL;
52706+ }
52707+ }
52708+ }
52709+ break;
52710+
52711+ case R200_EMIT_VAP_CTL: {
52712+ RING_LOCALS;
52713+ BEGIN_RING(2);
52714+ OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
52715+ ADVANCE_RING();
52716+ }
52717+ break;
52718+
52719+ case RADEON_EMIT_RB3D_COLORPITCH:
52720+ case RADEON_EMIT_RE_LINE_PATTERN:
52721+ case RADEON_EMIT_SE_LINE_WIDTH:
52722+ case RADEON_EMIT_PP_LUM_MATRIX:
52723+ case RADEON_EMIT_PP_ROT_MATRIX_0:
52724+ case RADEON_EMIT_RB3D_STENCILREFMASK:
52725+ case RADEON_EMIT_SE_VPORT_XSCALE:
52726+ case RADEON_EMIT_SE_CNTL:
52727+ case RADEON_EMIT_SE_CNTL_STATUS:
52728+ case RADEON_EMIT_RE_MISC:
52729+ case RADEON_EMIT_PP_BORDER_COLOR_0:
52730+ case RADEON_EMIT_PP_BORDER_COLOR_1:
52731+ case RADEON_EMIT_PP_BORDER_COLOR_2:
52732+ case RADEON_EMIT_SE_ZBIAS_FACTOR:
52733+ case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
52734+ case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
52735+ case R200_EMIT_PP_TXCBLEND_0:
52736+ case R200_EMIT_PP_TXCBLEND_1:
52737+ case R200_EMIT_PP_TXCBLEND_2:
52738+ case R200_EMIT_PP_TXCBLEND_3:
52739+ case R200_EMIT_PP_TXCBLEND_4:
52740+ case R200_EMIT_PP_TXCBLEND_5:
52741+ case R200_EMIT_PP_TXCBLEND_6:
52742+ case R200_EMIT_PP_TXCBLEND_7:
52743+ case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
52744+ case R200_EMIT_TFACTOR_0:
52745+ case R200_EMIT_VTX_FMT_0:
52746+ case R200_EMIT_MATRIX_SELECT_0:
52747+ case R200_EMIT_TEX_PROC_CTL_2:
52748+ case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
52749+ case R200_EMIT_PP_TXFILTER_0:
52750+ case R200_EMIT_PP_TXFILTER_1:
52751+ case R200_EMIT_PP_TXFILTER_2:
52752+ case R200_EMIT_PP_TXFILTER_3:
52753+ case R200_EMIT_PP_TXFILTER_4:
52754+ case R200_EMIT_PP_TXFILTER_5:
52755+ case R200_EMIT_VTE_CNTL:
52756+ case R200_EMIT_OUTPUT_VTX_COMP_SEL:
52757+ case R200_EMIT_PP_TAM_DEBUG3:
52758+ case R200_EMIT_PP_CNTL_X:
52759+ case R200_EMIT_RB3D_DEPTHXY_OFFSET:
52760+ case R200_EMIT_RE_AUX_SCISSOR_CNTL:
52761+ case R200_EMIT_RE_SCISSOR_TL_0:
52762+ case R200_EMIT_RE_SCISSOR_TL_1:
52763+ case R200_EMIT_RE_SCISSOR_TL_2:
52764+ case R200_EMIT_SE_VAP_CNTL_STATUS:
52765+ case R200_EMIT_SE_VTX_STATE_CNTL:
52766+ case R200_EMIT_RE_POINTSIZE:
52767+ case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
52768+ case R200_EMIT_PP_CUBIC_FACES_0:
52769+ case R200_EMIT_PP_CUBIC_FACES_1:
52770+ case R200_EMIT_PP_CUBIC_FACES_2:
52771+ case R200_EMIT_PP_CUBIC_FACES_3:
52772+ case R200_EMIT_PP_CUBIC_FACES_4:
52773+ case R200_EMIT_PP_CUBIC_FACES_5:
52774+ case RADEON_EMIT_PP_TEX_SIZE_0:
52775+ case RADEON_EMIT_PP_TEX_SIZE_1:
52776+ case RADEON_EMIT_PP_TEX_SIZE_2:
52777+ case R200_EMIT_RB3D_BLENDCOLOR:
52778+ case R200_EMIT_TCL_POINT_SPRITE_CNTL:
52779+ case RADEON_EMIT_PP_CUBIC_FACES_0:
52780+ case RADEON_EMIT_PP_CUBIC_FACES_1:
52781+ case RADEON_EMIT_PP_CUBIC_FACES_2:
52782+ case R200_EMIT_PP_TRI_PERF_CNTL:
52783+ case R200_EMIT_PP_AFS_0:
52784+ case R200_EMIT_PP_AFS_1:
52785+ case R200_EMIT_ATF_TFACTOR:
52786+ case R200_EMIT_PP_TXCTLALL_0:
52787+ case R200_EMIT_PP_TXCTLALL_1:
52788+ case R200_EMIT_PP_TXCTLALL_2:
52789+ case R200_EMIT_PP_TXCTLALL_3:
52790+ case R200_EMIT_PP_TXCTLALL_4:
52791+ case R200_EMIT_PP_TXCTLALL_5:
52792+ case R200_EMIT_VAP_PVS_CNTL:
52793+ /* These packets don't contain memory offsets */
52794+ break;
52795+
52796+ default:
52797+ DRM_ERROR("Unknown state packet ID %d\n", id);
52798+ return -EINVAL;
52799+ }
52800+
52801+ return 0;
52802+}
52803+
52804+static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
52805+ dev_priv,
52806+ struct drm_file *file_priv,
52807+ drm_radeon_kcmd_buffer_t *
52808+ cmdbuf,
52809+ unsigned int *cmdsz)
52810+{
52811+ u32 *cmd = (u32 *) cmdbuf->buf;
52812+ u32 offset, narrays;
52813+ int count, i, k;
52814+
52815+ *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
52816+
52817+ if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
52818+ DRM_ERROR("Not a type 3 packet\n");
52819+ return -EINVAL;
52820+ }
52821+
52822+ if (4 * *cmdsz > cmdbuf->bufsz) {
52823+ DRM_ERROR("Packet size larger than size of data provided\n");
52824+ return -EINVAL;
52825+ }
52826+
52827+ switch(cmd[0] & 0xff00) {
52828+ /* XXX Are there old drivers needing other packets? */
52829+
52830+ case RADEON_3D_DRAW_IMMD:
52831+ case RADEON_3D_DRAW_VBUF:
52832+ case RADEON_3D_DRAW_INDX:
52833+ case RADEON_WAIT_FOR_IDLE:
52834+ case RADEON_CP_NOP:
52835+ case RADEON_3D_CLEAR_ZMASK:
52836+/* case RADEON_CP_NEXT_CHAR:
52837+ case RADEON_CP_PLY_NEXTSCAN:
52838+ case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
52839+ /* these packets are safe */
52840+ break;
52841+
52842+ case RADEON_CP_3D_DRAW_IMMD_2:
52843+ case RADEON_CP_3D_DRAW_VBUF_2:
52844+ case RADEON_CP_3D_DRAW_INDX_2:
52845+ case RADEON_3D_CLEAR_HIZ:
52846+ /* safe but r200 only */
52847+ if (dev_priv->microcode_version != UCODE_R200) {
52848+ DRM_ERROR("Invalid 3d packet for r100-class chip\n");
52849+ return -EINVAL;
52850+ }
52851+ break;
52852+
52853+ case RADEON_3D_LOAD_VBPNTR:
52854+ count = (cmd[0] >> 16) & 0x3fff;
52855+
52856+ if (count > 18) { /* 12 arrays max */
52857+ DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
52858+ count);
52859+ return -EINVAL;
52860+ }
52861+
52862+ /* carefully check packet contents */
52863+ narrays = cmd[1] & ~0xc000;
52864+ k = 0;
52865+ i = 2;
52866+ while ((k < narrays) && (i < (count + 2))) {
52867+ i++; /* skip attribute field */
52868+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52869+ &cmd[i])) {
52870+ DRM_ERROR
52871+ ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
52872+ k, i);
52873+ return -EINVAL;
52874+ }
52875+ k++;
52876+ i++;
52877+ if (k == narrays)
52878+ break;
52879+ /* have one more to process, they come in pairs */
52880+ if (radeon_check_and_fixup_offset(dev_priv,
52881+ file_priv, &cmd[i]))
52882+ {
52883+ DRM_ERROR
52884+ ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
52885+ k, i);
52886+ return -EINVAL;
52887+ }
52888+ k++;
52889+ i++;
52890+ }
52891+ /* do the counts match what we expect ? */
52892+ if ((k != narrays) || (i != (count + 2))) {
52893+ DRM_ERROR
52894+ ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
52895+ k, i, narrays, count + 1);
52896+ return -EINVAL;
52897+ }
52898+ break;
52899+
52900+ case RADEON_3D_RNDR_GEN_INDX_PRIM:
52901+ if (dev_priv->microcode_version != UCODE_R100) {
52902+ DRM_ERROR("Invalid 3d packet for r200-class chip\n");
52903+ return -EINVAL;
52904+ }
52905+ if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) {
52906+ DRM_ERROR("Invalid rndr_gen_indx offset\n");
52907+ return -EINVAL;
52908+ }
52909+ break;
52910+
52911+ case RADEON_CP_INDX_BUFFER:
52912+ if (dev_priv->microcode_version != UCODE_R200) {
52913+ DRM_ERROR("Invalid 3d packet for r100-class chip\n");
52914+ return -EINVAL;
52915+ }
52916+ if ((cmd[1] & 0x8000ffff) != 0x80000810) {
52917+ DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
52918+ return -EINVAL;
52919+ }
52920+ if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) {
52921+ DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
52922+ return -EINVAL;
52923+ }
52924+ break;
52925+
52926+ case RADEON_CNTL_HOSTDATA_BLT:
52927+ case RADEON_CNTL_PAINT_MULTI:
52928+ case RADEON_CNTL_BITBLT_MULTI:
52929+ /* MSB of opcode: next DWORD GUI_CNTL */
52930+ if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
52931+ | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
52932+ offset = cmd[2] << 10;
52933+ if (radeon_check_and_fixup_offset
52934+ (dev_priv, file_priv, &offset)) {
52935+ DRM_ERROR("Invalid first packet offset\n");
52936+ return -EINVAL;
52937+ }
52938+ cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
52939+ }
52940+
52941+ if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
52942+ (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
52943+ offset = cmd[3] << 10;
52944+ if (radeon_check_and_fixup_offset
52945+ (dev_priv, file_priv, &offset)) {
52946+ DRM_ERROR("Invalid second packet offset\n");
52947+ return -EINVAL;
52948+ }
52949+ cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
52950+ }
52951+ break;
52952+
52953+ default:
52954+ DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00);
52955+ return -EINVAL;
52956+ }
52957+
52958+ return 0;
52959+}
52960+
52961+/* ================================================================
52962+ * CP hardware state programming functions
52963+ */
52964+
52965+static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
52966+ struct drm_clip_rect * box)
52967+{
52968+ RING_LOCALS;
52969+
52970+ DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
52971+ box->x1, box->y1, box->x2, box->y2);
52972+
52973+ BEGIN_RING(4);
52974+ OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
52975+ OUT_RING((box->y1 << 16) | box->x1);
52976+ OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
52977+ OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
52978+ ADVANCE_RING();
52979+}
52980+
52981+/* Emit 1.1 state
52982+ */
52983+static int radeon_emit_state(drm_radeon_private_t * dev_priv,
52984+ struct drm_file *file_priv,
52985+ drm_radeon_context_regs_t * ctx,
52986+ drm_radeon_texture_regs_t * tex,
52987+ unsigned int dirty)
52988+{
52989+ RING_LOCALS;
52990+ DRM_DEBUG("dirty=0x%08x\n", dirty);
52991+
52992+ if (dirty & RADEON_UPLOAD_CONTEXT) {
52993+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
52994+ &ctx->rb3d_depthoffset)) {
52995+ DRM_ERROR("Invalid depth buffer offset\n");
52996+ return -EINVAL;
52997+ }
52998+
52999+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
53000+ &ctx->rb3d_coloroffset)) {
53001+ DRM_ERROR("Invalid depth buffer offset\n");
53002+ return -EINVAL;
53003+ }
53004+
53005+ BEGIN_RING(14);
53006+ OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
53007+ OUT_RING(ctx->pp_misc);
53008+ OUT_RING(ctx->pp_fog_color);
53009+ OUT_RING(ctx->re_solid_color);
53010+ OUT_RING(ctx->rb3d_blendcntl);
53011+ OUT_RING(ctx->rb3d_depthoffset);
53012+ OUT_RING(ctx->rb3d_depthpitch);
53013+ OUT_RING(ctx->rb3d_zstencilcntl);
53014+ OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
53015+ OUT_RING(ctx->pp_cntl);
53016+ OUT_RING(ctx->rb3d_cntl);
53017+ OUT_RING(ctx->rb3d_coloroffset);
53018+ OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
53019+ OUT_RING(ctx->rb3d_colorpitch);
53020+ ADVANCE_RING();
53021+ }
53022+
53023+ if (dirty & RADEON_UPLOAD_VERTFMT) {
53024+ BEGIN_RING(2);
53025+ OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
53026+ OUT_RING(ctx->se_coord_fmt);
53027+ ADVANCE_RING();
53028+ }
53029+
53030+ if (dirty & RADEON_UPLOAD_LINE) {
53031+ BEGIN_RING(5);
53032+ OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
53033+ OUT_RING(ctx->re_line_pattern);
53034+ OUT_RING(ctx->re_line_state);
53035+ OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
53036+ OUT_RING(ctx->se_line_width);
53037+ ADVANCE_RING();
53038+ }
53039+
53040+ if (dirty & RADEON_UPLOAD_BUMPMAP) {
53041+ BEGIN_RING(5);
53042+ OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
53043+ OUT_RING(ctx->pp_lum_matrix);
53044+ OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
53045+ OUT_RING(ctx->pp_rot_matrix_0);
53046+ OUT_RING(ctx->pp_rot_matrix_1);
53047+ ADVANCE_RING();
53048+ }
53049+
53050+ if (dirty & RADEON_UPLOAD_MASKS) {
53051+ BEGIN_RING(4);
53052+ OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
53053+ OUT_RING(ctx->rb3d_stencilrefmask);
53054+ OUT_RING(ctx->rb3d_ropcntl);
53055+ OUT_RING(ctx->rb3d_planemask);
53056+ ADVANCE_RING();
53057+ }
53058+
53059+ if (dirty & RADEON_UPLOAD_VIEWPORT) {
53060+ BEGIN_RING(7);
53061+ OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
53062+ OUT_RING(ctx->se_vport_xscale);
53063+ OUT_RING(ctx->se_vport_xoffset);
53064+ OUT_RING(ctx->se_vport_yscale);
53065+ OUT_RING(ctx->se_vport_yoffset);
53066+ OUT_RING(ctx->se_vport_zscale);
53067+ OUT_RING(ctx->se_vport_zoffset);
53068+ ADVANCE_RING();
53069+ }
53070+
53071+ if (dirty & RADEON_UPLOAD_SETUP) {
53072+ BEGIN_RING(4);
53073+ OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
53074+ OUT_RING(ctx->se_cntl);
53075+ OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
53076+ OUT_RING(ctx->se_cntl_status);
53077+ ADVANCE_RING();
53078+ }
53079+
53080+ if (dirty & RADEON_UPLOAD_MISC) {
53081+ BEGIN_RING(2);
53082+ OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
53083+ OUT_RING(ctx->re_misc);
53084+ ADVANCE_RING();
53085+ }
53086+
53087+ if (dirty & RADEON_UPLOAD_TEX0) {
53088+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
53089+ &tex[0].pp_txoffset)) {
53090+ DRM_ERROR("Invalid texture offset for unit 0\n");
53091+ return -EINVAL;
53092+ }
53093+
53094+ BEGIN_RING(9);
53095+ OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
53096+ OUT_RING(tex[0].pp_txfilter);
53097+ OUT_RING(tex[0].pp_txformat);
53098+ OUT_RING(tex[0].pp_txoffset);
53099+ OUT_RING(tex[0].pp_txcblend);
53100+ OUT_RING(tex[0].pp_txablend);
53101+ OUT_RING(tex[0].pp_tfactor);
53102+ OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
53103+ OUT_RING(tex[0].pp_border_color);
53104+ ADVANCE_RING();
53105+ }
53106+
53107+ if (dirty & RADEON_UPLOAD_TEX1) {
53108+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
53109+ &tex[1].pp_txoffset)) {
53110+ DRM_ERROR("Invalid texture offset for unit 1\n");
53111+ return -EINVAL;
53112+ }
53113+
53114+ BEGIN_RING(9);
53115+ OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
53116+ OUT_RING(tex[1].pp_txfilter);
53117+ OUT_RING(tex[1].pp_txformat);
53118+ OUT_RING(tex[1].pp_txoffset);
53119+ OUT_RING(tex[1].pp_txcblend);
53120+ OUT_RING(tex[1].pp_txablend);
53121+ OUT_RING(tex[1].pp_tfactor);
53122+ OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
53123+ OUT_RING(tex[1].pp_border_color);
53124+ ADVANCE_RING();
53125+ }
53126+
53127+ if (dirty & RADEON_UPLOAD_TEX2) {
53128+ if (radeon_check_and_fixup_offset(dev_priv, file_priv,
53129+ &tex[2].pp_txoffset)) {
53130+ DRM_ERROR("Invalid texture offset for unit 2\n");
53131+ return -EINVAL;
53132+ }
53133+
53134+ BEGIN_RING(9);
53135+ OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
53136+ OUT_RING(tex[2].pp_txfilter);
53137+ OUT_RING(tex[2].pp_txformat);
53138+ OUT_RING(tex[2].pp_txoffset);
53139+ OUT_RING(tex[2].pp_txcblend);
53140+ OUT_RING(tex[2].pp_txablend);
53141+ OUT_RING(tex[2].pp_tfactor);
53142+ OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
53143+ OUT_RING(tex[2].pp_border_color);
53144+ ADVANCE_RING();
53145+ }
53146+
53147+ return 0;
53148+}
53149+
53150+/* Emit 1.2 state
53151+ */
53152+static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
53153+ struct drm_file *file_priv,
53154+ drm_radeon_state_t * state)
53155+{
53156+ RING_LOCALS;
53157+
53158+ if (state->dirty & RADEON_UPLOAD_ZBIAS) {
53159+ BEGIN_RING(3);
53160+ OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
53161+ OUT_RING(state->context2.se_zbias_factor);
53162+ OUT_RING(state->context2.se_zbias_constant);
53163+ ADVANCE_RING();
53164+ }
53165+
53166+ return radeon_emit_state(dev_priv, file_priv, &state->context,
53167+ state->tex, state->dirty);
53168+}
53169+
53170+/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
53171+ * 1.3 cmdbuffers allow all previous state to be updated as well as
53172+ * the tcl scalar and vector areas.
53173+ */
53174+static struct {
53175+ int start;
53176+ int len;
53177+ const char *name;
53178+} packet[RADEON_MAX_STATE_PACKETS] = {
53179+ {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
53180+ {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
53181+ {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
53182+ {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
53183+ {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
53184+ {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
53185+ {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
53186+ {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
53187+ {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
53188+ {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
53189+ {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
53190+ {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
53191+ {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
53192+ {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
53193+ {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
53194+ {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
53195+ {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
53196+ {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
53197+ {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
53198+ {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
53199+ {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
53200+ "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
53201+ {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
53202+ {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
53203+ {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
53204+ {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
53205+ {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
53206+ {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
53207+ {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
53208+ {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
53209+ {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
53210+ {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
53211+ {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
53212+ {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
53213+ {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
53214+ {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
53215+ {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
53216+ {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
53217+ {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
53218+ {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
53219+ {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
53220+ {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
53221+ {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
53222+ {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
53223+ {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
53224+ {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
53225+ {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
53226+ {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
53227+ {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
53228+ {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
53229+ {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
53230+ "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
53231+ {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
53232+ {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
53233+ {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
53234+ {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
53235+ {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
53236+ {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
53237+ {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
53238+ {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
53239+ {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
53240+ {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
53241+ {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
53242+ "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
53243+ {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
53244+ {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
53245+ {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
53246+ {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
53247+ {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
53248+ {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
53249+ {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
53250+ {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
53251+ {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
53252+ {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
53253+ {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
53254+ {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
53255+ {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
53256+ {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
53257+ {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
53258+ {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
53259+ {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
53260+ {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
53261+ {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
53262+ {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
53263+ {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
53264+ {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
53265+ {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
53266+ {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
53267+ {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
53268+ {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
53269+ {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
53270+ {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
53271+ {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
53272+ {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
53273+ {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
53274+ {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
53275+ {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
53276+ {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
53277+};
53278+
53279+/* ================================================================
53280+ * Performance monitoring functions
53281+ */
53282+
53283+static void radeon_clear_box(drm_radeon_private_t * dev_priv,
53284+ int x, int y, int w, int h, int r, int g, int b)
53285+{
53286+ u32 color;
53287+ RING_LOCALS;
53288+
53289+ x += dev_priv->sarea_priv->boxes[0].x1;
53290+ y += dev_priv->sarea_priv->boxes[0].y1;
53291+
53292+ switch (dev_priv->color_fmt) {
53293+ case RADEON_COLOR_FORMAT_RGB565:
53294+ color = (((r & 0xf8) << 8) |
53295+ ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
53296+ break;
53297+ case RADEON_COLOR_FORMAT_ARGB8888:
53298+ default:
53299+ color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
53300+ break;
53301+ }
53302+
53303+ BEGIN_RING(4);
53304+ RADEON_WAIT_UNTIL_3D_IDLE();
53305+ OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
53306+ OUT_RING(0xffffffff);
53307+ ADVANCE_RING();
53308+
53309+ BEGIN_RING(6);
53310+
53311+ OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
53312+ OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
53313+ RADEON_GMC_BRUSH_SOLID_COLOR |
53314+ (dev_priv->color_fmt << 8) |
53315+ RADEON_GMC_SRC_DATATYPE_COLOR |
53316+ RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
53317+
53318+ if (dev_priv->sarea_priv->pfCurrentPage == 1) {
53319+ OUT_RING(dev_priv->front_pitch_offset);
53320+ } else {
53321+ OUT_RING(dev_priv->back_pitch_offset);
53322+ }
53323+
53324+ OUT_RING(color);
53325+
53326+ OUT_RING((x << 16) | y);
53327+ OUT_RING((w << 16) | h);
53328+
53329+ ADVANCE_RING();
53330+}
53331+
53332+static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
53333+{
53334+ /* Collapse various things into a wait flag -- trying to
53335+ * guess if userspase slept -- better just to have them tell us.
53336+ */
53337+ if (dev_priv->stats.last_frame_reads > 1 ||
53338+ dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
53339+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
53340+ }
53341+
53342+ if (dev_priv->stats.freelist_loops) {
53343+ dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
53344+ }
53345+
53346+ /* Purple box for page flipping
53347+ */
53348+ if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
53349+ radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
53350+
53351+ /* Red box if we have to wait for idle at any point
53352+ */
53353+ if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
53354+ radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
53355+
53356+ /* Blue box: lost context?
53357+ */
53358+
53359+ /* Yellow box for texture swaps
53360+ */
53361+ if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
53362+ radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
53363+
53364+ /* Green box if hardware never idles (as far as we can tell)
53365+ */
53366+ if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
53367+ radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
53368+
53369+ /* Draw bars indicating number of buffers allocated
53370+ * (not a great measure, easily confused)
53371+ */
53372+ if (dev_priv->stats.requested_bufs) {
53373+ if (dev_priv->stats.requested_bufs > 100)
53374+ dev_priv->stats.requested_bufs = 100;
53375+
53376+ radeon_clear_box(dev_priv, 4, 16,
53377+ dev_priv->stats.requested_bufs, 4,
53378+ 196, 128, 128);
53379+ }
53380+
53381+ memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
53382+
53383+}
53384+
53385+/* ================================================================
53386+ * CP command dispatch functions
53387+ */
53388+
53389+static void radeon_cp_dispatch_clear(struct drm_device * dev,
53390+ drm_radeon_clear_t * clear,
53391+ drm_radeon_clear_rect_t * depth_boxes)
53392+{
53393+ drm_radeon_private_t *dev_priv = dev->dev_private;
53394+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
53395+ drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
53396+ int nbox = sarea_priv->nbox;
53397+ struct drm_clip_rect *pbox = sarea_priv->boxes;
53398+ unsigned int flags = clear->flags;
53399+ u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
53400+ int i;
53401+ RING_LOCALS;
53402+ DRM_DEBUG("flags = 0x%x\n", flags);
53403+
53404+ dev_priv->stats.clears++;
53405+
53406+ if (dev_priv->sarea_priv->pfCurrentPage == 1) {
53407+ unsigned int tmp = flags;
53408+
53409+ flags &= ~(RADEON_FRONT | RADEON_BACK);
53410+ if (tmp & RADEON_FRONT)
53411+ flags |= RADEON_BACK;
53412+ if (tmp & RADEON_BACK)
53413+ flags |= RADEON_FRONT;
53414+ }
53415+
53416+ if (flags & (RADEON_FRONT | RADEON_BACK)) {
53417+
53418+ BEGIN_RING(4);
53419+
53420+ /* Ensure the 3D stream is idle before doing a
53421+ * 2D fill to clear the front or back buffer.
53422+ */
53423+ RADEON_WAIT_UNTIL_3D_IDLE();
53424+
53425+ OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
53426+ OUT_RING(clear->color_mask);
53427+
53428+ ADVANCE_RING();
53429+
53430+ /* Make sure we restore the 3D state next time.
53431+ */
53432+ dev_priv->sarea_priv->ctx_owner = 0;
53433+
53434+ for (i = 0; i < nbox; i++) {
53435+ int x = pbox[i].x1;
53436+ int y = pbox[i].y1;
53437+ int w = pbox[i].x2 - x;
53438+ int h = pbox[i].y2 - y;
53439+
53440+ DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
53441+ x, y, w, h, flags);
53442+
53443+ if (flags & RADEON_FRONT) {
53444+ BEGIN_RING(6);
53445+
53446+ OUT_RING(CP_PACKET3
53447+ (RADEON_CNTL_PAINT_MULTI, 4));
53448+ OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
53449+ RADEON_GMC_BRUSH_SOLID_COLOR |
53450+ (dev_priv->
53451+ color_fmt << 8) |
53452+ RADEON_GMC_SRC_DATATYPE_COLOR |
53453+ RADEON_ROP3_P |
53454+ RADEON_GMC_CLR_CMP_CNTL_DIS);
53455+
53456+ OUT_RING(dev_priv->front_pitch_offset);
53457+ OUT_RING(clear->clear_color);
53458+
53459+ OUT_RING((x << 16) | y);
53460+ OUT_RING((w << 16) | h);
53461+
53462+ ADVANCE_RING();
53463+ }
53464+
53465+ if (flags & RADEON_BACK) {
53466+ BEGIN_RING(6);
53467+
53468+ OUT_RING(CP_PACKET3
53469+ (RADEON_CNTL_PAINT_MULTI, 4));
53470+ OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
53471+ RADEON_GMC_BRUSH_SOLID_COLOR |
53472+ (dev_priv->
53473+ color_fmt << 8) |
53474+ RADEON_GMC_SRC_DATATYPE_COLOR |
53475+ RADEON_ROP3_P |
53476+ RADEON_GMC_CLR_CMP_CNTL_DIS);
53477+
53478+ OUT_RING(dev_priv->back_pitch_offset);
53479+ OUT_RING(clear->clear_color);
53480+
53481+ OUT_RING((x << 16) | y);
53482+ OUT_RING((w << 16) | h);
53483+
53484+ ADVANCE_RING();
53485+ }
53486+ }
53487+ }
53488+
53489+ /* hyper z clear */
53490+ /* no docs available, based on reverse engeneering by Stephane Marchesin */
53491+ if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
53492+ && (flags & RADEON_CLEAR_FASTZ)) {
53493+
53494+ int i;
53495+ int depthpixperline =
53496+ dev_priv->depth_fmt ==
53497+ RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
53498+ 2) : (dev_priv->
53499+ depth_pitch / 4);
53500+
53501+ u32 clearmask;
53502+
53503+ u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
53504+ ((clear->depth_mask & 0xff) << 24);
53505+
53506+ /* Make sure we restore the 3D state next time.
53507+ * we haven't touched any "normal" state - still need this?
53508+ */
53509+ dev_priv->sarea_priv->ctx_owner = 0;
53510+
53511+ if ((dev_priv->flags & RADEON_HAS_HIERZ)
53512+ && (flags & RADEON_USE_HIERZ)) {
53513+ /* FIXME : reverse engineer that for Rx00 cards */
53514+ /* FIXME : the mask supposedly contains low-res z values. So can't set
53515+ just to the max (0xff? or actually 0x3fff?), need to take z clear
53516+ value into account? */
53517+ /* pattern seems to work for r100, though get slight
53518+ rendering errors with glxgears. If hierz is not enabled for r100,
53519+ only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
53520+ other ones are ignored, and the same clear mask can be used. That's
53521+ very different behaviour than R200 which needs different clear mask
53522+ and different number of tiles to clear if hierz is enabled or not !?!
53523+ */
53524+ clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
53525+ } else {
53526+ /* clear mask : chooses the clearing pattern.
53527+ rv250: could be used to clear only parts of macrotiles
53528+ (but that would get really complicated...)?
53529+ bit 0 and 1 (either or both of them ?!?!) are used to
53530+ not clear tile (or maybe one of the bits indicates if the tile is
53531+ compressed or not), bit 2 and 3 to not clear tile 1,...,.
53532+ Pattern is as follows:
53533+ | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
53534+ bits -------------------------------------------------
53535+ | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
53536+ rv100: clearmask covers 2x8 4x1 tiles, but one clear still
53537+ covers 256 pixels ?!?
53538+ */
53539+ clearmask = 0x0;
53540+ }
53541+
53542+ BEGIN_RING(8);
53543+ RADEON_WAIT_UNTIL_2D_IDLE();
53544+ OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
53545+ tempRB3D_DEPTHCLEARVALUE);
53546+ /* what offset is this exactly ? */
53547+ OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
53548+ /* need ctlstat, otherwise get some strange black flickering */
53549+ OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
53550+ RADEON_RB3D_ZC_FLUSH_ALL);
53551+ ADVANCE_RING();
53552+
53553+ for (i = 0; i < nbox; i++) {
53554+ int tileoffset, nrtilesx, nrtilesy, j;
53555+ /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
53556+ if ((dev_priv->flags & RADEON_HAS_HIERZ)
53557+ && !(dev_priv->microcode_version == UCODE_R200)) {
53558+ /* FIXME : figure this out for r200 (when hierz is enabled). Or
53559+ maybe r200 actually doesn't need to put the low-res z value into
53560+ the tile cache like r100, but just needs to clear the hi-level z-buffer?
53561+ Works for R100, both with hierz and without.
53562+ R100 seems to operate on 2x1 8x8 tiles, but...
53563+ odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
53564+ problematic with resolutions which are not 64 pix aligned? */
53565+ tileoffset =
53566+ ((pbox[i].y1 >> 3) * depthpixperline +
53567+ pbox[i].x1) >> 6;
53568+ nrtilesx =
53569+ ((pbox[i].x2 & ~63) -
53570+ (pbox[i].x1 & ~63)) >> 4;
53571+ nrtilesy =
53572+ (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
53573+ for (j = 0; j <= nrtilesy; j++) {
53574+ BEGIN_RING(4);
53575+ OUT_RING(CP_PACKET3
53576+ (RADEON_3D_CLEAR_ZMASK, 2));
53577+ /* first tile */
53578+ OUT_RING(tileoffset * 8);
53579+ /* the number of tiles to clear */
53580+ OUT_RING(nrtilesx + 4);
53581+ /* clear mask : chooses the clearing pattern. */
53582+ OUT_RING(clearmask);
53583+ ADVANCE_RING();
53584+ tileoffset += depthpixperline >> 6;
53585+ }
53586+ } else if (dev_priv->microcode_version == UCODE_R200) {
53587+ /* works for rv250. */
53588+ /* find first macro tile (8x2 4x4 z-pixels on rv250) */
53589+ tileoffset =
53590+ ((pbox[i].y1 >> 3) * depthpixperline +
53591+ pbox[i].x1) >> 5;
53592+ nrtilesx =
53593+ (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
53594+ nrtilesy =
53595+ (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
53596+ for (j = 0; j <= nrtilesy; j++) {
53597+ BEGIN_RING(4);
53598+ OUT_RING(CP_PACKET3
53599+ (RADEON_3D_CLEAR_ZMASK, 2));
53600+ /* first tile */
53601+ /* judging by the first tile offset needed, could possibly
53602+ directly address/clear 4x4 tiles instead of 8x2 * 4x4
53603+ macro tiles, though would still need clear mask for
53604+ right/bottom if truely 4x4 granularity is desired ? */
53605+ OUT_RING(tileoffset * 16);
53606+ /* the number of tiles to clear */
53607+ OUT_RING(nrtilesx + 1);
53608+ /* clear mask : chooses the clearing pattern. */
53609+ OUT_RING(clearmask);
53610+ ADVANCE_RING();
53611+ tileoffset += depthpixperline >> 5;
53612+ }
53613+ } else { /* rv 100 */
53614+ /* rv100 might not need 64 pix alignment, who knows */
53615+ /* offsets are, hmm, weird */
53616+ tileoffset =
53617+ ((pbox[i].y1 >> 4) * depthpixperline +
53618+ pbox[i].x1) >> 6;
53619+ nrtilesx =
53620+ ((pbox[i].x2 & ~63) -
53621+ (pbox[i].x1 & ~63)) >> 4;
53622+ nrtilesy =
53623+ (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
53624+ for (j = 0; j <= nrtilesy; j++) {
53625+ BEGIN_RING(4);
53626+ OUT_RING(CP_PACKET3
53627+ (RADEON_3D_CLEAR_ZMASK, 2));
53628+ OUT_RING(tileoffset * 128);
53629+ /* the number of tiles to clear */
53630+ OUT_RING(nrtilesx + 4);
53631+ /* clear mask : chooses the clearing pattern. */
53632+ OUT_RING(clearmask);
53633+ ADVANCE_RING();
53634+ tileoffset += depthpixperline >> 6;
53635+ }
53636+ }
53637+ }
53638+
53639+ /* TODO don't always clear all hi-level z tiles */
53640+ if ((dev_priv->flags & RADEON_HAS_HIERZ)
53641+ && (dev_priv->microcode_version == UCODE_R200)
53642+ && (flags & RADEON_USE_HIERZ))
53643+ /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
53644+ /* FIXME : the mask supposedly contains low-res z values. So can't set
53645+ just to the max (0xff? or actually 0x3fff?), need to take z clear
53646+ value into account? */
53647+ {
53648+ BEGIN_RING(4);
53649+ OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
53650+ OUT_RING(0x0); /* First tile */
53651+ OUT_RING(0x3cc0);
53652+ OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
53653+ ADVANCE_RING();
53654+ }
53655+ }
53656+
53657+ /* We have to clear the depth and/or stencil buffers by
53658+ * rendering a quad into just those buffers. Thus, we have to
53659+ * make sure the 3D engine is configured correctly.
53660+ */
53661+ else if ((dev_priv->microcode_version == UCODE_R200) &&
53662+ (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
53663+
53664+ int tempPP_CNTL;
53665+ int tempRE_CNTL;
53666+ int tempRB3D_CNTL;
53667+ int tempRB3D_ZSTENCILCNTL;
53668+ int tempRB3D_STENCILREFMASK;
53669+ int tempRB3D_PLANEMASK;
53670+ int tempSE_CNTL;
53671+ int tempSE_VTE_CNTL;
53672+ int tempSE_VTX_FMT_0;
53673+ int tempSE_VTX_FMT_1;
53674+ int tempSE_VAP_CNTL;
53675+ int tempRE_AUX_SCISSOR_CNTL;
53676+
53677+ tempPP_CNTL = 0;
53678+ tempRE_CNTL = 0;
53679+
53680+ tempRB3D_CNTL = depth_clear->rb3d_cntl;
53681+
53682+ tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
53683+ tempRB3D_STENCILREFMASK = 0x0;
53684+
53685+ tempSE_CNTL = depth_clear->se_cntl;
53686+
53687+ /* Disable TCL */
53688+
53689+ tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
53690+ (0x9 <<
53691+ SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
53692+
53693+ tempRB3D_PLANEMASK = 0x0;
53694+
53695+ tempRE_AUX_SCISSOR_CNTL = 0x0;
53696+
53697+ tempSE_VTE_CNTL =
53698+ SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
53699+
53700+ /* Vertex format (X, Y, Z, W) */
53701+ tempSE_VTX_FMT_0 =
53702+ SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
53703+ SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
53704+ tempSE_VTX_FMT_1 = 0x0;
53705+
53706+ /*
53707+ * Depth buffer specific enables
53708+ */
53709+ if (flags & RADEON_DEPTH) {
53710+ /* Enable depth buffer */
53711+ tempRB3D_CNTL |= RADEON_Z_ENABLE;
53712+ } else {
53713+ /* Disable depth buffer */
53714+ tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
53715+ }
53716+
53717+ /*
53718+ * Stencil buffer specific enables
53719+ */
53720+ if (flags & RADEON_STENCIL) {
53721+ tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
53722+ tempRB3D_STENCILREFMASK = clear->depth_mask;
53723+ } else {
53724+ tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
53725+ tempRB3D_STENCILREFMASK = 0x00000000;
53726+ }
53727+
53728+ if (flags & RADEON_USE_COMP_ZBUF) {
53729+ tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
53730+ RADEON_Z_DECOMPRESSION_ENABLE;
53731+ }
53732+ if (flags & RADEON_USE_HIERZ) {
53733+ tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
53734+ }
53735+
53736+ BEGIN_RING(26);
53737+ RADEON_WAIT_UNTIL_2D_IDLE();
53738+
53739+ OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
53740+ OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
53741+ OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
53742+ OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
53743+ OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
53744+ tempRB3D_STENCILREFMASK);
53745+ OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
53746+ OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
53747+ OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
53748+ OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
53749+ OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
53750+ OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
53751+ OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
53752+ ADVANCE_RING();
53753+
53754+ /* Make sure we restore the 3D state next time.
53755+ */
53756+ dev_priv->sarea_priv->ctx_owner = 0;
53757+
53758+ for (i = 0; i < nbox; i++) {
53759+
53760+ /* Funny that this should be required --
53761+ * sets top-left?
53762+ */
53763+ radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
53764+
53765+ BEGIN_RING(14);
53766+ OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
53767+ OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
53768+ RADEON_PRIM_WALK_RING |
53769+ (3 << RADEON_NUM_VERTICES_SHIFT)));
53770+ OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
53771+ OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
53772+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53773+ OUT_RING(0x3f800000);
53774+ OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
53775+ OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
53776+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53777+ OUT_RING(0x3f800000);
53778+ OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
53779+ OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
53780+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53781+ OUT_RING(0x3f800000);
53782+ ADVANCE_RING();
53783+ }
53784+ } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
53785+
53786+ int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
53787+
53788+ rb3d_cntl = depth_clear->rb3d_cntl;
53789+
53790+ if (flags & RADEON_DEPTH) {
53791+ rb3d_cntl |= RADEON_Z_ENABLE;
53792+ } else {
53793+ rb3d_cntl &= ~RADEON_Z_ENABLE;
53794+ }
53795+
53796+ if (flags & RADEON_STENCIL) {
53797+ rb3d_cntl |= RADEON_STENCIL_ENABLE;
53798+ rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
53799+ } else {
53800+ rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
53801+ rb3d_stencilrefmask = 0x00000000;
53802+ }
53803+
53804+ if (flags & RADEON_USE_COMP_ZBUF) {
53805+ tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
53806+ RADEON_Z_DECOMPRESSION_ENABLE;
53807+ }
53808+ if (flags & RADEON_USE_HIERZ) {
53809+ tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
53810+ }
53811+
53812+ BEGIN_RING(13);
53813+ RADEON_WAIT_UNTIL_2D_IDLE();
53814+
53815+ OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
53816+ OUT_RING(0x00000000);
53817+ OUT_RING(rb3d_cntl);
53818+
53819+ OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
53820+ OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
53821+ OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
53822+ OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
53823+ ADVANCE_RING();
53824+
53825+ /* Make sure we restore the 3D state next time.
53826+ */
53827+ dev_priv->sarea_priv->ctx_owner = 0;
53828+
53829+ for (i = 0; i < nbox; i++) {
53830+
53831+ /* Funny that this should be required --
53832+ * sets top-left?
53833+ */
53834+ radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
53835+
53836+ BEGIN_RING(15);
53837+
53838+ OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
53839+ OUT_RING(RADEON_VTX_Z_PRESENT |
53840+ RADEON_VTX_PKCOLOR_PRESENT);
53841+ OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
53842+ RADEON_PRIM_WALK_RING |
53843+ RADEON_MAOS_ENABLE |
53844+ RADEON_VTX_FMT_RADEON_MODE |
53845+ (3 << RADEON_NUM_VERTICES_SHIFT)));
53846+
53847+ OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
53848+ OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
53849+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53850+ OUT_RING(0x0);
53851+
53852+ OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
53853+ OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
53854+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53855+ OUT_RING(0x0);
53856+
53857+ OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
53858+ OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
53859+ OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
53860+ OUT_RING(0x0);
53861+
53862+ ADVANCE_RING();
53863+ }
53864+ }
53865+
53866+ /* Increment the clear counter. The client-side 3D driver must
53867+ * wait on this value before performing the clear ioctl. We
53868+ * need this because the card's so damned fast...
53869+ */
53870+ dev_priv->sarea_priv->last_clear++;
53871+
53872+ BEGIN_RING(4);
53873+
53874+ RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
53875+ RADEON_WAIT_UNTIL_IDLE();
53876+
53877+ ADVANCE_RING();
53878+}
53879+
53880+static void radeon_cp_dispatch_swap(struct drm_device * dev)
53881+{
53882+ drm_radeon_private_t *dev_priv = dev->dev_private;
53883+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
53884+ int nbox = sarea_priv->nbox;
53885+ struct drm_clip_rect *pbox = sarea_priv->boxes;
53886+ int i;
53887+ RING_LOCALS;
53888+ DRM_DEBUG("\n");
53889+
53890+ /* Do some trivial performance monitoring...
53891+ */
53892+ if (dev_priv->do_boxes)
53893+ radeon_cp_performance_boxes(dev_priv);
53894+
53895+ /* Wait for the 3D stream to idle before dispatching the bitblt.
53896+ * This will prevent data corruption between the two streams.
53897+ */
53898+ BEGIN_RING(2);
53899+
53900+ RADEON_WAIT_UNTIL_3D_IDLE();
53901+
53902+ ADVANCE_RING();
53903+
53904+ for (i = 0; i < nbox; i++) {
53905+ int x = pbox[i].x1;
53906+ int y = pbox[i].y1;
53907+ int w = pbox[i].x2 - x;
53908+ int h = pbox[i].y2 - y;
53909+
53910+ DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
53911+
53912+ BEGIN_RING(9);
53913+
53914+ OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
53915+ OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
53916+ RADEON_GMC_DST_PITCH_OFFSET_CNTL |
53917+ RADEON_GMC_BRUSH_NONE |
53918+ (dev_priv->color_fmt << 8) |
53919+ RADEON_GMC_SRC_DATATYPE_COLOR |
53920+ RADEON_ROP3_S |
53921+ RADEON_DP_SRC_SOURCE_MEMORY |
53922+ RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
53923+
53924+ /* Make this work even if front & back are flipped:
53925+ */
53926+ OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
53927+ if (dev_priv->sarea_priv->pfCurrentPage == 0) {
53928+ OUT_RING(dev_priv->back_pitch_offset);
53929+ OUT_RING(dev_priv->front_pitch_offset);
53930+ } else {
53931+ OUT_RING(dev_priv->front_pitch_offset);
53932+ OUT_RING(dev_priv->back_pitch_offset);
53933+ }
53934+
53935+ OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
53936+ OUT_RING((x << 16) | y);
53937+ OUT_RING((x << 16) | y);
53938+ OUT_RING((w << 16) | h);
53939+
53940+ ADVANCE_RING();
53941+ }
53942+
53943+ /* Increment the frame counter. The client-side 3D driver must
53944+ * throttle the framerate by waiting for this value before
53945+ * performing the swapbuffer ioctl.
53946+ */
53947+ dev_priv->sarea_priv->last_frame++;
53948+
53949+ BEGIN_RING(4);
53950+
53951+ RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
53952+ RADEON_WAIT_UNTIL_2D_IDLE();
53953+
53954+ ADVANCE_RING();
53955+}
53956+
53957+static void radeon_cp_dispatch_flip(struct drm_device * dev)
53958+{
53959+ drm_radeon_private_t *dev_priv = dev->dev_private;
53960+ struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
53961+ int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
53962+ ? dev_priv->front_offset : dev_priv->back_offset;
53963+ RING_LOCALS;
53964+ DRM_DEBUG("%s: pfCurrentPage=%d\n",
53965+ __FUNCTION__,
53966+ dev_priv->sarea_priv->pfCurrentPage);
53967+
53968+ /* Do some trivial performance monitoring...
53969+ */
53970+ if (dev_priv->do_boxes) {
53971+ dev_priv->stats.boxes |= RADEON_BOX_FLIP;
53972+ radeon_cp_performance_boxes(dev_priv);
53973+ }
53974+
53975+ /* Update the frame offsets for both CRTCs
53976+ */
53977+ BEGIN_RING(6);
53978+
53979+ RADEON_WAIT_UNTIL_3D_IDLE();
53980+ OUT_RING_REG(RADEON_CRTC_OFFSET,
53981+ ((sarea->frame.y * dev_priv->front_pitch +
53982+ sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
53983+ + offset);
53984+ OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
53985+ + offset);
53986+
53987+ ADVANCE_RING();
53988+
53989+ /* Increment the frame counter. The client-side 3D driver must
53990+ * throttle the framerate by waiting for this value before
53991+ * performing the swapbuffer ioctl.
53992+ */
53993+ dev_priv->sarea_priv->last_frame++;
53994+ dev_priv->sarea_priv->pfCurrentPage =
53995+ 1 - dev_priv->sarea_priv->pfCurrentPage;
53996+
53997+ BEGIN_RING(2);
53998+
53999+ RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
54000+
54001+ ADVANCE_RING();
54002+}
54003+
54004+static int bad_prim_vertex_nr(int primitive, int nr)
54005+{
54006+ switch (primitive & RADEON_PRIM_TYPE_MASK) {
54007+ case RADEON_PRIM_TYPE_NONE:
54008+ case RADEON_PRIM_TYPE_POINT:
54009+ return nr < 1;
54010+ case RADEON_PRIM_TYPE_LINE:
54011+ return (nr & 1) || nr == 0;
54012+ case RADEON_PRIM_TYPE_LINE_STRIP:
54013+ return nr < 2;
54014+ case RADEON_PRIM_TYPE_TRI_LIST:
54015+ case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
54016+ case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
54017+ case RADEON_PRIM_TYPE_RECT_LIST:
54018+ return nr % 3 || nr == 0;
54019+ case RADEON_PRIM_TYPE_TRI_FAN:
54020+ case RADEON_PRIM_TYPE_TRI_STRIP:
54021+ return nr < 3;
54022+ default:
54023+ return 1;
54024+ }
54025+}
54026+
54027+typedef struct {
54028+ unsigned int start;
54029+ unsigned int finish;
54030+ unsigned int prim;
54031+ unsigned int numverts;
54032+ unsigned int offset;
54033+ unsigned int vc_format;
54034+} drm_radeon_tcl_prim_t;
54035+
54036+static void radeon_cp_dispatch_vertex(struct drm_device * dev,
54037+ struct drm_buf * buf,
54038+ drm_radeon_tcl_prim_t * prim)
54039+{
54040+ drm_radeon_private_t *dev_priv = dev->dev_private;
54041+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
54042+ int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
54043+ int numverts = (int)prim->numverts;
54044+ int nbox = sarea_priv->nbox;
54045+ int i = 0;
54046+ RING_LOCALS;
54047+
54048+ DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
54049+ prim->prim,
54050+ prim->vc_format, prim->start, prim->finish, prim->numverts);
54051+
54052+ if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
54053+ DRM_ERROR("bad prim %x numverts %d\n",
54054+ prim->prim, prim->numverts);
54055+ return;
54056+ }
54057+
54058+ do {
54059+ /* Emit the next cliprect */
54060+ if (i < nbox) {
54061+ radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
54062+ }
54063+
54064+ /* Emit the vertex buffer rendering commands */
54065+ BEGIN_RING(5);
54066+
54067+ OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
54068+ OUT_RING(offset);
54069+ OUT_RING(numverts);
54070+ OUT_RING(prim->vc_format);
54071+ OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
54072+ RADEON_COLOR_ORDER_RGBA |
54073+ RADEON_VTX_FMT_RADEON_MODE |
54074+ (numverts << RADEON_NUM_VERTICES_SHIFT));
54075+
54076+ ADVANCE_RING();
54077+
54078+ i++;
54079+ } while (i < nbox);
54080+}
54081+
54082+static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
54083+{
54084+ drm_radeon_private_t *dev_priv = dev->dev_private;
54085+ drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
54086+ RING_LOCALS;
54087+
54088+ buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
54089+
54090+ /* Emit the vertex buffer age */
54091+ BEGIN_RING(2);
54092+ RADEON_DISPATCH_AGE(buf_priv->age);
54093+ ADVANCE_RING();
54094+
54095+ buf->pending = 1;
54096+ buf->used = 0;
54097+}
54098+
54099+static void radeon_cp_dispatch_indirect(struct drm_device * dev,
54100+ struct drm_buf * buf, int start, int end)
54101+{
54102+ drm_radeon_private_t *dev_priv = dev->dev_private;
54103+ RING_LOCALS;
54104+ DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
54105+
54106+ if (start != end) {
54107+ int offset = (dev_priv->gart_buffers_offset
54108+ + buf->offset + start);
54109+ int dwords = (end - start + 3) / sizeof(u32);
54110+
54111+ /* Indirect buffer data must be an even number of
54112+ * dwords, so if we've been given an odd number we must
54113+ * pad the data with a Type-2 CP packet.
54114+ */
54115+ if (dwords & 1) {
54116+ u32 *data = (u32 *)
54117+ ((char *)dev->agp_buffer_map->handle
54118+ + buf->offset + start);
54119+ data[dwords++] = RADEON_CP_PACKET2;
54120+ }
54121+
54122+ /* Fire off the indirect buffer */
54123+ BEGIN_RING(3);
54124+
54125+ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
54126+ OUT_RING(offset);
54127+ OUT_RING(dwords);
54128+
54129+ ADVANCE_RING();
54130+ }
54131+}
54132+
54133+static void radeon_cp_dispatch_indices(struct drm_device * dev,
54134+ struct drm_buf * elt_buf,
54135+ drm_radeon_tcl_prim_t * prim)
54136+{
54137+ drm_radeon_private_t *dev_priv = dev->dev_private;
54138+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
54139+ int offset = dev_priv->gart_buffers_offset + prim->offset;
54140+ u32 *data;
54141+ int dwords;
54142+ int i = 0;
54143+ int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
54144+ int count = (prim->finish - start) / sizeof(u16);
54145+ int nbox = sarea_priv->nbox;
54146+
54147+ DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
54148+ prim->prim,
54149+ prim->vc_format,
54150+ prim->start, prim->finish, prim->offset, prim->numverts);
54151+
54152+ if (bad_prim_vertex_nr(prim->prim, count)) {
54153+ DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
54154+ return;
54155+ }
54156+
54157+ if (start >= prim->finish || (prim->start & 0x7)) {
54158+ DRM_ERROR("buffer prim %d\n", prim->prim);
54159+ return;
54160+ }
54161+
54162+ dwords = (prim->finish - prim->start + 3) / sizeof(u32);
54163+
54164+ data = (u32 *) ((char *)dev->agp_buffer_map->handle +
54165+ elt_buf->offset + prim->start);
54166+
54167+ data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
54168+ data[1] = offset;
54169+ data[2] = prim->numverts;
54170+ data[3] = prim->vc_format;
54171+ data[4] = (prim->prim |
54172+ RADEON_PRIM_WALK_IND |
54173+ RADEON_COLOR_ORDER_RGBA |
54174+ RADEON_VTX_FMT_RADEON_MODE |
54175+ (count << RADEON_NUM_VERTICES_SHIFT));
54176+
54177+ do {
54178+ if (i < nbox)
54179+ radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
54180+
54181+ radeon_cp_dispatch_indirect(dev, elt_buf,
54182+ prim->start, prim->finish);
54183+
54184+ i++;
54185+ } while (i < nbox);
54186+
54187+}
54188+
54189+#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
54190+
54191+static int radeon_cp_dispatch_texture(struct drm_device * dev,
54192+ struct drm_file *file_priv,
54193+ drm_radeon_texture_t * tex,
54194+ drm_radeon_tex_image_t * image)
54195+{
54196+ drm_radeon_private_t *dev_priv = dev->dev_private;
54197+ struct drm_buf *buf;
54198+ u32 format;
54199+ u32 *buffer;
54200+ const u8 __user *data;
54201+ int size, dwords, tex_width, blit_width, spitch;
54202+ u32 height;
54203+ int i;
54204+ u32 texpitch, microtile;
54205+ u32 offset;
54206+ RING_LOCALS;
54207+
54208+ if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
54209+ DRM_ERROR("Invalid destination offset\n");
54210+ return -EINVAL;
54211+ }
54212+
54213+ dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
54214+
54215+ /* Flush the pixel cache. This ensures no pixel data gets mixed
54216+ * up with the texture data from the host data blit, otherwise
54217+ * part of the texture image may be corrupted.
54218+ */
54219+ BEGIN_RING(4);
54220+ RADEON_FLUSH_CACHE();
54221+ RADEON_WAIT_UNTIL_IDLE();
54222+ ADVANCE_RING();
54223+
54224+ /* The compiler won't optimize away a division by a variable,
54225+ * even if the only legal values are powers of two. Thus, we'll
54226+ * use a shift instead.
54227+ */
54228+ switch (tex->format) {
54229+ case RADEON_TXFORMAT_ARGB8888:
54230+ case RADEON_TXFORMAT_RGBA8888:
54231+ format = RADEON_COLOR_FORMAT_ARGB8888;
54232+ tex_width = tex->width * 4;
54233+ blit_width = image->width * 4;
54234+ break;
54235+ case RADEON_TXFORMAT_AI88:
54236+ case RADEON_TXFORMAT_ARGB1555:
54237+ case RADEON_TXFORMAT_RGB565:
54238+ case RADEON_TXFORMAT_ARGB4444:
54239+ case RADEON_TXFORMAT_VYUY422:
54240+ case RADEON_TXFORMAT_YVYU422:
54241+ format = RADEON_COLOR_FORMAT_RGB565;
54242+ tex_width = tex->width * 2;
54243+ blit_width = image->width * 2;
54244+ break;
54245+ case RADEON_TXFORMAT_I8:
54246+ case RADEON_TXFORMAT_RGB332:
54247+ format = RADEON_COLOR_FORMAT_CI8;
54248+ tex_width = tex->width * 1;
54249+ blit_width = image->width * 1;
54250+ break;
54251+ default:
54252+ DRM_ERROR("invalid texture format %d\n", tex->format);
54253+ return -EINVAL;
54254+ }
54255+ spitch = blit_width >> 6;
54256+ if (spitch == 0 && image->height > 1)
54257+ return -EINVAL;
54258+
54259+ texpitch = tex->pitch;
54260+ if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
54261+ microtile = 1;
54262+ if (tex_width < 64) {
54263+ texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
54264+ /* we got tiled coordinates, untile them */
54265+ image->x *= 2;
54266+ }
54267+ } else
54268+ microtile = 0;
54269+
54270+ DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
54271+
54272+ do {
54273+ DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
54274+ tex->offset >> 10, tex->pitch, tex->format,
54275+ image->x, image->y, image->width, image->height);
54276+
54277+ /* Make a copy of some parameters in case we have to
54278+ * update them for a multi-pass texture blit.
54279+ */
54280+ height = image->height;
54281+ data = (const u8 __user *)image->data;
54282+
54283+ size = height * blit_width;
54284+
54285+ if (size > RADEON_MAX_TEXTURE_SIZE) {
54286+ height = RADEON_MAX_TEXTURE_SIZE / blit_width;
54287+ size = height * blit_width;
54288+ } else if (size < 4 && size > 0) {
54289+ size = 4;
54290+ } else if (size == 0) {
54291+ return 0;
54292+ }
54293+
54294+ buf = radeon_freelist_get(dev);
54295+ if (0 && !buf) {
54296+ radeon_do_cp_idle(dev_priv);
54297+ buf = radeon_freelist_get(dev);
54298+ }
54299+ if (!buf) {
54300+ DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
54301+ if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
54302+ return -EFAULT;
54303+ return -EAGAIN;
54304+ }
54305+
54306+ /* Dispatch the indirect buffer.
54307+ */
54308+ buffer =
54309+ (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
54310+ dwords = size / 4;
54311+
54312+#define RADEON_COPY_MT(_buf, _data, _width) \
54313+ do { \
54314+ if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\
54315+ DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
54316+ return -EFAULT; \
54317+ } \
54318+ } while(0)
54319+
54320+ if (microtile) {
54321+ /* texture micro tiling in use, minimum texture width is thus 16 bytes.
54322+ however, we cannot use blitter directly for texture width < 64 bytes,
54323+ since minimum tex pitch is 64 bytes and we need this to match
54324+ the texture width, otherwise the blitter will tile it wrong.
54325+ Thus, tiling manually in this case. Additionally, need to special
54326+ case tex height = 1, since our actual image will have height 2
54327+ and we need to ensure we don't read beyond the texture size
54328+ from user space. */
54329+ if (tex->height == 1) {
54330+ if (tex_width >= 64 || tex_width <= 16) {
54331+ RADEON_COPY_MT(buffer, data,
54332+ (int)(tex_width * sizeof(u32)));
54333+ } else if (tex_width == 32) {
54334+ RADEON_COPY_MT(buffer, data, 16);
54335+ RADEON_COPY_MT(buffer + 8,
54336+ data + 16, 16);
54337+ }
54338+ } else if (tex_width >= 64 || tex_width == 16) {
54339+ RADEON_COPY_MT(buffer, data,
54340+ (int)(dwords * sizeof(u32)));
54341+ } else if (tex_width < 16) {
54342+ for (i = 0; i < tex->height; i++) {
54343+ RADEON_COPY_MT(buffer, data, tex_width);
54344+ buffer += 4;
54345+ data += tex_width;
54346+ }
54347+ } else if (tex_width == 32) {
54348+ /* TODO: make sure this works when not fitting in one buffer
54349+ (i.e. 32bytes x 2048...) */
54350+ for (i = 0; i < tex->height; i += 2) {
54351+ RADEON_COPY_MT(buffer, data, 16);
54352+ data += 16;
54353+ RADEON_COPY_MT(buffer + 8, data, 16);
54354+ data += 16;
54355+ RADEON_COPY_MT(buffer + 4, data, 16);
54356+ data += 16;
54357+ RADEON_COPY_MT(buffer + 12, data, 16);
54358+ data += 16;
54359+ buffer += 16;
54360+ }
54361+ }
54362+ } else {
54363+ if (tex_width >= 32) {
54364+ /* Texture image width is larger than the minimum, so we
54365+ * can upload it directly.
54366+ */
54367+ RADEON_COPY_MT(buffer, data,
54368+ (int)(dwords * sizeof(u32)));
54369+ } else {
54370+ /* Texture image width is less than the minimum, so we
54371+ * need to pad out each image scanline to the minimum
54372+ * width.
54373+ */
54374+ for (i = 0; i < tex->height; i++) {
54375+ RADEON_COPY_MT(buffer, data, tex_width);
54376+ buffer += 8;
54377+ data += tex_width;
54378+ }
54379+ }
54380+ }
54381+
54382+#undef RADEON_COPY_MT
54383+ buf->file_priv = file_priv;
54384+ buf->used = size;
54385+ offset = dev_priv->gart_buffers_offset + buf->offset;
54386+ BEGIN_RING(9);
54387+ OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
54388+ OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
54389+ RADEON_GMC_DST_PITCH_OFFSET_CNTL |
54390+ RADEON_GMC_BRUSH_NONE |
54391+ (format << 8) |
54392+ RADEON_GMC_SRC_DATATYPE_COLOR |
54393+ RADEON_ROP3_S |
54394+ RADEON_DP_SRC_SOURCE_MEMORY |
54395+ RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
54396+ OUT_RING((spitch << 22) | (offset >> 10));
54397+ OUT_RING((texpitch << 22) | (tex->offset >> 10));
54398+ OUT_RING(0);
54399+ OUT_RING((image->x << 16) | image->y);
54400+ OUT_RING((image->width << 16) | height);
54401+ RADEON_WAIT_UNTIL_2D_IDLE();
54402+ ADVANCE_RING();
54403+
54404+ radeon_cp_discard_buffer(dev, buf);
54405+
54406+ /* Update the input parameters for next time */
54407+ image->y += height;
54408+ image->height -= height;
54409+ image->data = (const u8 __user *)image->data + size;
54410+ } while (image->height > 0);
54411+
54412+ /* Flush the pixel cache after the blit completes. This ensures
54413+ * the texture data is written out to memory before rendering
54414+ * continues.
54415+ */
54416+ BEGIN_RING(4);
54417+ RADEON_FLUSH_CACHE();
54418+ RADEON_WAIT_UNTIL_2D_IDLE();
54419+ ADVANCE_RING();
54420+ return 0;
54421+}
54422+
54423+static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
54424+{
54425+ drm_radeon_private_t *dev_priv = dev->dev_private;
54426+ int i;
54427+ RING_LOCALS;
54428+ DRM_DEBUG("\n");
54429+
54430+ BEGIN_RING(35);
54431+
54432+ OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
54433+ OUT_RING(0x00000000);
54434+
54435+ OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
54436+ for (i = 0; i < 32; i++) {
54437+ OUT_RING(stipple[i]);
54438+ }
54439+
54440+ ADVANCE_RING();
54441+}
54442+
54443+static void radeon_apply_surface_regs(int surf_index,
54444+ drm_radeon_private_t *dev_priv)
54445+{
54446+ if (!dev_priv->mmio)
54447+ return;
54448+
54449+ radeon_do_cp_idle(dev_priv);
54450+
54451+ RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
54452+ dev_priv->surfaces[surf_index].flags);
54453+ RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
54454+ dev_priv->surfaces[surf_index].lower);
54455+ RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
54456+ dev_priv->surfaces[surf_index].upper);
54457+}
54458+
54459+/* Allocates a virtual surface
54460+ * doesn't always allocate a real surface, will stretch an existing
54461+ * surface when possible.
54462+ *
54463+ * Note that refcount can be at most 2, since during a free refcount=3
54464+ * might mean we have to allocate a new surface which might not always
54465+ * be available.
54466+ * For example : we allocate three contigous surfaces ABC. If B is
54467+ * freed, we suddenly need two surfaces to store A and C, which might
54468+ * not always be available.
54469+ */
54470+static int alloc_surface(drm_radeon_surface_alloc_t *new,
54471+ drm_radeon_private_t *dev_priv,
54472+ struct drm_file *file_priv)
54473+{
54474+ struct radeon_virt_surface *s;
54475+ int i;
54476+ int virt_surface_index;
54477+ uint32_t new_upper, new_lower;
54478+
54479+ new_lower = new->address;
54480+ new_upper = new_lower + new->size - 1;
54481+
54482+ /* sanity check */
54483+ if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
54484+ ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
54485+ RADEON_SURF_ADDRESS_FIXED_MASK)
54486+ || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
54487+ return -1;
54488+
54489+ /* make sure there is no overlap with existing surfaces */
54490+ for (i = 0; i < RADEON_MAX_SURFACES; i++) {
54491+ if ((dev_priv->surfaces[i].refcount != 0) &&
54492+ (((new_lower >= dev_priv->surfaces[i].lower) &&
54493+ (new_lower < dev_priv->surfaces[i].upper)) ||
54494+ ((new_lower < dev_priv->surfaces[i].lower) &&
54495+ (new_upper > dev_priv->surfaces[i].lower)))) {
54496+ return -1;
54497+ }
54498+ }
54499+
54500+ /* find a virtual surface */
54501+ for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
54502+ if (dev_priv->virt_surfaces[i].file_priv == 0)
54503+ break;
54504+ if (i == 2 * RADEON_MAX_SURFACES) {
54505+ return -1;
54506+ }
54507+ virt_surface_index = i;
54508+
54509+ /* try to reuse an existing surface */
54510+ for (i = 0; i < RADEON_MAX_SURFACES; i++) {
54511+ /* extend before */
54512+ if ((dev_priv->surfaces[i].refcount == 1) &&
54513+ (new->flags == dev_priv->surfaces[i].flags) &&
54514+ (new_upper + 1 == dev_priv->surfaces[i].lower)) {
54515+ s = &(dev_priv->virt_surfaces[virt_surface_index]);
54516+ s->surface_index = i;
54517+ s->lower = new_lower;
54518+ s->upper = new_upper;
54519+ s->flags = new->flags;
54520+ s->file_priv = file_priv;
54521+ dev_priv->surfaces[i].refcount++;
54522+ dev_priv->surfaces[i].lower = s->lower;
54523+ radeon_apply_surface_regs(s->surface_index, dev_priv);
54524+ return virt_surface_index;
54525+ }
54526+
54527+ /* extend after */
54528+ if ((dev_priv->surfaces[i].refcount == 1) &&
54529+ (new->flags == dev_priv->surfaces[i].flags) &&
54530+ (new_lower == dev_priv->surfaces[i].upper + 1)) {
54531+ s = &(dev_priv->virt_surfaces[virt_surface_index]);
54532+ s->surface_index = i;
54533+ s->lower = new_lower;
54534+ s->upper = new_upper;
54535+ s->flags = new->flags;
54536+ s->file_priv = file_priv;
54537+ dev_priv->surfaces[i].refcount++;
54538+ dev_priv->surfaces[i].upper = s->upper;
54539+ radeon_apply_surface_regs(s->surface_index, dev_priv);
54540+ return virt_surface_index;
54541+ }
54542+ }
54543+
54544+ /* okay, we need a new one */
54545+ for (i = 0; i < RADEON_MAX_SURFACES; i++) {
54546+ if (dev_priv->surfaces[i].refcount == 0) {
54547+ s = &(dev_priv->virt_surfaces[virt_surface_index]);
54548+ s->surface_index = i;
54549+ s->lower = new_lower;
54550+ s->upper = new_upper;
54551+ s->flags = new->flags;
54552+ s->file_priv = file_priv;
54553+ dev_priv->surfaces[i].refcount = 1;
54554+ dev_priv->surfaces[i].lower = s->lower;
54555+ dev_priv->surfaces[i].upper = s->upper;
54556+ dev_priv->surfaces[i].flags = s->flags;
54557+ radeon_apply_surface_regs(s->surface_index, dev_priv);
54558+ return virt_surface_index;
54559+ }
54560+ }
54561+
54562+ /* we didn't find anything */
54563+ return -1;
54564+}
54565+
54566+static int free_surface(struct drm_file *file_priv,
54567+ drm_radeon_private_t * dev_priv,
54568+ int lower)
54569+{
54570+ struct radeon_virt_surface *s;
54571+ int i;
54572+ /* find the virtual surface */
54573+ for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
54574+ s = &(dev_priv->virt_surfaces[i]);
54575+ if (s->file_priv) {
54576+ if ((lower == s->lower) && (file_priv == s->file_priv))
54577+ {
54578+ if (dev_priv->surfaces[s->surface_index].
54579+ lower == s->lower)
54580+ dev_priv->surfaces[s->surface_index].
54581+ lower = s->upper;
54582+
54583+ if (dev_priv->surfaces[s->surface_index].
54584+ upper == s->upper)
54585+ dev_priv->surfaces[s->surface_index].
54586+ upper = s->lower;
54587+
54588+ dev_priv->surfaces[s->surface_index].refcount--;
54589+ if (dev_priv->surfaces[s->surface_index].
54590+ refcount == 0)
54591+ dev_priv->surfaces[s->surface_index].
54592+ flags = 0;
54593+ s->file_priv = NULL;
54594+ radeon_apply_surface_regs(s->surface_index,
54595+ dev_priv);
54596+ return 0;
54597+ }
54598+ }
54599+ }
54600+ return 1;
54601+}
54602+
54603+static void radeon_surfaces_release(struct drm_file *file_priv,
54604+ drm_radeon_private_t * dev_priv)
54605+{
54606+ int i;
54607+ for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
54608+ if (dev_priv->virt_surfaces[i].file_priv == file_priv)
54609+ free_surface(file_priv, dev_priv,
54610+ dev_priv->virt_surfaces[i].lower);
54611+ }
54612+}
54613+
54614+/* ================================================================
54615+ * IOCTL functions
54616+ */
54617+static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
54618+{
54619+ drm_radeon_private_t *dev_priv = dev->dev_private;
54620+ drm_radeon_surface_alloc_t *alloc = data;
54621+
54622+ if (!dev_priv) {
54623+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
54624+ return -EINVAL;
54625+ }
54626+
54627+ if (alloc_surface(alloc, dev_priv, file_priv) == -1)
54628+ return -EINVAL;
54629+ else
54630+ return 0;
54631+}
54632+
54633+static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
54634+{
54635+ drm_radeon_private_t *dev_priv = dev->dev_private;
54636+ drm_radeon_surface_free_t *memfree = data;
54637+
54638+ if (!dev_priv) {
54639+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
54640+ return -EINVAL;
54641+ }
54642+
54643+ if (free_surface(file_priv, dev_priv, memfree->address))
54644+ return -EINVAL;
54645+ else
54646+ return 0;
54647+}
54648+
54649+static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
54650+{
54651+ drm_radeon_private_t *dev_priv = dev->dev_private;
54652+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
54653+ drm_radeon_clear_t *clear = data;
54654+ drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
54655+ DRM_DEBUG("\n");
54656+
54657+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54658+
54659+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54660+
54661+ if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
54662+ sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
54663+
54664+ if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes,
54665+ sarea_priv->nbox * sizeof(depth_boxes[0])))
54666+ return -EFAULT;
54667+
54668+ radeon_cp_dispatch_clear(dev, clear, depth_boxes);
54669+
54670+ COMMIT_RING();
54671+ return 0;
54672+}
54673+
54674+/* Not sure why this isn't set all the time:
54675+ */
54676+static int radeon_do_init_pageflip(struct drm_device * dev)
54677+{
54678+ drm_radeon_private_t *dev_priv = dev->dev_private;
54679+ RING_LOCALS;
54680+
54681+ DRM_DEBUG("\n");
54682+
54683+ BEGIN_RING(6);
54684+ RADEON_WAIT_UNTIL_3D_IDLE();
54685+ OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
54686+ OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
54687+ RADEON_CRTC_OFFSET_FLIP_CNTL);
54688+ OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
54689+ OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
54690+ RADEON_CRTC_OFFSET_FLIP_CNTL);
54691+ ADVANCE_RING();
54692+
54693+ dev_priv->page_flipping = 1;
54694+
54695+ if (dev_priv->sarea_priv->pfCurrentPage != 1)
54696+ dev_priv->sarea_priv->pfCurrentPage = 0;
54697+
54698+ return 0;
54699+}
54700+
54701+/* Swapping and flipping are different operations, need different ioctls.
54702+ * They can & should be intermixed to support multiple 3d windows.
54703+ */
54704+static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
54705+{
54706+ drm_radeon_private_t *dev_priv = dev->dev_private;
54707+ DRM_DEBUG("\n");
54708+
54709+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54710+
54711+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54712+
54713+ if (!dev_priv->page_flipping)
54714+ radeon_do_init_pageflip(dev);
54715+
54716+ radeon_cp_dispatch_flip(dev);
54717+
54718+ COMMIT_RING();
54719+ return 0;
54720+}
54721+
54722+static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
54723+{
54724+ drm_radeon_private_t *dev_priv = dev->dev_private;
54725+ drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
54726+ DRM_DEBUG("\n");
54727+
54728+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54729+
54730+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54731+
54732+ if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
54733+ sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
54734+
54735+ radeon_cp_dispatch_swap(dev);
54736+ dev_priv->sarea_priv->ctx_owner = 0;
54737+
54738+ COMMIT_RING();
54739+ return 0;
54740+}
54741+
54742+static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
54743+{
54744+ drm_radeon_private_t *dev_priv = dev->dev_private;
54745+ drm_radeon_sarea_t *sarea_priv;
54746+ struct drm_device_dma *dma = dev->dma;
54747+ struct drm_buf *buf;
54748+ drm_radeon_vertex_t *vertex = data;
54749+ drm_radeon_tcl_prim_t prim;
54750+
54751+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54752+
54753+ if (!dev_priv) {
54754+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
54755+ return -EINVAL;
54756+ }
54757+
54758+ sarea_priv = dev_priv->sarea_priv;
54759+
54760+ DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
54761+ DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
54762+
54763+ if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
54764+ DRM_ERROR("buffer index %d (of %d max)\n",
54765+ vertex->idx, dma->buf_count - 1);
54766+ return -EINVAL;
54767+ }
54768+ if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
54769+ DRM_ERROR("buffer prim %d\n", vertex->prim);
54770+ return -EINVAL;
54771+ }
54772+
54773+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54774+ VB_AGE_TEST_WITH_RETURN(dev_priv);
54775+
54776+ buf = dma->buflist[vertex->idx];
54777+
54778+ if (buf->file_priv != file_priv) {
54779+ DRM_ERROR("process %d using buffer owned by %p\n",
54780+ DRM_CURRENTPID, buf->file_priv);
54781+ return -EINVAL;
54782+ }
54783+ if (buf->pending) {
54784+ DRM_ERROR("sending pending buffer %d\n", vertex->idx);
54785+ return -EINVAL;
54786+ }
54787+
54788+ /* Build up a prim_t record:
54789+ */
54790+ if (vertex->count) {
54791+ buf->used = vertex->count; /* not used? */
54792+
54793+ if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
54794+ if (radeon_emit_state(dev_priv, file_priv,
54795+ &sarea_priv->context_state,
54796+ sarea_priv->tex_state,
54797+ sarea_priv->dirty)) {
54798+ DRM_ERROR("radeon_emit_state failed\n");
54799+ return -EINVAL;
54800+ }
54801+
54802+ sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
54803+ RADEON_UPLOAD_TEX1IMAGES |
54804+ RADEON_UPLOAD_TEX2IMAGES |
54805+ RADEON_REQUIRE_QUIESCENCE);
54806+ }
54807+
54808+ prim.start = 0;
54809+ prim.finish = vertex->count; /* unused */
54810+ prim.prim = vertex->prim;
54811+ prim.numverts = vertex->count;
54812+ prim.vc_format = dev_priv->sarea_priv->vc_format;
54813+
54814+ radeon_cp_dispatch_vertex(dev, buf, &prim);
54815+ }
54816+
54817+ if (vertex->discard) {
54818+ radeon_cp_discard_buffer(dev, buf);
54819+ }
54820+
54821+ COMMIT_RING();
54822+ return 0;
54823+}
54824+
54825+static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
54826+{
54827+ drm_radeon_private_t *dev_priv = dev->dev_private;
54828+ drm_radeon_sarea_t *sarea_priv;
54829+ struct drm_device_dma *dma = dev->dma;
54830+ struct drm_buf *buf;
54831+ drm_radeon_indices_t *elts = data;
54832+ drm_radeon_tcl_prim_t prim;
54833+ int count;
54834+
54835+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54836+
54837+ if (!dev_priv) {
54838+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
54839+ return -EINVAL;
54840+ }
54841+ sarea_priv = dev_priv->sarea_priv;
54842+
54843+ DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
54844+ DRM_CURRENTPID, elts->idx, elts->start, elts->end,
54845+ elts->discard);
54846+
54847+ if (elts->idx < 0 || elts->idx >= dma->buf_count) {
54848+ DRM_ERROR("buffer index %d (of %d max)\n",
54849+ elts->idx, dma->buf_count - 1);
54850+ return -EINVAL;
54851+ }
54852+ if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
54853+ DRM_ERROR("buffer prim %d\n", elts->prim);
54854+ return -EINVAL;
54855+ }
54856+
54857+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54858+ VB_AGE_TEST_WITH_RETURN(dev_priv);
54859+
54860+ buf = dma->buflist[elts->idx];
54861+
54862+ if (buf->file_priv != file_priv) {
54863+ DRM_ERROR("process %d using buffer owned by %p\n",
54864+ DRM_CURRENTPID, buf->file_priv);
54865+ return -EINVAL;
54866+ }
54867+ if (buf->pending) {
54868+ DRM_ERROR("sending pending buffer %d\n", elts->idx);
54869+ return -EINVAL;
54870+ }
54871+
54872+ count = (elts->end - elts->start) / sizeof(u16);
54873+ elts->start -= RADEON_INDEX_PRIM_OFFSET;
54874+
54875+ if (elts->start & 0x7) {
54876+ DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
54877+ return -EINVAL;
54878+ }
54879+ if (elts->start < buf->used) {
54880+ DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
54881+ return -EINVAL;
54882+ }
54883+
54884+ buf->used = elts->end;
54885+
54886+ if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
54887+ if (radeon_emit_state(dev_priv, file_priv,
54888+ &sarea_priv->context_state,
54889+ sarea_priv->tex_state,
54890+ sarea_priv->dirty)) {
54891+ DRM_ERROR("radeon_emit_state failed\n");
54892+ return -EINVAL;
54893+ }
54894+
54895+ sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
54896+ RADEON_UPLOAD_TEX1IMAGES |
54897+ RADEON_UPLOAD_TEX2IMAGES |
54898+ RADEON_REQUIRE_QUIESCENCE);
54899+ }
54900+
54901+ /* Build up a prim_t record:
54902+ */
54903+ prim.start = elts->start;
54904+ prim.finish = elts->end;
54905+ prim.prim = elts->prim;
54906+ prim.offset = 0; /* offset from start of dma buffers */
54907+ prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
54908+ prim.vc_format = dev_priv->sarea_priv->vc_format;
54909+
54910+ radeon_cp_dispatch_indices(dev, buf, &prim);
54911+ if (elts->discard) {
54912+ radeon_cp_discard_buffer(dev, buf);
54913+ }
54914+
54915+ COMMIT_RING();
54916+ return 0;
54917+}
54918+
54919+static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
54920+{
54921+ drm_radeon_private_t *dev_priv = dev->dev_private;
54922+ drm_radeon_texture_t *tex = data;
54923+ drm_radeon_tex_image_t image;
54924+ int ret;
54925+
54926+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54927+
54928+ if (tex->image == NULL) {
54929+ DRM_ERROR("null texture image!\n");
54930+ return -EINVAL;
54931+ }
54932+
54933+ if (DRM_COPY_FROM_USER(&image,
54934+ (drm_radeon_tex_image_t __user *) tex->image,
54935+ sizeof(image)))
54936+ return -EFAULT;
54937+
54938+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54939+ VB_AGE_TEST_WITH_RETURN(dev_priv);
54940+
54941+ ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
54942+
54943+ COMMIT_RING();
54944+ return ret;
54945+}
54946+
54947+static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
54948+{
54949+ drm_radeon_private_t *dev_priv = dev->dev_private;
54950+ drm_radeon_stipple_t *stipple = data;
54951+ u32 mask[32];
54952+
54953+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54954+
54955+ if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32)))
54956+ return -EFAULT;
54957+
54958+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
54959+
54960+ radeon_cp_dispatch_stipple(dev, mask);
54961+
54962+ COMMIT_RING();
54963+ return 0;
54964+}
54965+
54966+static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
54967+{
54968+ drm_radeon_private_t *dev_priv = dev->dev_private;
54969+ struct drm_device_dma *dma = dev->dma;
54970+ struct drm_buf *buf;
54971+ drm_radeon_indirect_t *indirect = data;
54972+ RING_LOCALS;
54973+
54974+ LOCK_TEST_WITH_RETURN(dev, file_priv);
54975+
54976+ if (!dev_priv) {
54977+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
54978+ return -EINVAL;
54979+ }
54980+
54981+ DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
54982+ indirect->idx, indirect->start, indirect->end,
54983+ indirect->discard);
54984+
54985+ if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
54986+ DRM_ERROR("buffer index %d (of %d max)\n",
54987+ indirect->idx, dma->buf_count - 1);
54988+ return -EINVAL;
54989+ }
54990+
54991+ buf = dma->buflist[indirect->idx];
54992+
54993+ if (buf->file_priv != file_priv) {
54994+ DRM_ERROR("process %d using buffer owned by %p\n",
54995+ DRM_CURRENTPID, buf->file_priv);
54996+ return -EINVAL;
54997+ }
54998+ if (buf->pending) {
54999+ DRM_ERROR("sending pending buffer %d\n", indirect->idx);
55000+ return -EINVAL;
55001+ }
55002+
55003+ if (indirect->start < buf->used) {
55004+ DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
55005+ indirect->start, buf->used);
55006+ return -EINVAL;
55007+ }
55008+
55009+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
55010+ VB_AGE_TEST_WITH_RETURN(dev_priv);
55011+
55012+ buf->used = indirect->end;
55013+
55014+ /* Wait for the 3D stream to idle before the indirect buffer
55015+ * containing 2D acceleration commands is processed.
55016+ */
55017+ BEGIN_RING(2);
55018+
55019+ RADEON_WAIT_UNTIL_3D_IDLE();
55020+
55021+ ADVANCE_RING();
55022+
55023+ /* Dispatch the indirect buffer full of commands from the
55024+ * X server. This is insecure and is thus only available to
55025+ * privileged clients.
55026+ */
55027+ radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
55028+ if (indirect->discard) {
55029+ radeon_cp_discard_buffer(dev, buf);
55030+ }
55031+
55032+ COMMIT_RING();
55033+ return 0;
55034+}
55035+
55036+static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
55037+{
55038+ drm_radeon_private_t *dev_priv = dev->dev_private;
55039+ drm_radeon_sarea_t *sarea_priv;
55040+ struct drm_device_dma *dma = dev->dma;
55041+ struct drm_buf *buf;
55042+ drm_radeon_vertex2_t *vertex = data;
55043+ int i;
55044+ unsigned char laststate;
55045+
55046+ LOCK_TEST_WITH_RETURN(dev, file_priv);
55047+
55048+ if (!dev_priv) {
55049+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
55050+ return -EINVAL;
55051+ }
55052+
55053+ sarea_priv = dev_priv->sarea_priv;
55054+
55055+ DRM_DEBUG("pid=%d index=%d discard=%d\n",
55056+ DRM_CURRENTPID, vertex->idx, vertex->discard);
55057+
55058+ if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
55059+ DRM_ERROR("buffer index %d (of %d max)\n",
55060+ vertex->idx, dma->buf_count - 1);
55061+ return -EINVAL;
55062+ }
55063+
55064+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
55065+ VB_AGE_TEST_WITH_RETURN(dev_priv);
55066+
55067+ buf = dma->buflist[vertex->idx];
55068+
55069+ if (buf->file_priv != file_priv) {
55070+ DRM_ERROR("process %d using buffer owned by %p\n",
55071+ DRM_CURRENTPID, buf->file_priv);
55072+ return -EINVAL;
55073+ }
55074+
55075+ if (buf->pending) {
55076+ DRM_ERROR("sending pending buffer %d\n", vertex->idx);
55077+ return -EINVAL;
55078+ }
55079+
55080+ if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
55081+ return -EINVAL;
55082+
55083+ for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
55084+ drm_radeon_prim_t prim;
55085+ drm_radeon_tcl_prim_t tclprim;
55086+
55087+ if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim)))
55088+ return -EFAULT;
55089+
55090+ if (prim.stateidx != laststate) {
55091+ drm_radeon_state_t state;
55092+
55093+ if (DRM_COPY_FROM_USER(&state,
55094+ &vertex->state[prim.stateidx],
55095+ sizeof(state)))
55096+ return -EFAULT;
55097+
55098+ if (radeon_emit_state2(dev_priv, file_priv, &state)) {
55099+ DRM_ERROR("radeon_emit_state2 failed\n");
55100+ return -EINVAL;
55101+ }
55102+
55103+ laststate = prim.stateidx;
55104+ }
55105+
55106+ tclprim.start = prim.start;
55107+ tclprim.finish = prim.finish;
55108+ tclprim.prim = prim.prim;
55109+ tclprim.vc_format = prim.vc_format;
55110+
55111+ if (prim.prim & RADEON_PRIM_WALK_IND) {
55112+ tclprim.offset = prim.numverts * 64;
55113+ tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
55114+
55115+ radeon_cp_dispatch_indices(dev, buf, &tclprim);
55116+ } else {
55117+ tclprim.numverts = prim.numverts;
55118+ tclprim.offset = 0; /* not used */
55119+
55120+ radeon_cp_dispatch_vertex(dev, buf, &tclprim);
55121+ }
55122+
55123+ if (sarea_priv->nbox == 1)
55124+ sarea_priv->nbox = 0;
55125+ }
55126+
55127+ if (vertex->discard) {
55128+ radeon_cp_discard_buffer(dev, buf);
55129+ }
55130+
55131+ COMMIT_RING();
55132+ return 0;
55133+}
55134+
55135+static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
55136+ struct drm_file *file_priv,
55137+ drm_radeon_cmd_header_t header,
55138+ drm_radeon_kcmd_buffer_t *cmdbuf)
55139+{
55140+ int id = (int)header.packet.packet_id;
55141+ int sz, reg;
55142+ int *data = (int *)cmdbuf->buf;
55143+ RING_LOCALS;
55144+
55145+ if (id >= RADEON_MAX_STATE_PACKETS)
55146+ return -EINVAL;
55147+
55148+ sz = packet[id].len;
55149+ reg = packet[id].start;
55150+
55151+ if (sz * sizeof(int) > cmdbuf->bufsz) {
55152+ DRM_ERROR("Packet size provided larger than data provided\n");
55153+ return -EINVAL;
55154+ }
55155+
55156+ if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) {
55157+ DRM_ERROR("Packet verification failed\n");
55158+ return -EINVAL;
55159+ }
55160+
55161+ BEGIN_RING(sz + 1);
55162+ OUT_RING(CP_PACKET0(reg, (sz - 1)));
55163+ OUT_RING_TABLE(data, sz);
55164+ ADVANCE_RING();
55165+
55166+ cmdbuf->buf += sz * sizeof(int);
55167+ cmdbuf->bufsz -= sz * sizeof(int);
55168+ return 0;
55169+}
55170+
55171+static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
55172+ drm_radeon_cmd_header_t header,
55173+ drm_radeon_kcmd_buffer_t *cmdbuf)
55174+{
55175+ int sz = header.scalars.count;
55176+ int start = header.scalars.offset;
55177+ int stride = header.scalars.stride;
55178+ RING_LOCALS;
55179+
55180+ BEGIN_RING(3 + sz);
55181+ OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
55182+ OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
55183+ OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
55184+ OUT_RING_TABLE(cmdbuf->buf, sz);
55185+ ADVANCE_RING();
55186+ cmdbuf->buf += sz * sizeof(int);
55187+ cmdbuf->bufsz -= sz * sizeof(int);
55188+ return 0;
55189+}
55190+
55191+/* God this is ugly
55192+ */
55193+static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
55194+ drm_radeon_cmd_header_t header,
55195+ drm_radeon_kcmd_buffer_t *cmdbuf)
55196+{
55197+ int sz = header.scalars.count;
55198+ int start = ((unsigned int)header.scalars.offset) + 0x100;
55199+ int stride = header.scalars.stride;
55200+ RING_LOCALS;
55201+
55202+ BEGIN_RING(3 + sz);
55203+ OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
55204+ OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
55205+ OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
55206+ OUT_RING_TABLE(cmdbuf->buf, sz);
55207+ ADVANCE_RING();
55208+ cmdbuf->buf += sz * sizeof(int);
55209+ cmdbuf->bufsz -= sz * sizeof(int);
55210+ return 0;
55211+}
55212+
55213+static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
55214+ drm_radeon_cmd_header_t header,
55215+ drm_radeon_kcmd_buffer_t *cmdbuf)
55216+{
55217+ int sz = header.vectors.count;
55218+ int start = header.vectors.offset;
55219+ int stride = header.vectors.stride;
55220+ RING_LOCALS;
55221+
55222+ BEGIN_RING(5 + sz);
55223+ OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
55224+ OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
55225+ OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
55226+ OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
55227+ OUT_RING_TABLE(cmdbuf->buf, sz);
55228+ ADVANCE_RING();
55229+
55230+ cmdbuf->buf += sz * sizeof(int);
55231+ cmdbuf->bufsz -= sz * sizeof(int);
55232+ return 0;
55233+}
55234+
55235+static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
55236+ drm_radeon_cmd_header_t header,
55237+ drm_radeon_kcmd_buffer_t *cmdbuf)
55238+{
55239+ int sz = header.veclinear.count * 4;
55240+ int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
55241+ RING_LOCALS;
55242+
55243+ if (!sz)
55244+ return 0;
55245+ if (sz * 4 > cmdbuf->bufsz)
55246+ return -EINVAL;
55247+
55248+ BEGIN_RING(5 + sz);
55249+ OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
55250+ OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
55251+ OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
55252+ OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
55253+ OUT_RING_TABLE(cmdbuf->buf, sz);
55254+ ADVANCE_RING();
55255+
55256+ cmdbuf->buf += sz * sizeof(int);
55257+ cmdbuf->bufsz -= sz * sizeof(int);
55258+ return 0;
55259+}
55260+
55261+static int radeon_emit_packet3(struct drm_device * dev,
55262+ struct drm_file *file_priv,
55263+ drm_radeon_kcmd_buffer_t *cmdbuf)
55264+{
55265+ drm_radeon_private_t *dev_priv = dev->dev_private;
55266+ unsigned int cmdsz;
55267+ int ret;
55268+ RING_LOCALS;
55269+
55270+ DRM_DEBUG("\n");
55271+
55272+ if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
55273+ cmdbuf, &cmdsz))) {
55274+ DRM_ERROR("Packet verification failed\n");
55275+ return ret;
55276+ }
55277+
55278+ BEGIN_RING(cmdsz);
55279+ OUT_RING_TABLE(cmdbuf->buf, cmdsz);
55280+ ADVANCE_RING();
55281+
55282+ cmdbuf->buf += cmdsz * 4;
55283+ cmdbuf->bufsz -= cmdsz * 4;
55284+ return 0;
55285+}
55286+
55287+static int radeon_emit_packet3_cliprect(struct drm_device *dev,
55288+ struct drm_file *file_priv,
55289+ drm_radeon_kcmd_buffer_t *cmdbuf,
55290+ int orig_nbox)
55291+{
55292+ drm_radeon_private_t *dev_priv = dev->dev_private;
55293+ struct drm_clip_rect box;
55294+ unsigned int cmdsz;
55295+ int ret;
55296+ struct drm_clip_rect __user *boxes = cmdbuf->boxes;
55297+ int i = 0;
55298+ RING_LOCALS;
55299+
55300+ DRM_DEBUG("\n");
55301+
55302+ if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
55303+ cmdbuf, &cmdsz))) {
55304+ DRM_ERROR("Packet verification failed\n");
55305+ return ret;
55306+ }
55307+
55308+ if (!orig_nbox)
55309+ goto out;
55310+
55311+ do {
55312+ if (i < cmdbuf->nbox) {
55313+ if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
55314+ return -EFAULT;
55315+ /* FIXME The second and subsequent times round
55316+ * this loop, send a WAIT_UNTIL_3D_IDLE before
55317+ * calling emit_clip_rect(). This fixes a
55318+ * lockup on fast machines when sending
55319+ * several cliprects with a cmdbuf, as when
55320+ * waving a 2D window over a 3D
55321+ * window. Something in the commands from user
55322+ * space seems to hang the card when they're
55323+ * sent several times in a row. That would be
55324+ * the correct place to fix it but this works
55325+ * around it until I can figure that out - Tim
55326+ * Smith */
55327+ if (i) {
55328+ BEGIN_RING(2);
55329+ RADEON_WAIT_UNTIL_3D_IDLE();
55330+ ADVANCE_RING();
55331+ }
55332+ radeon_emit_clip_rect(dev_priv, &box);
55333+ }
55334+
55335+ BEGIN_RING(cmdsz);
55336+ OUT_RING_TABLE(cmdbuf->buf, cmdsz);
55337+ ADVANCE_RING();
55338+
55339+ } while (++i < cmdbuf->nbox);
55340+ if (cmdbuf->nbox == 1)
55341+ cmdbuf->nbox = 0;
55342+
55343+ out:
55344+ cmdbuf->buf += cmdsz * 4;
55345+ cmdbuf->bufsz -= cmdsz * 4;
55346+ return 0;
55347+}
55348+
55349+static int radeon_emit_wait(struct drm_device * dev, int flags)
55350+{
55351+ drm_radeon_private_t *dev_priv = dev->dev_private;
55352+ RING_LOCALS;
55353+
55354+ DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
55355+ switch (flags) {
55356+ case RADEON_WAIT_2D:
55357+ BEGIN_RING(2);
55358+ RADEON_WAIT_UNTIL_2D_IDLE();
55359+ ADVANCE_RING();
55360+ break;
55361+ case RADEON_WAIT_3D:
55362+ BEGIN_RING(2);
55363+ RADEON_WAIT_UNTIL_3D_IDLE();
55364+ ADVANCE_RING();
55365+ break;
55366+ case RADEON_WAIT_2D | RADEON_WAIT_3D:
55367+ BEGIN_RING(2);
55368+ RADEON_WAIT_UNTIL_IDLE();
55369+ ADVANCE_RING();
55370+ break;
55371+ default:
55372+ return -EINVAL;
55373+ }
55374+
55375+ return 0;
55376+}
55377+
55378+static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv)
55379+{
55380+ drm_radeon_private_t *dev_priv = dev->dev_private;
55381+ struct drm_device_dma *dma = dev->dma;
55382+ struct drm_buf *buf = NULL;
55383+ int idx;
55384+ drm_radeon_kcmd_buffer_t *cmdbuf = data;
55385+ drm_radeon_cmd_header_t header;
55386+ int orig_nbox, orig_bufsz;
55387+ char *kbuf = NULL;
55388+
55389+ LOCK_TEST_WITH_RETURN(dev, file_priv);
55390+
55391+ if (!dev_priv) {
55392+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
55393+ return -EINVAL;
55394+ }
55395+
55396+ RING_SPACE_TEST_WITH_RETURN(dev_priv);
55397+ VB_AGE_TEST_WITH_RETURN(dev_priv);
55398+
55399+ if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
55400+ return -EINVAL;
55401+ }
55402+
55403+ /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
55404+ * races between checking values and using those values in other code,
55405+ * and simply to avoid a lot of function calls to copy in data.
55406+ */
55407+ orig_bufsz = cmdbuf->bufsz;
55408+ if (orig_bufsz != 0) {
55409+ kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER);
55410+ if (kbuf == NULL)
55411+ return -ENOMEM;
55412+ if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf,
55413+ cmdbuf->bufsz)) {
55414+ drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
55415+ return -EFAULT;
55416+ }
55417+ cmdbuf->buf = kbuf;
55418+ }
55419+
55420+ orig_nbox = cmdbuf->nbox;
55421+
55422+ if (dev_priv->microcode_version == UCODE_R300) {
55423+ int temp;
55424+ temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
55425+
55426+ if (orig_bufsz != 0)
55427+ drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
55428+
55429+ return temp;
55430+ }
55431+
55432+ /* microcode_version != r300 */
55433+ while (cmdbuf->bufsz >= sizeof(header)) {
55434+
55435+ header.i = *(int *)cmdbuf->buf;
55436+ cmdbuf->buf += sizeof(header);
55437+ cmdbuf->bufsz -= sizeof(header);
55438+
55439+ switch (header.header.cmd_type) {
55440+ case RADEON_CMD_PACKET:
55441+ DRM_DEBUG("RADEON_CMD_PACKET\n");
55442+ if (radeon_emit_packets
55443+ (dev_priv, file_priv, header, cmdbuf)) {
55444+ DRM_ERROR("radeon_emit_packets failed\n");
55445+ goto err;
55446+ }
55447+ break;
55448+
55449+ case RADEON_CMD_SCALARS:
55450+ DRM_DEBUG("RADEON_CMD_SCALARS\n");
55451+ if (radeon_emit_scalars(dev_priv, header, cmdbuf)) {
55452+ DRM_ERROR("radeon_emit_scalars failed\n");
55453+ goto err;
55454+ }
55455+ break;
55456+
55457+ case RADEON_CMD_VECTORS:
55458+ DRM_DEBUG("RADEON_CMD_VECTORS\n");
55459+ if (radeon_emit_vectors(dev_priv, header, cmdbuf)) {
55460+ DRM_ERROR("radeon_emit_vectors failed\n");
55461+ goto err;
55462+ }
55463+ break;
55464+
55465+ case RADEON_CMD_DMA_DISCARD:
55466+ DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
55467+ idx = header.dma.buf_idx;
55468+ if (idx < 0 || idx >= dma->buf_count) {
55469+ DRM_ERROR("buffer index %d (of %d max)\n",
55470+ idx, dma->buf_count - 1);
55471+ goto err;
55472+ }
55473+
55474+ buf = dma->buflist[idx];
55475+ if (buf->file_priv != file_priv || buf->pending) {
55476+ DRM_ERROR("bad buffer %p %p %d\n",
55477+ buf->file_priv, file_priv,
55478+ buf->pending);
55479+ goto err;
55480+ }
55481+
55482+ radeon_cp_discard_buffer(dev, buf);
55483+ break;
55484+
55485+ case RADEON_CMD_PACKET3:
55486+ DRM_DEBUG("RADEON_CMD_PACKET3\n");
55487+ if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
55488+ DRM_ERROR("radeon_emit_packet3 failed\n");
55489+ goto err;
55490+ }
55491+ break;
55492+
55493+ case RADEON_CMD_PACKET3_CLIP:
55494+ DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
55495+ if (radeon_emit_packet3_cliprect
55496+ (dev, file_priv, cmdbuf, orig_nbox)) {
55497+ DRM_ERROR("radeon_emit_packet3_clip failed\n");
55498+ goto err;
55499+ }
55500+ break;
55501+
55502+ case RADEON_CMD_SCALARS2:
55503+ DRM_DEBUG("RADEON_CMD_SCALARS2\n");
55504+ if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) {
55505+ DRM_ERROR("radeon_emit_scalars2 failed\n");
55506+ goto err;
55507+ }
55508+ break;
55509+
55510+ case RADEON_CMD_WAIT:
55511+ DRM_DEBUG("RADEON_CMD_WAIT\n");
55512+ if (radeon_emit_wait(dev, header.wait.flags)) {
55513+ DRM_ERROR("radeon_emit_wait failed\n");
55514+ goto err;
55515+ }
55516+ break;
55517+ case RADEON_CMD_VECLINEAR:
55518+ DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
55519+ if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) {
55520+ DRM_ERROR("radeon_emit_veclinear failed\n");
55521+ goto err;
55522+ }
55523+ break;
55524+
55525+ default:
55526+ DRM_ERROR("bad cmd_type %d at %p\n",
55527+ header.header.cmd_type,
55528+ cmdbuf->buf - sizeof(header));
55529+ goto err;
55530+ }
55531+ }
55532+
55533+ if (orig_bufsz != 0)
55534+ drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
55535+
55536+ DRM_DEBUG("DONE\n");
55537+ COMMIT_RING();
55538+ return 0;
55539+
55540+ err:
55541+ if (orig_bufsz != 0)
55542+ drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
55543+ return -EINVAL;
55544+}
55545+
55546+static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
55547+{
55548+ drm_radeon_private_t *dev_priv = dev->dev_private;
55549+ drm_radeon_getparam_t *param = data;
55550+ int value;
55551+
55552+ if (!dev_priv) {
55553+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
55554+ return -EINVAL;
55555+ }
55556+
55557+ DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
55558+
55559+ switch (param->param) {
55560+ case RADEON_PARAM_GART_BUFFER_OFFSET:
55561+ value = dev_priv->gart_buffers_offset;
55562+ break;
55563+ case RADEON_PARAM_LAST_FRAME:
55564+ dev_priv->stats.last_frame_reads++;
55565+ value = GET_SCRATCH(0);
55566+ break;
55567+ case RADEON_PARAM_LAST_DISPATCH:
55568+ value = GET_SCRATCH(1);
55569+ break;
55570+ case RADEON_PARAM_LAST_CLEAR:
55571+ dev_priv->stats.last_clear_reads++;
55572+ value = GET_SCRATCH(2);
55573+ break;
55574+ case RADEON_PARAM_IRQ_NR:
55575+ value = dev->irq;
55576+ break;
55577+ case RADEON_PARAM_GART_BASE:
55578+ value = dev_priv->gart_vm_start;
55579+ break;
55580+ case RADEON_PARAM_REGISTER_HANDLE:
55581+ value = dev_priv->mmio->offset;
55582+ break;
55583+ case RADEON_PARAM_STATUS_HANDLE:
55584+ value = dev_priv->ring_rptr_offset;
55585+ break;
55586+#ifndef __LP64__
55587+ /*
55588+ * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
55589+ * pointer which can't fit into an int-sized variable. According to
55590+ * Michel Dänzer, the ioctl() is only used on embedded platforms, so
55591+ * not supporting it shouldn't be a problem. If the same functionality
55592+ * is needed on 64-bit platforms, a new ioctl() would have to be added,
55593+ * so backwards-compatibility for the embedded platforms can be
55594+ * maintained. --davidm 4-Feb-2004.
55595+ */
55596+ case RADEON_PARAM_SAREA_HANDLE:
55597+ /* The lock is the first dword in the sarea. */
55598+ value = (long)dev->lock.hw_lock;
55599+ break;
55600+#endif
55601+ case RADEON_PARAM_GART_TEX_HANDLE:
55602+ value = dev_priv->gart_textures_offset;
55603+ break;
55604+ case RADEON_PARAM_SCRATCH_OFFSET:
55605+ if (!dev_priv->writeback_works)
55606+ return -EINVAL;
55607+ value = RADEON_SCRATCH_REG_OFFSET;
55608+ break;
55609+
55610+ case RADEON_PARAM_CARD_TYPE:
55611+ if (dev_priv->flags & RADEON_IS_PCIE)
55612+ value = RADEON_CARD_PCIE;
55613+ else if (dev_priv->flags & RADEON_IS_AGP)
55614+ value = RADEON_CARD_AGP;
55615+ else
55616+ value = RADEON_CARD_PCI;
55617+ break;
55618+ case RADEON_PARAM_VBLANK_CRTC:
55619+ value = radeon_vblank_crtc_get(dev);
55620+ break;
55621+ default:
55622+ DRM_DEBUG( "Invalid parameter %d\n", param->param );
55623+ return -EINVAL;
55624+ }
55625+
55626+ if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
55627+ DRM_ERROR("copy_to_user\n");
55628+ return -EFAULT;
55629+ }
55630+
55631+ return 0;
55632+}
55633+
55634+static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
55635+{
55636+ drm_radeon_private_t *dev_priv = dev->dev_private;
55637+ drm_radeon_setparam_t *sp = data;
55638+ struct drm_radeon_driver_file_fields *radeon_priv;
55639+
55640+ if (!dev_priv) {
55641+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
55642+ return -EINVAL;
55643+ }
55644+
55645+ switch (sp->param) {
55646+ case RADEON_SETPARAM_FB_LOCATION:
55647+ radeon_priv = file_priv->driver_priv;
55648+ radeon_priv->radeon_fb_delta = dev_priv->fb_location -
55649+ sp->value;
55650+ break;
55651+ case RADEON_SETPARAM_SWITCH_TILING:
55652+ if (sp->value == 0) {
55653+ DRM_DEBUG("color tiling disabled\n");
55654+ dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
55655+ dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
55656+ dev_priv->sarea_priv->tiling_enabled = 0;
55657+ } else if (sp->value == 1) {
55658+ DRM_DEBUG("color tiling enabled\n");
55659+ dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
55660+ dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
55661+ dev_priv->sarea_priv->tiling_enabled = 1;
55662+ }
55663+ break;
55664+ case RADEON_SETPARAM_PCIGART_LOCATION:
55665+ dev_priv->pcigart_offset = sp->value;
55666+ dev_priv->pcigart_offset_set = 1;
55667+ break;
55668+ case RADEON_SETPARAM_NEW_MEMMAP:
55669+ dev_priv->new_memmap = sp->value;
55670+ break;
55671+ case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
55672+ dev_priv->gart_info.table_size = sp->value;
55673+ if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
55674+ dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
55675+ break;
55676+ case RADEON_SETPARAM_VBLANK_CRTC:
55677+ return radeon_vblank_crtc_set(dev, sp->value);
55678+ break;
55679+ default:
55680+ DRM_DEBUG("Invalid parameter %d\n", sp->param);
55681+ return -EINVAL;
55682+ }
55683+
55684+ return 0;
55685+}
55686+
55687+/* When a client dies:
55688+ * - Check for and clean up flipped page state
55689+ * - Free any alloced GART memory.
55690+ * - Free any alloced radeon surfaces.
55691+ *
55692+ * DRM infrastructure takes care of reclaiming dma buffers.
55693+ */
55694+void radeon_driver_preclose(struct drm_device * dev,
55695+ struct drm_file *file_priv)
55696+{
55697+ if (dev->dev_private) {
55698+ drm_radeon_private_t *dev_priv = dev->dev_private;
55699+ dev_priv->page_flipping = 0;
55700+ radeon_mem_release(file_priv, dev_priv->gart_heap);
55701+ radeon_mem_release(file_priv, dev_priv->fb_heap);
55702+ radeon_surfaces_release(file_priv, dev_priv);
55703+ }
55704+}
55705+
55706+void radeon_driver_lastclose(struct drm_device * dev)
55707+{
55708+ if (dev->dev_private) {
55709+ drm_radeon_private_t *dev_priv = dev->dev_private;
55710+
55711+ if (dev_priv->sarea_priv &&
55712+ dev_priv->sarea_priv->pfCurrentPage != 0)
55713+ radeon_cp_dispatch_flip(dev);
55714+ }
55715+
55716+ radeon_do_release(dev);
55717+}
55718+
55719+int radeon_driver_open(struct drm_device * dev, struct drm_file *file_priv)
55720+{
55721+ drm_radeon_private_t *dev_priv = dev->dev_private;
55722+ struct drm_radeon_driver_file_fields *radeon_priv;
55723+
55724+ DRM_DEBUG("\n");
55725+ radeon_priv =
55726+ (struct drm_radeon_driver_file_fields *)
55727+ drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
55728+
55729+ if (!radeon_priv)
55730+ return -ENOMEM;
55731+
55732+ file_priv->driver_priv = radeon_priv;
55733+
55734+ if (dev_priv)
55735+ radeon_priv->radeon_fb_delta = dev_priv->fb_location;
55736+ else
55737+ radeon_priv->radeon_fb_delta = 0;
55738+ return 0;
55739+}
55740+
55741+void radeon_driver_postclose(struct drm_device * dev, struct drm_file *file_priv)
55742+{
55743+ struct drm_radeon_driver_file_fields *radeon_priv =
55744+ file_priv->driver_priv;
55745+
55746+ drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
55747+}
55748+
55749+struct drm_ioctl_desc radeon_ioctls[] = {
55750+ DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55751+ DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55752+ DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55753+ DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55754+ DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
55755+ DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
55756+ DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH),
55757+ DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
55758+ DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
55759+ DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
55760+ DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
55761+ DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
55762+ DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
55763+ DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
55764+ DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55765+ DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
55766+ DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
55767+ DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
55768+ DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
55769+ DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
55770+ DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH),
55771+ DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
55772+ DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
55773+ DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
55774+ DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
55775+ DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
55776+ DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH)
55777+};
55778+
55779+int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
55780Index: git/shared-core/savage_bci.c
55781===================================================================
55782--- /dev/null 1970-01-01 00:00:00.000000000 +0000
55783+++ git/shared-core/savage_bci.c 2008-12-12 17:35:22.000000000 +0000
55784@@ -0,0 +1,1095 @@
55785+/* savage_bci.c -- BCI support for Savage
55786+ *
55787+ * Copyright 2004 Felix Kuehling
55788+ * All Rights Reserved.
55789+ *
55790+ * Permission is hereby granted, free of charge, to any person obtaining a
55791+ * copy of this software and associated documentation files (the "Software"),
55792+ * to deal in the Software without restriction, including without limitation
55793+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
55794+ * and/or sell copies of the Software, and to permit persons to whom the
55795+ * Software is furnished to do so, subject to the following conditions:
55796+ *
55797+ * The above copyright notice and this permission notice (including the
55798+ * next paragraph) shall be included in all copies or substantial portions
55799+ * of the Software.
55800+ *
55801+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
55802+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
55803+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
55804+ * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
55805+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
55806+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
55807+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
55808+ */
55809+#include "drmP.h"
55810+#include "savage_drm.h"
55811+#include "savage_drv.h"
55812+
55813+/* Need a long timeout for shadow status updates can take a while
55814+ * and so can waiting for events when the queue is full. */
55815+#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
55816+#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
55817+#define SAVAGE_FREELIST_DEBUG 0
55818+
55819+static int savage_do_cleanup_bci(struct drm_device *dev);
55820+
55821+static int
55822+savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n)
55823+{
55824+ uint32_t mask = dev_priv->status_used_mask;
55825+ uint32_t threshold = dev_priv->bci_threshold_hi;
55826+ uint32_t status;
55827+ int i;
55828+
55829+#if SAVAGE_BCI_DEBUG
55830+ if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
55831+ DRM_ERROR("Trying to emit %d words "
55832+ "(more than guaranteed space in COB)\n", n);
55833+#endif
55834+
55835+ for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
55836+ DRM_MEMORYBARRIER();
55837+ status = dev_priv->status_ptr[0];
55838+ if ((status & mask) < threshold)
55839+ return 0;
55840+ DRM_UDELAY(1);
55841+ }
55842+
55843+#if SAVAGE_BCI_DEBUG
55844+ DRM_ERROR("failed!\n");
55845+ DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
55846+#endif
55847+ return -EBUSY;
55848+}
55849+
55850+static int
55851+savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n)
55852+{
55853+ uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
55854+ uint32_t status;
55855+ int i;
55856+
55857+ for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
55858+ status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
55859+ if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
55860+ return 0;
55861+ DRM_UDELAY(1);
55862+ }
55863+
55864+#if SAVAGE_BCI_DEBUG
55865+ DRM_ERROR("failed!\n");
55866+ DRM_INFO(" status=0x%08x\n", status);
55867+#endif
55868+ return -EBUSY;
55869+}
55870+
55871+static int
55872+savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n)
55873+{
55874+ uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
55875+ uint32_t status;
55876+ int i;
55877+
55878+ for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
55879+ status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
55880+ if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
55881+ return 0;
55882+ DRM_UDELAY(1);
55883+ }
55884+
55885+#if SAVAGE_BCI_DEBUG
55886+ DRM_ERROR("failed!\n");
55887+ DRM_INFO(" status=0x%08x\n", status);
55888+#endif
55889+ return -EBUSY;
55890+}
55891+
55892+/*
55893+ * Waiting for events.
55894+ *
55895+ * The BIOSresets the event tag to 0 on mode changes. Therefore we
55896+ * never emit 0 to the event tag. If we find a 0 event tag we know the
55897+ * BIOS stomped on it and return success assuming that the BIOS waited
55898+ * for engine idle.
55899+ *
55900+ * Note: if the Xserver uses the event tag it has to follow the same
55901+ * rule. Otherwise there may be glitches every 2^16 events.
55902+ */
55903+static int
55904+savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e)
55905+{
55906+ uint32_t status;
55907+ int i;
55908+
55909+ for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
55910+ DRM_MEMORYBARRIER();
55911+ status = dev_priv->status_ptr[1];
55912+ if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
55913+ (status & 0xffff) == 0)
55914+ return 0;
55915+ DRM_UDELAY(1);
55916+ }
55917+
55918+#if SAVAGE_BCI_DEBUG
55919+ DRM_ERROR("failed!\n");
55920+ DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
55921+#endif
55922+
55923+ return -EBUSY;
55924+}
55925+
55926+static int
55927+savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e)
55928+{
55929+ uint32_t status;
55930+ int i;
55931+
55932+ for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
55933+ status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
55934+ if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
55935+ (status & 0xffff) == 0)
55936+ return 0;
55937+ DRM_UDELAY(1);
55938+ }
55939+
55940+#if SAVAGE_BCI_DEBUG
55941+ DRM_ERROR("failed!\n");
55942+ DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
55943+#endif
55944+
55945+ return -EBUSY;
55946+}
55947+
55948+uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
55949+ unsigned int flags)
55950+{
55951+ uint16_t count;
55952+ BCI_LOCALS;
55953+
55954+ if (dev_priv->status_ptr) {
55955+ /* coordinate with Xserver */
55956+ count = dev_priv->status_ptr[1023];
55957+ if (count < dev_priv->event_counter)
55958+ dev_priv->event_wrap++;
55959+ } else {
55960+ count = dev_priv->event_counter;
55961+ }
55962+ count = (count + 1) & 0xffff;
55963+ if (count == 0) {
55964+ count++; /* See the comment above savage_wait_event_*. */
55965+ dev_priv->event_wrap++;
55966+ }
55967+ dev_priv->event_counter = count;
55968+ if (dev_priv->status_ptr)
55969+ dev_priv->status_ptr[1023] = (uint32_t)count;
55970+
55971+ if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
55972+ unsigned int wait_cmd = BCI_CMD_WAIT;
55973+ if ((flags & SAVAGE_WAIT_2D))
55974+ wait_cmd |= BCI_CMD_WAIT_2D;
55975+ if ((flags & SAVAGE_WAIT_3D))
55976+ wait_cmd |= BCI_CMD_WAIT_3D;
55977+ BEGIN_BCI(2);
55978+ BCI_WRITE(wait_cmd);
55979+ } else {
55980+ BEGIN_BCI(1);
55981+ }
55982+ BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count);
55983+
55984+ return count;
55985+}
55986+
55987+/*
55988+ * Freelist management
55989+ */
55990+static int savage_freelist_init(struct drm_device *dev)
55991+{
55992+ drm_savage_private_t *dev_priv = dev->dev_private;
55993+ struct drm_device_dma *dma = dev->dma;
55994+ struct drm_buf *buf;
55995+ drm_savage_buf_priv_t *entry;
55996+ int i;
55997+ DRM_DEBUG("count=%d\n", dma->buf_count);
55998+
55999+ dev_priv->head.next = &dev_priv->tail;
56000+ dev_priv->head.prev = NULL;
56001+ dev_priv->head.buf = NULL;
56002+
56003+ dev_priv->tail.next = NULL;
56004+ dev_priv->tail.prev = &dev_priv->head;
56005+ dev_priv->tail.buf = NULL;
56006+
56007+ for (i = 0; i < dma->buf_count; i++) {
56008+ buf = dma->buflist[i];
56009+ entry = buf->dev_private;
56010+
56011+ SET_AGE(&entry->age, 0, 0);
56012+ entry->buf = buf;
56013+
56014+ entry->next = dev_priv->head.next;
56015+ entry->prev = &dev_priv->head;
56016+ dev_priv->head.next->prev = entry;
56017+ dev_priv->head.next = entry;
56018+ }
56019+
56020+ return 0;
56021+}
56022+
56023+static struct drm_buf *savage_freelist_get(struct drm_device *dev)
56024+{
56025+ drm_savage_private_t *dev_priv = dev->dev_private;
56026+ drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
56027+ uint16_t event;
56028+ unsigned int wrap;
56029+ DRM_DEBUG("\n");
56030+
56031+ UPDATE_EVENT_COUNTER();
56032+ if (dev_priv->status_ptr)
56033+ event = dev_priv->status_ptr[1] & 0xffff;
56034+ else
56035+ event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
56036+ wrap = dev_priv->event_wrap;
56037+ if (event > dev_priv->event_counter)
56038+ wrap--; /* hardware hasn't passed the last wrap yet */
56039+
56040+ DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
56041+ DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
56042+
56043+ if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
56044+ drm_savage_buf_priv_t *next = tail->next;
56045+ drm_savage_buf_priv_t *prev = tail->prev;
56046+ prev->next = next;
56047+ next->prev = prev;
56048+ tail->next = tail->prev = NULL;
56049+ return tail->buf;
56050+ }
56051+
56052+ DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
56053+ return NULL;
56054+}
56055+
56056+void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf)
56057+{
56058+ drm_savage_private_t *dev_priv = dev->dev_private;
56059+ drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
56060+
56061+ DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
56062+
56063+ if (entry->next != NULL || entry->prev != NULL) {
56064+ DRM_ERROR("entry already on freelist.\n");
56065+ return;
56066+ }
56067+
56068+ prev = &dev_priv->head;
56069+ next = prev->next;
56070+ prev->next = entry;
56071+ next->prev = entry;
56072+ entry->prev = prev;
56073+ entry->next = next;
56074+}
56075+
56076+/*
56077+ * Command DMA
56078+ */
56079+static int savage_dma_init(drm_savage_private_t *dev_priv)
56080+{
56081+ unsigned int i;
56082+
56083+ dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
56084+ (SAVAGE_DMA_PAGE_SIZE*4);
56085+ dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
56086+ dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
56087+ if (dev_priv->dma_pages == NULL)
56088+ return -ENOMEM;
56089+
56090+ for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
56091+ SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
56092+ dev_priv->dma_pages[i].used = 0;
56093+ dev_priv->dma_pages[i].flushed = 0;
56094+ }
56095+ SET_AGE(&dev_priv->last_dma_age, 0, 0);
56096+
56097+ dev_priv->first_dma_page = 0;
56098+ dev_priv->current_dma_page = 0;
56099+
56100+ return 0;
56101+}
56102+
56103+void savage_dma_reset(drm_savage_private_t *dev_priv)
56104+{
56105+ uint16_t event;
56106+ unsigned int wrap, i;
56107+ event = savage_bci_emit_event(dev_priv, 0);
56108+ wrap = dev_priv->event_wrap;
56109+ for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
56110+ SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
56111+ dev_priv->dma_pages[i].used = 0;
56112+ dev_priv->dma_pages[i].flushed = 0;
56113+ }
56114+ SET_AGE(&dev_priv->last_dma_age, event, wrap);
56115+ dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
56116+}
56117+
56118+void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page)
56119+{
56120+ uint16_t event;
56121+ unsigned int wrap;
56122+
56123+ /* Faked DMA buffer pages don't age. */
56124+ if (dev_priv->cmd_dma == &dev_priv->fake_dma)
56125+ return;
56126+
56127+ UPDATE_EVENT_COUNTER();
56128+ if (dev_priv->status_ptr)
56129+ event = dev_priv->status_ptr[1] & 0xffff;
56130+ else
56131+ event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
56132+ wrap = dev_priv->event_wrap;
56133+ if (event > dev_priv->event_counter)
56134+ wrap--; /* hardware hasn't passed the last wrap yet */
56135+
56136+ if (dev_priv->dma_pages[page].age.wrap > wrap ||
56137+ (dev_priv->dma_pages[page].age.wrap == wrap &&
56138+ dev_priv->dma_pages[page].age.event > event)) {
56139+ if (dev_priv->wait_evnt(dev_priv,
56140+ dev_priv->dma_pages[page].age.event)
56141+ < 0)
56142+ DRM_ERROR("wait_evnt failed!\n");
56143+ }
56144+}
56145+
56146+uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
56147+{
56148+ unsigned int cur = dev_priv->current_dma_page;
56149+ unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
56150+ dev_priv->dma_pages[cur].used;
56151+ unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) /
56152+ SAVAGE_DMA_PAGE_SIZE;
56153+ uint32_t *dma_ptr;
56154+ unsigned int i;
56155+
56156+ DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
56157+ cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
56158+
56159+ if (cur + nr_pages < dev_priv->nr_dma_pages) {
56160+ dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
56161+ cur*SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
56162+ if (n < rest)
56163+ rest = n;
56164+ dev_priv->dma_pages[cur].used += rest;
56165+ n -= rest;
56166+ cur++;
56167+ } else {
56168+ dev_priv->dma_flush(dev_priv);
56169+ nr_pages =
56170+ (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE;
56171+ for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
56172+ dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
56173+ dev_priv->dma_pages[i].used = 0;
56174+ dev_priv->dma_pages[i].flushed = 0;
56175+ }
56176+ dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle;
56177+ dev_priv->first_dma_page = cur = 0;
56178+ }
56179+ for (i = cur; nr_pages > 0; ++i, --nr_pages) {
56180+#if SAVAGE_DMA_DEBUG
56181+ if (dev_priv->dma_pages[i].used) {
56182+ DRM_ERROR("unflushed page %u: used=%u\n",
56183+ i, dev_priv->dma_pages[i].used);
56184+ }
56185+#endif
56186+ if (n > SAVAGE_DMA_PAGE_SIZE)
56187+ dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
56188+ else
56189+ dev_priv->dma_pages[i].used = n;
56190+ n -= SAVAGE_DMA_PAGE_SIZE;
56191+ }
56192+ dev_priv->current_dma_page = --i;
56193+
56194+ DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
56195+ i, dev_priv->dma_pages[i].used, n);
56196+
56197+ savage_dma_wait(dev_priv, dev_priv->current_dma_page);
56198+
56199+ return dma_ptr;
56200+}
56201+
56202+static void savage_dma_flush(drm_savage_private_t *dev_priv)
56203+{
56204+ unsigned int first = dev_priv->first_dma_page;
56205+ unsigned int cur = dev_priv->current_dma_page;
56206+ uint16_t event;
56207+ unsigned int wrap, pad, align, len, i;
56208+ unsigned long phys_addr;
56209+ BCI_LOCALS;
56210+
56211+ if (first == cur &&
56212+ dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
56213+ return;
56214+
56215+ /* pad length to multiples of 2 entries
56216+ * align start of next DMA block to multiles of 8 entries */
56217+ pad = -dev_priv->dma_pages[cur].used & 1;
56218+ align = -(dev_priv->dma_pages[cur].used + pad) & 7;
56219+
56220+ DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
56221+ "pad=%u, align=%u\n",
56222+ first, cur, dev_priv->dma_pages[first].flushed,
56223+ dev_priv->dma_pages[cur].used, pad, align);
56224+
56225+ /* pad with noops */
56226+ if (pad) {
56227+ uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
56228+ cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
56229+ dev_priv->dma_pages[cur].used += pad;
56230+ while(pad != 0) {
56231+ *dma_ptr++ = BCI_CMD_WAIT;
56232+ pad--;
56233+ }
56234+ }
56235+
56236+ DRM_MEMORYBARRIER();
56237+
56238+ /* do flush ... */
56239+ phys_addr = dev_priv->cmd_dma->offset +
56240+ (first * SAVAGE_DMA_PAGE_SIZE +
56241+ dev_priv->dma_pages[first].flushed) * 4;
56242+ len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
56243+ dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
56244+
56245+ DRM_DEBUG("phys_addr=%lx, len=%u\n",
56246+ phys_addr | dev_priv->dma_type, len);
56247+
56248+ BEGIN_BCI(3);
56249+ BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
56250+ BCI_WRITE(phys_addr | dev_priv->dma_type);
56251+ BCI_DMA(len);
56252+
56253+ /* fix alignment of the start of the next block */
56254+ dev_priv->dma_pages[cur].used += align;
56255+
56256+ /* age DMA pages */
56257+ event = savage_bci_emit_event(dev_priv, 0);
56258+ wrap = dev_priv->event_wrap;
56259+ for (i = first; i < cur; ++i) {
56260+ SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
56261+ dev_priv->dma_pages[i].used = 0;
56262+ dev_priv->dma_pages[i].flushed = 0;
56263+ }
56264+ /* age the current page only when it's full */
56265+ if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
56266+ SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
56267+ dev_priv->dma_pages[cur].used = 0;
56268+ dev_priv->dma_pages[cur].flushed = 0;
56269+ /* advance to next page */
56270+ cur++;
56271+ if (cur == dev_priv->nr_dma_pages)
56272+ cur = 0;
56273+ dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
56274+ } else {
56275+ dev_priv->first_dma_page = cur;
56276+ dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
56277+ }
56278+ SET_AGE(&dev_priv->last_dma_age, event, wrap);
56279+
56280+ DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
56281+ dev_priv->dma_pages[cur].used,
56282+ dev_priv->dma_pages[cur].flushed);
56283+}
56284+
56285+static void savage_fake_dma_flush(drm_savage_private_t *dev_priv)
56286+{
56287+ unsigned int i, j;
56288+ BCI_LOCALS;
56289+
56290+ if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
56291+ dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
56292+ return;
56293+
56294+ DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
56295+ dev_priv->first_dma_page, dev_priv->current_dma_page,
56296+ dev_priv->dma_pages[dev_priv->current_dma_page].used);
56297+
56298+ for (i = dev_priv->first_dma_page;
56299+ i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
56300+ ++i) {
56301+ uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle +
56302+ i * SAVAGE_DMA_PAGE_SIZE;
56303+#if SAVAGE_DMA_DEBUG
56304+ /* Sanity check: all pages except the last one must be full. */
56305+ if (i < dev_priv->current_dma_page &&
56306+ dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
56307+ DRM_ERROR("partial DMA page %u: used=%u",
56308+ i, dev_priv->dma_pages[i].used);
56309+ }
56310+#endif
56311+ BEGIN_BCI(dev_priv->dma_pages[i].used);
56312+ for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
56313+ BCI_WRITE(dma_ptr[j]);
56314+ }
56315+ dev_priv->dma_pages[i].used = 0;
56316+ }
56317+
56318+ /* reset to first page */
56319+ dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
56320+}
56321+
56322+int savage_driver_load(struct drm_device *dev, unsigned long chipset)
56323+{
56324+ drm_savage_private_t *dev_priv;
56325+
56326+ dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
56327+ if (dev_priv == NULL)
56328+ return -ENOMEM;
56329+
56330+ memset(dev_priv, 0, sizeof(drm_savage_private_t));
56331+ dev->dev_private = (void *)dev_priv;
56332+
56333+ dev_priv->chipset = (enum savage_family)chipset;
56334+
56335+ return 0;
56336+}
56337+
56338+/*
56339+ * Initalize mappings. On Savage4 and SavageIX the alignment
56340+ * and size of the aperture is not suitable for automatic MTRR setup
56341+ * in drm_addmap. Therefore we add them manually before the maps are
56342+ * initialized, and tear them down on last close.
56343+ */
56344+int savage_driver_firstopen(struct drm_device *dev)
56345+{
56346+ drm_savage_private_t *dev_priv = dev->dev_private;
56347+ unsigned long mmio_base, fb_base, fb_size, aperture_base;
56348+ /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
56349+ * in case we decide we need information on the BAR for BSD in the
56350+ * future.
56351+ */
56352+ unsigned int fb_rsrc, aper_rsrc;
56353+ int ret = 0;
56354+
56355+ dev_priv->mtrr[0].handle = -1;
56356+ dev_priv->mtrr[1].handle = -1;
56357+ dev_priv->mtrr[2].handle = -1;
56358+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
56359+ fb_rsrc = 0;
56360+ fb_base = drm_get_resource_start(dev, 0);
56361+ fb_size = SAVAGE_FB_SIZE_S3;
56362+ mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
56363+ aper_rsrc = 0;
56364+ aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
56365+ /* this should always be true */
56366+ if (drm_get_resource_len(dev, 0) == 0x08000000) {
56367+ /* Don't make MMIO write-cobining! We need 3
56368+ * MTRRs. */
56369+ dev_priv->mtrr[0].base = fb_base;
56370+ dev_priv->mtrr[0].size = 0x01000000;
56371+ dev_priv->mtrr[0].handle =
56372+ drm_mtrr_add(dev_priv->mtrr[0].base,
56373+ dev_priv->mtrr[0].size, DRM_MTRR_WC);
56374+ dev_priv->mtrr[1].base = fb_base+0x02000000;
56375+ dev_priv->mtrr[1].size = 0x02000000;
56376+ dev_priv->mtrr[1].handle =
56377+ drm_mtrr_add(dev_priv->mtrr[1].base,
56378+ dev_priv->mtrr[1].size, DRM_MTRR_WC);
56379+ dev_priv->mtrr[2].base = fb_base+0x04000000;
56380+ dev_priv->mtrr[2].size = 0x04000000;
56381+ dev_priv->mtrr[2].handle =
56382+ drm_mtrr_add(dev_priv->mtrr[2].base,
56383+ dev_priv->mtrr[2].size, DRM_MTRR_WC);
56384+ } else {
56385+ DRM_ERROR("strange pci_resource_len %08lx\n",
56386+ drm_get_resource_len(dev, 0));
56387+ }
56388+ } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
56389+ dev_priv->chipset != S3_SAVAGE2000) {
56390+ mmio_base = drm_get_resource_start(dev, 0);
56391+ fb_rsrc = 1;
56392+ fb_base = drm_get_resource_start(dev, 1);
56393+ fb_size = SAVAGE_FB_SIZE_S4;
56394+ aper_rsrc = 1;
56395+ aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
56396+ /* this should always be true */
56397+ if (drm_get_resource_len(dev, 1) == 0x08000000) {
56398+ /* Can use one MTRR to cover both fb and
56399+ * aperture. */
56400+ dev_priv->mtrr[0].base = fb_base;
56401+ dev_priv->mtrr[0].size = 0x08000000;
56402+ dev_priv->mtrr[0].handle =
56403+ drm_mtrr_add(dev_priv->mtrr[0].base,
56404+ dev_priv->mtrr[0].size, DRM_MTRR_WC);
56405+ } else {
56406+ DRM_ERROR("strange pci_resource_len %08lx\n",
56407+ drm_get_resource_len(dev, 1));
56408+ }
56409+ } else {
56410+ mmio_base = drm_get_resource_start(dev, 0);
56411+ fb_rsrc = 1;
56412+ fb_base = drm_get_resource_start(dev, 1);
56413+ fb_size = drm_get_resource_len(dev, 1);
56414+ aper_rsrc = 2;
56415+ aperture_base = drm_get_resource_start(dev, 2);
56416+ /* Automatic MTRR setup will do the right thing. */
56417+ }
56418+
56419+ ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
56420+ _DRM_READ_ONLY, &dev_priv->mmio);
56421+ if (ret)
56422+ return ret;
56423+
56424+ ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
56425+ _DRM_WRITE_COMBINING, &dev_priv->fb);
56426+ if (ret)
56427+ return ret;
56428+
56429+ ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
56430+ _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
56431+ &dev_priv->aperture);
56432+ if (ret)
56433+ return ret;
56434+
56435+ return ret;
56436+}
56437+
56438+/*
56439+ * Delete MTRRs and free device-private data.
56440+ */
56441+void savage_driver_lastclose(struct drm_device *dev)
56442+{
56443+ drm_savage_private_t *dev_priv = dev->dev_private;
56444+ int i;
56445+
56446+ for (i = 0; i < 3; ++i)
56447+ if (dev_priv->mtrr[i].handle >= 0)
56448+ drm_mtrr_del(dev_priv->mtrr[i].handle,
56449+ dev_priv->mtrr[i].base,
56450+ dev_priv->mtrr[i].size, DRM_MTRR_WC);
56451+}
56452+
56453+int savage_driver_unload(struct drm_device *dev)
56454+{
56455+ drm_savage_private_t *dev_priv = dev->dev_private;
56456+
56457+ drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
56458+
56459+ return 0;
56460+}
56461+
56462+static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init)
56463+{
56464+ drm_savage_private_t *dev_priv = dev->dev_private;
56465+
56466+ if (init->fb_bpp != 16 && init->fb_bpp != 32) {
56467+ DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
56468+ return -EINVAL;
56469+ }
56470+ if (init->depth_bpp != 16 && init->depth_bpp != 32) {
56471+ DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
56472+ return -EINVAL;
56473+ }
56474+ if (init->dma_type != SAVAGE_DMA_AGP &&
56475+ init->dma_type != SAVAGE_DMA_PCI) {
56476+ DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
56477+ return -EINVAL;
56478+ }
56479+
56480+ dev_priv->cob_size = init->cob_size;
56481+ dev_priv->bci_threshold_lo = init->bci_threshold_lo;
56482+ dev_priv->bci_threshold_hi = init->bci_threshold_hi;
56483+ dev_priv->dma_type = init->dma_type;
56484+
56485+ dev_priv->fb_bpp = init->fb_bpp;
56486+ dev_priv->front_offset = init->front_offset;
56487+ dev_priv->front_pitch = init->front_pitch;
56488+ dev_priv->back_offset = init->back_offset;
56489+ dev_priv->back_pitch = init->back_pitch;
56490+ dev_priv->depth_bpp = init->depth_bpp;
56491+ dev_priv->depth_offset = init->depth_offset;
56492+ dev_priv->depth_pitch = init->depth_pitch;
56493+
56494+ dev_priv->texture_offset = init->texture_offset;
56495+ dev_priv->texture_size = init->texture_size;
56496+
56497+ dev_priv->sarea = drm_getsarea(dev);
56498+ if (!dev_priv->sarea) {
56499+ DRM_ERROR("could not find sarea!\n");
56500+ savage_do_cleanup_bci(dev);
56501+ return -EINVAL;
56502+ }
56503+ if (init->status_offset != 0) {
56504+ dev_priv->status = drm_core_findmap(dev, init->status_offset);
56505+ if (!dev_priv->status) {
56506+ DRM_ERROR("could not find shadow status region!\n");
56507+ savage_do_cleanup_bci(dev);
56508+ return -EINVAL;
56509+ }
56510+ } else {
56511+ dev_priv->status = NULL;
56512+ }
56513+ if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
56514+ dev->agp_buffer_token = init->buffers_offset;
56515+ dev->agp_buffer_map = drm_core_findmap(dev,
56516+ init->buffers_offset);
56517+ if (!dev->agp_buffer_map) {
56518+ DRM_ERROR("could not find DMA buffer region!\n");
56519+ savage_do_cleanup_bci(dev);
56520+ return -EINVAL;
56521+ }
56522+ drm_core_ioremap(dev->agp_buffer_map, dev);
56523+ if (!dev->agp_buffer_map) {
56524+ DRM_ERROR("failed to ioremap DMA buffer region!\n");
56525+ savage_do_cleanup_bci(dev);
56526+ return -ENOMEM;
56527+ }
56528+ }
56529+ if (init->agp_textures_offset) {
56530+ dev_priv->agp_textures =
56531+ drm_core_findmap(dev, init->agp_textures_offset);
56532+ if (!dev_priv->agp_textures) {
56533+ DRM_ERROR("could not find agp texture region!\n");
56534+ savage_do_cleanup_bci(dev);
56535+ return -EINVAL;
56536+ }
56537+ } else {
56538+ dev_priv->agp_textures = NULL;
56539+ }
56540+
56541+ if (init->cmd_dma_offset) {
56542+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
56543+ DRM_ERROR("command DMA not supported on "
56544+ "Savage3D/MX/IX.\n");
56545+ savage_do_cleanup_bci(dev);
56546+ return -EINVAL;
56547+ }
56548+ if (dev->dma && dev->dma->buflist) {
56549+ DRM_ERROR("command and vertex DMA not supported "
56550+ "at the same time.\n");
56551+ savage_do_cleanup_bci(dev);
56552+ return -EINVAL;
56553+ }
56554+ dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
56555+ if (!dev_priv->cmd_dma) {
56556+ DRM_ERROR("could not find command DMA region!\n");
56557+ savage_do_cleanup_bci(dev);
56558+ return -EINVAL;
56559+ }
56560+ if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
56561+ if (dev_priv->cmd_dma->type != _DRM_AGP) {
56562+ DRM_ERROR("AGP command DMA region is not a "
56563+ "_DRM_AGP map!\n");
56564+ savage_do_cleanup_bci(dev);
56565+ return -EINVAL;
56566+ }
56567+ drm_core_ioremap(dev_priv->cmd_dma, dev);
56568+ if (!dev_priv->cmd_dma->handle) {
56569+ DRM_ERROR("failed to ioremap command "
56570+ "DMA region!\n");
56571+ savage_do_cleanup_bci(dev);
56572+ return -ENOMEM;
56573+ }
56574+ } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
56575+ DRM_ERROR("PCI command DMA region is not a "
56576+ "_DRM_CONSISTENT map!\n");
56577+ savage_do_cleanup_bci(dev);
56578+ return -EINVAL;
56579+ }
56580+ } else {
56581+ dev_priv->cmd_dma = NULL;
56582+ }
56583+
56584+ dev_priv->dma_flush = savage_dma_flush;
56585+ if (!dev_priv->cmd_dma) {
56586+ DRM_DEBUG("falling back to faked command DMA.\n");
56587+ dev_priv->fake_dma.offset = 0;
56588+ dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
56589+ dev_priv->fake_dma.type = _DRM_SHM;
56590+ dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
56591+ DRM_MEM_DRIVER);
56592+ if (!dev_priv->fake_dma.handle) {
56593+ DRM_ERROR("could not allocate faked DMA buffer!\n");
56594+ savage_do_cleanup_bci(dev);
56595+ return -ENOMEM;
56596+ }
56597+ dev_priv->cmd_dma = &dev_priv->fake_dma;
56598+ dev_priv->dma_flush = savage_fake_dma_flush;
56599+ }
56600+
56601+ dev_priv->sarea_priv =
56602+ (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle +
56603+ init->sarea_priv_offset);
56604+
56605+ /* setup bitmap descriptors */
56606+ {
56607+ unsigned int color_tile_format;
56608+ unsigned int depth_tile_format;
56609+ unsigned int front_stride, back_stride, depth_stride;
56610+ if (dev_priv->chipset <= S3_SAVAGE4) {
56611+ color_tile_format = dev_priv->fb_bpp == 16 ?
56612+ SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
56613+ depth_tile_format = dev_priv->depth_bpp == 16 ?
56614+ SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
56615+ } else {
56616+ color_tile_format = SAVAGE_BD_TILE_DEST;
56617+ depth_tile_format = SAVAGE_BD_TILE_DEST;
56618+ }
56619+ front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
56620+ back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
56621+ depth_stride =
56622+ dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
56623+
56624+ dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
56625+ (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
56626+ (color_tile_format << SAVAGE_BD_TILE_SHIFT);
56627+
56628+ dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
56629+ (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
56630+ (color_tile_format << SAVAGE_BD_TILE_SHIFT);
56631+
56632+ dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
56633+ (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
56634+ (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
56635+ }
56636+
56637+ /* setup status and bci ptr */
56638+ dev_priv->event_counter = 0;
56639+ dev_priv->event_wrap = 0;
56640+ dev_priv->bci_ptr = (volatile uint32_t *)
56641+ ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
56642+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
56643+ dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
56644+ } else {
56645+ dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
56646+ }
56647+ if (dev_priv->status != NULL) {
56648+ dev_priv->status_ptr =
56649+ (volatile uint32_t *)dev_priv->status->handle;
56650+ dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
56651+ dev_priv->wait_evnt = savage_bci_wait_event_shadow;
56652+ dev_priv->status_ptr[1023] = dev_priv->event_counter;
56653+ } else {
56654+ dev_priv->status_ptr = NULL;
56655+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
56656+ dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
56657+ } else {
56658+ dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
56659+ }
56660+ dev_priv->wait_evnt = savage_bci_wait_event_reg;
56661+ }
56662+
56663+ /* cliprect functions */
56664+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
56665+ dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
56666+ else
56667+ dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
56668+
56669+ if (savage_freelist_init(dev) < 0) {
56670+ DRM_ERROR("could not initialize freelist\n");
56671+ savage_do_cleanup_bci(dev);
56672+ return -ENOMEM;
56673+ }
56674+
56675+ if (savage_dma_init(dev_priv) < 0) {
56676+ DRM_ERROR("could not initialize command DMA\n");
56677+ savage_do_cleanup_bci(dev);
56678+ return -ENOMEM;
56679+ }
56680+
56681+ return 0;
56682+}
56683+
56684+static int savage_do_cleanup_bci(struct drm_device *dev)
56685+{
56686+ drm_savage_private_t *dev_priv = dev->dev_private;
56687+
56688+ if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
56689+ if (dev_priv->fake_dma.handle)
56690+ drm_free(dev_priv->fake_dma.handle,
56691+ SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
56692+ } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
56693+ dev_priv->cmd_dma->type == _DRM_AGP &&
56694+ dev_priv->dma_type == SAVAGE_DMA_AGP)
56695+ drm_core_ioremapfree(dev_priv->cmd_dma, dev);
56696+
56697+ if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
56698+ dev->agp_buffer_map && dev->agp_buffer_map->handle) {
56699+ drm_core_ioremapfree(dev->agp_buffer_map, dev);
56700+ /* make sure the next instance (which may be running
56701+ * in PCI mode) doesn't try to use an old
56702+ * agp_buffer_map. */
56703+ dev->agp_buffer_map = NULL;
56704+ }
56705+
56706+ if (dev_priv->dma_pages)
56707+ drm_free(dev_priv->dma_pages,
56708+ sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages,
56709+ DRM_MEM_DRIVER);
56710+
56711+ return 0;
56712+}
56713+
56714+static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
56715+{
56716+ drm_savage_init_t *init = data;
56717+
56718+ LOCK_TEST_WITH_RETURN(dev, file_priv);
56719+
56720+ switch (init->func) {
56721+ case SAVAGE_INIT_BCI:
56722+ return savage_do_init_bci(dev, init);
56723+ case SAVAGE_CLEANUP_BCI:
56724+ return savage_do_cleanup_bci(dev);
56725+ }
56726+
56727+ return -EINVAL;
56728+}
56729+
56730+static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
56731+{
56732+ drm_savage_private_t *dev_priv = dev->dev_private;
56733+ drm_savage_event_emit_t *event = data;
56734+
56735+ DRM_DEBUG("\n");
56736+
56737+ LOCK_TEST_WITH_RETURN(dev, file_priv);
56738+
56739+ event->count = savage_bci_emit_event(dev_priv, event->flags);
56740+ event->count |= dev_priv->event_wrap << 16;
56741+
56742+ return 0;
56743+}
56744+
56745+static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
56746+{
56747+ drm_savage_private_t *dev_priv = dev->dev_private;
56748+ drm_savage_event_wait_t *event = data;
56749+ unsigned int event_e, hw_e;
56750+ unsigned int event_w, hw_w;
56751+
56752+ DRM_DEBUG("\n");
56753+
56754+ UPDATE_EVENT_COUNTER();
56755+ if (dev_priv->status_ptr)
56756+ hw_e = dev_priv->status_ptr[1] & 0xffff;
56757+ else
56758+ hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
56759+ hw_w = dev_priv->event_wrap;
56760+ if (hw_e > dev_priv->event_counter)
56761+ hw_w--; /* hardware hasn't passed the last wrap yet */
56762+
56763+ event_e = event->count & 0xffff;
56764+ event_w = event->count >> 16;
56765+
56766+ /* Don't need to wait if
56767+ * - event counter wrapped since the event was emitted or
56768+ * - the hardware has advanced up to or over the event to wait for.
56769+ */
56770+ if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) )
56771+ return 0;
56772+ else
56773+ return dev_priv->wait_evnt(dev_priv, event_e);
56774+}
56775+
56776+/*
56777+ * DMA buffer management
56778+ */
56779+
56780+static int savage_bci_get_buffers(struct drm_device *dev,
56781+ struct drm_file *file_priv,
56782+ struct drm_dma *d)
56783+{
56784+ struct drm_buf *buf;
56785+ int i;
56786+
56787+ for (i = d->granted_count; i < d->request_count; i++) {
56788+ buf = savage_freelist_get(dev);
56789+ if (!buf)
56790+ return -EAGAIN;
56791+
56792+ buf->file_priv = file_priv;
56793+
56794+ if (DRM_COPY_TO_USER(&d->request_indices[i],
56795+ &buf->idx, sizeof(buf->idx)))
56796+ return -EFAULT;
56797+ if (DRM_COPY_TO_USER(&d->request_sizes[i],
56798+ &buf->total, sizeof(buf->total)))
56799+ return -EFAULT;
56800+
56801+ d->granted_count++;
56802+ }
56803+ return 0;
56804+}
56805+
56806+int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
56807+{
56808+ struct drm_device_dma *dma = dev->dma;
56809+ struct drm_dma *d = data;
56810+ int ret = 0;
56811+
56812+ LOCK_TEST_WITH_RETURN(dev, file_priv);
56813+
56814+ /* Please don't send us buffers.
56815+ */
56816+ if (d->send_count != 0) {
56817+ DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
56818+ DRM_CURRENTPID, d->send_count);
56819+ return -EINVAL;
56820+ }
56821+
56822+ /* We'll send you buffers.
56823+ */
56824+ if (d->request_count < 0 || d->request_count > dma->buf_count) {
56825+ DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
56826+ DRM_CURRENTPID, d->request_count, dma->buf_count);
56827+ return -EINVAL;
56828+ }
56829+
56830+ d->granted_count = 0;
56831+
56832+ if (d->request_count) {
56833+ ret = savage_bci_get_buffers(dev, file_priv, d);
56834+ }
56835+
56836+ return ret;
56837+}
56838+
56839+void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
56840+{
56841+ struct drm_device_dma *dma = dev->dma;
56842+ drm_savage_private_t *dev_priv = dev->dev_private;
56843+ int i;
56844+
56845+ if (!dma)
56846+ return;
56847+ if (!dev_priv)
56848+ return;
56849+ if (!dma->buflist)
56850+ return;
56851+
56852+ /*i830_flush_queue(dev);*/
56853+
56854+ for (i = 0; i < dma->buf_count; i++) {
56855+ struct drm_buf *buf = dma->buflist[i];
56856+ drm_savage_buf_priv_t *buf_priv = buf->dev_private;
56857+
56858+ if (buf->file_priv == file_priv && buf_priv &&
56859+ buf_priv->next == NULL && buf_priv->prev == NULL) {
56860+ uint16_t event;
56861+ DRM_DEBUG("reclaimed from client\n");
56862+ event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
56863+ SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
56864+ savage_freelist_put(dev, buf);
56865+ }
56866+ }
56867+
56868+ drm_core_reclaim_buffers(dev, file_priv);
56869+}
56870+
56871+struct drm_ioctl_desc savage_ioctls[] = {
56872+ DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
56873+ DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH),
56874+ DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
56875+ DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH),
56876+};
56877+
56878+int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
56879+
56880Index: git/shared-core/savage_drm.h
56881===================================================================
56882--- git.orig/shared-core/savage_drm.h 2008-12-12 17:20:14.000000000 +0000
56883+++ git/shared-core/savage_drm.h 2008-12-12 17:35:22.000000000 +0000
56884@@ -47,7 +47,7 @@
56885 typedef struct _drm_savage_sarea {
56886 /* LRU lists for texture memory in agp space and on the card.
56887 */
56888- drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1];
56889+ struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1];
56890 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
56891
56892 /* Mechanism to validate card state.
56893@@ -112,7 +112,7 @@
56894 unsigned int vb_size; /* size of client vertex buffer in bytes */
56895 unsigned int vb_stride; /* stride of vertices in 32bit words */
56896 /* boxes in client's address space */
56897- drm_clip_rect_t __user *box_addr;
56898+ struct drm_clip_rect __user *box_addr;
56899 unsigned int nbox; /* number of clipping boxes */
56900 } drm_savage_cmdbuf_t;
56901
56902Index: git/shared-core/savage_drv.h
56903===================================================================
56904--- /dev/null 1970-01-01 00:00:00.000000000 +0000
56905+++ git/shared-core/savage_drv.h 2008-12-12 17:35:22.000000000 +0000
56906@@ -0,0 +1,575 @@
56907+/* savage_drv.h -- Private header for the savage driver */
56908+/*
56909+ * Copyright 2004 Felix Kuehling
56910+ * All Rights Reserved.
56911+ *
56912+ * Permission is hereby granted, free of charge, to any person obtaining a
56913+ * copy of this software and associated documentation files (the "Software"),
56914+ * to deal in the Software without restriction, including without limitation
56915+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
56916+ * and/or sell copies of the Software, and to permit persons to whom the
56917+ * Software is furnished to do so, subject to the following conditions:
56918+ *
56919+ * The above copyright notice and this permission notice (including the
56920+ * next paragraph) shall be included in all copies or substantial portions
56921+ * of the Software.
56922+ *
56923+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
56924+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
56925+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
56926+ * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
56927+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
56928+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
56929+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
56930+ */
56931+
56932+#ifndef __SAVAGE_DRV_H__
56933+#define __SAVAGE_DRV_H__
56934+
56935+#define DRIVER_AUTHOR "Felix Kuehling"
56936+
56937+#define DRIVER_NAME "savage"
56938+#define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
56939+#define DRIVER_DATE "20050313"
56940+
56941+#define DRIVER_MAJOR 2
56942+#define DRIVER_MINOR 4
56943+#define DRIVER_PATCHLEVEL 1
56944+/* Interface history:
56945+ *
56946+ * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy
56947+ * 2.0 The first real DRM
56948+ * 2.1 Scissors registers managed by the DRM, 3D operations clipped by
56949+ * cliprects of the cmdbuf ioctl
56950+ * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
56951+ * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
56952+ * wide and thus very long lived (unlikely to ever wrap). The size
56953+ * in the struct was 32 bits before, but only 16 bits were used
56954+ * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
56955+ * actually used
56956+ */
56957+
56958+typedef struct drm_savage_age {
56959+ uint16_t event;
56960+ unsigned int wrap;
56961+} drm_savage_age_t;
56962+
56963+typedef struct drm_savage_buf_priv {
56964+ struct drm_savage_buf_priv *next;
56965+ struct drm_savage_buf_priv *prev;
56966+ drm_savage_age_t age;
56967+ struct drm_buf *buf;
56968+} drm_savage_buf_priv_t;
56969+
56970+typedef struct drm_savage_dma_page {
56971+ drm_savage_age_t age;
56972+ unsigned int used, flushed;
56973+} drm_savage_dma_page_t;
56974+#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
56975+/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
56976+ * size of 16kbytes or 4k entries. Minimum requirement would be
56977+ * 10kbytes for 255 40-byte vertices in one drawing command. */
56978+#define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
56979+
56980+/* interesting bits of hardware state that are saved in dev_priv */
56981+typedef union {
56982+ struct drm_savage_common_state {
56983+ uint32_t vbaddr;
56984+ } common;
56985+ struct {
56986+ unsigned char pad[sizeof(struct drm_savage_common_state)];
56987+ uint32_t texctrl, texaddr;
56988+ uint32_t scstart, new_scstart;
56989+ uint32_t scend, new_scend;
56990+ } s3d;
56991+ struct {
56992+ unsigned char pad[sizeof(struct drm_savage_common_state)];
56993+ uint32_t texdescr, texaddr0, texaddr1;
56994+ uint32_t drawctrl0, new_drawctrl0;
56995+ uint32_t drawctrl1, new_drawctrl1;
56996+ } s4;
56997+} drm_savage_state_t;
56998+
56999+/* these chip tags should match the ones in the 2D driver in savage_regs.h. */
57000+enum savage_family {
57001+ S3_UNKNOWN = 0,
57002+ S3_SAVAGE3D,
57003+ S3_SAVAGE_MX,
57004+ S3_SAVAGE4,
57005+ S3_PROSAVAGE,
57006+ S3_TWISTER,
57007+ S3_PROSAVAGEDDR,
57008+ S3_SUPERSAVAGE,
57009+ S3_SAVAGE2000,
57010+ S3_LAST
57011+};
57012+
57013+extern struct drm_ioctl_desc savage_ioctls[];
57014+extern int savage_max_ioctl;
57015+
57016+#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
57017+
57018+#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
57019+ || (chip==S3_PROSAVAGE) \
57020+ || (chip==S3_TWISTER) \
57021+ || (chip==S3_PROSAVAGEDDR))
57022+
57023+#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
57024+
57025+#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
57026+
57027+#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \
57028+ ||(chip==S3_PROSAVAGEDDR))
57029+
57030+/* flags */
57031+#define SAVAGE_IS_AGP 1
57032+
57033+typedef struct drm_savage_private {
57034+ drm_savage_sarea_t *sarea_priv;
57035+
57036+ drm_savage_buf_priv_t head, tail;
57037+
57038+ /* who am I? */
57039+ enum savage_family chipset;
57040+
57041+ unsigned int cob_size;
57042+ unsigned int bci_threshold_lo, bci_threshold_hi;
57043+ unsigned int dma_type;
57044+
57045+ /* frame buffer layout */
57046+ unsigned int fb_bpp;
57047+ unsigned int front_offset, front_pitch;
57048+ unsigned int back_offset, back_pitch;
57049+ unsigned int depth_bpp;
57050+ unsigned int depth_offset, depth_pitch;
57051+
57052+ /* bitmap descriptors for swap and clear */
57053+ unsigned int front_bd, back_bd, depth_bd;
57054+
57055+ /* local textures */
57056+ unsigned int texture_offset;
57057+ unsigned int texture_size;
57058+
57059+ /* memory regions in physical memory */
57060+ drm_local_map_t *sarea;
57061+ drm_local_map_t *mmio;
57062+ drm_local_map_t *fb;
57063+ drm_local_map_t *aperture;
57064+ drm_local_map_t *status;
57065+ drm_local_map_t *agp_textures;
57066+ drm_local_map_t *cmd_dma;
57067+ drm_local_map_t fake_dma;
57068+
57069+ struct {
57070+ int handle;
57071+ unsigned long base, size;
57072+ } mtrr[3];
57073+
57074+ /* BCI and status-related stuff */
57075+ volatile uint32_t *status_ptr, *bci_ptr;
57076+ uint32_t status_used_mask;
57077+ uint16_t event_counter;
57078+ unsigned int event_wrap;
57079+
57080+ /* Savage4 command DMA */
57081+ drm_savage_dma_page_t *dma_pages;
57082+ unsigned int nr_dma_pages, first_dma_page, current_dma_page;
57083+ drm_savage_age_t last_dma_age;
57084+
57085+ /* saved hw state for global/local check on S3D */
57086+ uint32_t hw_draw_ctrl, hw_zbuf_ctrl;
57087+ /* and for scissors (global, so don't emit if not changed) */
57088+ uint32_t hw_scissors_start, hw_scissors_end;
57089+
57090+ drm_savage_state_t state;
57091+
57092+ /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
57093+ unsigned int waiting;
57094+
57095+ /* config/hardware-dependent function pointers */
57096+ int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n);
57097+ int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e);
57098+ /* Err, there is a macro wait_event in include/linux/wait.h.
57099+ * Avoid unwanted macro expansion. */
57100+ void (*emit_clip_rect)(struct drm_savage_private *dev_priv,
57101+ const struct drm_clip_rect *pbox);
57102+ void (*dma_flush)(struct drm_savage_private *dev_priv);
57103+} drm_savage_private_t;
57104+
57105+/* ioctls */
57106+extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv);
57107+extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
57108+
57109+/* BCI functions */
57110+extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
57111+ unsigned int flags);
57112+extern void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf);
57113+extern void savage_dma_reset(drm_savage_private_t *dev_priv);
57114+extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page);
57115+extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv,
57116+ unsigned int n);
57117+extern int savage_driver_load(struct drm_device *dev, unsigned long chipset);
57118+extern int savage_driver_firstopen(struct drm_device *dev);
57119+extern void savage_driver_lastclose(struct drm_device *dev);
57120+extern int savage_driver_unload(struct drm_device *dev);
57121+extern void savage_reclaim_buffers(struct drm_device *dev,
57122+ struct drm_file *file_priv);
57123+
57124+/* state functions */
57125+extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
57126+ const struct drm_clip_rect *pbox);
57127+extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
57128+ const struct drm_clip_rect *pbox);
57129+
57130+#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
57131+#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
57132+#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
57133+#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
57134+#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
57135+
57136+#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
57137+ * inside the MMIO region */
57138+#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
57139+ * BCI FIFO */
57140+
57141+/*
57142+ * MMIO registers
57143+ */
57144+#define SAVAGE_STATUS_WORD0 0x48C00
57145+#define SAVAGE_STATUS_WORD1 0x48C04
57146+#define SAVAGE_ALT_STATUS_WORD0 0x48C60
57147+
57148+#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
57149+#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
57150+
57151+/* Copied from savage_bci.h in the 2D driver with some renaming. */
57152+
57153+/* Bitmap descriptors */
57154+#define SAVAGE_BD_STRIDE_SHIFT 0
57155+#define SAVAGE_BD_BPP_SHIFT 16
57156+#define SAVAGE_BD_TILE_SHIFT 24
57157+#define SAVAGE_BD_BW_DISABLE (1<<28)
57158+/* common: */
57159+#define SAVAGE_BD_TILE_LINEAR 0
57160+/* savage4, MX, IX, 3D */
57161+#define SAVAGE_BD_TILE_16BPP 2
57162+#define SAVAGE_BD_TILE_32BPP 3
57163+/* twister, prosavage, DDR, supersavage, 2000 */
57164+#define SAVAGE_BD_TILE_DEST 1
57165+#define SAVAGE_BD_TILE_TEXTURE 2
57166+/* GBD - BCI enable */
57167+/* savage4, MX, IX, 3D */
57168+#define SAVAGE_GBD_BCI_ENABLE 8
57169+/* twister, prosavage, DDR, supersavage, 2000 */
57170+#define SAVAGE_GBD_BCI_ENABLE_TWISTER 0
57171+
57172+#define SAVAGE_GBD_BIG_ENDIAN 4
57173+#define SAVAGE_GBD_LITTLE_ENDIAN 0
57174+#define SAVAGE_GBD_64 1
57175+
57176+/* Global Bitmap Descriptor */
57177+#define SAVAGE_BCI_GLB_BD_LOW 0x8168
57178+#define SAVAGE_BCI_GLB_BD_HIGH 0x816C
57179+
57180+/*
57181+ * BCI registers
57182+ */
57183+/* Savage4/Twister/ProSavage 3D registers */
57184+#define SAVAGE_DRAWLOCALCTRL_S4 0x1e
57185+#define SAVAGE_TEXPALADDR_S4 0x1f
57186+#define SAVAGE_TEXCTRL0_S4 0x20
57187+#define SAVAGE_TEXCTRL1_S4 0x21
57188+#define SAVAGE_TEXADDR0_S4 0x22
57189+#define SAVAGE_TEXADDR1_S4 0x23
57190+#define SAVAGE_TEXBLEND0_S4 0x24
57191+#define SAVAGE_TEXBLEND1_S4 0x25
57192+#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
57193+#define SAVAGE_TEXDESCR_S4 0x27
57194+#define SAVAGE_FOGTABLE_S4 0x28
57195+#define SAVAGE_FOGCTRL_S4 0x30
57196+#define SAVAGE_STENCILCTRL_S4 0x31
57197+#define SAVAGE_ZBUFCTRL_S4 0x32
57198+#define SAVAGE_ZBUFOFF_S4 0x33
57199+#define SAVAGE_DESTCTRL_S4 0x34
57200+#define SAVAGE_DRAWCTRL0_S4 0x35
57201+#define SAVAGE_DRAWCTRL1_S4 0x36
57202+#define SAVAGE_ZWATERMARK_S4 0x37
57203+#define SAVAGE_DESTTEXRWWATERMARK_S4 0x38
57204+#define SAVAGE_TEXBLENDCOLOR_S4 0x39
57205+/* Savage3D/MX/IX 3D registers */
57206+#define SAVAGE_TEXPALADDR_S3D 0x18
57207+#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
57208+#define SAVAGE_TEXADDR_S3D 0x1A
57209+#define SAVAGE_TEXDESCR_S3D 0x1B
57210+#define SAVAGE_TEXCTRL_S3D 0x1C
57211+#define SAVAGE_FOGTABLE_S3D 0x20
57212+#define SAVAGE_FOGCTRL_S3D 0x30
57213+#define SAVAGE_DRAWCTRL_S3D 0x31
57214+#define SAVAGE_ZBUFCTRL_S3D 0x32
57215+#define SAVAGE_ZBUFOFF_S3D 0x33
57216+#define SAVAGE_DESTCTRL_S3D 0x34
57217+#define SAVAGE_SCSTART_S3D 0x35
57218+#define SAVAGE_SCEND_S3D 0x36
57219+#define SAVAGE_ZWATERMARK_S3D 0x37
57220+#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
57221+/* common stuff */
57222+#define SAVAGE_VERTBUFADDR 0x3e
57223+#define SAVAGE_BITPLANEWTMASK 0xd7
57224+#define SAVAGE_DMABUFADDR 0x51
57225+
57226+/* texture enable bits (needed for tex addr checking) */
57227+#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
57228+#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
57229+#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
57230+
57231+/* Global fields in Savage4/Twister/ProSavage 3D registers:
57232+ *
57233+ * All texture registers and DrawLocalCtrl are local. All other
57234+ * registers are global. */
57235+
57236+/* Global fields in Savage3D/MX/IX 3D registers:
57237+ *
57238+ * All texture registers are local. DrawCtrl and ZBufCtrl are
57239+ * partially local. All other registers are global.
57240+ *
57241+ * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
57242+ * ZBufCtrl global fields: zCmpFunc, zBufEn
57243+ */
57244+#define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c
57245+#define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027
57246+
57247+/* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
57248+ */
57249+#define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff
57250+#define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff
57251+
57252+/*
57253+ * BCI commands
57254+ */
57255+#define BCI_CMD_NOP 0x40000000
57256+#define BCI_CMD_RECT 0x48000000
57257+#define BCI_CMD_RECT_XP 0x01000000
57258+#define BCI_CMD_RECT_YP 0x02000000
57259+#define BCI_CMD_SCANLINE 0x50000000
57260+#define BCI_CMD_LINE 0x5C000000
57261+#define BCI_CMD_LINE_LAST_PIXEL 0x58000000
57262+#define BCI_CMD_BYTE_TEXT 0x63000000
57263+#define BCI_CMD_NT_BYTE_TEXT 0x67000000
57264+#define BCI_CMD_BIT_TEXT 0x6C000000
57265+#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
57266+#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
57267+#define BCI_CMD_SEND_COLOR 0x00008000
57268+
57269+#define BCI_CMD_CLIP_NONE 0x00000000
57270+#define BCI_CMD_CLIP_CURRENT 0x00002000
57271+#define BCI_CMD_CLIP_LR 0x00004000
57272+#define BCI_CMD_CLIP_NEW 0x00006000
57273+
57274+#define BCI_CMD_DEST_GBD 0x00000000
57275+#define BCI_CMD_DEST_PBD 0x00000800
57276+#define BCI_CMD_DEST_PBD_NEW 0x00000C00
57277+#define BCI_CMD_DEST_SBD 0x00001000
57278+#define BCI_CMD_DEST_SBD_NEW 0x00001400
57279+
57280+#define BCI_CMD_SRC_TRANSPARENT 0x00000200
57281+#define BCI_CMD_SRC_SOLID 0x00000000
57282+#define BCI_CMD_SRC_GBD 0x00000020
57283+#define BCI_CMD_SRC_COLOR 0x00000040
57284+#define BCI_CMD_SRC_MONO 0x00000060
57285+#define BCI_CMD_SRC_PBD_COLOR 0x00000080
57286+#define BCI_CMD_SRC_PBD_MONO 0x000000A0
57287+#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0
57288+#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0
57289+#define BCI_CMD_SRC_SBD_COLOR 0x00000100
57290+#define BCI_CMD_SRC_SBD_MONO 0x00000120
57291+#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140
57292+#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160
57293+
57294+#define BCI_CMD_PAT_TRANSPARENT 0x00000010
57295+#define BCI_CMD_PAT_NONE 0x00000000
57296+#define BCI_CMD_PAT_COLOR 0x00000002
57297+#define BCI_CMD_PAT_MONO 0x00000003
57298+#define BCI_CMD_PAT_PBD_COLOR 0x00000004
57299+#define BCI_CMD_PAT_PBD_MONO 0x00000005
57300+#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006
57301+#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007
57302+#define BCI_CMD_PAT_SBD_COLOR 0x00000008
57303+#define BCI_CMD_PAT_SBD_MONO 0x00000009
57304+#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A
57305+#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B
57306+
57307+#define BCI_BD_BW_DISABLE 0x10000000
57308+#define BCI_BD_TILE_MASK 0x03000000
57309+#define BCI_BD_TILE_NONE 0x00000000
57310+#define BCI_BD_TILE_16 0x02000000
57311+#define BCI_BD_TILE_32 0x03000000
57312+#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF)
57313+#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
57314+#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF)
57315+#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
57316+
57317+#define BCI_CMD_SET_REGISTER 0x96000000
57318+
57319+#define BCI_CMD_WAIT 0xC0000000
57320+#define BCI_CMD_WAIT_3D 0x00010000
57321+#define BCI_CMD_WAIT_2D 0x00020000
57322+
57323+#define BCI_CMD_UPDATE_EVENT_TAG 0x98000000
57324+
57325+#define BCI_CMD_DRAW_PRIM 0x80000000
57326+#define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000
57327+#define BCI_CMD_DRAW_CONT 0x01000000
57328+#define BCI_CMD_DRAW_TRILIST 0x00000000
57329+#define BCI_CMD_DRAW_TRISTRIP 0x02000000
57330+#define BCI_CMD_DRAW_TRIFAN 0x04000000
57331+#define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff
57332+#define BCI_CMD_DRAW_NO_Z 0x00000001
57333+#define BCI_CMD_DRAW_NO_W 0x00000002
57334+#define BCI_CMD_DRAW_NO_CD 0x00000004
57335+#define BCI_CMD_DRAW_NO_CS 0x00000008
57336+#define BCI_CMD_DRAW_NO_U0 0x00000010
57337+#define BCI_CMD_DRAW_NO_V0 0x00000020
57338+#define BCI_CMD_DRAW_NO_UV0 0x00000030
57339+#define BCI_CMD_DRAW_NO_U1 0x00000040
57340+#define BCI_CMD_DRAW_NO_V1 0x00000080
57341+#define BCI_CMD_DRAW_NO_UV1 0x000000c0
57342+
57343+#define BCI_CMD_DMA 0xa8000000
57344+
57345+#define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF)
57346+#define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF)
57347+#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF)
57348+#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
57349+#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
57350+#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
57351+
57352+#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF))
57353+#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF))
57354+#define BCI_LINE_MISC(maj, ym, xp, yp, err) \
57355+ (((maj) & 0x1FFF) | \
57356+ ((ym) ? 1<<13 : 0) | \
57357+ ((xp) ? 1<<14 : 0) | \
57358+ ((yp) ? 1<<15 : 0) | \
57359+ ((err) << 16))
57360+
57361+/*
57362+ * common commands
57363+ */
57364+#define BCI_SET_REGISTERS( first, n ) \
57365+ BCI_WRITE(BCI_CMD_SET_REGISTER | \
57366+ ((uint32_t)(n) & 0xff) << 16 | \
57367+ ((uint32_t)(first) & 0xffff))
57368+#define DMA_SET_REGISTERS( first, n ) \
57369+ DMA_WRITE(BCI_CMD_SET_REGISTER | \
57370+ ((uint32_t)(n) & 0xff) << 16 | \
57371+ ((uint32_t)(first) & 0xffff))
57372+
57373+#define BCI_DRAW_PRIMITIVE(n, type, skip) \
57374+ BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
57375+ ((n) << 16))
57376+#define DMA_DRAW_PRIMITIVE(n, type, skip) \
57377+ DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
57378+ ((n) << 16))
57379+
57380+#define BCI_DRAW_INDICES_S3D(n, type, i0) \
57381+ BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
57382+ ((n) << 16) | (i0))
57383+
57384+#define BCI_DRAW_INDICES_S4(n, type, skip) \
57385+ BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
57386+ (skip) | ((n) << 16))
57387+
57388+#define BCI_DMA(n) \
57389+ BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
57390+
57391+/*
57392+ * access to MMIO
57393+ */
57394+#define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
57395+#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
57396+
57397+/*
57398+ * access to the burst command interface (BCI)
57399+ */
57400+#define SAVAGE_BCI_DEBUG 1
57401+
57402+#define BCI_LOCALS volatile uint32_t *bci_ptr;
57403+
57404+#define BEGIN_BCI( n ) do { \
57405+ dev_priv->wait_fifo(dev_priv, (n)); \
57406+ bci_ptr = dev_priv->bci_ptr; \
57407+} while(0)
57408+
57409+#define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
57410+
57411+/*
57412+ * command DMA support
57413+ */
57414+#define SAVAGE_DMA_DEBUG 1
57415+
57416+#define DMA_LOCALS uint32_t *dma_ptr;
57417+
57418+#define BEGIN_DMA( n ) do { \
57419+ unsigned int cur = dev_priv->current_dma_page; \
57420+ unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \
57421+ dev_priv->dma_pages[cur].used; \
57422+ if ((n) > rest) { \
57423+ dma_ptr = savage_dma_alloc(dev_priv, (n)); \
57424+ } else { /* fast path for small allocations */ \
57425+ dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \
57426+ cur * SAVAGE_DMA_PAGE_SIZE + \
57427+ dev_priv->dma_pages[cur].used; \
57428+ if (dev_priv->dma_pages[cur].used == 0) \
57429+ savage_dma_wait(dev_priv, cur); \
57430+ dev_priv->dma_pages[cur].used += (n); \
57431+ } \
57432+} while(0)
57433+
57434+#define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
57435+
57436+#define DMA_COPY(src, n) do { \
57437+ memcpy(dma_ptr, (src), (n)*4); \
57438+ dma_ptr += n; \
57439+} while(0)
57440+
57441+#if SAVAGE_DMA_DEBUG
57442+#define DMA_COMMIT() do { \
57443+ unsigned int cur = dev_priv->current_dma_page; \
57444+ uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \
57445+ cur * SAVAGE_DMA_PAGE_SIZE + \
57446+ dev_priv->dma_pages[cur].used; \
57447+ if (dma_ptr != expected) { \
57448+ DRM_ERROR("DMA allocation and use don't match: " \
57449+ "%p != %p\n", expected, dma_ptr); \
57450+ savage_dma_reset(dev_priv); \
57451+ } \
57452+} while(0)
57453+#else
57454+#define DMA_COMMIT() do {/* nothing */} while(0)
57455+#endif
57456+
57457+#define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
57458+
57459+/* Buffer aging via event tag
57460+ */
57461+
57462+#define UPDATE_EVENT_COUNTER( ) do { \
57463+ if (dev_priv->status_ptr) { \
57464+ uint16_t count; \
57465+ /* coordinate with Xserver */ \
57466+ count = dev_priv->status_ptr[1023]; \
57467+ if (count < dev_priv->event_counter) \
57468+ dev_priv->event_wrap++; \
57469+ dev_priv->event_counter = count; \
57470+ } \
57471+} while(0)
57472+
57473+#define SET_AGE( age, e, w ) do { \
57474+ (age)->event = e; \
57475+ (age)->wrap = w; \
57476+} while(0)
57477+
57478+#define TEST_AGE( age, e, w ) \
57479+ ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
57480+
57481+#endif /* __SAVAGE_DRV_H__ */
57482Index: git/shared-core/savage_state.c
57483===================================================================
57484--- /dev/null 1970-01-01 00:00:00.000000000 +0000
57485+++ git/shared-core/savage_state.c 2008-12-12 17:35:22.000000000 +0000
57486@@ -0,0 +1,1165 @@
57487+/* savage_state.c -- State and drawing support for Savage
57488+ *
57489+ * Copyright 2004 Felix Kuehling
57490+ * All Rights Reserved.
57491+ *
57492+ * Permission is hereby granted, free of charge, to any person obtaining a
57493+ * copy of this software and associated documentation files (the "Software"),
57494+ * to deal in the Software without restriction, including without limitation
57495+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
57496+ * and/or sell copies of the Software, and to permit persons to whom the
57497+ * Software is furnished to do so, subject to the following conditions:
57498+ *
57499+ * The above copyright notice and this permission notice (including the
57500+ * next paragraph) shall be included in all copies or substantial portions
57501+ * of the Software.
57502+ *
57503+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
57504+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
57505+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
57506+ * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
57507+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
57508+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
57509+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
57510+ */
57511+#include "drmP.h"
57512+#include "savage_drm.h"
57513+#include "savage_drv.h"
57514+
57515+void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
57516+ const struct drm_clip_rect *pbox)
57517+{
57518+ uint32_t scstart = dev_priv->state.s3d.new_scstart;
57519+ uint32_t scend = dev_priv->state.s3d.new_scend;
57520+ scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
57521+ ((uint32_t)pbox->x1 & 0x000007ff) |
57522+ (((uint32_t)pbox->y1 << 16) & 0x07ff0000);
57523+ scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
57524+ (((uint32_t)pbox->x2-1) & 0x000007ff) |
57525+ ((((uint32_t)pbox->y2-1) << 16) & 0x07ff0000);
57526+ if (scstart != dev_priv->state.s3d.scstart ||
57527+ scend != dev_priv->state.s3d.scend) {
57528+ DMA_LOCALS;
57529+ BEGIN_DMA(4);
57530+ DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
57531+ DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2);
57532+ DMA_WRITE(scstart);
57533+ DMA_WRITE(scend);
57534+ dev_priv->state.s3d.scstart = scstart;
57535+ dev_priv->state.s3d.scend = scend;
57536+ dev_priv->waiting = 1;
57537+ DMA_COMMIT();
57538+ }
57539+}
57540+
57541+void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
57542+ const struct drm_clip_rect *pbox)
57543+{
57544+ uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;
57545+ uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;
57546+ drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) |
57547+ ((uint32_t)pbox->x1 & 0x000007ff) |
57548+ (((uint32_t)pbox->y1 << 12) & 0x00fff000);
57549+ drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) |
57550+ (((uint32_t)pbox->x2-1) & 0x000007ff) |
57551+ ((((uint32_t)pbox->y2-1) << 12) & 0x00fff000);
57552+ if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||
57553+ drawctrl1 != dev_priv->state.s4.drawctrl1) {
57554+ DMA_LOCALS;
57555+ BEGIN_DMA(4);
57556+ DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
57557+ DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2);
57558+ DMA_WRITE(drawctrl0);
57559+ DMA_WRITE(drawctrl1);
57560+ dev_priv->state.s4.drawctrl0 = drawctrl0;
57561+ dev_priv->state.s4.drawctrl1 = drawctrl1;
57562+ dev_priv->waiting = 1;
57563+ DMA_COMMIT();
57564+ }
57565+}
57566+
57567+static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit,
57568+ uint32_t addr)
57569+{
57570+ if ((addr & 6) != 2) { /* reserved bits */
57571+ DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr);
57572+ return -EINVAL;
57573+ }
57574+ if (!(addr & 1)) { /* local */
57575+ addr &= ~7;
57576+ if (addr < dev_priv->texture_offset ||
57577+ addr >= dev_priv->texture_offset+dev_priv->texture_size) {
57578+ DRM_ERROR
57579+ ("bad texAddr%d %08x (local addr out of range)\n",
57580+ unit, addr);
57581+ return -EINVAL;
57582+ }
57583+ } else { /* AGP */
57584+ if (!dev_priv->agp_textures) {
57585+ DRM_ERROR("bad texAddr%d %08x (AGP not available)\n",
57586+ unit, addr);
57587+ return -EINVAL;
57588+ }
57589+ addr &= ~7;
57590+ if (addr < dev_priv->agp_textures->offset ||
57591+ addr >= (dev_priv->agp_textures->offset +
57592+ dev_priv->agp_textures->size)) {
57593+ DRM_ERROR
57594+ ("bad texAddr%d %08x (AGP addr out of range)\n",
57595+ unit, addr);
57596+ return -EINVAL;
57597+ }
57598+ }
57599+ return 0;
57600+}
57601+
57602+#define SAVE_STATE(reg,where) \
57603+ if(start <= reg && start+count > reg) \
57604+ dev_priv->state.where = regs[reg - start]
57605+#define SAVE_STATE_MASK(reg,where,mask) do { \
57606+ if(start <= reg && start+count > reg) { \
57607+ uint32_t tmp; \
57608+ tmp = regs[reg - start]; \
57609+ dev_priv->state.where = (tmp & (mask)) | \
57610+ (dev_priv->state.where & ~(mask)); \
57611+ } \
57612+} while (0)
57613+static int savage_verify_state_s3d(drm_savage_private_t *dev_priv,
57614+ unsigned int start, unsigned int count,
57615+ const uint32_t *regs)
57616+{
57617+ if (start < SAVAGE_TEXPALADDR_S3D ||
57618+ start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) {
57619+ DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
57620+ start, start+count-1);
57621+ return -EINVAL;
57622+ }
57623+
57624+ SAVE_STATE_MASK(SAVAGE_SCSTART_S3D, s3d.new_scstart,
57625+ ~SAVAGE_SCISSOR_MASK_S3D);
57626+ SAVE_STATE_MASK(SAVAGE_SCEND_S3D, s3d.new_scend,
57627+ ~SAVAGE_SCISSOR_MASK_S3D);
57628+
57629+ /* if any texture regs were changed ... */
57630+ if (start <= SAVAGE_TEXCTRL_S3D &&
57631+ start+count > SAVAGE_TEXPALADDR_S3D) {
57632+ /* ... check texture state */
57633+ SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl);
57634+ SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr);
57635+ if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)
57636+ return savage_verify_texaddr(dev_priv, 0,
57637+ dev_priv->state.s3d.texaddr);
57638+ }
57639+
57640+ return 0;
57641+}
57642+
57643+static int savage_verify_state_s4(drm_savage_private_t *dev_priv,
57644+ unsigned int start, unsigned int count,
57645+ const uint32_t *regs)
57646+{
57647+ int ret = 0;
57648+
57649+ if (start < SAVAGE_DRAWLOCALCTRL_S4 ||
57650+ start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) {
57651+ DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
57652+ start, start+count-1);
57653+ return -EINVAL;
57654+ }
57655+
57656+ SAVE_STATE_MASK(SAVAGE_DRAWCTRL0_S4, s4.new_drawctrl0,
57657+ ~SAVAGE_SCISSOR_MASK_S4);
57658+ SAVE_STATE_MASK(SAVAGE_DRAWCTRL1_S4, s4.new_drawctrl1,
57659+ ~SAVAGE_SCISSOR_MASK_S4);
57660+
57661+ /* if any texture regs were changed ... */
57662+ if (start <= SAVAGE_TEXDESCR_S4 &&
57663+ start + count > SAVAGE_TEXPALADDR_S4) {
57664+ /* ... check texture state */
57665+ SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr);
57666+ SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0);
57667+ SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1);
57668+ if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)
57669+ ret |= savage_verify_texaddr(dev_priv, 0,
57670+ dev_priv->state.s4.texaddr0);
57671+ if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)
57672+ ret |= savage_verify_texaddr(dev_priv, 1,
57673+ dev_priv->state.s4.texaddr1);
57674+ }
57675+
57676+ return ret;
57677+}
57678+#undef SAVE_STATE
57679+#undef SAVE_STATE_MASK
57680+
57681+static int savage_dispatch_state(drm_savage_private_t *dev_priv,
57682+ const drm_savage_cmd_header_t *cmd_header,
57683+ const uint32_t *regs)
57684+{
57685+ unsigned int count = cmd_header->state.count;
57686+ unsigned int start = cmd_header->state.start;
57687+ unsigned int count2 = 0;
57688+ unsigned int bci_size;
57689+ int ret;
57690+ DMA_LOCALS;
57691+
57692+ if (!count)
57693+ return 0;
57694+
57695+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
57696+ ret = savage_verify_state_s3d(dev_priv, start, count, regs);
57697+ if (ret != 0)
57698+ return ret;
57699+ /* scissor regs are emitted in savage_dispatch_draw */
57700+ if (start < SAVAGE_SCSTART_S3D) {
57701+ if (start+count > SAVAGE_SCEND_S3D+1)
57702+ count2 = count - (SAVAGE_SCEND_S3D+1 - start);
57703+ if (start+count > SAVAGE_SCSTART_S3D)
57704+ count = SAVAGE_SCSTART_S3D - start;
57705+ } else if (start <= SAVAGE_SCEND_S3D) {
57706+ if (start+count > SAVAGE_SCEND_S3D+1) {
57707+ count -= SAVAGE_SCEND_S3D+1 - start;
57708+ start = SAVAGE_SCEND_S3D+1;
57709+ } else
57710+ return 0;
57711+ }
57712+ } else {
57713+ ret = savage_verify_state_s4(dev_priv, start, count, regs);
57714+ if (ret != 0)
57715+ return ret;
57716+ /* scissor regs are emitted in savage_dispatch_draw */
57717+ if (start < SAVAGE_DRAWCTRL0_S4) {
57718+ if (start+count > SAVAGE_DRAWCTRL1_S4+1)
57719+ count2 = count -
57720+ (SAVAGE_DRAWCTRL1_S4 + 1 - start);
57721+ if (start+count > SAVAGE_DRAWCTRL0_S4)
57722+ count = SAVAGE_DRAWCTRL0_S4 - start;
57723+ } else if (start <= SAVAGE_DRAWCTRL1_S4) {
57724+ if (start+count > SAVAGE_DRAWCTRL1_S4+1) {
57725+ count -= SAVAGE_DRAWCTRL1_S4+1 - start;
57726+ start = SAVAGE_DRAWCTRL1_S4+1;
57727+ } else
57728+ return 0;
57729+ }
57730+ }
57731+
57732+ bci_size = count + (count+254)/255 + count2 + (count2+254)/255;
57733+
57734+ if (cmd_header->state.global) {
57735+ BEGIN_DMA(bci_size+1);
57736+ DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
57737+ dev_priv->waiting = 1;
57738+ } else {
57739+ BEGIN_DMA(bci_size);
57740+ }
57741+
57742+ do {
57743+ while (count > 0) {
57744+ unsigned int n = count < 255 ? count : 255;
57745+ DMA_SET_REGISTERS(start, n);
57746+ DMA_COPY(regs, n);
57747+ count -= n;
57748+ start += n;
57749+ regs += n;
57750+ }
57751+ start += 2;
57752+ regs += 2;
57753+ count = count2;
57754+ count2 = 0;
57755+ } while (count);
57756+
57757+ DMA_COMMIT();
57758+
57759+ return 0;
57760+}
57761+
57762+static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
57763+ const drm_savage_cmd_header_t *cmd_header,
57764+ const struct drm_buf *dmabuf)
57765+{
57766+ unsigned char reorder = 0;
57767+ unsigned int prim = cmd_header->prim.prim;
57768+ unsigned int skip = cmd_header->prim.skip;
57769+ unsigned int n = cmd_header->prim.count;
57770+ unsigned int start = cmd_header->prim.start;
57771+ unsigned int i;
57772+ BCI_LOCALS;
57773+
57774+ if (!dmabuf) {
57775+ DRM_ERROR("called without dma buffers!\n");
57776+ return -EINVAL;
57777+ }
57778+
57779+ if (!n)
57780+ return 0;
57781+
57782+ switch (prim) {
57783+ case SAVAGE_PRIM_TRILIST_201:
57784+ reorder = 1;
57785+ prim = SAVAGE_PRIM_TRILIST;
57786+ case SAVAGE_PRIM_TRILIST:
57787+ if (n % 3 != 0) {
57788+ DRM_ERROR("wrong number of vertices %u in TRILIST\n",
57789+ n);
57790+ return -EINVAL;
57791+ }
57792+ break;
57793+ case SAVAGE_PRIM_TRISTRIP:
57794+ case SAVAGE_PRIM_TRIFAN:
57795+ if (n < 3) {
57796+ DRM_ERROR
57797+ ("wrong number of vertices %u in TRIFAN/STRIP\n",
57798+ n);
57799+ return -EINVAL;
57800+ }
57801+ break;
57802+ default:
57803+ DRM_ERROR("invalid primitive type %u\n", prim);
57804+ return -EINVAL;
57805+ }
57806+
57807+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
57808+ if (skip != 0) {
57809+ DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
57810+ return -EINVAL;
57811+ }
57812+ } else {
57813+ unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
57814+ (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
57815+ (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
57816+ if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
57817+ DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
57818+ return -EINVAL;
57819+ }
57820+ if (reorder) {
57821+ DRM_ERROR("TRILIST_201 used on Savage4 hardware\n");
57822+ return -EINVAL;
57823+ }
57824+ }
57825+
57826+ if (start + n > dmabuf->total/32) {
57827+ DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
57828+ start, start + n - 1, dmabuf->total/32);
57829+ return -EINVAL;
57830+ }
57831+
57832+ /* Vertex DMA doesn't work with command DMA at the same time,
57833+ * so we use BCI_... to submit commands here. Flush buffered
57834+ * faked DMA first. */
57835+ DMA_FLUSH();
57836+
57837+ if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
57838+ BEGIN_BCI(2);
57839+ BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1);
57840+ BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
57841+ dev_priv->state.common.vbaddr = dmabuf->bus_address;
57842+ }
57843+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
57844+ /* Workaround for what looks like a hardware bug. If a
57845+ * WAIT_3D_IDLE was emitted some time before the
57846+ * indexed drawing command then the engine will lock
57847+ * up. There are two known workarounds:
57848+ * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */
57849+ BEGIN_BCI(63);
57850+ for (i = 0; i < 63; ++i)
57851+ BCI_WRITE(BCI_CMD_WAIT);
57852+ dev_priv->waiting = 0;
57853+ }
57854+
57855+ prim <<= 25;
57856+ while (n != 0) {
57857+ /* Can emit up to 255 indices (85 triangles) at once. */
57858+ unsigned int count = n > 255 ? 255 : n;
57859+ if (reorder) {
57860+ /* Need to reorder indices for correct flat
57861+ * shading while preserving the clock sense
57862+ * for correct culling. Only on Savage3D. */
57863+ int reorder[3] = {-1, -1, -1};
57864+ reorder[start%3] = 2;
57865+
57866+ BEGIN_BCI((count+1+1)/2);
57867+ BCI_DRAW_INDICES_S3D(count, prim, start+2);
57868+
57869+ for (i = start+1; i+1 < start+count; i += 2)
57870+ BCI_WRITE((i + reorder[i % 3]) |
57871+ ((i + 1 +
57872+ reorder[(i + 1) % 3]) << 16));
57873+ if (i < start+count)
57874+ BCI_WRITE(i + reorder[i%3]);
57875+ } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
57876+ BEGIN_BCI((count+1+1)/2);
57877+ BCI_DRAW_INDICES_S3D(count, prim, start);
57878+
57879+ for (i = start+1; i+1 < start+count; i += 2)
57880+ BCI_WRITE(i | ((i+1) << 16));
57881+ if (i < start+count)
57882+ BCI_WRITE(i);
57883+ } else {
57884+ BEGIN_BCI((count+2+1)/2);
57885+ BCI_DRAW_INDICES_S4(count, prim, skip);
57886+
57887+ for (i = start; i+1 < start+count; i += 2)
57888+ BCI_WRITE(i | ((i+1) << 16));
57889+ if (i < start+count)
57890+ BCI_WRITE(i);
57891+ }
57892+
57893+ start += count;
57894+ n -= count;
57895+
57896+ prim |= BCI_CMD_DRAW_CONT;
57897+ }
57898+
57899+ return 0;
57900+}
57901+
57902+static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
57903+ const drm_savage_cmd_header_t *cmd_header,
57904+ const uint32_t *vtxbuf, unsigned int vb_size,
57905+ unsigned int vb_stride)
57906+{
57907+ unsigned char reorder = 0;
57908+ unsigned int prim = cmd_header->prim.prim;
57909+ unsigned int skip = cmd_header->prim.skip;
57910+ unsigned int n = cmd_header->prim.count;
57911+ unsigned int start = cmd_header->prim.start;
57912+ unsigned int vtx_size;
57913+ unsigned int i;
57914+ DMA_LOCALS;
57915+
57916+ if (!n)
57917+ return 0;
57918+
57919+ switch (prim) {
57920+ case SAVAGE_PRIM_TRILIST_201:
57921+ reorder = 1;
57922+ prim = SAVAGE_PRIM_TRILIST;
57923+ case SAVAGE_PRIM_TRILIST:
57924+ if (n % 3 != 0) {
57925+ DRM_ERROR("wrong number of vertices %u in TRILIST\n",
57926+ n);
57927+ return -EINVAL;
57928+ }
57929+ break;
57930+ case SAVAGE_PRIM_TRISTRIP:
57931+ case SAVAGE_PRIM_TRIFAN:
57932+ if (n < 3) {
57933+ DRM_ERROR
57934+ ("wrong number of vertices %u in TRIFAN/STRIP\n",
57935+ n);
57936+ return -EINVAL;
57937+ }
57938+ break;
57939+ default:
57940+ DRM_ERROR("invalid primitive type %u\n", prim);
57941+ return -EINVAL;
57942+ }
57943+
57944+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
57945+ if (skip > SAVAGE_SKIP_ALL_S3D) {
57946+ DRM_ERROR("invalid skip flags 0x%04x\n", skip);
57947+ return -EINVAL;
57948+ }
57949+ vtx_size = 8; /* full vertex */
57950+ } else {
57951+ if (skip > SAVAGE_SKIP_ALL_S4) {
57952+ DRM_ERROR("invalid skip flags 0x%04x\n", skip);
57953+ return -EINVAL;
57954+ }
57955+ vtx_size = 10; /* full vertex */
57956+ }
57957+
57958+ vtx_size -= (skip & 1) + (skip >> 1 & 1) +
57959+ (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
57960+ (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
57961+
57962+ if (vtx_size > vb_stride) {
57963+ DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
57964+ vtx_size, vb_stride);
57965+ return -EINVAL;
57966+ }
57967+
57968+ if (start + n > vb_size / (vb_stride*4)) {
57969+ DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
57970+ start, start + n - 1, vb_size / (vb_stride*4));
57971+ return -EINVAL;
57972+ }
57973+
57974+ prim <<= 25;
57975+ while (n != 0) {
57976+ /* Can emit up to 255 vertices (85 triangles) at once. */
57977+ unsigned int count = n > 255 ? 255 : n;
57978+ if (reorder) {
57979+ /* Need to reorder vertices for correct flat
57980+ * shading while preserving the clock sense
57981+ * for correct culling. Only on Savage3D. */
57982+ int reorder[3] = {-1, -1, -1};
57983+ reorder[start%3] = 2;
57984+
57985+ BEGIN_DMA(count*vtx_size+1);
57986+ DMA_DRAW_PRIMITIVE(count, prim, skip);
57987+
57988+ for (i = start; i < start+count; ++i) {
57989+ unsigned int j = i + reorder[i % 3];
57990+ DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
57991+ }
57992+
57993+ DMA_COMMIT();
57994+ } else {
57995+ BEGIN_DMA(count*vtx_size+1);
57996+ DMA_DRAW_PRIMITIVE(count, prim, skip);
57997+
57998+ if (vb_stride == vtx_size) {
57999+ DMA_COPY(&vtxbuf[vb_stride*start],
58000+ vtx_size*count);
58001+ } else {
58002+ for (i = start; i < start+count; ++i) {
58003+ DMA_COPY(&vtxbuf[vb_stride*i],
58004+ vtx_size);
58005+ }
58006+ }
58007+
58008+ DMA_COMMIT();
58009+ }
58010+
58011+ start += count;
58012+ n -= count;
58013+
58014+ prim |= BCI_CMD_DRAW_CONT;
58015+ }
58016+
58017+ return 0;
58018+}
58019+
58020+static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
58021+ const drm_savage_cmd_header_t *cmd_header,
58022+ const uint16_t *idx,
58023+ const struct drm_buf *dmabuf)
58024+{
58025+ unsigned char reorder = 0;
58026+ unsigned int prim = cmd_header->idx.prim;
58027+ unsigned int skip = cmd_header->idx.skip;
58028+ unsigned int n = cmd_header->idx.count;
58029+ unsigned int i;
58030+ BCI_LOCALS;
58031+
58032+ if (!dmabuf) {
58033+ DRM_ERROR("called without dma buffers!\n");
58034+ return -EINVAL;
58035+ }
58036+
58037+ if (!n)
58038+ return 0;
58039+
58040+ switch (prim) {
58041+ case SAVAGE_PRIM_TRILIST_201:
58042+ reorder = 1;
58043+ prim = SAVAGE_PRIM_TRILIST;
58044+ case SAVAGE_PRIM_TRILIST:
58045+ if (n % 3 != 0) {
58046+ DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
58047+ return -EINVAL;
58048+ }
58049+ break;
58050+ case SAVAGE_PRIM_TRISTRIP:
58051+ case SAVAGE_PRIM_TRIFAN:
58052+ if (n < 3) {
58053+ DRM_ERROR
58054+ ("wrong number of indices %u in TRIFAN/STRIP\n", n);
58055+ return -EINVAL;
58056+ }
58057+ break;
58058+ default:
58059+ DRM_ERROR("invalid primitive type %u\n", prim);
58060+ return -EINVAL;
58061+ }
58062+
58063+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
58064+ if (skip != 0) {
58065+ DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
58066+ return -EINVAL;
58067+ }
58068+ } else {
58069+ unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
58070+ (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
58071+ (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
58072+ if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
58073+ DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
58074+ return -EINVAL;
58075+ }
58076+ if (reorder) {
58077+ DRM_ERROR("TRILIST_201 used on Savage4 hardware\n");
58078+ return -EINVAL;
58079+ }
58080+ }
58081+
58082+ /* Vertex DMA doesn't work with command DMA at the same time,
58083+ * so we use BCI_... to submit commands here. Flush buffered
58084+ * faked DMA first. */
58085+ DMA_FLUSH();
58086+
58087+ if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
58088+ BEGIN_BCI(2);
58089+ BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1);
58090+ BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
58091+ dev_priv->state.common.vbaddr = dmabuf->bus_address;
58092+ }
58093+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
58094+ /* Workaround for what looks like a hardware bug. If a
58095+ * WAIT_3D_IDLE was emitted some time before the
58096+ * indexed drawing command then the engine will lock
58097+ * up. There are two known workarounds:
58098+ * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */
58099+ BEGIN_BCI(63);
58100+ for (i = 0; i < 63; ++i)
58101+ BCI_WRITE(BCI_CMD_WAIT);
58102+ dev_priv->waiting = 0;
58103+ }
58104+
58105+ prim <<= 25;
58106+ while (n != 0) {
58107+ /* Can emit up to 255 indices (85 triangles) at once. */
58108+ unsigned int count = n > 255 ? 255 : n;
58109+
58110+ /* check indices */
58111+ for (i = 0; i < count; ++i) {
58112+ if (idx[i] > dmabuf->total/32) {
58113+ DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
58114+ i, idx[i], dmabuf->total/32);
58115+ return -EINVAL;
58116+ }
58117+ }
58118+
58119+ if (reorder) {
58120+ /* Need to reorder indices for correct flat
58121+ * shading while preserving the clock sense
58122+ * for correct culling. Only on Savage3D. */
58123+ int reorder[3] = {2, -1, -1};
58124+
58125+ BEGIN_BCI((count+1+1)/2);
58126+ BCI_DRAW_INDICES_S3D(count, prim, idx[2]);
58127+
58128+ for (i = 1; i+1 < count; i += 2)
58129+ BCI_WRITE(idx[i + reorder[i % 3]] |
58130+ (idx[i + 1 +
58131+ reorder[(i + 1) % 3]] << 16));
58132+ if (i < count)
58133+ BCI_WRITE(idx[i + reorder[i%3]]);
58134+ } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
58135+ BEGIN_BCI((count+1+1)/2);
58136+ BCI_DRAW_INDICES_S3D(count, prim, idx[0]);
58137+
58138+ for (i = 1; i+1 < count; i += 2)
58139+ BCI_WRITE(idx[i] | (idx[i+1] << 16));
58140+ if (i < count)
58141+ BCI_WRITE(idx[i]);
58142+ } else {
58143+ BEGIN_BCI((count+2+1)/2);
58144+ BCI_DRAW_INDICES_S4(count, prim, skip);
58145+
58146+ for (i = 0; i+1 < count; i += 2)
58147+ BCI_WRITE(idx[i] | (idx[i+1] << 16));
58148+ if (i < count)
58149+ BCI_WRITE(idx[i]);
58150+ }
58151+
58152+ idx += count;
58153+ n -= count;
58154+
58155+ prim |= BCI_CMD_DRAW_CONT;
58156+ }
58157+
58158+ return 0;
58159+}
58160+
58161+static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
58162+ const drm_savage_cmd_header_t *cmd_header,
58163+ const uint16_t *idx,
58164+ const uint32_t *vtxbuf,
58165+ unsigned int vb_size, unsigned int vb_stride)
58166+{
58167+ unsigned char reorder = 0;
58168+ unsigned int prim = cmd_header->idx.prim;
58169+ unsigned int skip = cmd_header->idx.skip;
58170+ unsigned int n = cmd_header->idx.count;
58171+ unsigned int vtx_size;
58172+ unsigned int i;
58173+ DMA_LOCALS;
58174+
58175+ if (!n)
58176+ return 0;
58177+
58178+ switch (prim) {
58179+ case SAVAGE_PRIM_TRILIST_201:
58180+ reorder = 1;
58181+ prim = SAVAGE_PRIM_TRILIST;
58182+ case SAVAGE_PRIM_TRILIST:
58183+ if (n % 3 != 0) {
58184+ DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
58185+ return -EINVAL;
58186+ }
58187+ break;
58188+ case SAVAGE_PRIM_TRISTRIP:
58189+ case SAVAGE_PRIM_TRIFAN:
58190+ if (n < 3) {
58191+ DRM_ERROR
58192+ ("wrong number of indices %u in TRIFAN/STRIP\n", n);
58193+ return -EINVAL;
58194+ }
58195+ break;
58196+ default:
58197+ DRM_ERROR("invalid primitive type %u\n", prim);
58198+ return -EINVAL;
58199+ }
58200+
58201+ if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
58202+ if (skip > SAVAGE_SKIP_ALL_S3D) {
58203+ DRM_ERROR("invalid skip flags 0x%04x\n", skip);
58204+ return -EINVAL;
58205+ }
58206+ vtx_size = 8; /* full vertex */
58207+ } else {
58208+ if (skip > SAVAGE_SKIP_ALL_S4) {
58209+ DRM_ERROR("invalid skip flags 0x%04x\n", skip);
58210+ return -EINVAL;
58211+ }
58212+ vtx_size = 10; /* full vertex */
58213+ }
58214+
58215+ vtx_size -= (skip & 1) + (skip >> 1 & 1) +
58216+ (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
58217+ (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
58218+
58219+ if (vtx_size > vb_stride) {
58220+ DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
58221+ vtx_size, vb_stride);
58222+ return -EINVAL;
58223+ }
58224+
58225+ prim <<= 25;
58226+ while (n != 0) {
58227+ /* Can emit up to 255 vertices (85 triangles) at once. */
58228+ unsigned int count = n > 255 ? 255 : n;
58229+
58230+ /* Check indices */
58231+ for (i = 0; i < count; ++i) {
58232+ if (idx[i] > vb_size / (vb_stride*4)) {
58233+ DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
58234+ i, idx[i], vb_size / (vb_stride*4));
58235+ return -EINVAL;
58236+ }
58237+ }
58238+
58239+ if (reorder) {
58240+ /* Need to reorder vertices for correct flat
58241+ * shading while preserving the clock sense
58242+ * for correct culling. Only on Savage3D. */
58243+ int reorder[3] = {2, -1, -1};
58244+
58245+ BEGIN_DMA(count*vtx_size+1);
58246+ DMA_DRAW_PRIMITIVE(count, prim, skip);
58247+
58248+ for (i = 0; i < count; ++i) {
58249+ unsigned int j = idx[i + reorder[i % 3]];
58250+ DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
58251+ }
58252+
58253+ DMA_COMMIT();
58254+ } else {
58255+ BEGIN_DMA(count*vtx_size+1);
58256+ DMA_DRAW_PRIMITIVE(count, prim, skip);
58257+
58258+ for (i = 0; i < count; ++i) {
58259+ unsigned int j = idx[i];
58260+ DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
58261+ }
58262+
58263+ DMA_COMMIT();
58264+ }
58265+
58266+ idx += count;
58267+ n -= count;
58268+
58269+ prim |= BCI_CMD_DRAW_CONT;
58270+ }
58271+
58272+ return 0;
58273+}
58274+
58275+static int savage_dispatch_clear(drm_savage_private_t *dev_priv,
58276+ const drm_savage_cmd_header_t *cmd_header,
58277+ const drm_savage_cmd_header_t *data,
58278+ unsigned int nbox,
58279+ const struct drm_clip_rect *boxes)
58280+{
58281+ unsigned int flags = cmd_header->clear0.flags;
58282+ unsigned int clear_cmd;
58283+ unsigned int i, nbufs;
58284+ DMA_LOCALS;
58285+
58286+ if (nbox == 0)
58287+ return 0;
58288+
58289+ clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
58290+ BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW;
58291+ BCI_CMD_SET_ROP(clear_cmd,0xCC);
58292+
58293+ nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) +
58294+ ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0);
58295+ if (nbufs == 0)
58296+ return 0;
58297+
58298+ if (data->clear1.mask != 0xffffffff) {
58299+ /* set mask */
58300+ BEGIN_DMA(2);
58301+ DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1);
58302+ DMA_WRITE(data->clear1.mask);
58303+ DMA_COMMIT();
58304+ }
58305+ for (i = 0; i < nbox; ++i) {
58306+ unsigned int x, y, w, h;
58307+ unsigned int buf;
58308+
58309+ x = boxes[i].x1, y = boxes[i].y1;
58310+ w = boxes[i].x2 - boxes[i].x1;
58311+ h = boxes[i].y2 - boxes[i].y1;
58312+ BEGIN_DMA(nbufs*6);
58313+ for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) {
58314+ if (!(flags & buf))
58315+ continue;
58316+ DMA_WRITE(clear_cmd);
58317+ switch(buf) {
58318+ case SAVAGE_FRONT:
58319+ DMA_WRITE(dev_priv->front_offset);
58320+ DMA_WRITE(dev_priv->front_bd);
58321+ break;
58322+ case SAVAGE_BACK:
58323+ DMA_WRITE(dev_priv->back_offset);
58324+ DMA_WRITE(dev_priv->back_bd);
58325+ break;
58326+ case SAVAGE_DEPTH:
58327+ DMA_WRITE(dev_priv->depth_offset);
58328+ DMA_WRITE(dev_priv->depth_bd);
58329+ break;
58330+ }
58331+ DMA_WRITE(data->clear1.value);
58332+ DMA_WRITE(BCI_X_Y(x, y));
58333+ DMA_WRITE(BCI_W_H(w, h));
58334+ }
58335+ DMA_COMMIT();
58336+ }
58337+ if (data->clear1.mask != 0xffffffff) {
58338+ /* reset mask */
58339+ BEGIN_DMA(2);
58340+ DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1);
58341+ DMA_WRITE(0xffffffff);
58342+ DMA_COMMIT();
58343+ }
58344+
58345+ return 0;
58346+}
58347+
58348+static int savage_dispatch_swap(drm_savage_private_t *dev_priv,
58349+ unsigned int nbox, const struct drm_clip_rect *boxes)
58350+{
58351+ unsigned int swap_cmd;
58352+ unsigned int i;
58353+ DMA_LOCALS;
58354+
58355+ if (nbox == 0)
58356+ return 0;
58357+
58358+ swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
58359+ BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD;
58360+ BCI_CMD_SET_ROP(swap_cmd,0xCC);
58361+
58362+ for (i = 0; i < nbox; ++i) {
58363+ BEGIN_DMA(6);
58364+ DMA_WRITE(swap_cmd);
58365+ DMA_WRITE(dev_priv->back_offset);
58366+ DMA_WRITE(dev_priv->back_bd);
58367+ DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
58368+ DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
58369+ DMA_WRITE(BCI_W_H(boxes[i].x2-boxes[i].x1,
58370+ boxes[i].y2-boxes[i].y1));
58371+ DMA_COMMIT();
58372+ }
58373+
58374+ return 0;
58375+}
58376+
58377+static int savage_dispatch_draw(drm_savage_private_t *dev_priv,
58378+ const drm_savage_cmd_header_t *start,
58379+ const drm_savage_cmd_header_t *end,
58380+ const struct drm_buf *dmabuf,
58381+ const unsigned int *vtxbuf,
58382+ unsigned int vb_size, unsigned int vb_stride,
58383+ unsigned int nbox,
58384+ const struct drm_clip_rect *boxes)
58385+{
58386+ unsigned int i, j;
58387+ int ret;
58388+
58389+ for (i = 0; i < nbox; ++i) {
58390+ const drm_savage_cmd_header_t *cmdbuf;
58391+ dev_priv->emit_clip_rect(dev_priv, &boxes[i]);
58392+
58393+ cmdbuf = start;
58394+ while (cmdbuf < end) {
58395+ drm_savage_cmd_header_t cmd_header;
58396+ cmd_header = *cmdbuf;
58397+ cmdbuf++;
58398+ switch (cmd_header.cmd.cmd) {
58399+ case SAVAGE_CMD_DMA_PRIM:
58400+ ret = savage_dispatch_dma_prim(
58401+ dev_priv, &cmd_header, dmabuf);
58402+ break;
58403+ case SAVAGE_CMD_VB_PRIM:
58404+ ret = savage_dispatch_vb_prim(
58405+ dev_priv, &cmd_header,
58406+ vtxbuf, vb_size, vb_stride);
58407+ break;
58408+ case SAVAGE_CMD_DMA_IDX:
58409+ j = (cmd_header.idx.count + 3) / 4;
58410+ /* j was check in savage_bci_cmdbuf */
58411+ ret = savage_dispatch_dma_idx(dev_priv,
58412+ &cmd_header, (const uint16_t *)cmdbuf,
58413+ dmabuf);
58414+ cmdbuf += j;
58415+ break;
58416+ case SAVAGE_CMD_VB_IDX:
58417+ j = (cmd_header.idx.count + 3) / 4;
58418+ /* j was check in savage_bci_cmdbuf */
58419+ ret = savage_dispatch_vb_idx(dev_priv,
58420+ &cmd_header, (const uint16_t *)cmdbuf,
58421+ (const uint32_t *)vtxbuf, vb_size,
58422+ vb_stride);
58423+ cmdbuf += j;
58424+ break;
58425+ default:
58426+ /* What's the best return code? EFAULT? */
58427+ DRM_ERROR("IMPLEMENTATION ERROR: "
58428+ "non-drawing-command %d\n",
58429+ cmd_header.cmd.cmd);
58430+ return -EINVAL;
58431+ }
58432+
58433+ if (ret != 0)
58434+ return ret;
58435+ }
58436+ }
58437+
58438+ return 0;
58439+}
58440+
58441+int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv)
58442+{
58443+ drm_savage_private_t *dev_priv = dev->dev_private;
58444+ struct drm_device_dma *dma = dev->dma;
58445+ struct drm_buf *dmabuf;
58446+ drm_savage_cmdbuf_t *cmdbuf = data;
58447+ drm_savage_cmd_header_t *kcmd_addr = NULL;
58448+ drm_savage_cmd_header_t *first_draw_cmd;
58449+ unsigned int *kvb_addr = NULL;
58450+ struct drm_clip_rect *kbox_addr = NULL;
58451+ unsigned int i, j;
58452+ int ret = 0;
58453+
58454+ DRM_DEBUG("\n");
58455+
58456+ LOCK_TEST_WITH_RETURN(dev, file_priv);
58457+
58458+ if (dma && dma->buflist) {
58459+ if (cmdbuf->dma_idx > dma->buf_count) {
58460+ DRM_ERROR
58461+ ("vertex buffer index %u out of range (0-%u)\n",
58462+ cmdbuf->dma_idx, dma->buf_count-1);
58463+ return -EINVAL;
58464+ }
58465+ dmabuf = dma->buflist[cmdbuf->dma_idx];
58466+ } else {
58467+ dmabuf = NULL;
58468+ }
58469+
58470+ /* Copy the user buffers into kernel temporary areas. This hasn't been
58471+ * a performance loss compared to VERIFYAREA_READ/
58472+ * COPY_FROM_USER_UNCHECKED when done in other drivers, and is correct
58473+ * for locking on FreeBSD.
58474+ */
58475+ if (cmdbuf->size) {
58476+ kcmd_addr = drm_alloc(cmdbuf->size * 8, DRM_MEM_DRIVER);
58477+ if (kcmd_addr == NULL)
58478+ return -ENOMEM;
58479+
58480+ if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf->cmd_addr,
58481+ cmdbuf->size * 8))
58482+ {
58483+ drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER);
58484+ return -EFAULT;
58485+ }
58486+ cmdbuf->cmd_addr = kcmd_addr;
58487+ }
58488+ if (cmdbuf->vb_size) {
58489+ kvb_addr = drm_alloc(cmdbuf->vb_size, DRM_MEM_DRIVER);
58490+ if (kvb_addr == NULL) {
58491+ ret = -ENOMEM;
58492+ goto done;
58493+ }
58494+
58495+ if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf->vb_addr,
58496+ cmdbuf->vb_size)) {
58497+ ret = -EFAULT;
58498+ goto done;
58499+ }
58500+ cmdbuf->vb_addr = kvb_addr;
58501+ }
58502+ if (cmdbuf->nbox) {
58503+ kbox_addr = drm_alloc(cmdbuf->nbox *
58504+ sizeof(struct drm_clip_rect),
58505+ DRM_MEM_DRIVER);
58506+ if (kbox_addr == NULL) {
58507+ ret = -ENOMEM;
58508+ goto done;
58509+ }
58510+
58511+ if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf->box_addr,
58512+ cmdbuf->nbox *
58513+ sizeof(struct drm_clip_rect))) {
58514+ ret = -EFAULT;
58515+ goto done;
58516+ }
58517+ cmdbuf->box_addr = kbox_addr;
58518+ }
58519+
58520+ /* Make sure writes to DMA buffers are finished before sending
58521+ * DMA commands to the graphics hardware. */
58522+ DRM_MEMORYBARRIER();
58523+
58524+ /* Coming from user space. Don't know if the Xserver has
58525+ * emitted wait commands. Assuming the worst. */
58526+ dev_priv->waiting = 1;
58527+
58528+ i = 0;
58529+ first_draw_cmd = NULL;
58530+ while (i < cmdbuf->size) {
58531+ drm_savage_cmd_header_t cmd_header;
58532+ cmd_header = *(drm_savage_cmd_header_t *)cmdbuf->cmd_addr;
58533+ cmdbuf->cmd_addr++;
58534+ i++;
58535+
58536+ /* Group drawing commands with same state to minimize
58537+ * iterations over clip rects. */
58538+ j = 0;
58539+ switch (cmd_header.cmd.cmd) {
58540+ case SAVAGE_CMD_DMA_IDX:
58541+ case SAVAGE_CMD_VB_IDX:
58542+ j = (cmd_header.idx.count + 3) / 4;
58543+ if (i + j > cmdbuf->size) {
58544+ DRM_ERROR("indexed drawing command extends "
58545+ "beyond end of command buffer\n");
58546+ DMA_FLUSH();
58547+ return -EINVAL;
58548+ }
58549+ /* fall through */
58550+ case SAVAGE_CMD_DMA_PRIM:
58551+ case SAVAGE_CMD_VB_PRIM:
58552+ if (!first_draw_cmd)
58553+ first_draw_cmd = cmdbuf->cmd_addr-1;
58554+ cmdbuf->cmd_addr += j;
58555+ i += j;
58556+ break;
58557+ default:
58558+ if (first_draw_cmd) {
58559+ ret = savage_dispatch_draw (
58560+ dev_priv, first_draw_cmd,
58561+ cmdbuf->cmd_addr-1,
58562+ dmabuf, cmdbuf->vb_addr,
58563+ cmdbuf->vb_size,
58564+ cmdbuf->vb_stride,
58565+ cmdbuf->nbox, cmdbuf->box_addr);
58566+ if (ret != 0)
58567+ return ret;
58568+ first_draw_cmd = NULL;
58569+ }
58570+ }
58571+ if (first_draw_cmd)
58572+ continue;
58573+
58574+ switch (cmd_header.cmd.cmd) {
58575+ case SAVAGE_CMD_STATE:
58576+ j = (cmd_header.state.count + 1) / 2;
58577+ if (i + j > cmdbuf->size) {
58578+ DRM_ERROR("command SAVAGE_CMD_STATE extends "
58579+ "beyond end of command buffer\n");
58580+ DMA_FLUSH();
58581+ ret = -EINVAL;
58582+ goto done;
58583+ }
58584+ ret = savage_dispatch_state(dev_priv, &cmd_header,
58585+ (const uint32_t *)cmdbuf->cmd_addr);
58586+ cmdbuf->cmd_addr += j;
58587+ i += j;
58588+ break;
58589+ case SAVAGE_CMD_CLEAR:
58590+ if (i + 1 > cmdbuf->size) {
58591+ DRM_ERROR("command SAVAGE_CMD_CLEAR extends "
58592+ "beyond end of command buffer\n");
58593+ DMA_FLUSH();
58594+ ret = -EINVAL;
58595+ goto done;
58596+ }
58597+ ret = savage_dispatch_clear(dev_priv, &cmd_header,
58598+ cmdbuf->cmd_addr,
58599+ cmdbuf->nbox,
58600+ cmdbuf->box_addr);
58601+ cmdbuf->cmd_addr++;
58602+ i++;
58603+ break;
58604+ case SAVAGE_CMD_SWAP:
58605+ ret = savage_dispatch_swap(dev_priv, cmdbuf->nbox,
58606+ cmdbuf->box_addr);
58607+ break;
58608+ default:
58609+ DRM_ERROR("invalid command 0x%x\n",
58610+ cmd_header.cmd.cmd);
58611+ DMA_FLUSH();
58612+ ret = -EINVAL;
58613+ goto done;
58614+ }
58615+
58616+ if (ret != 0) {
58617+ DMA_FLUSH();
58618+ goto done;
58619+ }
58620+ }
58621+
58622+ if (first_draw_cmd) {
58623+ ret = savage_dispatch_draw (
58624+ dev_priv, first_draw_cmd, cmdbuf->cmd_addr, dmabuf,
58625+ cmdbuf->vb_addr, cmdbuf->vb_size, cmdbuf->vb_stride,
58626+ cmdbuf->nbox, cmdbuf->box_addr);
58627+ if (ret != 0) {
58628+ DMA_FLUSH();
58629+ goto done;
58630+ }
58631+ }
58632+
58633+ DMA_FLUSH();
58634+
58635+ if (dmabuf && cmdbuf->discard) {
58636+ drm_savage_buf_priv_t *buf_priv = dmabuf->dev_private;
58637+ uint16_t event;
58638+ event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
58639+ SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
58640+ savage_freelist_put(dev, dmabuf);
58641+ }
58642+
58643+done:
58644+ /* If we didn't need to allocate them, these'll be NULL */
58645+ drm_free(kcmd_addr, cmdbuf->size * 8, DRM_MEM_DRIVER);
58646+ drm_free(kvb_addr, cmdbuf->vb_size, DRM_MEM_DRIVER);
58647+ drm_free(kbox_addr, cmdbuf->nbox * sizeof(struct drm_clip_rect),
58648+ DRM_MEM_DRIVER);
58649+
58650+ return ret;
58651+}
58652Index: git/shared-core/sis_drv.h
58653===================================================================
58654--- /dev/null 1970-01-01 00:00:00.000000000 +0000
58655+++ git/shared-core/sis_drv.h 2008-12-12 17:35:22.000000000 +0000
58656@@ -0,0 +1,92 @@
58657+/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
58658+/*
58659+ * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
58660+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
58661+ * All rights reserved.
58662+ *
58663+ * Permission is hereby granted, free of charge, to any person obtaining a
58664+ * copy of this software and associated documentation files (the "Software"),
58665+ * to deal in the Software without restriction, including without limitation
58666+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
58667+ * and/or sell copies of the Software, and to permit persons to whom the
58668+ * Software is furnished to do so, subject to the following conditions:
58669+ *
58670+ * The above copyright notice and this permission notice (including the next
58671+ * paragraph) shall be included in all copies or substantial portions of the
58672+ * Software.
58673+ *
58674+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
58675+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
58676+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58677+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
58678+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
58679+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
58680+ * DEALINGS IN THE SOFTWARE.
58681+ *
58682+ */
58683+
58684+#ifndef _SIS_DRV_H_
58685+#define _SIS_DRV_H_
58686+
58687+/* General customization:
58688+ */
58689+
58690+#define DRIVER_AUTHOR "SIS, Tungsten Graphics"
58691+#define DRIVER_NAME "sis"
58692+#define DRIVER_DESC "SIS 300/630/540 and XGI V3XE/V5/V8"
58693+#define DRIVER_DATE "20070626"
58694+#define DRIVER_MAJOR 1
58695+#define DRIVER_MINOR 3
58696+#define DRIVER_PATCHLEVEL 0
58697+
58698+enum sis_family {
58699+ SIS_OTHER = 0,
58700+ SIS_CHIP_315 = 1,
58701+};
58702+
58703+#if defined(__linux__)
58704+#define SIS_HAVE_CORE_MM
58705+#endif
58706+
58707+#ifdef SIS_HAVE_CORE_MM
58708+#include "drm_sman.h"
58709+
58710+#define SIS_BASE (dev_priv->mmio)
58711+#define SIS_READ(reg) DRM_READ32(SIS_BASE, reg);
58712+#define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val);
58713+
58714+typedef struct drm_sis_private {
58715+ drm_local_map_t *mmio;
58716+ unsigned int idle_fault;
58717+ struct drm_sman sman;
58718+ unsigned int chipset;
58719+ int vram_initialized;
58720+ int agp_initialized;
58721+ unsigned long vram_offset;
58722+ unsigned long agp_offset;
58723+} drm_sis_private_t;
58724+
58725+extern int sis_idle(struct drm_device *dev);
58726+extern void sis_reclaim_buffers_locked(struct drm_device *dev,
58727+ struct drm_file *file_priv);
58728+extern void sis_lastclose(struct drm_device *dev);
58729+
58730+#else
58731+#include "sis_ds.h"
58732+
58733+typedef struct drm_sis_private {
58734+ memHeap_t *AGPHeap;
58735+ memHeap_t *FBHeap;
58736+} drm_sis_private_t;
58737+
58738+extern int sis_init_context(struct drm_device * dev, int context);
58739+extern int sis_final_context(struct drm_device * dev, int context);
58740+
58741+#endif
58742+
58743+
58744+
58745+extern struct drm_ioctl_desc sis_ioctls[];
58746+extern int sis_max_ioctl;
58747+
58748+#endif
58749Index: git/shared-core/sis_ds.c
58750===================================================================
58751--- /dev/null 1970-01-01 00:00:00.000000000 +0000
58752+++ git/shared-core/sis_ds.c 2008-12-12 17:35:22.000000000 +0000
58753@@ -0,0 +1,299 @@
58754+/* sis_ds.c -- Private header for Direct Rendering Manager -*- linux-c -*-
58755+ * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw
58756+ *
58757+ * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
58758+ * All rights reserved.
58759+ *
58760+ * Permission is hereby granted, free of charge, to any person obtaining a
58761+ * copy of this software and associated documentation files (the "Software"),
58762+ * to deal in the Software without restriction, including without limitation
58763+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
58764+ * and/or sell copies of the Software, and to permit persons to whom the
58765+ * Software is furnished to do so, subject to the following conditions:
58766+ *
58767+ * The above copyright notice and this permission notice (including the next
58768+ * paragraph) shall be included in all copies or substantial portions of the
58769+ * Software.
58770+ *
58771+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
58772+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
58773+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58774+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
58775+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
58776+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
58777+ * DEALINGS IN THE SOFTWARE.
58778+ *
58779+ * Authors:
58780+ * Sung-Ching Lin <sclin@sis.com.tw>
58781+ *
58782+ */
58783+
58784+#include "drmP.h"
58785+#include "drm.h"
58786+#include "sis_ds.h"
58787+
58788+/* Set Data Structure, not check repeated value
58789+ * temporarily used
58790+ */
58791+
58792+set_t *setInit(void)
58793+{
58794+ int i;
58795+ set_t *set;
58796+
58797+ set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
58798+ if (set != NULL) {
58799+ for (i = 0; i < SET_SIZE; i++) {
58800+ set->list[i].free_next = i + 1;
58801+ set->list[i].alloc_next = -1;
58802+ }
58803+ set->list[SET_SIZE - 1].free_next = -1;
58804+ set->free = 0;
58805+ set->alloc = -1;
58806+ set->trace = -1;
58807+ }
58808+ return set;
58809+}
58810+
58811+int setAdd(set_t * set, ITEM_TYPE item)
58812+{
58813+ int free = set->free;
58814+
58815+ if (free != -1) {
58816+ set->list[free].val = item;
58817+ set->free = set->list[free].free_next;
58818+ } else {
58819+ return 0;
58820+ }
58821+
58822+ set->list[free].alloc_next = set->alloc;
58823+ set->alloc = free;
58824+ set->list[free].free_next = -1;
58825+
58826+ return 1;
58827+}
58828+
58829+int setDel(set_t * set, ITEM_TYPE item)
58830+{
58831+ int alloc = set->alloc;
58832+ int prev = -1;
58833+
58834+ while (alloc != -1) {
58835+ if (set->list[alloc].val == item) {
58836+ if (prev != -1)
58837+ set->list[prev].alloc_next =
58838+ set->list[alloc].alloc_next;
58839+ else
58840+ set->alloc = set->list[alloc].alloc_next;
58841+ break;
58842+ }
58843+ prev = alloc;
58844+ alloc = set->list[alloc].alloc_next;
58845+ }
58846+
58847+ if (alloc == -1)
58848+ return 0;
58849+
58850+ set->list[alloc].free_next = set->free;
58851+ set->free = alloc;
58852+ set->list[alloc].alloc_next = -1;
58853+
58854+ return 1;
58855+}
58856+
58857+/* setFirst -> setAdd -> setNext is wrong */
58858+
58859+int setFirst(set_t * set, ITEM_TYPE * item)
58860+{
58861+ if (set->alloc == -1)
58862+ return 0;
58863+
58864+ *item = set->list[set->alloc].val;
58865+ set->trace = set->list[set->alloc].alloc_next;
58866+
58867+ return 1;
58868+}
58869+
58870+int setNext(set_t * set, ITEM_TYPE * item)
58871+{
58872+ if (set->trace == -1)
58873+ return 0;
58874+
58875+ *item = set->list[set->trace].val;
58876+ set->trace = set->list[set->trace].alloc_next;
58877+
58878+ return 1;
58879+}
58880+
58881+int setDestroy(set_t * set)
58882+{
58883+ drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
58884+
58885+ return 1;
58886+}
58887+
58888+/*
58889+ * GLX Hardware Device Driver common code
58890+ * Copyright (C) 1999 Wittawat Yamwong
58891+ *
58892+ * Permission is hereby granted, free of charge, to any person obtaining a
58893+ * copy of this software and associated documentation files (the "Software"),
58894+ * to deal in the Software without restriction, including without limitation
58895+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
58896+ * and/or sell copies of the Software, and to permit persons to whom the
58897+ * Software is furnished to do so, subject to the following conditions:
58898+ *
58899+ * The above copyright notice and this permission notice shall be included
58900+ * in all copies or substantial portions of the Software.
58901+ *
58902+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
58903+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
58904+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58905+ * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
58906+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
58907+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
58908+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
58909+ *
58910+ */
58911+
58912+#define ISFREE(bptr) ((bptr)->free)
58913+
58914+memHeap_t *mmInit(int ofs, int size)
58915+{
58916+ PMemBlock blocks;
58917+
58918+ if (size <= 0)
58919+ return NULL;
58920+
58921+ blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
58922+ if (blocks != NULL) {
58923+ blocks->ofs = ofs;
58924+ blocks->size = size;
58925+ blocks->free = 1;
58926+ return (memHeap_t *) blocks;
58927+ } else
58928+ return NULL;
58929+}
58930+
58931+/* Checks if a pointer 'b' is part of the heap 'heap' */
58932+int mmBlockInHeap(memHeap_t * heap, PMemBlock b)
58933+{
58934+ TMemBlock *p;
58935+
58936+ if (heap == NULL || b == NULL)
58937+ return 0;
58938+
58939+ p = heap;
58940+ while (p != NULL && p != b) {
58941+ p = p->next;
58942+ }
58943+ if (p == b)
58944+ return 1;
58945+ else
58946+ return 0;
58947+}
58948+
58949+static TMemBlock *SliceBlock(TMemBlock * p,
58950+ int startofs, int size,
58951+ int reserved, int alignment)
58952+{
58953+ TMemBlock *newblock;
58954+
58955+ /* break left */
58956+ if (startofs > p->ofs) {
58957+ newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
58958+ DRM_MEM_DRIVER);
58959+ newblock->ofs = startofs;
58960+ newblock->size = p->size - (startofs - p->ofs);
58961+ newblock->free = 1;
58962+ newblock->next = p->next;
58963+ p->size -= newblock->size;
58964+ p->next = newblock;
58965+ p = newblock;
58966+ }
58967+
58968+ /* break right */
58969+ if (size < p->size) {
58970+ newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
58971+ DRM_MEM_DRIVER);
58972+ newblock->ofs = startofs + size;
58973+ newblock->size = p->size - size;
58974+ newblock->free = 1;
58975+ newblock->next = p->next;
58976+ p->size = size;
58977+ p->next = newblock;
58978+ }
58979+
58980+ /* p = middle block */
58981+ p->align = alignment;
58982+ p->free = 0;
58983+ p->reserved = reserved;
58984+ return p;
58985+}
58986+
58987+PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch)
58988+{
58989+ int mask, startofs, endofs;
58990+ TMemBlock *p;
58991+
58992+ if (heap == NULL || align2 < 0 || size <= 0)
58993+ return NULL;
58994+
58995+ mask = (1 << align2) - 1;
58996+ startofs = 0;
58997+ p = (TMemBlock *) heap;
58998+ while (p != NULL) {
58999+ if (ISFREE(p)) {
59000+ startofs = (p->ofs + mask) & ~mask;
59001+ if (startofs < startSearch) {
59002+ startofs = startSearch;
59003+ }
59004+ endofs = startofs + size;
59005+ if (endofs <= (p->ofs + p->size))
59006+ break;
59007+ }
59008+ p = p->next;
59009+ }
59010+ if (p == NULL)
59011+ return NULL;
59012+ p = SliceBlock(p, startofs, size, 0, mask + 1);
59013+ p->heap = heap;
59014+ return p;
59015+}
59016+
59017+static __inline__ int Join2Blocks(TMemBlock * p)
59018+{
59019+ if (p->free && p->next && p->next->free) {
59020+ TMemBlock *q = p->next;
59021+ p->size += q->size;
59022+ p->next = q->next;
59023+ drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER);
59024+ return 1;
59025+ }
59026+ return 0;
59027+}
59028+
59029+int mmFreeMem(PMemBlock b)
59030+{
59031+ TMemBlock *p, *prev;
59032+
59033+ if (b == NULL)
59034+ return 0;
59035+ if (b->heap == NULL)
59036+ return -1;
59037+
59038+ p = b->heap;
59039+ prev = NULL;
59040+ while (p != NULL && p != b) {
59041+ prev = p;
59042+ p = p->next;
59043+ }
59044+ if (p == NULL || p->free || p->reserved)
59045+ return -1;
59046+
59047+ p->free = 1;
59048+ Join2Blocks(p);
59049+ if (prev)
59050+ Join2Blocks(prev);
59051+ return 0;
59052+}
59053Index: git/shared-core/sis_ds.h
59054===================================================================
59055--- /dev/null 1970-01-01 00:00:00.000000000 +0000
59056+++ git/shared-core/sis_ds.h 2008-12-12 17:35:22.000000000 +0000
59057@@ -0,0 +1,146 @@
59058+/* sis_ds.h -- Private header for Direct Rendering Manager -*- linux-c -*-
59059+ * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw
59060+ */
59061+/*
59062+ * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
59063+ * All rights reserved.
59064+ *
59065+ * Permission is hereby granted, free of charge, to any person obtaining a
59066+ * copy of this software and associated documentation files (the "Software"),
59067+ * to deal in the Software without restriction, including without limitation
59068+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
59069+ * and/or sell copies of the Software, and to permit persons to whom the
59070+ * Software is furnished to do so, subject to the following conditions:
59071+ *
59072+ * The above copyright notice and this permission notice (including the next
59073+ * paragraph) shall be included in all copies or substantial portions of the
59074+ * Software.
59075+ *
59076+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
59077+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
59078+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59079+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
59080+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
59081+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
59082+ * DEALINGS IN THE SOFTWARE.
59083+ *
59084+ * Authors:
59085+ * Sung-Ching Lin <sclin@sis.com.tw>
59086+ *
59087+ */
59088+
59089+#ifndef __SIS_DS_H__
59090+#define __SIS_DS_H__
59091+
59092+/* Set Data Structure */
59093+
59094+#define SET_SIZE 5000
59095+
59096+typedef unsigned long ITEM_TYPE;
59097+
59098+typedef struct {
59099+ ITEM_TYPE val;
59100+ int alloc_next, free_next;
59101+} list_item_t;
59102+
59103+typedef struct {
59104+ int alloc;
59105+ int free;
59106+ int trace;
59107+ list_item_t list[SET_SIZE];
59108+} set_t;
59109+
59110+set_t *setInit(void);
59111+int setAdd(set_t * set, ITEM_TYPE item);
59112+int setDel(set_t * set, ITEM_TYPE item);
59113+int setFirst(set_t * set, ITEM_TYPE * item);
59114+int setNext(set_t * set, ITEM_TYPE * item);
59115+int setDestroy(set_t * set);
59116+
59117+/*
59118+ * GLX Hardware Device Driver common code
59119+ * Copyright (C) 1999 Wittawat Yamwong
59120+ *
59121+ * Permission is hereby granted, free of charge, to any person obtaining a
59122+ * copy of this software and associated documentation files (the "Software"),
59123+ * to deal in the Software without restriction, including without limitation
59124+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
59125+ * and/or sell copies of the Software, and to permit persons to whom the
59126+ * Software is furnished to do so, subject to the following conditions:
59127+ *
59128+ * The above copyright notice and this permission notice shall be included
59129+ * in all copies or substantial portions of the Software.
59130+ *
59131+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
59132+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
59133+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59134+ * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
59135+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
59136+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
59137+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
59138+ *
59139+ */
59140+
59141+struct mem_block_t {
59142+ struct mem_block_t *next;
59143+ struct mem_block_t *heap;
59144+ int ofs, size;
59145+ int align;
59146+ unsigned int free:1;
59147+ unsigned int reserved:1;
59148+};
59149+typedef struct mem_block_t TMemBlock;
59150+typedef struct mem_block_t *PMemBlock;
59151+
59152+/* a heap is just the first block in a chain */
59153+typedef struct mem_block_t memHeap_t;
59154+
59155+static __inline__ int mmBlockSize(PMemBlock b)
59156+{
59157+ return b->size;
59158+}
59159+
59160+static __inline__ int mmOffset(PMemBlock b)
59161+{
59162+ return b->ofs;
59163+}
59164+
59165+static __inline__ void mmMarkReserved(PMemBlock b)
59166+{
59167+ b->reserved = 1;
59168+}
59169+
59170+/*
59171+ * input: total size in bytes
59172+ * return: a heap pointer if OK, NULL if error
59173+ */
59174+memHeap_t *mmInit(int ofs, int size);
59175+
59176+/*
59177+ * Allocate 'size' bytes with 2^align2 bytes alignment,
59178+ * restrict the search to free memory after 'startSearch'
59179+ * depth and back buffers should be in different 4mb banks
59180+ * to get better page hits if possible
59181+ * input: size = size of block
59182+ * align2 = 2^align2 bytes alignment
59183+ * startSearch = linear offset from start of heap to begin search
59184+ * return: pointer to the allocated block, 0 if error
59185+ */
59186+PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch);
59187+
59188+/*
59189+ * Returns 1 if the block 'b' is part of the heap 'heap'
59190+ */
59191+int mmBlockInHeap(PMemBlock heap, PMemBlock b);
59192+
59193+/*
59194+ * Free block starts at offset
59195+ * input: pointer to a block
59196+ * return: 0 if OK, -1 if error
59197+ */
59198+int mmFreeMem(PMemBlock b);
59199+
59200+/* For debuging purpose. */
59201+void mmDumpMemInfo(memHeap_t * mmInit);
59202+
59203+#endif /* __SIS_DS_H__ */
59204Index: git/shared-core/sis_mm.c
59205===================================================================
59206--- /dev/null 1970-01-01 00:00:00.000000000 +0000
59207+++ git/shared-core/sis_mm.c 2008-12-12 17:35:22.000000000 +0000
59208@@ -0,0 +1,386 @@
59209+/* sis_mm.c -- Private header for Direct Rendering Manager -*- linux-c -*-
59210+ * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw
59211+ *
59212+ * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
59213+ * All rights reserved.
59214+ *
59215+ * Permission is hereby granted, free of charge, to any person obtaining a
59216+ * copy of this software and associated documentation files (the "Software"),
59217+ * to deal in the Software without restriction, including without limitation
59218+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
59219+ * and/or sell copies of the Software, and to permit persons to whom the
59220+ * Software is furnished to do so, subject to the following conditions:
59221+ *
59222+ * The above copyright notice and this permission notice (including the next
59223+ * paragraph) shall be included in all copies or substantial portions of the
59224+ * Software.
59225+ *
59226+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
59227+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
59228+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59229+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
59230+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
59231+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
59232+ * DEALINGS IN THE SOFTWARE.
59233+ *
59234+ * Authors:
59235+ * Sung-Ching Lin <sclin@sis.com.tw>
59236+ *
59237+ */
59238+
59239+#if defined(__linux__) && defined(CONFIG_FB_SIS)
59240+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
59241+#include <video/sisfb.h>
59242+#else
59243+#include <linux/sisfb.h>
59244+#endif
59245+#endif
59246+#include "drmP.h"
59247+#include "sis_drm.h"
59248+#include "sis_drv.h"
59249+#include "sis_ds.h"
59250+
59251+#define MAX_CONTEXT 100
59252+#define VIDEO_TYPE 0
59253+#define AGP_TYPE 1
59254+
59255+typedef struct {
59256+ int used;
59257+ int context;
59258+ set_t *sets[2]; /* 0 for video, 1 for AGP */
59259+} sis_context_t;
59260+
59261+static sis_context_t global_ppriv[MAX_CONTEXT];
59262+
59263+static int add_alloc_set(int context, int type, unsigned int val)
59264+{
59265+ int i, retval = 0;
59266+
59267+ for (i = 0; i < MAX_CONTEXT; i++) {
59268+ if (global_ppriv[i].used && global_ppriv[i].context == context) {
59269+ retval = setAdd(global_ppriv[i].sets[type], val);
59270+ break;
59271+ }
59272+ }
59273+ return retval;
59274+}
59275+
59276+static int del_alloc_set(int context, int type, unsigned int val)
59277+{
59278+ int i, retval = 0;
59279+
59280+ for (i = 0; i < MAX_CONTEXT; i++) {
59281+ if (global_ppriv[i].used && global_ppriv[i].context == context) {
59282+ retval = setDel(global_ppriv[i].sets[type], val);
59283+ break;
59284+ }
59285+ }
59286+ return retval;
59287+}
59288+
59289+/* fb management via fb device */
59290+#if defined(__linux__) && defined(CONFIG_FB_SIS)
59291+
59292+static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
59293+{
59294+ return 0;
59295+}
59296+
59297+static int sis_fb_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
59298+{
59299+ drm_sis_mem_t *fb = data;
59300+ struct sis_memreq req;
59301+ int retval = 0;
59302+
59303+ req.size = fb->size;
59304+ sis_malloc(&req);
59305+ if (req.offset) {
59306+ /* TODO */
59307+ fb->offset = req.offset;
59308+ fb->free = req.offset;
59309+ if (!add_alloc_set(fb->context, VIDEO_TYPE, fb->free)) {
59310+ DRM_DEBUG("adding to allocation set fails\n");
59311+ sis_free(req.offset);
59312+ retval = -EINVAL;
59313+ }
59314+ } else {
59315+ fb->offset = 0;
59316+ fb->size = 0;
59317+ fb->free = 0;
59318+ }
59319+
59320+ DRM_DEBUG("alloc fb, size = %d, offset = %ld\n", fb->size, req.offset);
59321+
59322+ return retval;
59323+}
59324+
59325+static int sis_fb_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
59326+{
59327+ drm_sis_mem_t fb;
59328+ int retval = 0;
59329+
59330+ if (!fb->free)
59331+ return -EINVAL;
59332+
59333+ if (!del_alloc_set(fb->context, VIDEO_TYPE, fb->free))
59334+ retval = -EINVAL;
59335+ sis_free(fb->free);
59336+
59337+ DRM_DEBUG("free fb, offset = 0x%lx\n", fb->free);
59338+
59339+ return retval;
59340+}
59341+
59342+#else
59343+
59344+/* Called by the X Server to initialize the FB heap. Allocations will fail
59345+ * unless this is called. Offset is the beginning of the heap from the
59346+ * framebuffer offset (MaxXFBMem in XFree86).
59347+ *
59348+ * Memory layout according to Thomas Winischofer:
59349+ * |------------------|DDDDDDDDDDDDDDDDDDDDDDDDDDDDD|HHHH|CCCCCCCCCCC|
59350+ *
59351+ * X driver/sisfb HW- Command-
59352+ * framebuffer memory DRI heap Cursor queue
59353+ */
59354+static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
59355+{
59356+ drm_sis_private_t *dev_priv = dev->dev_private;
59357+ drm_sis_fb_t *fb = data;
59358+
59359+ if (dev_priv == NULL) {
59360+ dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
59361+ DRM_MEM_DRIVER);
59362+ dev_priv = dev->dev_private;
59363+ if (dev_priv == NULL)
59364+ return ENOMEM;
59365+ }
59366+
59367+ if (dev_priv->FBHeap != NULL)
59368+ return -EINVAL;
59369+
59370+ dev_priv->FBHeap = mmInit(fb->offset, fb->size);
59371+
59372+ DRM_DEBUG("offset = %u, size = %u", fb->offset, fb->size);
59373+
59374+ return 0;
59375+}
59376+
59377+static int sis_fb_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
59378+{
59379+ drm_sis_private_t *dev_priv = dev->dev_private;
59380+ drm_sis_mem_t *fb = data;
59381+ PMemBlock block;
59382+ int retval = 0;
59383+
59384+ if (dev_priv == NULL || dev_priv->FBHeap == NULL)
59385+ return -EINVAL;
59386+
59387+ block = mmAllocMem(dev_priv->FBHeap, fb->size, 0, 0);
59388+ if (block) {
59389+ /* TODO */
59390+ fb->offset = block->ofs;
59391+ fb->free = (unsigned long)block;
59392+ if (!add_alloc_set(fb->context, VIDEO_TYPE, fb->free)) {
59393+ DRM_DEBUG("adding to allocation set fails\n");
59394+ mmFreeMem((PMemBlock) fb->free);
59395+ retval = -EINVAL;
59396+ }
59397+ } else {
59398+ fb->offset = 0;
59399+ fb->size = 0;
59400+ fb->free = 0;
59401+ }
59402+
59403+ DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb->size, fb->offset);
59404+
59405+ return retval;
59406+}
59407+
59408+static int sis_fb_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
59409+{
59410+ drm_sis_private_t *dev_priv = dev->dev_private;
59411+ drm_sis_mem_t *fb = data;
59412+
59413+ if (dev_priv == NULL || dev_priv->FBHeap == NULL)
59414+ return -EINVAL;
59415+
59416+ if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb->free))
59417+ return -EINVAL;
59418+
59419+ if (!del_alloc_set(fb->context, VIDEO_TYPE, fb->free))
59420+ return -EINVAL;
59421+ mmFreeMem((PMemBlock) fb->free);
59422+
59423+ DRM_DEBUG("free fb, free = 0x%lx\n", fb->free);
59424+
59425+ return 0;
59426+}
59427+
59428+#endif
59429+
59430+/* agp memory management */
59431+
59432+static int sis_ioctl_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
59433+{
59434+ drm_sis_private_t *dev_priv = dev->dev_private;
59435+ drm_sis_agp_t *agp = data;
59436+
59437+ if (dev_priv == NULL) {
59438+ dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
59439+ DRM_MEM_DRIVER);
59440+ dev_priv = dev->dev_private;
59441+ if (dev_priv == NULL)
59442+ return ENOMEM;
59443+ }
59444+
59445+ if (dev_priv->AGPHeap != NULL)
59446+ return -EINVAL;
59447+
59448+ dev_priv->AGPHeap = mmInit(agp->offset, agp->size);
59449+
59450+ DRM_DEBUG("offset = %u, size = %u", agp->offset, agp->size);
59451+
59452+ return 0;
59453+}
59454+
59455+static int sis_ioctl_agp_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
59456+{
59457+ drm_sis_private_t *dev_priv = dev->dev_private;
59458+ drm_sis_mem_t *agp = data;
59459+ PMemBlock block;
59460+ int retval = 0;
59461+
59462+ if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
59463+ return -EINVAL;
59464+
59465+ block = mmAllocMem(dev_priv->AGPHeap, agp->size, 0, 0);
59466+ if (block) {
59467+ /* TODO */
59468+ agp->offset = block->ofs;
59469+ agp->free = (unsigned long)block;
59470+ if (!add_alloc_set(agp->context, AGP_TYPE, agp->free)) {
59471+ DRM_DEBUG("adding to allocation set fails\n");
59472+ mmFreeMem((PMemBlock) agp->free);
59473+ retval = -1;
59474+ }
59475+ } else {
59476+ agp->offset = 0;
59477+ agp->size = 0;
59478+ agp->free = 0;
59479+ }
59480+
59481+ DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp->size,
59482+ agp->offset);
59483+
59484+ return retval;
59485+}
59486+
59487+static int sis_ioctl_agp_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
59488+{
59489+ drm_sis_private_t *dev_priv = dev->dev_private;
59490+ drm_sis_mem_t *agp = data;
59491+
59492+ if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
59493+ return -EINVAL;
59494+
59495+ if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp->free))
59496+ return -EINVAL;
59497+
59498+ mmFreeMem((PMemBlock) agp->free);
59499+ if (!del_alloc_set(agp->context, AGP_TYPE, agp->free))
59500+ return -EINVAL;
59501+
59502+ DRM_DEBUG("free agp, free = 0x%lx\n", agp->free);
59503+
59504+ return 0;
59505+}
59506+
59507+int sis_init_context(struct drm_device *dev, int context)
59508+{
59509+ int i;
59510+
59511+ for (i = 0; i < MAX_CONTEXT; i++) {
59512+ if (global_ppriv[i].used &&
59513+ (global_ppriv[i].context == context))
59514+ break;
59515+ }
59516+
59517+ if (i >= MAX_CONTEXT) {
59518+ for (i = 0; i < MAX_CONTEXT; i++) {
59519+ if (!global_ppriv[i].used) {
59520+ global_ppriv[i].context = context;
59521+ global_ppriv[i].used = 1;
59522+ global_ppriv[i].sets[0] = setInit();
59523+ global_ppriv[i].sets[1] = setInit();
59524+ DRM_DEBUG("init allocation set, socket=%d, "
59525+ "context = %d\n", i, context);
59526+ break;
59527+ }
59528+ }
59529+ if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
59530+ (global_ppriv[i].sets[1] == NULL)) {
59531+ return 0;
59532+ }
59533+ }
59534+
59535+ return 1;
59536+}
59537+
59538+int sis_final_context(struct drm_device *dev, int context)
59539+{
59540+ int i;
59541+
59542+ for (i = 0; i < MAX_CONTEXT; i++) {
59543+ if (global_ppriv[i].used &&
59544+ (global_ppriv[i].context == context))
59545+ break;
59546+ }
59547+
59548+ if (i < MAX_CONTEXT) {
59549+ set_t *set;
59550+ ITEM_TYPE item;
59551+ int retval;
59552+
59553+ DRM_DEBUG("find socket %d, context = %d\n", i, context);
59554+
59555+ /* Video Memory */
59556+ set = global_ppriv[i].sets[0];
59557+ retval = setFirst(set, &item);
59558+ while (retval) {
59559+ DRM_DEBUG("free video memory 0x%lx\n", item);
59560+#if defined(__linux__) && defined(CONFIG_FB_SIS)
59561+ sis_free(item);
59562+#else
59563+ mmFreeMem((PMemBlock) item);
59564+#endif
59565+ retval = setNext(set, &item);
59566+ }
59567+ setDestroy(set);
59568+
59569+ /* AGP Memory */
59570+ set = global_ppriv[i].sets[1];
59571+ retval = setFirst(set, &item);
59572+ while (retval) {
59573+ DRM_DEBUG("free agp memory 0x%lx\n", item);
59574+ mmFreeMem((PMemBlock) item);
59575+ retval = setNext(set, &item);
59576+ }
59577+ setDestroy(set);
59578+
59579+ global_ppriv[i].used = 0;
59580+ }
59581+
59582+ return 1;
59583+}
59584+
59585+drm_ioctl_desc_t sis_ioctls[] = {
59586+ DRM_IOCTL_DEF(DRM_SIS_FB_ALLOC, sis_fb_alloc, DRM_AUTH),
59587+ DRM_IOCTL_DEF(DRM_SIS_FB_FREE, sis_fb_free, DRM_AUTH),
59588+ DRM_IOCTL_DEF(DRM_SIS_AGP_INIT, sis_ioctl_agp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
59589+ DRM_IOCTL_DEF(DRM_SIS_AGP_ALLOC, sis_ioctl_agp_alloc, DRM_AUTH),
59590+ DRM_IOCTL_DEF(DRM_SIS_AGP_FREE, sis_ioctl_agp_free, DRM_AUTH),
59591+ DRM_IOCTL_DEF(DRM_SIS_FB_INIT, sis_fb_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)
59592+};
59593+
59594+int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls);
59595Index: git/shared-core/tdfx_drv.h
59596===================================================================
59597--- /dev/null 1970-01-01 00:00:00.000000000 +0000
59598+++ git/shared-core/tdfx_drv.h 2008-12-12 17:35:22.000000000 +0000
59599@@ -0,0 +1,47 @@
59600+/* tdfx.h -- 3dfx DRM template customization -*- linux-c -*-
59601+ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
59602+ */
59603+/*
59604+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
59605+ * All Rights Reserved.
59606+ *
59607+ * Permission is hereby granted, free of charge, to any person obtaining a
59608+ * copy of this software and associated documentation files (the "Software"),
59609+ * to deal in the Software without restriction, including without limitation
59610+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
59611+ * and/or sell copies of the Software, and to permit persons to whom the
59612+ * Software is furnished to do so, subject to the following conditions:
59613+ *
59614+ * The above copyright notice and this permission notice (including the next
59615+ * paragraph) shall be included in all copies or substantial portions of the
59616+ * Software.
59617+ *
59618+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
59619+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
59620+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
59621+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
59622+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
59623+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
59624+ * OTHER DEALINGS IN THE SOFTWARE.
59625+ *
59626+ * Authors:
59627+ * Gareth Hughes <gareth@valinux.com>
59628+ */
59629+
59630+#ifndef __TDFX_H__
59631+#define __TDFX_H__
59632+
59633+/* General customization:
59634+ */
59635+
59636+#define DRIVER_AUTHOR "VA Linux Systems Inc."
59637+
59638+#define DRIVER_NAME "tdfx"
59639+#define DRIVER_DESC "3dfx Banshee/Voodoo3+"
59640+#define DRIVER_DATE "20010216"
59641+
59642+#define DRIVER_MAJOR 1
59643+#define DRIVER_MINOR 0
59644+#define DRIVER_PATCHLEVEL 0
59645+
59646+#endif
59647Index: git/shared-core/via_dma.c
59648===================================================================
59649--- /dev/null 1970-01-01 00:00:00.000000000 +0000
59650+++ git/shared-core/via_dma.c 2008-12-12 17:35:22.000000000 +0000
59651@@ -0,0 +1,719 @@
59652+/* via_dma.c -- DMA support for the VIA Unichrome/Pro
59653+ *
59654+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
59655+ * All Rights Reserved.
59656+ *
59657+ * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
59658+ * All Rights Reserved.
59659+ *
59660+ * Copyright 2004 The Unichrome project.
59661+ * All Rights Reserved.
59662+ *
59663+ * Permission is hereby granted, free of charge, to any person obtaining a
59664+ * copy of this software and associated documentation files (the "Software"),
59665+ * to deal in the Software without restriction, including without limitation
59666+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
59667+ * and/or sell copies of the Software, and to permit persons to whom the
59668+ * Software is furnished to do so, subject to the following conditions:
59669+ *
59670+ * The above copyright notice and this permission notice (including the
59671+ * next paragraph) shall be included in all copies or substantial portions
59672+ * of the Software.
59673+ *
59674+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
59675+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
59676+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
59677+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
59678+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
59679+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
59680+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
59681+ *
59682+ * Authors:
59683+ * Tungsten Graphics,
59684+ * Erdi Chen,
59685+ * Thomas Hellstrom.
59686+ */
59687+
59688+#include "drmP.h"
59689+#include "drm.h"
59690+#include "via_drm.h"
59691+#include "via_drv.h"
59692+#include "via_3d_reg.h"
59693+
59694+#define SetReg2DAGP(nReg, nData) { \
59695+ *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
59696+ *((uint32_t *)(vb) + 1) = (nData); \
59697+ vb = ((uint32_t *)vb) + 2; \
59698+ dev_priv->dma_low +=8; \
59699+}
59700+
59701+#define via_flush_write_combine() DRM_MEMORYBARRIER()
59702+
59703+#define VIA_OUT_RING_QW(w1,w2) \
59704+ *vb++ = (w1); \
59705+ *vb++ = (w2); \
59706+ dev_priv->dma_low += 8;
59707+
59708+static void via_cmdbuf_start(drm_via_private_t * dev_priv);
59709+static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
59710+static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
59711+static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
59712+static int via_wait_idle(drm_via_private_t * dev_priv);
59713+static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
59714+
59715+
59716+/*
59717+ * Free space in command buffer.
59718+ */
59719+
59720+static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
59721+{
59722+ uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
59723+ uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
59724+
59725+ return ((hw_addr <= dev_priv->dma_low) ?
59726+ (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
59727+ (hw_addr - dev_priv->dma_low));
59728+}
59729+
59730+/*
59731+ * How much does the command regulator lag behind?
59732+ */
59733+
59734+static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
59735+{
59736+ uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
59737+ uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
59738+
59739+ return ((hw_addr <= dev_priv->dma_low) ?
59740+ (dev_priv->dma_low - hw_addr) :
59741+ (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
59742+}
59743+
59744+/*
59745+ * Check that the given size fits in the buffer, otherwise wait.
59746+ */
59747+
59748+static inline int
59749+via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
59750+{
59751+ uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
59752+ uint32_t cur_addr, hw_addr, next_addr;
59753+ volatile uint32_t *hw_addr_ptr;
59754+ uint32_t count;
59755+ hw_addr_ptr = dev_priv->hw_addr_ptr;
59756+ cur_addr = dev_priv->dma_low;
59757+ next_addr = cur_addr + size + 512 * 1024;
59758+ count = 1000000;
59759+ do {
59760+ hw_addr = *hw_addr_ptr - agp_base;
59761+ if (count-- == 0) {
59762+ DRM_ERROR
59763+ ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
59764+ hw_addr, cur_addr, next_addr);
59765+ return -1;
59766+ }
59767+ } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
59768+ return 0;
59769+}
59770+
59771+
59772+/*
59773+ * Checks whether buffer head has reach the end. Rewind the ring buffer
59774+ * when necessary.
59775+ *
59776+ * Returns virtual pointer to ring buffer.
59777+ */
59778+
59779+static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
59780+ unsigned int size)
59781+{
59782+ if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
59783+ dev_priv->dma_high) {
59784+ via_cmdbuf_rewind(dev_priv);
59785+ }
59786+ if (via_cmdbuf_wait(dev_priv, size) != 0) {
59787+ return NULL;
59788+ }
59789+
59790+ return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
59791+}
59792+
59793+int via_dma_cleanup(struct drm_device * dev)
59794+{
59795+ if (dev->dev_private) {
59796+ drm_via_private_t *dev_priv =
59797+ (drm_via_private_t *) dev->dev_private;
59798+
59799+ if (dev_priv->ring.virtual_start) {
59800+ via_cmdbuf_reset(dev_priv);
59801+
59802+ drm_core_ioremapfree(&dev_priv->ring.map, dev);
59803+ dev_priv->ring.virtual_start = NULL;
59804+ }
59805+
59806+ }
59807+
59808+ return 0;
59809+}
59810+
59811+static int via_initialize(struct drm_device * dev,
59812+ drm_via_private_t * dev_priv,
59813+ drm_via_dma_init_t * init)
59814+{
59815+ if (!dev_priv || !dev_priv->mmio) {
59816+ DRM_ERROR("via_dma_init called before via_map_init\n");
59817+ return -EFAULT;
59818+ }
59819+
59820+ if (dev_priv->ring.virtual_start != NULL) {
59821+ DRM_ERROR("%s called again without calling cleanup\n",
59822+ __FUNCTION__);
59823+ return -EFAULT;
59824+ }
59825+
59826+ if (!dev->agp || !dev->agp->base) {
59827+ DRM_ERROR("%s called with no agp memory available\n",
59828+ __FUNCTION__);
59829+ return -EFAULT;
59830+ }
59831+
59832+ if (dev_priv->chipset == VIA_DX9_0) {
59833+ DRM_ERROR("AGP DMA is not supported on this chip\n");
59834+ return -EINVAL;
59835+ }
59836+
59837+ dev_priv->ring.map.offset = dev->agp->base + init->offset;
59838+ dev_priv->ring.map.size = init->size;
59839+ dev_priv->ring.map.type = 0;
59840+ dev_priv->ring.map.flags = 0;
59841+ dev_priv->ring.map.mtrr = 0;
59842+
59843+ drm_core_ioremap(&dev_priv->ring.map, dev);
59844+
59845+ if (dev_priv->ring.map.handle == NULL) {
59846+ via_dma_cleanup(dev);
59847+ DRM_ERROR("can not ioremap virtual address for"
59848+ " ring buffer\n");
59849+ return -ENOMEM;
59850+ }
59851+
59852+ dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
59853+
59854+ dev_priv->dma_ptr = dev_priv->ring.virtual_start;
59855+ dev_priv->dma_low = 0;
59856+ dev_priv->dma_high = init->size;
59857+ dev_priv->dma_wrap = init->size;
59858+ dev_priv->dma_offset = init->offset;
59859+ dev_priv->last_pause_ptr = NULL;
59860+ dev_priv->hw_addr_ptr =
59861+ (volatile uint32_t *)((char *)dev_priv->mmio->handle +
59862+ init->reg_pause_addr);
59863+
59864+ via_cmdbuf_start(dev_priv);
59865+
59866+ return 0;
59867+}
59868+
59869+static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
59870+{
59871+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
59872+ drm_via_dma_init_t *init = data;
59873+ int retcode = 0;
59874+
59875+ switch (init->func) {
59876+ case VIA_INIT_DMA:
59877+ if (!DRM_SUSER(DRM_CURPROC))
59878+ retcode = -EPERM;
59879+ else
59880+ retcode = via_initialize(dev, dev_priv, init);
59881+ break;
59882+ case VIA_CLEANUP_DMA:
59883+ if (!DRM_SUSER(DRM_CURPROC))
59884+ retcode = -EPERM;
59885+ else
59886+ retcode = via_dma_cleanup(dev);
59887+ break;
59888+ case VIA_DMA_INITIALIZED:
59889+ retcode = (dev_priv->ring.virtual_start != NULL) ?
59890+ 0 : -EFAULT;
59891+ break;
59892+ default:
59893+ retcode = -EINVAL;
59894+ break;
59895+ }
59896+
59897+ return retcode;
59898+}
59899+
59900+
59901+
59902+static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
59903+{
59904+ drm_via_private_t *dev_priv;
59905+ uint32_t *vb;
59906+ int ret;
59907+
59908+ dev_priv = (drm_via_private_t *) dev->dev_private;
59909+
59910+ if (dev_priv->ring.virtual_start == NULL) {
59911+ DRM_ERROR("%s called without initializing AGP ring buffer.\n",
59912+ __FUNCTION__);
59913+ return -EFAULT;
59914+ }
59915+
59916+ if (cmd->size > VIA_PCI_BUF_SIZE) {
59917+ return -ENOMEM;
59918+ }
59919+
59920+ if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
59921+ return -EFAULT;
59922+
59923+ /*
59924+ * Running this function on AGP memory is dead slow. Therefore
59925+ * we run it on a temporary cacheable system memory buffer and
59926+ * copy it to AGP memory when ready.
59927+ */
59928+
59929+ if ((ret =
59930+ via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
59931+ cmd->size, dev, 1))) {
59932+ return ret;
59933+ }
59934+
59935+ vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
59936+ if (vb == NULL) {
59937+ return -EAGAIN;
59938+ }
59939+
59940+ memcpy(vb, dev_priv->pci_buf, cmd->size);
59941+
59942+ dev_priv->dma_low += cmd->size;
59943+
59944+ /*
59945+ * Small submissions somehow stalls the CPU. (AGP cache effects?)
59946+ * pad to greater size.
59947+ */
59948+
59949+ if (cmd->size < 0x100)
59950+ via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
59951+ via_cmdbuf_pause(dev_priv);
59952+
59953+ return 0;
59954+}
59955+
59956+int via_driver_dma_quiescent(struct drm_device * dev)
59957+{
59958+ drm_via_private_t *dev_priv = dev->dev_private;
59959+
59960+ if (!via_wait_idle(dev_priv)) {
59961+ return -EBUSY;
59962+ }
59963+ return 0;
59964+}
59965+
59966+static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
59967+{
59968+
59969+ LOCK_TEST_WITH_RETURN(dev, file_priv);
59970+
59971+ return via_driver_dma_quiescent(dev);
59972+}
59973+
59974+static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
59975+{
59976+ drm_via_cmdbuffer_t *cmdbuf = data;
59977+ int ret;
59978+
59979+ LOCK_TEST_WITH_RETURN(dev, file_priv);
59980+
59981+ DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf->buf,
59982+ cmdbuf->size);
59983+
59984+ ret = via_dispatch_cmdbuffer(dev, cmdbuf);
59985+ if (ret) {
59986+ return ret;
59987+ }
59988+
59989+ return 0;
59990+}
59991+
59992+static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
59993+ drm_via_cmdbuffer_t * cmd)
59994+{
59995+ drm_via_private_t *dev_priv = dev->dev_private;
59996+ int ret;
59997+
59998+ if (cmd->size > VIA_PCI_BUF_SIZE) {
59999+ return -ENOMEM;
60000+ }
60001+ if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
60002+ return -EFAULT;
60003+
60004+ if ((ret =
60005+ via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
60006+ cmd->size, dev, 0))) {
60007+ return ret;
60008+ }
60009+
60010+ ret =
60011+ via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
60012+ cmd->size);
60013+ return ret;
60014+}
60015+
60016+static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
60017+{
60018+ drm_via_cmdbuffer_t *cmdbuf = data;
60019+ int ret;
60020+
60021+ LOCK_TEST_WITH_RETURN(dev, file_priv);
60022+
60023+ DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf->buf,
60024+ cmdbuf->size);
60025+
60026+ ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
60027+ if (ret) {
60028+ return ret;
60029+ }
60030+
60031+ return 0;
60032+}
60033+
60034+static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
60035+ uint32_t * vb, int qw_count)
60036+{
60037+ for (; qw_count > 0; --qw_count) {
60038+ VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
60039+ }
60040+ return vb;
60041+}
60042+
60043+/*
60044+ * This function is used internally by ring buffer mangement code.
60045+ *
60046+ * Returns virtual pointer to ring buffer.
60047+ */
60048+static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
60049+{
60050+ return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
60051+}
60052+
60053+/*
60054+ * Hooks a segment of data into the tail of the ring-buffer by
60055+ * modifying the pause address stored in the buffer itself. If
60056+ * the regulator has already paused, restart it.
60057+ */
60058+static int via_hook_segment(drm_via_private_t * dev_priv,
60059+ uint32_t pause_addr_hi, uint32_t pause_addr_lo,
60060+ int no_pci_fire)
60061+{
60062+ int paused, count;
60063+ volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
60064+ uint32_t reader,ptr;
60065+
60066+ paused = 0;
60067+ via_flush_write_combine();
60068+ (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
60069+ *paused_at = pause_addr_lo;
60070+ via_flush_write_combine();
60071+ (void) *paused_at;
60072+ reader = *(dev_priv->hw_addr_ptr);
60073+ ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
60074+ dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
60075+ dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
60076+
60077+ if ((ptr - reader) <= dev_priv->dma_diff ) {
60078+ count = 10000000;
60079+ while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
60080+ }
60081+
60082+ if (paused && !no_pci_fire) {
60083+ reader = *(dev_priv->hw_addr_ptr);
60084+ if ((ptr - reader) == dev_priv->dma_diff) {
60085+
60086+ /*
60087+ * There is a concern that these writes may stall the PCI bus
60088+ * if the GPU is not idle. However, idling the GPU first
60089+ * doesn't make a difference.
60090+ */
60091+
60092+ VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
60093+ VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
60094+ VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
60095+ VIA_READ(VIA_REG_TRANSPACE);
60096+ }
60097+ }
60098+
60099+ return paused;
60100+}
60101+
60102+
60103+
60104+static int via_wait_idle(drm_via_private_t * dev_priv)
60105+{
60106+ int count = 10000000;
60107+
60108+ while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
60109+
60110+ while (count-- && (VIA_READ(VIA_REG_STATUS) &
60111+ (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
60112+ VIA_3D_ENG_BUSY))) ;
60113+ return count;
60114+}
60115+
60116+static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
60117+ uint32_t addr, uint32_t *cmd_addr_hi,
60118+ uint32_t *cmd_addr_lo, int skip_wait)
60119+{
60120+ uint32_t agp_base;
60121+ uint32_t cmd_addr, addr_lo, addr_hi;
60122+ uint32_t *vb;
60123+ uint32_t qw_pad_count;
60124+
60125+ if (!skip_wait)
60126+ via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
60127+
60128+ vb = via_get_dma(dev_priv);
60129+ VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
60130+ (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
60131+ agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
60132+ qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
60133+ ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
60134+
60135+ cmd_addr = (addr) ? addr :
60136+ agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
60137+ addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
60138+ (cmd_addr & HC_HAGPBpL_MASK));
60139+ addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
60140+
60141+ vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
60142+ VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
60143+ return vb;
60144+}
60145+
60146+static void via_cmdbuf_start(drm_via_private_t * dev_priv)
60147+{
60148+ uint32_t pause_addr_lo, pause_addr_hi;
60149+ uint32_t start_addr, start_addr_lo;
60150+ uint32_t end_addr, end_addr_lo;
60151+ uint32_t command;
60152+ uint32_t agp_base;
60153+ uint32_t ptr;
60154+ uint32_t reader;
60155+ int count;
60156+
60157+ dev_priv->dma_low = 0;
60158+
60159+ agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
60160+ start_addr = agp_base;
60161+ end_addr = agp_base + dev_priv->dma_high;
60162+
60163+ start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
60164+ end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
60165+ command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
60166+ ((end_addr & 0xff000000) >> 16));
60167+
60168+ dev_priv->last_pause_ptr =
60169+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
60170+ &pause_addr_hi, & pause_addr_lo, 1) - 1;
60171+
60172+ via_flush_write_combine();
60173+ (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
60174+
60175+ VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
60176+ VIA_WRITE(VIA_REG_TRANSPACE, command);
60177+ VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
60178+ VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
60179+
60180+ VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
60181+ VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
60182+ DRM_WRITEMEMORYBARRIER();
60183+ VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
60184+ VIA_READ(VIA_REG_TRANSPACE);
60185+
60186+ dev_priv->dma_diff = 0;
60187+
60188+ count = 10000000;
60189+ while (!(VIA_READ(0x41c) & 0x80000000) && count--);
60190+
60191+ reader = *(dev_priv->hw_addr_ptr);
60192+ ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
60193+ dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
60194+
60195+ /*
60196+ * This is the difference between where we tell the
60197+ * command reader to pause and where it actually pauses.
60198+ * This differs between hw implementation so we need to
60199+ * detect it.
60200+ */
60201+
60202+ dev_priv->dma_diff = ptr - reader;
60203+}
60204+
60205+static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
60206+{
60207+ uint32_t *vb;
60208+
60209+ via_cmdbuf_wait(dev_priv, qwords + 2);
60210+ vb = via_get_dma(dev_priv);
60211+ VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16);
60212+ via_align_buffer(dev_priv,vb,qwords);
60213+}
60214+
60215+static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
60216+{
60217+ uint32_t *vb = via_get_dma(dev_priv);
60218+ SetReg2DAGP(0x0C, (0 | (0 << 16)));
60219+ SetReg2DAGP(0x10, 0 | (0 << 16));
60220+ SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
60221+}
60222+
60223+static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
60224+{
60225+ uint32_t agp_base;
60226+ uint32_t pause_addr_lo, pause_addr_hi;
60227+ uint32_t jump_addr_lo, jump_addr_hi;
60228+ volatile uint32_t *last_pause_ptr;
60229+
60230+ agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
60231+ via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
60232+ &jump_addr_lo, 0);
60233+
60234+ dev_priv->dma_wrap = dev_priv->dma_low;
60235+
60236+
60237+ /*
60238+ * Wrap command buffer to the beginning.
60239+ */
60240+
60241+ dev_priv->dma_low = 0;
60242+ if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
60243+ DRM_ERROR("via_cmdbuf_jump failed\n");
60244+ }
60245+
60246+ via_dummy_bitblt(dev_priv);
60247+ via_dummy_bitblt(dev_priv);
60248+ last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
60249+ &pause_addr_lo, 0) -1;
60250+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
60251+ &pause_addr_lo, 0);
60252+ *last_pause_ptr = pause_addr_lo;
60253+
60254+ via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
60255+}
60256+
60257+
60258+static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
60259+{
60260+ via_cmdbuf_jump(dev_priv);
60261+}
60262+
60263+static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
60264+{
60265+ uint32_t pause_addr_lo, pause_addr_hi;
60266+
60267+ via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
60268+ via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
60269+}
60270+
60271+
60272+static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
60273+{
60274+ via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
60275+}
60276+
60277+static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
60278+{
60279+ via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
60280+ via_wait_idle(dev_priv);
60281+}
60282+
60283+/*
60284+ * User interface to the space and lag functions.
60285+ */
60286+
60287+static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
60288+{
60289+ drm_via_cmdbuf_size_t *d_siz = data;
60290+ int ret = 0;
60291+ uint32_t tmp_size, count;
60292+ drm_via_private_t *dev_priv;
60293+
60294+ DRM_DEBUG("via cmdbuf_size\n");
60295+ LOCK_TEST_WITH_RETURN(dev, file_priv);
60296+
60297+ dev_priv = (drm_via_private_t *) dev->dev_private;
60298+
60299+ if (dev_priv->ring.virtual_start == NULL) {
60300+ DRM_ERROR("%s called without initializing AGP ring buffer.\n",
60301+ __FUNCTION__);
60302+ return -EFAULT;
60303+ }
60304+
60305+ count = 1000000;
60306+ tmp_size = d_siz->size;
60307+ switch(d_siz->func) {
60308+ case VIA_CMDBUF_SPACE:
60309+ while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
60310+ && count--) {
60311+ if (!d_siz->wait) {
60312+ break;
60313+ }
60314+ }
60315+ if (!count) {
60316+ DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
60317+ ret = -EAGAIN;
60318+ }
60319+ break;
60320+ case VIA_CMDBUF_LAG:
60321+ while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
60322+ && count--) {
60323+ if (!d_siz->wait) {
60324+ break;
60325+ }
60326+ }
60327+ if (!count) {
60328+ DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
60329+ ret = -EAGAIN;
60330+ }
60331+ break;
60332+ default:
60333+ ret = -EFAULT;
60334+ }
60335+ d_siz->size = tmp_size;
60336+
60337+ return ret;
60338+}
60339+
60340+#ifndef VIA_HAVE_DMABLIT
60341+int
60342+via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
60343+ DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
60344+ return -EINVAL;
60345+}
60346+int
60347+via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
60348+ DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
60349+ return -EINVAL;
60350+}
60351+#endif
60352+
60353+struct drm_ioctl_desc via_ioctls[] = {
60354+ DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
60355+ DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),
60356+ DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
60357+ DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
60358+ DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
60359+ DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
60360+ DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),
60361+ DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
60362+ DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
60363+ DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
60364+ DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
60365+ DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
60366+ DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
60367+ DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
60368+};
60369+
60370+int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);
60371Index: git/shared-core/via_drm.h
60372===================================================================
60373--- git.orig/shared-core/via_drm.h 2008-12-12 17:20:14.000000000 +0000
60374+++ git/shared-core/via_drm.h 2008-12-12 17:35:22.000000000 +0000
60375@@ -42,37 +42,27 @@
60376 * backwards incompatibilities, (which should be avoided whenever possible).
60377 */
60378
60379-#define VIA_DRM_DRIVER_DATE "20060616"
60380+#define VIA_DRM_DRIVER_DATE "20070202"
60381
60382 #define VIA_DRM_DRIVER_MAJOR 2
60383-#define VIA_DRM_DRIVER_MINOR 10
60384-#define VIA_DRM_DRIVER_PATCHLEVEL 2
60385+#define VIA_DRM_DRIVER_MINOR 11
60386+#define VIA_DRM_DRIVER_PATCHLEVEL 1
60387 #define VIA_DRM_DRIVER_VERSION (((VIA_DRM_DRIVER_MAJOR) << 16) | (VIA_DRM_DRIVER_MINOR))
60388
60389-#define VIA_NR_SAREA_CLIPRECTS 8
60390+#define VIA_NR_SAREA_CLIPRECTS 8
60391 #define VIA_NR_XVMC_PORTS 10
60392 #define VIA_NR_XVMC_LOCKS 5
60393 #define VIA_MAX_CACHELINE_SIZE 64
60394 #define XVMCLOCKPTR(saPriv,lockNo) \
60395- ((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
60396+ ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
60397 (VIA_MAX_CACHELINE_SIZE - 1)) & \
60398 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
60399 VIA_MAX_CACHELINE_SIZE*(lockNo)))
60400-
60401-/* Each region is a minimum of 64k, and there are at most 64 of them.
60402- */
60403 #define VIA_NR_TEX_REGIONS 64
60404-#define VIA_LOG_MIN_TEX_REGION_SIZE 16
60405+
60406 #endif
60407
60408-#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
60409-#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
60410-#define VIA_UPLOAD_CTX 0x4
60411-#define VIA_UPLOAD_BUFFERS 0x8
60412-#define VIA_UPLOAD_TEX0 0x10
60413-#define VIA_UPLOAD_TEX1 0x20
60414-#define VIA_UPLOAD_CLIPRECTS 0x40
60415-#define VIA_UPLOAD_ALL 0xff
60416+#define DRM_VIA_FENCE_TYPE_ACCEL 0x00000002
60417
60418 /* VIA specific ioctls */
60419 #define DRM_VIA_ALLOCMEM 0x00
60420@@ -124,7 +114,7 @@
60421
60422 #define VIA_MEM_VIDEO 0 /* matches drm constant */
60423 #define VIA_MEM_AGP 1 /* matches drm constant */
60424-#define VIA_MEM_SYSTEM 2
60425+#define VIA_MEM_SYSTEM 2
60426 #define VIA_MEM_MIXED 3
60427 #define VIA_MEM_UNKNOWN 4
60428
60429@@ -197,7 +187,7 @@
60430 typedef struct _drm_via_sarea {
60431 unsigned int dirty;
60432 unsigned int nbox;
60433- drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
60434+ struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
60435 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
60436 int texAge; /* last time texture was uploaded */
60437 int ctxOwner; /* last context to upload state */
60438@@ -213,7 +203,7 @@
60439
60440 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
60441 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
60442- unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
60443+ unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
60444
60445 /* Used by the 3d driver only at this point, for pageflipping:
60446 */
60447@@ -260,14 +250,14 @@
60448 struct drm_wait_vblank_reply reply;
60449 } drm_via_irqwait_t;
60450
60451-typedef struct drm_via_blitsync {
60452+typedef struct drm_via_blitsync {
60453 uint32_t sync_handle;
60454 unsigned engine;
60455 } drm_via_blitsync_t;
60456
60457-/*
60458+/*
60459 * Below,"flags" is currently unused but will be used for possible future
60460- * extensions like kernel space bounce buffers for bad alignments and
60461+ * extensions like kernel space bounce buffers for bad alignments and
60462 * blit engine busy-wait polling for better latency in the absence of
60463 * interrupts.
60464 */
60465@@ -281,11 +271,11 @@
60466
60467 unsigned char *mem_addr;
60468 uint32_t mem_stride;
60469-
60470+
60471 uint32_t flags;
60472 int to_fb;
60473
60474- drm_via_blitsync_t sync;
60475+ drm_via_blitsync_t sync;
60476 } drm_via_dmablit_t;
60477
60478
60479Index: git/shared-core/via_drv.c
60480===================================================================
60481--- /dev/null 1970-01-01 00:00:00.000000000 +0000
60482+++ git/shared-core/via_drv.c 2008-12-12 17:35:22.000000000 +0000
60483@@ -0,0 +1,161 @@
60484+/*
60485+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
60486+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
60487+ *
60488+ * Permission is hereby granted, free of charge, to any person obtaining a
60489+ * copy of this software and associated documentation files (the "Software"),
60490+ * to deal in the Software without restriction, including without limitation
60491+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
60492+ * and/or sell copies of the Software, and to permit persons to whom the
60493+ * Software is furnished to do so, subject to the following conditions:
60494+ *
60495+ * The above copyright notice and this permission notice (including the
60496+ * next paragraph) shall be included in all copies or substantial portions
60497+ * of the Software.
60498+ *
60499+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
60500+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
60501+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
60502+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
60503+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
60504+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
60505+ * DEALINGS IN THE SOFTWARE.
60506+ */
60507+
60508+#include "drmP.h"
60509+#include "via_drm.h"
60510+#include "via_drv.h"
60511+
60512+#include "drm_pciids.h"
60513+
60514+
60515+static int dri_library_name(struct drm_device * dev, char * buf)
60516+{
60517+ return snprintf(buf, PAGE_SIZE, "unichrome\n");
60518+}
60519+
60520+static struct pci_device_id pciidlist[] = {
60521+ viadrv_PCI_IDS
60522+};
60523+
60524+
60525+#ifdef VIA_HAVE_FENCE
60526+static struct drm_fence_driver via_fence_driver = {
60527+ .num_classes = 1,
60528+ .wrap_diff = (1 << 30),
60529+ .flush_diff = (1 << 20),
60530+ .sequence_mask = 0xffffffffU,
60531+ .lazy_capable = 1,
60532+ .emit = via_fence_emit_sequence,
60533+ .poke_flush = via_poke_flush,
60534+ .has_irq = via_fence_has_irq,
60535+};
60536+#endif
60537+#ifdef VIA_HAVE_BUFFER
60538+
60539+/**
60540+ * If there's no thrashing. This is the preferred memory type order.
60541+ */
60542+static uint32_t via_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
60543+
60544+/**
60545+ * If we have thrashing, most memory will be evicted to TT anyway, so we might as well
60546+ * just move the new buffer into TT from the start.
60547+ */
60548+static uint32_t via_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL};
60549+
60550+
60551+static struct drm_bo_driver via_bo_driver = {
60552+ .mem_type_prio = via_mem_prios,
60553+ .mem_busy_prio = via_busy_prios,
60554+ .num_mem_type_prio = ARRAY_SIZE(via_mem_prios),
60555+ .num_mem_busy_prio = ARRAY_SIZE(via_busy_prios),
60556+ .create_ttm_backend_entry = via_create_ttm_backend_entry,
60557+ .fence_type = via_fence_types,
60558+ .invalidate_caches = via_invalidate_caches,
60559+ .init_mem_type = via_init_mem_type,
60560+ .evict_mask = via_evict_mask,
60561+ .move = NULL,
60562+};
60563+#endif
60564+
60565+static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
60566+static struct drm_driver driver = {
60567+ .driver_features =
60568+ DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ |
60569+ DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL,
60570+ .load = via_driver_load,
60571+ .unload = via_driver_unload,
60572+#ifndef VIA_HAVE_CORE_MM
60573+ .context_ctor = via_init_context,
60574+#endif
60575+ .context_dtor = via_final_context,
60576+ .vblank_wait = via_driver_vblank_wait,
60577+ .irq_preinstall = via_driver_irq_preinstall,
60578+ .irq_postinstall = via_driver_irq_postinstall,
60579+ .irq_uninstall = via_driver_irq_uninstall,
60580+ .irq_handler = via_driver_irq_handler,
60581+ .dma_quiescent = via_driver_dma_quiescent,
60582+ .dri_library_name = dri_library_name,
60583+ .reclaim_buffers = drm_core_reclaim_buffers,
60584+ .reclaim_buffers_locked = NULL,
60585+#ifdef VIA_HAVE_CORE_MM
60586+ .reclaim_buffers_idlelocked = via_reclaim_buffers_locked,
60587+ .lastclose = via_lastclose,
60588+#endif
60589+ .get_map_ofs = drm_core_get_map_ofs,
60590+ .get_reg_ofs = drm_core_get_reg_ofs,
60591+ .ioctls = via_ioctls,
60592+ .fops = {
60593+ .owner = THIS_MODULE,
60594+ .open = drm_open,
60595+ .release = drm_release,
60596+ .ioctl = drm_ioctl,
60597+ .mmap = drm_mmap,
60598+ .poll = drm_poll,
60599+ .fasync = drm_fasync,
60600+ },
60601+ .pci_driver = {
60602+ .name = DRIVER_NAME,
60603+ .id_table = pciidlist,
60604+ .probe = probe,
60605+ .remove = __devexit_p(drm_cleanup_pci),
60606+ },
60607+#ifdef VIA_HAVE_FENCE
60608+ .fence_driver = &via_fence_driver,
60609+#endif
60610+#ifdef VIA_HAVE_BUFFER
60611+ .bo_driver = &via_bo_driver,
60612+#endif
60613+ .name = DRIVER_NAME,
60614+ .desc = DRIVER_DESC,
60615+ .date = VIA_DRM_DRIVER_DATE,
60616+ .major = VIA_DRM_DRIVER_MAJOR,
60617+ .minor = VIA_DRM_DRIVER_MINOR,
60618+ .patchlevel = VIA_DRM_DRIVER_PATCHLEVEL
60619+};
60620+
60621+static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
60622+{
60623+ return drm_get_dev(pdev, ent, &driver);
60624+}
60625+
60626+static int __init via_init(void)
60627+{
60628+ driver.num_ioctls = via_max_ioctl;
60629+
60630+ via_init_command_verifier();
60631+ return drm_init(&driver, pciidlist);
60632+}
60633+
60634+static void __exit via_exit(void)
60635+{
60636+ drm_exit(&driver);
60637+}
60638+
60639+module_init(via_init);
60640+module_exit(via_exit);
60641+
60642+MODULE_AUTHOR(DRIVER_AUTHOR);
60643+MODULE_DESCRIPTION(DRIVER_DESC);
60644+MODULE_LICENSE("GPL and additional rights");
60645Index: git/shared-core/via_drv.h
60646===================================================================
60647--- /dev/null 1970-01-01 00:00:00.000000000 +0000
60648+++ git/shared-core/via_drv.h 2008-12-12 17:35:22.000000000 +0000
60649@@ -0,0 +1,219 @@
60650+/*
60651+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
60652+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
60653+ *
60654+ * Permission is hereby granted, free of charge, to any person obtaining a
60655+ * copy of this software and associated documentation files (the "Software"),
60656+ * to deal in the Software without restriction, including without limitation
60657+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
60658+ * and/or sell copies of the Software, and to permit persons to whom the
60659+ * Software is furnished to do so, subject to the following conditions:
60660+ *
60661+ * The above copyright notice and this permission notice (including the
60662+ * next paragraph) shall be included in all copies or substantial portions
60663+ * of the Software.
60664+ *
60665+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
60666+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
60667+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
60668+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
60669+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
60670+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
60671+ * DEALINGS IN THE SOFTWARE.
60672+ */
60673+#ifndef _VIA_DRV_H_
60674+#define _VIA_DRV_H_
60675+
60676+#include "drm_sman.h"
60677+#define DRIVER_AUTHOR "Various"
60678+
60679+#define DRIVER_NAME "via"
60680+#define DRIVER_DESC "VIA Unichrome / Pro"
60681+
60682+#include "via_verifier.h"
60683+
60684+/*
60685+ * Registers go here.
60686+ */
60687+
60688+
60689+#define CMDBUF_ALIGNMENT_SIZE (0x100)
60690+#define CMDBUF_ALIGNMENT_MASK (0x0ff)
60691+
60692+/* defines for VIA 3D registers */
60693+#define VIA_REG_STATUS 0x400
60694+#define VIA_REG_TRANSET 0x43C
60695+#define VIA_REG_TRANSPACE 0x440
60696+
60697+/* VIA_REG_STATUS(0x400): Engine Status */
60698+#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
60699+#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
60700+#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
60701+#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
60702+
60703+
60704+
60705+#if defined(__linux__)
60706+#include "via_dmablit.h"
60707+
60708+/*
60709+ * This define and all its references can be removed when
60710+ * the DMA blit code has been implemented for FreeBSD.
60711+ */
60712+#define VIA_HAVE_DMABLIT 1
60713+#define VIA_HAVE_CORE_MM 1
60714+#define VIA_HAVE_FENCE 1
60715+#define VIA_HAVE_BUFFER 1
60716+#endif
60717+
60718+#define VIA_PCI_BUF_SIZE 60000
60719+#define VIA_FIRE_BUF_SIZE 1024
60720+#define VIA_NUM_IRQS 4
60721+
60722+typedef struct drm_via_ring_buffer {
60723+ drm_local_map_t map;
60724+ char *virtual_start;
60725+} drm_via_ring_buffer_t;
60726+
60727+typedef uint32_t maskarray_t[5];
60728+
60729+typedef struct drm_via_irq {
60730+ atomic_t irq_received;
60731+ uint32_t pending_mask;
60732+ uint32_t enable_mask;
60733+ wait_queue_head_t irq_queue;
60734+} drm_via_irq_t;
60735+
60736+typedef struct drm_via_private {
60737+ drm_via_sarea_t *sarea_priv;
60738+ drm_local_map_t *sarea;
60739+ drm_local_map_t *fb;
60740+ drm_local_map_t *mmio;
60741+ unsigned long agpAddr;
60742+ wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
60743+ char *dma_ptr;
60744+ unsigned int dma_low;
60745+ unsigned int dma_high;
60746+ unsigned int dma_offset;
60747+ uint32_t dma_wrap;
60748+ volatile uint32_t *last_pause_ptr;
60749+ volatile uint32_t *hw_addr_ptr;
60750+ drm_via_ring_buffer_t ring;
60751+ struct timeval last_vblank;
60752+ int last_vblank_valid;
60753+ unsigned usec_per_vblank;
60754+ drm_via_state_t hc_state;
60755+ char pci_buf[VIA_PCI_BUF_SIZE];
60756+ const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
60757+ uint32_t num_fire_offsets;
60758+ int chipset;
60759+ drm_via_irq_t via_irqs[VIA_NUM_IRQS];
60760+ unsigned num_irqs;
60761+ maskarray_t *irq_masks;
60762+ uint32_t irq_enable_mask;
60763+ uint32_t irq_pending_mask;
60764+ int *irq_map;
60765+ /* Memory manager stuff */
60766+#ifdef VIA_HAVE_CORE_MM
60767+ unsigned int idle_fault;
60768+ struct drm_sman sman;
60769+ int vram_initialized;
60770+ int agp_initialized;
60771+ unsigned long vram_offset;
60772+ unsigned long agp_offset;
60773+#endif
60774+#ifdef VIA_HAVE_DMABLIT
60775+ drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES];
60776+#endif
60777+ uint32_t dma_diff;
60778+#ifdef VIA_HAVE_FENCE
60779+ spinlock_t fence_lock;
60780+ uint32_t emit_0_sequence;
60781+ int have_idlelock;
60782+ struct timer_list fence_timer;
60783+#endif
60784+} drm_via_private_t;
60785+
60786+enum via_family {
60787+ VIA_OTHER = 0, /* Baseline */
60788+ VIA_PRO_GROUP_A, /* Another video engine and DMA commands */
60789+ VIA_DX9_0 /* Same video as pro_group_a, but 3D is unsupported */
60790+};
60791+
60792+/* VIA MMIO register access */
60793+#define VIA_BASE ((dev_priv->mmio))
60794+
60795+#define VIA_READ(reg) DRM_READ32(VIA_BASE, reg)
60796+#define VIA_WRITE(reg,val) DRM_WRITE32(VIA_BASE, reg, val)
60797+#define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg)
60798+#define VIA_WRITE8(reg,val) DRM_WRITE8(VIA_BASE, reg, val)
60799+
60800+extern struct drm_ioctl_desc via_ioctls[];
60801+extern int via_max_ioctl;
60802+
60803+extern int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
60804+extern int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
60805+extern int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
60806+extern int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
60807+extern int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
60808+extern int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv);
60809+extern int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv);
60810+extern int via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv );
60811+extern int via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv );
60812+
60813+extern int via_driver_load(struct drm_device *dev, unsigned long chipset);
60814+extern int via_driver_unload(struct drm_device *dev);
60815+extern int via_final_context(struct drm_device * dev, int context);
60816+
60817+extern int via_do_cleanup_map(struct drm_device * dev);
60818+extern int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
60819+
60820+extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS);
60821+extern void via_driver_irq_preinstall(struct drm_device * dev);
60822+extern void via_driver_irq_postinstall(struct drm_device * dev);
60823+extern void via_driver_irq_uninstall(struct drm_device * dev);
60824+
60825+extern int via_dma_cleanup(struct drm_device * dev);
60826+extern void via_init_command_verifier(void);
60827+extern int via_driver_dma_quiescent(struct drm_device * dev);
60828+extern void via_init_futex(drm_via_private_t *dev_priv);
60829+extern void via_cleanup_futex(drm_via_private_t *dev_priv);
60830+extern void via_release_futex(drm_via_private_t *dev_priv, int context);
60831+
60832+#ifdef VIA_HAVE_CORE_MM
60833+extern void via_reclaim_buffers_locked(struct drm_device *dev,
60834+ struct drm_file *file_priv);
60835+extern void via_lastclose(struct drm_device *dev);
60836+#else
60837+extern int via_init_context(struct drm_device * dev, int context);
60838+#endif
60839+
60840+#ifdef VIA_HAVE_DMABLIT
60841+extern void via_dmablit_handler(struct drm_device *dev, int engine, int from_irq);
60842+extern void via_init_dmablit(struct drm_device *dev);
60843+#endif
60844+
60845+#ifdef VIA_HAVE_FENCE
60846+extern void via_fence_timer(unsigned long data);
60847+extern void via_poke_flush(struct drm_device * dev, uint32_t class);
60848+extern int via_fence_emit_sequence(struct drm_device * dev, uint32_t class,
60849+ uint32_t flags,
60850+ uint32_t * sequence,
60851+ uint32_t * native_type);
60852+extern int via_fence_has_irq(struct drm_device * dev, uint32_t class,
60853+ uint32_t flags);
60854+#endif
60855+
60856+#ifdef VIA_HAVE_BUFFER
60857+extern struct drm_ttm_backend *via_create_ttm_backend_entry(struct drm_device *dev);
60858+extern int via_fence_types(struct drm_buffer_object *bo, uint32_t *fclass,
60859+ uint32_t *type);
60860+extern int via_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
60861+extern int via_init_mem_type(struct drm_device *dev, uint32_t type,
60862+ struct drm_mem_type_manager *man);
60863+extern uint32_t via_evict_mask(struct drm_buffer_object *bo);
60864+extern int via_move(struct drm_buffer_object *bo, int evict,
60865+ int no_wait, struct drm_bo_mem_reg *new_mem);
60866+#endif
60867+
60868+#endif
60869Index: git/shared-core/via_ds.c
60870===================================================================
60871--- /dev/null 1970-01-01 00:00:00.000000000 +0000
60872+++ git/shared-core/via_ds.c 2008-12-12 17:35:22.000000000 +0000
60873@@ -0,0 +1,274 @@
60874+/*
60875+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
60876+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
60877+ * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
60878+ *
60879+ * Permission is hereby granted, free of charge, to any person obtaining a
60880+ * copy of this software and associated documentation files (the "Software"),
60881+ * to deal in the Software without restriction, including without limitation
60882+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
60883+ * and/or sell copies of the Software, and to permit persons to whom the
60884+ * Software is furnished to do so, subject to the following conditions:
60885+ *
60886+ * The above copyright notice and this permission notice (including the
60887+ * next paragraph) shall be included in all copies or substantial portions
60888+ * of the Software.
60889+ *
60890+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
60891+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
60892+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
60893+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
60894+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
60895+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
60896+ * DEALINGS IN THE SOFTWARE.
60897+ */
60898+
60899+#include "drmP.h"
60900+
60901+#include "via_ds.h"
60902+extern unsigned int VIA_DEBUG;
60903+
60904+set_t *via_setInit(void)
60905+{
60906+ int i;
60907+ set_t *set;
60908+ set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
60909+ for (i = 0; i < SET_SIZE; i++) {
60910+ set->list[i].free_next = i + 1;
60911+ set->list[i].alloc_next = -1;
60912+ }
60913+ set->list[SET_SIZE - 1].free_next = -1;
60914+ set->free = 0;
60915+ set->alloc = -1;
60916+ set->trace = -1;
60917+ return set;
60918+}
60919+
60920+int via_setAdd(set_t * set, ITEM_TYPE item)
60921+{
60922+ int free = set->free;
60923+ if (free != -1) {
60924+ set->list[free].val = item;
60925+ set->free = set->list[free].free_next;
60926+ } else {
60927+ return 0;
60928+ }
60929+ set->list[free].alloc_next = set->alloc;
60930+ set->alloc = free;
60931+ set->list[free].free_next = -1;
60932+ return 1;
60933+}
60934+
60935+int via_setDel(set_t * set, ITEM_TYPE item)
60936+{
60937+ int alloc = set->alloc;
60938+ int prev = -1;
60939+
60940+ while (alloc != -1) {
60941+ if (set->list[alloc].val == item) {
60942+ if (prev != -1)
60943+ set->list[prev].alloc_next =
60944+ set->list[alloc].alloc_next;
60945+ else
60946+ set->alloc = set->list[alloc].alloc_next;
60947+ break;
60948+ }
60949+ prev = alloc;
60950+ alloc = set->list[alloc].alloc_next;
60951+ }
60952+
60953+ if (alloc == -1)
60954+ return 0;
60955+
60956+ set->list[alloc].free_next = set->free;
60957+ set->free = alloc;
60958+ set->list[alloc].alloc_next = -1;
60959+
60960+ return 1;
60961+}
60962+
60963+/* setFirst -> setAdd -> setNext is wrong */
60964+
60965+int via_setFirst(set_t * set, ITEM_TYPE * item)
60966+{
60967+ if (set->alloc == -1)
60968+ return 0;
60969+
60970+ *item = set->list[set->alloc].val;
60971+ set->trace = set->list[set->alloc].alloc_next;
60972+
60973+ return 1;
60974+}
60975+
60976+int via_setNext(set_t * set, ITEM_TYPE * item)
60977+{
60978+ if (set->trace == -1)
60979+ return 0;
60980+
60981+ *item = set->list[set->trace].val;
60982+ set->trace = set->list[set->trace].alloc_next;
60983+
60984+ return 1;
60985+}
60986+
60987+int via_setDestroy(set_t * set)
60988+{
60989+ drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
60990+
60991+ return 1;
60992+}
60993+
60994+#define ISFREE(bptr) ((bptr)->free)
60995+
60996+#define fprintf(fmt, arg...) do{}while(0)
60997+
60998+memHeap_t *via_mmInit(int ofs, int size)
60999+{
61000+ PMemBlock blocks;
61001+
61002+ if (size <= 0)
61003+ return NULL;
61004+
61005+ blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
61006+
61007+ if (blocks) {
61008+ blocks->ofs = ofs;
61009+ blocks->size = size;
61010+ blocks->free = 1;
61011+ return (memHeap_t *) blocks;
61012+ } else
61013+ return NULL;
61014+}
61015+
61016+static TMemBlock *SliceBlock(TMemBlock * p,
61017+ int startofs, int size,
61018+ int reserved, int alignment)
61019+{
61020+ TMemBlock *newblock;
61021+
61022+ /* break left */
61023+ if (startofs > p->ofs) {
61024+ newblock =
61025+ (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
61026+ DRM_MEM_DRIVER);
61027+ newblock->ofs = startofs;
61028+ newblock->size = p->size - (startofs - p->ofs);
61029+ newblock->free = 1;
61030+ newblock->next = p->next;
61031+ p->size -= newblock->size;
61032+ p->next = newblock;
61033+ p = newblock;
61034+ }
61035+
61036+ /* break right */
61037+ if (size < p->size) {
61038+ newblock =
61039+ (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
61040+ DRM_MEM_DRIVER);
61041+ newblock->ofs = startofs + size;
61042+ newblock->size = p->size - size;
61043+ newblock->free = 1;
61044+ newblock->next = p->next;
61045+ p->size = size;
61046+ p->next = newblock;
61047+ }
61048+
61049+ /* p = middle block */
61050+ p->align = alignment;
61051+ p->free = 0;
61052+ p->reserved = reserved;
61053+ return p;
61054+}
61055+
61056+PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
61057+ int startSearch)
61058+{
61059+ int mask, startofs, endofs;
61060+ TMemBlock *p;
61061+
61062+ if (!heap || align2 < 0 || size <= 0)
61063+ return NULL;
61064+
61065+ mask = (1 << align2) - 1;
61066+ startofs = 0;
61067+ p = (TMemBlock *) heap;
61068+
61069+ while (p) {
61070+ if (ISFREE(p)) {
61071+ startofs = (p->ofs + mask) & ~mask;
61072+
61073+ if (startofs < startSearch)
61074+ startofs = startSearch;
61075+
61076+ endofs = startofs + size;
61077+
61078+ if (endofs <= (p->ofs + p->size))
61079+ break;
61080+ }
61081+
61082+ p = p->next;
61083+ }
61084+
61085+ if (!p)
61086+ return NULL;
61087+
61088+ p = SliceBlock(p, startofs, size, 0, mask + 1);
61089+ p->heap = heap;
61090+
61091+ return p;
61092+}
61093+
61094+static __inline__ int Join2Blocks(TMemBlock * p)
61095+{
61096+ if (p->free && p->next && p->next->free) {
61097+ TMemBlock *q = p->next;
61098+ p->size += q->size;
61099+ p->next = q->next;
61100+ drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER);
61101+
61102+ return 1;
61103+ }
61104+
61105+ return 0;
61106+}
61107+
61108+int via_mmFreeMem(PMemBlock b)
61109+{
61110+ TMemBlock *p, *prev;
61111+
61112+ if (!b)
61113+ return 0;
61114+
61115+ if (!b->heap) {
61116+ fprintf(stderr, "no heap\n");
61117+
61118+ return -1;
61119+ }
61120+
61121+ p = b->heap;
61122+ prev = NULL;
61123+
61124+ while (p && p != b) {
61125+ prev = p;
61126+ p = p->next;
61127+ }
61128+
61129+ if (!p || p->free || p->reserved) {
61130+ if (!p)
61131+ fprintf(stderr, "block not found in heap\n");
61132+ else if (p->free)
61133+ fprintf(stderr, "block already free\n");
61134+ else
61135+ fprintf(stderr, "block is reserved\n");
61136+
61137+ return -1;
61138+ }
61139+
61140+ p->free = 1;
61141+ Join2Blocks(p);
61142+
61143+ if (prev)
61144+ Join2Blocks(prev);
61145+
61146+ return 0;
61147+}
61148Index: git/shared-core/via_ds.h
61149===================================================================
61150--- /dev/null 1970-01-01 00:00:00.000000000 +0000
61151+++ git/shared-core/via_ds.h 2008-12-12 17:35:22.000000000 +0000
61152@@ -0,0 +1,104 @@
61153+/*
61154+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
61155+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
61156+ * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
61157+ * All rights reserved.
61158+ *
61159+ * Permission is hereby granted, free of charge, to any person obtaining a
61160+ * copy of this software and associated documentation files (the "Software"),
61161+ * to deal in the Software without restriction, including without limitation
61162+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
61163+ * and/or sell copies of the Software, and to permit persons to whom the
61164+ * Software is furnished to do so, subject to the following conditions:
61165+ *
61166+ * The above copyright notice and this permission notice (including the
61167+ * next paragraph) shall be included in all copies or substantial portions
61168+ * of the Software.
61169+ *
61170+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
61171+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
61172+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
61173+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
61174+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
61175+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
61176+ * DEALINGS IN THE SOFTWARE.
61177+ */
61178+#ifndef _via_ds_h_
61179+#define _via_ds_h_
61180+
61181+#include "drmP.h"
61182+
61183+/* Set Data Structure */
61184+#define SET_SIZE 5000
61185+typedef unsigned long ITEM_TYPE;
61186+
61187+typedef struct {
61188+ ITEM_TYPE val;
61189+ int alloc_next, free_next;
61190+} list_item_t;
61191+
61192+typedef struct {
61193+ int alloc;
61194+ int free;
61195+ int trace;
61196+ list_item_t list[SET_SIZE];
61197+} set_t;
61198+
61199+set_t *via_setInit(void);
61200+int via_setAdd(set_t * set, ITEM_TYPE item);
61201+int via_setDel(set_t * set, ITEM_TYPE item);
61202+int via_setFirst(set_t * set, ITEM_TYPE * item);
61203+int via_setNext(set_t * set, ITEM_TYPE * item);
61204+int via_setDestroy(set_t * set);
61205+
61206+#endif
61207+
61208+#ifndef MM_INC
61209+#define MM_INC
61210+
61211+struct mem_block_t {
61212+ struct mem_block_t *next;
61213+ struct mem_block_t *heap;
61214+ int ofs, size;
61215+ int align;
61216+ unsigned int free:1;
61217+ unsigned int reserved:1;
61218+};
61219+typedef struct mem_block_t TMemBlock;
61220+typedef struct mem_block_t *PMemBlock;
61221+
61222+/* a heap is just the first block in a chain */
61223+typedef struct mem_block_t memHeap_t;
61224+
61225+static __inline__ int mmBlockSize(PMemBlock b)
61226+{
61227+ return b->size;
61228+}
61229+
61230+static __inline__ int mmOffset(PMemBlock b)
61231+{
61232+ return b->ofs;
61233+}
61234+
61235+static __inline__ void mmMarkReserved(PMemBlock b)
61236+{
61237+ b->reserved = 1;
61238+}
61239+
61240+/*
61241+ * input: total size in bytes
61242+ * return: a heap pointer if OK, NULL if error
61243+ */
61244+memHeap_t *via_mmInit(int ofs, int size);
61245+
61246+PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
61247+ int startSearch);
61248+
61249+/*
61250+ * Free block starts at offset
61251+ * input: pointer to a block
61252+ * return: 0 if OK, -1 if error
61253+ */
61254+int via_mmFreeMem(PMemBlock b);
61255+
61256+#endif
61257Index: git/shared-core/via_irq.c
61258===================================================================
61259--- /dev/null 1970-01-01 00:00:00.000000000 +0000
61260+++ git/shared-core/via_irq.c 2008-12-12 17:35:22.000000000 +0000
61261@@ -0,0 +1,393 @@
61262+/* via_irq.c
61263+ *
61264+ * Copyright 2004 BEAM Ltd.
61265+ * Copyright 2002 Tungsten Graphics, Inc.
61266+ * Copyright 2005 Thomas Hellstrom.
61267+ * All Rights Reserved.
61268+ *
61269+ * Permission is hereby granted, free of charge, to any person obtaining a
61270+ * copy of this software and associated documentation files (the "Software"),
61271+ * to deal in the Software without restriction, including without limitation
61272+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
61273+ * and/or sell copies of the Software, and to permit persons to whom the
61274+ * Software is furnished to do so, subject to the following conditions:
61275+ *
61276+ * The above copyright notice and this permission notice (including the next
61277+ * paragraph) shall be included in all copies or substantial portions of the
61278+ * Software.
61279+ *
61280+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
61281+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
61282+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
61283+ * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
61284+ * DAMAGES OR
61285+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
61286+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
61287+ * DEALINGS IN THE SOFTWARE.
61288+ *
61289+ * Authors:
61290+ * Terry Barnaby <terry1@beam.ltd.uk>
61291+ * Keith Whitwell <keith@tungstengraphics.com>
61292+ * Thomas Hellstrom <unichrome@shipmail.org>
61293+ *
61294+ * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
61295+ * interrupt, as well as an infrastructure to handle other interrupts of the chip.
61296+ * The refresh rate is also calculated for video playback sync purposes.
61297+ */
61298+
61299+#include "drmP.h"
61300+#include "drm.h"
61301+#include "via_drm.h"
61302+#include "via_drv.h"
61303+
61304+#define VIA_REG_INTERRUPT 0x200
61305+
61306+/* VIA_REG_INTERRUPT */
61307+#define VIA_IRQ_GLOBAL (1 << 31)
61308+#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
61309+#define VIA_IRQ_VBLANK_PENDING (1 << 3)
61310+#define VIA_IRQ_HQV0_ENABLE (1 << 11)
61311+#define VIA_IRQ_HQV1_ENABLE (1 << 25)
61312+#define VIA_IRQ_HQV0_PENDING (1 << 9)
61313+#define VIA_IRQ_HQV1_PENDING (1 << 10)
61314+#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
61315+#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
61316+#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
61317+#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
61318+#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
61319+#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
61320+#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
61321+#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
61322+
61323+
61324+/*
61325+ * Device-specific IRQs go here. This type might need to be extended with
61326+ * the register if there are multiple IRQ control registers.
61327+ * Currently we activate the HQV interrupts of Unichrome Pro group A.
61328+ */
61329+
61330+static maskarray_t via_pro_group_a_irqs[] = {
61331+ {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
61332+ 0x00000000 },
61333+ {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
61334+ 0x00000000 },
61335+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
61336+ VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
61337+ {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
61338+ VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
61339+};
61340+static int via_num_pro_group_a =
61341+ sizeof(via_pro_group_a_irqs)/sizeof(maskarray_t);
61342+static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
61343+
61344+static maskarray_t via_unichrome_irqs[] = {
61345+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
61346+ VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
61347+ {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
61348+ VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
61349+};
61350+static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t);
61351+static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
61352+
61353+
61354+static unsigned time_diff(struct timeval *now,struct timeval *then)
61355+{
61356+ return (now->tv_usec >= then->tv_usec) ?
61357+ now->tv_usec - then->tv_usec :
61358+ 1000000 - (then->tv_usec - now->tv_usec);
61359+}
61360+
61361+irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
61362+{
61363+ struct drm_device *dev = (struct drm_device *) arg;
61364+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61365+ u32 status;
61366+ int handled = 0;
61367+ struct timeval cur_vblank;
61368+ drm_via_irq_t *cur_irq = dev_priv->via_irqs;
61369+ int i;
61370+
61371+ status = VIA_READ(VIA_REG_INTERRUPT);
61372+ if (status & VIA_IRQ_VBLANK_PENDING) {
61373+ atomic_inc(&dev->vbl_received);
61374+ if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
61375+#ifdef __linux__
61376+ do_gettimeofday(&cur_vblank);
61377+#else
61378+ microtime(&cur_vblank);
61379+#endif
61380+ if (dev_priv->last_vblank_valid) {
61381+ dev_priv->usec_per_vblank =
61382+ time_diff(&cur_vblank,
61383+ &dev_priv->last_vblank) >> 4;
61384+ }
61385+ dev_priv->last_vblank = cur_vblank;
61386+ dev_priv->last_vblank_valid = 1;
61387+ }
61388+ if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
61389+ DRM_DEBUG("US per vblank is: %u\n",
61390+ dev_priv->usec_per_vblank);
61391+ }
61392+ DRM_WAKEUP(&dev->vbl_queue);
61393+ drm_vbl_send_signals(dev);
61394+ handled = 1;
61395+ }
61396+
61397+ for (i=0; i<dev_priv->num_irqs; ++i) {
61398+ if (status & cur_irq->pending_mask) {
61399+ atomic_inc( &cur_irq->irq_received );
61400+ DRM_WAKEUP( &cur_irq->irq_queue );
61401+ handled = 1;
61402+#ifdef VIA_HAVE_DMABLIT
61403+ if (dev_priv->irq_map[drm_via_irq_dma0_td] == i) {
61404+ via_dmablit_handler(dev, 0, 1);
61405+ } else if (dev_priv->irq_map[drm_via_irq_dma1_td] == i) {
61406+ via_dmablit_handler(dev, 1, 1);
61407+ }
61408+#endif
61409+ }
61410+ cur_irq++;
61411+ }
61412+
61413+ /* Acknowlege interrupts */
61414+ VIA_WRITE(VIA_REG_INTERRUPT, status);
61415+
61416+
61417+ if (handled)
61418+ return IRQ_HANDLED;
61419+ else
61420+ return IRQ_NONE;
61421+}
61422+
61423+static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
61424+{
61425+ u32 status;
61426+
61427+ if (dev_priv) {
61428+ /* Acknowlege interrupts */
61429+ status = VIA_READ(VIA_REG_INTERRUPT);
61430+ VIA_WRITE(VIA_REG_INTERRUPT, status |
61431+ dev_priv->irq_pending_mask);
61432+ }
61433+}
61434+
61435+int via_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
61436+{
61437+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61438+ unsigned int cur_vblank;
61439+ int ret = 0;
61440+
61441+ DRM_DEBUG("viadrv_vblank_wait\n");
61442+ if (!dev_priv) {
61443+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
61444+ return -EINVAL;
61445+ }
61446+
61447+ viadrv_acknowledge_irqs(dev_priv);
61448+
61449+ /* Assume that the user has missed the current sequence number
61450+ * by about a day rather than she wants to wait for years
61451+ * using vertical blanks...
61452+ */
61453+
61454+ DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
61455+ (((cur_vblank = atomic_read(&dev->vbl_received)) -
61456+ *sequence) <= (1 << 23)));
61457+
61458+ *sequence = cur_vblank;
61459+ return ret;
61460+}
61461+
61462+static int
61463+via_driver_irq_wait(struct drm_device * dev, unsigned int irq, int force_sequence,
61464+ unsigned int *sequence)
61465+{
61466+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61467+ unsigned int cur_irq_sequence;
61468+ drm_via_irq_t *cur_irq;
61469+ int ret = 0;
61470+ maskarray_t *masks;
61471+ int real_irq;
61472+
61473+ DRM_DEBUG("%s\n", __FUNCTION__);
61474+
61475+ if (!dev_priv) {
61476+ DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
61477+ return -EINVAL;
61478+ }
61479+
61480+ if (irq >= drm_via_irq_num ) {
61481+ DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
61482+ irq);
61483+ return -EINVAL;
61484+ }
61485+
61486+ real_irq = dev_priv->irq_map[irq];
61487+
61488+ if (real_irq < 0) {
61489+ DRM_ERROR("%s Video IRQ %d not available on this hardware.\n",
61490+ __FUNCTION__, irq);
61491+ return -EINVAL;
61492+ }
61493+
61494+ masks = dev_priv->irq_masks;
61495+ cur_irq = dev_priv->via_irqs + real_irq;
61496+
61497+ if (masks[real_irq][2] && !force_sequence) {
61498+ DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
61499+ ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
61500+ masks[irq][4]));
61501+ cur_irq_sequence = atomic_read(&cur_irq->irq_received);
61502+ } else {
61503+ DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
61504+ (((cur_irq_sequence =
61505+ atomic_read(&cur_irq->irq_received)) -
61506+ *sequence) <= (1 << 23)));
61507+ }
61508+ *sequence = cur_irq_sequence;
61509+ return ret;
61510+}
61511+
61512+
61513+/*
61514+ * drm_dma.h hooks
61515+ */
61516+
61517+void via_driver_irq_preinstall(struct drm_device * dev)
61518+{
61519+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61520+ u32 status;
61521+ drm_via_irq_t *cur_irq;
61522+ int i;
61523+
61524+ DRM_DEBUG("driver_irq_preinstall: dev_priv: %p\n", dev_priv);
61525+ if (dev_priv) {
61526+ cur_irq = dev_priv->via_irqs;
61527+
61528+ dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
61529+ dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
61530+
61531+ if (dev_priv->chipset == VIA_PRO_GROUP_A ||
61532+ dev_priv->chipset == VIA_DX9_0) {
61533+ dev_priv->irq_masks = via_pro_group_a_irqs;
61534+ dev_priv->num_irqs = via_num_pro_group_a;
61535+ dev_priv->irq_map = via_irqmap_pro_group_a;
61536+ } else {
61537+ dev_priv->irq_masks = via_unichrome_irqs;
61538+ dev_priv->num_irqs = via_num_unichrome;
61539+ dev_priv->irq_map = via_irqmap_unichrome;
61540+ }
61541+
61542+ for(i=0; i < dev_priv->num_irqs; ++i) {
61543+ atomic_set(&cur_irq->irq_received, 0);
61544+ cur_irq->enable_mask = dev_priv->irq_masks[i][0];
61545+ cur_irq->pending_mask = dev_priv->irq_masks[i][1];
61546+ DRM_INIT_WAITQUEUE( &cur_irq->irq_queue );
61547+ dev_priv->irq_enable_mask |= cur_irq->enable_mask;
61548+ dev_priv->irq_pending_mask |= cur_irq->pending_mask;
61549+ cur_irq++;
61550+
61551+ DRM_DEBUG("Initializing IRQ %d\n", i);
61552+ }
61553+
61554+ dev_priv->last_vblank_valid = 0;
61555+
61556+ /* Clear VSync interrupt regs */
61557+ status = VIA_READ(VIA_REG_INTERRUPT);
61558+ VIA_WRITE(VIA_REG_INTERRUPT, status &
61559+ ~(dev_priv->irq_enable_mask));
61560+
61561+ /* Clear bits if they're already high */
61562+ viadrv_acknowledge_irqs(dev_priv);
61563+ }
61564+}
61565+
61566+void via_driver_irq_postinstall(struct drm_device * dev)
61567+{
61568+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61569+ u32 status;
61570+
61571+ DRM_DEBUG("via_driver_irq_postinstall\n");
61572+ if (dev_priv) {
61573+ status = VIA_READ(VIA_REG_INTERRUPT);
61574+ VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
61575+ | dev_priv->irq_enable_mask);
61576+
61577+ /* Some magic, oh for some data sheets ! */
61578+
61579+ VIA_WRITE8(0x83d4, 0x11);
61580+ VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
61581+
61582+ }
61583+}
61584+
61585+void via_driver_irq_uninstall(struct drm_device * dev)
61586+{
61587+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61588+ u32 status;
61589+
61590+ DRM_DEBUG("driver_irq_uninstall)\n");
61591+ if (dev_priv) {
61592+
61593+ /* Some more magic, oh for some data sheets ! */
61594+
61595+ VIA_WRITE8(0x83d4, 0x11);
61596+ VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
61597+
61598+ status = VIA_READ(VIA_REG_INTERRUPT);
61599+ VIA_WRITE(VIA_REG_INTERRUPT, status &
61600+ ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
61601+ }
61602+}
61603+
61604+int via_wait_irq(struct drm_device *dev, void *data, struct drm_file *file_priv)
61605+{
61606+ drm_via_irqwait_t *irqwait = data;
61607+ struct timeval now;
61608+ int ret = 0;
61609+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61610+ drm_via_irq_t *cur_irq = dev_priv->via_irqs;
61611+ int force_sequence;
61612+
61613+ if (!dev->irq)
61614+ return -EINVAL;
61615+
61616+ if (irqwait->request.irq >= dev_priv->num_irqs) {
61617+ DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
61618+ irqwait->request.irq);
61619+ return -EINVAL;
61620+ }
61621+
61622+ cur_irq += irqwait->request.irq;
61623+
61624+ switch (irqwait->request.type & ~VIA_IRQ_FLAGS_MASK) {
61625+ case VIA_IRQ_RELATIVE:
61626+ irqwait->request.sequence +=
61627+ atomic_read(&cur_irq->irq_received);
61628+ irqwait->request.type &= ~_DRM_VBLANK_RELATIVE;
61629+ case VIA_IRQ_ABSOLUTE:
61630+ break;
61631+ default:
61632+ return -EINVAL;
61633+ }
61634+
61635+ if (irqwait->request.type & VIA_IRQ_SIGNAL) {
61636+ DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
61637+ __FUNCTION__);
61638+ return -EINVAL;
61639+ }
61640+
61641+ force_sequence = (irqwait->request.type & VIA_IRQ_FORCE_SEQUENCE);
61642+
61643+ ret = via_driver_irq_wait(dev, irqwait->request.irq, force_sequence,
61644+ &irqwait->request.sequence);
61645+#ifdef __linux__
61646+ do_gettimeofday(&now);
61647+#else
61648+ microtime(&now);
61649+#endif
61650+ irqwait->reply.tval_sec = now.tv_sec;
61651+ irqwait->reply.tval_usec = now.tv_usec;
61652+
61653+ return ret;
61654+}
61655Index: git/shared-core/via_map.c
61656===================================================================
61657--- /dev/null 1970-01-01 00:00:00.000000000 +0000
61658+++ git/shared-core/via_map.c 2008-12-12 17:35:22.000000000 +0000
61659@@ -0,0 +1,143 @@
61660+/*
61661+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
61662+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
61663+ *
61664+ * Permission is hereby granted, free of charge, to any person obtaining a
61665+ * copy of this software and associated documentation files (the "Software"),
61666+ * to deal in the Software without restriction, including without limitation
61667+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
61668+ * and/or sell copies of the Software, and to permit persons to whom the
61669+ * Software is furnished to do so, subject to the following conditions:
61670+ *
61671+ * The above copyright notice and this permission notice (including the
61672+ * next paragraph) shall be included in all copies or substantial portions
61673+ * of the Software.
61674+ *
61675+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
61676+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
61677+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
61678+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
61679+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
61680+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
61681+ * DEALINGS IN THE SOFTWARE.
61682+ */
61683+#include "drmP.h"
61684+#include "via_drm.h"
61685+#include "via_drv.h"
61686+
61687+static int via_do_init_map(struct drm_device * dev, drm_via_init_t * init)
61688+{
61689+ drm_via_private_t *dev_priv = dev->dev_private;
61690+ int ret = 0;
61691+
61692+ DRM_DEBUG("%s\n", __FUNCTION__);
61693+
61694+ dev_priv->sarea = drm_getsarea(dev);
61695+ if (!dev_priv->sarea) {
61696+ DRM_ERROR("could not find sarea!\n");
61697+ dev->dev_private = (void *)dev_priv;
61698+ via_do_cleanup_map(dev);
61699+ return -EINVAL;
61700+ }
61701+
61702+ dev_priv->fb = drm_core_findmap(dev, init->fb_offset);
61703+ if (!dev_priv->fb) {
61704+ DRM_ERROR("could not find framebuffer!\n");
61705+ dev->dev_private = (void *)dev_priv;
61706+ via_do_cleanup_map(dev);
61707+ return -EINVAL;
61708+ }
61709+ dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
61710+ if (!dev_priv->mmio) {
61711+ DRM_ERROR("could not find mmio region!\n");
61712+ dev->dev_private = (void *)dev_priv;
61713+ via_do_cleanup_map(dev);
61714+ return -EINVAL;
61715+ }
61716+
61717+ dev_priv->sarea_priv =
61718+ (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle +
61719+ init->sarea_priv_offset);
61720+
61721+ dev_priv->agpAddr = init->agpAddr;
61722+
61723+ via_init_futex( dev_priv );
61724+#ifdef VIA_HAVE_DMABLIT
61725+ via_init_dmablit( dev );
61726+#endif
61727+#ifdef VIA_HAVE_FENCE
61728+ dev_priv->emit_0_sequence = 0;
61729+ dev_priv->have_idlelock = 0;
61730+ spin_lock_init(&dev_priv->fence_lock);
61731+ init_timer(&dev_priv->fence_timer);
61732+ dev_priv->fence_timer.function = &via_fence_timer;
61733+ dev_priv->fence_timer.data = (unsigned long) dev;
61734+#endif /* VIA_HAVE_FENCE */
61735+ dev->dev_private = (void *)dev_priv;
61736+#ifdef VIA_HAVE_BUFFER
61737+ ret = drm_bo_driver_init(dev);
61738+ if (ret)
61739+ DRM_ERROR("Could not initialize buffer object driver.\n");
61740+#endif
61741+ return ret;
61742+
61743+}
61744+
61745+int via_do_cleanup_map(struct drm_device * dev)
61746+{
61747+ via_dma_cleanup(dev);
61748+
61749+ return 0;
61750+}
61751+
61752+
61753+int via_map_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
61754+{
61755+ drm_via_init_t *init = data;
61756+
61757+ DRM_DEBUG("%s\n", __FUNCTION__);
61758+
61759+ switch (init->func) {
61760+ case VIA_INIT_MAP:
61761+ return via_do_init_map(dev, init);
61762+ case VIA_CLEANUP_MAP:
61763+ return via_do_cleanup_map(dev);
61764+ }
61765+
61766+ return -EINVAL;
61767+}
61768+
61769+int via_driver_load(struct drm_device *dev, unsigned long chipset)
61770+{
61771+ drm_via_private_t *dev_priv;
61772+ int ret = 0;
61773+
61774+ dev_priv = drm_calloc(1, sizeof(drm_via_private_t), DRM_MEM_DRIVER);
61775+ if (dev_priv == NULL)
61776+ return -ENOMEM;
61777+
61778+ dev->dev_private = (void *)dev_priv;
61779+
61780+ dev_priv->chipset = chipset;
61781+
61782+#ifdef VIA_HAVE_CORE_MM
61783+ ret = drm_sman_init(&dev_priv->sman, 2, 12, 8);
61784+ if (ret) {
61785+ drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
61786+ }
61787+#endif
61788+ return ret;
61789+}
61790+
61791+int via_driver_unload(struct drm_device *dev)
61792+{
61793+ drm_via_private_t *dev_priv = dev->dev_private;
61794+
61795+#ifdef VIA_HAVE_CORE_MM
61796+ drm_sman_takedown(&dev_priv->sman);
61797+#endif
61798+ drm_free(dev_priv, sizeof(drm_via_private_t), DRM_MEM_DRIVER);
61799+
61800+ return 0;
61801+}
61802+
61803Index: git/shared-core/via_mm.c
61804===================================================================
61805--- /dev/null 1970-01-01 00:00:00.000000000 +0000
61806+++ git/shared-core/via_mm.c 2008-12-12 17:35:22.000000000 +0000
61807@@ -0,0 +1,347 @@
61808+/*
61809+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
61810+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
61811+ *
61812+ * Permission is hereby granted, free of charge, to any person obtaining a
61813+ * copy of this software and associated documentation files (the "Software"),
61814+ * to deal in the Software without restriction, including without limitation
61815+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
61816+ * and/or sell copies of the Software, and to permit persons to whom the
61817+ * Software is furnished to do so, subject to the following conditions:
61818+ *
61819+ * The above copyright notice and this permission notice (including the
61820+ * next paragraph) shall be included in all copies or substantial portions
61821+ * of the Software.
61822+ *
61823+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
61824+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
61825+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
61826+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
61827+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
61828+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
61829+ * DEALINGS IN THE SOFTWARE.
61830+ */
61831+#include "drmP.h"
61832+#include "via_drm.h"
61833+#include "via_drv.h"
61834+#include "via_ds.h"
61835+#include "via_mm.h"
61836+
61837+#define MAX_CONTEXT 100
61838+
61839+typedef struct {
61840+ int used;
61841+ int context;
61842+ set_t *sets[2]; /* 0 for frame buffer, 1 for AGP , 2 for System */
61843+} via_context_t;
61844+
61845+static via_context_t global_ppriv[MAX_CONTEXT];
61846+
61847+static int via_agp_alloc(drm_via_mem_t * mem);
61848+static int via_agp_free(drm_via_mem_t * mem);
61849+static int via_fb_alloc(drm_via_mem_t * mem);
61850+static int via_fb_free(drm_via_mem_t * mem);
61851+
61852+static int add_alloc_set(int context, int type, unsigned long val)
61853+{
61854+ int i, retval = 0;
61855+
61856+ for (i = 0; i < MAX_CONTEXT; i++) {
61857+ if (global_ppriv[i].used && global_ppriv[i].context == context) {
61858+ retval = via_setAdd(global_ppriv[i].sets[type], val);
61859+ break;
61860+ }
61861+ }
61862+
61863+ return retval;
61864+}
61865+
61866+static int del_alloc_set(int context, int type, unsigned long val)
61867+{
61868+ int i, retval = 0;
61869+
61870+ for (i = 0; i < MAX_CONTEXT; i++)
61871+ if (global_ppriv[i].used && global_ppriv[i].context == context) {
61872+ retval = via_setDel(global_ppriv[i].sets[type], val);
61873+ break;
61874+ }
61875+
61876+ return retval;
61877+}
61878+
61879+/* agp memory management */
61880+static memHeap_t *AgpHeap = NULL;
61881+
61882+int via_agp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
61883+{
61884+ drm_via_agp_t *agp = data;
61885+
61886+ AgpHeap = via_mmInit(agp->offset, agp->size);
61887+
61888+ DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp->offset,
61889+ (unsigned long)agp->size);
61890+
61891+ return 0;
61892+}
61893+
61894+/* fb memory management */
61895+static memHeap_t *FBHeap = NULL;
61896+
61897+int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
61898+{
61899+ drm_via_fb_t *fb = data;
61900+
61901+ FBHeap = via_mmInit(fb.offset, fb.size);
61902+
61903+ DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset,
61904+ (unsigned long)fb.size);
61905+
61906+ return 0;
61907+}
61908+
61909+int via_init_context(struct drm_device *dev, int context)
61910+{
61911+ int i;
61912+
61913+ for (i = 0; i < MAX_CONTEXT; i++)
61914+ if (global_ppriv[i].used &&
61915+ (global_ppriv[i].context == context))
61916+ break;
61917+
61918+ if (i >= MAX_CONTEXT) {
61919+ for (i = 0; i < MAX_CONTEXT; i++) {
61920+ if (!global_ppriv[i].used) {
61921+ global_ppriv[i].context = context;
61922+ global_ppriv[i].used = 1;
61923+ global_ppriv[i].sets[0] = via_setInit();
61924+ global_ppriv[i].sets[1] = via_setInit();
61925+ DRM_DEBUG("init allocation set, socket=%d,"
61926+ " context = %d\n", i, context);
61927+ break;
61928+ }
61929+ }
61930+
61931+ if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
61932+ (global_ppriv[i].sets[1] == NULL)) {
61933+ return 0;
61934+ }
61935+ }
61936+
61937+ return 1;
61938+}
61939+
61940+int via_final_context(struct drm_device *dev, int context)
61941+{
61942+ int i;
61943+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
61944+
61945+ for (i = 0; i < MAX_CONTEXT; i++)
61946+ if (global_ppriv[i].used &&
61947+ (global_ppriv[i].context == context))
61948+ break;
61949+
61950+ if (i < MAX_CONTEXT) {
61951+ set_t *set;
61952+ ITEM_TYPE item;
61953+ int retval;
61954+
61955+ DRM_DEBUG("find socket %d, context = %d\n", i, context);
61956+
61957+ /* Video Memory */
61958+ set = global_ppriv[i].sets[0];
61959+ retval = via_setFirst(set, &item);
61960+ while (retval) {
61961+ DRM_DEBUG("free video memory 0x%lx\n", item);
61962+ via_mmFreeMem((PMemBlock) item);
61963+ retval = via_setNext(set, &item);
61964+ }
61965+ via_setDestroy(set);
61966+
61967+ /* AGP Memory */
61968+ set = global_ppriv[i].sets[1];
61969+ retval = via_setFirst(set, &item);
61970+ while (retval) {
61971+ DRM_DEBUG("free agp memory 0x%lx\n", item);
61972+ via_mmFreeMem((PMemBlock) item);
61973+ retval = via_setNext(set, &item);
61974+ }
61975+ via_setDestroy(set);
61976+ global_ppriv[i].used = 0;
61977+ }
61978+ via_release_futex(dev_priv, context);
61979+
61980+#if defined(__linux__)
61981+ /* Linux specific until context tracking code gets ported to BSD */
61982+ /* Last context, perform cleanup */
61983+ if (dev->ctx_count == 1 && dev->dev_private) {
61984+ DRM_DEBUG("Last Context\n");
61985+ if (dev->irq)
61986+ drm_irq_uninstall(dev);
61987+
61988+ via_cleanup_futex(dev_priv);
61989+ via_do_cleanup_map(dev);
61990+ }
61991+#endif
61992+
61993+ return 1;
61994+}
61995+
61996+int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
61997+{
61998+ drm_via_mem_t *mem = data;
61999+
62000+ switch (mem.type) {
62001+ case VIA_MEM_VIDEO:
62002+ if (via_fb_alloc(mem) < 0)
62003+ return -EFAULT;
62004+ return 0;
62005+ case VIA_MEM_AGP:
62006+ if (via_agp_alloc(mem) < 0)
62007+ return -EFAULT;
62008+ return 0;
62009+ }
62010+
62011+ return -EFAULT;
62012+}
62013+
62014+static int via_fb_alloc(drm_via_mem_t * mem)
62015+{
62016+ drm_via_mm_t fb;
62017+ PMemBlock block;
62018+ int retval = 0;
62019+
62020+ if (!FBHeap)
62021+ return -1;
62022+
62023+ fb.size = mem->size;
62024+ fb.context = mem->context;
62025+
62026+ block = via_mmAllocMem(FBHeap, fb.size, 5, 0);
62027+ if (block) {
62028+ fb.offset = block->ofs;
62029+ fb.free = (unsigned long)block;
62030+ if (!add_alloc_set(fb.context, VIA_MEM_VIDEO, fb.free)) {
62031+ DRM_DEBUG("adding to allocation set fails\n");
62032+ via_mmFreeMem((PMemBlock) fb.free);
62033+ retval = -1;
62034+ }
62035+ } else {
62036+ fb.offset = 0;
62037+ fb.size = 0;
62038+ fb.free = 0;
62039+ retval = -1;
62040+ }
62041+
62042+ mem->offset = fb.offset;
62043+ mem->index = fb.free;
62044+
62045+ DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size,
62046+ (int)fb.offset);
62047+
62048+ return retval;
62049+}
62050+
62051+static int via_agp_alloc(drm_via_mem_t * mem)
62052+{
62053+ drm_via_mm_t agp;
62054+ PMemBlock block;
62055+ int retval = 0;
62056+
62057+ if (!AgpHeap)
62058+ return -1;
62059+
62060+ agp.size = mem->size;
62061+ agp.context = mem->context;
62062+
62063+ block = via_mmAllocMem(AgpHeap, agp.size, 5, 0);
62064+ if (block) {
62065+ agp.offset = block->ofs;
62066+ agp.free = (unsigned long)block;
62067+ if (!add_alloc_set(agp.context, VIA_MEM_AGP, agp.free)) {
62068+ DRM_DEBUG("adding to allocation set fails\n");
62069+ via_mmFreeMem((PMemBlock) agp.free);
62070+ retval = -1;
62071+ }
62072+ } else {
62073+ agp.offset = 0;
62074+ agp.size = 0;
62075+ agp.free = 0;
62076+ }
62077+
62078+ mem->offset = agp.offset;
62079+ mem->index = agp.free;
62080+
62081+ DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp.size,
62082+ (unsigned int)agp.offset);
62083+ return retval;
62084+}
62085+
62086+int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
62087+{
62088+ drm_via_mem_t *mem = data;
62089+
62090+ switch (mem->type) {
62091+
62092+ case VIA_MEM_VIDEO:
62093+ if (via_fb_free(mem) == 0)
62094+ return 0;
62095+ break;
62096+ case VIA_MEM_AGP:
62097+ if (via_agp_free(mem) == 0)
62098+ return 0;
62099+ break;
62100+ }
62101+
62102+ return -EFAULT;
62103+}
62104+
62105+static int via_fb_free(drm_via_mem_t * mem)
62106+{
62107+ drm_via_mm_t fb;
62108+ int retval = 0;
62109+
62110+ if (!FBHeap) {
62111+ return -1;
62112+ }
62113+
62114+ fb.free = mem->index;
62115+ fb.context = mem->context;
62116+
62117+ if (!fb.free) {
62118+ return -1;
62119+
62120+ }
62121+
62122+ via_mmFreeMem((PMemBlock) fb.free);
62123+
62124+ if (!del_alloc_set(fb.context, VIA_MEM_VIDEO, fb.free)) {
62125+ retval = -1;
62126+ }
62127+
62128+ DRM_DEBUG("free fb, free = %ld\n", fb.free);
62129+
62130+ return retval;
62131+}
62132+
62133+static int via_agp_free(drm_via_mem_t * mem)
62134+{
62135+ drm_via_mm_t agp;
62136+
62137+ int retval = 0;
62138+
62139+ agp.free = mem->index;
62140+ agp.context = mem->context;
62141+
62142+ if (!agp.free)
62143+ return -1;
62144+
62145+ via_mmFreeMem((PMemBlock) agp.free);
62146+
62147+ if (!del_alloc_set(agp.context, VIA_MEM_AGP, agp.free)) {
62148+ retval = -1;
62149+ }
62150+
62151+ DRM_DEBUG("free agp, free = %ld\n", agp.nfree);
62152+
62153+ return retval;
62154+}
62155Index: git/shared-core/via_mm.h
62156===================================================================
62157--- /dev/null 1970-01-01 00:00:00.000000000 +0000
62158+++ git/shared-core/via_mm.h 2008-12-12 17:35:22.000000000 +0000
62159@@ -0,0 +1,40 @@
62160+/*
62161+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
62162+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
62163+ *
62164+ * Permission is hereby granted, free of charge, to any person obtaining a
62165+ * copy of this software and associated documentation files (the "Software"),
62166+ * to deal in the Software without restriction, including without limitation
62167+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
62168+ * and/or sell copies of the Software, and to permit persons to whom the
62169+ * Software is furnished to do so, subject to the following conditions:
62170+ *
62171+ * The above copyright notice and this permission notice (including the
62172+ * next paragraph) shall be included in all copies or substantial portions
62173+ * of the Software.
62174+ *
62175+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
62176+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
62177+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
62178+ * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
62179+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
62180+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
62181+ * DEALINGS IN THE SOFTWARE.
62182+ */
62183+#ifndef _via_drm_mm_h_
62184+#define _via_drm_mm_h_
62185+
62186+typedef struct {
62187+ unsigned int context;
62188+ unsigned int size;
62189+ unsigned long offset;
62190+ unsigned long free;
62191+} drm_via_mm_t;
62192+
62193+typedef struct {
62194+ unsigned int size;
62195+ unsigned long handle;
62196+ void *virtual;
62197+} drm_via_dma_t;
62198+
62199+#endif
62200Index: git/shared-core/via_verifier.c
62201===================================================================
62202--- /dev/null 1970-01-01 00:00:00.000000000 +0000
62203+++ git/shared-core/via_verifier.c 2008-12-12 17:35:22.000000000 +0000
62204@@ -0,0 +1,1121 @@
62205+/*
62206+ * Copyright 2004 The Unichrome Project. All Rights Reserved.
62207+ * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
62208+ *
62209+ * Permission is hereby granted, free of charge, to any person obtaining a
62210+ * copy of this software and associated documentation files (the "Software"),
62211+ * to deal in the Software without restriction, including without limitation
62212+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
62213+ * and/or sell copies of the Software, and to permit persons to whom the
62214+ * Software is furnished to do so, subject to the following conditions:
62215+ *
62216+ * The above copyright notice and this permission notice (including the
62217+ * next paragraph) shall be included in all copies or substantial portions
62218+ * of the Software.
62219+ *
62220+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
62221+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
62222+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
62223+ * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
62224+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
62225+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
62226+ * DEALINGS IN THE SOFTWARE.
62227+ *
62228+ * Author: Thomas Hellstrom 2004, 2005.
62229+ * This code was written using docs obtained under NDA from VIA Inc.
62230+ *
62231+ * Don't run this code directly on an AGP buffer. Due to cache problems it will
62232+ * be very slow.
62233+ */
62234+
62235+#include "via_3d_reg.h"
62236+#include "drmP.h"
62237+#include "drm.h"
62238+#include "via_drm.h"
62239+#include "via_verifier.h"
62240+#include "via_drv.h"
62241+
62242+typedef enum {
62243+ state_command,
62244+ state_header2,
62245+ state_header1,
62246+ state_vheader5,
62247+ state_vheader6,
62248+ state_error
62249+} verifier_state_t;
62250+
62251+typedef enum {
62252+ no_check = 0,
62253+ check_for_header2,
62254+ check_for_header1,
62255+ check_for_header2_err,
62256+ check_for_header1_err,
62257+ check_for_fire,
62258+ check_z_buffer_addr0,
62259+ check_z_buffer_addr1,
62260+ check_z_buffer_addr_mode,
62261+ check_destination_addr0,
62262+ check_destination_addr1,
62263+ check_destination_addr_mode,
62264+ check_for_dummy,
62265+ check_for_dd,
62266+ check_texture_addr0,
62267+ check_texture_addr1,
62268+ check_texture_addr2,
62269+ check_texture_addr3,
62270+ check_texture_addr4,
62271+ check_texture_addr5,
62272+ check_texture_addr6,
62273+ check_texture_addr7,
62274+ check_texture_addr8,
62275+ check_texture_addr_mode,
62276+ check_for_vertex_count,
62277+ check_number_texunits,
62278+ forbidden_command
62279+} hazard_t;
62280+
62281+/*
62282+ * Associates each hazard above with a possible multi-command
62283+ * sequence. For example an address that is split over multiple
62284+ * commands and that needs to be checked at the first command
62285+ * that does not include any part of the address.
62286+ */
62287+
62288+static drm_via_sequence_t seqs[] = {
62289+ no_sequence,
62290+ no_sequence,
62291+ no_sequence,
62292+ no_sequence,
62293+ no_sequence,
62294+ no_sequence,
62295+ z_address,
62296+ z_address,
62297+ z_address,
62298+ dest_address,
62299+ dest_address,
62300+ dest_address,
62301+ no_sequence,
62302+ no_sequence,
62303+ tex_address,
62304+ tex_address,
62305+ tex_address,
62306+ tex_address,
62307+ tex_address,
62308+ tex_address,
62309+ tex_address,
62310+ tex_address,
62311+ tex_address,
62312+ tex_address,
62313+ no_sequence
62314+};
62315+
62316+typedef struct {
62317+ unsigned int code;
62318+ hazard_t hz;
62319+} hz_init_t;
62320+
62321+static hz_init_t init_table1[] = {
62322+ {0xf2, check_for_header2_err},
62323+ {0xf0, check_for_header1_err},
62324+ {0xee, check_for_fire},
62325+ {0xcc, check_for_dummy},
62326+ {0xdd, check_for_dd},
62327+ {0x00, no_check},
62328+ {0x10, check_z_buffer_addr0},
62329+ {0x11, check_z_buffer_addr1},
62330+ {0x12, check_z_buffer_addr_mode},
62331+ {0x13, no_check},
62332+ {0x14, no_check},
62333+ {0x15, no_check},
62334+ {0x23, no_check},
62335+ {0x24, no_check},
62336+ {0x33, no_check},
62337+ {0x34, no_check},
62338+ {0x35, no_check},
62339+ {0x36, no_check},
62340+ {0x37, no_check},
62341+ {0x38, no_check},
62342+ {0x39, no_check},
62343+ {0x3A, no_check},
62344+ {0x3B, no_check},
62345+ {0x3C, no_check},
62346+ {0x3D, no_check},
62347+ {0x3E, no_check},
62348+ {0x40, check_destination_addr0},
62349+ {0x41, check_destination_addr1},
62350+ {0x42, check_destination_addr_mode},
62351+ {0x43, no_check},
62352+ {0x44, no_check},
62353+ {0x50, no_check},
62354+ {0x51, no_check},
62355+ {0x52, no_check},
62356+ {0x53, no_check},
62357+ {0x54, no_check},
62358+ {0x55, no_check},
62359+ {0x56, no_check},
62360+ {0x57, no_check},
62361+ {0x58, no_check},
62362+ {0x70, no_check},
62363+ {0x71, no_check},
62364+ {0x78, no_check},
62365+ {0x79, no_check},
62366+ {0x7A, no_check},
62367+ {0x7B, no_check},
62368+ {0x7C, no_check},
62369+ {0x7D, check_for_vertex_count}
62370+};
62371+
62372+static hz_init_t init_table2[] = {
62373+ {0xf2, check_for_header2_err},
62374+ {0xf0, check_for_header1_err},
62375+ {0xee, check_for_fire},
62376+ {0xcc, check_for_dummy},
62377+ {0x00, check_texture_addr0},
62378+ {0x01, check_texture_addr0},
62379+ {0x02, check_texture_addr0},
62380+ {0x03, check_texture_addr0},
62381+ {0x04, check_texture_addr0},
62382+ {0x05, check_texture_addr0},
62383+ {0x06, check_texture_addr0},
62384+ {0x07, check_texture_addr0},
62385+ {0x08, check_texture_addr0},
62386+ {0x09, check_texture_addr0},
62387+ {0x20, check_texture_addr1},
62388+ {0x21, check_texture_addr1},
62389+ {0x22, check_texture_addr1},
62390+ {0x23, check_texture_addr4},
62391+ {0x2B, check_texture_addr3},
62392+ {0x2C, check_texture_addr3},
62393+ {0x2D, check_texture_addr3},
62394+ {0x2E, check_texture_addr3},
62395+ {0x2F, check_texture_addr3},
62396+ {0x30, check_texture_addr3},
62397+ {0x31, check_texture_addr3},
62398+ {0x32, check_texture_addr3},
62399+ {0x33, check_texture_addr3},
62400+ {0x34, check_texture_addr3},
62401+ {0x4B, check_texture_addr5},
62402+ {0x4C, check_texture_addr6},
62403+ {0x51, check_texture_addr7},
62404+ {0x52, check_texture_addr8},
62405+ {0x77, check_texture_addr2},
62406+ {0x78, no_check},
62407+ {0x79, no_check},
62408+ {0x7A, no_check},
62409+ {0x7B, check_texture_addr_mode},
62410+ {0x7C, no_check},
62411+ {0x7D, no_check},
62412+ {0x7E, no_check},
62413+ {0x7F, no_check},
62414+ {0x80, no_check},
62415+ {0x81, no_check},
62416+ {0x82, no_check},
62417+ {0x83, no_check},
62418+ {0x85, no_check},
62419+ {0x86, no_check},
62420+ {0x87, no_check},
62421+ {0x88, no_check},
62422+ {0x89, no_check},
62423+ {0x8A, no_check},
62424+ {0x90, no_check},
62425+ {0x91, no_check},
62426+ {0x92, no_check},
62427+ {0x93, no_check}
62428+};
62429+
62430+static hz_init_t init_table3[] = {
62431+ {0xf2, check_for_header2_err},
62432+ {0xf0, check_for_header1_err},
62433+ {0xcc, check_for_dummy},
62434+ {0x00, check_number_texunits}
62435+};
62436+
62437+static hazard_t table1[256];
62438+static hazard_t table2[256];
62439+static hazard_t table3[256];
62440+
62441+static __inline__ int
62442+eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words)
62443+{
62444+ if ((buf_end - *buf) >= num_words) {
62445+ *buf += num_words;
62446+ return 0;
62447+ }
62448+ DRM_ERROR("Illegal termination of DMA command buffer\n");
62449+ return 1;
62450+}
62451+
62452+/*
62453+ * Partially stolen from drm_memory.h
62454+ */
62455+
62456+static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
62457+ unsigned long offset,
62458+ unsigned long size,
62459+ struct drm_device * dev)
62460+{
62461+#ifdef __linux__
62462+ struct drm_map_list *r_list;
62463+#endif
62464+ drm_local_map_t *map = seq->map_cache;
62465+
62466+ if (map && map->offset <= offset
62467+ && (offset + size) <= (map->offset + map->size)) {
62468+ return map;
62469+ }
62470+#ifdef __linux__
62471+ list_for_each_entry(r_list, &dev->maplist, head) {
62472+ map = r_list->map;
62473+ if (!map)
62474+ continue;
62475+#else
62476+ TAILQ_FOREACH(map, &dev->maplist, link) {
62477+#endif
62478+ if (map->offset <= offset
62479+ && (offset + size) <= (map->offset + map->size)
62480+ && !(map->flags & _DRM_RESTRICTED)
62481+ && (map->type == _DRM_AGP)) {
62482+ seq->map_cache = map;
62483+ return map;
62484+ }
62485+ }
62486+ return NULL;
62487+}
62488+
62489+/*
62490+ * Require that all AGP texture levels reside in the same AGP map which should
62491+ * be mappable by the client. This is not a big restriction.
62492+ * FIXME: To actually enforce this security policy strictly, drm_rmmap
62493+ * would have to wait for dma quiescent before removing an AGP map.
62494+ * The via_drm_lookup_agp_map call in reality seems to take
62495+ * very little CPU time.
62496+ */
62497+
62498+static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq)
62499+{
62500+ switch (cur_seq->unfinished) {
62501+ case z_address:
62502+ DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
62503+ break;
62504+ case dest_address:
62505+ DRM_DEBUG("Destination start address is 0x%x\n",
62506+ cur_seq->d_addr);
62507+ break;
62508+ case tex_address:
62509+ if (cur_seq->agp_texture) {
62510+ unsigned start =
62511+ cur_seq->tex_level_lo[cur_seq->texture];
62512+ unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
62513+ unsigned long lo = ~0, hi = 0, tmp;
62514+ uint32_t *addr, *pitch, *height, tex;
62515+ unsigned i;
62516+ int npot;
62517+
62518+ if (end > 9)
62519+ end = 9;
62520+ if (start > 9)
62521+ start = 9;
62522+
62523+ addr =
62524+ &(cur_seq->t_addr[tex = cur_seq->texture][start]);
62525+ pitch = &(cur_seq->pitch[tex][start]);
62526+ height = &(cur_seq->height[tex][start]);
62527+ npot = cur_seq->tex_npot[tex];
62528+ for (i = start; i <= end; ++i) {
62529+ tmp = *addr++;
62530+ if (tmp < lo)
62531+ lo = tmp;
62532+ if (i == 0 && npot)
62533+ tmp += (*height++ * *pitch++);
62534+ else
62535+ tmp += (*height++ << *pitch++);
62536+ if (tmp > hi)
62537+ hi = tmp;
62538+ }
62539+
62540+ if (!via_drm_lookup_agp_map
62541+ (cur_seq, lo, hi - lo, cur_seq->dev)) {
62542+ DRM_ERROR
62543+ ("AGP texture is not in allowed map\n");
62544+ return 2;
62545+ }
62546+ }
62547+ break;
62548+ default:
62549+ break;
62550+ }
62551+ cur_seq->unfinished = no_sequence;
62552+ return 0;
62553+}
62554+
62555+static __inline__ int
62556+investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq)
62557+{
62558+ register uint32_t tmp, *tmp_addr;
62559+
62560+ if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
62561+ int ret;
62562+ if ((ret = finish_current_sequence(cur_seq)))
62563+ return ret;
62564+ }
62565+
62566+ switch (hz) {
62567+ case check_for_header2:
62568+ if (cmd == HALCYON_HEADER2)
62569+ return 1;
62570+ return 0;
62571+ case check_for_header1:
62572+ if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
62573+ return 1;
62574+ return 0;
62575+ case check_for_header2_err:
62576+ if (cmd == HALCYON_HEADER2)
62577+ return 1;
62578+ DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
62579+ break;
62580+ case check_for_header1_err:
62581+ if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
62582+ return 1;
62583+ DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
62584+ break;
62585+ case check_for_fire:
62586+ if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD)
62587+ return 1;
62588+ DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
62589+ break;
62590+ case check_for_dummy:
62591+ if (HC_DUMMY == cmd)
62592+ return 0;
62593+ DRM_ERROR("Illegal DMA HC_DUMMY command\n");
62594+ break;
62595+ case check_for_dd:
62596+ if (0xdddddddd == cmd)
62597+ return 0;
62598+ DRM_ERROR("Illegal DMA 0xdddddddd command\n");
62599+ break;
62600+ case check_z_buffer_addr0:
62601+ cur_seq->unfinished = z_address;
62602+ cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
62603+ (cmd & 0x00FFFFFF);
62604+ return 0;
62605+ case check_z_buffer_addr1:
62606+ cur_seq->unfinished = z_address;
62607+ cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
62608+ ((cmd & 0xFF) << 24);
62609+ return 0;
62610+ case check_z_buffer_addr_mode:
62611+ cur_seq->unfinished = z_address;
62612+ if ((cmd & 0x0000C000) == 0)
62613+ return 0;
62614+ DRM_ERROR("Attempt to place Z buffer in system memory\n");
62615+ return 2;
62616+ case check_destination_addr0:
62617+ cur_seq->unfinished = dest_address;
62618+ cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
62619+ (cmd & 0x00FFFFFF);
62620+ return 0;
62621+ case check_destination_addr1:
62622+ cur_seq->unfinished = dest_address;
62623+ cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
62624+ ((cmd & 0xFF) << 24);
62625+ return 0;
62626+ case check_destination_addr_mode:
62627+ cur_seq->unfinished = dest_address;
62628+ if ((cmd & 0x0000C000) == 0)
62629+ return 0;
62630+ DRM_ERROR
62631+ ("Attempt to place 3D drawing buffer in system memory\n");
62632+ return 2;
62633+ case check_texture_addr0:
62634+ cur_seq->unfinished = tex_address;
62635+ tmp = (cmd >> 24);
62636+ tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
62637+ *tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF);
62638+ return 0;
62639+ case check_texture_addr1:
62640+ cur_seq->unfinished = tex_address;
62641+ tmp = ((cmd >> 24) - 0x20);
62642+ tmp += tmp << 1;
62643+ tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
62644+ *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
62645+ tmp_addr++;
62646+ *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16);
62647+ tmp_addr++;
62648+ *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8);
62649+ return 0;
62650+ case check_texture_addr2:
62651+ cur_seq->unfinished = tex_address;
62652+ cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F;
62653+ cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6;
62654+ return 0;
62655+ case check_texture_addr3:
62656+ cur_seq->unfinished = tex_address;
62657+ tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit);
62658+ if (tmp == 0 &&
62659+ (cmd & HC_HTXnEnPit_MASK)) {
62660+ cur_seq->pitch[cur_seq->texture][tmp] =
62661+ (cmd & HC_HTXnLnPit_MASK);
62662+ cur_seq->tex_npot[cur_seq->texture] = 1;
62663+ } else {
62664+ cur_seq->pitch[cur_seq->texture][tmp] =
62665+ (cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT;
62666+ cur_seq->tex_npot[cur_seq->texture] = 0;
62667+ if (cmd & 0x000FFFFF) {
62668+ DRM_ERROR
62669+ ("Unimplemented texture level 0 pitch mode.\n");
62670+ return 2;
62671+ }
62672+ }
62673+ return 0;
62674+ case check_texture_addr4:
62675+ cur_seq->unfinished = tex_address;
62676+ tmp_addr = &cur_seq->t_addr[cur_seq->texture][9];
62677+ *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
62678+ return 0;
62679+ case check_texture_addr5:
62680+ case check_texture_addr6:
62681+ cur_seq->unfinished = tex_address;
62682+ /*
62683+ * Texture width. We don't care since we have the pitch.
62684+ */
62685+ return 0;
62686+ case check_texture_addr7:
62687+ cur_seq->unfinished = tex_address;
62688+ tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
62689+ tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20);
62690+ tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16);
62691+ tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12);
62692+ tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8);
62693+ tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4);
62694+ tmp_addr[0] = 1 << (cmd & 0x0000000F);
62695+ return 0;
62696+ case check_texture_addr8:
62697+ cur_seq->unfinished = tex_address;
62698+ tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
62699+ tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
62700+ tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
62701+ tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
62702+ tmp_addr[6] = 1 << (cmd & 0x0000000F);
62703+ return 0;
62704+ case check_texture_addr_mode:
62705+ cur_seq->unfinished = tex_address;
62706+ if (2 == (tmp = cmd & 0x00000003)) {
62707+ DRM_ERROR
62708+ ("Attempt to fetch texture from system memory.\n");
62709+ return 2;
62710+ }
62711+ cur_seq->agp_texture = (tmp == 3);
62712+ cur_seq->tex_palette_size[cur_seq->texture] =
62713+ (cmd >> 16) & 0x000000007;
62714+ return 0;
62715+ case check_for_vertex_count:
62716+ cur_seq->vertex_count = cmd & 0x0000FFFF;
62717+ return 0;
62718+ case check_number_texunits:
62719+ cur_seq->multitex = (cmd >> 3) & 1;
62720+ return 0;
62721+ default:
62722+ DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
62723+ return 2;
62724+ }
62725+ return 2;
62726+}
62727+
62728+static __inline__ int
62729+via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end,
62730+ drm_via_state_t * cur_seq)
62731+{
62732+ drm_via_private_t *dev_priv =
62733+ (drm_via_private_t *) cur_seq->dev->dev_private;
62734+ uint32_t a_fire, bcmd, dw_count;
62735+ int ret = 0;
62736+ int have_fire;
62737+ const uint32_t *buf = *buffer;
62738+
62739+ while (buf < buf_end) {
62740+ have_fire = 0;
62741+ if ((buf_end - buf) < 2) {
62742+ DRM_ERROR
62743+ ("Unexpected termination of primitive list.\n");
62744+ ret = 1;
62745+ break;
62746+ }
62747+ if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB)
62748+ break;
62749+ bcmd = *buf++;
62750+ if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
62751+ DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
62752+ *buf);
62753+ ret = 1;
62754+ break;
62755+ }
62756+ a_fire =
62757+ *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK |
62758+ HC_HE3Fire_MASK;
62759+
62760+ /*
62761+ * How many dwords per vertex ?
62762+ */
62763+
62764+ if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
62765+ DRM_ERROR("Illegal B command vertex data for AGP.\n");
62766+ ret = 1;
62767+ break;
62768+ }
62769+
62770+ dw_count = 0;
62771+ if (bcmd & (1 << 7))
62772+ dw_count += (cur_seq->multitex) ? 2 : 1;
62773+ if (bcmd & (1 << 8))
62774+ dw_count += (cur_seq->multitex) ? 2 : 1;
62775+ if (bcmd & (1 << 9))
62776+ dw_count++;
62777+ if (bcmd & (1 << 10))
62778+ dw_count++;
62779+ if (bcmd & (1 << 11))
62780+ dw_count++;
62781+ if (bcmd & (1 << 12))
62782+ dw_count++;
62783+ if (bcmd & (1 << 13))
62784+ dw_count++;
62785+ if (bcmd & (1 << 14))
62786+ dw_count++;
62787+
62788+ while (buf < buf_end) {
62789+ if (*buf == a_fire) {
62790+ if (dev_priv->num_fire_offsets >=
62791+ VIA_FIRE_BUF_SIZE) {
62792+ DRM_ERROR("Fire offset buffer full.\n");
62793+ ret = 1;
62794+ break;
62795+ }
62796+ dev_priv->fire_offsets[dev_priv->
62797+ num_fire_offsets++] =
62798+ buf;
62799+ have_fire = 1;
62800+ buf++;
62801+ if (buf < buf_end && *buf == a_fire)
62802+ buf++;
62803+ break;
62804+ }
62805+ if ((*buf == HALCYON_HEADER2) ||
62806+ ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
62807+ DRM_ERROR("Missing Vertex Fire command, "
62808+ "Stray Vertex Fire command or verifier "
62809+ "lost sync.\n");
62810+ ret = 1;
62811+ break;
62812+ }
62813+ if ((ret = eat_words(&buf, buf_end, dw_count)))
62814+ break;
62815+ }
62816+ if (buf >= buf_end && !have_fire) {
62817+ DRM_ERROR("Missing Vertex Fire command or verifier "
62818+ "lost sync.\n");
62819+ ret = 1;
62820+ break;
62821+ }
62822+ if (cur_seq->agp && ((buf - cur_seq->buf_start) & 0x01)) {
62823+ DRM_ERROR("AGP Primitive list end misaligned.\n");
62824+ ret = 1;
62825+ break;
62826+ }
62827+ }
62828+ *buffer = buf;
62829+ return ret;
62830+}
62831+
62832+static __inline__ verifier_state_t
62833+via_check_header2(uint32_t const **buffer, const uint32_t * buf_end,
62834+ drm_via_state_t * hc_state)
62835+{
62836+ uint32_t cmd;
62837+ int hz_mode;
62838+ hazard_t hz;
62839+ const uint32_t *buf = *buffer;
62840+ const hazard_t *hz_table;
62841+
62842+ if ((buf_end - buf) < 2) {
62843+ DRM_ERROR
62844+ ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
62845+ return state_error;
62846+ }
62847+ buf++;
62848+ cmd = (*buf++ & 0xFFFF0000) >> 16;
62849+
62850+ switch (cmd) {
62851+ case HC_ParaType_CmdVdata:
62852+ if (via_check_prim_list(&buf, buf_end, hc_state))
62853+ return state_error;
62854+ *buffer = buf;
62855+ return state_command;
62856+ case HC_ParaType_NotTex:
62857+ hz_table = table1;
62858+ break;
62859+ case HC_ParaType_Tex:
62860+ hc_state->texture = 0;
62861+ hz_table = table2;
62862+ break;
62863+ case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)):
62864+ hc_state->texture = 1;
62865+ hz_table = table2;
62866+ break;
62867+ case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)):
62868+ hz_table = table3;
62869+ break;
62870+ case HC_ParaType_Auto:
62871+ if (eat_words(&buf, buf_end, 2))
62872+ return state_error;
62873+ *buffer = buf;
62874+ return state_command;
62875+ case (HC_ParaType_Palette | (HC_SubType_Stipple << 8)):
62876+ if (eat_words(&buf, buf_end, 32))
62877+ return state_error;
62878+ *buffer = buf;
62879+ return state_command;
62880+ case (HC_ParaType_Palette | (HC_SubType_TexPalette0 << 8)):
62881+ case (HC_ParaType_Palette | (HC_SubType_TexPalette1 << 8)):
62882+ DRM_ERROR("Texture palettes are rejected because of "
62883+ "lack of info how to determine their size.\n");
62884+ return state_error;
62885+ case (HC_ParaType_Palette | (HC_SubType_FogTable << 8)):
62886+ DRM_ERROR("Fog factor palettes are rejected because of "
62887+ "lack of info how to determine their size.\n");
62888+ return state_error;
62889+ default:
62890+
62891+ /*
62892+ * There are some unimplemented HC_ParaTypes here, that
62893+ * need to be implemented if the Mesa driver is extended.
62894+ */
62895+
62896+ DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
62897+ "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
62898+ cmd, *(buf - 2));
62899+ *buffer = buf;
62900+ return state_error;
62901+ }
62902+
62903+ while (buf < buf_end) {
62904+ cmd = *buf++;
62905+ if ((hz = hz_table[cmd >> 24])) {
62906+ if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
62907+ if (hz_mode == 1) {
62908+ buf--;
62909+ break;
62910+ }
62911+ return state_error;
62912+ }
62913+ } else if (hc_state->unfinished &&
62914+ finish_current_sequence(hc_state)) {
62915+ return state_error;
62916+ }
62917+ }
62918+ if (hc_state->unfinished && finish_current_sequence(hc_state)) {
62919+ return state_error;
62920+ }
62921+ *buffer = buf;
62922+ return state_command;
62923+}
62924+
62925+static __inline__ verifier_state_t
62926+via_parse_header2(drm_via_private_t * dev_priv, uint32_t const **buffer,
62927+ const uint32_t * buf_end, int *fire_count)
62928+{
62929+ uint32_t cmd;
62930+ const uint32_t *buf = *buffer;
62931+ const uint32_t *next_fire;
62932+ int burst = 0;
62933+
62934+ next_fire = dev_priv->fire_offsets[*fire_count];
62935+ buf++;
62936+ cmd = (*buf & 0xFFFF0000) >> 16;
62937+ VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
62938+ switch (cmd) {
62939+ case HC_ParaType_CmdVdata:
62940+ while ((buf < buf_end) &&
62941+ (*fire_count < dev_priv->num_fire_offsets) &&
62942+ (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
62943+ while (buf <= next_fire) {
62944+ VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
62945+ (burst & 63), *buf++);
62946+ burst += 4;
62947+ }
62948+ if ((buf < buf_end)
62949+ && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
62950+ buf++;
62951+
62952+ if (++(*fire_count) < dev_priv->num_fire_offsets)
62953+ next_fire = dev_priv->fire_offsets[*fire_count];
62954+ }
62955+ break;
62956+ default:
62957+ while (buf < buf_end) {
62958+
62959+ if (*buf == HC_HEADER2 ||
62960+ (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
62961+ (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
62962+ (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
62963+ break;
62964+
62965+ VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
62966+ (burst & 63), *buf++);
62967+ burst += 4;
62968+ }
62969+ }
62970+ *buffer = buf;
62971+ return state_command;
62972+}
62973+
62974+static __inline__ int verify_mmio_address(uint32_t address)
62975+{
62976+ if ((address > 0x3FF) && (address < 0xC00)) {
62977+ DRM_ERROR("Invalid VIDEO DMA command. "
62978+ "Attempt to access 3D- or command burst area.\n");
62979+ return 1;
62980+ } else if ((address > 0xCFF) && (address < 0x1300)) {
62981+ DRM_ERROR("Invalid VIDEO DMA command. "
62982+ "Attempt to access PCI DMA area.\n");
62983+ return 1;
62984+ } else if (address > 0x13FF) {
62985+ DRM_ERROR("Invalid VIDEO DMA command. "
62986+ "Attempt to access VGA registers.\n");
62987+ return 1;
62988+ }
62989+ return 0;
62990+}
62991+
62992+static __inline__ int
62993+verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end,
62994+ uint32_t dwords)
62995+{
62996+ const uint32_t *buf = *buffer;
62997+
62998+ if (buf_end - buf < dwords) {
62999+ DRM_ERROR("Illegal termination of video command.\n");
63000+ return 1;
63001+ }
63002+ while (dwords--) {
63003+ if (*buf++) {
63004+ DRM_ERROR("Illegal video command tail.\n");
63005+ return 1;
63006+ }
63007+ }
63008+ *buffer = buf;
63009+ return 0;
63010+}
63011+
63012+static __inline__ verifier_state_t
63013+via_check_header1(uint32_t const **buffer, const uint32_t * buf_end)
63014+{
63015+ uint32_t cmd;
63016+ const uint32_t *buf = *buffer;
63017+ verifier_state_t ret = state_command;
63018+
63019+ while (buf < buf_end) {
63020+ cmd = *buf;
63021+ if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
63022+ (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
63023+ if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
63024+ break;
63025+ DRM_ERROR("Invalid HALCYON_HEADER1 command. "
63026+ "Attempt to access 3D- or command burst area.\n");
63027+ ret = state_error;
63028+ break;
63029+ } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
63030+ if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
63031+ break;
63032+ DRM_ERROR("Invalid HALCYON_HEADER1 command. "
63033+ "Attempt to access VGA registers.\n");
63034+ ret = state_error;
63035+ break;
63036+ } else {
63037+ buf += 2;
63038+ }
63039+ }
63040+ *buffer = buf;
63041+ return ret;
63042+}
63043+
63044+static __inline__ verifier_state_t
63045+via_parse_header1(drm_via_private_t * dev_priv, uint32_t const **buffer,
63046+ const uint32_t * buf_end)
63047+{
63048+ register uint32_t cmd;
63049+ const uint32_t *buf = *buffer;
63050+
63051+ while (buf < buf_end) {
63052+ cmd = *buf;
63053+ if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
63054+ break;
63055+ VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
63056+ buf++;
63057+ }
63058+ *buffer = buf;
63059+ return state_command;
63060+}
63061+
63062+static __inline__ verifier_state_t
63063+via_check_vheader5(uint32_t const **buffer, const uint32_t * buf_end)
63064+{
63065+ uint32_t data;
63066+ const uint32_t *buf = *buffer;
63067+
63068+ if (buf_end - buf < 4) {
63069+ DRM_ERROR("Illegal termination of video header5 command\n");
63070+ return state_error;
63071+ }
63072+
63073+ data = *buf++ & ~VIA_VIDEOMASK;
63074+ if (verify_mmio_address(data))
63075+ return state_error;
63076+
63077+ data = *buf++;
63078+ if (*buf++ != 0x00F50000) {
63079+ DRM_ERROR("Illegal header5 header data\n");
63080+ return state_error;
63081+ }
63082+ if (*buf++ != 0x00000000) {
63083+ DRM_ERROR("Illegal header5 header data\n");
63084+ return state_error;
63085+ }
63086+ if (eat_words(&buf, buf_end, data))
63087+ return state_error;
63088+ if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
63089+ return state_error;
63090+ *buffer = buf;
63091+ return state_command;
63092+
63093+}
63094+
63095+static __inline__ verifier_state_t
63096+via_parse_vheader5(drm_via_private_t * dev_priv, uint32_t const **buffer,
63097+ const uint32_t * buf_end)
63098+{
63099+ uint32_t addr, count, i;
63100+ const uint32_t *buf = *buffer;
63101+
63102+ addr = *buf++ & ~VIA_VIDEOMASK;
63103+ i = count = *buf;
63104+ buf += 3;
63105+ while (i--) {
63106+ VIA_WRITE(addr, *buf++);
63107+ }
63108+ if (count & 3)
63109+ buf += 4 - (count & 3);
63110+ *buffer = buf;
63111+ return state_command;
63112+}
63113+
63114+static __inline__ verifier_state_t
63115+via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end)
63116+{
63117+ uint32_t data;
63118+ const uint32_t *buf = *buffer;
63119+ uint32_t i;
63120+
63121+ if (buf_end - buf < 4) {
63122+ DRM_ERROR("Illegal termination of video header6 command\n");
63123+ return state_error;
63124+ }
63125+ buf++;
63126+ data = *buf++;
63127+ if (*buf++ != 0x00F60000) {
63128+ DRM_ERROR("Illegal header6 header data\n");
63129+ return state_error;
63130+ }
63131+ if (*buf++ != 0x00000000) {
63132+ DRM_ERROR("Illegal header6 header data\n");
63133+ return state_error;
63134+ }
63135+ if ((buf_end - buf) < (data << 1)) {
63136+ DRM_ERROR("Illegal termination of video header6 command\n");
63137+ return state_error;
63138+ }
63139+ for (i = 0; i < data; ++i) {
63140+ if (verify_mmio_address(*buf++))
63141+ return state_error;
63142+ buf++;
63143+ }
63144+ data <<= 1;
63145+ if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
63146+ return state_error;
63147+ *buffer = buf;
63148+ return state_command;
63149+}
63150+
63151+static __inline__ verifier_state_t
63152+via_parse_vheader6(drm_via_private_t * dev_priv, uint32_t const **buffer,
63153+ const uint32_t * buf_end)
63154+{
63155+
63156+ uint32_t addr, count, i;
63157+ const uint32_t *buf = *buffer;
63158+
63159+ i = count = *++buf;
63160+ buf += 3;
63161+ while (i--) {
63162+ addr = *buf++;
63163+ VIA_WRITE(addr, *buf++);
63164+ }
63165+ count <<= 1;
63166+ if (count & 3)
63167+ buf += 4 - (count & 3);
63168+ *buffer = buf;
63169+ return state_command;
63170+}
63171+
63172+int
63173+via_verify_command_stream(const uint32_t * buf, unsigned int size,
63174+ struct drm_device * dev, int agp)
63175+{
63176+
63177+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
63178+ drm_via_state_t *hc_state = &dev_priv->hc_state;
63179+ drm_via_state_t saved_state = *hc_state;
63180+ uint32_t cmd;
63181+ const uint32_t *buf_end = buf + (size >> 2);
63182+ verifier_state_t state = state_command;
63183+ int cme_video;
63184+ int supported_3d;
63185+
63186+ cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A ||
63187+ dev_priv->chipset == VIA_DX9_0);
63188+
63189+ supported_3d = dev_priv->chipset != VIA_DX9_0;
63190+
63191+ hc_state->dev = dev;
63192+ hc_state->unfinished = no_sequence;
63193+ hc_state->map_cache = NULL;
63194+ hc_state->agp = agp;
63195+ hc_state->buf_start = buf;
63196+ dev_priv->num_fire_offsets = 0;
63197+
63198+ while (buf < buf_end) {
63199+
63200+ switch (state) {
63201+ case state_header2:
63202+ state = via_check_header2(&buf, buf_end, hc_state);
63203+ break;
63204+ case state_header1:
63205+ state = via_check_header1(&buf, buf_end);
63206+ break;
63207+ case state_vheader5:
63208+ state = via_check_vheader5(&buf, buf_end);
63209+ break;
63210+ case state_vheader6:
63211+ state = via_check_vheader6(&buf, buf_end);
63212+ break;
63213+ case state_command:
63214+ if ((HALCYON_HEADER2 == (cmd = *buf)) &&
63215+ supported_3d)
63216+ state = state_header2;
63217+ else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
63218+ state = state_header1;
63219+ else if (cme_video
63220+ && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
63221+ state = state_vheader5;
63222+ else if (cme_video
63223+ && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
63224+ state = state_vheader6;
63225+ else if ((cmd == HALCYON_HEADER2) && !supported_3d) {
63226+ DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n");
63227+ state = state_error;
63228+ } else {
63229+ DRM_ERROR
63230+ ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
63231+ cmd);
63232+ state = state_error;
63233+ }
63234+ break;
63235+ case state_error:
63236+ default:
63237+ *hc_state = saved_state;
63238+ return -EINVAL;
63239+ }
63240+ }
63241+ if (state == state_error) {
63242+ *hc_state = saved_state;
63243+ return -EINVAL;
63244+ }
63245+ return 0;
63246+}
63247+
63248+int
63249+via_parse_command_stream(struct drm_device * dev, const uint32_t * buf,
63250+ unsigned int size)
63251+{
63252+
63253+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
63254+ uint32_t cmd;
63255+ const uint32_t *buf_end = buf + (size >> 2);
63256+ verifier_state_t state = state_command;
63257+ int fire_count = 0;
63258+
63259+ while (buf < buf_end) {
63260+
63261+ switch (state) {
63262+ case state_header2:
63263+ state =
63264+ via_parse_header2(dev_priv, &buf, buf_end,
63265+ &fire_count);
63266+ break;
63267+ case state_header1:
63268+ state = via_parse_header1(dev_priv, &buf, buf_end);
63269+ break;
63270+ case state_vheader5:
63271+ state = via_parse_vheader5(dev_priv, &buf, buf_end);
63272+ break;
63273+ case state_vheader6:
63274+ state = via_parse_vheader6(dev_priv, &buf, buf_end);
63275+ break;
63276+ case state_command:
63277+ if (HALCYON_HEADER2 == (cmd = *buf))
63278+ state = state_header2;
63279+ else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
63280+ state = state_header1;
63281+ else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
63282+ state = state_vheader5;
63283+ else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
63284+ state = state_vheader6;
63285+ else {
63286+ DRM_ERROR
63287+ ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
63288+ cmd);
63289+ state = state_error;
63290+ }
63291+ break;
63292+ case state_error:
63293+ default:
63294+ return -EINVAL;
63295+ }
63296+ }
63297+ if (state == state_error) {
63298+ return -EINVAL;
63299+ }
63300+ return 0;
63301+}
63302+
63303+static void
63304+setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
63305+{
63306+ int i;
63307+
63308+ for (i = 0; i < 256; ++i) {
63309+ table[i] = forbidden_command;
63310+ }
63311+
63312+ for (i = 0; i < size; ++i) {
63313+ table[init_table[i].code] = init_table[i].hz;
63314+ }
63315+}
63316+
63317+void via_init_command_verifier(void)
63318+{
63319+ setup_hazard_table(init_table1, table1,
63320+ sizeof(init_table1) / sizeof(hz_init_t));
63321+ setup_hazard_table(init_table2, table2,
63322+ sizeof(init_table2) / sizeof(hz_init_t));
63323+ setup_hazard_table(init_table3, table3,
63324+ sizeof(init_table3) / sizeof(hz_init_t));
63325+}
63326Index: git/shared-core/via_verifier.h
63327===================================================================
63328--- /dev/null 1970-01-01 00:00:00.000000000 +0000
63329+++ git/shared-core/via_verifier.h 2008-12-12 17:35:22.000000000 +0000
63330@@ -0,0 +1,64 @@
63331+/*
63332+ * Copyright 2004 The Unichrome Project. All Rights Reserved.
63333+ *
63334+ * Permission is hereby granted, free of charge, to any person obtaining a
63335+ * copy of this software and associated documentation files (the "Software"),
63336+ * to deal in the Software without restriction, including without limitation
63337+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
63338+ * and/or sell copies of the Software, and to permit persons to whom the
63339+ * Software is furnished to do so, subject to the following conditions:
63340+ *
63341+ * The above copyright notice and this permission notice (including the
63342+ * next paragraph) shall be included in all copies or substantial portions
63343+ * of the Software.
63344+ *
63345+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
63346+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
63347+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
63348+ * THE UNICHROME PROJECT, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
63349+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
63350+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
63351+ * DEALINGS IN THE SOFTWARE.
63352+ *
63353+ * Author: Thomas Hellström 2004.
63354+ */
63355+
63356+#ifndef _VIA_VERIFIER_H_
63357+#define _VIA_VERIFIER_H_
63358+
63359+typedef enum {
63360+ no_sequence = 0,
63361+ z_address,
63362+ dest_address,
63363+ tex_address
63364+} drm_via_sequence_t;
63365+
63366+
63367+
63368+typedef struct {
63369+ unsigned texture;
63370+ uint32_t z_addr;
63371+ uint32_t d_addr;
63372+ uint32_t t_addr[2][10];
63373+ uint32_t pitch[2][10];
63374+ uint32_t height[2][10];
63375+ uint32_t tex_level_lo[2];
63376+ uint32_t tex_level_hi[2];
63377+ uint32_t tex_palette_size[2];
63378+ uint32_t tex_npot[2];
63379+ drm_via_sequence_t unfinished;
63380+ int agp_texture;
63381+ int multitex;
63382+ struct drm_device *dev;
63383+ drm_local_map_t *map_cache;
63384+ uint32_t vertex_count;
63385+ int agp;
63386+ const uint32_t *buf_start;
63387+} drm_via_state_t;
63388+
63389+extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
63390+ struct drm_device *dev, int agp);
63391+extern int via_parse_command_stream(struct drm_device *dev, const uint32_t * buf,
63392+ unsigned int size);
63393+
63394+#endif
63395Index: git/shared-core/via_video.c
63396===================================================================
63397--- /dev/null 1970-01-01 00:00:00.000000000 +0000
63398+++ git/shared-core/via_video.c 2008-12-12 17:35:22.000000000 +0000
63399@@ -0,0 +1,93 @@
63400+/*
63401+ * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
63402+ *
63403+ * Permission is hereby granted, free of charge, to any person obtaining a
63404+ * copy of this software and associated documentation files (the "Software"),
63405+ * to deal in the Software without restriction, including without limitation
63406+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
63407+ * and/or sell copies of the Software, and to permit persons to whom the
63408+ * Software is furnished to do so, subject to the following conditions:
63409+ *
63410+ * The above copyright notice and this permission notice (including the
63411+ * next paragraph) shall be included in all copies or substantial portions
63412+ * of the Software.
63413+ *
63414+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
63415+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
63416+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
63417+ * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
63418+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
63419+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
63420+ * DEALINGS IN THE SOFTWARE.
63421+ *
63422+ * Author: Thomas Hellstrom 2005.
63423+ *
63424+ * Video and XvMC related functions.
63425+ */
63426+
63427+#include "drmP.h"
63428+#include "via_drm.h"
63429+#include "via_drv.h"
63430+
63431+void via_init_futex(drm_via_private_t * dev_priv)
63432+{
63433+ unsigned int i;
63434+
63435+ DRM_DEBUG("%s\n", __FUNCTION__);
63436+
63437+ for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
63438+ DRM_INIT_WAITQUEUE(&(dev_priv->decoder_queue[i]));
63439+ XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0;
63440+ }
63441+}
63442+
63443+void via_cleanup_futex(drm_via_private_t * dev_priv)
63444+{
63445+}
63446+
63447+void via_release_futex(drm_via_private_t * dev_priv, int context)
63448+{
63449+ unsigned int i;
63450+ volatile int *lock;
63451+
63452+ if (!dev_priv->sarea_priv)
63453+ return;
63454+
63455+ for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
63456+ lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i);
63457+ if ((_DRM_LOCKING_CONTEXT(*lock) == context)) {
63458+ if (_DRM_LOCK_IS_HELD(*lock)
63459+ && (*lock & _DRM_LOCK_CONT)) {
63460+ DRM_WAKEUP(&(dev_priv->decoder_queue[i]));
63461+ }
63462+ *lock = 0;
63463+ }
63464+ }
63465+}
63466+
63467+int via_decoder_futex(struct drm_device *dev, void *data, struct drm_file *file_priv)
63468+{
63469+ drm_via_futex_t *fx = data;
63470+ volatile int *lock;
63471+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
63472+ drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
63473+ int ret = 0;
63474+
63475+ DRM_DEBUG("%s\n", __FUNCTION__);
63476+
63477+ if (fx->lock > VIA_NR_XVMC_LOCKS)
63478+ return -EFAULT;
63479+
63480+ lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock);
63481+
63482+ switch (fx->func) {
63483+ case VIA_FUTEX_WAIT:
63484+ DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock],
63485+ (fx->ms / 10) * (DRM_HZ / 100), *lock != fx->val);
63486+ return ret;
63487+ case VIA_FUTEX_WAKE:
63488+ DRM_WAKEUP(&(dev_priv->decoder_queue[fx->lock]));
63489+ return 0;
63490+ }
63491+ return 0;
63492+}
diff --git a/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb b/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb
new file mode 100644
index 0000000000..60e10d91f2
--- /dev/null
+++ b/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb
@@ -0,0 +1,17 @@
1SECTION = "x11/base"
2LICENSE = "MIT"
3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2 \
4 file://poulsbo.patch;patch=1"
5PROVIDES = "drm libdrm"
6
7S = ${WORKDIR}/libdrm-${PV}
8
9DEPENDS = "libpthread-stubs"
10
11PR = "r7"
12
13COMPATIBLE_MACHINE = "menlow"
14
15LEAD_SONAME = "libdrm.so"
16
17inherit autotools_stage pkgconfig
diff --git a/meta-moblin/packages/drm/libdrm-psb_git.bb b/meta-moblin/packages/drm/libdrm-psb_git.bb
deleted file mode 100644
index c3a1fda49a..0000000000
--- a/meta-moblin/packages/drm/libdrm-psb_git.bb
+++ /dev/null
@@ -1,21 +0,0 @@
1SECTION = "x11/base"
2LICENSE = "MIT"
3SRC_URI = "git://git.moblin.org/projects/libdrm.git/;protocol=git \
4 file://poulsbo_libdrm_update.patch;patch=1"
5PROVIDES = "drm libdrm"
6
7S = ${WORKDIR}/git
8
9DEPENDS = "libpthread-stubs"
10
11PR = "r2"
12PV = "2.3.0+git${SRCREV}"
13
14#PROVIDES = "libdrm"
15COMPATIBLE_MACHINE = "menlow"
16#DEFAULT_PREFERENCE_menlow = "5"
17#PACKAGE_ARCH = "${MACHINE_ARCH}"
18
19LEAD_SONAME = "libdrm.so"
20
21inherit autotools_stage pkgconfig
diff --git a/meta-moblin/packages/drm/linux-psb-modules_2.6.24.bb b/meta-moblin/packages/drm/linux-psb-modules_2.6.27.bb
index 5ad64b3a0b..2643f1ee6c 100644
--- a/meta-moblin/packages/drm/linux-psb-modules_2.6.24.bb
+++ b/meta-moblin/packages/drm/linux-psb-modules_2.6.27.bb
@@ -1,6 +1,9 @@
1SRC_URI = "http://archive.ubuntu.com/ubuntu/pool/main/l/linux-ubuntu-modules-2.6.24/linux-ubuntu-modules-2.6.24_2.6.24-22.35.tar.gz \ 1SRC_URI = "http://archive.ubuntu.com/ubuntu/pool/main/l/linux-ubuntu-modules-2.6.24/linux-ubuntu-modules-2.6.24_2.6.24-22.35.tar.gz \
2 file://fixes-kernversion.patch;patch=1 \
2 file://menlow-config" 3 file://menlow-config"
3 4
5PR = "r4"
6
4S = "${WORKDIR}/lum/ubuntu" 7S = "${WORKDIR}/lum/ubuntu"
5 8
6inherit module 9inherit module
@@ -19,9 +22,9 @@ do_compile() {
19MODULE_PATH = "/lib/modules/${KERNEL_VERSION}" 22MODULE_PATH = "/lib/modules/${KERNEL_VERSION}"
20 23
21do_install () { 24do_install () {
22 install -d ${D}${MODULE_PATH}/kernel/drivers/char/drm/ 25 install -d ${D}${MODULE_PATH}/tmp/kernel/drivers/char/drm/
23 install -m 644 ${S}/media/drm-poulsbo/drm.ko ${D}${MODULE_PATH}/kernel/drivers/char/drm/ 26 install -m 644 ${S}/media/drm-poulsbo/drm.ko ${D}${MODULE_PATH}/tmp/kernel/drivers/char/drm/
24 install -m 644 ${S}/media/drm-poulsbo/psb.ko ${D}${MODULE_PATH}/kernel/drivers/char/drm/ 27 install -m 644 ${S}/media/drm-poulsbo/psb.ko ${D}${MODULE_PATH}/tmp/kernel/drivers/char/drm/
25} 28}
26 29
27COMPATIBLE_MACHINE = "menlow" \ No newline at end of file 30COMPATIBLE_MACHINE = "menlow" \ No newline at end of file
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-07-06 14:07:18 +0000