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authorKhem Raj <raj.khem@gmail.com>2017-11-07 23:26:52 (GMT)
committerRichard Purdie <richard.purdie@linuxfoundation.org>2018-03-14 14:55:02 (GMT)
commitd80e2417823ba7378304f92ea3404609dbe45906 (patch)
tree417a45db4a4e62e3af7f4714327de3c50da91663
parent02b66069c561be3d5567712e5fc43b6340109ed1 (diff)
downloadpoky-d80e2417823ba7378304f92ea3404609dbe45906.tar.gz
gcc7/gcc6: Fix unaligned STRD issue on ARM
Backport https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82445 Fixes [YOCTO 12297] Cherry-picked from oe-core master 568227133be3f9f015679df3525f6c4f86304fd0 (From OE-Core rev: b6d00ad1a26bfbbe17ec394365df755624e8c4f7) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Ross Burton <ross.burton@intel.com> (cherry picked from commit 568227133be3f9f015679df3525f6c4f86304fd0) Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
-rw-r--r--meta/recipes-devtools/gcc/gcc-6.4.inc1
-rw-r--r--meta/recipes-devtools/gcc/gcc-6.4/0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch194
2 files changed, 195 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-6.4.inc b/meta/recipes-devtools/gcc/gcc-6.4.inc
index 314994b..9ddd56f 100644
--- a/meta/recipes-devtools/gcc/gcc-6.4.inc
+++ b/meta/recipes-devtools/gcc/gcc-6.4.inc
@@ -86,6 +86,7 @@ SRC_URI = "\
86" 86"
87BACKPORTS = "\ 87BACKPORTS = "\
88 file://CVE-2016-6131.patch \ 88 file://CVE-2016-6131.patch \
89 file://0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch \
89" 90"
90SRC_URI[md5sum] = "11ba51a0cfb8471927f387c8895fe232" 91SRC_URI[md5sum] = "11ba51a0cfb8471927f387c8895fe232"
91SRC_URI[sha256sum] = "850bf21eafdfe5cd5f6827148184c08c4a0852a37ccf36ce69855334d2c914d4" 92SRC_URI[sha256sum] = "850bf21eafdfe5cd5f6827148184c08c4a0852a37ccf36ce69855334d2c914d4"
diff --git a/meta/recipes-devtools/gcc/gcc-6.4/0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch b/meta/recipes-devtools/gcc/gcc-6.4/0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch
new file mode 100644
index 0000000..0214ab8
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-6.4/0057-ARM-PR-82445-suppress-32-bit-aligned-ldrd-strd-peeph.patch
@@ -0,0 +1,194 @@
1From ad5bf450aef2ffee6d57ed193fabc5f72f8eaa65 Mon Sep 17 00:00:00 2001
2From: rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Thu, 19 Oct 2017 13:16:42 +0000
4Subject: [PATCH] [ARM] PR 82445 - suppress 32-bit aligned ldrd/strd peepholing
5 with -mno-unaligned-access
6
7Peephole patterns exist in the arm backend to spot load/store
8operations to adjacent memory operations in order to convert them into
9ldrd/strd instructions. However, when we have strict alignment
10enforced, then we can only do this if the accesses are known to be
1164-bit aligned; this is unlikely to be the case for most loads. The
12patch adds some alignment checking to the code that validates the
13addresses for use in the peephole patterns. This should also fix
14incorrect generation of ldrd/strd with unaligned accesses that could
15previously have occurred on ARMv5e where all such operations must be
1664-bit aligned.
17
18I've added some new tests as well. In doing so I discovered that the
19ldrd/strd peephole tests could never fail since they would match the
20source file name in the scanned assembly as well as any instructions
21of the intended type. I've fixed those by tightening the scan results
22slightly.
23
24gcc:
25
26* config/arm/arm.c (align_ok_ldrd_strd): New function.
27(mem_ok_for_ldrd_strd): New parameter align. Extract the alignment of the
28mem into it.
29(gen_operands_ldrd_strd): Validate the alignment of the accesses.
30
31testsuite:
32
33* gcc.target/arm/peep-ldrd-1.c: Tighten test scan pattern.
34* gcc.target/arm/peep-strd-1.c: Likewise.
35* gcc.target/arm/peep-ldrd-2.c: New test.
36* gcc.target/arm/peep-strd-2.c: New test.
37
38
39
40git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-6-branch@253892 138bc75d-0d04-0410-961f-82ee72b054a4
41---
42Upstream-Status: Backport
43Signed-off-by: Khem Raj <raj.khem@gmail.com>
44
45 gcc/ChangeLog | 8 +++++++
46 gcc/config/arm/arm.c | 27 ++++++++++++++++++----
47 gcc/testsuite/ChangeLog | 8 +++++++
48 gcc/testsuite/gcc.target/arm/peep-ldrd-1.c | 2 +-
49 .../arm/{peep-ldrd-1.c => peep-ldrd-2.c} | 4 ++--
50 gcc/testsuite/gcc.target/arm/peep-strd-1.c | 2 +-
51 .../arm/{peep-strd-1.c => peep-strd-2.c} | 4 ++--
52 7 files changed, 44 insertions(+), 11 deletions(-)
53 copy gcc/testsuite/gcc.target/arm/{peep-ldrd-1.c => peep-ldrd-2.c} (63%)
54 copy gcc/testsuite/gcc.target/arm/{peep-strd-1.c => peep-strd-2.c} (58%)
55
56diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
57index 9c0813d598d..e3da9f77fb6 100644
58--- a/gcc/config/arm/arm.c
59+++ b/gcc/config/arm/arm.c
60@@ -15926,12 +15926,23 @@ operands_ok_ldrd_strd (rtx rt, rtx rt2, rtx rn, HOST_WIDE_INT offset,
61 return true;
62 }
63
64+/* Return true if a 64-bit access with alignment ALIGN and with a
65+ constant offset OFFSET from the base pointer is permitted on this
66+ architecture. */
67+static bool
68+align_ok_ldrd_strd (HOST_WIDE_INT align, HOST_WIDE_INT offset)
69+{
70+ return (unaligned_access
71+ ? (align >= BITS_PER_WORD && (offset & 3) == 0)
72+ : (align >= 2 * BITS_PER_WORD && (offset & 7) == 0));
73+}
74+
75 /* Helper for gen_operands_ldrd_strd. Returns true iff the memory
76 operand MEM's address contains an immediate offset from the base
77- register and has no side effects, in which case it sets BASE and
78- OFFSET accordingly. */
79+ register and has no side effects, in which case it sets BASE,
80+ OFFSET and ALIGN accordingly. */
81 static bool
82-mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset)
83+mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset, HOST_WIDE_INT *align)
84 {
85 rtx addr;
86
87@@ -15950,6 +15961,7 @@ mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset)
88 gcc_assert (MEM_P (mem));
89
90 *offset = const0_rtx;
91+ *align = MEM_ALIGN (mem);
92
93 addr = XEXP (mem, 0);
94
95@@ -15990,7 +16002,7 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
96 bool const_store, bool commute)
97 {
98 int nops = 2;
99- HOST_WIDE_INT offsets[2], offset;
100+ HOST_WIDE_INT offsets[2], offset, align[2];
101 rtx base = NULL_RTX;
102 rtx cur_base, cur_offset, tmp;
103 int i, gap;
104@@ -16002,7 +16014,8 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
105 registers, and the corresponding memory offsets. */
106 for (i = 0; i < nops; i++)
107 {
108- if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset))
109+ if (!mem_ok_for_ldrd_strd (operands[nops+i], &cur_base, &cur_offset,
110+ &align[i]))
111 return false;
112
113 if (i == 0)
114@@ -16114,6 +16127,7 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
115 /* Swap the instructions such that lower memory is accessed first. */
116 std::swap (operands[0], operands[1]);
117 std::swap (operands[2], operands[3]);
118+ std::swap (align[0], align[1]);
119 if (const_store)
120 std::swap (operands[4], operands[5]);
121 }
122@@ -16127,6 +16141,9 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
123 if (gap != 4)
124 return false;
125
126+ if (!align_ok_ldrd_strd (align[0], offset))
127+ return false;
128+
129 /* Make sure we generate legal instructions. */
130 if (operands_ok_ldrd_strd (operands[0], operands[1], base, offset,
131 false, load))
132diff --git a/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c b/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
133index eb2b86ee7b6..d49eff6b87e 100644
134--- a/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
135+++ b/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
136@@ -8,4 +8,4 @@ int foo(int a, int b, int* p, int *q)
137 *p = a;
138 return a;
139 }
140-/* { dg-final { scan-assembler "ldrd" } } */
141+/* { dg-final { scan-assembler "ldrd\\t" } } */
142diff --git a/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c b/gcc/testsuite/gcc.target/arm/peep-ldrd-2.c
143similarity index 63%
144copy from gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
145copy to gcc/testsuite/gcc.target/arm/peep-ldrd-2.c
146index eb2b86ee7b6..6822c2b1454 100644
147--- a/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
148+++ b/gcc/testsuite/gcc.target/arm/peep-ldrd-2.c
149@@ -1,6 +1,6 @@
150 /* { dg-do compile } */
151 /* { dg-require-effective-target arm_prefer_ldrd_strd } */
152-/* { dg-options "-O2" } */
153+/* { dg-options "-O2 -mno-unaligned-access" } */
154 int foo(int a, int b, int* p, int *q)
155 {
156 a = p[2] + p[3];
157@@ -8,4 +8,4 @@ int foo(int a, int b, int* p, int *q)
158 *p = a;
159 return a;
160 }
161-/* { dg-final { scan-assembler "ldrd" } } */
162+/* { dg-final { scan-assembler-not "ldrd\\t" } } */
163diff --git a/gcc/testsuite/gcc.target/arm/peep-strd-1.c b/gcc/testsuite/gcc.target/arm/peep-strd-1.c
164index bd330769599..fe1beac7229 100644
165--- a/gcc/testsuite/gcc.target/arm/peep-strd-1.c
166+++ b/gcc/testsuite/gcc.target/arm/peep-strd-1.c
167@@ -6,4 +6,4 @@ void foo(int a, int b, int* p)
168 p[2] = a;
169 p[3] = b;
170 }
171-/* { dg-final { scan-assembler "strd" } } */
172+/* { dg-final { scan-assembler "strd\\t" } } */
173diff --git a/gcc/testsuite/gcc.target/arm/peep-strd-1.c b/gcc/testsuite/gcc.target/arm/peep-strd-2.c
174similarity index 58%
175copy from gcc/testsuite/gcc.target/arm/peep-strd-1.c
176copy to gcc/testsuite/gcc.target/arm/peep-strd-2.c
177index bd330769599..bfc5ebe9eec 100644
178--- a/gcc/testsuite/gcc.target/arm/peep-strd-1.c
179+++ b/gcc/testsuite/gcc.target/arm/peep-strd-2.c
180@@ -1,9 +1,9 @@
181 /* { dg-do compile } */
182 /* { dg-require-effective-target arm_prefer_ldrd_strd } */
183-/* { dg-options "-O2" } */
184+/* { dg-options "-O2 -mno-unaligned-access" } */
185 void foo(int a, int b, int* p)
186 {
187 p[2] = a;
188 p[3] = b;
189 }
190-/* { dg-final { scan-assembler "strd" } } */
191+/* { dg-final { scan-assembler-not "strd\\t" } } */
192--
1932.15.0
194