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authorKhem Raj <raj.khem@gmail.com>2021-05-22 21:45:29 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2021-05-25 22:36:08 +0100
commitd7daabfbd794a84c1d36311b6ed99f54f24246ce (patch)
tree13b3d3fc206b2e4c9312bc98885ebeeb1f8fb2d4
parentc23a25e60791b463639751b516ab63a0347a70df (diff)
downloadpoky-d7daabfbd794a84c1d36311b6ed99f54f24246ce.tar.gz
glibc: Update to latest 2.33 branch
Drop backported patches Add CVE-2021-27645 to CVE_CHECK_WHITELIST and drop the patch as its also upstreamed Changes in the version bump are * 3f5080aedd nptl: Do not build nptl/tst-pthread-gdb-attach as PIE * 36783141cf nptl: Check for compatible GDB in nptl/tst-pthread-gdb-attach * ea299b62e8 nptl_db: Support different libpthread/ld.so load orders (bug 27744) * 162df872f0 x86: tst-cpu-features-supports.c: Update AMX check * 12ff80b312 Remove PR_TAGGED_ADDR_ENABLE from sys/prctl.h * 1bf38e7260 Fix SXID_ERASE behavior in setuid programs (BZ #27471) * a7b8e8ec9b Enhance setuid-tunables test * ee16c81063 tst-env-setuid: Use support_capture_subprogram_self_sgid * 267e174f19 support: Add capability to fork an sgid child * 249c486ce8 support: Pass environ to child process * 45b2c57d34 support: Typo and formatting fixes * e07abf59b2 tunables: Fix comparison of tunable values * 3e9ca60a58 linux: always update select timeout (BZ #27706) * 8380ca5833 linux: Normalize and return timeout on select (BZ #27651) * 85e4dc415a libsupport: Add support_select_normalizes_timeout * b5b4aa62c1 libsupport: Add support_select_modifies_timeout * 3d525dd639 misc: Fix tst-select timeout handling (BZ#27648) * 830674605f tst: Provide test for select * e78ea9bd26 Update Nios II libm-test-ulps. * 98bb18f52a malloc: Fix a realloc crash with heap tagging [BZ 27468] * fc4ecce85b S390: Also check vector support in memmove ifunc-selector [BZ #27511] * db32fc27e7 test-container: Always copy test-specific support files [BZ #27537] * 79c6be6a0a nptl: Remove private futex optimization [BZ #27304] * f90d6b0484 pthread_once hangs when init routine throws an exception [BZ #18435] * dd8023c2ac elf: ld.so --help calls _dl_init_paths without a main map [BZ #27577] * ea5a537e87 elf: Always set l in _dl_init_paths (bug 23462) * 64f6c287ad x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] * 32b9280f1d io: Return EBAFD for negative file descriptor on fstat (BZ #27559) * a151f2e05a nscd: Fix double free in netgroupcache [BZ #27462] * ee9f98d9ca x86: Set minimum x86-64 level marker [BZ #27318] * 3e880d7337 nss: Re-enable NSS module loading after chroot [BZ #27389] * 71b2463f61 x86: Add CPU-specific diagnostics to ld.so --list-diagnostics * a1eb3915e7 x86: Automate generation of PREFERRED_FEATURE_INDEX_1 bitfield * 33dc1dd602 ld.so: Implement the --list-diagnostics option * 8d4241b897 string: Work around GCC PR 98512 in rawmemchr * 6efa2d44c8 S390: Add new hwcap values. * c5e3545897 tunables: Disallow negative values for some tunables * 905fdc7071 x86: Use SIZE_MAX instead of (long int)-1 for tunable range value * 15afd6b8d8 tunables: Simplify TUNABLE_SET interface * 17f0ff0978 nsswitch: return result when nss database is locked [BZ #27343] (From OE-Core rev: c6fb9b80ecb0a4e7970157774ce9add12e9ef3ea) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat
-rw-r--r--meta/recipes-core/glibc/glibc-version.inc2
-rw-r--r--meta/recipes-core/glibc/glibc/0001-nptl-Remove-private-futex-optimization-BZ-27304.patch49
-rw-r--r--meta/recipes-core/glibc/glibc/0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch116
-rw-r--r--meta/recipes-core/glibc/glibc/0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch58
-rw-r--r--meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch185
-rw-r--r--meta/recipes-core/glibc/glibc/CVE-2021-27645.patch51
-rw-r--r--meta/recipes-core/glibc/glibc_2.33.bb7
7 files changed, 2 insertions, 466 deletions
diff --git a/meta/recipes-core/glibc/glibc-version.inc b/meta/recipes-core/glibc/glibc-version.inc
index 3a95173175..376ead66ac 100644
--- a/meta/recipes-core/glibc/glibc-version.inc
+++ b/meta/recipes-core/glibc/glibc-version.inc
@@ -1,6 +1,6 @@
1SRCBRANCH ?= "release/2.33/master" 1SRCBRANCH ?= "release/2.33/master"
2PV = "2.33" 2PV = "2.33"
3SRCREV_glibc ?= "9826b03b747b841f5fc6de2054bf1ef3f5c4bdf3" 3SRCREV_glibc ?= "3f5080aedd164c1f92a53552dd3e0b82ac6d2bd3"
4SRCREV_localedef ?= "bd644c9e6f3e20c5504da1488448173c69c56c28" 4SRCREV_localedef ?= "bd644c9e6f3e20c5504da1488448173c69c56c28"
5 5
6GLIBC_GIT_URI ?= "git://sourceware.org/git/glibc.git" 6GLIBC_GIT_URI ?= "git://sourceware.org/git/glibc.git"
diff --git a/meta/recipes-core/glibc/glibc/0001-nptl-Remove-private-futex-optimization-BZ-27304.patch b/meta/recipes-core/glibc/glibc/0001-nptl-Remove-private-futex-optimization-BZ-27304.patch
deleted file mode 100644
index 39fde5b785..0000000000
--- a/meta/recipes-core/glibc/glibc/0001-nptl-Remove-private-futex-optimization-BZ-27304.patch
+++ /dev/null
@@ -1,49 +0,0 @@
1From c4ad832276f4dadfa40904109b26a521468f66bc Mon Sep 17 00:00:00 2001
2From: Florian Weimer <fweimer@redhat.com>
3Date: Thu, 4 Feb 2021 15:00:20 +0100
4Subject: [PATCH] nptl: Remove private futex optimization [BZ #27304]
5
6It is effectively used, unexcept for pthread_cond_destroy, where we do
7not want it; see bug 27304. The internal locks do not support a
8process-shared mode.
9
10This fixes commit dc6cfdc934db9997c33728082d63552b9eee4563 ("nptl:
11Move pthread_cond_destroy implementation into libc").
12
13Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
14
15Upstream-Status: Backport [https://sourceware.org/bugzilla/show_bug.cgi?id=27304]
16Signed-off-by: Yanfei Xu <yanfei.xu@windriver.com>
17---
18 sysdeps/nptl/lowlevellock-futex.h | 14 +-------------
19 1 file changed, 1 insertion(+), 13 deletions(-)
20
21diff --git a/sysdeps/nptl/lowlevellock-futex.h b/sysdeps/nptl/lowlevellock-futex.h
22index ecb729da6b..ca96397a4a 100644
23--- a/sysdeps/nptl/lowlevellock-futex.h
24+++ b/sysdeps/nptl/lowlevellock-futex.h
25@@ -50,20 +50,8 @@
26 #define LLL_SHARED FUTEX_PRIVATE_FLAG
27
28 #ifndef __ASSEMBLER__
29-
30-# if IS_IN (libc) || IS_IN (rtld)
31-/* In libc.so or ld.so all futexes are private. */
32-# define __lll_private_flag(fl, private) \
33- ({ \
34- /* Prevent warnings in callers of this macro. */ \
35- int __lll_private_flag_priv __attribute__ ((unused)); \
36- __lll_private_flag_priv = (private); \
37- ((fl) | FUTEX_PRIVATE_FLAG); \
38- })
39-# else
40-# define __lll_private_flag(fl, private) \
41+# define __lll_private_flag(fl, private) \
42 (((fl) | FUTEX_PRIVATE_FLAG) ^ (private))
43-# endif
44
45 # define lll_futex_syscall(nargs, futexp, op, ...) \
46 ({ \
47--
482.27.0
49
diff --git a/meta/recipes-core/glibc/glibc/0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch b/meta/recipes-core/glibc/glibc/0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch
deleted file mode 100644
index 3cb60b2e55..0000000000
--- a/meta/recipes-core/glibc/glibc/0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch
+++ /dev/null
@@ -1,116 +0,0 @@
1From b1971f6f1331d738d1d6b376b4741668a7546125 Mon Sep 17 00:00:00 2001
2From: "H.J. Lu" <hjl.tools@gmail.com>
3Date: Tue, 2 Feb 2021 13:45:58 -0800
4Subject: [PATCH] x86: Require full ISA support for x86-64 level marker [BZ #27318]
5
6Since -march=sandybridge enables ISAs in x86-64 ISA level v3, the v3
7marker is set on libc.so. We couldn't set the needed ISA marker to v2
8since this libc won't run on all v2 machines. Technically, the v3 marker
9is correct. But the resulting libc.so won't run on Sandy Brigde, which
10is a v2 machine, even when libc is compiled with -march=sandybridge:
11
12$ ./elf/ld.so ./libc.so
13./libc.so: (p) CPU ISA level is lower than required: needed: 7; got: 3
14
15Instead, we require full ISA support for x86-64 level marker and disable
16x86-64 level marker for -march=sandybridge which enables ISAs between v2
17and v3.
18
19Upstream-Status: Submitted [https://sourceware.org/pipermail/libc-alpha/2021-February/122297.html]
20Signed-off-by: Khem Raj <raj.khem@gmail.com>
21---
22
23 sysdeps/x86/configure | 7 ++++++-
24 sysdeps/x86/configure.ac | 2 +-
25 sysdeps/x86/isa-level.c | 21 ++++++++++++++++++++-
26 3 files changed, 27 insertions(+), 3 deletions(-)
27
28diff --git a/sysdeps/x86/configure b/sysdeps/x86/configure
29index 5e32dc62b3..5b20646843 100644
30--- a/sysdeps/x86/configure
31+++ b/sysdeps/x86/configure
32@@ -133,7 +133,12 @@ if { ac_try='${CC-cc} $CFLAGS $CPPFLAGS -nostartfiles -nostdlib -r -o conftest c
33 $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
34 test $ac_status = 0; }; }; then
35 count=`LC_ALL=C $READELF -n conftest | grep NT_GNU_PROPERTY_TYPE_0 | wc -l`
36- if test "$count" = 1; then
37+ if test "$count" = 1 && { ac_try='${CC-cc} $CFLAGS $CPPFLAGS -DINCLUDE_X86_ISA_LEVEL -S -o conftest.s $srcdir/sysdeps/x86/isa-level.c'
38+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
39+ (eval $ac_try) 2>&5
40+ ac_status=$?
41+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
42+ test $ac_status = 0; }; }; then
43 libc_cv_include_x86_isa_level=yes
44 fi
45 fi
46diff --git a/sysdeps/x86/configure.ac b/sysdeps/x86/configure.ac
47index f94088f377..54ecd33d2c 100644
48--- a/sysdeps/x86/configure.ac
49+++ b/sysdeps/x86/configure.ac
50@@ -100,7 +100,7 @@ EOF
51 libc_cv_include_x86_isa_level=no
52 if AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS -nostartfiles -nostdlib -r -o conftest conftest1.S conftest2.S); then
53 count=`LC_ALL=C $READELF -n conftest | grep NT_GNU_PROPERTY_TYPE_0 | wc -l`
54- if test "$count" = 1; then
55+ if test "$count" = 1 && AC_TRY_COMMAND(${CC-cc} $CFLAGS $CPPFLAGS -DINCLUDE_X86_ISA_LEVEL -S -o conftest.s $srcdir/sysdeps/x86/isa-level.c); then
56 libc_cv_include_x86_isa_level=yes
57 fi
58 fi
59diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c
60index aaf524cb56..7f83449061 100644
61--- a/sysdeps/x86/isa-level.c
62+++ b/sysdeps/x86/isa-level.c
63@@ -25,12 +25,17 @@
64 License along with the GNU C Library; if not, see
65 <https://www.gnu.org/licenses/>. */
66
67-#include <elf.h>
68+#ifdef _LIBC
69+# include <elf.h>
70+#endif
71
72 /* ELF program property for x86 ISA level. */
73 #ifdef INCLUDE_X86_ISA_LEVEL
74 # if defined __x86_64__ || defined __FXSR__ || !defined _SOFT_FLOAT \
75 || defined __MMX__ || defined __SSE__ || defined __SSE2__
76+# if !defined __SSE__ || !defined __SSE2__
77+# error "Missing ISAs for x86-64 ISA level baseline"
78+# endif
79 # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE
80 # else
81 # define ISA_BASELINE 0
82@@ -40,6 +45,11 @@
83 || (defined __x86_64__ && defined __LAHF_SAHF__) \
84 || defined __POPCNT__ || defined __SSE3__ \
85 || defined __SSSE3__ || defined __SSE4_1__ || defined __SSE4_2__
86+# if !defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
87+ || !defined __POPCNT__ || !defined __SSE3__ \
88+ || !defined __SSSE3__ || !defined __SSE4_1__ || !defined __SSE4_2__
89+# error "Missing ISAs for x86-64 ISA level v2"
90+# endif
91 # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2
92 # else
93 # define ISA_V2 0
94@@ -48,6 +58,10 @@
95 # if defined __AVX__ || defined __AVX2__ || defined __F16C__ \
96 || defined __FMA__ || defined __LZCNT__ || defined __MOVBE__ \
97 || defined __XSAVE__
98+# if !defined __AVX__ || !defined __AVX2__ || !defined __F16C__ \
99+ || !defined __FMA__ || !defined __LZCNT__
100+# error "Missing ISAs for x86-64 ISA level v3"
101+# endif
102 # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3
103 # else
104 # define ISA_V3 0
105@@ -55,6 +69,11 @@
106
107 # if defined __AVX512F__ || defined __AVX512BW__ || defined __AVX512CD__ \
108 || defined __AVX512DQ__ || defined __AVX512VL__
109+# if !defined __AVX512F__ || !defined __AVX512BW__ \
110+ || !defined __AVX512CD__ || !defined __AVX512DQ__ \
111+ || !defined __AVX512VL__
112+# error "Missing ISAs for x86-64 ISA level v4"
113+# endif
114 # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4
115 # else
116 # define ISA_V4 0
diff --git a/meta/recipes-core/glibc/glibc/0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch b/meta/recipes-core/glibc/glibc/0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch
deleted file mode 100644
index e904b28a05..0000000000
--- a/meta/recipes-core/glibc/glibc/0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch
+++ /dev/null
@@ -1,58 +0,0 @@
1From 044e603b698093cf48f6e6229e0b66acf05227e4 Mon Sep 17 00:00:00 2001
2From: Florian Weimer <fweimer@redhat.com>
3Date: Fri, 19 Feb 2021 13:29:00 +0100
4Subject: [PATCH] string: Work around GCC PR 98512 in rawmemchr
5
6Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=044e603b698093cf48f6e6229e0b66acf05227e4]
7Signed-off-by: Khem Raj <raj.khem@gmail.com>
8---
9 string/rawmemchr.c | 26 +++++++++++++++-----------
10 1 file changed, 15 insertions(+), 11 deletions(-)
11
12diff --git a/string/rawmemchr.c b/string/rawmemchr.c
13index 59bbeeaa42..b8523118e5 100644
14--- a/string/rawmemchr.c
15+++ b/string/rawmemchr.c
16@@ -22,24 +22,28 @@
17 # define RAWMEMCHR __rawmemchr
18 #endif
19
20-/* Find the first occurrence of C in S. */
21-void *
22-RAWMEMCHR (const void *s, int c)
23-{
24- DIAG_PUSH_NEEDS_COMMENT;
25+/* The pragmata should be nested inside RAWMEMCHR below, but that
26+ triggers GCC PR 98512. */
27+DIAG_PUSH_NEEDS_COMMENT;
28 #if __GNUC_PREREQ (7, 0)
29- /* GCC 8 warns about the size passed to memchr being larger than
30- PTRDIFF_MAX; the use of SIZE_MAX is deliberate here. */
31- DIAG_IGNORE_NEEDS_COMMENT (8, "-Wstringop-overflow=");
32+/* GCC 8 warns about the size passed to memchr being larger than
33+ PTRDIFF_MAX; the use of SIZE_MAX is deliberate here. */
34+DIAG_IGNORE_NEEDS_COMMENT (8, "-Wstringop-overflow=");
35 #endif
36 #if __GNUC_PREREQ (11, 0)
37- /* Likewise GCC 11, with a different warning option. */
38- DIAG_IGNORE_NEEDS_COMMENT (11, "-Wstringop-overread");
39+/* Likewise GCC 11, with a different warning option. */
40+DIAG_IGNORE_NEEDS_COMMENT (11, "-Wstringop-overread");
41 #endif
42+
43+/* Find the first occurrence of C in S. */
44+void *
45+RAWMEMCHR (const void *s, int c)
46+{
47 if (c != '\0')
48 return memchr (s, c, (size_t)-1);
49- DIAG_POP_NEEDS_COMMENT;
50 return (char *)s + strlen (s);
51 }
52 libc_hidden_def (__rawmemchr)
53 weak_alias (__rawmemchr, rawmemchr)
54+
55+DIAG_POP_NEEDS_COMMENT;
56--
572.30.1
58
diff --git a/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch b/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch
deleted file mode 100644
index 3a004e227f..0000000000
--- a/meta/recipes-core/glibc/glibc/0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch
+++ /dev/null
@@ -1,185 +0,0 @@
1From 750b00a1ddae220403fd892a6fd4e0791ffd154a Mon Sep 17 00:00:00 2001
2From: "H.J. Lu" <hjl.tools@gmail.com>
3Date: Fri, 18 Sep 2020 07:55:14 -0700
4Subject: [PATCH] x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]
5
6 x86: Move x86 processor cache info to cpu_features
7
8missed _SC_LEVEL1_ICACHE_LINESIZE.
9
101. Add level1_icache_linesize to struct cpu_features.
112. Initialize level1_icache_linesize by calling handle_intel,
12handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE.
133. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE.
14
15Upstream-Status: Backport [https://sourceware.org/bugzilla/show_bug.cgi?id=27444]
16Signed-off-by: Andrei Gherzan <andrei.gherzan@huawei.com>
17---
18 sysdeps/x86/Makefile | 8 +++
19 sysdeps/x86/cacheinfo.c | 3 +
20 sysdeps/x86/dl-cacheinfo.h | 6 ++
21 sysdeps/x86/include/cpu-features.h | 2 +
22 .../x86/tst-sysconf-cache-linesize-static.c | 1 +
23 sysdeps/x86/tst-sysconf-cache-linesize.c | 57 +++++++++++++++++++
24 6 files changed, 77 insertions(+)
25 create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize-static.c
26 create mode 100644 sysdeps/x86/tst-sysconf-cache-linesize.c
27
28diff --git a/sysdeps/x86/Makefile b/sysdeps/x86/Makefile
29index dd82674342..d231263051 100644
30--- a/sysdeps/x86/Makefile
31+++ b/sysdeps/x86/Makefile
32@@ -208,3 +208,11 @@ $(objpfx)check-cet.out: $(..)sysdeps/x86/check-cet.awk \
33 generated += check-cet.out
34 endif
35 endif
36+
37+ifeq ($(subdir),posix)
38+tests += \
39+ tst-sysconf-cache-linesize \
40+ tst-sysconf-cache-linesize-static
41+tests-static += \
42+ tst-sysconf-cache-linesize-static
43+endif
44diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
45index 7b8df45e3b..5ea4723ca6 100644
46--- a/sysdeps/x86/cacheinfo.c
47+++ b/sysdeps/x86/cacheinfo.c
48@@ -32,6 +32,9 @@ __cache_sysconf (int name)
49 case _SC_LEVEL1_ICACHE_SIZE:
50 return cpu_features->level1_icache_size;
51
52+ case _SC_LEVEL1_ICACHE_LINESIZE:
53+ return cpu_features->level1_icache_linesize;
54+
55 case _SC_LEVEL1_DCACHE_SIZE:
56 return cpu_features->level1_dcache_size;
57
58diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
59index a31fa0783a..7cd00b92f1 100644
60--- a/sysdeps/x86/dl-cacheinfo.h
61+++ b/sysdeps/x86/dl-cacheinfo.h
62@@ -707,6 +707,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
63 long int core;
64 unsigned int threads = 0;
65 unsigned long int level1_icache_size = -1;
66+ unsigned long int level1_icache_linesize = -1;
67 unsigned long int level1_dcache_size = -1;
68 unsigned long int level1_dcache_assoc = -1;
69 unsigned long int level1_dcache_linesize = -1;
70@@ -726,6 +727,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
71
72 level1_icache_size
73 = handle_intel (_SC_LEVEL1_ICACHE_SIZE, cpu_features);
74+ level1_icache_linesize
75+ = handle_intel (_SC_LEVEL1_ICACHE_LINESIZE, cpu_features);
76 level1_dcache_size = data;
77 level1_dcache_assoc
78 = handle_intel (_SC_LEVEL1_DCACHE_ASSOC, cpu_features);
79@@ -753,6 +756,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
80 shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
81
82 level1_icache_size = handle_zhaoxin (_SC_LEVEL1_ICACHE_SIZE);
83+ level1_icache_linesize = handle_zhaoxin (_SC_LEVEL1_ICACHE_LINESIZE);
84 level1_dcache_size = data;
85 level1_dcache_assoc = handle_zhaoxin (_SC_LEVEL1_DCACHE_ASSOC);
86 level1_dcache_linesize = handle_zhaoxin (_SC_LEVEL1_DCACHE_LINESIZE);
87@@ -772,6 +776,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
88 shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
89
90 level1_icache_size = handle_amd (_SC_LEVEL1_ICACHE_SIZE);
91+ level1_icache_linesize = handle_amd (_SC_LEVEL1_ICACHE_LINESIZE);
92 level1_dcache_size = data;
93 level1_dcache_assoc = handle_amd (_SC_LEVEL1_DCACHE_ASSOC);
94 level1_dcache_linesize = handle_amd (_SC_LEVEL1_DCACHE_LINESIZE);
95@@ -833,6 +838,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
96 }
97
98 cpu_features->level1_icache_size = level1_icache_size;
99+ cpu_features->level1_icache_linesize = level1_icache_linesize;
100 cpu_features->level1_dcache_size = level1_dcache_size;
101 cpu_features->level1_dcache_assoc = level1_dcache_assoc;
102 cpu_features->level1_dcache_linesize = level1_dcache_linesize;
103diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
104index 624736b40e..39a3f4f311 100644
105--- a/sysdeps/x86/include/cpu-features.h
106+++ b/sysdeps/x86/include/cpu-features.h
107@@ -874,6 +874,8 @@ struct cpu_features
108 unsigned long int rep_stosb_threshold;
109 /* _SC_LEVEL1_ICACHE_SIZE. */
110 unsigned long int level1_icache_size;
111+ /* _SC_LEVEL1_ICACHE_LINESIZE. */
112+ unsigned long int level1_icache_linesize;
113 /* _SC_LEVEL1_DCACHE_SIZE. */
114 unsigned long int level1_dcache_size;
115 /* _SC_LEVEL1_DCACHE_ASSOC. */
116diff --git a/sysdeps/x86/tst-sysconf-cache-linesize-static.c b/sysdeps/x86/tst-sysconf-cache-linesize-static.c
117new file mode 100644
118index 0000000000..152ae68821
119--- /dev/null
120+++ b/sysdeps/x86/tst-sysconf-cache-linesize-static.c
121@@ -0,0 +1 @@
122+#include "tst-sysconf-cache-linesize.c"
123diff --git a/sysdeps/x86/tst-sysconf-cache-linesize.c b/sysdeps/x86/tst-sysconf-cache-linesize.c
124new file mode 100644
125index 0000000000..642dbde5d2
126--- /dev/null
127+++ b/sysdeps/x86/tst-sysconf-cache-linesize.c
128@@ -0,0 +1,57 @@
129+/* Test system cache line sizes.
130+ Copyright (C) 2021 Free Software Foundation, Inc.
131+ This file is part of the GNU C Library.
132+
133+ The GNU C Library is free software; you can redistribute it and/or
134+ modify it under the terms of the GNU Lesser General Public
135+ License as published by the Free Software Foundation; either
136+ version 2.1 of the License, or (at your option) any later version.
137+
138+ The GNU C Library is distributed in the hope that it will be useful,
139+ but WITHOUT ANY WARRANTY; without even the implied warranty of
140+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
141+ Lesser General Public License for more details.
142+
143+ You should have received a copy of the GNU Lesser General Public
144+ License along with the GNU C Library; if not, see
145+ <https://www.gnu.org/licenses/>. */
146+
147+#include <stdio.h>
148+#include <stdlib.h>
149+#include <unistd.h>
150+#include <array_length.h>
151+
152+static struct
153+{
154+ const char *name;
155+ int _SC_val;
156+} sc_options[] =
157+ {
158+#define N(name) { "_SC_"#name, _SC_##name }
159+ N (LEVEL1_ICACHE_LINESIZE),
160+ N (LEVEL1_DCACHE_LINESIZE),
161+ N (LEVEL2_CACHE_LINESIZE)
162+ };
163+
164+static int
165+do_test (void)
166+{
167+ int result = EXIT_SUCCESS;
168+
169+ for (int i = 0; i < array_length (sc_options); ++i)
170+ {
171+ long int scret = sysconf (sc_options[i]._SC_val);
172+ if (scret < 0)
173+ {
174+ printf ("sysconf (%s) returned < 0 (%ld)\n",
175+ sc_options[i].name, scret);
176+ result = EXIT_FAILURE;
177+ }
178+ else
179+ printf ("sysconf (%s): %ld\n", sc_options[i].name, scret);
180+ }
181+
182+ return result;
183+}
184+
185+#include <support/test-driver.c>
diff --git a/meta/recipes-core/glibc/glibc/CVE-2021-27645.patch b/meta/recipes-core/glibc/glibc/CVE-2021-27645.patch
deleted file mode 100644
index 26c5c0d2a9..0000000000
--- a/meta/recipes-core/glibc/glibc/CVE-2021-27645.patch
+++ /dev/null
@@ -1,51 +0,0 @@
1From dca565886b5e8bd7966e15f0ca42ee5cff686673 Mon Sep 17 00:00:00 2001
2From: DJ Delorie <dj@redhat.com>
3Date: Thu, 25 Feb 2021 16:08:21 -0500
4Subject: [PATCH] nscd: Fix double free in netgroupcache [BZ #27462]
5
6In commit 745664bd798ec8fd50438605948eea594179fba1 a use-after-free
7was fixed, but this led to an occasional double-free. This patch
8tracks the "live" allocation better.
9
10Tested manually by a third party.
11
12Related: RHBZ 1927877
13
14Reviewed-by: Siddhesh Poyarekar <siddhesh@sourceware.org>
15Reviewed-by: Carlos O'Donell <carlos@redhat.com>
16
17Upstream-Status: Backport [https://sourceware.org/git/?p=glibc.git;a=commit;h=dca565886b5e8bd7966e15f0ca42ee5cff686673]
18
19CVE: CVE-2021-27645
20
21Reviewed-by: Carlos O'Donell <carlos@redhat.com>
22Signed-off-by: Khairul Rohaizzat Jamaluddin <khairul.rohaizzat.jamaluddin@intel.com>
23---
24 nscd/netgroupcache.c | 4 ++--
25 1 file changed, 2 insertions(+), 2 deletions(-)
26
27diff --git a/nscd/netgroupcache.c b/nscd/netgroupcache.c
28index dba6ceec1b..ad2daddafd 100644
29--- a/nscd/netgroupcache.c
30+++ b/nscd/netgroupcache.c
31@@ -248,7 +248,7 @@ addgetnetgrentX (struct database_dyn *db, int fd, request_header *req,
32 : NULL);
33 ndomain = (ndomain ? newbuf + ndomaindiff
34 : NULL);
35- buffer = newbuf;
36+ *tofreep = buffer = newbuf;
37 }
38
39 nhost = memcpy (buffer + bufused,
40@@ -319,7 +319,7 @@ addgetnetgrentX (struct database_dyn *db, int fd, request_header *req,
41 else if (status == NSS_STATUS_TRYAGAIN && e == ERANGE)
42 {
43 buflen *= 2;
44- buffer = xrealloc (buffer, buflen);
45+ *tofreep = buffer = xrealloc (buffer, buflen);
46 }
47 else if (status == NSS_STATUS_RETURN
48 || status == NSS_STATUS_NOTFOUND
49--
502.27.0
51
diff --git a/meta/recipes-core/glibc/glibc_2.33.bb b/meta/recipes-core/glibc/glibc_2.33.bb
index 75a1f36d6b..6bdfdfcd4a 100644
--- a/meta/recipes-core/glibc/glibc_2.33.bb
+++ b/meta/recipes-core/glibc/glibc_2.33.bb
@@ -1,7 +1,7 @@
1require glibc.inc 1require glibc.inc
2require glibc-version.inc 2require glibc-version.inc
3 3
4CVE_CHECK_WHITELIST += "CVE-2020-10029" 4CVE_CHECK_WHITELIST += "CVE-2020-10029 CVE-2021-27645"
5 5
6# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010022 6# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010022
7# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010023 7# glibc https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2019-1010023
@@ -56,11 +56,6 @@ SRC_URI = "${GLIBC_GIT_URI};branch=${SRCBRANCH};name=glibc \
56 file://0028-readlib-Add-OECORE_KNOWN_INTERPRETER_NAMES-to-known-.patch \ 56 file://0028-readlib-Add-OECORE_KNOWN_INTERPRETER_NAMES-to-known-.patch \
57 file://0029-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch \ 57 file://0029-wordsize.h-Unify-the-header-between-arm-and-aarch64.patch \
58 file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch \ 58 file://0030-powerpc-Do-not-ask-compiler-for-finding-arch.patch \
59 file://0031-x86-Require-full-ISA-support-for-x86-64-level-marker.patch \
60 file://0032-string-Work-around-GCC-PR-98512-in-rawmemchr.patch \
61 file://0033-x86-Handle-_SC_LEVEL1_ICACHE_LINESIZE-BZ-27444.patch \
62 file://CVE-2021-27645.patch \
63 file://0001-nptl-Remove-private-futex-optimization-BZ-27304.patch \
64 " 59 "
65S = "${WORKDIR}/git" 60S = "${WORKDIR}/git"
66B = "${WORKDIR}/build-${TARGET_SYS}" 61B = "${WORKDIR}/build-${TARGET_SYS}"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 02:46:35 +0000