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authorRichard Purdie <rpurdie@linux.intel.com>2009-02-05 14:05:03 +0000
committerRichard Purdie <rpurdie@linux.intel.com>2009-02-05 14:05:03 +0000
commitcc01c77c99811094c6dbdaddfaf9fe4445d8afb8 (patch)
tree5cea7dfcfa9165253a0a67dd57f96fde3003f4df
parente5f1566660f4434ac26c9fb056b6ec7a7d68bff8 (diff)
downloadpoky-cc01c77c99811094c6dbdaddfaf9fe4445d8afb8.tar.gz
meta-moblin: Drop now uneeded libdrm-psb
Diffstat
-rw-r--r--meta-moblin/packages/drm/files/poulsbo.patch4050
-rw-r--r--meta-moblin/packages/drm/libdrm-psb_2.3.1.bb17
2 files changed, 0 insertions, 4067 deletions
diff --git a/meta-moblin/packages/drm/files/poulsbo.patch b/meta-moblin/packages/drm/files/poulsbo.patch
deleted file mode 100644
index 13a16bfd74..0000000000
--- a/meta-moblin/packages/drm/files/poulsbo.patch
+++ /dev/null
@@ -1,4050 +0,0 @@
1Index: libdrm-2.3.1/configure.ac
2===================================================================
3--- libdrm-2.3.1.orig/configure.ac 2008-07-01 08:50:43.000000000 +0100
4+++ libdrm-2.3.1/configure.ac 2009-01-14 18:26:59.000000000 +0000
5@@ -39,5 +39,4 @@
6 Makefile
7 libdrm/Makefile
8 shared-core/Makefile
9- tests/Makefile
10 libdrm.pc])
11Index: libdrm-2.3.1/libdrm/Makefile.am
12===================================================================
13--- libdrm-2.3.1.orig/libdrm/Makefile.am 2008-07-01 08:51:40.000000000 +0100
14+++ libdrm-2.3.1/libdrm/Makefile.am 2009-01-14 18:26:59.000000000 +0000
15@@ -23,10 +23,9 @@
16 libdrm_la_LDFLAGS = -version-number 2:3:1 -no-undefined
17
18 AM_CFLAGS = -I$(top_srcdir)/shared-core
19-libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c
20+libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c xf86drmMode.c
21
22 libdrmincludedir = ${includedir}
23-
24-libdrminclude_HEADERS = xf86drm.h
25+libdrminclude_HEADERS = xf86drm.h xf86mm.h xf86drmMode.h
26
27 EXTRA_DIST = ChangeLog TODO
28Index: libdrm-2.3.1/libdrm/xf86drm.c
29===================================================================
30--- libdrm-2.3.1.orig/libdrm/xf86drm.c 2008-07-01 08:51:40.000000000 +0100
31+++ libdrm-2.3.1/libdrm/xf86drm.c 2009-01-14 18:26:59.000000000 +0000
32@@ -2337,6 +2337,569 @@
33 return 0;
34 }
35
36+
37+/*
38+ * Valid flags are
39+ * DRM_FENCE_FLAG_EMIT
40+ * DRM_FENCE_FLAG_SHAREABLE
41+ * DRM_FENCE_MASK_DRIVER
42+ */
43+
44+int drmFenceCreate(int fd, unsigned flags, int fence_class, unsigned type,
45+ drmFence *fence)
46+{
47+ drm_fence_arg_t arg;
48+
49+ memset(&arg, 0, sizeof(arg));
50+ arg.flags = flags;
51+ arg.type = type;
52+ arg.fence_class = fence_class;
53+
54+ if (ioctl(fd, DRM_IOCTL_FENCE_CREATE, &arg))
55+ return -errno;
56+ fence->handle = arg.handle;
57+ fence->fence_class = arg.fence_class;
58+ fence->type = arg.type;
59+ fence->flags = arg.flags;
60+ fence->signaled = 0;
61+ return 0;
62+}
63+
64+/*
65+ * Valid flags are
66+ * DRM_FENCE_FLAG_SHAREABLE
67+ * DRM_FENCE_MASK_DRIVER
68+ */
69+
70+int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence)
71+{
72+ drm_fence_arg_t arg;
73+
74+ memset(&arg, 0, sizeof(arg));
75+ arg.flags = flags;
76+ arg.fence_class = fence_class;
77+
78+ if (ioctl(fd, DRM_IOCTL_FENCE_BUFFERS, &arg))
79+ return -errno;
80+ fence->handle = arg.handle;
81+ fence->fence_class = arg.fence_class;
82+ fence->type = arg.type;
83+ fence->flags = arg.flags;
84+ fence->sequence = arg.sequence;
85+ fence->signaled = 0;
86+ return 0;
87+}
88+
89+int drmFenceReference(int fd, unsigned handle, drmFence *fence)
90+{
91+ drm_fence_arg_t arg;
92+
93+ memset(&arg, 0, sizeof(arg));
94+ arg.handle = handle;
95+
96+ if (ioctl(fd, DRM_IOCTL_FENCE_REFERENCE, &arg))
97+ return -errno;
98+ fence->handle = arg.handle;
99+ fence->fence_class = arg.fence_class;
100+ fence->type = arg.type;
101+ fence->flags = arg.flags;
102+ fence->signaled = arg.signaled;
103+ return 0;
104+}
105+
106+int drmFenceUnreference(int fd, const drmFence *fence)
107+{
108+ drm_fence_arg_t arg;
109+
110+ memset(&arg, 0, sizeof(arg));
111+ arg.handle = fence->handle;
112+
113+ if (ioctl(fd, DRM_IOCTL_FENCE_UNREFERENCE, &arg))
114+ return -errno;
115+ return 0;
116+}
117+
118+int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type)
119+{
120+ drm_fence_arg_t arg;
121+
122+ memset(&arg, 0, sizeof(arg));
123+ arg.handle = fence->handle;
124+ arg.type = flush_type;
125+
126+ if (ioctl(fd, DRM_IOCTL_FENCE_FLUSH, &arg))
127+ return -errno;
128+ fence->fence_class = arg.fence_class;
129+ fence->type = arg.type;
130+ fence->signaled = arg.signaled;
131+ return arg.error;
132+}
133+
134+int drmFenceUpdate(int fd, drmFence *fence)
135+{
136+ drm_fence_arg_t arg;
137+
138+ memset(&arg, 0, sizeof(arg));
139+ arg.handle = fence->handle;
140+
141+ if (ioctl(fd, DRM_IOCTL_FENCE_SIGNALED, &arg))
142+ return -errno;
143+ fence->fence_class = arg.fence_class;
144+ fence->type = arg.type;
145+ fence->signaled = arg.signaled;
146+ return 0;
147+}
148+
149+int drmFenceSignaled(int fd, drmFence *fence, unsigned fenceType,
150+ int *signaled)
151+{
152+ if ((fence->flags & DRM_FENCE_FLAG_SHAREABLE) ||
153+ ((fenceType & fence->signaled) != fenceType)) {
154+ int ret = drmFenceFlush(fd, fence, fenceType);
155+ if (ret)
156+ return ret;
157+ }
158+
159+ *signaled = ((fenceType & fence->signaled) == fenceType);
160+
161+ return 0;
162+}
163+
164+/*
165+ * Valid flags are
166+ * DRM_FENCE_FLAG_SHAREABLE
167+ * DRM_FENCE_MASK_DRIVER
168+ */
169+
170+
171+int drmFenceEmit(int fd, unsigned flags, drmFence *fence, unsigned emit_type)
172+{
173+ drm_fence_arg_t arg;
174+
175+ memset(&arg, 0, sizeof(arg));
176+ arg.fence_class = fence->fence_class;
177+ arg.flags = flags;
178+ arg.handle = fence->handle;
179+ arg.type = emit_type;
180+
181+ if (ioctl(fd, DRM_IOCTL_FENCE_EMIT, &arg))
182+ return -errno;
183+ fence->fence_class = arg.fence_class;
184+ fence->type = arg.type;
185+ fence->signaled = arg.signaled;
186+ fence->sequence = arg.sequence;
187+ return 0;
188+}
189+
190+/*
191+ * Valid flags are
192+ * DRM_FENCE_FLAG_WAIT_LAZY
193+ * DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS
194+ */
195+
196+#define DRM_IOCTL_TIMEOUT_USEC 3000000UL
197+
198+static unsigned long
199+drmTimeDiff(struct timeval *now, struct timeval *then)
200+{
201+ uint64_t val;
202+
203+ val = now->tv_sec - then->tv_sec;
204+ val *= 1000000LL;
205+ val += now->tv_usec;
206+ val -= then->tv_usec;
207+
208+ return (unsigned long) val;
209+}
210+
211+static int
212+drmIoctlTimeout(int fd, unsigned long request, void *argp)
213+{
214+ int haveThen = 0;
215+ struct timeval then, now;
216+ int ret;
217+
218+ do {
219+ ret = ioctl(fd, request, argp);
220+ if (ret != 0 && errno == EAGAIN) {
221+ if (!haveThen) {
222+ gettimeofday(&then, NULL);
223+ haveThen = 1;
224+ }
225+ gettimeofday(&now, NULL);
226+ }
227+ } while (ret != 0 && errno == EAGAIN &&
228+ drmTimeDiff(&now, &then) < DRM_IOCTL_TIMEOUT_USEC);
229+
230+ if (ret != 0)
231+ return ((errno == EAGAIN) ? -EBUSY : -errno);
232+
233+ return 0;
234+}
235+
236+
237+
238+
239+int drmFenceWait(int fd, unsigned flags, drmFence *fence, unsigned flush_type)
240+{
241+ drm_fence_arg_t arg;
242+ int ret;
243+
244+ if (flush_type == 0) {
245+ flush_type = fence->type;
246+ }
247+
248+ if (!(fence->flags & DRM_FENCE_FLAG_SHAREABLE)) {
249+ if ((flush_type & fence->signaled) == flush_type) {
250+ return 0;
251+ }
252+ }
253+
254+ memset(&arg, 0, sizeof(arg));
255+ arg.handle = fence->handle;
256+ arg.type = flush_type;
257+ arg.flags = flags;
258+
259+
260+ ret = drmIoctlTimeout(fd, DRM_IOCTL_FENCE_WAIT, &arg);
261+ if (ret)
262+ return ret;
263+
264+ fence->fence_class = arg.fence_class;
265+ fence->type = arg.type;
266+ fence->signaled = arg.signaled;
267+ return arg.error;
268+}
269+
270+static void drmBOCopyReply(const struct drm_bo_info_rep *rep, drmBO *buf)
271+{
272+ buf->handle = rep->handle;
273+ buf->flags = rep->flags;
274+ buf->size = rep->size;
275+ buf->offset = rep->offset;
276+ buf->mapHandle = rep->arg_handle;
277+ buf->mask = rep->mask;
278+ buf->start = rep->buffer_start;
279+ buf->fenceFlags = rep->fence_flags;
280+ buf->replyFlags = rep->rep_flags;
281+ buf->pageAlignment = rep->page_alignment;
282+ buf->tileInfo = rep->tile_info;
283+ buf->hwTileStride = rep->hw_tile_stride;
284+ buf->desiredTileStride = rep->desired_tile_stride;
285+}
286+
287+
288+
289+int drmBOCreate(int fd, unsigned long size,
290+ unsigned pageAlignment, void *user_buffer,
291+ uint64_t mask,
292+ unsigned hint, drmBO *buf)
293+{
294+ struct drm_bo_create_arg arg;
295+ struct drm_bo_create_req *req = &arg.d.req;
296+ struct drm_bo_info_rep *rep = &arg.d.rep;
297+ int ret;
298+
299+ memset(buf, 0, sizeof(*buf));
300+ memset(&arg, 0, sizeof(arg));
301+ req->mask = mask;
302+ req->hint = hint;
303+ req->size = size;
304+ req->page_alignment = pageAlignment;
305+ req->buffer_start = (unsigned long) user_buffer;
306+
307+ buf->virtual = NULL;
308+
309+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_CREATE, &arg);
310+ if (ret)
311+ return ret;
312+
313+ drmBOCopyReply(rep, buf);
314+ buf->virtual = user_buffer;
315+ buf->mapCount = 0;
316+
317+ return 0;
318+}
319+
320+int drmBOReference(int fd, unsigned handle, drmBO *buf)
321+{
322+ struct drm_bo_reference_info_arg arg;
323+ struct drm_bo_handle_arg *req = &arg.d.req;
324+ struct drm_bo_info_rep *rep = &arg.d.rep;
325+
326+ memset(&arg, 0, sizeof(arg));
327+ req->handle = handle;
328+
329+ if (ioctl(fd, DRM_IOCTL_BO_REFERENCE, &arg))
330+ return -errno;
331+
332+ drmBOCopyReply(rep, buf);
333+ buf->mapVirtual = NULL;
334+ buf->mapCount = 0;
335+ buf->virtual = NULL;
336+
337+ return 0;
338+}
339+
340+int drmBOUnreference(int fd, drmBO *buf)
341+{
342+ struct drm_bo_handle_arg arg;
343+
344+ if (buf->mapVirtual && buf->mapHandle) {
345+ (void) munmap(buf->mapVirtual, buf->start + buf->size);
346+ buf->mapVirtual = NULL;
347+ buf->virtual = NULL;
348+ }
349+
350+ memset(&arg, 0, sizeof(arg));
351+ arg.handle = buf->handle;
352+
353+ if (ioctl(fd, DRM_IOCTL_BO_UNREFERENCE, &arg))
354+ return -errno;
355+
356+ buf->handle = 0;
357+ return 0;
358+}
359+
360+
361+/*
362+ * Flags can be DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE or'ed together
363+ * Hint currently be DRM_BO_HINT_DONT_BLOCK, which makes the
364+ * call return an -EBUSY if it can' immediately honor the mapping request.
365+ */
366+
367+int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
368+ void **address)
369+{
370+ struct drm_bo_map_wait_idle_arg arg;
371+ struct drm_bo_info_req *req = &arg.d.req;
372+ struct drm_bo_info_rep *rep = &arg.d.rep;
373+ int ret = 0;
374+
375+ /*
376+ * Make sure we have a virtual address of the buffer.
377+ */
378+
379+ if (!buf->virtual) {
380+ drmAddress virtual;
381+ virtual = mmap(0, buf->size + buf->start,
382+ PROT_READ | PROT_WRITE, MAP_SHARED,
383+ fd, buf->mapHandle);
384+ if (virtual == MAP_FAILED) {
385+ ret = -errno;
386+ }
387+ if (ret)
388+ return ret;
389+ buf->mapVirtual = virtual;
390+ buf->virtual = ((char *) virtual) + buf->start;
391+ }
392+
393+ memset(&arg, 0, sizeof(arg));
394+ req->handle = buf->handle;
395+ req->mask = mapFlags;
396+ req->hint = mapHint;
397+
398+ /*
399+ * May hang if the buffer object is busy.
400+ * This IOCTL synchronizes the buffer.
401+ */
402+
403+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_MAP, &arg);
404+ if (ret)
405+ return ret;
406+
407+ drmBOCopyReply(rep, buf);
408+ buf->mapFlags = mapFlags;
409+ ++buf->mapCount;
410+ *address = buf->virtual;
411+
412+ return 0;
413+}
414+
415+
416+int drmBOUnmap(int fd, drmBO *buf)
417+{
418+ struct drm_bo_handle_arg arg;
419+
420+ memset(&arg, 0, sizeof(arg));
421+ arg.handle = buf->handle;
422+
423+ if (ioctl(fd, DRM_IOCTL_BO_UNMAP, &arg)) {
424+ return -errno;
425+ }
426+ buf->mapCount--;
427+ return 0;
428+}
429+
430+int drmBOSetStatus(int fd, drmBO *buf,
431+ uint64_t flags, uint64_t mask,
432+ unsigned int hint,
433+ unsigned int desired_tile_stride,
434+ unsigned int tile_info)
435+{
436+
437+ struct drm_bo_map_wait_idle_arg arg;
438+ struct drm_bo_info_req *req = &arg.d.req;
439+ struct drm_bo_info_rep *rep = &arg.d.rep;
440+ int ret = 0;
441+
442+ memset(&arg, 0, sizeof(arg));
443+ req->mask = mask;
444+ req->flags = flags;
445+ req->handle = buf->handle;
446+ req->hint = hint;
447+ req->desired_tile_stride = desired_tile_stride;
448+ req->tile_info = tile_info;
449+
450+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_SETSTATUS, &arg);
451+ if (ret)
452+ return ret;
453+
454+ drmBOCopyReply(rep, buf);
455+ return 0;
456+}
457+
458+
459+int drmBOInfo(int fd, drmBO *buf)
460+{
461+ struct drm_bo_reference_info_arg arg;
462+ struct drm_bo_handle_arg *req = &arg.d.req;
463+ struct drm_bo_info_rep *rep = &arg.d.rep;
464+ int ret = 0;
465+
466+ memset(&arg, 0, sizeof(arg));
467+ req->handle = buf->handle;
468+
469+ ret = ioctl(fd, DRM_IOCTL_BO_INFO, &arg);
470+ if (ret)
471+ return -errno;
472+
473+ drmBOCopyReply(rep, buf);
474+ return 0;
475+}
476+
477+int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint)
478+{
479+ struct drm_bo_map_wait_idle_arg arg;
480+ struct drm_bo_info_req *req = &arg.d.req;
481+ struct drm_bo_info_rep *rep = &arg.d.rep;
482+ int ret = 0;
483+
484+ if ((buf->flags & DRM_BO_FLAG_SHAREABLE) ||
485+ (buf->replyFlags & DRM_BO_REP_BUSY)) {
486+ memset(&arg, 0, sizeof(arg));
487+ req->handle = buf->handle;
488+ req->hint = hint;
489+
490+ ret = drmIoctlTimeout(fd, DRM_IOCTL_BO_WAIT_IDLE, &arg);
491+ if (ret)
492+ return ret;
493+
494+ drmBOCopyReply(rep, buf);
495+ }
496+ return 0;
497+}
498+
499+int drmBOBusy(int fd, drmBO *buf, int *busy)
500+{
501+ if (!(buf->flags & DRM_BO_FLAG_SHAREABLE) &&
502+ !(buf->replyFlags & DRM_BO_REP_BUSY)) {
503+ *busy = 0;
504+ return 0;
505+ }
506+ else {
507+ int ret = drmBOInfo(fd, buf);
508+ if (ret)
509+ return ret;
510+ *busy = (buf->replyFlags & DRM_BO_REP_BUSY);
511+ return 0;
512+ }
513+}
514+
515+int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
516+ unsigned memType)
517+{
518+ struct drm_mm_init_arg arg;
519+
520+ memset(&arg, 0, sizeof(arg));
521+
522+ arg.magic = DRM_BO_INIT_MAGIC;
523+ arg.major = DRM_BO_INIT_MAJOR;
524+ arg.minor = DRM_BO_INIT_MINOR;
525+ arg.p_offset = pOffset;
526+ arg.p_size = pSize;
527+ arg.mem_type = memType;
528+
529+ if (ioctl(fd, DRM_IOCTL_MM_INIT, &arg))
530+ return -errno;
531+ return 0;
532+}
533+
534+int drmMMTakedown(int fd, unsigned memType)
535+{
536+ struct drm_mm_type_arg arg;
537+
538+ memset(&arg, 0, sizeof(arg));
539+ arg.mem_type = memType;
540+
541+ if (ioctl(fd, DRM_IOCTL_MM_TAKEDOWN, &arg))
542+ return -errno;
543+ return 0;
544+}
545+
546+/*
547+ * If this function returns an error, and lockBM was set to 1,
548+ * the buffer manager is NOT locked.
549+ */
550+
551+int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict)
552+{
553+ struct drm_mm_type_arg arg;
554+
555+ memset(&arg, 0, sizeof(arg));
556+ arg.mem_type = memType;
557+ arg.lock_flags |= (lockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
558+ arg.lock_flags |= (ignoreNoEvict) ? DRM_BO_LOCK_IGNORE_NO_EVICT : 0;
559+
560+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_LOCK, &arg);
561+}
562+
563+int drmMMUnlock(int fd, unsigned memType, int unlockBM)
564+{
565+ struct drm_mm_type_arg arg;
566+
567+ memset(&arg, 0, sizeof(arg));
568+
569+ arg.mem_type = memType;
570+ arg.lock_flags |= (unlockBM) ? DRM_BO_LOCK_UNLOCK_BM : 0;
571+
572+ return drmIoctlTimeout(fd, DRM_IOCTL_MM_UNLOCK, &arg);
573+}
574+
575+int drmBOVersion(int fd, unsigned int *major,
576+ unsigned int *minor,
577+ unsigned int *patchlevel)
578+{
579+ struct drm_bo_version_arg arg;
580+ int ret;
581+
582+ memset(&arg, 0, sizeof(arg));
583+ ret = ioctl(fd, DRM_IOCTL_BO_VERSION, &arg);
584+ if (ret)
585+ return -errno;
586+
587+ if (major)
588+ *major = arg.major;
589+ if (minor)
590+ *minor = arg.minor;
591+ if (patchlevel)
592+ *patchlevel = arg.patchlevel;
593+
594+ return 0;
595+}
596+
597+
598+
599 #define DRM_MAX_FDS 16
600 static struct {
601 char *BusID;
602Index: libdrm-2.3.1/libdrm/xf86drm.h
603===================================================================
604--- libdrm-2.3.1.orig/libdrm/xf86drm.h 2008-07-01 08:51:40.000000000 +0100
605+++ libdrm-2.3.1/libdrm/xf86drm.h 2009-01-14 18:26:59.000000000 +0000
606@@ -658,4 +658,6 @@
607 extern int drmOpenOnce(void *unused, const char *BusID, int *newlyopened);
608 extern void drmCloseOnce(int fd);
609
610+#include "xf86mm.h"
611+
612 #endif
613Index: libdrm-2.3.1/libdrm/xf86drmMode.c
614===================================================================
615--- /dev/null 1970-01-01 00:00:00.000000000 +0000
616+++ libdrm-2.3.1/libdrm/xf86drmMode.c 2009-01-14 18:26:59.000000000 +0000
617@@ -0,0 +1,465 @@
618+/*
619+ * \file xf86drmMode.c
620+ * Header for DRM modesetting interface.
621+ *
622+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
623+ *
624+ * \par Acknowledgements:
625+ * Feb 2007, Dave Airlie <airlied@linux.ie>
626+ */
627+
628+/*
629+ * Copyright (c) <year> <copyright holders>
630+ *
631+ * Permission is hereby granted, free of charge, to any person obtaining a
632+ * copy of this software and associated documentation files (the "Software"),
633+ * to deal in the Software without restriction, including without limitation
634+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
635+ * and/or sell copies of the Software, and to permit persons to whom the
636+ * Software is furnished to do so, subject to the following conditions:
637+ *
638+ * The above copyright notice and this permission notice shall be included in
639+ * all copies or substantial portions of the Software.
640+ *
641+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
642+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
643+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
644+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
645+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
646+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
647+ * IN THE SOFTWARE.
648+ *
649+ */
650+
651+/*
652+ * TODO the types we are after are defined in diffrent headers on diffrent
653+ * platforms find which headers to include to get uint32_t
654+ */
655+#include <stdint.h>
656+
657+#include "xf86drmMode.h"
658+#include "xf86drm.h"
659+#include <drm.h>
660+#include <string.h>
661+
662+/*
663+ * Util functions
664+ */
665+
666+void* drmAllocCpy(void *array, int count, int entry_size)
667+{
668+ char *r;
669+ int i;
670+
671+ if (!count || !array || !entry_size)
672+ return 0;
673+
674+ if (!(r = drmMalloc(count*entry_size)))
675+ return 0;
676+
677+ for (i = 0; i < count; i++)
678+ memcpy(r+(entry_size*i), array+(entry_size*i), entry_size);
679+
680+ return r;
681+}
682+
683+/**
684+ * Generate crtc and output ids.
685+ *
686+ * Will generate ids starting from 1 up to count if count is greater then 0.
687+ */
688+static uint32_t* drmAllocGenerate(int count)
689+{
690+ uint32_t *r;
691+ int i;
692+
693+ if(0 <= count)
694+ return 0;
695+
696+ if (!(r = drmMalloc(count*sizeof(*r))))
697+ return 0;
698+
699+ for (i = 0; i < count; r[i] = ++i);
700+
701+ return 0;
702+}
703+
704+/*
705+ * A couple of free functions.
706+ */
707+
708+void drmModeFreeModeInfo(struct drm_mode_modeinfo *ptr)
709+{
710+ if (!ptr)
711+ return;
712+
713+ drmFree(ptr);
714+}
715+
716+void drmModeFreeResources(drmModeResPtr ptr)
717+{
718+ if (!ptr)
719+ return;
720+
721+ drmFree(ptr->modes);
722+ drmFree(ptr);
723+
724+}
725+
726+void drmModeFreeFB(drmModeFBPtr ptr)
727+{
728+ if (!ptr)
729+ return;
730+
731+ /* we might add more frees later. */
732+ drmFree(ptr);
733+}
734+
735+void drmModeFreeCrtc(drmModeCrtcPtr ptr)
736+{
737+ if (!ptr)
738+ return;
739+
740+ drmFree(ptr);
741+
742+}
743+
744+void drmModeFreeOutput(drmModeOutputPtr ptr)
745+{
746+ if (!ptr)
747+ return;
748+
749+ drmFree(ptr->modes);
750+ drmFree(ptr);
751+
752+}
753+
754+/*
755+ * ModeSetting functions.
756+ */
757+
758+drmModeResPtr drmModeGetResources(int fd)
759+{
760+ struct drm_mode_card_res res;
761+ int i;
762+ drmModeResPtr r = 0;
763+
764+ memset(&res, 0, sizeof(struct drm_mode_card_res));
765+
766+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res))
767+ return 0;
768+
769+ if (res.count_fbs)
770+ res.fb_id = drmMalloc(res.count_fbs*sizeof(uint32_t));
771+ if (res.count_crtcs)
772+ res.crtc_id = drmMalloc(res.count_crtcs*sizeof(uint32_t));
773+ if (res.count_outputs)
774+ res.output_id = drmMalloc(res.count_outputs*sizeof(uint32_t));
775+ if (res.count_modes)
776+ res.modes = drmMalloc(res.count_modes*sizeof(*res.modes));
777+
778+ if (ioctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) {
779+ r = NULL;
780+ goto err_allocs;
781+ }
782+
783+ /*
784+ * return
785+ */
786+
787+
788+ if (!(r = drmMalloc(sizeof(*r))))
789+ return 0;
790+
791+ r->count_fbs = res.count_fbs;
792+ r->count_crtcs = res.count_crtcs;
793+ r->count_outputs = res.count_outputs;
794+ r->count_modes = res.count_modes;
795+ /* TODO we realy should test if these allocs fails. */
796+ r->fbs = drmAllocCpy(res.fb_id, res.count_fbs, sizeof(uint32_t));
797+ r->crtcs = drmAllocCpy(res.crtc_id, res.count_crtcs, sizeof(uint32_t));
798+ r->outputs = drmAllocCpy(res.output_id, res.count_outputs, sizeof(uint32_t));
799+ r->modes = drmAllocCpy(res.modes, res.count_modes, sizeof(struct drm_mode_modeinfo));
800+
801+err_allocs:
802+ drmFree(res.fb_id);
803+ drmFree(res.crtc_id);
804+ drmFree(res.output_id);
805+ drmFree(res.modes);
806+
807+ return r;
808+}
809+
810+int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
811+ uint8_t bpp, uint32_t pitch, drmBO *bo, uint32_t *buf_id)
812+{
813+ struct drm_mode_fb_cmd f;
814+ int ret;
815+
816+ f.width = width;
817+ f.height = height;
818+ f.pitch = pitch;
819+ f.bpp = bpp;
820+ f.depth = depth;
821+ f.handle = bo->handle;
822+
823+ if (ret = ioctl(fd, DRM_IOCTL_MODE_ADDFB, &f))
824+ return ret;
825+
826+ *buf_id = f.buffer_id;
827+ return 0;
828+}
829+
830+int drmModeRmFB(int fd, uint32_t bufferId)
831+{
832+ return ioctl(fd, DRM_IOCTL_MODE_RMFB, &bufferId);
833+}
834+
835+drmModeFBPtr drmModeGetFB(int fd, uint32_t buf)
836+{
837+ struct drm_mode_fb_cmd info;
838+ drmModeFBPtr r;
839+
840+ info.buffer_id = buf;
841+
842+ if (ioctl(fd, DRM_IOCTL_MODE_GETFB, &info))
843+ return NULL;
844+
845+ if (!(r = drmMalloc(sizeof(*r))))
846+ return NULL;
847+
848+ r->buffer_id = info.buffer_id;
849+ r->width = info.width;
850+ r->height = info.height;
851+ r->pitch = info.pitch;
852+ r->bpp = info.bpp;
853+ r->handle = info.handle;
854+ r->depth = info.depth;
855+
856+ return r;
857+}
858+
859+
860+/*
861+ * Crtc functions
862+ */
863+
864+drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
865+{
866+ struct drm_mode_crtc crtc;
867+ drmModeCrtcPtr r;
868+ int i = 0;
869+
870+ crtc.count_outputs = 0;
871+ crtc.outputs = 0;
872+ crtc.count_possibles = 0;
873+ crtc.possibles = 0;
874+ crtc.crtc_id = crtcId;
875+
876+ if (ioctl(fd, DRM_IOCTL_MODE_GETCRTC, &crtc))
877+ return 0;
878+
879+ /*
880+ * return
881+ */
882+
883+ if (!(r = drmMalloc(sizeof(*r))))
884+ return 0;
885+
886+ r->crtc_id = crtc.crtc_id;
887+ r->x = crtc.x;
888+ r->y = crtc.y;
889+ r->mode = crtc.mode;
890+ r->buffer_id = crtc.fb_id;
891+ r->gamma_size = crtc.gamma_size;
892+ r->count_outputs = crtc.count_outputs;
893+ r->count_possibles = crtc.count_possibles;
894+ /* TODO we realy should test if these alloc & cpy fails. */
895+ r->outputs = crtc.outputs;
896+ r->possibles = crtc.possibles;
897+
898+ return r;
899+
900+err_allocs:
901+
902+ return 0;
903+}
904+
905+
906+int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
907+ uint32_t x, uint32_t y, uint32_t modeId,
908+ uint32_t *outputs, int count)
909+{
910+ struct drm_mode_crtc crtc;
911+
912+ crtc.count_outputs = 0;
913+ crtc.outputs = 0;
914+ crtc.count_possibles = 0;
915+ crtc.possibles = 0;
916+
917+ crtc.x = x;
918+ crtc.y = y;
919+ crtc.crtc_id = crtcId;
920+ crtc.fb_id = bufferId;
921+ crtc.set_outputs = outputs;
922+ crtc.count_outputs = count;
923+ crtc.mode = modeId;
924+
925+ return ioctl(fd, DRM_IOCTL_MODE_SETCRTC, &crtc);
926+}
927+
928+
929+/*
930+ * Output manipulation
931+ */
932+
933+drmModeOutputPtr drmModeGetOutput(int fd, uint32_t output_id)
934+{
935+ struct drm_mode_get_output out;
936+ drmModeOutputPtr r = NULL;
937+
938+ out.output = output_id;
939+ out.count_crtcs = 0;
940+ out.crtcs = 0;
941+ out.count_clones = 0;
942+ out.clones = 0;
943+ out.count_modes = 0;
944+ out.modes = 0;
945+ out.count_props = 0;
946+ out.props = NULL;
947+ out.prop_values = NULL;
948+
949+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
950+ return 0;
951+
952+ if (out.count_props) {
953+ out.props = drmMalloc(out.count_props*sizeof(uint32_t));
954+ out.prop_values = drmMalloc(out.count_props*sizeof(uint32_t));
955+ }
956+
957+ if (out.count_modes)
958+ out.modes = drmMalloc(out.count_modes*sizeof(uint32_t));
959+
960+ if (ioctl(fd, DRM_IOCTL_MODE_GETOUTPUT, &out))
961+ goto err_allocs;
962+
963+ if(!(r = drmMalloc(sizeof(*r)))) {
964+ goto err_allocs;
965+ }
966+
967+ r->output_id = out.output;
968+ r->crtc = out.crtc;
969+ r->connection = out.connection;
970+ r->mmWidth = out.mm_width;
971+ r->mmHeight = out.mm_height;
972+ r->subpixel = out.subpixel;
973+ r->count_crtcs = out.count_crtcs;
974+ r->count_clones = out.count_clones;
975+ r->count_modes = out.count_modes;
976+ /* TODO we should test if these alloc & cpy fails. */
977+ r->crtcs = out.crtcs;
978+ r->clones = out.clones;
979+ r->count_props = out.count_props;
980+ r->props = drmAllocCpy(out.props, out.count_props, sizeof(uint32_t));
981+ r->prop_values = drmAllocCpy(out.prop_values, out.count_props, sizeof(uint32_t));
982+ r->modes = drmAllocCpy(out.modes, out.count_modes, sizeof(uint32_t));
983+ strncpy(r->name, out.name, DRM_OUTPUT_NAME_LEN);
984+ r->name[DRM_OUTPUT_NAME_LEN-1] = 0;
985+
986+err_allocs:
987+ drmFree(out.prop_values);
988+ drmFree(out.props);
989+ drmFree(out.modes);
990+
991+ return r;
992+}
993+
994+uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *mode_info)
995+{
996+ if (ioctl(fd, DRM_IOCTL_MODE_ADDMODE, mode_info))
997+ return 0;
998+
999+ return mode_info->id;
1000+}
1001+
1002+int drmModeRmMode(int fd, uint32_t mode_id)
1003+{
1004+ return ioctl(fd, DRM_IOCTL_MODE_RMMODE, &mode_id);
1005+}
1006+
1007+int drmModeAttachMode(int fd, uint32_t output_id, uint32_t mode_id)
1008+{
1009+
1010+ struct drm_mode_mode_cmd res;
1011+
1012+ res.output_id = output_id;
1013+ res.mode_id = mode_id;
1014+
1015+ return ioctl(fd, DRM_IOCTL_MODE_ATTACHMODE, &res);
1016+}
1017+
1018+int drmModeDetachMode(int fd, uint32_t output_id, uint32_t mode_id)
1019+{
1020+ struct drm_mode_mode_cmd res;
1021+
1022+ res.output_id = output_id;
1023+ res.mode_id = mode_id;
1024+
1025+ return ioctl(fd, DRM_IOCTL_MODE_DETACHMODE, &res);
1026+}
1027+
1028+
1029+drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id)
1030+{
1031+ struct drm_mode_get_property prop;
1032+ drmModePropertyPtr r;
1033+
1034+ prop.prop_id = property_id;
1035+ prop.count_enums = 0;
1036+ prop.count_values = 0;
1037+ prop.flags = 0;
1038+ prop.enums = NULL;
1039+ prop.values = NULL;
1040+
1041+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop))
1042+ return 0;
1043+
1044+ if (prop.count_values)
1045+ prop.values = drmMalloc(prop.count_values * sizeof(uint32_t));
1046+
1047+ if (prop.count_enums)
1048+ prop.enums = drmMalloc(prop.count_enums * sizeof(struct drm_mode_property_enum));
1049+
1050+ if (ioctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop)) {
1051+ r = NULL;
1052+ goto err_allocs;
1053+ }
1054+
1055+ if (!(r = drmMalloc(sizeof(*r))))
1056+ return NULL;
1057+
1058+ r->prop_id = prop.prop_id;
1059+ r->count_values = prop.count_values;
1060+ r->count_enums = prop.count_enums;
1061+
1062+ r->values = drmAllocCpy(prop.values, prop.count_values, sizeof(uint32_t));
1063+ r->enums = drmAllocCpy(prop.enums, prop.count_enums, sizeof(struct drm_mode_property_enum));
1064+ strncpy(r->name, prop.name, DRM_PROP_NAME_LEN);
1065+ r->name[DRM_PROP_NAME_LEN-1] = 0;
1066+
1067+err_allocs:
1068+ drmFree(prop.values);
1069+ drmFree(prop.enums);
1070+
1071+ return r;
1072+}
1073+
1074+void drmModeFreeProperty(drmModePropertyPtr ptr)
1075+{
1076+ if (!ptr)
1077+ return;
1078+
1079+ drmFree(ptr->values);
1080+ drmFree(ptr->enums);
1081+ drmFree(ptr);
1082+}
1083Index: libdrm-2.3.1/libdrm/xf86drmMode.h
1084===================================================================
1085--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1086+++ libdrm-2.3.1/libdrm/xf86drmMode.h 2009-01-14 18:26:59.000000000 +0000
1087@@ -0,0 +1,226 @@
1088+/*
1089+ * \file xf86drmMode.h
1090+ * Header for DRM modesetting interface.
1091+ *
1092+ * \author Jakob Bornecrantz <wallbraker@gmail.com>
1093+ *
1094+ * \par Acknowledgements:
1095+ * Feb 2007, Dave Airlie <airlied@linux.ie>
1096+ */
1097+
1098+/*
1099+ * Copyright (c) <year> <copyright holders>
1100+ *
1101+ * Permission is hereby granted, free of charge, to any person obtaining a
1102+ * copy of this software and associated documentation files (the "Software"),
1103+ * to deal in the Software without restriction, including without limitation
1104+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1105+ * and/or sell copies of the Software, and to permit persons to whom the
1106+ * Software is furnished to do so, subject to the following conditions:
1107+ *
1108+ * The above copyright notice and this permission notice shall be included in
1109+ * all copies or substantial portions of the Software.
1110+ *
1111+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1112+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1113+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
1114+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1115+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1116+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
1117+ * IN THE SOFTWARE.
1118+ *
1119+ */
1120+
1121+#include <drm.h>
1122+#include "xf86mm.h"
1123+
1124+/*
1125+ * This is the interface for modesetting for drm.
1126+ *
1127+ * In order to use this interface you must include either <stdint.h> or another
1128+ * header defining uint32_t, int32_t and uint16_t.
1129+ *
1130+ * It aims to provide a randr1.2 compatible interface for modesettings in the
1131+ * kernel, the interface is also ment to be used by libraries like EGL.
1132+ *
1133+ * More information can be found in randrproto.txt which can be found here:
1134+ * http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git
1135+ *
1136+ * There are some major diffrences to be noted. Unlike the randr1.2 proto you
1137+ * need to create the memory object of the framebuffer yourself with the ttm
1138+ * buffer object interface. This object needs to be pinned.
1139+ */
1140+
1141+
1142+typedef struct _drmModeRes {
1143+
1144+ int count_fbs;
1145+ uint32_t *fbs;
1146+
1147+ int count_crtcs;
1148+ uint32_t *crtcs;
1149+
1150+ int count_outputs;
1151+ uint32_t *outputs;
1152+
1153+ int count_modes;
1154+ struct drm_mode_modeinfo *modes;
1155+
1156+} drmModeRes, *drmModeResPtr;
1157+
1158+typedef struct drm_mode_fb_cmd drmModeFB, *drmModeFBPtr;
1159+
1160+typedef struct _drmModeProperty {
1161+ unsigned int prop_id;
1162+ unsigned int flags;
1163+ unsigned char name[DRM_PROP_NAME_LEN];
1164+ int count_values;
1165+ uint32_t *values;
1166+ int count_enums;
1167+ struct drm_mode_property_enum *enums;
1168+
1169+} drmModePropertyRes, *drmModePropertyPtr;
1170+
1171+typedef struct _drmModeCrtc {
1172+ unsigned int crtc_id;
1173+ unsigned int buffer_id; /**< FB id to connect to 0 = disconnect*/
1174+
1175+ uint32_t x, y; /**< Position on the frameuffer */
1176+ uint32_t width, height;
1177+ uint32_t mode; /**< Current mode used */
1178+
1179+ int count_outputs;
1180+ uint32_t outputs; /**< Outputs that are connected */
1181+
1182+ int count_possibles;
1183+ uint32_t possibles; /**< Outputs that can be connected */
1184+
1185+ int gamma_size; /**< Number of gamma stops */
1186+
1187+} drmModeCrtc, *drmModeCrtcPtr;
1188+
1189+typedef enum {
1190+ DRM_MODE_CONNECTED = 1,
1191+ DRM_MODE_DISCONNECTED = 2,
1192+ DRM_MODE_UNKNOWNCONNECTION = 3
1193+} drmModeConnection;
1194+
1195+typedef enum {
1196+ DRM_MODE_SUBPIXEL_UNKNOWN = 1,
1197+ DRM_MODE_SUBPIXEL_HORIZONTAL_RGB = 2,
1198+ DRM_MODE_SUBPIXEL_HORIZONTAL_BGR = 3,
1199+ DRM_MODE_SUBPIXEL_VERTICAL_RGB = 4,
1200+ DRM_MODE_SUBPIXEL_VERTICAL_BGR = 5,
1201+ DRM_MODE_SUBPIXEL_NONE = 6
1202+} drmModeSubPixel;
1203+
1204+typedef struct _drmModeOutput {
1205+ unsigned int output_id;
1206+
1207+ unsigned int crtc; /**< Crtc currently connected to */
1208+ unsigned char name[DRM_OUTPUT_NAME_LEN];
1209+ drmModeConnection connection;
1210+ uint32_t mmWidth, mmHeight; /**< HxW in millimeters */
1211+ drmModeSubPixel subpixel;
1212+
1213+ int count_crtcs;
1214+ uint32_t crtcs; /**< Possible crtc to connect to */
1215+
1216+ int count_clones;
1217+ uint32_t clones; /**< Mask of clones */
1218+
1219+ int count_modes;
1220+ uint32_t *modes; /**< List of modes ids */
1221+
1222+ int count_props;
1223+ uint32_t *props; /**< List of property ids */
1224+ uint32_t *prop_values; /**< List of property values */
1225+
1226+} drmModeOutput, *drmModeOutputPtr;
1227+
1228+
1229+
1230+extern void drmModeFreeModeInfo( struct drm_mode_modeinfo *ptr );
1231+extern void drmModeFreeResources( drmModeResPtr ptr );
1232+extern void drmModeFreeFB( drmModeFBPtr ptr );
1233+extern void drmModeFreeCrtc( drmModeCrtcPtr ptr );
1234+extern void drmModeFreeOutput( drmModeOutputPtr ptr );
1235+
1236+/**
1237+ * Retrives all of the resources associated with a card.
1238+ */
1239+extern drmModeResPtr drmModeGetResources(int fd);
1240+
1241+
1242+/*
1243+ * FrameBuffer manipulation.
1244+ */
1245+
1246+/**
1247+ * Retrive information about framebuffer bufferId
1248+ */
1249+extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId);
1250+
1251+/**
1252+ * Creates a new framebuffer with an buffer object as its scanout buffer.
1253+ */
1254+extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
1255+ uint8_t bpp, uint32_t pitch, drmBO *bo,
1256+ uint32_t *buf_id);
1257+/**
1258+ * Destroies the given framebuffer.
1259+ */
1260+extern int drmModeRmFB(int fd, uint32_t bufferId);
1261+
1262+
1263+/*
1264+ * Crtc functions
1265+ */
1266+
1267+/**
1268+ * Retrive information about the ctrt crtcId
1269+ */
1270+extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId);
1271+
1272+/**
1273+ * Set the mode on a crtc crtcId with the given mode modeId.
1274+ */
1275+extern int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
1276+ uint32_t x, uint32_t y, uint32_t modeId,
1277+ uint32_t *outputs, int count);
1278+
1279+
1280+/*
1281+ * Output manipulation
1282+ */
1283+
1284+/**
1285+ * Retrive information about the output outputId.
1286+ */
1287+extern drmModeOutputPtr drmModeGetOutput(int fd,
1288+ uint32_t outputId);
1289+
1290+/**
1291+ * Adds a new mode from the given mode info.
1292+ * Name must be unique.
1293+ */
1294+extern uint32_t drmModeAddMode(int fd, struct drm_mode_modeinfo *modeInfo);
1295+
1296+/**
1297+ * Removes a mode created with AddMode, must be unused.
1298+ */
1299+extern int drmModeRmMode(int fd, uint32_t modeId);
1300+
1301+/**
1302+ * Attaches the given mode to an output.
1303+ */
1304+extern int drmModeAttachMode(int fd, uint32_t outputId, uint32_t modeId);
1305+
1306+/**
1307+ * Detaches a mode from the output
1308+ * must be unused, by the given mode.
1309+ */
1310+extern int drmModeDetachMode(int fd, uint32_t outputId, uint32_t modeId);
1311+
1312+extern drmModePropertyPtr drmModeGetProperty(int fd, uint32_t propertyId);
1313+extern void drmModeFreeProperty(drmModePropertyPtr ptr);
1314Index: libdrm-2.3.1/libdrm/xf86mm.h
1315===================================================================
1316--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1317+++ libdrm-2.3.1/libdrm/xf86mm.h 2009-01-14 18:26:59.000000000 +0000
1318@@ -0,0 +1,185 @@
1319+/**************************************************************************
1320+ *
1321+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA.
1322+ * All Rights Reserved.
1323+ *
1324+ * Permission is hereby granted, free of charge, to any person obtaining a
1325+ * copy of this software and associated documentation files (the
1326+ * "Software"), to deal in the Software without restriction, including
1327+ * without limitation the rights to use, copy, modify, merge, publish,
1328+ * distribute, sub license, and/or sell copies of the Software, and to
1329+ * permit persons to whom the Software is furnished to do so, subject to
1330+ * the following conditions:
1331+ *
1332+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1333+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1334+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
1335+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
1336+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
1337+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
1338+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
1339+ *
1340+ * The above copyright notice and this permission notice (including the
1341+ * next paragraph) shall be included in all copies or substantial portions
1342+ * of the Software.
1343+ *
1344+ *
1345+ **************************************************************************/
1346+
1347+#ifndef _XF86MM_H_
1348+#define _XF86MM_H_
1349+#include <stddef.h>
1350+#include <stdint.h>
1351+#include "drm.h"
1352+
1353+/*
1354+ * Note on multithreaded applications using this interface.
1355+ * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to
1356+ * be protected using an external mutex.
1357+ *
1358+ * Note: Don't protect the following functions, as it may lead to deadlocks:
1359+ * drmBOUnmap().
1360+ * The kernel is synchronizing and refcounting buffer maps.
1361+ * User space only needs to refcount object usage within the same application.
1362+ */
1363+
1364+
1365+/*
1366+ * List macros heavily inspired by the Linux kernel
1367+ * list handling. No list looping yet.
1368+ */
1369+
1370+typedef struct _drmMMListHead
1371+{
1372+ struct _drmMMListHead *prev;
1373+ struct _drmMMListHead *next;
1374+} drmMMListHead;
1375+
1376+#define DRMINITLISTHEAD(__item) \
1377+ do{ \
1378+ (__item)->prev = (__item); \
1379+ (__item)->next = (__item); \
1380+ } while (0)
1381+
1382+#define DRMLISTADD(__item, __list) \
1383+ do { \
1384+ (__item)->prev = (__list); \
1385+ (__item)->next = (__list)->next; \
1386+ (__list)->next->prev = (__item); \
1387+ (__list)->next = (__item); \
1388+ } while (0)
1389+
1390+#define DRMLISTADDTAIL(__item, __list) \
1391+ do { \
1392+ (__item)->next = (__list); \
1393+ (__item)->prev = (__list)->prev; \
1394+ (__list)->prev->next = (__item); \
1395+ (__list)->prev = (__item); \
1396+ } while(0)
1397+
1398+#define DRMLISTDEL(__item) \
1399+ do { \
1400+ (__item)->prev->next = (__item)->next; \
1401+ (__item)->next->prev = (__item)->prev; \
1402+ } while(0)
1403+
1404+#define DRMLISTDELINIT(__item) \
1405+ do { \
1406+ (__item)->prev->next = (__item)->next; \
1407+ (__item)->next->prev = (__item)->prev; \
1408+ (__item)->next = (__item); \
1409+ (__item)->prev = (__item); \
1410+ } while(0)
1411+
1412+#define DRMLISTENTRY(__type, __item, __field) \
1413+ ((__type *)(((char *) (__item)) - offsetof(__type, __field)))
1414+
1415+typedef struct _drmFence
1416+{
1417+ unsigned handle;
1418+ int fence_class;
1419+ unsigned type;
1420+ unsigned flags;
1421+ unsigned signaled;
1422+ uint32_t sequence;
1423+ unsigned pad[4]; /* for future expansion */
1424+} drmFence;
1425+
1426+typedef struct _drmBO
1427+{
1428+ unsigned handle;
1429+ uint64_t mapHandle;
1430+ uint64_t flags;
1431+ uint64_t mask;
1432+ unsigned mapFlags;
1433+ unsigned long size;
1434+ unsigned long offset;
1435+ unsigned long start;
1436+ unsigned replyFlags;
1437+ unsigned fenceFlags;
1438+ unsigned pageAlignment;
1439+ unsigned tileInfo;
1440+ unsigned hwTileStride;
1441+ unsigned desiredTileStride;
1442+ void *virtual;
1443+ void *mapVirtual;
1444+ int mapCount;
1445+ unsigned pad[8]; /* for future expansion */
1446+} drmBO;
1447+
1448+/*
1449+ * Fence functions.
1450+ */
1451+
1452+extern int drmFenceCreate(int fd, unsigned flags, int fence_class,
1453+ unsigned type, drmFence *fence);
1454+extern int drmFenceReference(int fd, unsigned handle, drmFence *fence);
1455+extern int drmFenceUnreference(int fd, const drmFence *fence);
1456+extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type);
1457+extern int drmFenceSignaled(int fd, drmFence *fence,
1458+ unsigned fenceType, int *signaled);
1459+extern int drmFenceWait(int fd, unsigned flags, drmFence *fence,
1460+ unsigned flush_type);
1461+extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence,
1462+ unsigned emit_type);
1463+extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence);
1464+
1465+
1466+/*
1467+ * Buffer object functions.
1468+ */
1469+
1470+extern int drmBOCreate(int fd, unsigned long size,
1471+ unsigned pageAlignment, void *user_buffer,
1472+ uint64_t mask, unsigned hint, drmBO *buf);
1473+extern int drmBOReference(int fd, unsigned handle, drmBO *buf);
1474+extern int drmBOUnreference(int fd, drmBO *buf);
1475+extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint,
1476+ void **address);
1477+extern int drmBOUnmap(int fd, drmBO *buf);
1478+extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle);
1479+extern int drmBOInfo(int fd, drmBO *buf);
1480+extern int drmBOBusy(int fd, drmBO *buf, int *busy);
1481+
1482+extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint);
1483+
1484+/*
1485+ * Initialization functions.
1486+ */
1487+
1488+extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize,
1489+ unsigned memType);
1490+extern int drmMMTakedown(int fd, unsigned memType);
1491+extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict);
1492+extern int drmMMUnlock(int fd, unsigned memType, int unlockBM);
1493+extern int drmBOSetStatus(int fd, drmBO *buf,
1494+ uint64_t flags, uint64_t mask,
1495+ unsigned int hint,
1496+ unsigned int desired_tile_stride,
1497+ unsigned int tile_info);
1498+extern int drmBOVersion(int fd, unsigned int *major,
1499+ unsigned int *minor,
1500+ unsigned int *patchlevel);
1501+
1502+
1503+#endif
1504Index: libdrm-2.3.1/Makefile.am
1505===================================================================
1506--- libdrm-2.3.1.orig/Makefile.am 2008-07-01 08:50:43.000000000 +0100
1507+++ libdrm-2.3.1/Makefile.am 2009-01-14 18:26:59.000000000 +0000
1508@@ -22,7 +22,7 @@
1509 # here too, but let's just do libdrm for now
1510
1511 AUTOMAKE_OPTIONS = foreign
1512-SUBDIRS = libdrm shared-core tests
1513+SUBDIRS = libdrm shared-core
1514
1515 pkgconfigdir = @pkgconfigdir@
1516 pkgconfig_DATA = libdrm.pc
1517Index: libdrm-2.3.1/shared-core/drm.h
1518===================================================================
1519--- libdrm-2.3.1.orig/shared-core/drm.h 2008-07-01 08:55:17.000000000 +0100
1520+++ libdrm-2.3.1/shared-core/drm.h 2009-01-14 18:26:59.000000000 +0000
1521@@ -236,6 +236,7 @@
1522 _DRM_AGP = 3, /**< AGP/GART */
1523 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
1524 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
1525+ _DRM_TTM = 6
1526 };
1527
1528 /**
1529@@ -640,6 +641,398 @@
1530 int drm_dd_minor;
1531 };
1532
1533+
1534+#define DRM_FENCE_FLAG_EMIT 0x00000001
1535+#define DRM_FENCE_FLAG_SHAREABLE 0x00000002
1536+#define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
1537+#define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
1538+#define DRM_FENCE_FLAG_NO_USER 0x00000010
1539+
1540+/* Reserved for driver use */
1541+#define DRM_FENCE_MASK_DRIVER 0xFF000000
1542+
1543+#define DRM_FENCE_TYPE_EXE 0x00000001
1544+
1545+struct drm_fence_arg {
1546+ unsigned int handle;
1547+ unsigned int fence_class;
1548+ unsigned int type;
1549+ unsigned int flags;
1550+ unsigned int signaled;
1551+ unsigned int error;
1552+ unsigned int sequence;
1553+ unsigned int pad64;
1554+ uint64_t expand_pad[2]; /*Future expansion */
1555+};
1556+
1557+/* Buffer permissions, referring to how the GPU uses the buffers.
1558+ * these translate to fence types used for the buffers.
1559+ * Typically a texture buffer is read, A destination buffer is write and
1560+ * a command (batch-) buffer is exe. Can be or-ed together.
1561+ */
1562+
1563+#define DRM_BO_FLAG_READ (1ULL << 0)
1564+#define DRM_BO_FLAG_WRITE (1ULL << 1)
1565+#define DRM_BO_FLAG_EXE (1ULL << 2)
1566+
1567+/*
1568+ * Status flags. Can be read to determine the actual state of a buffer.
1569+ * Can also be set in the buffer mask before validation.
1570+ */
1571+
1572+/*
1573+ * Mask: Never evict this buffer. Not even with force. This type of buffer is only
1574+ * available to root and must be manually removed before buffer manager shutdown
1575+ * or lock.
1576+ * Flags: Acknowledge
1577+ */
1578+#define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
1579+
1580+/*
1581+ * Mask: Require that the buffer is placed in mappable memory when validated.
1582+ * If not set the buffer may or may not be in mappable memory when validated.
1583+ * Flags: If set, the buffer is in mappable memory.
1584+ */
1585+#define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
1586+
1587+/* Mask: The buffer should be shareable with other processes.
1588+ * Flags: The buffer is shareable with other processes.
1589+ */
1590+#define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
1591+
1592+/* Mask: If set, place the buffer in cache-coherent memory if available.
1593+ * If clear, never place the buffer in cache coherent memory if validated.
1594+ * Flags: The buffer is currently in cache-coherent memory.
1595+ */
1596+#define DRM_BO_FLAG_CACHED (1ULL << 7)
1597+
1598+/* Mask: Make sure that every time this buffer is validated,
1599+ * it ends up on the same location provided that the memory mask is the same.
1600+ * The buffer will also not be evicted when claiming space for
1601+ * other buffers. Basically a pinned buffer but it may be thrown out as
1602+ * part of buffer manager shutdown or locking.
1603+ * Flags: Acknowledge.
1604+ */
1605+#define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
1606+
1607+/* Mask: Make sure the buffer is in cached memory when mapped
1608+ * Flags: Acknowledge.
1609+ * Buffers allocated with this flag should not be used for suballocators
1610+ * This type may have issues on CPUs with over-aggressive caching
1611+ * http://marc.info/?l=linux-kernel&m=102376926732464&w=2
1612+ */
1613+#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
1614+
1615+
1616+/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
1617+ * Flags: Acknowledge.
1618+ */
1619+#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
1620+
1621+/*
1622+ * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
1623+ * Flags: Acknowledge.
1624+ */
1625+#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
1626+#define DRM_BO_FLAG_TILE (1ULL << 15)
1627+
1628+/*
1629+ * Memory type flags that can be or'ed together in the mask, but only
1630+ * one appears in flags.
1631+ */
1632+
1633+/* System memory */
1634+#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
1635+/* Translation table memory */
1636+#define DRM_BO_FLAG_MEM_TT (1ULL << 25)
1637+/* Vram memory */
1638+#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
1639+/* Up to the driver to define. */
1640+#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
1641+#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
1642+#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
1643+#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
1644+#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
1645+/* We can add more of these now with a 64-bit flag type */
1646+
1647+/* Memory flag mask */
1648+#define DRM_BO_MASK_MEM 0x00000000FF000000ULL
1649+#define DRM_BO_MASK_MEMTYPE 0x00000000FF0800A0ULL
1650+
1651+/* Driver-private flags */
1652+#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
1653+
1654+/* Don't block on validate and map */
1655+#define DRM_BO_HINT_DONT_BLOCK 0x00000002
1656+/* Don't place this buffer on the unfenced list.*/
1657+#define DRM_BO_HINT_DONT_FENCE 0x00000004
1658+#define DRM_BO_HINT_WAIT_LAZY 0x00000008
1659+
1660+#define DRM_BO_INIT_MAGIC 0xfe769812
1661+#define DRM_BO_INIT_MAJOR 1
1662+#define DRM_BO_INIT_MINOR 0
1663+#define DRM_BO_INIT_PATCH 0
1664+
1665+
1666+struct drm_bo_info_req {
1667+ uint64_t mask;
1668+ uint64_t flags;
1669+ unsigned int handle;
1670+ unsigned int hint;
1671+ unsigned int fence_class;
1672+ unsigned int desired_tile_stride;
1673+ unsigned int tile_info;
1674+ unsigned int pad64;
1675+};
1676+
1677+struct drm_bo_create_req {
1678+ uint64_t mask;
1679+ uint64_t size;
1680+ uint64_t buffer_start;
1681+ unsigned int hint;
1682+ unsigned int page_alignment;
1683+};
1684+
1685+
1686+/*
1687+ * Reply flags
1688+ */
1689+
1690+#define DRM_BO_REP_BUSY 0x00000001
1691+
1692+struct drm_bo_info_rep {
1693+ uint64_t flags;
1694+ uint64_t mask;
1695+ uint64_t size;
1696+ uint64_t offset;
1697+ uint64_t arg_handle;
1698+ uint64_t buffer_start;
1699+ unsigned int handle;
1700+ unsigned int fence_flags;
1701+ unsigned int rep_flags;
1702+ unsigned int page_alignment;
1703+ unsigned int desired_tile_stride;
1704+ unsigned int hw_tile_stride;
1705+ unsigned int tile_info;
1706+ unsigned int pad64;
1707+ uint64_t expand_pad[4]; /*Future expansion */
1708+};
1709+
1710+struct drm_bo_arg_rep {
1711+ struct drm_bo_info_rep bo_info;
1712+ int ret;
1713+ unsigned int pad64;
1714+};
1715+
1716+struct drm_bo_create_arg {
1717+ union {
1718+ struct drm_bo_create_req req;
1719+ struct drm_bo_info_rep rep;
1720+ } d;
1721+};
1722+
1723+struct drm_bo_handle_arg {
1724+ unsigned int handle;
1725+};
1726+
1727+struct drm_bo_reference_info_arg {
1728+ union {
1729+ struct drm_bo_handle_arg req;
1730+ struct drm_bo_info_rep rep;
1731+ } d;
1732+};
1733+
1734+struct drm_bo_map_wait_idle_arg {
1735+ union {
1736+ struct drm_bo_info_req req;
1737+ struct drm_bo_info_rep rep;
1738+ } d;
1739+};
1740+
1741+struct drm_bo_op_req {
1742+ enum {
1743+ drm_bo_validate,
1744+ drm_bo_fence,
1745+ drm_bo_ref_fence,
1746+ } op;
1747+ unsigned int arg_handle;
1748+ struct drm_bo_info_req bo_req;
1749+};
1750+
1751+
1752+struct drm_bo_op_arg {
1753+ uint64_t next;
1754+ union {
1755+ struct drm_bo_op_req req;
1756+ struct drm_bo_arg_rep rep;
1757+ } d;
1758+ int handled;
1759+ unsigned int pad64;
1760+};
1761+
1762+
1763+#define DRM_BO_MEM_LOCAL 0
1764+#define DRM_BO_MEM_TT 1
1765+#define DRM_BO_MEM_VRAM 2
1766+#define DRM_BO_MEM_PRIV0 3
1767+#define DRM_BO_MEM_PRIV1 4
1768+#define DRM_BO_MEM_PRIV2 5
1769+#define DRM_BO_MEM_PRIV3 6
1770+#define DRM_BO_MEM_PRIV4 7
1771+
1772+#define DRM_BO_MEM_TYPES 8 /* For now. */
1773+
1774+#define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
1775+#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
1776+
1777+struct drm_bo_version_arg {
1778+ uint32_t major;
1779+ uint32_t minor;
1780+ uint32_t patchlevel;
1781+};
1782+
1783+struct drm_mm_type_arg {
1784+ unsigned int mem_type;
1785+ unsigned int lock_flags;
1786+};
1787+
1788+struct drm_mm_init_arg {
1789+ unsigned int magic;
1790+ unsigned int major;
1791+ unsigned int minor;
1792+ unsigned int mem_type;
1793+ uint64_t p_offset;
1794+ uint64_t p_size;
1795+};
1796+
1797+/*
1798+ * Drm mode setting
1799+ */
1800+#define DRM_DISPLAY_INFO_LEN 32
1801+#define DRM_OUTPUT_NAME_LEN 32
1802+#define DRM_DISPLAY_MODE_LEN 32
1803+#define DRM_PROP_NAME_LEN 32
1804+
1805+#define DRM_MODE_TYPE_BUILTIN (1<<0)
1806+#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
1807+#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
1808+#define DRM_MODE_TYPE_PREFERRED (1<<3)
1809+#define DRM_MODE_TYPE_DEFAULT (1<<4)
1810+#define DRM_MODE_TYPE_USERDEF (1<<5)
1811+#define DRM_MODE_TYPE_DRIVER (1<<6)
1812+
1813+struct drm_mode_modeinfo {
1814+
1815+ unsigned int id;
1816+
1817+ unsigned int clock;
1818+ unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
1819+ unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
1820+
1821+ unsigned int vrefresh; /* vertical refresh * 1000 */
1822+
1823+ unsigned int flags;
1824+ unsigned int type;
1825+ char name[DRM_DISPLAY_MODE_LEN];
1826+};
1827+
1828+struct drm_mode_card_res {
1829+
1830+ int count_fbs;
1831+ unsigned int __user *fb_id;
1832+
1833+ int count_crtcs;
1834+ unsigned int __user *crtc_id;
1835+
1836+ int count_outputs;
1837+ unsigned int __user *output_id;
1838+
1839+ int count_modes;
1840+ struct drm_mode_modeinfo __user *modes;
1841+
1842+};
1843+
1844+struct drm_mode_crtc {
1845+ unsigned int crtc_id; /**< Id */
1846+ unsigned int fb_id; /**< Id of framebuffer */
1847+
1848+ int x, y; /**< Position on the frameuffer */
1849+
1850+ unsigned int mode; /**< Current mode used */
1851+
1852+ int count_outputs;
1853+ unsigned int outputs; /**< Outputs that are connected */
1854+
1855+ int count_possibles;
1856+ unsigned int possibles; /**< Outputs that can be connected */
1857+
1858+ unsigned int __user *set_outputs; /**< Outputs to be connected */
1859+
1860+ int gamma_size;
1861+
1862+};
1863+
1864+struct drm_mode_get_output {
1865+
1866+ unsigned int output; /**< Id */
1867+ unsigned int crtc; /**< Id of crtc */
1868+ unsigned char name[DRM_OUTPUT_NAME_LEN];
1869+
1870+ unsigned int connection;
1871+ unsigned int mm_width, mm_height; /**< HxW in millimeters */
1872+ unsigned int subpixel;
1873+
1874+ int count_crtcs;
1875+ unsigned int crtcs; /**< possible crtc to connect to */
1876+
1877+ int count_clones;
1878+ unsigned int clones; /**< list of clones */
1879+
1880+ int count_modes;
1881+ unsigned int __user *modes; /**< list of modes it supports */
1882+
1883+ int count_props;
1884+ unsigned int __user *props;
1885+ unsigned int __user *prop_values;
1886+};
1887+
1888+#define DRM_MODE_PROP_PENDING (1<<0)
1889+#define DRM_MODE_PROP_RANGE (1<<1)
1890+#define DRM_MODE_PROP_IMMUTABLE (1<<2)
1891+#define DRM_MODE_PROP_ENUM (1<<3) // enumerated type with text strings
1892+
1893+struct drm_mode_property_enum {
1894+ uint32_t value;
1895+ unsigned char name[DRM_PROP_NAME_LEN];
1896+};
1897+
1898+struct drm_mode_get_property {
1899+
1900+ unsigned int prop_id;
1901+ unsigned int flags;
1902+ unsigned char name[DRM_PROP_NAME_LEN];
1903+
1904+ int count_values;
1905+ uint32_t __user *values;
1906+
1907+ int count_enums;
1908+ struct drm_mode_property_enum *enums;
1909+};
1910+
1911+struct drm_mode_fb_cmd {
1912+ unsigned int buffer_id;
1913+ unsigned int width, height;
1914+ unsigned int pitch;
1915+ unsigned int bpp;
1916+ unsigned int handle;
1917+ unsigned int depth;
1918+};
1919+
1920+struct drm_mode_mode_cmd {
1921+ unsigned int output_id;
1922+ unsigned int mode_id;
1923+};
1924+
1925 /**
1926 * \name Ioctls Definitions
1927 */
1928@@ -708,6 +1101,45 @@
1929
1930 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1931
1932+#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
1933+#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
1934+#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
1935+#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
1936+
1937+#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
1938+#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
1939+#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
1940+#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
1941+#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
1942+#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
1943+#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
1944+#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
1945+
1946+#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
1947+#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
1948+#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
1949+#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
1950+#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
1951+#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
1952+#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
1953+#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1954+#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
1955+
1956+
1957+#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1958+#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
1959+#define DRM_IOCTL_MODE_GETOUTPUT DRM_IOWR(0xA2, struct drm_mode_get_output)
1960+#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
1961+#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
1962+#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
1963+#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
1964+
1965+#define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
1966+#define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
1967+#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
1968+#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
1969+
1970+#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property)
1971 /*@}*/
1972
1973 /**
1974@@ -763,6 +1195,10 @@
1975 typedef struct drm_scatter_gather drm_scatter_gather_t;
1976 typedef struct drm_set_version drm_set_version_t;
1977
1978+typedef struct drm_fence_arg drm_fence_arg_t;
1979+typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1980+typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1981+typedef enum drm_bo_type drm_bo_type_t;
1982 #endif
1983
1984 #endif
1985Index: libdrm-2.3.1/shared-core/i915_drm.h
1986===================================================================
1987--- libdrm-2.3.1.orig/shared-core/i915_drm.h 2008-07-01 08:51:40.000000000 +0100
1988+++ libdrm-2.3.1/shared-core/i915_drm.h 2009-01-14 18:26:59.000000000 +0000
1989@@ -138,6 +138,14 @@
1990
1991 /* Driver specific fence types and classes.
1992 */
1993+
1994+/* The only fence class we support */
1995+#define DRM_I915_FENCE_CLASS_ACCEL 0
1996+/* Fence type that guarantees read-write flush */
1997+#define DRM_I915_FENCE_TYPE_RW 2
1998+/* MI_FLUSH programmed just before the fence */
1999+#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
2000+
2001 /* Flags for perf_boxes
2002 */
2003 #define I915_BOX_RING_EMPTY 0x1
2004@@ -167,6 +175,7 @@
2005 #define DRM_I915_VBLANK_SWAP 0x0f
2006 #define DRM_I915_MMIO 0x10
2007 #define DRM_I915_HWS_ADDR 0x11
2008+#define DRM_I915_EXECBUFFER 0x12
2009
2010 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
2011 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
2012@@ -184,7 +193,7 @@
2013 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
2014 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
2015 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
2016-#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
2017+#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
2018
2019 /* Asynchronous page flipping:
2020 */
2021@@ -333,4 +342,40 @@
2022 uint64_t addr;
2023 } drm_i915_hws_addr_t;
2024
2025+/*
2026+ * Relocation header is 4 uint32_ts
2027+ * 0 - (16-bit relocation type << 16)| 16 bit reloc count
2028+ * 1 - buffer handle for another list of relocs
2029+ * 2-3 - spare.
2030+ */
2031+#define I915_RELOC_HEADER 4
2032+
2033+/*
2034+ * type 0 relocation has 4-uint32_t stride
2035+ * 0 - offset into buffer
2036+ * 1 - delta to add in
2037+ * 2 - index into buffer list
2038+ * 3 - reserved (for optimisations later).
2039+ */
2040+#define I915_RELOC_TYPE_0 0
2041+#define I915_RELOC0_STRIDE 4
2042+
2043+struct drm_i915_op_arg {
2044+ uint64_t next;
2045+ uint32_t reloc_handle;
2046+ int handled;
2047+ union {
2048+ struct drm_bo_op_req req;
2049+ struct drm_bo_arg_rep rep;
2050+ } d;
2051+
2052+};
2053+
2054+struct drm_i915_execbuffer {
2055+ uint64_t ops_list;
2056+ uint32_t num_buffers;
2057+ struct drm_i915_batchbuffer batch;
2058+ struct drm_fence_arg fence_arg;
2059+};
2060+
2061 #endif /* _I915_DRM_H_ */
2062Index: libdrm-2.3.1/shared-core/Makefile.am
2063===================================================================
2064--- libdrm-2.3.1.orig/shared-core/Makefile.am 2008-07-01 08:51:40.000000000 +0100
2065+++ libdrm-2.3.1/shared-core/Makefile.am 2009-01-14 18:26:59.000000000 +0000
2066@@ -29,10 +29,14 @@
2067 i915_drm.h \
2068 mach64_drm.h \
2069 mga_drm.h \
2070+ nouveau_drm.h \
2071+ psb_drm.h \
2072+ psb_reg.h \
2073 r128_drm.h \
2074 radeon_drm.h \
2075 savage_drm.h \
2076 sis_drm.h \
2077 via_drm.h \
2078+ psb_reg.h \
2079 r300_reg.h \
2080 via_3d_reg.h
2081Index: libdrm-2.3.1/shared-core/nouveau_drm.h
2082===================================================================
2083--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2084+++ libdrm-2.3.1/shared-core/nouveau_drm.h 2009-01-14 18:26:59.000000000 +0000
2085@@ -0,0 +1,164 @@
2086+/*
2087+ * Copyright 2005 Stephane Marchesin.
2088+ * All Rights Reserved.
2089+ *
2090+ * Permission is hereby granted, free of charge, to any person obtaining a
2091+ * copy of this software and associated documentation files (the "Software"),
2092+ * to deal in the Software without restriction, including without limitation
2093+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
2094+ * and/or sell copies of the Software, and to permit persons to whom the
2095+ * Software is furnished to do so, subject to the following conditions:
2096+ *
2097+ * The above copyright notice and this permission notice (including the next
2098+ * paragraph) shall be included in all copies or substantial portions of the
2099+ * Software.
2100+ *
2101+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2102+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2103+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
2104+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2105+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2106+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2107+ * OTHER DEALINGS IN THE SOFTWARE.
2108+ */
2109+
2110+#ifndef __NOUVEAU_DRM_H__
2111+#define __NOUVEAU_DRM_H__
2112+
2113+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 10
2114+
2115+struct drm_nouveau_channel_alloc {
2116+ uint32_t fb_ctxdma_handle;
2117+ uint32_t tt_ctxdma_handle;
2118+
2119+ int channel;
2120+ uint32_t put_base;
2121+ /* FIFO control regs */
2122+ drm_handle_t ctrl;
2123+ int ctrl_size;
2124+ /* DMA command buffer */
2125+ drm_handle_t cmdbuf;
2126+ int cmdbuf_size;
2127+ /* Notifier memory */
2128+ drm_handle_t notifier;
2129+ int notifier_size;
2130+};
2131+
2132+struct drm_nouveau_channel_free {
2133+ int channel;
2134+};
2135+
2136+struct drm_nouveau_grobj_alloc {
2137+ int channel;
2138+ uint32_t handle;
2139+ int class;
2140+};
2141+
2142+#define NOUVEAU_MEM_ACCESS_RO 1
2143+#define NOUVEAU_MEM_ACCESS_WO 2
2144+#define NOUVEAU_MEM_ACCESS_RW 3
2145+struct drm_nouveau_notifierobj_alloc {
2146+ int channel;
2147+ uint32_t handle;
2148+ int count;
2149+
2150+ uint32_t offset;
2151+};
2152+
2153+struct drm_nouveau_gpuobj_free {
2154+ int channel;
2155+ uint32_t handle;
2156+};
2157+
2158+#define NOUVEAU_MEM_FB 0x00000001
2159+#define NOUVEAU_MEM_AGP 0x00000002
2160+#define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004
2161+#define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008
2162+#define NOUVEAU_MEM_PCI 0x00000010
2163+#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020
2164+#define NOUVEAU_MEM_PINNED 0x00000040
2165+#define NOUVEAU_MEM_USER_BACKED 0x00000080
2166+#define NOUVEAU_MEM_MAPPED 0x00000100
2167+#define NOUVEAU_MEM_INSTANCE 0x00000200 /* internal */
2168+#define NOUVEAU_MEM_NOTIFIER 0x00000400 /* internal */
2169+
2170+struct drm_nouveau_mem_alloc {
2171+ int flags;
2172+ int alignment;
2173+ uint64_t size; // in bytes
2174+ uint64_t offset;
2175+ drm_handle_t map_handle;
2176+};
2177+
2178+struct drm_nouveau_mem_free {
2179+ uint64_t offset;
2180+ int flags;
2181+};
2182+
2183+/* FIXME : maybe unify {GET,SET}PARAMs */
2184+#define NOUVEAU_GETPARAM_PCI_VENDOR 3
2185+#define NOUVEAU_GETPARAM_PCI_DEVICE 4
2186+#define NOUVEAU_GETPARAM_BUS_TYPE 5
2187+#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
2188+#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
2189+#define NOUVEAU_GETPARAM_FB_SIZE 8
2190+#define NOUVEAU_GETPARAM_AGP_SIZE 9
2191+#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
2192+#define NOUVEAU_GETPARAM_CHIPSET_ID 11
2193+struct drm_nouveau_getparam {
2194+ uint64_t param;
2195+ uint64_t value;
2196+};
2197+
2198+#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
2199+#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2
2200+struct drm_nouveau_setparam {
2201+ uint64_t param;
2202+ uint64_t value;
2203+};
2204+
2205+enum nouveau_card_type {
2206+ NV_UNKNOWN =0,
2207+ NV_04 =4,
2208+ NV_05 =5,
2209+ NV_10 =10,
2210+ NV_11 =11,
2211+ NV_15 =11,
2212+ NV_17 =17,
2213+ NV_20 =20,
2214+ NV_25 =20,
2215+ NV_30 =30,
2216+ NV_34 =30,
2217+ NV_40 =40,
2218+ NV_44 =44,
2219+ NV_50 =50,
2220+ NV_LAST =0xffff,
2221+};
2222+
2223+enum nouveau_bus_type {
2224+ NV_AGP =0,
2225+ NV_PCI =1,
2226+ NV_PCIE =2,
2227+};
2228+
2229+#define NOUVEAU_MAX_SAREA_CLIPRECTS 16
2230+
2231+struct drm_nouveau_sarea {
2232+ /* the cliprects */
2233+ struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
2234+ unsigned int nbox;
2235+};
2236+
2237+#define DRM_NOUVEAU_CARD_INIT 0x00
2238+#define DRM_NOUVEAU_GETPARAM 0x01
2239+#define DRM_NOUVEAU_SETPARAM 0x02
2240+#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
2241+#define DRM_NOUVEAU_CHANNEL_FREE 0x04
2242+#define DRM_NOUVEAU_GROBJ_ALLOC 0x05
2243+#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
2244+#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
2245+#define DRM_NOUVEAU_MEM_ALLOC 0x08
2246+#define DRM_NOUVEAU_MEM_FREE 0x09
2247+
2248+#endif /* __NOUVEAU_DRM_H__ */
2249+
2250Index: libdrm-2.3.1/shared-core/psb_drm.h
2251===================================================================
2252--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2253+++ libdrm-2.3.1/shared-core/psb_drm.h 2009-01-14 18:26:59.000000000 +0000
2254@@ -0,0 +1,359 @@
2255+/**************************************************************************
2256+ * Copyright (c) 2007, Intel Corporation.
2257+ * All Rights Reserved.
2258+ *
2259+ * This program is free software; you can redistribute it and/or modify it
2260+ * under the terms and conditions of the GNU General Public License,
2261+ * version 2, as published by the Free Software Foundation.
2262+ *
2263+ * This program is distributed in the hope it will be useful, but WITHOUT
2264+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2265+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2266+ * more details.
2267+ *
2268+ * You should have received a copy of the GNU General Public License along with
2269+ * this program; if not, write to the Free Software Foundation, Inc.,
2270+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2271+ *
2272+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
2273+ * develop this driver.
2274+ *
2275+ **************************************************************************/
2276+/*
2277+ */
2278+
2279+#ifndef _PSB_DRM_H_
2280+#define _PSB_DRM_H_
2281+
2282+#if defined(__linux__) && !defined(__KERNEL__)
2283+#include<stdint.h>
2284+#endif
2285+
2286+/*
2287+ * Intel Poulsbo driver package version.
2288+ *
2289+ */
2290+/* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
2291+#define PSB_PACKAGE_VERSION "2.0.0.32L.0007"
2292+
2293+#define DRM_PSB_SAREA_MAJOR 0
2294+#define DRM_PSB_SAREA_MINOR 1
2295+#define PSB_FIXED_SHIFT 16
2296+
2297+/*
2298+ * Public memory types.
2299+ */
2300+
2301+#define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
2302+#define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
2303+#define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
2304+#define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
2305+#define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
2306+#define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
2307+#define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
2308+#define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
2309+#define PSB_MEM_RASTGEOM_START 0x30000000
2310+
2311+typedef int32_t psb_fixed;
2312+typedef uint32_t psb_ufixed;
2313+
2314+static inline psb_fixed psb_int_to_fixed(int a)
2315+{
2316+ return a * (1 << PSB_FIXED_SHIFT);
2317+}
2318+
2319+static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
2320+{
2321+ return a << PSB_FIXED_SHIFT;
2322+}
2323+
2324+/*Status of the command sent to the gfx device.*/
2325+typedef enum {
2326+ DRM_CMD_SUCCESS,
2327+ DRM_CMD_FAILED,
2328+ DRM_CMD_HANG
2329+} drm_cmd_status_t;
2330+
2331+struct drm_psb_scanout {
2332+ uint32_t buffer_id; /* DRM buffer object ID */
2333+ uint32_t rotation; /* Rotation as in RR_rotation definitions */
2334+ uint32_t stride; /* Buffer stride in bytes */
2335+ uint32_t depth; /* Buffer depth in bits (NOT) bpp */
2336+ uint32_t width; /* Buffer width in pixels */
2337+ uint32_t height; /* Buffer height in lines */
2338+ psb_fixed transform[3][3]; /* Buffer composite transform */
2339+ /* (scaling, rot, reflect) */
2340+};
2341+
2342+#define DRM_PSB_SAREA_OWNERS 16
2343+#define DRM_PSB_SAREA_OWNER_2D 0
2344+#define DRM_PSB_SAREA_OWNER_3D 1
2345+
2346+#define DRM_PSB_SAREA_SCANOUTS 3
2347+
2348+struct drm_psb_sarea {
2349+ /* Track changes of this data structure */
2350+
2351+ uint32_t major;
2352+ uint32_t minor;
2353+
2354+ /* Last context to touch part of hw */
2355+ uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
2356+
2357+ /* Definition of front- and rotated buffers */
2358+ uint32_t num_scanouts;
2359+ struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
2360+
2361+ int planeA_x;
2362+ int planeA_y;
2363+ int planeA_w;
2364+ int planeA_h;
2365+ int planeB_x;
2366+ int planeB_y;
2367+ int planeB_w;
2368+ int planeB_h;
2369+ uint32_t msvdx_state;
2370+ uint32_t msvdx_context;
2371+};
2372+
2373+#define PSB_RELOC_MAGIC 0x67676767
2374+#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
2375+#define PSB_RELOC_SHIFT_SHIFT 0
2376+#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
2377+#define PSB_RELOC_ALSHIFT_SHIFT 16
2378+
2379+#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
2380+ * buffer
2381+ */
2382+#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
2383+ * buffer, relative to 2D
2384+ * base address
2385+ */
2386+#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
2387+ * relative to PDS base address
2388+ */
2389+#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
2390+ * buffer (for tiling)
2391+ */
2392+#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
2393+ * relative to base reg
2394+ */
2395+#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
2396+
2397+struct drm_psb_reloc {
2398+ uint32_t reloc_op;
2399+ uint32_t where; /* offset in destination buffer */
2400+ uint32_t buffer; /* Buffer reloc applies to */
2401+ uint32_t mask; /* Destination format: */
2402+ uint32_t shift; /* Destination format: */
2403+ uint32_t pre_add; /* Destination format: */
2404+ uint32_t background; /* Destination add */
2405+ uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
2406+ uint32_t arg0; /* Reloc-op dependant */
2407+ uint32_t arg1;
2408+};
2409+
2410+#define PSB_BO_FLAG_TA (1ULL << 48)
2411+#define PSB_BO_FLAG_SCENE (1ULL << 49)
2412+#define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
2413+#define PSB_BO_FLAG_USSE (1ULL << 51)
2414+
2415+#define PSB_ENGINE_2D 0
2416+#define PSB_ENGINE_VIDEO 1
2417+#define PSB_ENGINE_RASTERIZER 2
2418+#define PSB_ENGINE_TA 3
2419+#define PSB_ENGINE_HPRAST 4
2420+
2421+/*
2422+ * For this fence class we have a couple of
2423+ * fence types.
2424+ */
2425+
2426+#define _PSB_FENCE_EXE_SHIFT 0
2427+#define _PSB_FENCE_TA_DONE_SHIFT 1
2428+#define _PSB_FENCE_RASTER_DONE_SHIFT 2
2429+#define _PSB_FENCE_SCENE_DONE_SHIFT 3
2430+#define _PSB_FENCE_FEEDBACK_SHIFT 4
2431+
2432+#define _PSB_ENGINE_TA_FENCE_TYPES 5
2433+#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
2434+#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
2435+#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
2436+#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
2437+
2438+#define PSB_ENGINE_HPRAST 4
2439+#define PSB_NUM_ENGINES 5
2440+
2441+#define PSB_TA_FLAG_FIRSTPASS (1 << 0)
2442+#define PSB_TA_FLAG_LASTPASS (1 << 1)
2443+
2444+#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
2445+
2446+struct drm_psb_scene {
2447+ int handle_valid;
2448+ uint32_t handle;
2449+ uint32_t w;
2450+ uint32_t h;
2451+ uint32_t num_buffers;
2452+};
2453+
2454+typedef struct drm_psb_cmdbuf_arg {
2455+ uint64_t buffer_list; /* List of buffers to validate */
2456+ uint64_t clip_rects; /* See i915 counterpart */
2457+ uint64_t scene_arg;
2458+ uint64_t fence_arg;
2459+
2460+ uint32_t ta_flags;
2461+
2462+ uint32_t ta_handle; /* TA reg-value pairs */
2463+ uint32_t ta_offset;
2464+ uint32_t ta_size;
2465+
2466+ uint32_t oom_handle;
2467+ uint32_t oom_offset;
2468+ uint32_t oom_size;
2469+
2470+ uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
2471+ uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
2472+ uint32_t cmdbuf_size;
2473+
2474+ uint32_t reloc_handle; /* Reloc buffer object */
2475+ uint32_t reloc_offset;
2476+ uint32_t num_relocs;
2477+
2478+ int32_t damage; /* Damage front buffer with cliprects */
2479+ /* Not implemented yet */
2480+ uint32_t fence_flags;
2481+ uint32_t engine;
2482+
2483+ /*
2484+ * Feedback;
2485+ */
2486+
2487+ uint32_t feedback_ops;
2488+ uint32_t feedback_handle;
2489+ uint32_t feedback_offset;
2490+ uint32_t feedback_breakpoints;
2491+ uint32_t feedback_size;
2492+} drm_psb_cmdbuf_arg_t;
2493+
2494+struct drm_psb_xhw_init_arg {
2495+ uint32_t operation;
2496+ uint32_t buffer_handle;
2497+};
2498+
2499+/*
2500+ * Feedback components:
2501+ */
2502+
2503+/*
2504+ * Vistest component. The number of these in the feedback buffer
2505+ * equals the number of vistest breakpoints + 1.
2506+ * This is currently the only feedback component.
2507+ */
2508+
2509+struct drm_psb_vistest {
2510+ uint32_t vt[8];
2511+};
2512+
2513+#define PSB_HW_COOKIE_SIZE 16
2514+#define PSB_HW_FEEDBACK_SIZE 8
2515+#define PSB_HW_OOM_CMD_SIZE 6
2516+
2517+struct drm_psb_xhw_arg {
2518+ uint32_t op;
2519+ int ret;
2520+ uint32_t irq_op;
2521+ uint32_t issue_irq;
2522+ uint32_t cookie[PSB_HW_COOKIE_SIZE];
2523+ union {
2524+ struct {
2525+ uint32_t w;
2526+ uint32_t h;
2527+ uint32_t size;
2528+ uint32_t clear_p_start;
2529+ uint32_t clear_num_pages;
2530+ } si;
2531+ struct {
2532+ uint32_t fire_flags;
2533+ uint32_t hw_context;
2534+ uint32_t offset;
2535+ uint32_t engine;
2536+ uint32_t flags;
2537+ uint32_t rca;
2538+ uint32_t num_oom_cmds;
2539+ uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
2540+ } sb;
2541+ struct {
2542+ uint32_t pages;
2543+ uint32_t size;
2544+ } bi;
2545+ struct {
2546+ uint32_t bca;
2547+ uint32_t rca;
2548+ uint32_t flags;
2549+ } oom;
2550+ struct {
2551+ uint32_t pt_offset;
2552+ uint32_t param_offset;
2553+ uint32_t flags;
2554+ } bl;
2555+ uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
2556+ } arg;
2557+};
2558+
2559+#define DRM_PSB_CMDBUF 0x00
2560+#define DRM_PSB_XHW_INIT 0x01
2561+#define DRM_PSB_XHW 0x02
2562+#define DRM_PSB_SCENE_UNREF 0x03
2563+/* Controlling the kernel modesetting buffers */
2564+#define DRM_PSB_KMS_OFF 0x04
2565+#define DRM_PSB_KMS_ON 0x05
2566+
2567+#define PSB_XHW_INIT 0x00
2568+#define PSB_XHW_TAKEDOWN 0x01
2569+
2570+#define PSB_XHW_FIRE_RASTER 0x00
2571+#define PSB_XHW_SCENE_INFO 0x01
2572+#define PSB_XHW_SCENE_BIND_FIRE 0x02
2573+#define PSB_XHW_TA_MEM_INFO 0x03
2574+#define PSB_XHW_RESET_DPM 0x04
2575+#define PSB_XHW_OOM 0x05
2576+#define PSB_XHW_TERMINATE 0x06
2577+#define PSB_XHW_VISTEST 0x07
2578+#define PSB_XHW_RESUME 0x08
2579+#define PSB_XHW_TA_MEM_LOAD 0x09
2580+
2581+#define PSB_SCENE_FLAG_DIRTY (1 << 0)
2582+#define PSB_SCENE_FLAG_COMPLETE (1 << 1)
2583+#define PSB_SCENE_FLAG_SETUP (1 << 2)
2584+#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
2585+#define PSB_SCENE_FLAG_CLEARED (1 << 4)
2586+
2587+#define PSB_TA_MEM_FLAG_TA (1 << 0)
2588+#define PSB_TA_MEM_FLAG_RASTER (1 << 1)
2589+#define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
2590+#define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
2591+#define PSB_TA_MEM_FLAG_INIT (1 << 4)
2592+#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
2593+
2594+/*Raster fire will deallocate memory */
2595+#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
2596+/*Isp reset needed due to change in ZLS format */
2597+#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
2598+/*These are set by Xpsb. */
2599+#define PSB_FIRE_FLAG_XHW_MASK 0xff000000
2600+/*The task has had at least one OOM and Xpsb will
2601+ send back messages on each fire. */
2602+#define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
2603+
2604+#define PSB_SCENE_ENGINE_TA 0
2605+#define PSB_SCENE_ENGINE_RASTER 1
2606+#define PSB_SCENE_NUM_ENGINES 2
2607+
2608+struct drm_psb_dev_info_arg {
2609+ uint32_t num_use_attribute_registers;
2610+};
2611+#define DRM_PSB_DEVINFO 0x01
2612+
2613+#endif
2614Index: libdrm-2.3.1/shared-core/psb_drv.h
2615===================================================================
2616--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2617+++ libdrm-2.3.1/shared-core/psb_drv.h 2009-01-14 18:26:59.000000000 +0000
2618@@ -0,0 +1,786 @@
2619+/**************************************************************************
2620+ * Copyright (c) 2007, Intel Corporation.
2621+ * All Rights Reserved.
2622+ *
2623+ * This program is free software; you can redistribute it and/or modify it
2624+ * under the terms and conditions of the GNU General Public License,
2625+ * version 2, as published by the Free Software Foundation.
2626+ *
2627+ * This program is distributed in the hope it will be useful, but WITHOUT
2628+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2629+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
2630+ * more details.
2631+ *
2632+ * You should have received a copy of the GNU General Public License along with
2633+ * this program; if not, write to the Free Software Foundation, Inc.,
2634+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
2635+ *
2636+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
2637+ * develop this driver.
2638+ *
2639+ **************************************************************************/
2640+/*
2641+ */
2642+#ifndef _PSB_DRV_H_
2643+#define _PSB_DRV_H_
2644+
2645+#include "drmP.h"
2646+#include "psb_drm.h"
2647+#include "psb_reg.h"
2648+#include "psb_schedule.h"
2649+#include "intel_drv.h"
2650+
2651+enum {
2652+ CHIP_PSB_8108 = 0,
2653+ CHIP_PSB_8109 = 1
2654+};
2655+
2656+#define DRIVER_NAME "psb"
2657+#define DRIVER_DESC "drm driver for the Intel GMA500"
2658+#define DRIVER_AUTHOR "Tungsten Graphics Inc."
2659+
2660+#define PSB_DRM_DRIVER_DATE "20080107"
2661+#define PSB_DRM_DRIVER_MAJOR 4
2662+#define PSB_DRM_DRIVER_MINOR 1
2663+#define PSB_DRM_DRIVER_PATCHLEVEL 0
2664+
2665+#define PSB_VDC_OFFSET 0x00000000
2666+#define PSB_VDC_SIZE 0x000080000
2667+#define PSB_SGX_SIZE 0x8000
2668+#define PSB_SGX_OFFSET 0x00040000
2669+#define PSB_MMIO_RESOURCE 0
2670+#define PSB_GATT_RESOURCE 2
2671+#define PSB_GTT_RESOURCE 3
2672+#define PSB_GMCH_CTRL 0x52
2673+#define PSB_BSM 0x5C
2674+#define _PSB_GMCH_ENABLED 0x4
2675+#define PSB_PGETBL_CTL 0x2020
2676+#define _PSB_PGETBL_ENABLED 0x00000001
2677+#define PSB_SGX_2D_SLAVE_PORT 0x4000
2678+#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
2679+#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
2680+#define PSB_NUM_VALIDATE_BUFFERS 640
2681+#define PSB_MEM_KERNEL_START 0x10000000
2682+#define PSB_MEM_PDS_START 0x20000000
2683+#define PSB_MEM_MMU_START 0x40000000
2684+
2685+#define DRM_PSB_MEM_KERNEL DRM_BO_MEM_PRIV0
2686+#define DRM_PSB_FLAG_MEM_KERNEL DRM_BO_FLAG_MEM_PRIV0
2687+
2688+/*
2689+ * Flags for external memory type field.
2690+ */
2691+
2692+#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
2693+#define PSB_MSVDX_SIZE 0x8000 /*MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
2694+
2695+#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
2696+#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
2697+#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
2698+
2699+/*
2700+ * PTE's and PDE's
2701+ */
2702+
2703+#define PSB_PDE_MASK 0x003FFFFF
2704+#define PSB_PDE_SHIFT 22
2705+#define PSB_PTE_SHIFT 12
2706+
2707+#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
2708+#define PSB_PTE_WO 0x0002 /* Write only */
2709+#define PSB_PTE_RO 0x0004 /* Read only */
2710+#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
2711+
2712+/*
2713+ * VDC registers and bits
2714+ */
2715+#define PSB_HWSTAM 0x2098
2716+#define PSB_INSTPM 0x20C0
2717+#define PSB_INT_IDENTITY_R 0x20A4
2718+#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
2719+#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
2720+#define _PSB_IRQ_SGX_FLAG (1<<18)
2721+#define _PSB_IRQ_MSVDX_FLAG (1<<19)
2722+#define PSB_INT_MASK_R 0x20A8
2723+#define PSB_INT_ENABLE_R 0x20A0
2724+#define PSB_PIPEASTAT 0x70024
2725+#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17)
2726+#define _PSB_VBLANK_CLEAR (1 << 1)
2727+#define PSB_PIPEBSTAT 0x71024
2728+
2729+#define _PSB_MMU_ER_MASK 0x0001FF00
2730+#define _PSB_MMU_ER_HOST (1 << 16)
2731+#define GPIOA 0x5010
2732+#define GPIOB 0x5014
2733+#define GPIOC 0x5018
2734+#define GPIOD 0x501c
2735+#define GPIOE 0x5020
2736+#define GPIOF 0x5024
2737+#define GPIOG 0x5028
2738+#define GPIOH 0x502c
2739+#define GPIO_CLOCK_DIR_MASK (1 << 0)
2740+#define GPIO_CLOCK_DIR_IN (0 << 1)
2741+#define GPIO_CLOCK_DIR_OUT (1 << 1)
2742+#define GPIO_CLOCK_VAL_MASK (1 << 2)
2743+#define GPIO_CLOCK_VAL_OUT (1 << 3)
2744+#define GPIO_CLOCK_VAL_IN (1 << 4)
2745+#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2746+#define GPIO_DATA_DIR_MASK (1 << 8)
2747+#define GPIO_DATA_DIR_IN (0 << 9)
2748+#define GPIO_DATA_DIR_OUT (1 << 9)
2749+#define GPIO_DATA_VAL_MASK (1 << 10)
2750+#define GPIO_DATA_VAL_OUT (1 << 11)
2751+#define GPIO_DATA_VAL_IN (1 << 12)
2752+#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2753+
2754+#define VCLK_DIVISOR_VGA0 0x6000
2755+#define VCLK_DIVISOR_VGA1 0x6004
2756+#define VCLK_POST_DIV 0x6010
2757+
2758+#define DRM_DRIVER_PRIVATE_T struct drm_psb_private
2759+#define I915_WRITE(_offs, _val) \
2760+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
2761+#define I915_READ(_offs) \
2762+ ioread32(dev_priv->vdc_reg + (_offs))
2763+
2764+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
2765+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
2766+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
2767+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
2768+#define PSB_COMM_USER_IRQ (1024 >> 2)
2769+#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
2770+#define PSB_COMM_FW (2048 >> 2)
2771+
2772+#define PSB_UIRQ_VISTEST 1
2773+#define PSB_UIRQ_OOM_REPLY 2
2774+#define PSB_UIRQ_FIRE_TA_REPLY 3
2775+#define PSB_UIRQ_FIRE_RASTER_REPLY 4
2776+
2777+#define PSB_2D_SIZE (256*1024*1024)
2778+#define PSB_MAX_RELOC_PAGES 1024
2779+
2780+#define PSB_LOW_REG_OFFS 0x0204
2781+#define PSB_HIGH_REG_OFFS 0x0600
2782+
2783+#define PSB_NUM_VBLANKS 2
2784+
2785+#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
2786+#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
2787+#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
2788+#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
2789+#define PSB_COMM_FW (2048 >> 2)
2790+
2791+#define PSB_2D_SIZE (256*1024*1024)
2792+#define PSB_MAX_RELOC_PAGES 1024
2793+
2794+#define PSB_LOW_REG_OFFS 0x0204
2795+#define PSB_HIGH_REG_OFFS 0x0600
2796+
2797+#define PSB_NUM_VBLANKS 2
2798+#define PSB_WATCHDOG_DELAY (DRM_HZ / 10)
2799+
2800+/*
2801+ * User options.
2802+ */
2803+
2804+struct drm_psb_uopt {
2805+ int disable_clock_gating;
2806+};
2807+
2808+struct psb_gtt {
2809+ struct drm_device *dev;
2810+ int initialized;
2811+ uint32_t gatt_start;
2812+ uint32_t gtt_start;
2813+ uint32_t gtt_phys_start;
2814+ unsigned gtt_pages;
2815+ unsigned gatt_pages;
2816+ uint32_t stolen_base;
2817+ uint32_t pge_ctl;
2818+ u16 gmch_ctrl;
2819+ unsigned long stolen_size;
2820+ uint32_t *gtt_map;
2821+ struct rw_semaphore sem;
2822+};
2823+
2824+struct psb_use_base {
2825+ struct list_head head;
2826+ struct drm_fence_object *fence;
2827+ unsigned int reg;
2828+ unsigned long offset;
2829+ unsigned int dm;
2830+};
2831+
2832+struct psb_buflist_item {
2833+ struct drm_buffer_object *bo;
2834+ void __user *data;
2835+ struct drm_bo_info_rep rep;
2836+ int ret;
2837+};
2838+
2839+struct psb_msvdx_cmd_queue {
2840+ struct list_head head;
2841+ void *cmd;
2842+ unsigned long cmd_size;
2843+ uint32_t sequence;
2844+};
2845+
2846+struct drm_psb_private {
2847+ unsigned long chipset;
2848+
2849+ struct psb_xhw_buf resume_buf;
2850+ struct drm_psb_dev_info_arg dev_info;
2851+ struct drm_psb_uopt uopt;
2852+
2853+ struct psb_gtt *pg;
2854+
2855+ struct page *scratch_page;
2856+ struct page *comm_page;
2857+
2858+ volatile uint32_t *comm;
2859+ uint32_t comm_mmu_offset;
2860+ uint32_t mmu_2d_offset;
2861+ uint32_t sequence[PSB_NUM_ENGINES];
2862+ uint32_t last_sequence[PSB_NUM_ENGINES];
2863+ int idle[PSB_NUM_ENGINES];
2864+ uint32_t last_submitted_seq[PSB_NUM_ENGINES];
2865+ int engine_lockup_2d;
2866+
2867+ struct psb_mmu_driver *mmu;
2868+ struct psb_mmu_pd *pf_pd;
2869+
2870+ uint8_t *sgx_reg;
2871+ uint8_t *vdc_reg;
2872+ uint8_t *msvdx_reg;
2873+ /*MSVDX*/ int msvdx_needs_reset;
2874+ int has_msvdx;
2875+ uint32_t gatt_free_offset;
2876+
2877+ /*
2878+ * Fencing / irq.
2879+ */
2880+
2881+ uint32_t sgx_irq_mask;
2882+ uint32_t vdc_irq_mask;
2883+
2884+ spinlock_t irqmask_lock;
2885+ spinlock_t sequence_lock;
2886+ int fence0_irq_on;
2887+ int irq_enabled;
2888+ unsigned int irqen_count_2d;
2889+ wait_queue_head_t event_2d_queue;
2890+
2891+ uint32_t msvdx_current_sequence;
2892+ uint32_t msvdx_last_sequence;
2893+ int fence2_irq_on;
2894+ struct mutex mutex_2d;
2895+
2896+ /*
2897+ * MSVDX Rendec Memory
2898+ */
2899+ struct drm_buffer_object *ccb0;
2900+ uint32_t base_addr0;
2901+ struct drm_buffer_object *ccb1;
2902+ uint32_t base_addr1;
2903+
2904+ /*
2905+ * Memory managers
2906+ */
2907+
2908+ int have_vram;
2909+ int have_tt;
2910+ int have_mem_mmu;
2911+ int have_mem_aper;
2912+ int have_mem_kernel;
2913+ int have_mem_pds;
2914+ int have_mem_rastgeom;
2915+ struct mutex temp_mem;
2916+
2917+ /*
2918+ * Relocation buffer mapping.
2919+ */
2920+
2921+ spinlock_t reloc_lock;
2922+ unsigned int rel_mapped_pages;
2923+ wait_queue_head_t rel_mapped_queue;
2924+
2925+ /*
2926+ * SAREA
2927+ */
2928+ struct drm_psb_sarea *sarea_priv;
2929+
2930+ /*
2931+ * LVDS info
2932+ */
2933+ uint8_t blc_type;
2934+ uint8_t blc_pol;
2935+ uint8_t blc_freq;
2936+ uint8_t blc_minbrightness;
2937+ uint8_t blc_i2caddr;
2938+ uint8_t blc_brightnesscmd;
2939+ int backlight; /* restore backlight to this value */
2940+
2941+ struct intel_i2c_chan *i2c_bus;
2942+ u32 CoreClock;
2943+ u32 PWMControlRegFreq;
2944+
2945+ unsigned char * OpRegion;
2946+ unsigned int OpRegionSize;
2947+
2948+ int backlight_duty_cycle; /* restore backlight to this value */
2949+ bool panel_wants_dither;
2950+ struct drm_display_mode *panel_fixed_mode;
2951+
2952+ /*
2953+ * Register state
2954+ */
2955+ uint32_t saveDSPACNTR;
2956+ uint32_t saveDSPBCNTR;
2957+ uint32_t savePIPEACONF;
2958+ uint32_t savePIPEBCONF;
2959+ uint32_t savePIPEASRC;
2960+ uint32_t savePIPEBSRC;
2961+ uint32_t saveFPA0;
2962+ uint32_t saveFPA1;
2963+ uint32_t saveDPLL_A;
2964+ uint32_t saveDPLL_A_MD;
2965+ uint32_t saveHTOTAL_A;
2966+ uint32_t saveHBLANK_A;
2967+ uint32_t saveHSYNC_A;
2968+ uint32_t saveVTOTAL_A;
2969+ uint32_t saveVBLANK_A;
2970+ uint32_t saveVSYNC_A;
2971+ uint32_t saveDSPASTRIDE;
2972+ uint32_t saveDSPASIZE;
2973+ uint32_t saveDSPAPOS;
2974+ uint32_t saveDSPABASE;
2975+ uint32_t saveDSPASURF;
2976+ uint32_t saveFPB0;
2977+ uint32_t saveFPB1;
2978+ uint32_t saveDPLL_B;
2979+ uint32_t saveDPLL_B_MD;
2980+ uint32_t saveHTOTAL_B;
2981+ uint32_t saveHBLANK_B;
2982+ uint32_t saveHSYNC_B;
2983+ uint32_t saveVTOTAL_B;
2984+ uint32_t saveVBLANK_B;
2985+ uint32_t saveVSYNC_B;
2986+ uint32_t saveDSPBSTRIDE;
2987+ uint32_t saveDSPBSIZE;
2988+ uint32_t saveDSPBPOS;
2989+ uint32_t saveDSPBBASE;
2990+ uint32_t saveDSPBSURF;
2991+ uint32_t saveVCLK_DIVISOR_VGA0;
2992+ uint32_t saveVCLK_DIVISOR_VGA1;
2993+ uint32_t saveVCLK_POST_DIV;
2994+ uint32_t saveVGACNTRL;
2995+ uint32_t saveADPA;
2996+ uint32_t saveLVDS;
2997+ uint32_t saveDVOA;
2998+ uint32_t saveDVOB;
2999+ uint32_t saveDVOC;
3000+ uint32_t savePP_ON;
3001+ uint32_t savePP_OFF;
3002+ uint32_t savePP_CONTROL;
3003+ uint32_t savePP_CYCLE;
3004+ uint32_t savePFIT_CONTROL;
3005+ uint32_t savePaletteA[256];
3006+ uint32_t savePaletteB[256];
3007+ uint32_t saveBLC_PWM_CTL;
3008+
3009+ /*
3010+ * USE code base register management.
3011+ */
3012+
3013+ struct drm_reg_manager use_manager;
3014+
3015+ /*
3016+ * Xhw
3017+ */
3018+
3019+ uint32_t *xhw;
3020+ struct drm_buffer_object *xhw_bo;
3021+ struct drm_bo_kmap_obj xhw_kmap;
3022+ struct list_head xhw_in;
3023+ spinlock_t xhw_lock;
3024+ atomic_t xhw_client;
3025+ struct drm_file *xhw_file;
3026+ wait_queue_head_t xhw_queue;
3027+ wait_queue_head_t xhw_caller_queue;
3028+ struct mutex xhw_mutex;
3029+ struct psb_xhw_buf *xhw_cur_buf;
3030+ int xhw_submit_ok;
3031+ int xhw_on;
3032+
3033+ /*
3034+ * Scheduling.
3035+ */
3036+
3037+ struct mutex reset_mutex;
3038+ struct mutex cmdbuf_mutex;
3039+ struct psb_scheduler scheduler;
3040+ struct psb_buflist_item buffers[PSB_NUM_VALIDATE_BUFFERS];
3041+ uint32_t ta_mem_pages;
3042+ struct psb_ta_mem *ta_mem;
3043+ int force_ta_mem_load;
3044+
3045+ /*
3046+ * Watchdog
3047+ */
3048+
3049+ spinlock_t watchdog_lock;
3050+ struct timer_list watchdog_timer;
3051+ struct work_struct watchdog_wq;
3052+ struct work_struct msvdx_watchdog_wq;
3053+ int timer_available;
3054+
3055+ /*
3056+ * msvdx command queue
3057+ */
3058+ spinlock_t msvdx_lock;
3059+ struct mutex msvdx_mutex;
3060+ struct list_head msvdx_queue;
3061+ int msvdx_busy;
3062+};
3063+
3064+struct psb_mmu_driver;
3065+
3066+extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
3067+ int trap_pagefaults,
3068+ int invalid_type);
3069+extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
3070+extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver);
3071+extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
3072+ uint32_t gtt_start, uint32_t gtt_pages);
3073+extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset);
3074+extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
3075+ int trap_pagefaults,
3076+ int invalid_type);
3077+extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
3078+extern void psb_mmu_flush(struct psb_mmu_driver *driver);
3079+extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
3080+ unsigned long address,
3081+ uint32_t num_pages);
3082+extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
3083+ uint32_t start_pfn,
3084+ unsigned long address,
3085+ uint32_t num_pages, int type);
3086+extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
3087+ unsigned long *pfn);
3088+
3089+/*
3090+ * Enable / disable MMU for different requestors.
3091+ */
3092+
3093+extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver,
3094+ uint32_t mask);
3095+extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver,
3096+ uint32_t mask);
3097+extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
3098+extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
3099+ unsigned long address, uint32_t num_pages,
3100+ uint32_t desired_tile_stride,
3101+ uint32_t hw_tile_stride, int type);
3102+extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
3103+ uint32_t num_pages,
3104+ uint32_t desired_tile_stride,
3105+ uint32_t hw_tile_stride);
3106+/*
3107+ * psb_sgx.c
3108+ */
3109+
3110+extern int psb_blit_sequence(struct drm_psb_private *dev_priv,
3111+ uint32_t sequence);
3112+extern void psb_init_2d(struct drm_psb_private *dev_priv);
3113+extern int drm_psb_idle(struct drm_device *dev);
3114+extern int psb_emit_2d_copy_blit(struct drm_device *dev,
3115+ uint32_t src_offset,
3116+ uint32_t dst_offset, uint32_t pages,
3117+ int direction);
3118+extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
3119+ struct drm_file *file_priv);
3120+extern int psb_reg_submit(struct drm_psb_private *dev_priv, uint32_t * regs,
3121+ unsigned int cmds);
3122+extern int psb_submit_copy_cmdbuf(struct drm_device *dev,
3123+ struct drm_buffer_object *cmd_buffer,
3124+ unsigned long cmd_offset,
3125+ unsigned long cmd_size, int engine,
3126+ uint32_t * copy_buffer);
3127+
3128+extern int psb_fence_for_errors(struct drm_file *priv,
3129+ struct drm_psb_cmdbuf_arg *arg,
3130+ struct drm_fence_arg *fence_arg,
3131+ struct drm_fence_object **fence_p);
3132+
3133+/*
3134+ * psb_irq.c
3135+ */
3136+
3137+extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
3138+extern void psb_irq_preinstall(struct drm_device *dev);
3139+extern void psb_irq_postinstall(struct drm_device *dev);
3140+extern void psb_irq_uninstall(struct drm_device *dev);
3141+extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
3142+extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
3143+
3144+/*
3145+ * psb_fence.c
3146+ */
3147+
3148+extern void psb_poke_flush(struct drm_device *dev, uint32_t class);
3149+extern int psb_fence_emit_sequence(struct drm_device *dev, uint32_t class,
3150+ uint32_t flags, uint32_t * sequence,
3151+ uint32_t * native_type);
3152+extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
3153+extern int psb_fence_has_irq(struct drm_device *dev, uint32_t class,
3154+ uint32_t flags);
3155+extern void psb_2D_irq_off(struct drm_psb_private *dev_priv);
3156+extern void psb_2D_irq_on(struct drm_psb_private *dev_priv);
3157+extern uint32_t psb_fence_advance_sequence(struct drm_device *dev,
3158+ uint32_t class);
3159+extern void psb_fence_error(struct drm_device *dev,
3160+ uint32_t class,
3161+ uint32_t sequence, uint32_t type, int error);
3162+
3163+/*MSVDX stuff*/
3164+extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv);
3165+extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv);
3166+
3167+/*
3168+ * psb_buffer.c
3169+ */
3170+extern struct drm_ttm_backend *drm_psb_tbe_init(struct drm_device *dev);
3171+extern int psb_fence_types(struct drm_buffer_object *bo, uint32_t * class,
3172+ uint32_t * type);
3173+extern uint32_t psb_evict_mask(struct drm_buffer_object *bo);
3174+extern int psb_invalidate_caches(struct drm_device *dev, uint64_t flags);
3175+extern int psb_init_mem_type(struct drm_device *dev, uint32_t type,
3176+ struct drm_mem_type_manager *man);
3177+extern int psb_move(struct drm_buffer_object *bo,
3178+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
3179+
3180+/*
3181+ * psb_gtt.c
3182+ */
3183+extern int psb_gtt_init(struct psb_gtt *pg, int resume);
3184+extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
3185+ unsigned offset_pages, unsigned num_pages,
3186+ unsigned desired_tile_stride,
3187+ unsigned hw_tile_stride, int type);
3188+extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
3189+ unsigned num_pages,
3190+ unsigned desired_tile_stride,
3191+ unsigned hw_tile_stride);
3192+
3193+extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
3194+extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
3195+
3196+/*
3197+ * psb_fb.c
3198+ */
3199+extern int psbfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
3200+extern int psbfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
3201+extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
3202+ struct drm_file *file_priv);
3203+extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
3204+ struct drm_file *file_priv);
3205+
3206+/*
3207+ * psb_reset.c
3208+ */
3209+
3210+extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d);
3211+extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv);
3212+extern void psb_watchdog_init(struct drm_psb_private *dev_priv);
3213+extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv);
3214+
3215+/*
3216+ * psb_regman.c
3217+ */
3218+
3219+extern void psb_takedown_use_base(struct drm_psb_private *dev_priv);
3220+extern int psb_grab_use_base(struct drm_psb_private *dev_priv,
3221+ unsigned long dev_virtual,
3222+ unsigned long size,
3223+ unsigned int data_master,
3224+ uint32_t fence_class,
3225+ uint32_t fence_type,
3226+ int no_wait,
3227+ int ignore_signals,
3228+ int *r_reg, uint32_t * r_offset);
3229+extern int psb_init_use_base(struct drm_psb_private *dev_priv,
3230+ unsigned int reg_start, unsigned int reg_num);
3231+
3232+/*
3233+ * psb_xhw.c
3234+ */
3235+
3236+extern int psb_xhw_ioctl(struct drm_device *dev, void *data,
3237+ struct drm_file *file_priv);
3238+extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data,
3239+ struct drm_file *file_priv);
3240+extern int psb_xhw_init(struct drm_device *dev);
3241+extern void psb_xhw_takedown(struct drm_psb_private *dev_priv);
3242+extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv,
3243+ struct drm_file *file_priv, int closing);
3244+extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv,
3245+ struct psb_xhw_buf *buf,
3246+ uint32_t fire_flags,
3247+ uint32_t hw_context,
3248+ uint32_t * cookie,
3249+ uint32_t * oom_cmds,
3250+ uint32_t num_oom_cmds,
3251+ uint32_t offset,
3252+ uint32_t engine, uint32_t flags);
3253+extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv,
3254+ struct psb_xhw_buf *buf, uint32_t fire_flags);
3255+extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv,
3256+ struct psb_xhw_buf *buf,
3257+ uint32_t w,
3258+ uint32_t h,
3259+ uint32_t * hw_cookie,
3260+ uint32_t * bo_size,
3261+ uint32_t * clear_p_start,
3262+ uint32_t * clear_num_pages);
3263+
3264+extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv,
3265+ struct psb_xhw_buf *buf);
3266+extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv,
3267+ struct psb_xhw_buf *buf,
3268+ uint32_t pages,
3269+ uint32_t * hw_cookie, uint32_t * size);
3270+extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv,
3271+ struct psb_xhw_buf *buf, uint32_t * cookie);
3272+extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv,
3273+ struct psb_xhw_buf *buf,
3274+ uint32_t * cookie,
3275+ uint32_t * bca,
3276+ uint32_t * rca, uint32_t * flags);
3277+extern int psb_xhw_vistest(struct drm_psb_private *dev_priv,
3278+ struct psb_xhw_buf *buf);
3279+extern int psb_xhw_handler(struct drm_psb_private *dev_priv);
3280+extern int psb_xhw_resume(struct drm_psb_private *dev_priv,
3281+ struct psb_xhw_buf *buf);
3282+extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv,
3283+ struct psb_xhw_buf *buf, uint32_t * cookie);
3284+extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv,
3285+ struct psb_xhw_buf *buf,
3286+ uint32_t flags,
3287+ uint32_t param_offset,
3288+ uint32_t pt_offset,
3289+ uint32_t *hw_cookie);
3290+extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv,
3291+ struct psb_xhw_buf *buf);
3292+
3293+/*
3294+ * Utilities
3295+ */
3296+
3297+#define PSB_ALIGN_TO(_val, _align) \
3298+ (((_val) + ((_align) - 1)) & ~((_align) - 1))
3299+#define PSB_WVDC32(_val, _offs) \
3300+ iowrite32(_val, dev_priv->vdc_reg + (_offs))
3301+#define PSB_RVDC32(_offs) \
3302+ ioread32(dev_priv->vdc_reg + (_offs))
3303+#define PSB_WSGX32(_val, _offs) \
3304+ iowrite32(_val, dev_priv->sgx_reg + (_offs))
3305+#define PSB_RSGX32(_offs) \
3306+ ioread32(dev_priv->sgx_reg + (_offs))
3307+#define PSB_WMSVDX32(_val, _offs) \
3308+ iowrite32(_val, dev_priv->msvdx_reg + (_offs))
3309+#define PSB_RMSVDX32(_offs) \
3310+ ioread32(dev_priv->msvdx_reg + (_offs))
3311+
3312+#define PSB_ALPL(_val, _base) \
3313+ (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
3314+#define PSB_ALPLM(_val, _base) \
3315+ ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
3316+
3317+static inline psb_fixed psb_mul_fixed(psb_fixed a, psb_fixed b)
3318+{
3319+ s64 tmp;
3320+ s64 a64 = (s64) a;
3321+ s64 b64 = (s64) b;
3322+
3323+ tmp = a64 * b64;
3324+ return tmp / (1ULL << PSB_FIXED_SHIFT) +
3325+ ((tmp & 0x80000000ULL) ? 1 : 0);
3326+}
3327+
3328+static inline psb_fixed psb_mul_ufixed(psb_ufixed a, psb_fixed b)
3329+{
3330+ u64 tmp;
3331+ u64 a64 = (u64) a;
3332+ u64 b64 = (u64) b;
3333+
3334+ tmp = a64 * b64;
3335+ return (tmp >> PSB_FIXED_SHIFT) + ((tmp & 0x80000000ULL) ? 1 : 0);
3336+}
3337+
3338+static inline uint32_t psb_ufixed_to_float32(psb_ufixed a)
3339+{
3340+ uint32_t exp = 0x7f + 7;
3341+ uint32_t mantissa = (uint32_t) a;
3342+
3343+ if (a == 0)
3344+ return 0;
3345+ while ((mantissa & 0xff800000) == 0) {
3346+ exp -= 1;
3347+ mantissa <<= 1;
3348+ }
3349+ while ((mantissa & 0xff800000) > 0x00800000) {
3350+ exp += 1;
3351+ mantissa >>= 1;
3352+ }
3353+ return (mantissa & ~0xff800000) | (exp << 23);
3354+}
3355+
3356+static inline uint32_t psb_fixed_to_float32(psb_fixed a)
3357+{
3358+ if (a < 0)
3359+ return psb_ufixed_to_float32(-a) | 0x80000000;
3360+ else
3361+ return psb_ufixed_to_float32(a);
3362+}
3363+
3364+#define PSB_D_RENDER (1 << 16)
3365+
3366+#define PSB_D_GENERAL (1 << 0)
3367+#define PSB_D_INIT (1 << 1)
3368+#define PSB_D_IRQ (1 << 2)
3369+#define PSB_D_FW (1 << 3)
3370+#define PSB_D_PERF (1 << 4)
3371+#define PSB_D_TMP (1 << 5)
3372+
3373+extern int drm_psb_debug;
3374+extern int drm_psb_no_fb;
3375+extern int drm_psb_disable_vsync;
3376+
3377+#define PSB_DEBUG_FW(_fmt, _arg...) \
3378+ PSB_DEBUG(PSB_D_FW, _fmt, ##_arg)
3379+#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
3380+ PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
3381+#define PSB_DEBUG_INIT(_fmt, _arg...) \
3382+ PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
3383+#define PSB_DEBUG_IRQ(_fmt, _arg...) \
3384+ PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
3385+#define PSB_DEBUG_RENDER(_fmt, _arg...) \
3386+ PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
3387+#define PSB_DEBUG_PERF(_fmt, _arg...) \
3388+ PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg)
3389+#define PSB_DEBUG_TMP(_fmt, _arg...) \
3390+ PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg)
3391+
3392+#if DRM_DEBUG_CODE
3393+#define PSB_DEBUG(_flag, _fmt, _arg...) \
3394+ do { \
3395+ if ((_flag) & drm_psb_debug) \
3396+ printk(KERN_DEBUG \
3397+ "[psb:0x%02x:%s] " _fmt , _flag, \
3398+ __FUNCTION__ , ##_arg); \
3399+ } while (0)
3400+#else
3401+#define PSB_DEBUG(_fmt, _arg...) do { } while (0)
3402+#endif
3403+
3404+#endif
3405Index: libdrm-2.3.1/shared-core/psb_reg.h
3406===================================================================
3407--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3408+++ libdrm-2.3.1/shared-core/psb_reg.h 2009-01-14 18:26:59.000000000 +0000
3409@@ -0,0 +1,555 @@
3410+/**************************************************************************
3411+ *
3412+ * Copyright (c) (2005-2007) Imagination Technologies Limited.
3413+ * Copyright (c) 2007, Intel Corporation.
3414+ * All Rights Reserved.
3415+ *
3416+ * This program is free software; you can redistribute it and/or modify it
3417+ * under the terms and conditions of the GNU General Public License,
3418+ * version 2, as published by the Free Software Foundation.
3419+ *
3420+ * This program is distributed in the hope it will be useful, but WITHOUT
3421+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3422+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3423+ * more details.
3424+ *
3425+ * You should have received a copy of the GNU General Public License along with
3426+ * this program; if not, write to the Free Software Foundation, Inc.,
3427+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
3428+ *
3429+ * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
3430+ * develop this driver.
3431+ *
3432+ **************************************************************************/
3433+/*
3434+ */
3435+#ifndef _PSB_REG_H_
3436+#define _PSB_REG_H_
3437+
3438+#define PSB_CR_CLKGATECTL 0x0000
3439+#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24)
3440+#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20)
3441+#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20)
3442+#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16)
3443+#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16)
3444+#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12)
3445+#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12)
3446+#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8)
3447+#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8)
3448+#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4)
3449+#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4)
3450+#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0)
3451+#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0)
3452+#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0)
3453+#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1)
3454+#define _PSB_C_CLKGATECTL_CLKG_AUTO (2)
3455+
3456+#define PSB_CR_CORE_ID 0x0010
3457+#define _PSB_CC_ID_ID_SHIFT (16)
3458+#define _PSB_CC_ID_ID_MASK (0xFFFF << 16)
3459+#define _PSB_CC_ID_CONFIG_SHIFT (0)
3460+#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0)
3461+
3462+#define PSB_CR_CORE_REVISION 0x0014
3463+#define _PSB_CC_REVISION_DESIGNER_SHIFT (24)
3464+#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24)
3465+#define _PSB_CC_REVISION_MAJOR_SHIFT (16)
3466+#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16)
3467+#define _PSB_CC_REVISION_MINOR_SHIFT (8)
3468+#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8)
3469+#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0)
3470+#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0)
3471+
3472+#define PSB_CR_DESIGNER_REV_FIELD1 0x0018
3473+
3474+#define PSB_CR_SOFT_RESET 0x0080
3475+#define _PSB_CS_RESET_TSP_RESET (1 << 6)
3476+#define _PSB_CS_RESET_ISP_RESET (1 << 5)
3477+#define _PSB_CS_RESET_USE_RESET (1 << 4)
3478+#define _PSB_CS_RESET_TA_RESET (1 << 3)
3479+#define _PSB_CS_RESET_DPM_RESET (1 << 2)
3480+#define _PSB_CS_RESET_TWOD_RESET (1 << 1)
3481+#define _PSB_CS_RESET_BIF_RESET (1 << 0)
3482+
3483+#define PSB_CR_DESIGNER_REV_FIELD2 0x001C
3484+
3485+#define PSB_CR_EVENT_STATUS 0x012C
3486+
3487+#define PSB_CR_EVENT_HOST_ENABLE 0x0130
3488+
3489+#define PSB_CR_EVENT_HOST_CLEAR 0x0134
3490+#define _PSB_CE_MASTER_INTERRUPT (1 << 31)
3491+#define _PSB_CE_TA_DPM_FAULT (1 << 28)
3492+#define _PSB_CE_TWOD_COMPLETE (1 << 27)
3493+#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25)
3494+#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24)
3495+#define _PSB_CE_PIXELBE_END_RENDER (1 << 18)
3496+#define _PSB_CE_SW_EVENT (1 << 14)
3497+#define _PSB_CE_TA_FINISHED (1 << 13)
3498+#define _PSB_CE_TA_TERMINATE (1 << 12)
3499+#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3)
3500+#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2)
3501+#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1)
3502+#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0)
3503+
3504+
3505+#define PSB_USE_OFFSET_MASK 0x0007FFFF
3506+#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1)
3507+#define PSB_CR_USE_CODE_BASE0 0x0A0C
3508+#define PSB_CR_USE_CODE_BASE1 0x0A10
3509+#define PSB_CR_USE_CODE_BASE2 0x0A14
3510+#define PSB_CR_USE_CODE_BASE3 0x0A18
3511+#define PSB_CR_USE_CODE_BASE4 0x0A1C
3512+#define PSB_CR_USE_CODE_BASE5 0x0A20
3513+#define PSB_CR_USE_CODE_BASE6 0x0A24
3514+#define PSB_CR_USE_CODE_BASE7 0x0A28
3515+#define PSB_CR_USE_CODE_BASE8 0x0A2C
3516+#define PSB_CR_USE_CODE_BASE9 0x0A30
3517+#define PSB_CR_USE_CODE_BASE10 0x0A34
3518+#define PSB_CR_USE_CODE_BASE11 0x0A38
3519+#define PSB_CR_USE_CODE_BASE12 0x0A3C
3520+#define PSB_CR_USE_CODE_BASE13 0x0A40
3521+#define PSB_CR_USE_CODE_BASE14 0x0A44
3522+#define PSB_CR_USE_CODE_BASE15 0x0A48
3523+#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2))
3524+#define _PSB_CUC_BASE_DM_SHIFT (25)
3525+#define _PSB_CUC_BASE_DM_MASK (0x3 << 25)
3526+#define _PSB_CUC_BASE_ADDR_SHIFT (0) // 1024-bit aligned address?
3527+#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7)
3528+#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0)
3529+#define _PSB_CUC_DM_VERTEX (0)
3530+#define _PSB_CUC_DM_PIXEL (1)
3531+#define _PSB_CUC_DM_RESERVED (2)
3532+#define _PSB_CUC_DM_EDM (3)
3533+
3534+#define PSB_CR_PDS_EXEC_BASE 0x0AB8
3535+#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) // 1MB aligned address
3536+#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20)
3537+
3538+#define PSB_CR_EVENT_KICKER 0x0AC4
3539+#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) // 128-bit aligned address
3540+
3541+#define PSB_CR_EVENT_KICK 0x0AC8
3542+#define _PSB_CE_KICK_NOW (1 << 0)
3543+
3544+
3545+#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38
3546+
3547+#define PSB_CR_BIF_CTRL 0x0C00
3548+#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4)
3549+#define _PSB_CB_CTRL_INVALDC (1 << 3)
3550+#define _PSB_CB_CTRL_FLUSH (1 << 2)
3551+
3552+#define PSB_CR_BIF_INT_STAT 0x0C04
3553+
3554+#define PSB_CR_BIF_FAULT 0x0C08
3555+#define _PSB_CBI_STAT_PF_N_RW (1 << 14)
3556+#define _PSB_CBI_STAT_FAULT_SHIFT (0)
3557+#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0)
3558+#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1)
3559+#define _PSB_CBI_STAT_FAULT_TA (1 << 2)
3560+#define _PSB_CBI_STAT_FAULT_VDM (1 << 3)
3561+#define _PSB_CBI_STAT_FAULT_2D (1 << 4)
3562+#define _PSB_CBI_STAT_FAULT_PBE (1 << 5)
3563+#define _PSB_CBI_STAT_FAULT_TSP (1 << 6)
3564+#define _PSB_CBI_STAT_FAULT_ISP (1 << 7)
3565+#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8)
3566+#define _PSB_CBI_STAT_FAULT_HOST (1 << 9)
3567+
3568+#define PSB_CR_BIF_BANK0 0x0C78
3569+
3570+#define PSB_CR_BIF_BANK1 0x0C7C
3571+
3572+#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84
3573+
3574+#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88
3575+#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC
3576+
3577+#define PSB_CR_2D_SOCIF 0x0E18
3578+#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0)
3579+#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0)
3580+#define _PSB_C2_SOCIF_EMPTY (0x80 << 0)
3581+
3582+#define PSB_CR_2D_BLIT_STATUS 0x0E04
3583+#define _PSB_C2B_STATUS_BUSY (1 << 24)
3584+#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0)
3585+#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0)
3586+
3587+/*
3588+ * 2D defs.
3589+ */
3590+
3591+/*
3592+ * 2D Slave Port Data : Block Header's Object Type
3593+ */
3594+
3595+#define PSB_2D_CLIP_BH (0x00000000)
3596+#define PSB_2D_PAT_BH (0x10000000)
3597+#define PSB_2D_CTRL_BH (0x20000000)
3598+#define PSB_2D_SRC_OFF_BH (0x30000000)
3599+#define PSB_2D_MASK_OFF_BH (0x40000000)
3600+#define PSB_2D_RESERVED1_BH (0x50000000)
3601+#define PSB_2D_RESERVED2_BH (0x60000000)
3602+#define PSB_2D_FENCE_BH (0x70000000)
3603+#define PSB_2D_BLIT_BH (0x80000000)
3604+#define PSB_2D_SRC_SURF_BH (0x90000000)
3605+#define PSB_2D_DST_SURF_BH (0xA0000000)
3606+#define PSB_2D_PAT_SURF_BH (0xB0000000)
3607+#define PSB_2D_SRC_PAL_BH (0xC0000000)
3608+#define PSB_2D_PAT_PAL_BH (0xD0000000)
3609+#define PSB_2D_MASK_SURF_BH (0xE0000000)
3610+#define PSB_2D_FLUSH_BH (0xF0000000)
3611+
3612+/*
3613+ * Clip Definition block (PSB_2D_CLIP_BH)
3614+ */
3615+#define PSB_2D_CLIPCOUNT_MAX (1)
3616+#define PSB_2D_CLIPCOUNT_MASK (0x00000000)
3617+#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF)
3618+#define PSB_2D_CLIPCOUNT_SHIFT (0)
3619+// clip rectangle min & max
3620+#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000)
3621+#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF)
3622+#define PSB_2D_CLIP_XMAX_SHIFT (12)
3623+#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF)
3624+#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000)
3625+#define PSB_2D_CLIP_XMIN_SHIFT (0)
3626+// clip rectangle offset
3627+#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000)
3628+#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF)
3629+#define PSB_2D_CLIP_YMAX_SHIFT (12)
3630+#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF)
3631+#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000)
3632+#define PSB_2D_CLIP_YMIN_SHIFT (0)
3633+
3634+/*
3635+ * Pattern Control (PSB_2D_PAT_BH)
3636+ */
3637+#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F)
3638+#define PSB_2D_PAT_HEIGHT_SHIFT (0)
3639+#define PSB_2D_PAT_WIDTH_MASK (0x000003E0)
3640+#define PSB_2D_PAT_WIDTH_SHIFT (5)
3641+#define PSB_2D_PAT_YSTART_MASK (0x00007C00)
3642+#define PSB_2D_PAT_YSTART_SHIFT (10)
3643+#define PSB_2D_PAT_XSTART_MASK (0x000F8000)
3644+#define PSB_2D_PAT_XSTART_SHIFT (15)
3645+
3646+/*
3647+ * 2D Control block (PSB_2D_CTRL_BH)
3648+ */
3649+// Present Flags
3650+#define PSB_2D_SRCCK_CTRL (0x00000001)
3651+#define PSB_2D_DSTCK_CTRL (0x00000002)
3652+#define PSB_2D_ALPHA_CTRL (0x00000004)
3653+// Colour Key Colour (SRC/DST)
3654+#define PSB_2D_CK_COL_MASK (0xFFFFFFFF)
3655+#define PSB_2D_CK_COL_CLRMASK (0x00000000)
3656+#define PSB_2D_CK_COL_SHIFT (0)
3657+// Colour Key Mask (SRC/DST)
3658+#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF)
3659+#define PSB_2D_CK_MASK_CLRMASK (0x00000000)
3660+#define PSB_2D_CK_MASK_SHIFT (0)
3661+// Alpha Control (Alpha/RGB)
3662+#define PSB_2D_GBLALPHA_MASK (0x000FF000)
3663+#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF)
3664+#define PSB_2D_GBLALPHA_SHIFT (12)
3665+#define PSB_2D_SRCALPHA_OP_MASK (0x00700000)
3666+#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF)
3667+#define PSB_2D_SRCALPHA_OP_SHIFT (20)
3668+#define PSB_2D_SRCALPHA_OP_ONE (0x00000000)
3669+#define PSB_2D_SRCALPHA_OP_SRC (0x00100000)
3670+#define PSB_2D_SRCALPHA_OP_DST (0x00200000)
3671+#define PSB_2D_SRCALPHA_OP_SG (0x00300000)
3672+#define PSB_2D_SRCALPHA_OP_DG (0x00400000)
3673+#define PSB_2D_SRCALPHA_OP_GBL (0x00500000)
3674+#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000)
3675+#define PSB_2D_SRCALPHA_INVERT (0x00800000)
3676+#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF)
3677+#define PSB_2D_DSTALPHA_OP_MASK (0x07000000)
3678+#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF)
3679+#define PSB_2D_DSTALPHA_OP_SHIFT (24)
3680+#define PSB_2D_DSTALPHA_OP_ONE (0x00000000)
3681+#define PSB_2D_DSTALPHA_OP_SRC (0x01000000)
3682+#define PSB_2D_DSTALPHA_OP_DST (0x02000000)
3683+#define PSB_2D_DSTALPHA_OP_SG (0x03000000)
3684+#define PSB_2D_DSTALPHA_OP_DG (0x04000000)
3685+#define PSB_2D_DSTALPHA_OP_GBL (0x05000000)
3686+#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000)
3687+#define PSB_2D_DSTALPHA_INVERT (0x08000000)
3688+#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF)
3689+
3690+#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000)
3691+#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF)
3692+#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000)
3693+#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF)
3694+
3695+/*
3696+ *Source Offset (PSB_2D_SRC_OFF_BH)
3697+ */
3698+#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12)
3699+#define PSB_2D_SRCOFF_XSTART_SHIFT (12)
3700+#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF)
3701+#define PSB_2D_SRCOFF_YSTART_SHIFT (0)
3702+
3703+/*
3704+ * Mask Offset (PSB_2D_MASK_OFF_BH)
3705+ */
3706+#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12)
3707+#define PSB_2D_MASKOFF_XSTART_SHIFT (12)
3708+#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF)
3709+#define PSB_2D_MASKOFF_YSTART_SHIFT (0)
3710+
3711+/*
3712+ * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored
3713+ */
3714+
3715+/*
3716+ *Blit Rectangle (PSB_2D_BLIT_BH)
3717+ */
3718+
3719+#define PSB_2D_ROT_MASK (3<<25)
3720+#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK)
3721+#define PSB_2D_ROT_NONE (0<<25)
3722+#define PSB_2D_ROT_90DEGS (1<<25)
3723+#define PSB_2D_ROT_180DEGS (2<<25)
3724+#define PSB_2D_ROT_270DEGS (3<<25)
3725+
3726+#define PSB_2D_COPYORDER_MASK (3<<23)
3727+#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK)
3728+#define PSB_2D_COPYORDER_TL2BR (0<<23)
3729+#define PSB_2D_COPYORDER_BR2TL (1<<23)
3730+#define PSB_2D_COPYORDER_TR2BL (2<<23)
3731+#define PSB_2D_COPYORDER_BL2TR (3<<23)
3732+
3733+#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF)
3734+#define PSB_2D_DSTCK_DISABLE (0x00000000)
3735+#define PSB_2D_DSTCK_PASS (0x00200000)
3736+#define PSB_2D_DSTCK_REJECT (0x00400000)
3737+
3738+#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF)
3739+#define PSB_2D_SRCCK_DISABLE (0x00000000)
3740+#define PSB_2D_SRCCK_PASS (0x00080000)
3741+#define PSB_2D_SRCCK_REJECT (0x00100000)
3742+
3743+#define PSB_2D_CLIP_ENABLE (0x00040000)
3744+
3745+#define PSB_2D_ALPHA_ENABLE (0x00020000)
3746+
3747+#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF)
3748+#define PSB_2D_PAT_MASK (0x00010000)
3749+#define PSB_2D_USE_PAT (0x00010000)
3750+#define PSB_2D_USE_FILL (0x00000000)
3751+/*
3752+ * Tungsten Graphics note on rop codes: If rop A and rop B are
3753+ * identical, the mask surface will not be read and need not be
3754+ * set up.
3755+ */
3756+
3757+#define PSB_2D_ROP3B_MASK (0x0000FF00)
3758+#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF)
3759+#define PSB_2D_ROP3B_SHIFT (8)
3760+// rop code A
3761+#define PSB_2D_ROP3A_MASK (0x000000FF)
3762+#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00)
3763+#define PSB_2D_ROP3A_SHIFT (0)
3764+
3765+#define PSB_2D_ROP4_MASK (0x0000FFFF)
3766+/*
3767+ * DWORD0: (Only pass if Pattern control == Use Fill Colour)
3768+ * Fill Colour RGBA8888
3769+ */
3770+#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF)
3771+#define PSB_2D_FILLCOLOUR_SHIFT (0)
3772+/*
3773+ * DWORD1: (Always Present)
3774+ * X Start (Dest)
3775+ * Y Start (Dest)
3776+ */
3777+#define PSB_2D_DST_XSTART_MASK (0x00FFF000)
3778+#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF)
3779+#define PSB_2D_DST_XSTART_SHIFT (12)
3780+#define PSB_2D_DST_YSTART_MASK (0x00000FFF)
3781+#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000)
3782+#define PSB_2D_DST_YSTART_SHIFT (0)
3783+/*
3784+ * DWORD2: (Always Present)
3785+ * X Size (Dest)
3786+ * Y Size (Dest)
3787+ */
3788+#define PSB_2D_DST_XSIZE_MASK (0x00FFF000)
3789+#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF)
3790+#define PSB_2D_DST_XSIZE_SHIFT (12)
3791+#define PSB_2D_DST_YSIZE_MASK (0x00000FFF)
3792+#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000)
3793+#define PSB_2D_DST_YSIZE_SHIFT (0)
3794+
3795+/*
3796+ * Source Surface (PSB_2D_SRC_SURF_BH)
3797+ */
3798+/*
3799+ * WORD 0
3800+ */
3801+
3802+#define PSB_2D_SRC_FORMAT_MASK (0x00078000)
3803+#define PSB_2D_SRC_1_PAL (0x00000000)
3804+#define PSB_2D_SRC_2_PAL (0x00008000)
3805+#define PSB_2D_SRC_4_PAL (0x00010000)
3806+#define PSB_2D_SRC_8_PAL (0x00018000)
3807+#define PSB_2D_SRC_8_ALPHA (0x00020000)
3808+#define PSB_2D_SRC_4_ALPHA (0x00028000)
3809+#define PSB_2D_SRC_332RGB (0x00030000)
3810+#define PSB_2D_SRC_4444ARGB (0x00038000)
3811+#define PSB_2D_SRC_555RGB (0x00040000)
3812+#define PSB_2D_SRC_1555ARGB (0x00048000)
3813+#define PSB_2D_SRC_565RGB (0x00050000)
3814+#define PSB_2D_SRC_0888ARGB (0x00058000)
3815+#define PSB_2D_SRC_8888ARGB (0x00060000)
3816+#define PSB_2D_SRC_8888UYVY (0x00068000)
3817+#define PSB_2D_SRC_RESERVED (0x00070000)
3818+#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000)
3819+
3820+
3821+#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF)
3822+#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000)
3823+#define PSB_2D_SRC_STRIDE_SHIFT (0)
3824+/*
3825+ * WORD 1 - Base Address
3826+ */
3827+#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC)
3828+#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003)
3829+#define PSB_2D_SRC_ADDR_SHIFT (2)
3830+#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2)
3831+
3832+/*
3833+ * Pattern Surface (PSB_2D_PAT_SURF_BH)
3834+ */
3835+/*
3836+ * WORD 0
3837+ */
3838+
3839+#define PSB_2D_PAT_FORMAT_MASK (0x00078000)
3840+#define PSB_2D_PAT_1_PAL (0x00000000)
3841+#define PSB_2D_PAT_2_PAL (0x00008000)
3842+#define PSB_2D_PAT_4_PAL (0x00010000)
3843+#define PSB_2D_PAT_8_PAL (0x00018000)
3844+#define PSB_2D_PAT_8_ALPHA (0x00020000)
3845+#define PSB_2D_PAT_4_ALPHA (0x00028000)
3846+#define PSB_2D_PAT_332RGB (0x00030000)
3847+#define PSB_2D_PAT_4444ARGB (0x00038000)
3848+#define PSB_2D_PAT_555RGB (0x00040000)
3849+#define PSB_2D_PAT_1555ARGB (0x00048000)
3850+#define PSB_2D_PAT_565RGB (0x00050000)
3851+#define PSB_2D_PAT_0888ARGB (0x00058000)
3852+#define PSB_2D_PAT_8888ARGB (0x00060000)
3853+
3854+#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF)
3855+#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000)
3856+#define PSB_2D_PAT_STRIDE_SHIFT (0)
3857+/*
3858+ * WORD 1 - Base Address
3859+ */
3860+#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC)
3861+#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003)
3862+#define PSB_2D_PAT_ADDR_SHIFT (2)
3863+#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2)
3864+
3865+/*
3866+ * Destination Surface (PSB_2D_DST_SURF_BH)
3867+ */
3868+/*
3869+ * WORD 0
3870+ */
3871+
3872+#define PSB_2D_DST_FORMAT_MASK (0x00078000)
3873+#define PSB_2D_DST_332RGB (0x00030000)
3874+#define PSB_2D_DST_4444ARGB (0x00038000)
3875+#define PSB_2D_DST_555RGB (0x00040000)
3876+#define PSB_2D_DST_1555ARGB (0x00048000)
3877+#define PSB_2D_DST_565RGB (0x00050000)
3878+#define PSB_2D_DST_0888ARGB (0x00058000)
3879+#define PSB_2D_DST_8888ARGB (0x00060000)
3880+#define PSB_2D_DST_8888AYUV (0x00070000)
3881+
3882+#define PSB_2D_DST_STRIDE_MASK (0x00007FFF)
3883+#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000)
3884+#define PSB_2D_DST_STRIDE_SHIFT (0)
3885+/*
3886+ * WORD 1 - Base Address
3887+ */
3888+#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC)
3889+#define PSB_2D_DST_ADDR_CLRMASK (0x00000003)
3890+#define PSB_2D_DST_ADDR_SHIFT (2)
3891+#define PSB_2D_DST_ADDR_ALIGNSHIFT (2)
3892+
3893+/*
3894+ * Mask Surface (PSB_2D_MASK_SURF_BH)
3895+ */
3896+/*
3897+ * WORD 0
3898+ */
3899+#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF)
3900+#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000)
3901+#define PSB_2D_MASK_STRIDE_SHIFT (0)
3902+/*
3903+ * WORD 1 - Base Address
3904+ */
3905+#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC)
3906+#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003)
3907+#define PSB_2D_MASK_ADDR_SHIFT (2)
3908+#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2)
3909+
3910+/*
3911+ * Source Palette (PSB_2D_SRC_PAL_BH)
3912+ */
3913+
3914+#define PSB_2D_SRCPAL_ADDR_SHIFT (0)
3915+#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007)
3916+#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8)
3917+#define PSB_2D_SRCPAL_BYTEALIGN (1024)
3918+
3919+/*
3920+ * Pattern Palette (PSB_2D_PAT_PAL_BH)
3921+ */
3922+
3923+#define PSB_2D_PATPAL_ADDR_SHIFT (0)
3924+#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007)
3925+#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8)
3926+#define PSB_2D_PATPAL_BYTEALIGN (1024)
3927+
3928+/*
3929+ * Rop3 Codes (2 LS bytes)
3930+ */
3931+
3932+#define PSB_2D_ROP3_SRCCOPY (0xCCCC)
3933+#define PSB_2D_ROP3_PATCOPY (0xF0F0)
3934+#define PSB_2D_ROP3_WHITENESS (0xFFFF)
3935+#define PSB_2D_ROP3_BLACKNESS (0x0000)
3936+#define PSB_2D_ROP3_SRC (0xCC)
3937+#define PSB_2D_ROP3_PAT (0xF0)
3938+#define PSB_2D_ROP3_DST (0xAA)
3939+
3940+
3941+/*
3942+ * Sizes.
3943+ */
3944+
3945+#define PSB_SCENE_HW_COOKIE_SIZE 16
3946+#define PSB_TA_MEM_HW_COOKIE_SIZE 16
3947+
3948+/*
3949+ * Scene stuff.
3950+ */
3951+
3952+#define PSB_NUM_HW_SCENES 2
3953+
3954+/*
3955+ * Scheduler completion actions.
3956+ */
3957+
3958+#define PSB_RASTER_BLOCK 0
3959+#define PSB_RASTER 1
3960+#define PSB_RETURN 2
3961+#define PSB_TA 3
3962+
3963+
3964+#endif
3965Index: libdrm-2.3.1/shared-core/radeon_drm.h
3966===================================================================
3967--- libdrm-2.3.1.orig/shared-core/radeon_drm.h 2008-07-01 08:50:43.000000000 +0100
3968+++ libdrm-2.3.1/shared-core/radeon_drm.h 2009-01-14 18:26:59.000000000 +0000
3969@@ -453,8 +453,17 @@
3970 int pfCurrentPage; /* which buffer is being displayed? */
3971 int crtc2_base; /* CRTC2 frame offset */
3972 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
3973+
3974+ unsigned int last_fence;
3975 } drm_radeon_sarea_t;
3976
3977+/* The only fence class we support */
3978+#define DRM_RADEON_FENCE_CLASS_ACCEL 0
3979+/* Fence type that guarantees read-write flush */
3980+#define DRM_RADEON_FENCE_TYPE_RW 2
3981+/* cache flushes programmed just before the fence */
3982+#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000
3983+
3984 /* WARNING: If you change any of these defines, make sure to change the
3985 * defines in the Xserver file (xf86drmRadeon.h)
3986 *
3987Index: libdrm-2.3.1/shared-core/tdfx_drv.h
3988===================================================================
3989--- /dev/null 1970-01-01 00:00:00.000000000 +0000
3990+++ libdrm-2.3.1/shared-core/tdfx_drv.h 2009-01-14 18:26:59.000000000 +0000
3991@@ -0,0 +1,47 @@
3992+/* tdfx.h -- 3dfx DRM template customization -*- linux-c -*-
3993+ * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
3994+ */
3995+/*
3996+ * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3997+ * All Rights Reserved.
3998+ *
3999+ * Permission is hereby granted, free of charge, to any person obtaining a
4000+ * copy of this software and associated documentation files (the "Software"),
4001+ * to deal in the Software without restriction, including without limitation
4002+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
4003+ * and/or sell copies of the Software, and to permit persons to whom the
4004+ * Software is furnished to do so, subject to the following conditions:
4005+ *
4006+ * The above copyright notice and this permission notice (including the next
4007+ * paragraph) shall be included in all copies or substantial portions of the
4008+ * Software.
4009+ *
4010+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
4011+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
4012+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
4013+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
4014+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
4015+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4016+ * OTHER DEALINGS IN THE SOFTWARE.
4017+ *
4018+ * Authors:
4019+ * Gareth Hughes <gareth@valinux.com>
4020+ */
4021+
4022+#ifndef __TDFX_H__
4023+#define __TDFX_H__
4024+
4025+/* General customization:
4026+ */
4027+
4028+#define DRIVER_AUTHOR "VA Linux Systems Inc."
4029+
4030+#define DRIVER_NAME "tdfx"
4031+#define DRIVER_DESC "3dfx Banshee/Voodoo3+"
4032+#define DRIVER_DATE "20010216"
4033+
4034+#define DRIVER_MAJOR 1
4035+#define DRIVER_MINOR 0
4036+#define DRIVER_PATCHLEVEL 0
4037+
4038+#endif
4039Index: libdrm-2.3.1/shared-core/via_3d_reg.h
4040===================================================================
4041--- libdrm-2.3.1.orig/shared-core/via_3d_reg.h 2008-07-01 08:50:43.000000000 +0100
4042+++ libdrm-2.3.1/shared-core/via_3d_reg.h 2009-01-14 18:26:59.000000000 +0000
4043@@ -1643,6 +1643,7 @@
4044 #define HC_HAGPBpID_STOP 0x00000002
4045 #define HC_HAGPBpH_MASK 0x00ffffff
4046
4047+
4048 #define VIA_VIDEO_HEADER5 0xFE040000
4049 #define VIA_VIDEO_HEADER6 0xFE050000
4050 #define VIA_VIDEO_HEADER7 0xFE060000
diff --git a/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb b/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb
deleted file mode 100644
index 60e10d91f2..0000000000
--- a/meta-moblin/packages/drm/libdrm-psb_2.3.1.bb
+++ /dev/null
@@ -1,17 +0,0 @@
1SECTION = "x11/base"
2LICENSE = "MIT"
3SRC_URI = "http://dri.freedesktop.org/libdrm/libdrm-${PV}.tar.bz2 \
4 file://poulsbo.patch;patch=1"
5PROVIDES = "drm libdrm"
6
7S = ${WORKDIR}/libdrm-${PV}
8
9DEPENDS = "libpthread-stubs"
10
11PR = "r7"
12
13COMPATIBLE_MACHINE = "menlow"
14
15LEAD_SONAME = "libdrm.so"
16
17inherit autotools_stage pkgconfig
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-16 11:47:22 +0000