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authorAlistair Francis <alistair.francis@wdc.com>2019-05-24 10:08:17 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2019-05-27 17:06:34 +0100
commit274f038d3eeced911d711e3bcacabab3408ac8fe (patch)
tree58b6af47b3176ce22041dc628fe01c923fbf9f0d
parent12aa79f5bf16bd6d3fa3ef7a13650289e7f15da4 (diff)
downloadpoky-274f038d3eeced911d711e3bcacabab3408ac8fe.tar.gz
qemu: Backport the arm segfault fix
When we updated to QEMU 4.0 we saw a segfault when running tests on the qemuarm machine. At the time we just reverted the offending patch from QEMU. Now that the fix has been merged into upstream let's remove that revert patch and replace it with the correct backport. (From OE-Core rev: ce0cae5511ce4ba7b9dcc9c6676ec7ea10622cb7) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat
-rw-r--r--meta/recipes-devtools/qemu/qemu.inc2
-rw-r--r--meta/recipes-devtools/qemu/qemu/0013-Revert-target-arm-Use-vector-operations-for-saturati.patch493
-rw-r--r--meta/recipes-devtools/qemu/qemu/0013-target-arm-Fix-vector-operation-segfault.patch66
3 files changed, 67 insertions, 494 deletions
diff --git a/meta/recipes-devtools/qemu/qemu.inc b/meta/recipes-devtools/qemu/qemu.inc
index f7b41412ad..e44e351129 100644
--- a/meta/recipes-devtools/qemu/qemu.inc
+++ b/meta/recipes-devtools/qemu/qemu.inc
@@ -20,7 +20,7 @@ SRC_URI = "https://download.qemu.org/${BPN}-${PV}.tar.xz \
20 file://0008-apic-fixup-fallthrough-to-PIC.patch \ 20 file://0008-apic-fixup-fallthrough-to-PIC.patch \
21 file://0009-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch \ 21 file://0009-linux-user-Fix-webkitgtk-hangs-on-32-bit-x86-target.patch \
22 file://0010-Revert-linux-user-fix-mmap-munmap-mprotect-mremap-sh.patch \ 22 file://0010-Revert-linux-user-fix-mmap-munmap-mprotect-mremap-sh.patch \
23 file://0013-Revert-target-arm-Use-vector-operations-for-saturati.patch \ 23 file://0013-target-arm-Fix-vector-operation-segfault.patch \
24 " 24 "
25UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar" 25UPSTREAM_CHECK_REGEX = "qemu-(?P<pver>\d+(\.\d+)+)\.tar"
26 26
diff --git a/meta/recipes-devtools/qemu/qemu/0013-Revert-target-arm-Use-vector-operations-for-saturati.patch b/meta/recipes-devtools/qemu/qemu/0013-Revert-target-arm-Use-vector-operations-for-saturati.patch
deleted file mode 100644
index 3d018a74d9..0000000000
--- a/meta/recipes-devtools/qemu/qemu/0013-Revert-target-arm-Use-vector-operations-for-saturati.patch
+++ /dev/null
@@ -1,493 +0,0 @@
1From b46cdcdeb762c1f0eef68dc4a7d90f8176152e07 Mon Sep 17 00:00:00 2001
2From: Alistair Francis <alistair.francis@wdc.com>
3Date: Wed, 1 May 2019 19:51:27 -0700
4Subject: [PATCH] Revert "target/arm: Use vector operations for saturation"
5
6This reverts commit 89e68b575e138d0af1435f11a8ffcd8779c237bd.
7
8This fixes QEMU aborts when running the qemuarm machine.
9
10Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11Upstream-Status: Pending
12---
13 target/arm/helper.h | 33 -------
14 target/arm/translate-a64.c | 36 ++++----
15 target/arm/translate.c | 172 ++++++-------------------------------
16 target/arm/translate.h | 4 -
17 target/arm/vec_helper.c | 130 ----------------------------
18 5 files changed, 44 insertions(+), 331 deletions(-)
19
20diff --git a/target/arm/helper.h b/target/arm/helper.h
21index 50cb036378..b2669f140f 100644
22--- a/target/arm/helper.h
23+++ b/target/arm/helper.h
24@@ -646,39 +646,6 @@ DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,
25 DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG,
26 void, ptr, ptr, ptr, ptr, ptr, i32)
27
28-DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG,
29- void, ptr, ptr, ptr, ptr, i32)
30-DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG,
31- void, ptr, ptr, ptr, ptr, i32)
32-DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG,
33- void, ptr, ptr, ptr, ptr, i32)
34-DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG,
35- void, ptr, ptr, ptr, ptr, i32)
36-DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG,
37- void, ptr, ptr, ptr, ptr, i32)
38-DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG,
39- void, ptr, ptr, ptr, ptr, i32)
40-DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG,
41- void, ptr, ptr, ptr, ptr, i32)
42-DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG,
43- void, ptr, ptr, ptr, ptr, i32)
44-DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG,
45- void, ptr, ptr, ptr, ptr, i32)
46-DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG,
47- void, ptr, ptr, ptr, ptr, i32)
48-DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG,
49- void, ptr, ptr, ptr, ptr, i32)
50-DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG,
51- void, ptr, ptr, ptr, ptr, i32)
52-DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG,
53- void, ptr, ptr, ptr, ptr, i32)
54-DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG,
55- void, ptr, ptr, ptr, ptr, i32)
56-DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
57- void, ptr, ptr, ptr, ptr, i32)
58-DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
59- void, ptr, ptr, ptr, ptr, i32)
60-
61 DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
62 void, ptr, ptr, ptr, ptr, i32)
63 DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
64diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
65index 9dcc5ff3a3..428211f92f 100644
66--- a/target/arm/translate-a64.c
67+++ b/target/arm/translate-a64.c
68@@ -11230,22 +11230,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
69 }
70
71 switch (opcode) {
72- case 0x01: /* SQADD, UQADD */
73- tcg_gen_gvec_4(vec_full_reg_offset(s, rd),
74- offsetof(CPUARMState, vfp.qc),
75- vec_full_reg_offset(s, rn),
76- vec_full_reg_offset(s, rm),
77- is_q ? 16 : 8, vec_full_reg_size(s),
78- (u ? uqadd_op : sqadd_op) + size);
79- return;
80- case 0x05: /* SQSUB, UQSUB */
81- tcg_gen_gvec_4(vec_full_reg_offset(s, rd),
82- offsetof(CPUARMState, vfp.qc),
83- vec_full_reg_offset(s, rn),
84- vec_full_reg_offset(s, rm),
85- is_q ? 16 : 8, vec_full_reg_size(s),
86- (u ? uqsub_op : sqsub_op) + size);
87- return;
88 case 0x0c: /* SMAX, UMAX */
89 if (u) {
90 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
91@@ -11341,6 +11325,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
92 genfn = fns[size][u];
93 break;
94 }
95+ case 0x1: /* SQADD, UQADD */
96+ {
97+ static NeonGenTwoOpEnvFn * const fns[3][2] = {
98+ { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
99+ { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
100+ { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
101+ };
102+ genenvfn = fns[size][u];
103+ break;
104+ }
105 case 0x2: /* SRHADD, URHADD */
106 {
107 static NeonGenTwoOpFn * const fns[3][2] = {
108@@ -11361,6 +11355,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
109 genfn = fns[size][u];
110 break;
111 }
112+ case 0x5: /* SQSUB, UQSUB */
113+ {
114+ static NeonGenTwoOpEnvFn * const fns[3][2] = {
115+ { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
116+ { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
117+ { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
118+ };
119+ genenvfn = fns[size][u];
120+ break;
121+ }
122 case 0x8: /* SSHL, USHL */
123 {
124 static NeonGenTwoOpFn * const fns[3][2] = {
125diff --git a/target/arm/translate.c b/target/arm/translate.c
126index 10bc53f91c..cf675cef3f 100644
127--- a/target/arm/translate.c
128+++ b/target/arm/translate.c
129@@ -6242,142 +6242,6 @@ const GVecGen3 cmtst_op[4] = {
130 .vece = MO_64 },
131 };
132
133-static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
134- TCGv_vec a, TCGv_vec b)
135-{
136- TCGv_vec x = tcg_temp_new_vec_matching(t);
137- tcg_gen_add_vec(vece, x, a, b);
138- tcg_gen_usadd_vec(vece, t, a, b);
139- tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t);
140- tcg_gen_or_vec(vece, sat, sat, x);
141- tcg_temp_free_vec(x);
142-}
143-
144-const GVecGen4 uqadd_op[4] = {
145- { .fniv = gen_uqadd_vec,
146- .fno = gen_helper_gvec_uqadd_b,
147- .opc = INDEX_op_usadd_vec,
148- .write_aofs = true,
149- .vece = MO_8 },
150- { .fniv = gen_uqadd_vec,
151- .fno = gen_helper_gvec_uqadd_h,
152- .opc = INDEX_op_usadd_vec,
153- .write_aofs = true,
154- .vece = MO_16 },
155- { .fniv = gen_uqadd_vec,
156- .fno = gen_helper_gvec_uqadd_s,
157- .opc = INDEX_op_usadd_vec,
158- .write_aofs = true,
159- .vece = MO_32 },
160- { .fniv = gen_uqadd_vec,
161- .fno = gen_helper_gvec_uqadd_d,
162- .opc = INDEX_op_usadd_vec,
163- .write_aofs = true,
164- .vece = MO_64 },
165-};
166-
167-static void gen_sqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
168- TCGv_vec a, TCGv_vec b)
169-{
170- TCGv_vec x = tcg_temp_new_vec_matching(t);
171- tcg_gen_add_vec(vece, x, a, b);
172- tcg_gen_ssadd_vec(vece, t, a, b);
173- tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t);
174- tcg_gen_or_vec(vece, sat, sat, x);
175- tcg_temp_free_vec(x);
176-}
177-
178-const GVecGen4 sqadd_op[4] = {
179- { .fniv = gen_sqadd_vec,
180- .fno = gen_helper_gvec_sqadd_b,
181- .opc = INDEX_op_ssadd_vec,
182- .write_aofs = true,
183- .vece = MO_8 },
184- { .fniv = gen_sqadd_vec,
185- .fno = gen_helper_gvec_sqadd_h,
186- .opc = INDEX_op_ssadd_vec,
187- .write_aofs = true,
188- .vece = MO_16 },
189- { .fniv = gen_sqadd_vec,
190- .fno = gen_helper_gvec_sqadd_s,
191- .opc = INDEX_op_ssadd_vec,
192- .write_aofs = true,
193- .vece = MO_32 },
194- { .fniv = gen_sqadd_vec,
195- .fno = gen_helper_gvec_sqadd_d,
196- .opc = INDEX_op_ssadd_vec,
197- .write_aofs = true,
198- .vece = MO_64 },
199-};
200-
201-static void gen_uqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
202- TCGv_vec a, TCGv_vec b)
203-{
204- TCGv_vec x = tcg_temp_new_vec_matching(t);
205- tcg_gen_sub_vec(vece, x, a, b);
206- tcg_gen_ussub_vec(vece, t, a, b);
207- tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t);
208- tcg_gen_or_vec(vece, sat, sat, x);
209- tcg_temp_free_vec(x);
210-}
211-
212-const GVecGen4 uqsub_op[4] = {
213- { .fniv = gen_uqsub_vec,
214- .fno = gen_helper_gvec_uqsub_b,
215- .opc = INDEX_op_ussub_vec,
216- .write_aofs = true,
217- .vece = MO_8 },
218- { .fniv = gen_uqsub_vec,
219- .fno = gen_helper_gvec_uqsub_h,
220- .opc = INDEX_op_ussub_vec,
221- .write_aofs = true,
222- .vece = MO_16 },
223- { .fniv = gen_uqsub_vec,
224- .fno = gen_helper_gvec_uqsub_s,
225- .opc = INDEX_op_ussub_vec,
226- .write_aofs = true,
227- .vece = MO_32 },
228- { .fniv = gen_uqsub_vec,
229- .fno = gen_helper_gvec_uqsub_d,
230- .opc = INDEX_op_ussub_vec,
231- .write_aofs = true,
232- .vece = MO_64 },
233-};
234-
235-static void gen_sqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
236- TCGv_vec a, TCGv_vec b)
237-{
238- TCGv_vec x = tcg_temp_new_vec_matching(t);
239- tcg_gen_sub_vec(vece, x, a, b);
240- tcg_gen_sssub_vec(vece, t, a, b);
241- tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t);
242- tcg_gen_or_vec(vece, sat, sat, x);
243- tcg_temp_free_vec(x);
244-}
245-
246-const GVecGen4 sqsub_op[4] = {
247- { .fniv = gen_sqsub_vec,
248- .fno = gen_helper_gvec_sqsub_b,
249- .opc = INDEX_op_sssub_vec,
250- .write_aofs = true,
251- .vece = MO_8 },
252- { .fniv = gen_sqsub_vec,
253- .fno = gen_helper_gvec_sqsub_h,
254- .opc = INDEX_op_sssub_vec,
255- .write_aofs = true,
256- .vece = MO_16 },
257- { .fniv = gen_sqsub_vec,
258- .fno = gen_helper_gvec_sqsub_s,
259- .opc = INDEX_op_sssub_vec,
260- .write_aofs = true,
261- .vece = MO_32 },
262- { .fniv = gen_sqsub_vec,
263- .fno = gen_helper_gvec_sqsub_d,
264- .opc = INDEX_op_sssub_vec,
265- .write_aofs = true,
266- .vece = MO_64 },
267-};
268-
269 /* Translate a NEON data processing instruction. Return nonzero if the
270 instruction is invalid.
271 We process data in a mixture of 32-bit and 64-bit chunks.
272@@ -6561,18 +6425,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
273 }
274 return 0;
275
276- case NEON_3R_VQADD:
277- tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
278- rn_ofs, rm_ofs, vec_size, vec_size,
279- (u ? uqadd_op : sqadd_op) + size);
280- break;
281-
282- case NEON_3R_VQSUB:
283- tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
284- rn_ofs, rm_ofs, vec_size, vec_size,
285- (u ? uqsub_op : sqsub_op) + size);
286- break;
287-
288 case NEON_3R_VMUL: /* VMUL */
289 if (u) {
290 /* Polynomial case allows only P8 and is handled below. */
291@@ -6637,6 +6489,24 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
292 neon_load_reg64(cpu_V0, rn + pass);
293 neon_load_reg64(cpu_V1, rm + pass);
294 switch (op) {
295+ case NEON_3R_VQADD:
296+ if (u) {
297+ gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
298+ cpu_V0, cpu_V1);
299+ } else {
300+ gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
301+ cpu_V0, cpu_V1);
302+ }
303+ break;
304+ case NEON_3R_VQSUB:
305+ if (u) {
306+ gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
307+ cpu_V0, cpu_V1);
308+ } else {
309+ gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
310+ cpu_V0, cpu_V1);
311+ }
312+ break;
313 case NEON_3R_VSHL:
314 if (u) {
315 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
316@@ -6752,12 +6622,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
317 case NEON_3R_VHADD:
318 GEN_NEON_INTEGER_OP(hadd);
319 break;
320+ case NEON_3R_VQADD:
321+ GEN_NEON_INTEGER_OP_ENV(qadd);
322+ break;
323 case NEON_3R_VRHADD:
324 GEN_NEON_INTEGER_OP(rhadd);
325 break;
326 case NEON_3R_VHSUB:
327 GEN_NEON_INTEGER_OP(hsub);
328 break;
329+ case NEON_3R_VQSUB:
330+ GEN_NEON_INTEGER_OP_ENV(qsub);
331+ break;
332 case NEON_3R_VSHL:
333 GEN_NEON_INTEGER_OP(shl);
334 break;
335diff --git a/target/arm/translate.h b/target/arm/translate.h
336index c2348def0d..07055c9449 100644
337--- a/target/arm/translate.h
338+++ b/target/arm/translate.h
339@@ -248,10 +248,6 @@ extern const GVecGen2i ssra_op[4];
340 extern const GVecGen2i usra_op[4];
341 extern const GVecGen2i sri_op[4];
342 extern const GVecGen2i sli_op[4];
343-extern const GVecGen4 uqadd_op[4];
344-extern const GVecGen4 sqadd_op[4];
345-extern const GVecGen4 uqsub_op[4];
346-extern const GVecGen4 sqsub_op[4];
347 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
348
349 /*
350diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
351index dedef62403..be3271659f 100644
352--- a/target/arm/vec_helper.c
353+++ b/target/arm/vec_helper.c
354@@ -769,136 +769,6 @@ DO_FMLA_IDX(gvec_fmla_idx_d, float64, )
355
356 #undef DO_FMLA_IDX
357
358-#define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \
359-void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \
360-{ \
361- intptr_t i, oprsz = simd_oprsz(desc); \
362- TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
363- bool q = false; \
364- for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \
365- WTYPE dd = (WTYPE)n[i] OP m[i]; \
366- if (dd < MIN) { \
367- dd = MIN; \
368- q = true; \
369- } else if (dd > MAX) { \
370- dd = MAX; \
371- q = true; \
372- } \
373- d[i] = dd; \
374- } \
375- if (q) { \
376- uint32_t *qc = vq; \
377- qc[0] = 1; \
378- } \
379- clear_tail(d, oprsz, simd_maxsz(desc)); \
380-}
381-
382-DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX)
383-DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX)
384-DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX)
385-
386-DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX)
387-DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX)
388-DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX)
389-
390-DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX)
391-DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX)
392-DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX)
393-
394-DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX)
395-DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX)
396-DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX)
397-
398-#undef DO_SAT
399-
400-void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn,
401- void *vm, uint32_t desc)
402-{
403- intptr_t i, oprsz = simd_oprsz(desc);
404- uint64_t *d = vd, *n = vn, *m = vm;
405- bool q = false;
406-
407- for (i = 0; i < oprsz / 8; i++) {
408- uint64_t nn = n[i], mm = m[i], dd = nn + mm;
409- if (dd < nn) {
410- dd = UINT64_MAX;
411- q = true;
412- }
413- d[i] = dd;
414- }
415- if (q) {
416- uint32_t *qc = vq;
417- qc[0] = 1;
418- }
419- clear_tail(d, oprsz, simd_maxsz(desc));
420-}
421-
422-void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn,
423- void *vm, uint32_t desc)
424-{
425- intptr_t i, oprsz = simd_oprsz(desc);
426- uint64_t *d = vd, *n = vn, *m = vm;
427- bool q = false;
428-
429- for (i = 0; i < oprsz / 8; i++) {
430- uint64_t nn = n[i], mm = m[i], dd = nn - mm;
431- if (nn < mm) {
432- dd = 0;
433- q = true;
434- }
435- d[i] = dd;
436- }
437- if (q) {
438- uint32_t *qc = vq;
439- qc[0] = 1;
440- }
441- clear_tail(d, oprsz, simd_maxsz(desc));
442-}
443-
444-void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn,
445- void *vm, uint32_t desc)
446-{
447- intptr_t i, oprsz = simd_oprsz(desc);
448- int64_t *d = vd, *n = vn, *m = vm;
449- bool q = false;
450-
451- for (i = 0; i < oprsz / 8; i++) {
452- int64_t nn = n[i], mm = m[i], dd = nn + mm;
453- if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) {
454- dd = (nn >> 63) ^ ~INT64_MIN;
455- q = true;
456- }
457- d[i] = dd;
458- }
459- if (q) {
460- uint32_t *qc = vq;
461- qc[0] = 1;
462- }
463- clear_tail(d, oprsz, simd_maxsz(desc));
464-}
465-
466-void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
467- void *vm, uint32_t desc)
468-{
469- intptr_t i, oprsz = simd_oprsz(desc);
470- int64_t *d = vd, *n = vn, *m = vm;
471- bool q = false;
472-
473- for (i = 0; i < oprsz / 8; i++) {
474- int64_t nn = n[i], mm = m[i], dd = nn - mm;
475- if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) {
476- dd = (nn >> 63) ^ ~INT64_MIN;
477- q = true;
478- }
479- d[i] = dd;
480- }
481- if (q) {
482- uint32_t *qc = vq;
483- qc[0] = 1;
484- }
485- clear_tail(d, oprsz, simd_maxsz(desc));
486-}
487-
488 /*
489 * Convert float16 to float32, raising no exceptions and
490 * preserving exceptional values, including SNaN.
491--
4922.21.0
493
diff --git a/meta/recipes-devtools/qemu/qemu/0013-target-arm-Fix-vector-operation-segfault.patch b/meta/recipes-devtools/qemu/qemu/0013-target-arm-Fix-vector-operation-segfault.patch
new file mode 100644
index 0000000000..c1dd957dc9
--- /dev/null
+++ b/meta/recipes-devtools/qemu/qemu/0013-target-arm-Fix-vector-operation-segfault.patch
@@ -0,0 +1,66 @@
1From 2f143d3ad1c05e91cf2cdf5de06d59a80a95e6c8 Mon Sep 17 00:00:00 2001
2From: Alistair Francis <alistair.francis@wdc.com>
3Date: Thu, 23 May 2019 14:47:43 +0100
4Subject: [PATCH] target/arm: Fix vector operation segfault
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Commit 89e68b575 "target/arm: Use vector operations for saturation"
10causes this abort() when booting QEMU ARM with a Cortex-A15:
11
120 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
131 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
142 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
153 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
164 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
175 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
186 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
197 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
208 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
219 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
2210 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
2311 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
2412 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
2513 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
2614 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
2715 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
28
29This patch ensures that we don't hit the abort() in the second switch
30case in disas_neon_data_insn() as we will return from the first case.
31
32Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
33Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
35Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
36Tested-by: Alex Bennée <alex.bennee@linaro.org>
37Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
38Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39Upstream-Status: Backport [4.1.0]
40---
41 target/arm/translate.c | 4 ++--
42 1 file changed, 2 insertions(+), 2 deletions(-)
43
44diff --git a/target/arm/translate.c b/target/arm/translate.c
45index dd053c80d6..298c262825 100644
46--- a/target/arm/translate.c
47+++ b/target/arm/translate.c
48@@ -6598,13 +6598,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
49 tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
50 rn_ofs, rm_ofs, vec_size, vec_size,
51 (u ? uqadd_op : sqadd_op) + size);
52- break;
53+ return 0;
54
55 case NEON_3R_VQSUB:
56 tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
57 rn_ofs, rm_ofs, vec_size, vec_size,
58 (u ? uqsub_op : sqsub_op) + size);
59- break;
60+ return 0;
61
62 case NEON_3R_VMUL: /* VMUL */
63 if (u) {
64--
652.21.0
66
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-12 06:48:26 +0000