diff options
author | Mark Hatle <mark.hatle@windriver.com> | 2015-10-20 10:54:33 -0500 |
---|---|---|
committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2015-12-08 10:27:14 +0000 |
commit | 1401976a024a56e733d1498c8d25b560af4c4c18 (patch) | |
tree | 5d616f44f62a999c1ae24fc2a13fb1e140f82eb4 | |
parent | a54a0dba100503b8bc0f80e5d03ca11c6e53a258 (diff) | |
download | poky-1401976a024a56e733d1498c8d25b560af4c4c18.tar.gz |
binutils: Fix octeon3 disassembly patch
The structure has apparently changed, and there was a missing
setting. This corrects a segfault when disassembling code.
(From OE-Core master rev: 2e8f1ffe3a8d7740b0ac68eefbba3fe28f7ba6d4)
(From OE-Core rev: 6a6f5446303a9b0b858d153137244a5a101520ce)
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch b/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch index 6108c0d5cb..4e8c69f3ed 100644 --- a/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch +++ b/meta/recipes-devtools/binutils/binutils/binutils-octeon3.patch | |||
@@ -229,7 +229,7 @@ Index: git/opcodes/mips-dis.c | |||
229 | + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, | 229 | + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, |
230 | + ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, | 230 | + ISA_MIPS64R2 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, |
231 | + mips_cp0_names_numeric, | 231 | + mips_cp0_names_numeric, |
232 | + NULL, 0, mips_hwr_names_numeric }, | 232 | + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, |
233 | + | 233 | + |
234 | { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, | 234 | { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, |
235 | ISA_MIPS64 | INSN_XLR, 0, | 235 | ISA_MIPS64 | INSN_XLR, 0, |