From 29a9511c3004d3ad8a0e9a66e6cd312677b8cc68 Mon Sep 17 00:00:00 2001 From: Mark Hatle Date: Wed, 1 Dec 2021 12:51:12 -0800 Subject: gcc: Move everything to gcc-11 directory Signed-off-by: Mark Hatle --- ...croblaze64-Add-Zero_extended-instructions.patch | 57 ---------------------- ...croblaze64-Add-Zero_extended-instructions.patch | 57 ++++++++++++++++++++++ .../recipes-devtools/gcc/gcc-source_11.%.bbappend | 2 +- 3 files changed, 58 insertions(+), 58 deletions(-) delete mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-10/0056-patch-microblaze64-Add-Zero_extended-instructions.patch create mode 100644 meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch (limited to 'meta-microblaze') diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-patch-microblaze64-Add-Zero_extended-instructions.patch deleted file mode 100644 index 949e6346..00000000 --- a/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-patch-microblaze64-Add-Zero_extended-instructions.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4096da3ea3765ec9484af719a16074789b8946ee Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala -Date: Mon, 30 Aug 2021 12:13:45 +0530 -Subject: [PATCH] [patch, microblaze64]: Add Zero_extended instructions - -Due to latest changes in GCC-10.2 MB64 perforamance has reduced -We have added zero_extended instructions to get rid of left shift -and right shift loops - -[CR/TSR]: TSR-974519 - -Signed-off-by: Nagaraju Mekala ---- - gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 71ac46dfb6c..51c2751e6be 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -1191,6 +1191,33 @@ - (set_attr "mode" "SI,SI,SI") - (set_attr "length" "4,4,8")]) - -+(define_insn "zero_extendhidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendsidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0xffffffff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ -+(define_insn "zero_extendqidi2" -+ [(set (match_operand:DI 0 "register_operand" "=d") -+ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] -+ "TARGET_MB_64" -+ "andli\t%0,%1,0x00ff" -+ [(set_attr "type" "no_delay_arith") -+ (set_attr "mode" "DI") -+ (set_attr "length" "8")]) -+ - ;;---------------------------------------------------------------- - ;; Sign extension - ;;---------------------------------------------------------------- --- -2.17.1 - diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch new file mode 100644 index 00000000..949e6346 --- /dev/null +++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch @@ -0,0 +1,57 @@ +From 4096da3ea3765ec9484af719a16074789b8946ee Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala +Date: Mon, 30 Aug 2021 12:13:45 +0530 +Subject: [PATCH] [patch, microblaze64]: Add Zero_extended instructions + +Due to latest changes in GCC-10.2 MB64 perforamance has reduced +We have added zero_extended instructions to get rid of left shift +and right shift loops + +[CR/TSR]: TSR-974519 + +Signed-off-by: Nagaraju Mekala +--- + gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 71ac46dfb6c..51c2751e6be 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1191,6 +1191,33 @@ + (set_attr "mode" "SI,SI,SI") + (set_attr "length" "4,4,8")]) + ++(define_insn "zero_extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendsidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0xffffffff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ ++(define_insn "zero_extendqidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "andli\t%0,%1,0x00ff" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8")]) ++ + ;;---------------------------------------------------------------- + ;; Sign extension + ;;---------------------------------------------------------------- +-- +2.17.1 + diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend index c0ad2e66..e7d453a4 100644 --- a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend +++ b/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend @@ -1,5 +1,5 @@ # Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/gcc-10" +FILESEXTRAPATHS:append:microblaze := ":${THISDIR}/gcc-11" SRC_URI:append:microblaze = " \ file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ -- cgit v1.2.3-54-g00ecf